Add minimize memory to PE connection resource algorithm

• Added min_mem_to_pe resource allocation/assignment algorithm.
• Fixed bug where two PEs/memories with the same name broke the architecture rendering by enforcing unique names.
• Fixed comments from !507 (merged)

Closes: #347 (closed)

b_asic/architecture.py

@@ -615,13 +615,29 @@ of :class:`~b_asic.architecture.ProcessingElement`
         direct_interconnects: ProcessCollection | None = None,
     ):
         super().__init__(entity_name)
+
+        pe_names = [pe._entity_name for pe in processing_elements]
+        if None in pe_names:
+            raise ValueError(
+                "Entity names must be defined for all processing elements."
+            )
+        if len(pe_names) != len(set(pe_names)):
+            raise ValueError("Entity names of processing elements needs to be unique.")
         self._processing_elements = (
             [processing_elements]
             if isinstance(processing_elements, ProcessingElement)
             else list(processing_elements)
         )
+
+        mem_names = [mem._entity_name for mem in memories]
+        if None in mem_names:
+            raise ValueError("Entity names must be defined for all memories.")
+        if len(mem_names) != len(set(mem_names)):
+            raise ValueError("Entity names of memories needs to be unique.")
         self._memories = [memories] if isinstance(memories, Memory) else list(memories)
+
         self._direct_interconnects = direct_interconnects
+
         self._variable_input_port_to_resource: defaultdict[
             InputPort, set[tuple[Resource, int]]
         ] = defaultdict(set)