WIP: codegen: add B-ASIC commit hash in VHDL preamble
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@@ -4,6 +4,7 @@ Generation of common VHDL constructs
@@ -4,6 +4,7 @@ Generation of common VHDL constructs
@@ -18,9 +19,18 @@ def write_b_asic_vhdl_preamble(f: TextIOWrapper):
@@ -18,9 +19,18 @@ def write_b_asic_vhdl_preamble(f: TextIOWrapper):