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Computer Engineering
B-ASIC - Better ASIC Toolbox
Commits
f87edabd
Commit
f87edabd
authored
1 year ago
by
Oscar Gustafsson
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Fix fwl simulation
parent
244fa3a7
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!275
Fix fwl simulation
Pipeline
#93756
passed
1 year ago
Stage: test
Stage: deploy
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b_asic/operation.py
+2
-3
2 additions, 3 deletions
b_asic/operation.py
with
2 additions
and
3 deletions
b_asic/operation.py
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2
−
3
View file @
f87edabd
...
...
@@ -928,14 +928,13 @@ class AbstractOperation(Operation, AbstractGraphComponent):
)
return
self
.
input
(
0
)
# TODO: Fix
def
quantize_input
(
self
,
index
:
int
,
value
:
Num
,
bits
:
int
)
->
Num
:
if
isinstance
(
value
,
(
float
,
int
)):
return
round
(
value
)
&
((
2
**
bits
)
-
1
)
b
=
2
**
bits
return
round
((
value
+
1
)
*
b
%
(
2
*
b
)
-
b
)
/
b
else
:
raise
TypeError
# TODO: Seems wrong??? - Oscar
def
quantize_inputs
(
self
,
input_values
:
Sequence
[
Num
],
...
...
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