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Commit 70f5be89 authored by angloth's avatar angloth
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Rename find_components_with_type_name to get

parent 933f1e77
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1 merge request!29Resolve "Generate PG from SFG"
Pipeline #13954 passed
...@@ -269,7 +269,7 @@ class SFG(AbstractOperation): ...@@ -269,7 +269,7 @@ class SFG(AbstractOperation):
"""Get all operations of this graph in depth-first order.""" """Get all operations of this graph in depth-first order."""
return self._operations_ordered return self._operations_ordered
def find_components_with_type_name(self, type_name: TypeName) -> List[GraphComponent]: def get_components_with_type_name(self, type_name: TypeName) -> List[GraphComponent]:
"""Get a list with all components in this graph with the specified type_name. """Get a list with all components in this graph with the specified type_name.
Keyword arguments: Keyword arguments:
...@@ -478,7 +478,7 @@ class SFG(AbstractOperation): ...@@ -478,7 +478,7 @@ class SFG(AbstractOperation):
results[key] = value results[key] = value
return value return value
def get_precedence_list(self): def get_precedence_list(self) -> List[List[OutputPort]]:
"""Returns a Precedence list of the SFG where each element in n:th the list consists """Returns a Precedence list of the SFG where each element in n:th the list consists
of elements that are executed in the n:th step. If the precedence list already has been of elements that are executed in the n:th step. If the precedence list already has been
calculated for the current SFG then returns the cached version.""" calculated for the current SFG then returns the cached version."""
...@@ -490,7 +490,7 @@ class SFG(AbstractOperation): ...@@ -490,7 +490,7 @@ class SFG(AbstractOperation):
# Find all operations with only outputs and no inputs. # Find all operations with only outputs and no inputs.
no_input_ops = list( no_input_ops = list(
filter(lambda op: op.input_count == 0, self.operations)) filter(lambda op: op.input_count == 0, self.operations))
reg_ops = self.find_components_with_type_name(Register.type_name()) reg_ops = self.get_components_with_type_name(Register.type_name())
# Find all first iter output ports for precedence # Find all first iter output ports for precedence
curr_iter_ports = [op.output(i) for op in ( curr_iter_ports = [op.output(i) for op in (
......
...@@ -290,19 +290,19 @@ class TestFindComponentsWithTypeName: ...@@ -290,19 +290,19 @@ class TestFindComponentsWithTypeName:
print(mac_sfg._components_by_id) print(mac_sfg._components_by_id)
assert {comp.name for comp in mac_sfg.find_components_with_type_name( assert {comp.name for comp in mac_sfg.get_components_with_type_name(
inp1.type_name())} == {"INP1", "INP2", "INP3"} inp1.type_name())} == {"INP1", "INP2", "INP3"}
assert {comp.name for comp in mac_sfg.find_components_with_type_name( assert {comp.name for comp in mac_sfg.get_components_with_type_name(
add1.type_name())} == {"ADD1", "ADD2"} add1.type_name())} == {"ADD1", "ADD2"}
assert {comp.name for comp in mac_sfg.find_components_with_type_name( assert {comp.name for comp in mac_sfg.get_components_with_type_name(
mul1.type_name())} == {"MUL1"} mul1.type_name())} == {"MUL1"}
assert {comp.name for comp in mac_sfg.find_components_with_type_name( assert {comp.name for comp in mac_sfg.get_components_with_type_name(
out1.type_name())} == {"OUT1"} out1.type_name())} == {"OUT1"}
assert {comp.name for comp in mac_sfg.find_components_with_type_name( assert {comp.name for comp in mac_sfg.get_components_with_type_name(
Signal.type_name())} == {"S1", "S2", "S3", "S4", "S5", "S6", "S7"} Signal.type_name())} == {"S1", "S2", "S3", "S4", "S5", "S6", "S7"}
......
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