Started working on migration Chalmers->LiU

cadence/genus/README → cadence/21.10/README

 # st28flow
 A collection of scripts used for synthesis and place and route in Cadence 
 Genus and Innovus. The scripts use a STMicroelectronics 28nm FD-SOI cell 
-library and are designed to be run on umbriel.cse.chalmers.se. 
+library and are designed to be run on only-da.ad.liu.se
 
 ## Sofware versions
 The scripts use the following software versions.
 
-- Cadence Genus 16.22
-- Cadence Innovus 16.13
+- Cadence Genus 21.10
+- Cadence Innovus 21.10
 - Cadence Virtuoso 6.1.7
 
 ## Cloning
 The repo can be cloned on the umbriel server by executing:
-`git clone /Home/erikbor/git/st28flow.git`
+`git clone https://gitlab.liu.se/mikhe33/da-eda.git`
 
 ## Content
 The following sections describe the content of the repo.

cadence/genus/config_syn.tcl → cadence/21.10/config_syn.tcl

@@ -4,8 +4,7 @@ set PATH_LIB_BASE "/sw/cadence/libraries/CMOS28_FDSOI-2.5.d"; # Base path to cel
 # testar, LVT verkar finnas
 #set PATH_LIB_BASE "/sw/cadence/libraries/cmos28fdsoi_27a"; # Base path to cell library
 
-#set PATH_SRC_BASE "./ex";                                   # Base path to source files
-set PATH_SRC_BASE "../code/VE-LiU2";                                   # Base path to source files
+set PATH_SRC_BASE "./ex";                                   # Base path to source files
 
 # Files
 #set FILE_SOURCE_LIST "./ex/$INSTANCE_NAME/sources.txt"; # List of source files

cadence/21.10/ex/pe.vhdl

+--
+-- Process element for the Coordinate Descent architecture.
+-- Author: Mikael Henriksson (2021)
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package PE_PACKAGE is
+    type MUX1_SEL_TYPE is (YH, S2, TREE);
+    type MUX2_SEL_TYPE is (Y, QS2, SIGMA_Y, FEEDBACK);
+    type MUX3_SEL_TYPE is (SIGMA_INV, ZERO, FEEDBACK);
+    type PE_SUB_TYPE   is (ADD, SUB);
+end package PE_PACKAGE;
+
+library ieee, work;
+use work.PE_PACKAGE.all;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity PE is
+    port(
+        clk     : in std_logic;
+        rst     : in std_logic;
+        pe_sub  : in PE_SUB_TYPE;
+
+        -- Input of Mux 1
+        YH_real, YH_imag                 : in signed(9+3 - 1 downto 0);
+        s2_real, s2_imag                 : in signed(-1+36 - 1 downto 0);
+        tree_real, tree_imag             : in signed(-1+36 - 1 downto 0);
+        mux1_sel                         : in MUX1_SEL_TYPE;
+
+        -- Input of Mux 2
+        Y_real, Y_imag                   : in signed(9+3 - 1 downto 0);
+        qs2_real, qs2_imag               : in signed(7+33 - 1 downto 0);
+        Sigma_Y_real, Sigma_Y_imag       : in signed(18+6 - 1 downto 0);
+        mux2_sel                         : in MUX2_SEL_TYPE;
+
+        -- Input of Mux 3
+        Sigma_inv_real, Sigma_inv_imag   : in signed(-2+36 - 1 downto 0);
+        mux3_sel                         : in MUX3_SEL_TYPE;
+
+        -- MAC register output
+        mac_out_real                     : out signed(40 - 1 downto 0);
+        mac_out_imag                     : out signed(40 - 1 downto 0)
+    );
+end entity PE;
+
+architecture rtl of PE is
+    signal mux1_out_real, mux1_out_imag       : signed(35 - 1 downto 0);
+    signal mux2_out_real, mux2_out_imag       : signed(40 - 1 downto 0);
+    signal mux3_out_real, mux3_out_imag       : signed(40 - 1 downto 0);
+    signal mul_out_real, mul_out_imag         : signed(35+40 - 1 downto 0);
+    signal mul_out_real_rnd, mul_out_imag_rnd : signed(40 - 1 downto 0);
+    signal add_out_real, add_out_imag         : signed(40 - 1 downto 0);
+    signal reg_real, reg_imag                 : signed(40 - 1 downto 0);
+begin
+
+    -- Multiplexer 1 logic
+    with mux1_sel select mux1_out_real <=
+        Y_real & x"00000" & "000" when YH,
+        s2_real                    when S2,
+        tree_real                  when TREE;
+    with mux1_sel select mux1_out_imag <=
+        Y_imag & x"00000" & "000" when YH,
+        s2_imag                    when S2,
+        tree_imag                  when TREE;
+
+    -- Multiplexer 2 logic
+    with mux2_sel select mux2_out_real <=
+        YH_real & x"0000000"    when Y,
+        qs2_real               when QS2,
+        Sigma_Y_real & X"0000" when SIGMA_Y,
+        reg_imag               when FEEDBACK;
+    with mux2_sel select mux2_out_imag <=
+        YH_imag & x"0000000"    when Y,
+        qs2_imag               when QS2,
+        Sigma_Y_imag & X"0000" when SIGMA_Y,
+        reg_real               when FEEDBACK;
+
+    -- Multiplexer 3 logic
+    with mux3_sel select mux3_out_real <=
+        Sigma_inv_real & "000000" when SIGMA_INV,
+        reg_real(39 downto 0)     when FEEDBACK,
+        (others => '0')           when ZERO;
+    with mux3_sel select mux3_out_imag <=
+        Sigma_inv_imag & "000000" when SIGMA_INV,
+        reg_imag(39 downto 0)     when FEEDBACK,
+        (others => '0')           when ZERO;
+
+    --
+    -- Process element complex multiplier
+    --
+    process(clk)
+    begin
+        if rising_edge(clk) then
+            mul_out_real <= mux1_out_real*mux2_out_real +
+                            mux1_out_imag*mux2_out_imag;
+            mul_out_imag <= mux1_out_real*mux2_out_imag -
+                            mux1_out_imag*mux2_out_real;
+        end if;
+    end process;
+
+    --
+    -- Selection of complex multiplication output bits and rounding.
+    --
+    process(mul_out_real, mul_out_imag, pe_sub)
+        variable mul_out_real_rnd_long, mul_out_imag_rnd_long : signed(41-1 downto 0);
+    begin
+        case pe_sub is
+            when ADD =>
+                -- Select the most significant bits of multiplier
+                mul_out_real_rnd_long := mul_out_real(74 downto 34) + x"01";
+                mul_out_imag_rnd_long := mul_out_imag(74 downto 34) + x"01";
+            when SUB =>
+                -- From FixP: <6,69> --> FixP: <-2,43>  --> FixP: <-2,37>
+                mul_out_real_rnd_long := mul_out_real(66 downto 26) + x"040";
+                mul_out_imag_rnd_long := mul_out_imag(66 downto 26) + x"040";
+                mul_out_real_rnd_long(6 downto 0) := "0000000";
+                mul_out_imag_rnd_long(6 downto 0) := "0000000";
+        end case;
+        mul_out_real_rnd <= mul_out_real_rnd_long(40 downto 1);
+        mul_out_imag_rnd <= mul_out_imag_rnd_long(40 downto 1);
+    end process;
+
+    --
+    -- Process element adder
+    --
+    process(mul_out_real_rnd, mul_out_imag_rnd, mux3_out_real, mux3_out_imag, pe_sub)
+        variable add_out_real_long, add_out_imag_long : signed(41 - 1 downto 0);
+        variable add_in_real, add_in_imag   : signed(40 - 1 downto 0);
+        variable cin_real, cin_imag : std_logic;
+    begin
+        case pe_sub is
+            when ADD =>
+                cin_real := '0'; cin_imag := '0';
+                add_in_real := mul_out_real_rnd;
+                add_in_imag := mul_out_imag_rnd;
+            when SUB =>
+                cin_real := '1'; cin_imag := '1';
+                add_in_real := not(mul_out_real_rnd);
+                add_in_imag := not(mul_out_imag_rnd);
+        end case;
+        add_out_real_long := (mux3_out_real & '1') + (add_in_real & cin_real);
+        add_out_imag_long := (mux3_out_imag & '1') + (add_in_imag & cin_imag);
+        add_out_real <= add_out_real_long(40 downto 1);
+        add_out_imag <= add_out_imag_long(40 downto 1);
+    end process;
+
+    -- Mac register
+    process(clk)
+    begin
+        if rising_edge(clk) then
+            if rst = '1' then
+                reg_real <= (others => '0');
+                reg_imag <= (others => '0');
+            else
+                reg_real <= add_out_real;
+                reg_imag <= add_out_imag;
+            end if;
+        end if;
+    end process;
+    mac_out_real <= reg_real;
+    mac_out_imag <= reg_imag;
+
+end architecture rtl;
+

cadence/21.10/ex/sources.txt

+# This file contains the names of all files used in the design. These files
+# should be located in the folder specified in the folder specified in
+# PATH_SRC_BASE set in config_syn.tcl
+
+pe.vhdl
+