diff --git a/cadence/genus/README b/cadence/21.10/README similarity index 95% rename from cadence/genus/README rename to cadence/21.10/README index e6e9b6e82e60ab15ebe2216c8f998de795803990..d3b798fafde664ef48979eaef738cb8745ba33cb 100644 --- a/cadence/genus/README +++ b/cadence/21.10/README @@ -1,18 +1,18 @@ # st28flow A collection of scripts used for synthesis and place and route in Cadence Genus and Innovus. The scripts use a STMicroelectronics 28nm FD-SOI cell -library and are designed to be run on umbriel.cse.chalmers.se. +library and are designed to be run on only-da.ad.liu.se ## Sofware versions The scripts use the following software versions. -- Cadence Genus 16.22 -- Cadence Innovus 16.13 +- Cadence Genus 21.10 +- Cadence Innovus 21.10 - Cadence Virtuoso 6.1.7 ## Cloning The repo can be cloned on the umbriel server by executing: -`git clone /Home/erikbor/git/st28flow.git` +`git clone https://gitlab.liu.se/mikhe33/da-eda.git` ## Content The following sections describe the content of the repo. diff --git a/cadence/genus/config_pnr.tcl b/cadence/21.10/config_pnr.tcl similarity index 100% rename from cadence/genus/config_pnr.tcl rename to cadence/21.10/config_pnr.tcl diff --git a/cadence/genus/config_syn.tcl b/cadence/21.10/config_syn.tcl similarity index 92% rename from cadence/genus/config_syn.tcl rename to cadence/21.10/config_syn.tcl index 626705457e686a9823243841eb1fe94597d696cf..e4a7a4c3ad4d1d55d69dfe9fe4da6eab0f2902c7 100644 --- a/cadence/genus/config_syn.tcl +++ b/cadence/21.10/config_syn.tcl @@ -4,8 +4,7 @@ set PATH_LIB_BASE "/sw/cadence/libraries/CMOS28_FDSOI-2.5.d"; # Base path to cel # testar, LVT verkar finnas #set PATH_LIB_BASE "/sw/cadence/libraries/cmos28fdsoi_27a"; # Base path to cell library -#set PATH_SRC_BASE "./ex"; # Base path to source files -set PATH_SRC_BASE "../code/VE-LiU2"; # Base path to source files +set PATH_SRC_BASE "./ex"; # Base path to source files # Files #set FILE_SOURCE_LIST "./ex/$INSTANCE_NAME/sources.txt"; # List of source files diff --git a/cadence/21.10/ex/pe.vhdl b/cadence/21.10/ex/pe.vhdl new file mode 100644 index 0000000000000000000000000000000000000000..7bc487d7409394a54f347ba6ee7566cf60aab106 --- /dev/null +++ b/cadence/21.10/ex/pe.vhdl @@ -0,0 +1,168 @@ +-- +-- Process element for the Coordinate Descent architecture. +-- Author: Mikael Henriksson (2021) +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +package PE_PACKAGE is + type MUX1_SEL_TYPE is (YH, S2, TREE); + type MUX2_SEL_TYPE is (Y, QS2, SIGMA_Y, FEEDBACK); + type MUX3_SEL_TYPE is (SIGMA_INV, ZERO, FEEDBACK); + type PE_SUB_TYPE is (ADD, SUB); +end package PE_PACKAGE; + +library ieee, work; +use work.PE_PACKAGE.all; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity PE is + port( + clk : in std_logic; + rst : in std_logic; + pe_sub : in PE_SUB_TYPE; + + -- Input of Mux 1 + YH_real, YH_imag : in signed(9+3 - 1 downto 0); + s2_real, s2_imag : in signed(-1+36 - 1 downto 0); + tree_real, tree_imag : in signed(-1+36 - 1 downto 0); + mux1_sel : in MUX1_SEL_TYPE; + + -- Input of Mux 2 + Y_real, Y_imag : in signed(9+3 - 1 downto 0); + qs2_real, qs2_imag : in signed(7+33 - 1 downto 0); + Sigma_Y_real, Sigma_Y_imag : in signed(18+6 - 1 downto 0); + mux2_sel : in MUX2_SEL_TYPE; + + -- Input of Mux 3 + Sigma_inv_real, Sigma_inv_imag : in signed(-2+36 - 1 downto 0); + mux3_sel : in MUX3_SEL_TYPE; + + -- MAC register output + mac_out_real : out signed(40 - 1 downto 0); + mac_out_imag : out signed(40 - 1 downto 0) + ); +end entity PE; + +architecture rtl of PE is + signal mux1_out_real, mux1_out_imag : signed(35 - 1 downto 0); + signal mux2_out_real, mux2_out_imag : signed(40 - 1 downto 0); + signal mux3_out_real, mux3_out_imag : signed(40 - 1 downto 0); + signal mul_out_real, mul_out_imag : signed(35+40 - 1 downto 0); + signal mul_out_real_rnd, mul_out_imag_rnd : signed(40 - 1 downto 0); + signal add_out_real, add_out_imag : signed(40 - 1 downto 0); + signal reg_real, reg_imag : signed(40 - 1 downto 0); +begin + + -- Multiplexer 1 logic + with mux1_sel select mux1_out_real <= + Y_real & x"00000" & "000" when YH, + s2_real when S2, + tree_real when TREE; + with mux1_sel select mux1_out_imag <= + Y_imag & x"00000" & "000" when YH, + s2_imag when S2, + tree_imag when TREE; + + -- Multiplexer 2 logic + with mux2_sel select mux2_out_real <= + YH_real & x"0000000" when Y, + qs2_real when QS2, + Sigma_Y_real & X"0000" when SIGMA_Y, + reg_imag when FEEDBACK; + with mux2_sel select mux2_out_imag <= + YH_imag & x"0000000" when Y, + qs2_imag when QS2, + Sigma_Y_imag & X"0000" when SIGMA_Y, + reg_real when FEEDBACK; + + -- Multiplexer 3 logic + with mux3_sel select mux3_out_real <= + Sigma_inv_real & "000000" when SIGMA_INV, + reg_real(39 downto 0) when FEEDBACK, + (others => '0') when ZERO; + with mux3_sel select mux3_out_imag <= + Sigma_inv_imag & "000000" when SIGMA_INV, + reg_imag(39 downto 0) when FEEDBACK, + (others => '0') when ZERO; + + -- + -- Process element complex multiplier + -- + process(clk) + begin + if rising_edge(clk) then + mul_out_real <= mux1_out_real*mux2_out_real + + mux1_out_imag*mux2_out_imag; + mul_out_imag <= mux1_out_real*mux2_out_imag - + mux1_out_imag*mux2_out_real; + end if; + end process; + + -- + -- Selection of complex multiplication output bits and rounding. + -- + process(mul_out_real, mul_out_imag, pe_sub) + variable mul_out_real_rnd_long, mul_out_imag_rnd_long : signed(41-1 downto 0); + begin + case pe_sub is + when ADD => + -- Select the most significant bits of multiplier + mul_out_real_rnd_long := mul_out_real(74 downto 34) + x"01"; + mul_out_imag_rnd_long := mul_out_imag(74 downto 34) + x"01"; + when SUB => + -- From FixP: <6,69> --> FixP: <-2,43> --> FixP: <-2,37> + mul_out_real_rnd_long := mul_out_real(66 downto 26) + x"040"; + mul_out_imag_rnd_long := mul_out_imag(66 downto 26) + x"040"; + mul_out_real_rnd_long(6 downto 0) := "0000000"; + mul_out_imag_rnd_long(6 downto 0) := "0000000"; + end case; + mul_out_real_rnd <= mul_out_real_rnd_long(40 downto 1); + mul_out_imag_rnd <= mul_out_imag_rnd_long(40 downto 1); + end process; + + -- + -- Process element adder + -- + process(mul_out_real_rnd, mul_out_imag_rnd, mux3_out_real, mux3_out_imag, pe_sub) + variable add_out_real_long, add_out_imag_long : signed(41 - 1 downto 0); + variable add_in_real, add_in_imag : signed(40 - 1 downto 0); + variable cin_real, cin_imag : std_logic; + begin + case pe_sub is + when ADD => + cin_real := '0'; cin_imag := '0'; + add_in_real := mul_out_real_rnd; + add_in_imag := mul_out_imag_rnd; + when SUB => + cin_real := '1'; cin_imag := '1'; + add_in_real := not(mul_out_real_rnd); + add_in_imag := not(mul_out_imag_rnd); + end case; + add_out_real_long := (mux3_out_real & '1') + (add_in_real & cin_real); + add_out_imag_long := (mux3_out_imag & '1') + (add_in_imag & cin_imag); + add_out_real <= add_out_real_long(40 downto 1); + add_out_imag <= add_out_imag_long(40 downto 1); + end process; + + -- Mac register + process(clk) + begin + if rising_edge(clk) then + if rst = '1' then + reg_real <= (others => '0'); + reg_imag <= (others => '0'); + else + reg_real <= add_out_real; + reg_imag <= add_out_imag; + end if; + end if; + end process; + mac_out_real <= reg_real; + mac_out_imag <= reg_imag; + +end architecture rtl; + diff --git a/cadence/21.10/ex/sources.txt b/cadence/21.10/ex/sources.txt new file mode 100644 index 0000000000000000000000000000000000000000..e3226b986477631fee888b73ddcbc6f41fef0a3a --- /dev/null +++ b/cadence/21.10/ex/sources.txt @@ -0,0 +1,6 @@ +# This file contains the names of all files used in the design. These files +# should be located in the folder specified in the folder specified in +# PATH_SRC_BASE set in config_syn.tcl + +pe.vhdl + diff --git a/cadence/genus/lvs/control.tcl b/cadence/21.10/lvs/control.tcl similarity index 100% rename from cadence/genus/lvs/control.tcl rename to cadence/21.10/lvs/control.tcl diff --git a/cadence/genus/lvs/gen_lvs_box.sh b/cadence/21.10/lvs/gen_lvs_box.sh similarity index 100% rename from cadence/genus/lvs/gen_lvs_box.sh rename to cadence/21.10/lvs/gen_lvs_box.sh diff --git a/cadence/genus/pnr.sh b/cadence/21.10/pnr.sh similarity index 100% rename from cadence/genus/pnr.sh rename to cadence/21.10/pnr.sh diff --git a/cadence/genus/power_analysis.sh b/cadence/21.10/power_analysis.sh similarity index 100% rename from cadence/genus/power_analysis.sh rename to cadence/21.10/power_analysis.sh diff --git a/cadence/genus/power_analysis.tcl b/cadence/21.10/power_analysis.tcl similarity index 100% rename from cadence/genus/power_analysis.tcl rename to cadence/21.10/power_analysis.tcl diff --git a/cadence/genus/synth.sh b/cadence/21.10/synth.bash old mode 100644 new mode 100755 similarity index 100% rename from cadence/genus/synth.sh rename to cadence/21.10/synth.bash diff --git a/cadence/genus/tcl/fp.tcl b/cadence/21.10/tcl/fp.tcl similarity index 100% rename from cadence/genus/tcl/fp.tcl rename to cadence/21.10/tcl/fp.tcl diff --git a/cadence/genus/tcl/pnr.tcl b/cadence/21.10/tcl/pnr.tcl similarity index 100% rename from cadence/genus/tcl/pnr.tcl rename to cadence/21.10/tcl/pnr.tcl diff --git a/cadence/genus/tcl/pnr/checks.tcl b/cadence/21.10/tcl/pnr/checks.tcl similarity index 100% rename from cadence/genus/tcl/pnr/checks.tcl rename to cadence/21.10/tcl/pnr/checks.tcl diff --git a/cadence/genus/tcl/pnr/clock.tcl b/cadence/21.10/tcl/pnr/clock.tcl similarity index 100% rename from cadence/genus/tcl/pnr/clock.tcl rename to cadence/21.10/tcl/pnr/clock.tcl diff --git a/cadence/genus/tcl/pnr/export.tcl b/cadence/21.10/tcl/pnr/export.tcl similarity index 100% rename from cadence/genus/tcl/pnr/export.tcl rename to cadence/21.10/tcl/pnr/export.tcl diff --git a/cadence/genus/tcl/pnr/fillers.tcl b/cadence/21.10/tcl/pnr/fillers.tcl similarity index 100% rename from cadence/genus/tcl/pnr/fillers.tcl rename to cadence/21.10/tcl/pnr/fillers.tcl diff --git a/cadence/genus/tcl/pnr/floorplan.tcl b/cadence/21.10/tcl/pnr/floorplan.tcl similarity index 100% rename from cadence/genus/tcl/pnr/floorplan.tcl rename to cadence/21.10/tcl/pnr/floorplan.tcl diff --git a/cadence/genus/tcl/pnr/init.tcl b/cadence/21.10/tcl/pnr/init.tcl similarity index 100% rename from cadence/genus/tcl/pnr/init.tcl rename to cadence/21.10/tcl/pnr/init.tcl diff --git a/cadence/genus/tcl/pnr/mmmc.tcl b/cadence/21.10/tcl/pnr/mmmc.tcl similarity index 100% rename from cadence/genus/tcl/pnr/mmmc.tcl rename to cadence/21.10/tcl/pnr/mmmc.tcl diff --git a/cadence/genus/tcl/pnr/place.tcl b/cadence/21.10/tcl/pnr/place.tcl similarity index 100% rename from cadence/genus/tcl/pnr/place.tcl rename to cadence/21.10/tcl/pnr/place.tcl diff --git a/cadence/genus/tcl/pnr/power.tcl b/cadence/21.10/tcl/pnr/power.tcl similarity index 100% rename from cadence/genus/tcl/pnr/power.tcl rename to cadence/21.10/tcl/pnr/power.tcl diff --git a/cadence/genus/tcl/pnr/route.tcl b/cadence/21.10/tcl/pnr/route.tcl similarity index 100% rename from cadence/genus/tcl/pnr/route.tcl rename to cadence/21.10/tcl/pnr/route.tcl diff --git a/cadence/genus/tcl/synth.tcl b/cadence/21.10/tcl/synth.tcl similarity index 100% rename from cadence/genus/tcl/synth.tcl rename to cadence/21.10/tcl/synth.tcl diff --git a/cadence/genus/ex/sources.txt b/cadence/genus/ex/sources.txt deleted file mode 100644 index 13e1f24fd61bac4bf4b210a15f11c6f6003ab24f..0000000000000000000000000000000000000000 --- a/cadence/genus/ex/sources.txt +++ /dev/null @@ -1,34 +0,0 @@ -# This file contains the names of all files used in the design. These files -# should be located in the folder specified in the folder specified in -# PATH_SRC_BASE set in settings.tcl. - -# VE-LiU2 -vetypes.vhdl -instructiontypes.vhdl -lzod.vhdl -writebuff.vhdl -ppshift.vhdl -ppmap1.vhdl -ctrlmap_acc.vhdl -ctrlmap_alu.vhdl -ppadd.vhdl -accumulatoreven.vhdl -accumulatorodd.vhdl -addmul.vhdl -vearith.vhdl -memreg.vhdl -vecore.vhdl -ve_wctrlpipe.vhdl -./ldl/ldlinvcontroller.vhdl -ve_wctrl.vhdl - - -# VE-LIU -#./VE-LIU/VE.vhdl -#./VE-LIU/Accumulator.vhdl -#./VE-LIU/mul.vhdl - - -# r2butterfly -#./r2butterfly_syn/r2butterfly.vhdl -#./r2butterfly_syn/r2butterfly_syn.vhdl