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Commit 0cea0499 authored by Martin Högstedt's avatar Martin Högstedt
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merged w main

parents 855868ba 7bc3c424
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1 merge request!13We know have asm instructions, can step forward and backward between clock cycle and asm instructions
Pipeline #131566 passed
from simudator.core.module import Module
from simudator.core.processor import Processor from simudator.core.processor import Processor
TEST_PATH = "test/test_core/processor_state_test.txt" TEST_PATH = "test/test_core/processor_state_test.txt"
class Dummymodule: class Dummymodule(Module):
def __init__(self, name): def __init__(self, name):
self.name = name self.name = name
self.string = None self.string = None
def load_from_str(self, string): def load_from_str(self, state_string):
self.string = string self.string = state_string
def get_string(self): def get_string(self):
return self.string return self.string
def reset(self):
self.string = ""
def test_load_from_file(): def test_load_from_file():
cpu = Processor() cpu = Processor()
......
...@@ -83,11 +83,11 @@ def test_load(): ...@@ -83,11 +83,11 @@ def test_load():
input_s1 = Signal(cpu, value=0) input_s1 = Signal(cpu, value=0)
output_s1 = Signal(cpu, value=0) output_s1 = Signal(cpu, value=0)
adress_s1 = Signal(cpu, value=0) adress_s1 = Signal(cpu, value=0)
bus_control_s1 = Signal(cpu, value=0) bus_control_s1 = Signal(cpu)
input_s2 = Signal(cpu, value=0) input_s2 = Signal(cpu, value=0)
output_s2 = Signal(cpu, value=0) output_s2 = Signal(cpu, value=0)
adress_s2 = Signal(cpu, value=0) adress_s2 = Signal(cpu, value=0)
bus_control_s2 = Signal(cpu, value=0) bus_control_s2 = Signal(cpu)
pm1 = MiaMemory( pm1 = MiaMemory(
input_s1, output_s1, adress_s1, bus_control_s1, 4, 0b010, name="PM1" input_s1, output_s1, adress_s1, bus_control_s1, 4, 0b010, name="PM1"
) )
......
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