diff --git a/test/test_core/test_processor.py b/test/test_core/test_processor.py
index e619636f3f43b9c7b017e744087a6600f1120f47..7e978f5a419589e81d2a11a7c452c450261aefa8 100644
--- a/test/test_core/test_processor.py
+++ b/test/test_core/test_processor.py
@@ -1,19 +1,23 @@
+from simudator.core.module import Module
 from simudator.core.processor import Processor
 
 TEST_PATH = "test/test_core/processor_state_test.txt"
 
 
-class Dummymodule:
+class Dummymodule(Module):
     def __init__(self, name):
         self.name = name
         self.string = None
 
-    def load_from_str(self, string):
-        self.string = string
+    def load_from_str(self, state_string):
+        self.string = state_string 
 
     def get_string(self):
         return self.string
 
+    def reset(self):
+        self.string = ""
+
 
 def test_load_from_file():
     cpu = Processor()
diff --git a/test/test_mia/test_mia_memory.py b/test/test_mia/test_mia_memory.py
index 99e0227c01bf6edc1869fbf16487931704af93b5..b0bd470a2dd183b7a0d5b236d561fd196f9c5fe1 100644
--- a/test/test_mia/test_mia_memory.py
+++ b/test/test_mia/test_mia_memory.py
@@ -83,11 +83,11 @@ def test_load():
     input_s1 = Signal(cpu, value=0)
     output_s1 = Signal(cpu, value=0)
     adress_s1 = Signal(cpu, value=0)
-    bus_control_s1 = Signal(cpu, value=0)
+    bus_control_s1 = Signal(cpu)
     input_s2 = Signal(cpu, value=0)
     output_s2 = Signal(cpu, value=0)
     adress_s2 = Signal(cpu, value=0)
-    bus_control_s2 = Signal(cpu, value=0)
+    bus_control_s2 = Signal(cpu)
     pm1 = MiaMemory(
         input_s1, output_s1, adress_s1, bus_control_s1, 4, 0b010, name="PM1"
     )