Add more execution time != 1 tests for ListScheduler and fix port-constraint bugs
- Add more execution time != 1 tests for ListScheduler.
- Fix port-constraint bugs.
- Add ILP-based
split_on_execution_time
method. - Add ILP-based
assign
method for memories.
Closes: #356 (closed) #354 (closed)
Merge request reports
Activity
added Scheduling label
assigned to @simbj106
411 411 log.debug("Scheduler initializing") 412 412 self._initialize_scheduler(schedule) 413 413 414 if self._sfg.loops and self._schedule.cyclic: 414 if self._schedule.cyclic and self._sfg.loops: This will be much faster when cyclic=False since the loops method is slow for large SFGs.
Edited by Simon BjurekI guess it would be an option to add an admonition https://sphinx-book-theme.readthedocs.io/en/stable/reference/kitchen-sink/admonitions.html just stating that it will not work for recursive algorithms if computing the loops is too time consuming. Shit in, shit out.
changed this line in version 5 of the diff
added 1 commit
- 5c634d6b - Add more execution time != 1 tests for ListScheduler and fix port-constraint bugs
1891 memories.append(memory) 1892 memory.assign("graph_color") 1893 1894 arch = Architecture( 1895 processing_elements, 1896 memories, 1897 direct_interconnects=direct, 1898 ) 1899 assert len(arch.processing_elements) == 4 1900 assert len(arch.memories) == 2 1901 1902 def test_execution_time_not_one_and_latency_offsets_port_constrained(self): 1903 sfg = radix_2_dif_fft(points=16) 1904 1905 sfg.set_latency_offsets_of_type( 1906 Butterfly, {"in0": 0, "in1": 1, "out0": 1, "out1": 2} and execution time of 2 will actually lead to a realistic case. (Single input port butterfly, computing addition and subtraction sequentially.)
(This also opens the question how to model that inputs and outputs share the same PE port...)
changed this line in version 5 of the diff
821 825 822 826 def _update_port_reads(self, next_op: "Operation") -> None: 823 827 for input_port in next_op.inputs: 824 source_op = input_port.signals[0].source.operation 828 source_port = input_port.signals[0].source 829 source_op = source_port.operation 830 time = self._current_time + input_port.latency_offset 825 831 if ( 826 832 not isinstance(source_op, DontCare) 827 833 and not isinstance(source_op, Delay) changed this line in version 5 of the diff