Split on ports-bug

Consider https://da.gitlab-pages.liu.se/B-ASIC/examples/secondorderdirectformiir_architecture.html

When executing with total_ports=1, the result is e.g.:

Where two variables, cmul1.0 and add1.0 read at the same time, despite read_ports=1.

It is not even possible to split solve this using a single port in total as one variable is read and written at the same time, but nothing complains.

Using total_ports=2 leads to:

where cmul3.0 and cmul4.0 are read at the same time, despite read_ports=1. (cmul4.0 can go in the other memory without any problems.)