# Conflicts:
#   b_asic/operation.py
#   b_asic/signal_flow_graph.py
#   test/fixtures/signal_flow_graph.py

Kevin Scott authored 5 years ago and Ivar Härnqvist committed 5 years ago

Refactor constructor so that Input signals and Output signals are connected to ports before traversal is started, that way edge cases of empty SFG's are easily handled

Refactor constructor so that Input signals and Output signals are connected to ports before traversal is started, that way edge cases of empty SFG's are easily handled

Resolve "System tests iteration 1"

See merge request PUM_TDDD96/B-ASIC!25

Kevin Scott authored 5 years ago and Adam Jakobsson committed 5 years ago

Refactor constructor so that Input signals and Output signals are connected to ports before traversal is started, that way edge cases of empty SFG's are easily handled

Resolve "Replacing Operations in SFG"

See merge request PUM_TDDD96/B-ASIC!22

Resolve "Simulate SFG"

See merge request PUM_TDDD96/B-ASIC!23

Ivar Härnqvist authored 5 years ago and Angus Lothian committed 5 years ago

Refactor constructor so that Input signals and Output signals are connected to ports before traversal is started, that way edge cases of empty SFG's are easily handled

add support for reverse operator overloads, remove constant operations other than ConstantMultiplication (as discussed with client) to make the core operations less bloated/confusing

Resolve "Print SFG"

See merge request PUM_TDDD96/B-ASIC!21

Adam Jakobsson authored 5 years ago and Felix Goding committed 5 years ago

Refactor constructor so that Input signals and Output signals are connected to ports before traversal is started, that way edge cases of empty SFG's are easily handled

refactor graph component/operation interfaces, refactor traverse, fix tests, move value_length to signal, rename value_length to bits