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Commit e623759a authored by Oscar Gustafsson's avatar Oscar Gustafsson :bicyclist:
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Add more tests for Process

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......@@ -58,7 +58,7 @@ class Process:
return self._name
def __repr__(self) -> str:
return f"Process({self.start_time}, {self.execution_time}, {self.name})"
return f"Process({self.start_time}, {self.execution_time}, {self.name!r})"
# Static counter for default names
_name_cnt = 0
......@@ -166,7 +166,8 @@ class PlainMemoryVariable(Process):
Identifier for the source of the memory variable.
reads : {int: int, ...}
Dictionary where the key is the destination identifier and the value
is the time after *write_time* that the memory variable is read.
is the time after *write_time* that the memory variable is read, i.e., the
lifetime of the variable.
name : str, optional
The name of the process.
"""
......
......@@ -9,13 +9,13 @@ def simple_collection():
NO_PORT = 0
return ProcessCollection(
{
PlainMemoryVariable(4, NO_PORT, {NO_PORT: 2}),
PlainMemoryVariable(2, NO_PORT, {NO_PORT: 6}),
PlainMemoryVariable(3, NO_PORT, {NO_PORT: 5}),
PlainMemoryVariable(6, NO_PORT, {NO_PORT: 2}),
PlainMemoryVariable(0, NO_PORT, {NO_PORT: 3}),
PlainMemoryVariable(0, NO_PORT, {NO_PORT: 2}),
PlainMemoryVariable(0, NO_PORT, {NO_PORT: 6}),
PlainMemoryVariable(4, NO_PORT, {NO_PORT: 2}, "Proc. 1"),
PlainMemoryVariable(2, NO_PORT, {NO_PORT: 6}, "Proc. 2"),
PlainMemoryVariable(3, NO_PORT, {NO_PORT: 5}, "Proc. 3"),
PlainMemoryVariable(6, NO_PORT, {NO_PORT: 2}, "Proc. 4"),
PlainMemoryVariable(0, NO_PORT, {NO_PORT: 3}, "Proc. 5"),
PlainMemoryVariable(0, NO_PORT, {NO_PORT: 2}, "Proc. 6"),
PlainMemoryVariable(0, NO_PORT, {NO_PORT: 6}, "Proc. 7"),
},
8,
)
......
import re
import pytest
from b_asic.process import PlainMemoryVariable
......@@ -10,3 +12,25 @@ def test_PlainMemoryVariable():
assert mem.execution_time == 2
assert mem.life_times == (1, 2)
assert mem.read_ports == (4, 5)
assert repr(mem) == "PlainMemoryVariable(3, 0, {4: 1, 5: 2}, 'Proc. 0')"
mem2 = PlainMemoryVariable(2, 0, {4: 2, 5: 3}, 'foo')
assert repr(mem2) == "PlainMemoryVariable(2, 0, {4: 2, 5: 3}, 'foo')"
assert mem2 < mem
mem3 = PlainMemoryVariable(2, 0, {4: 1, 5: 2})
assert mem2 < mem3
def test_MemoryVariables(secondorder_iir_schedule):
pc = secondorder_iir_schedule.get_memory_variables()
mem_vars = pc.collection
pattern = re.compile(
"MemoryVariable\\(3, <b_asic.port.OutputPort object at 0x[a-f0-9]+>,"
" {<b_asic.port.InputPort object at 0x[a-f0-9]+>: 4}, 'cmul1.0'\\)"
)
mem_var = [m for m in mem_vars if m.name == 'cmul1.0'][0]
assert pattern.match(repr(mem_var))
assert mem_var.execution_time == 4
assert mem_var.start_time == 3
......@@ -4,6 +4,7 @@ import matplotlib.pyplot as plt
import networkx as nx
import pytest
from b_asic.process import Process
from b_asic.research.interleaver import (
generate_matrix_transposer,
generate_random_interleaver,
......
......@@ -46,6 +46,8 @@ class TestRunFor:
assert simulation.results["0"][3] == 13
assert simulation.results["1"][3] == 20
assert simulation.iteration == 101
def test_with_numpy_arrays_as_input(self, sfg_two_inputs_two_outputs):
input0 = np.array([5, 9, 25, -5, 7])
input1 = np.array([7, 3, 3, 54, 2])
......@@ -131,15 +133,11 @@ class TestRunFor:
)
sim.run()
assert (
sim.results[
precedence_sfg_delays.find_result_keys_by_name("ADD2")[0]
][4]
sim.results[precedence_sfg_delays.find_result_keys_by_name("ADD2")[0]][4]
== 31220
)
assert (
sim.results[
precedence_sfg_delays.find_result_keys_by_name("A1")[0]
][2]
sim.results[precedence_sfg_delays.find_result_keys_by_name("A1")[0]][2]
== 80
)
......@@ -220,9 +218,7 @@ class TestRun:
input0 = np.array([1, 2, 3, 4, 5])
simulation = Simulation(sfg_simple_filter, [input0])
simulation.run_for(len(input0), save_results=True)
assert all(
simulation.results["0"] == np.array([0, 1.0, 2.5, 4.25, 6.125])
)
assert all(simulation.results["0"] == np.array([0, 1.0, 2.5, 4.25, 6.125]))
def test_custom_operation(self, sfg_custom_operation):
simulation = Simulation(sfg_custom_operation, [lambda n: n + 1])
......
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