Assign argument to resources

b_asic/architecture.py

@@ -293,10 +293,15 @@ class ProcessingElement(Resource):
         Process collection containing operations to map to processing element.
     entity_name : str, optional
         Name of processing element entity.
+    assign : bool, default True
+        Perform assignment when creating the ProcessingElement.
     """
 
     def __init__(
-        self, process_collection: ProcessCollection, entity_name: Optional[str] = None
+        self,
+        process_collection: ProcessCollection,
+        entity_name: Optional[str] = None,
+        assign: bool = True,
     ):
         super().__init__(process_collection=process_collection, entity_name=entity_name)
         if not all(
@@ -318,7 +323,8 @@ class ProcessingElement(Resource):
         self._type_name = op_type.type_name()
         self._input_count = ops[0].input_count
         self._output_count = ops[0].output_count
-        self.assign()
+        if assign:
+            self.assign()
 
     @property
     def processes(self) -> List[OperatorProcess]:
@@ -364,6 +370,9 @@ class Memory(Resource):
         Number of read ports for memory.
     write_ports : int, optional
         Number of write ports for memory.
+    assign : bool, default False
+        Perform assignment when creating the Memory (using the default properties).
+
     """
 
     def __init__(
@@ -373,6 +382,7 @@ class Memory(Resource):
         entity_name: Optional[str] = None,
         read_ports: Optional[int] = None,
         write_ports: Optional[int] = None,
+        assign: bool = False,
     ):
         super().__init__(process_collection=process_collection, entity_name=entity_name)
         if not all(
@@ -401,6 +411,8 @@ class Memory(Resource):
                 raise ValueError(f"At least {write_ports_bound} write ports required")
             self._input_count = write_ports
         self._memory_type = memory_type
+        if assign:
+            self.assign()
 
         memory_processes = [
             cast(MemoryProcess, process) for process in process_collection

examples/thirdorderblwdf.py

@@ -5,9 +5,13 @@ Third-order Bireciprocal LWDF
 
 Small bireciprocal lattice wave digital filter.
 """
+import numpy as np
+from mplsignal.freq_plots import freqz_fir
+
 from b_asic.core_operations import Addition, SymmetricTwoportAdaptor
 from b_asic.schedule import Schedule
 from b_asic.signal_flow_graph import SFG
+from b_asic.signal_generator import Impulse
 from b_asic.simulation import Simulation
 from b_asic.special_operations import Delay, Input, Output
 
@@ -21,19 +25,28 @@ a = s.output(0) + D0
 out0 = Output(a, "y")
 
 sfg = SFG(inputs=[in0], outputs=[out0], name="Third-order BLWDF")
+# %%
+# The SFG looks like
+sfg
 
-# Set latencies and exection times
+# %%
+# Set latencies and execution times
 sfg.set_latency_of_type(SymmetricTwoportAdaptor.type_name(), 4)
 sfg.set_latency_of_type(Addition.type_name(), 1)
 sfg.set_execution_time_of_type(SymmetricTwoportAdaptor.type_name(), 1)
 sfg.set_execution_time_of_type(Addition.type_name(), 1)
 
-sim = Simulation(sfg, [lambda n: 0 if n else 1])
+# %%
+# Simulate
+sim = Simulation(sfg, [Impulse()])
 sim.run_for(1000)
 
-import numpy as np
-from mplsignal.freq_plots import freqz_fir
 
+# %%
+# Display output
 freqz_fir(np.array(sim.results['0']) / 2)
 
+# %%
+# Create and display schedule
 schedule = Schedule(sfg, cyclic=True)
+schedule.show()