Skip to content
Snippets Groups Projects
Commit 9deafbbd authored by Oscar Gustafsson's avatar Oscar Gustafsson :bicyclist:
Browse files

Correct Delay documentation

parent 01109a8a
No related branches found
No related tags found
1 merge request!266Correct Delay documentation
Pipeline #93305 passed
...@@ -21,7 +21,7 @@ class Input(AbstractOperation): ...@@ -21,7 +21,7 @@ class Input(AbstractOperation):
""" """
Input operation. Input operation.
Marks an input port to an SFG. Represents an input port to an SFG.
Its value will be updated on each iteration when simulating the SFG. Its value will be updated on each iteration when simulating the SFG.
""" """
...@@ -102,7 +102,7 @@ class Output(AbstractOperation): ...@@ -102,7 +102,7 @@ class Output(AbstractOperation):
""" """
Output operation. Output operation.
Marks an output port to an SFG. Represents an output port to an SFG.
The SFG will forward its input to the corresponding output signal The SFG will forward its input to the corresponding output signal
destinations. destinations.
""" """
...@@ -160,8 +160,17 @@ class Delay(AbstractOperation): ...@@ -160,8 +160,17 @@ class Delay(AbstractOperation):
""" """
Unit delay operation. Unit delay operation.
Represents one unit of delay in a circuit, typically a clock cycle. Represents a delay of one iteration.
Can be thought of as a register or a D flip-flop. The initial value is zero unless otherwise specified.
Parameters
----------
src0 : SignalSourceProvider, optional
The node to be delayed.
initial_value : Number, default: 0
Initial value of the delay.
name : Name, default ""
Name.
""" """
def __init__( def __init__(
......
0% Loading or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment