Skip to content
Snippets Groups Projects
Commit 739cffd1 authored by Hugo Winbladh's avatar Hugo Winbladh
Browse files

add bold names to architecture resources

parent 49696f2b
No related branches found
No related tags found
No related merge requests found
Pipeline #100167 passed
...@@ -204,8 +204,8 @@ class Resource(HardwareBlock): ...@@ -204,8 +204,8 @@ class Resource(HardwareBlock):
] ]
ret += f"<TR>{''.join(in_strs)}</TR>" ret += f"<TR>{''.join(in_strs)}</TR>"
ret += ( ret += (
'<TR><TD' f'<TR><TD COLSPAN="{table_width}">'
f' COLSPAN="{table_width}">{self.entity_name}{self._info()}</TD></TR>' f'<B>{self.entity_name}{self._info()}</B></TD></TR>'
) )
if outputs: if outputs:
out_strs = [ out_strs = [
...@@ -987,7 +987,7 @@ of :class:`~b_asic.architecture.ProcessingElement` ...@@ -987,7 +987,7 @@ of :class:`~b_asic.architecture.ProcessingElement`
name = f"{destination.replace(':', '_')}_mux" name = f"{destination.replace(':', '_')}_mux"
ret += ( ret += (
f'<TR><TD COLSPAN="{len(inputs)}"' f'<TR><TD COLSPAN="{len(inputs)}"'
f' PORT="{name}">{name}</TD></TR>' f' PORT="{name}"><B>{name}</B></TD></TR>'
) )
ret += f'<TR><TD COLSPAN="{len(inputs)}" PORT="out0">out0</TD></TR>' ret += f'<TR><TD COLSPAN="{len(inputs)}" PORT="out0">out0</TD></TR>'
dg.node( dg.node(
......
...@@ -100,7 +100,7 @@ def test_architecture(schedule_direct_form_iir_lp_filter: Schedule): ...@@ -100,7 +100,7 @@ def test_architecture(schedule_direct_form_iir_lp_filter: Schedule):
+ ' [label=<<TABLE BORDER="0" CELLBORDER="1" CELLSPACING="0" CELLPADDING="4">' + ' [label=<<TABLE BORDER="0" CELLBORDER="1" CELLSPACING="0" CELLPADDING="4">'
+ '<TR><TD COLSPAN="1" PORT="in0">in0</TD>' + '<TR><TD COLSPAN="1" PORT="in0">in0</TD>'
+ '<TD COLSPAN="1" PORT="in1">in1</TD></TR>' + '<TD COLSPAN="1" PORT="in1">in1</TD></TR>'
+ '<TR><TD COLSPAN="2">adder</TD></TR>' + '<TR><TD COLSPAN="2"><B>adder</B></TD></TR>'
+ '<TR><TD COLSPAN="2" PORT="out0">out0</TD></TR>' + '<TR><TD COLSPAN="2" PORT="out0">out0</TD></TR>'
+ '</TABLE>> fillcolor="#00B9E7" fontname="Times New Roman" style=filled]\n}' + '</TABLE>> fillcolor="#00B9E7" fontname="Times New Roman" style=filled]\n}'
) )
...@@ -122,7 +122,7 @@ def test_architecture(schedule_direct_form_iir_lp_filter: Schedule): ...@@ -122,7 +122,7 @@ def test_architecture(schedule_direct_form_iir_lp_filter: Schedule):
+ ' [label=<<TABLE BORDER="0" CELLBORDER="1"' + ' [label=<<TABLE BORDER="0" CELLBORDER="1"'
+ ' CELLSPACING="0" CELLPADDING="4">' + ' CELLSPACING="0" CELLPADDING="4">'
+ '<TR><TD COLSPAN="1" PORT="in0">in0</TD></TR>' + '<TR><TD COLSPAN="1" PORT="in0">in0</TD></TR>'
+ '<TR><TD COLSPAN="1">MEM0</TD></TR>' + '<TR><TD COLSPAN="1"><B>MEM0</B></TD></TR>'
+ '<TR><TD COLSPAN="1" PORT="out0">out0</TD></TR>' + '<TR><TD COLSPAN="1" PORT="out0">out0</TD></TR>'
+ '</TABLE>> fillcolor="#00CFB5" fontname="Times New Roman" ' + '</TABLE>> fillcolor="#00CFB5" fontname="Times New Roman" '
+ 'style=filled]\n}' + 'style=filled]\n}'
......
0% Loading or .
You are about to add 0 people to the discussion. Proceed with caution.
Please register or to comment