Add cell info to architecture

b_asic/architecture.py

@@ -184,12 +184,15 @@ class Resource(HardwareBlock):
         if inputs:
             in_strs = [f"<{in_str}> {in_str}" for in_str in inputs]
             ret += f"{{{'|'.join(in_strs)}}}|"
-        ret += f"{self.entity_name}"
+        ret += f"<{self.entity_name}> {self.entity_name}{self._info()}"
         if outputs:
             out_strs = [f"<{out_str}> {out_str}" for out_str in outputs]
             ret += f"|{{{'|'.join(out_strs)}}}"
         return "{" + ret + "}"
 
+    def _info(self):
+        return ""
+
     @property
     def schedule_time(self) -> int:
         # doc-string inherited
@@ -456,6 +459,13 @@ class Memory(Resource):
         # Add information about the iterator type
         return cast(Iterator[MemoryVariable], iter(self._collection))
 
+    def _info(self):
+        if self.is_assigned:
+            if self._memory_type == "RAM":
+                plural_s = 's' if len(self._assignment) >= 2 else ''
+                return f": (RAM, {len(self._assignment)} cell{plural_s})"
+        return ""
+
     def assign(self, heuristic: str = "left_edge") -> None:
         """
         Perform assignment of the memory variables.
@@ -819,7 +829,7 @@ of :class:`~b_asic.architecture.ProcessingElement`
                     in_strs = [f"<{in_str}> {in_str}" for in_str in inputs]
                     ret += f"{{{'|'.join(in_strs)}}}|"
                     name = f"{destination.replace(':', '_')}_mux"
-                    ret += name
+                    ret += f"<{name}> {name}"
                     ret += "|<out> out"
                     dg.node(name, "{" + ret + "}")
                     dg.edge(f"{name}:out", destination)

test/test_architecture.py

@@ -104,9 +104,9 @@ def test_architecture(schedule_direct_form_iir_lp_filter: Schedule):
         if pe._type_name == 'add':
             s = (
                 'digraph {\n\tnode [shape=record]\n\t'
-                + pe._entity_name
+                + pe.entity_name
                 + ' [label="{{<in0> in0|<in1> in1}|'
-                + pe._entity_name
+                + f'<{pe.entity_name}> {pe.entity_name}'
                 + '|{<out0> out0}}"]\n}'
             )
             assert pe._digraph().source in (s, s + '\n')
@@ -123,8 +123,8 @@ def test_architecture(schedule_direct_form_iir_lp_filter: Schedule):
     for i, memory in enumerate(memories):
         memory.set_entity_name(f"MEM{i}")
         s = (
-            'digraph {\n\tnode [shape=record]\n\tMEM0 [label="{{<in0> in0}|MEM0|{<out0>'
-            ' out0}}"]\n}'
+            'digraph {\n\tnode [shape=record]\n\tMEM0 [label="{{<in0> in0}|<MEM0>'
+            ' MEM0|{<out0> out0}}"]\n}'
         )
         assert memory.schedule_time == 18
         assert memory._digraph().source in (s, s + '\n')
@@ -134,6 +134,14 @@ def test_architecture(schedule_direct_form_iir_lp_filter: Schedule):
         processing_elements, memories, direct_interconnects=direct_conn
     )
 
+    # Parts are non-deterministic, but this first part seems OK
+    s = (
+        'digraph {\n\tnode [shape=record]\n\tsplines=spline\n\tsubgraph'
+        ' cluster_memories'
+    )
+    assert architecture._digraph().source.startswith(s)
+    s = 'digraph {\n\tnode [shape=record]\n\tsplines=spline\n\tMEM0'
+    assert architecture._digraph(cluster=False).source.startswith(s)
     assert architecture.schedule_time == 18
 
     # assert architecture._digraph().source == "foo"