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Computer Engineering
B-ASIC - Better ASIC Toolbox
Commits
4d596b1c
Commit
4d596b1c
authored
2 years ago
by
Oscar Gustafsson
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Rename split*-methods
parent
22fe6ad7
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1 merge request
!343
Rename split*-methods
Pipeline
#96624
passed
2 years ago
Stage: test
Stage: deploy
Changes
3
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2
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3 changed files
b_asic/resources.py
+14
-7
14 additions, 7 deletions
b_asic/resources.py
test/test_architecture.py
+8
-10
8 additions, 10 deletions
test/test_architecture.py
test/test_resources.py
+4
-4
4 additions, 4 deletions
test/test_resources.py
with
26 additions
and
21 deletions
b_asic/resources.py
+
14
−
7
View file @
4d596b1c
...
...
@@ -754,7 +754,7 @@ class ProcessCollection:
exclusion_graph
.
add_edge
(
process1
,
process2
)
return
exclusion_graph
def
split_execution_time
(
def
split_
on_
execution_time
(
self
,
heuristic
:
str
=
"
graph_color
"
,
coloring_strategy
:
str
=
"
saturation_largest_first
"
,
...
...
@@ -795,7 +795,7 @@ class ProcessCollection:
else
:
raise
ValueError
(
f
"
Invalid heuristic
'
{
heuristic
}
'"
)
def
split_ports
(
def
split_
on_
ports
(
self
,
heuristic
:
str
=
"
graph_color
"
,
read_ports
:
Optional
[
int
]
=
None
,
...
...
@@ -803,7 +803,9 @@ class ProcessCollection:
total_ports
:
Optional
[
int
]
=
None
,
)
->
Set
[
"
ProcessCollection
"
]:
"""
Split this process storage based on concurrent read/write times according to some heuristic.
Split this process storage based on concurrent read/write times according.
Different heurstic methods can be used.
Parameters
----------
...
...
@@ -963,6 +965,7 @@ class ProcessCollection:
def
left_edge_cell_assignment
(
self
)
->
Dict
[
int
,
"
ProcessCollection
"
]:
"""
Perform cell assignment of the processes in this collection using the left-edge algorithm.
Two or more processes can share a single cell if, and only if, they have no overlaping time alive.
Returns
...
...
@@ -1112,18 +1115,22 @@ class ProcessCollection:
input_sync
=
input_sync
,
)
def
split_on_length
(
self
,
length
:
int
=
0
):
def
split_on_length
(
self
,
length
:
int
=
0
)
->
Tuple
[
"
ProcessCollection
"
,
"
ProcessCollection
"
]:
"""
Split
the current ProcessCollection
into two new ProcessCollection based on exec
t
uion time length.
Split into two new ProcessCollection
s
based on execu
t
ion time length.
Parameters
----------
length : int, default: 0
The execution time length to split on. Length is inclusive for the smaller collection.
The execution time length to split on. Length is inclusive for the smaller
collection.
Returns
-------
A tuple of two ProcessCollections, one with short than or equal execution times and one with greater execution times.
A tuple of two ProcessCollections, one with shorter than or equal execution
times and one with longer execution times.
"""
short
=
set
()
long
=
set
()
...
...
This diff is collapsed.
Click to expand it.
test/test_architecture.py
+
8
−
10
View file @
4d596b1c
from
itertools
import
chain
from
typing
import
List
,
Set
,
cast
from
typing
import
List
,
cast
import
matplotlib.pyplot
as
plt
import
pytest
from
b_asic.architecture
import
Architecture
,
Memory
,
ProcessingElement
...
...
@@ -9,7 +8,6 @@ from b_asic.core_operations import Addition, ConstantMultiplication
from
b_asic.process
import
MemoryVariable
,
OperatorProcess
from
b_asic.resources
import
ProcessCollection
from
b_asic.schedule
import
Schedule
from
b_asic.signal_flow_graph
import
SFG
from
b_asic.special_operations
import
Input
,
Output
...
...
@@ -32,10 +30,10 @@ def test_extract_processing_elements(schedule_direct_form_iir_lp_filter: Schedul
operations
=
schedule_direct_form_iir_lp_filter
.
get_operations
()
# Split into new process collections on overlapping execution time
adders
=
operations
.
get_by_type_name
(
Addition
.
type_name
()).
split_execution_time
()
adders
=
operations
.
get_by_type_name
(
Addition
.
type_name
()).
split_
on_
execution_time
()
const_mults
=
operations
.
get_by_type_name
(
ConstantMultiplication
.
type_name
()
).
split_execution_time
()
).
split_
on_
execution_time
()
# List of ProcessingElements
processing_elements
:
List
[
ProcessingElement
]
=
[]
...
...
@@ -69,15 +67,15 @@ def test_architecture(schedule_direct_form_iir_lp_filter: Schedule):
operations
=
schedule_direct_form_iir_lp_filter
.
get_operations
()
# Split operations further into chunks
adders
=
operations
.
get_by_type_name
(
Addition
.
type_name
()).
split_execution_time
()
adders
=
operations
.
get_by_type_name
(
Addition
.
type_name
()).
split_
on_
execution_time
()
assert
len
(
adders
)
==
1
const_mults
=
operations
.
get_by_type_name
(
ConstantMultiplication
.
type_name
()
).
split_execution_time
()
).
split_
on_
execution_time
()
assert
len
(
const_mults
)
==
1
inputs
=
operations
.
get_by_type_name
(
Input
.
type_name
()).
split_execution_time
()
inputs
=
operations
.
get_by_type_name
(
Input
.
type_name
()).
split_
on_
execution_time
()
assert
len
(
inputs
)
==
1
outputs
=
operations
.
get_by_type_name
(
Output
.
type_name
()).
split_execution_time
()
outputs
=
operations
.
get_by_type_name
(
Output
.
type_name
()).
split_
on_
execution_time
()
assert
len
(
outputs
)
==
1
# Create necessary processing elements
...
...
@@ -93,7 +91,7 @@ def test_architecture(schedule_direct_form_iir_lp_filter: Schedule):
# Create Memories from the memory variables
memories
:
List
[
Memory
]
=
[
Memory
(
pc
)
for
pc
in
mvs
.
split_ports
(
read_ports
=
1
,
write_ports
=
1
)
Memory
(
pc
)
for
pc
in
mvs
.
split_
on_
ports
(
read_ports
=
1
,
write_ports
=
1
)
]
assert
len
(
memories
)
==
1
for
i
,
memory
in
enumerate
(
memories
):
...
...
This diff is collapsed.
Click to expand it.
test/test_resources.py
+
4
−
4
View file @
4d596b1c
...
...
@@ -27,7 +27,7 @@ class TestProcessCollectionPlainMemoryVariable:
return
fig
def
test_split_memory_variable
(
self
,
simple_collection
:
ProcessCollection
):
collection_split
=
simple_collection
.
split_ports
(
collection_split
=
simple_collection
.
split_
on_
ports
(
heuristic
=
"
graph_color
"
,
read_ports
=
1
,
write_ports
=
1
,
total_ports
=
2
)
assert
len
(
collection_split
)
==
3
...
...
@@ -113,15 +113,15 @@ class TestProcessCollectionPlainMemoryVariable:
def
test_interleaver_issue175
(
self
):
with
open
(
'
test/fixtures/interleaver-two-port-issue175.p
'
,
'
rb
'
)
as
f
:
interleaver_collection
:
ProcessCollection
=
pickle
.
load
(
f
)
assert
len
(
interleaver_collection
.
split_ports
(
total_ports
=
1
))
==
2
assert
len
(
interleaver_collection
.
split_
on_
ports
(
total_ports
=
1
))
==
2
def
test_generate_random_interleaver
(
self
):
for
_
in
range
(
10
):
for
size
in
range
(
5
,
20
,
5
):
collection
=
generate_random_interleaver
(
size
)
assert
len
(
collection
.
split_ports
(
read_ports
=
1
,
write_ports
=
1
))
==
1
assert
len
(
collection
.
split_
on_
ports
(
read_ports
=
1
,
write_ports
=
1
))
==
1
if
any
(
var
.
execution_time
for
var
in
collection
.
collection
):
assert
len
(
collection
.
split_ports
(
total_ports
=
1
))
==
2
assert
len
(
collection
.
split_
on_
ports
(
total_ports
=
1
))
==
2
def
test_len_process_collection
(
self
,
simple_collection
:
ProcessCollection
):
assert
len
(
simple_collection
)
==
7
...
...
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Click to expand it.
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