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B-ASIC - Better ASIC Toolbox
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Computer Engineering
B-ASIC - Better ASIC Toolbox
Commits
078ac59c
Commit
078ac59c
authored
2 years ago
by
Mikael Henriksson
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Add left_edge_cell_assignment method to ProcessCollection
parent
a56cb4e2
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!244
WIP: VHDL code generation for register and memory based storages
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b_asic/resources.py
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b_asic/resources.py
test/baseline/test_left_edge_cell_assignment.png
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test/baseline/test_left_edge_cell_assignment.png
test/test_resources.py
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test/test_resources.py
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