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Refactor constructor so that Input signals and Output signals are connected to...
Refactor constructor so that Input signals and Output signals are connected to ports before traversal is started, that way edge cases of empty SFG's are easily handled
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- test/fixtures/port.py 8 additions, 0 deletionstest/fixtures/port.py
- test/fixtures/signal_flow_graph.py 19 additions, 2 deletionstest/fixtures/signal_flow_graph.py
- test/test_inputport.py 29 additions, 37 deletionstest/test_inputport.py
- test/test_outputport.py 5 additions, 22 deletionstest/test_outputport.py
- test/test_print_sfg.py 0 additions, 46 deletionstest/test_print_sfg.py
- test/test_sfg.py 62 additions, 13 deletionstest/test_sfg.py
- test/test_signal.py 25 additions, 24 deletionstest/test_signal.py
- test/test_simulation.py 26 additions, 19 deletionstest/test_simulation.py
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