Sweep combinational designs (without clock).
We should be able to sweep combinational designs without sequential logic or any clock signal. To set delay targets for paths in Synopsys Design Compiler we can use set_max_delay
. For a general combinational design set_max_delay "${DELAY_CONSTRAINT}" -from [all_inputs] -to [all_outputs]
should do the trick. Note especially that [all_inputs]
is a list of all inputs to a design in Design Compiler and [all_outputs]
is a list of all outputs.
Extract from man set_max_delay
:
SYNTAX
status set_max_delay
delay_value
[-rise | -fall]
[-from from_list
| -rise_from rise_from_list
| -fall_from fall_from_list]
[-through through_list]
[-rise_through rise_through_list]
[-fall_through fall_through_list]
[-to to_list
| -rise_to rise_to_list
| -fall_to fall_to_list]
[-group_path group_name]
[-reset_path]
[-comment comment_string]
[-ignore_clock_latency]
ARGUMENTS
delay_value
Specifies the value of the desired maximum delay for paths
between start and end points. You must express delay_value in
the same units as the technology library used during optimiza-
tion. If a path startpoint is on a sequential device, clock
skew is included in the computed delay. If a path startpoint
has an input delay specified, that delay value is added to the
path delay. If a path endpoint is on a sequential device, clock
skew and library setup time are included in the computed delay.
If the endpoint has an output delay specified, that delay is
added into the path delay.
-rise | -fall
Specifies whether endpoint rising or falling delays are con-
strained. If you don't specify either, both rising and falling
delays are constrained.
-from from_list
Specifies a list of path startpoints (port, pin, clock, or cell
names) of the current design. If you specify a clock, all path
startpoints related to that clock are affected. If you specify
a cell name, one path startpoint on that cell is affected. All
paths from these startpoints to the endpoints in the to_list are
constrained to delay_value. If you don't specify to_list, all
paths from from_list are affected. This list cannot include
output ports. If you include more than one object, you must
enclose the objects in quotation marks ("") or braces ({}).
-to to_list
Specifies a list of path endpoints (port, clock, cell, or pin
names) of the current design. All paths to the endpoints in the
to_list are constrained to delay_value. If you don't specify a
from_list, all paths to to_list are affected. This list cannot
include input ports. If you include more than one object, you
must enclose the objects in quotation marks ("") or braces ({}).
If you specify a cell, one path endpoint on that cell is
affected. If you specify a clock, all path endpoints related to
that clock are affected.