Update report_references.bib

report_references.bib

@@ -182,11 +182,24 @@
   number    = {10},
   pages     = {1315--1319},
   month     = oct,
-  abstract  = {Along with the trend to reduce the power consumption of mobile devices, interface circuits such as analog-to-digital converters (ADCs) should also be designed to operate reliably at low supply voltages without compromising production yield. We present a high-fidelity audio {{$\Sigma$}}A ADC suitable for lowvoltage mobile applications, based on a new multi-bit quantizer. Its effective resolution is increased economically by augmenting an internal low-resolution quantizer with the proposed multi-rate noise-shaping technique. Fabricated in a 0.13-$\mu$m CMOS technology, our ADC uses 3.5 mW at 1.2 V, and achieved an A-weighted DR of 108.9 dB and a peak signal-to-noise and distortion ratio of 101.4 dB.},
+  abstract  = {n this work we present the design and implementa-tion of a decimationfilter for an audio range -modulator. Thearchitecture is based on a dual wordlength multiply-accumulate(MAC)  unit  to  handle  the  reduced  wordlength  of  the  input.Each stage is composed of FIRfilters which are mapped to theMAC unit. The design trade-offs and decisions for co-design ofarchitecture andfilters are discussed},
   doi       = {10.1109/TCSII.2018.2853189},
   keywords  = {analogue-digital conversion;CMOS integrated circuits;delta-sigma modulation;low-power electronics;quantisation (signal);sigma-delta modulation;mobile devices;interface circuits;analog-to-digital converters;low supply voltages;high-fidelity audio;ADC suitable;multibit quantizer;internal low-resolution quantizer;multirate noise-shaping technique;peak signal-to-noise;multirate noise-shaping quantizer;power consumption;low-voltage mobile applications;power 3.5 mW;voltage 1.2 V;noise figure 108.9 dB;noise figure 101.4 dB;Noise shaping;Adders;Quantization (signal);Signal resolution;Voltage measurement;Finite impulse response filters;Delays;CMOS;audio;mobile application;analog-to-digital conversion;multi-rate noise-shaping;quantizer},
-  publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
   timestamp = {2019.10.14},
 }
 
+@InProceedings{Lindahl2008,
+  author    = {Erik Lindahl and Oscar Gustafsson},
+  title     = {Architecture-Aware Design of a Decimation Filter Based on a Dual Wordlength Multiply-Accumulate Unit},
+  booktitle = {2008 42nd Asilomar Conference on Signals, Systems and Computers},
+  year      = {2008},
+  pages     = {1897--1901},
+  month     = oct,
+  abstract  = {n this work we present the design and implementa-tion of a decimationfilter for an audio range $\Sigma\Delta$-modulator. Thearchitecture is based on a dual wordlength multiply-accumulate(MAC)  unit  to  handle  the  reduced  wordlength  of  the  input.Each stage is composed of FIRfilters which are mapped to theMAC unit. The design trade-offs and decisions for co-design ofarchitecture andfilters are discussed},
+  doi       = {10.1109/ACSSC.2008.5074758},
+  publisher = {Institute of Electrical and Electronics Engineers ({IEEE})},
+  timestamp = {2020.01.13},
+}
+
 @Comment{jabref-meta: databaseType:bibtex;}
+