Added all files

ArduinoZeroTemplate.atsln

+
+Microsoft Visual Studio Solution File, Format Version 12.00
+# Atmel Studio Solution File, Format Version 11.00
+VisualStudioVersion = 14.0.23107.0
+MinimumVisualStudioVersion = 10.0.40219.1
+Project("{54F91283-7BC4-4236-8FF9-10F437C3AD48}") = "ArduinoZeroTemplate", "ArduinoZeroTemplate.cproj", "{DCE6C7E3-EE26-4D79-826B-08594B9AD897}"
+EndProject
+Global
+	GlobalSection(SolutionConfigurationPlatforms) = preSolution
+		Debug|ARM = Debug|ARM
+		Release|ARM = Release|ARM
+	EndGlobalSection
+	GlobalSection(ProjectConfigurationPlatforms) = postSolution
+		{DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Debug|ARM.ActiveCfg = Debug|ARM
+		{DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Debug|ARM.Build.0 = Debug|ARM
+		{DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Release|ARM.ActiveCfg = Release|ARM
+		{DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Release|ARM.Build.0 = Release|ARM
+	EndGlobalSection
+	GlobalSection(SolutionProperties) = preSolution
+		HideSolutionNode = FALSE
+	EndGlobalSection
+EndGlobal

ArduinoZeroTemplate.c

+/*
+ * ArduinoZeroTemplate.c
+ *
+ * Created: 2020-12-09 09:56:19
+ *  Author: ilosz01
+ */ 
+
+#include <asf.h>
+#include "ArduinoZeroTemplate.h"
+
+
+// Globala variabler
+// Instances for peripherals. One for each used.
+struct rtc_module rtc_instance_struct;
+//struct spi_module spi1_instance_struct;
+uint32_t t1ms_timer = 0;
+
+
+void ArduinoZeroTemplate(void)
+{
+	
+	while (true)
+	{
+
+	}// end while (true) infinite loop
+}// end ArduinoZeroTemplate
+
+void ArduinoZeroTemplateInit(void)
+{
+	// Temporary Configuration structures
+	struct rtc_count_config rtc_count_config_struct;
+	// If used: struct spi_config spi_config_struct;
+
+	// I/O
+		// Set pin input/output directions.
+		// For outputs, only the direction bit needs to be set.
+		// For inputs direction bit is already set but the input buffer must be enabled.
+		// Most pin functions is set through the PINCFG registers, one for each pin.
+
+		// Before writing to any port registers, enable constant input sampling on pins that shall be able to use the faster IOBUS.
+			// Note: Only Data Output Value, Data Input Value and Pin Direction registers can be accessed through IOBUS operation.
+			PORT_SET_CTRLSAMPLING(LED0_PIN_PORTNR,LED_0_PIN);
+			PORT_SET_CTRLSAMPLING(MY_OUTPUT_PIN_PORTNR,MY_OUTPUT_PIN);
+			PORT_SET_CTRLSAMPLING(MY_INPUT_PIN_PORTNR,MY_INPUT_PIN);
+
+		// Configure output pins
+			// To in all circumstances avoid glitches, set the default value of the pin before setting the direction. 
+			PORT_CLR_PIN(LED0_PIN_PORTNR,LED_0_PIN);							// LED
+			PORT_OUTPUT_PIN(LED0_PIN_PORTNR,LED_0_PIN);
+//			PORT_SET_PIN(MY_OUTPUT_PIN_PORTNR,MY_OUTPUT_PIN)			// MY_OUTPUT
+//			PORT_OUTPUT_PIN(MY_OUTPUT_PIN_PORTNR,MY_OUTPUT_PIN);
+
+		// Configure input pins
+			// All IN-buffers for pins used as inputs must be enabled. This is controlled through the PINCFG.INEN bit
+			PORT_INPUT_PIN(MY_INPUT_PIN_PORTNR,MY_INPUT_PIN);		// MY_INPUT
+			PORT_INPUT_PIN_EN(MY_INPUT_PIN_PORTNR,MY_INPUT_PIN);
+
+	// End I/O configuration
+
+	// RTC
+		// Time is measured by saving start time and then compare desired time with current time.
+		rtc_count_get_config_defaults(&rtc_count_config_struct);
+		// Clock source is hardcoded to GCLK_2 in rtc_count_init and set to prescaler of 1 in Channel8ForceClocks.h
+		rtc_count_config_struct.mode = RTC_COUNT_MODE_32BIT;
+		rtc_count_config_struct.prescaler = RTC_COUNT_PRESCALER_DIV_4;	// 32kHz/1/4 ~ 12,2 s
+		rtc_count_config_struct.clear_on_match = false;
+		//rtc_count_config_struct.continuously_update = true;
+		//rtc_count_config_struct.enable_read_sync = true;
+		rtc_count_init(&rtc_instance_struct, RTC, &rtc_count_config_struct);
+		rtc_count_enable(&rtc_instance_struct);
+	
+	// USART 1
+		/* If used
+		// I/O does not need top be defined separately for USARTS. Is done automatically when defining the use (SPI) below.
+		port_get_config_defaults(&port_config_struct);
+		port_config_struct.direction  = PORT_PIN_DIR_OUTPUT;
+		port_pin_set_config(SCK, &port_config_struct);		// SCK, Mode 1. Normally low, trigg negative edge. CPOL=0, CPHA=1
+		port_pin_set_config(MOSI, &port_config_struct);
+		*/
+
+	// SPI
+		/* If used
+		spi_get_config_defaults(&spi_config_struct);
+		spi_config_struct.generator_source = GCLK_GENERATOR_3;
+		spi_config_struct.mode             = SPI_MODE_MASTER;
+		spi_config_struct.data_order       = SPI_DATA_ORDER_MSB;
+		spi_config_struct.transfer_mode    = SPI_TRANSFER_MODE_1;
+		spi_config_struct.mux_setting      = SPI_SIGNAL_MUX_SETTING_D;
+		spi_config_struct.character_size   = SPI_CHARACTER_SIZE_8BIT;
+		spi_config_struct.pinmux_pad0 = PINMUX_PA16C_SERCOM1_PAD0;
+		spi_config_struct.pinmux_pad1 = PINMUX_PA17C_SERCOM1_PAD1;
+		spi_config_struct.pinmux_pad2 = PINMUX_PA18C_SERCOM1_PAD2;	// Not used. Can it be ignored to leave open for other use?
+		spi_config_struct.pinmux_pad3 = PINMUX_PA19C_SERCOM1_PAD3;
+		spi_config_struct.mode_specific.master.baudrate = 2000000;
+		spi_init(&spi1_instance_struct, SERCOM1, &spi_config_struct);
+		spi_enable(&spi1_instance_struct);
+		*/
+
+} // end init
+
+
+void Update1msClock(void)
+{
+	// Create a 1 ms clock (0.9765625 ms)
+	// Note that the program will hang here a maximum of 400 s to synchronize the system clock to the slower RTC clock.
+	static uint32_t current_time;								// Counts in ticks of the RTC clock
+	static uint32_t	previous_time_1ms=0;				// Also counts in ticks of the RTC clock
+
+	current_time = rtc_count_get_count(&rtc_instance_struct);
+	if (current_time >= (previous_time_1ms + 8))		// That is 1 ms!
+	{
+		t1ms_timer++;	// Increase our 1 ms clock
+		previous_time_1ms = current_time;				// Remember the RTC time of the 1 ms tick
+	}
+} // end Create1msClock
+

ArduinoZeroTemplate.componentinfo.xml

+<?xml version="1.0" encoding="utf-8"?>
+<Store xmlns:i="http://www.w3.org/2001/XMLSchema-instance" xmlns="AtmelPackComponentManagement">
+	<ProjectComponents />
+</Store>
\ No newline at end of file

ArduinoZeroTemplate.h

+/*
+ * ArduinoZeroTemplate.h
+ *
+ * Created: 2020-12-09 09:57:03
+ *  Author: ilosz01
+ */ 
+
+#ifndef ARDUINOZEROTEMPLATE_H_
+#define ARDUINOZEROTEMPLATE_H_
+
+/* Pin mapping
+
+Hardware:
+	Crystal:
+		PA00
+		PA01
+
+	USB:
+		PA18
+		PA24
+		PA25
+
+	Micro SD:
+		PA12
+		PA13
+		PA14
+		PA15
+		PA27
+
+	LED:
+		PB08
+
+	VBatt:
+		PB09
+
+	I2C: To SM05B
+		PA08 - SERCOM2/Pad[0]/I2C_SDA. Has pull-up "DNP"
+		PA09 - SERCOM2/Pad[1]/I2C_SCL. Has pull-up "DNP"
+		PA21
+
+	Crypto:
+		PA08 (I2C)
+		PA09 (I2C)
+
+	Not connected:
+		PA28
+	
+	Debug:
+		PA30 - SWCK
+		PA31 - SWDIO
+		Pin 40 - Reset
+
+Available for user
+		DAC0:
+		(J4-2)	PA02 - Vout
+		(J4-1)	PA03 - VrefA
+
+		USART 0: Free
+		(J4-5)	PA04 - SERCOM0/Pad[0] - AIN4 - Reserved for RTX (out)
+		(J4-6)	PA05 - SERCOM0/Pad[1] - AIN5 - Reserved for CTS (in)
+		(J4-7)	PA06 - SERCOM0/Pad[2] - AIN6 - TX (out)
+		(J4-8)	PA07 - SERCOM0/Pad[3] - AIN7 - RX (in)
+
+		USART 1:	Prefer to used for SPI to external components
+		(J5-3)	PA16 - SERCOM1/Pad[0] - MOSI
+		(J5-4		PA17 - SERCOM1/Pad[1] - SCK
+						PA18                  - USB
+		(J5-5)	PA19 - SERCOM1/Pad[3] - MISO
+						// SPI pad combination is SPI_SIGNAL_MUX_SETTING_D
+
+		USART 2: Free
+		(J5-6)	PA08 - SERCOM2/Pad[0] - I2C_SDA (J7), pull-up "DNP"
+		(J5-7)	PA09 - SERCOM2/Pad[1] - I2C_SCL (J7), pull-up "DNP"
+		(J4-11)	PA10 - SERCOM2/Pad[2]
+		(J4-12)	PA11 - SERCOM2/Pad[3]
+
+		USART 3: Used for USB to play with the USB to PC
+						// If used for USB: (PA24 and PA254 is in this case free)
+		(J4-9)	PA22 - SERCOM3/Pad[0]
+		(J4-10)	PA23 - SERCOM3/Pad[1]
+						PA24 - SERCOM3/Pad[2] - USB. Only ESD-protected
+						PA25 - SERCOM3/Pad[3] - USB. Only ESD-protected
+						// If used for UART:
+		(J4-9)	PA22 - SERCOM5/Pad[0] - Reserved for RTX (out)
+		(J4-10)	PA23 - SERCOM5/Pad[1] - Reserved for CTS (in)
+		(J5-9)	PB22 - SERCOM5/Pad[2] - TX (out)
+		(J5-8)	PB23 - SERCOM5/Pad[3] - RX (in)
+
+		SERCOM4 can not be used on Arduino Zero.
+		SERCOM5 can not be used on Arduino Zero.
+
+		Free:
+		(J4-3)	PB02 - AIN10
+		(J4-4)	PB03 - AIN11
+		(J5-1)	PA20 - TCC0-W6
+		(J5-2)	PA21 - TCC0-W7
+		(J4-13)	PB10 - TCC0-W4
+		(J4-14)	PB11 - TCC0-W5
+*/
+
+// Macros for writing to I/O:
+	// Note: Only Data Output Value, Data Input Value and Pin Direction registers can be accessed through IOBUS operation.
+	// putting port to a variable in advance is faster than reading from array
+	// PORT_IOBUS is faster that PORT. Especially if compiler optimizations are enabled.
+	// Read more here about writing to ports:
+	// https://electronics.stackexchange.com/questions/139117/atmels-arm-programming-without-asf
+	// And here: https://community.atmel.com/forum/getting-started-arm-3
+	#define PORT_SET_PIN(port,port_pin)			PORT_IOBUS->Group[port].OUTSET.reg = port_pin			// Set to 1; Time with 40MHz is 190nsec
+//	#define PORT_SET_PIN(portnr,pin)				PORT_IOBUS->Group[portnr].OUTSET.reg = pin			// Set to 1; Time with 40MHz is 190nsec
+	#define PORT_CLR_PIN(portnr,pin)				PORT_IOBUS->Group[portnr].OUTCLR.reg = pin			// Set to 0
+	#define PORT_TOGGLE_PIN(portnr,pin)			PORT_IOBUS->Group[portnr].OUTTGL.reg = pin			// Toggle pin
+	#define PORT_OUTPUT_PIN(portnr,pin)			PORT_IOBUS->Group[portnr].DIRSET.reg =  pin			// port.DIRSET.reg = pin			// Set pin to output
+	#define PORT_INPUT_PIN(portnr,pin)			PORT_IOBUS->Group[portnr].DIRCLR.reg =  pin			// port.DIRCLR.reg = pin			// Set pin to input
+ 	#define PORT_INPUT_PIN_EN(portnr,pin)		PORT->Group[portnr].PINCFG[pin].bit.INEN = 1
+	#define PORT_READ_PIN(portnr,pin)				PORT_IOBUS->Group[portnr].IN[pin]
+	#define PORT_READ(portnr)								PORT->Group[portnr].IN.reg
+	#define PORT_SET_CTRLSAMPLING(portnr,pin)	PORT->Group[portnr].CTRL.reg |= pin;
+	#define PORT_CLR_CTRLSAMPLING(portnr,pin)	PORT->Group[portnr].CTRL.reg &= ~pin;
+
+// Other register fiddling: #define bitwrite	SYSCTRL->VREG.bit.RUNSTDBY = 1
+
+// Definitions
+	
+	// I/O
+		// Definitions used for the pin group numbers needed if using the faster IOBUS I/O method. (Can be used for normal PORT as well)
+		// Group number for PORTA and PORTB
+		#define PORTA_NR						0
+		#define PORTB_NR						1
+
+		#define LED_0_PIN							PORT_PB08			// LED
+		#define LED0_PIN_PORTNR				PORTB_NR
+
+		#define MY_OUTPUT_PIN					PORT_PA20			// MY_OUTPUT
+		#define MY_OUTPUT_PIN_PORTNR	PORTA_NR
+
+		#define MY_INPUT_PIN					PORT_PB02			// MY_INPUT
+		#define MY_INPUT_PIN_PORTNR		PORTB_NR
+
+		// And so on for all pins...
+
+/* SPI if used
+	#define SCK				PIN_PA17
+	#define MOSI			PIN_PA16
+	#define MISO			PIN_PA19
+*/
+
+// Functions
+void ArduinoZeroTemplateInit(void);
+void ArduinoZeroTemplate(void);
+void Update1msClock(void);
+
+
+// Put any typedefs here
+
+#endif /* ARDUINOZEROTEMPLATE_H_ */
\ No newline at end of file

ArduinoZeroTemplateClocks.h

+/*
+ * ArduinoZeroemplateClocks.h
+ *
+ * Created: 2020-12-09 09:50:42
+ *  Author: ilosz01
+ */ 
+
+
+// System clock bus configuration 
+#  define CONF_CLOCK_CPU_CLOCK_FAILURE_DETECT     false
+#  define CONF_CLOCK_FLASH_WAIT_STATES            1		// Changed from 0 to 1 if using DFLL clock > 24 MHz.
+#  define CONF_CLOCK_CPU_DIVIDER                  SYSTEM_MAIN_CLOCK_DIV_1
+#  define CONF_CLOCK_APBA_DIVIDER                 SYSTEM_MAIN_CLOCK_DIV_1
+#  define CONF_CLOCK_APBB_DIVIDER                 SYSTEM_MAIN_CLOCK_DIV_1
+#  define CONF_CLOCK_APBC_DIVIDER                 SYSTEM_MAIN_CLOCK_DIV_1
+
+// SYSTEM_CLOCK_SOURCE_OSC8M configuration - Internal 8MHz oscillator 
+#  define CONF_CLOCK_OSC8M_PRESCALER              SYSTEM_OSC8M_DIV_1
+#  define CONF_CLOCK_OSC8M_ON_DEMAND              true
+#  define CONF_CLOCK_OSC8M_RUN_IN_STANDBY         false
+
+// SYSTEM_CLOCK_SOURCE_XOSC configuration - External clock/oscillator 
+#  define CONF_CLOCK_XOSC_ENABLE                  false
+#  define CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL        SYSTEM_CLOCK_EXTERNAL_CRYSTAL
+#  define CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY      12000000UL
+#  define CONF_CLOCK_XOSC_STARTUP_TIME            SYSTEM_XOSC_STARTUP_32768
+#  define CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL       true
+#  define CONF_CLOCK_XOSC_ON_DEMAND               true
+#  define CONF_CLOCK_XOSC_RUN_IN_STANDBY          false
+
+// SYSTEM_CLOCK_SOURCE_XOSC32K configuration - External 32KHz crystal/clock oscillator 
+#  define CONF_CLOCK_XOSC32K_ENABLE               true	// Used to synchronize DFLL. (Can be used for low power clock also).
+#  define CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL     SYSTEM_CLOCK_EXTERNAL_CRYSTAL
+#  define CONF_CLOCK_XOSC32K_STARTUP_TIME         SYSTEM_XOSC32K_STARTUP_65536
+#  define CONF_CLOCK_XOSC32K_AUTO_AMPLITUDE_CONTROL  false
+#  define CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT    false
+#  define CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT  true
+#  define CONF_CLOCK_XOSC32K_ON_DEMAND            true
+#  define CONF_CLOCK_XOSC32K_RUN_IN_STANDBY       false
+
+// SYSTEM_CLOCK_SOURCE_OSC32K configuration - Internal 32KHz oscillator 
+#  define CONF_CLOCK_OSC32K_ENABLE                false
+#  define CONF_CLOCK_OSC32K_STARTUP_TIME          SYSTEM_OSC32K_STARTUP_130
+#  define CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT    true
+#  define CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT   true
+#  define CONF_CLOCK_OSC32K_ON_DEMAND             true
+#  define CONF_CLOCK_OSC32K_RUN_IN_STANDBY        false
+
+// SYSTEM_CLOCK_SOURCE_DFLL configuration - Digital Frequency Locked Loop 
+#  define CONF_CLOCK_DFLL_ENABLE                  true
+#  define CONF_CLOCK_DFLL_LOOP_MODE               SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN
+#  define CONF_CLOCK_DFLL_ON_DEMAND               false
+
+// DFLL open loop mode configuration 
+#  define CONF_CLOCK_DFLL_FINE_VALUE              (512)
+
+// DFLL closed loop mode configuration 
+#  define CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR   GCLK_GENERATOR_1
+#  define CONF_CLOCK_DFLL_MULTIPLY_FACTOR         (48000000 / 32768)
+#  define CONF_CLOCK_DFLL_QUICK_LOCK              true
+#  define CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK   true
+#  define CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP     true
+#  define CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE      true
+#  define CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE    (0x1f / 4)
+#  define CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE      (0xff / 4)
+
+// SYSTEM_CLOCK_SOURCE_DPLL configuration - Digital Phase-Locked Loop 
+#  define CONF_CLOCK_DPLL_ENABLE                  true
+#  define CONF_CLOCK_DPLL_ON_DEMAND               true
+#  define CONF_CLOCK_DPLL_RUN_IN_STANDBY          false
+#  define CONF_CLOCK_DPLL_LOCK_BYPASS             false
+#  define CONF_CLOCK_DPLL_WAKE_UP_FAST            false
+#  define CONF_CLOCK_DPLL_LOW_POWER_ENABLE        false
+
+#  define CONF_CLOCK_DPLL_LOCK_TIME               SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT
+#  define CONF_CLOCK_DPLL_REFERENCE_CLOCK         SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC32K
+#  define CONF_CLOCK_DPLL_FILTER                  SYSTEM_CLOCK_SOURCE_DPLL_FILTER_DEFAULT
+
+#  define CONF_CLOCK_DPLL_REFERENCE_FREQUENCY     32768
+#  define CONF_CLOCK_DPLL_REFERENCE_DIVIDER       1
+#  define CONF_CLOCK_DPLL_OUTPUT_FREQUENCY        48000000
+
+// DPLL GCLK reference configuration 
+#  define CONF_CLOCK_DPLL_REFERENCE_GCLK_GENERATOR  GCLK_GENERATOR_1
+// DPLL GCLK lock timer configuration 
+#  define CONF_CLOCK_DPLL_LOCK_GCLK_GENERATOR     GCLK_GENERATOR_1
+
+// Set this to true to configure the GCLK when running clocks_init. If set to
+// * false, none of the GCLK generators will be configured in clocks_init(). 
+#  define CONF_CLOCK_CONFIGURE_GCLK               true
+
+
+/* Configure GCLK generator 0 (Main Clock) */
+#  define CONF_CLOCK_GCLK_0_ENABLE                true
+#  define CONF_CLOCK_GCLK_0_RUN_IN_STANDBY        false
+#  define CONF_CLOCK_GCLK_0_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_DPLL	//	SYSTEM_CLOCK_SOURCE_OSC8M
+#  define CONF_CLOCK_GCLK_0_PRESCALER             1
+#  define CONF_CLOCK_GCLK_0_OUTPUT_ENABLE         false
+
+/* Configure GCLK generator 1 (DFLL Clock) */
+#  define CONF_CLOCK_GCLK_1_ENABLE                true
+#  define CONF_CLOCK_GCLK_1_RUN_IN_STANDBY        false
+#  define CONF_CLOCK_GCLK_1_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_XOSC32K
+#  define CONF_CLOCK_GCLK_1_PRESCALER             1
+#  define CONF_CLOCK_GCLK_1_OUTPUT_ENABLE         false
+
+/* Configure GCLK generator 2 (RTC) */
+#  define CONF_CLOCK_GCLK_2_ENABLE                true
+#  define CONF_CLOCK_GCLK_2_RUN_IN_STANDBY        true
+#  define CONF_CLOCK_GCLK_2_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_XOSC32K
+#  define CONF_CLOCK_GCLK_2_PRESCALER             1
+#  define CONF_CLOCK_GCLK_2_OUTPUT_ENABLE         false
+
+/* Configure GCLK generator 3 (SPI Clock) */
+#  define CONF_CLOCK_GCLK_3_ENABLE                true
+#  define CONF_CLOCK_GCLK_3_RUN_IN_STANDBY        false
+#  define CONF_CLOCK_GCLK_3_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_OSC8M //SYSTEM_CLOCK_SOURCE_DPLL	//SYSTEM_CLOCK_SOURCE_OSC8M
+#  define CONF_CLOCK_GCLK_3_PRESCALER             1
+#  define CONF_CLOCK_GCLK_3_OUTPUT_ENABLE         false
+
+/* Configure GCLK generator */
+#  define CONF_CLOCK_GCLK_4_ENABLE                false
+#  define CONF_CLOCK_GCLK_4_RUN_IN_STANDBY        false
+#  define CONF_CLOCK_GCLK_4_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_OSC8M
+#  define CONF_CLOCK_GCLK_4_PRESCALER             1
+#  define CONF_CLOCK_GCLK_4_OUTPUT_ENABLE         false
+
+/* Configure GCLK generator 5 */
+#  define CONF_CLOCK_GCLK_5_ENABLE                false
+#  define CONF_CLOCK_GCLK_5_RUN_IN_STANDBY        false
+#  define CONF_CLOCK_GCLK_5_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_OSC8M
+#  define CONF_CLOCK_GCLK_5_PRESCALER             1
+#  define CONF_CLOCK_GCLK_5_OUTPUT_ENABLE         false
+
+/* Configure GCLK generator 6 */
+#  define CONF_CLOCK_GCLK_6_ENABLE                false
+#  define CONF_CLOCK_GCLK_6_RUN_IN_STANDBY        false
+#  define CONF_CLOCK_GCLK_6_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_OSC8M
+#  define CONF_CLOCK_GCLK_6_PRESCALER             1
+#  define CONF_CLOCK_GCLK_6_OUTPUT_ENABLE         false
+
+/* Configure GCLK generator 7 */
+#  define CONF_CLOCK_GCLK_7_ENABLE                false
+#  define CONF_CLOCK_GCLK_7_RUN_IN_STANDBY        false
+#  define CONF_CLOCK_GCLK_7_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_OSC8M
+#  define CONF_CLOCK_GCLK_7_PRESCALER             1
+#  define CONF_CLOCK_GCLK_7_OUTPUT_ENABLE         false
+
+/* Configure GCLK generator 8 */
+#  define CONF_CLOCK_GCLK_8_ENABLE                false
+#  define CONF_CLOCK_GCLK_8_RUN_IN_STANDBY        false
+#  define CONF_CLOCK_GCLK_8_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_OSC8M
+#  define CONF_CLOCK_GCLK_8_PRESCALER             1
+#  define CONF_CLOCK_GCLK_8_OUTPUT_ENABLE         false
+

src/ASF/common/utils/interrupt.h

+/**
+ * \file
+ *
+ * \brief Global interrupt management for 8- and 32-bit AVR
+ *
+ * Copyright (c) 2010-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+#ifndef UTILS_INTERRUPT_H
+#define UTILS_INTERRUPT_H
+
+#include <parts.h>
+
+#if XMEGA || MEGA
+#  include "interrupt/interrupt_avr8.h"
+#elif UC3
+#  include "interrupt/interrupt_avr32.h"
+#elif SAM || SAMB
+#  include "interrupt/interrupt_sam_nvic.h"
+#else
+#  error Unsupported device.
+#endif
+
+/**
+ * \defgroup interrupt_group Global interrupt management
+ *
+ * This is a driver for global enabling and disabling of interrupts.
+ *
+ * @{
+ */
+
+#if defined(__DOXYGEN__)
+/**
+ * \def CONFIG_INTERRUPT_FORCE_INTC
+ * \brief Force usage of the ASF INTC driver
+ *
+ * Predefine this symbol when preprocessing to force the use of the ASF INTC driver.
+ * This is useful to ensure compatibility across compilers and shall be used only when required
+ * by the application needs.
+ */
+#  define CONFIG_INTERRUPT_FORCE_INTC
+#endif
+
+//! \name Global interrupt flags
+//@{
+/**
+ * \typedef irqflags_t
+ * \brief Type used for holding state of interrupt flag
+ */
+
+/**
+ * \def cpu_irq_enable
+ * \brief Enable interrupts globally
+ */
+
+/**
+ * \def cpu_irq_disable
+ * \brief Disable interrupts globally
+ */
+
+/**
+ * \fn irqflags_t cpu_irq_save(void)
+ * \brief Get and clear the global interrupt flags
+ *
+ * Use in conjunction with \ref cpu_irq_restore.
+ *
+ * \return Current state of interrupt flags.
+ *
+ * \note This function leaves interrupts disabled.
+ */
+
+/**
+ * \fn void cpu_irq_restore(irqflags_t flags)
+ * \brief Restore global interrupt flags
+ *
+ * Use in conjunction with \ref cpu_irq_save.
+ *
+ * \param flags State to set interrupt flag to.
+ */
+
+/**
+ * \fn bool cpu_irq_is_enabled_flags(irqflags_t flags)
+ * \brief Check if interrupts are globally enabled in supplied flags
+ *
+ * \param flags Currents state of interrupt flags.
+ *
+ * \return True if interrupts are enabled.
+ */
+
+/**
+ * \def cpu_irq_is_enabled
+ * \brief Check if interrupts are globally enabled
+ *
+ * \return True if interrupts are enabled.
+ */
+//@}
+
+//! @}
+
+/**
+ * \ingroup interrupt_group
+ * \defgroup interrupt_deprecated_group Deprecated interrupt definitions
+ */
+
+#endif /* UTILS_INTERRUPT_H */

src/ASF/common/utils/interrupt/interrupt_sam_nvic.c

+/**
+ * \file
+ *
+ * \brief Global interrupt management for SAM D20, SAM3 and SAM4 (NVIC based)
+ *
+ * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#include "interrupt_sam_nvic.h"
+
+#if !defined(__DOXYGEN__)
+/* Deprecated - global flag to determine the global interrupt state. Required by
+ * QTouch library, however new applications should use cpu_irq_is_enabled()
+ * which probes the true global interrupt state from the CPU special registers.
+ */
+volatile bool g_interrupt_enabled = true;
+#endif
+
+void cpu_irq_enter_critical(void)
+{
+	if (cpu_irq_critical_section_counter == 0) {
+		if (cpu_irq_is_enabled()) {
+			cpu_irq_disable();
+			cpu_irq_prev_interrupt_state = true;
+		} else {
+			/* Make sure the to save the prev state as false */
+			cpu_irq_prev_interrupt_state = false;
+		}
+
+	}
+
+	cpu_irq_critical_section_counter++;
+}
+
+void cpu_irq_leave_critical(void)
+{
+	/* Check if the user is trying to leave a critical section when not in a critical section */
+	Assert(cpu_irq_critical_section_counter > 0);
+
+	cpu_irq_critical_section_counter--;
+
+	/* Only enable global interrupts when the counter reaches 0 and the state of the global interrupt flag
+	   was enabled when entering critical state */
+	if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
+		cpu_irq_enable();
+	}
+}
+

src/ASF/common/utils/interrupt/interrupt_sam_nvic.h

+/**
+ * \file
+ *
+ * \brief Global interrupt management for SAM D20, SAM3 and SAM4 (NVIC based)
+ *
+ * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#ifndef UTILS_INTERRUPT_INTERRUPT_H
+#define UTILS_INTERRUPT_INTERRUPT_H
+
+#include <compiler.h>
+#include <parts.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \weakgroup interrupt_group
+ *
+ * @{
+ */
+
+/**
+ * \name Interrupt Service Routine definition
+ *
+ * @{
+ */
+
+/**
+ * \brief Define service routine
+ *
+ * \note For NVIC devices the interrupt service routines are predefined to
+ *       add to vector table in binary generation, so there is no service
+ *       register at run time. The routine collections are in exceptions.h.
+ *
+ * Usage:
+ * \code
+	ISR(foo_irq_handler)
+	{
+	     // Function definition
+	     ...
+	}
+\endcode
+ *
+ * \param func Name for the function.
+ */
+#  define ISR(func)   \
+	void func (void)
+
+/**
+ * \brief Initialize interrupt vectors
+ *
+ * For NVIC the interrupt vectors are put in vector table. So nothing
+ * to do to initialize them, except defined the vector function with
+ * right name.
+ *
+ * This must be called prior to \ref irq_register_handler.
+ */
+#  define irq_initialize_vectors()   \
+	do {                             \
+	} while(0)
+
+/**
+ * \brief Register handler for interrupt
+ *
+ * For NVIC the interrupt vectors are put in vector table. So nothing
+ * to do to register them, except defined the vector function with
+ * right name.
+ *
+ * Usage:
+ * \code
+	irq_initialize_vectors();
+	irq_register_handler(foo_irq_handler);
+\endcode
+ *
+ * \note The function \a func must be defined with the \ref ISR macro.
+ * \note The functions prototypes can be found in the device exception header
+ *       files (exceptions.h).
+ */
+#  define irq_register_handler(int_num, int_prio)                      \
+	NVIC_ClearPendingIRQ(    (IRQn_Type)int_num);                      \
+	NVIC_SetPriority(    (IRQn_Type)int_num, int_prio);                \
+	NVIC_EnableIRQ(      (IRQn_Type)int_num);                          \
+
+//@}
+
+#  define cpu_irq_enable()                     \
+	do {                                       \
+		g_interrupt_enabled = true;            \
+		__DMB();                               \
+		__enable_irq();                        \
+	} while (0)
+#  define cpu_irq_disable()                    \
+	do {                                       \
+		__disable_irq();                       \
+		__DMB();                               \
+		g_interrupt_enabled = false;           \
+	} while (0)
+
+typedef uint32_t irqflags_t;
+
+#if !defined(__DOXYGEN__)
+extern volatile bool g_interrupt_enabled;
+#endif
+
+#define cpu_irq_is_enabled()    (__get_PRIMASK() == 0)
+
+static volatile uint32_t cpu_irq_critical_section_counter;
+static volatile bool     cpu_irq_prev_interrupt_state;
+
+static inline irqflags_t cpu_irq_save(void)
+{
+	volatile irqflags_t flags = cpu_irq_is_enabled();
+	cpu_irq_disable();
+	return flags;
+}
+
+static inline bool cpu_irq_is_enabled_flags(irqflags_t flags)
+{
+	return (flags);
+}
+
+static inline void cpu_irq_restore(irqflags_t flags)
+{
+	if (cpu_irq_is_enabled_flags(flags))
+		cpu_irq_enable();
+}
+
+void cpu_irq_enter_critical(void);
+void cpu_irq_leave_critical(void);
+
+/**
+ * \weakgroup interrupt_deprecated_group
+ * @{
+ */
+
+#define Enable_global_interrupt()            cpu_irq_enable()
+#define Disable_global_interrupt()           cpu_irq_disable()
+#define Is_global_interrupt_enabled()        cpu_irq_is_enabled()
+
+//@}
+
+//@}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* UTILS_INTERRUPT_INTERRUPT_H */

src/ASF/common2/boards/user_board/init.c

+/**
+ * \file
+ *
+ * \brief User board initialization template
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#include <asf.h>
+#include <board.h>
+#include <conf_board.h>
+
+#if defined(__GNUC__)
+void board_init(void) WEAK __attribute__((alias("system_board_init")));
+#elif defined(__ICCARM__)
+void board_init(void);
+#  pragma weak board_init=system_board_init
+#endif
+
+void system_board_init(void)
+{
+	/* This function is meant to contain board-specific initialization code
+	 * for, e.g., the I/O pins. The initialization can rely on application-
+	 * specific board configuration, found in conf_board.h.
+	 */
+}
\ No newline at end of file

src/ASF/common2/boards/user_board/user_board.h

+/**
+ * \file
+ *
+ * \brief User board definition template
+ *
+ */
+
+ /* This file is intended to contain definitions and configuration details for
+ * features and devices that are available on the board, e.g., frequency and
+ * startup time for an external crystal, external memory devices, LED and USART
+ * pins.
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+
+#ifndef USER_BOARD_H
+#define USER_BOARD_H
+
+#include <conf_board.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \ingroup group_common_boards
+ * \defgroup user_board_group User board
+ *
+ * @{
+ */
+
+void system_board_init(void);
+
+/** Name string macro */
+#define BOARD_NAME                "USER_BOARD"
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // USER_BOARD_H

src/ASF/sam0/drivers/dac/dac.h

+/**
+ * \file
+ *
+ * \brief SAM Peripheral Digital-to-Analog Converter Driver
+ *
+ * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+#ifndef DAC_H_INCLUDED
+#define DAC_H_INCLUDED
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <compiler.h>
+#include <clock.h>
+#include <gclk.h>
+
+/**
+ * \addtogroup asfdoc_sam0_dac_group
+ *
+ * @{
+ */
+
+/**
+ * Define DAC features set according to different device families.
+ * @{
+ */
+#if (SAMD21 || SAMD10 || SAMD11 || SAMDA1 || SAMHA1 || SAMHA0)
+#  define FEATURE_DAC_DATABUF_WRITE_PROTECTION
+#endif
+/**@}*/
+
+#ifndef DAC_TIMEOUT
+#  define DAC_TIMEOUT 0xFFFF
+#endif
+
+#if DAC_CALLBACK_MODE == true
+#  include <system_interrupt.h>
+
+/** Forward definition of the device instance. */
+struct dac_module;
+
+#if !defined(__DOXYGEN__)
+extern struct dac_module *_dac_instances[DAC_INST_NUM];
+#endif
+
+/** Type definition for a DAC module callback function. */
+typedef void (*dac_callback_t)(uint8_t channel);
+
+/** Enum for the possible callback types for the DAC module. */
+enum dac_callback {
+	/** Callback type for when a DAC channel data empty condition occurs
+	 *  (requires event triggered mode) */
+	DAC_CALLBACK_DATA_EMPTY,
+
+	/** Callback type for when a DAC channel data underrun condition occurs
+	 *  (requires event triggered mode) */
+	DAC_CALLBACK_DATA_UNDERRUN,
+
+	/** Callback type for when a DAC channel write buffer job complete (requires
+	 *  event triggered mode) */
+	DAC_CALLBACK_TRANSFER_COMPLETE,
+#if !defined(__DOXYGEN__)
+	DAC_CALLBACK_N,
+#endif
+};
+
+#endif
+
+#include <dac_feature.h>
+
+/**
+ * \name Configuration and Initialization
+ * @{
+ */
+
+bool dac_is_syncing(
+		struct dac_module *const dev_inst);
+
+void dac_get_config_defaults(
+		struct dac_config *const config);
+
+enum status_code dac_init(
+		struct dac_module *const dev_inst,
+		Dac *const module,
+		struct dac_config *const config);
+
+void dac_reset(
+		struct dac_module *const dev_inst);
+
+void dac_enable(
+		struct dac_module *const dev_inst);
+
+void dac_disable(
+		struct dac_module *const dev_inst);
+
+void dac_enable_events(
+		struct dac_module *const module_inst,
+		struct dac_events *const events);
+
+void dac_disable_events(
+		struct dac_module *const module_inst,
+		struct dac_events *const events);
+
+/** @} */
+
+/**
+ * \name Configuration and Initialization (Channel)
+ * @{
+ */
+
+void dac_chan_get_config_defaults(
+		struct dac_chan_config *const config);
+
+void dac_chan_set_config(
+		struct dac_module *const dev_inst,
+		const enum dac_channel channel,
+		struct dac_chan_config *const config);
+
+void dac_chan_enable(
+		struct dac_module *const dev_inst,
+		enum dac_channel channel);
+
+void dac_chan_disable(
+		struct dac_module *const dev_inst,
+		enum dac_channel channel);
+
+/** @} */
+
+/**
+ * \name Channel Data Management
+ * @{
+ */
+
+enum status_code dac_chan_write(
+		struct dac_module *const dev_inst,
+		enum dac_channel channel,
+		const uint16_t data);
+
+enum status_code dac_chan_write_buffer_wait(
+		struct dac_module *const module_inst,
+		enum dac_channel channel,
+		uint16_t *buffer,
+		uint32_t length);
+
+/** @} */
+
+/**
+ * \name Status Management
+ * @{
+ */
+uint32_t dac_get_status(
+		struct dac_module *const module_inst);
+void dac_clear_status(
+		struct dac_module *const module_inst,
+		uint32_t status_flags);
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+
+
+#endif /* DAC_H_INCLUDED */

src/ASF/sam0/drivers/port/port.c

+/**
+ * \file
+ *
+ * \brief SAM GPIO Port Driver
+ *
+ * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */
+#include <port.h>
+
+/**
+ *  \brief Writes a Port pin configuration to the hardware module.
+ *
+ *  Writes out a given configuration of a Port pin configuration to the hardware
+ *  module.
+ *
+ *  \note If the pin direction is set as an output, the pull-up/pull-down input
+ *        configuration setting is ignored.
+ *
+ *  \param[in] gpio_pin  Index of the GPIO pin to configure
+ *  \param[in] config    Configuration settings for the pin
+ */
+void port_pin_set_config(
+		const uint8_t gpio_pin,
+		const struct port_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(config);
+
+	struct system_pinmux_config pinmux_config;
+	system_pinmux_get_config_defaults(&pinmux_config);
+
+	pinmux_config.mux_position = SYSTEM_PINMUX_GPIO;
+	pinmux_config.direction    = (enum system_pinmux_pin_dir)config->direction;
+	pinmux_config.input_pull   = (enum system_pinmux_pin_pull)config->input_pull;
+	pinmux_config.powersave    = config->powersave;
+
+	system_pinmux_pin_set_config(gpio_pin, &pinmux_config);
+}
+
+/**
+ *  \brief Writes a Port group configuration group to the hardware module.
+ *
+ *  Writes out a given configuration of a Port group configuration to the
+ *  hardware module.
+ *
+ *  \note If the pin direction is set as an output, the pull-up/pull-down input
+ *        configuration setting is ignored.
+ *
+ *  \param[out] port    Base of the PORT module to write to
+ *  \param[in]  mask    Mask of the port pin(s) to configure
+ *  \param[in]  config  Configuration settings for the pin group
+ */
+void port_group_set_config(
+		PortGroup *const port,
+		const uint32_t mask,
+		const struct port_config *const config)
+{
+	/* Sanity check arguments */
+	Assert(port);
+	Assert(config);
+
+	struct system_pinmux_config pinmux_config;
+	system_pinmux_get_config_defaults(&pinmux_config);
+
+	pinmux_config.mux_position = SYSTEM_PINMUX_GPIO;
+	pinmux_config.direction    = (enum system_pinmux_pin_dir)config->direction;
+	pinmux_config.input_pull   = (enum system_pinmux_pin_pull)config->input_pull;
+	pinmux_config.powersave    = config->powersave;
+
+	system_pinmux_group_set_config(port, mask, &pinmux_config);
+}

src/ASF/sam0/drivers/port/quick_start/qs_port_basic.h

+/**
+ * \file
+ *
+ * \brief SAM GPIO Port Driver Quick Start
+ *
+ * Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/**
+ * \page asfdoc_sam0_port_basic_use_case Quick Start Guide for PORT - Basic
+ *
+ * In this use case, the PORT module is configured for:
+ *  \li One pin in input mode, with pull-up enabled
+ *  \li One pin in output mode
+ *
+ * This use case sets up the PORT to read the current state of a GPIO pin set as
+ * an input, and mirrors the opposite logical state on a pin configured as an
+ * output.
+ *
+ * \section asfdoc_sam0_port_basic_use_case_setup Setup
+ *
+ * \subsection asfdoc_sam0_port_basic_use_case_setup_prereq Prerequisites
+ * There are no special setup requirements for this use-case.
+ *
+ * \subsection asfdoc_sam0_port_basic_use_case_setup_code Code
+ * Copy-paste the following setup code to your user application:
+ * \snippet qs_port_basic.c setup
+ *
+ * Add to user application initialization (typically the start of \c main()):
+ * \snippet qs_port_basic.c setup_init
+ *
+ * \subsection asfdoc_sam0_port_basic_use_case_setup_flow Workflow
+ * -# Create a PORT module pin configuration struct, which can be filled out to
+ *    adjust the configuration of a single port pin.
+ *    \snippet qs_port_basic.c setup_1
+ * -# Initialize the pin configuration struct with the module's default values.
+ *    \snippet qs_port_basic.c setup_2
+ *    \note This should always be performed before using the configuration
+ *          struct to ensure that all values are initialized to known default
+ *          settings.
+ *
+ * -# Adjust the configuration struct to request an input pin.
+ *    \snippet qs_port_basic.c setup_3
+ * -# Configure push button pin with the initialized pin configuration struct, to enable
+ *    the input sampler on the pin.
+ *    \snippet qs_port_basic.c setup_4
+ * -# Adjust the configuration struct to request an output pin.
+ *    \snippet qs_port_basic.c setup_5
+ *    \note The existing configuration struct may be re-used, as long as any
+ *          values that have been altered from the default settings are taken
+ *          into account by the user application.
+ *
+ * -# Configure LED pin with the initialized pin configuration struct, to enable
+ *    the output driver on the pin.
+ *    \snippet qs_port_basic.c setup_6
+ *
+ * \section asfdoc_sam0_port_basic_use_case_use_main Use Case
+ *
+ * \subsection asfdoc_sam0_port_basic_use_case_code Code
+ * Copy-paste the following code to your user application:
+ * \snippet qs_port_basic.c main
+ *
+ * \subsection asfdoc_sam0_port_basic_use_case_flow Workflow
+ * -# Read in the current input sampler state of push button pin, which has been
+ *    configured as an input in the use-case setup code.
+ *    \snippet qs_port_basic.c main_1
+ * -# Write the inverted pin level state to LED pin, which has been configured as
+ *    an output in the use-case setup code.
+ *    \snippet qs_port_basic.c main_2
+ */
+/*
+ * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
+ */