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Commit 6cd68eea authored by Bengt Ragnemalm's avatar Bengt Ragnemalm
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More updates to macros.h

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......@@ -88,12 +88,14 @@ set several pins at once.
*/
#define GROUPNR(pin) (pin>>5)
#define PINMASK(pin) (1 << (pin & 31))
#define PINMASK_8_GROUP(pin) (0xFF << ( 8*((pin & 31)/8) )) // pin&32 => pin=0-32. Divide by 8 => pin=0-4. Skift FF up 8x that.
#define PINNR(pin) (pin & 31)
#define PINMASK(pin) (1 << (pin & 31)) // A mask there the bit position sets the pin accessed
#define PINMASK_8_GROUP(pin) (0xFF << ( 8*((pin & 31)/8) )) // Special for PORT_CLR_CTRLSAMPLING. pin&32 => pin=0-32. Divide by 8 => pin=0-4. Skift FF up 8x that.
#define PINNR(pin) (pin & 31) // A nr to access a pin register. Like 10 to access a register belonging to pin 10.
// Basic PORT registers. These are not defined with bitfields in ASF and can only be accessed word-wise.
// These registers can also can be accessed using IOBUS. (IOBUS only exist in Cortex M0+)
// GROUPNR sets which port register that is accessed
// PINMASK sets which pin (or pins but the PINMASK macro does only access one pin) in the port that is accessed
#define PORT_SET_PIN(pin) PORT->Group[GROUPNR(pin)].OUTSET.reg = PINMASK(pin)
#define PORT_CLR_PIN(pin) PORT->Group[GROUPNR(pin)].OUTCLR.reg = PINMASK(pin)
#define PORT_TOGGLE_PIN(pin) PORT->Group[GROUPNR(pin)].OUTTGL.reg = PINMASK(pin)
......@@ -115,18 +117,29 @@ set several pins at once.
#define PORT_IOB_READ_PIN1(pin) (PORT_IOBUS->Group[GROUPNR(pin)].IN.reg & PINMASK(pin)) >> (pin & 31) // Returns pin value 0 or 1.
#endif
// The remaining PORT registers. All of these have the individual bit names defined as bit fields.
// The remaining PORT registers of which there is only one register for the whole port (like above) but
// the register cannot be accessed using IOBUS.
// GROUPNR sets which port register that is accessed
// PINMASK sets which pin setting in the register that is to be accessed.
#define PORT_SET_CTRLSAMPLING(pin) PORT->Group[GROUPNR(pin)].CTRL.reg |= PINMASK(pin); // Enable continuous sampling of a pin group the pin belongs to. (Always in groups of 8)
// To disable continuous sampling, all eight bits/pins of that group must be cleared simultaneously. A special mask definition is used that will do that.
#define PORT_CLR_CTRLSAMPLING(pin) PORT->Group[GROUPNR(pin)].CTRL.reg &= ~PINMASK_8_GROUP(pin); // Remove continuous sampling of a pins group
// WRCONFIG must be handled with special handling and is therefore not defined here.
// The remaining PORT registers of which there is one register for each port pin.
// All of these have the individual bit names defined as bit fields.
// Therefore they can be accessed bitwise or as a word. These registers can not be accessed using IOBUS.
#define PORT_INPUT_PIN_EN(pin) PORT->Group[GROUPNR(pin)].PINCFG[PINNR(pin)].bit.INEN = 1 // Enable input buffer (needed to be able to read a pin)
#define PORT_SET_CTRLSAMPLING(pin) PORT->Group[GROUPNR(pin)].CTRL.reg |= PINMASK(pin); // Enable continuous sampling of a pin group the pin belongs to. (Always in groups of 8)
// To disable continous sampling, all eight bits/pins of that group must be cleared simultaneously.
#define PORT_CLR_CTRLSAMPLING(pin) PORT->Group[GROUPNR(pin)].CTRL.reg &= ~PINMASK_8_GROUP(pin); // Remove continuous sampling of a pins group
/* WRCONFIG must be handled with special ´handling and is therfore not defined normally.
#define PORT_PULL_PIN_EN(pin) PORT->Group[GROUPNR(pin)].PINCFG[PINNR(pin)].bit.PULLEN=1 // Enable pull on a pin (Typ 40 kohm). Data value defines pull-up (1) or pull-down (0). Not on PA24 and PA25
#define PORT_PULL_PIN_DIS(pin) PORT->Group[GROUPNR(pin)].PINCFG[PINNR(pin)].bit.PULLEN=0 // Disable pull on a pin
#define PORT_PULL_PIN_DRIVE_STRONG(pin) PORT->Group[GROUPNR(pin)].PINCFG[PINNR(pin)].bit.DRVSTR=1 // Enable strong drive strength on a pin. (~3mA, twice for VCC=3.6V). Not on PA24 and PA25
#define PORT_PULL_PIN_DRIVE_WEAK(pin) PORT->Group[GROUPNR(pin)].PINCFG[PINNR(pin)].bit.DRVSTR=0 // Disable strong drive strength on a pin. (~1mA, twice for VCC=3.6V)
*/
// GROUPNR sets which port register that is accessed.
// PINNR sets which pin the register that is to be accessed belongs to.
// The number 1 or 0 is the modified bit value.
#define PORT_INPUT_PMUXEN_EN(pin) PORT->Group[GROUPNR(pin)].PINCFG[PINNR(pin)].bit.INEN = 1 // Enable the peripheral multiplexer
#define PORT_INPUT_PIN_EN(pin) PORT->Group[GROUPNR(pin)].PINCFG[PINNR(pin)].bit.INEN = 1 // Enable input buffer (needed to be able to read a pin)
#define PORT_PULL_PIN_EN(pin) PORT->Group[GROUPNR(pin)].PINCFG[PINNR(pin)].bit.PULLEN=1 // Enable pull on a pin (Typ 40 kohm). Data value defines pull-up (1) or pull-down (0). Not on PA24 and PA25
#define PORT_PULL_PIN_DIS(pin) PORT->Group[GROUPNR(pin)].PINCFG[PINNR(pin)].bit.PULLEN=0 // Disable pull on a pin
#define PORT_PULL_PIN_DRIVE_STRONG(pin) PORT->Group[GROUPNR(pin)].PINCFG[PINNR(pin)].bit.DRVSTR=1 // Enable strong drive strength on a pin. (~3mA, twice for VCC=3.6V). Not on PA24 and PA25
#define PORT_PULL_PIN_DRIVE_WEAK(pin) PORT->Group[GROUPNR(pin)].PINCFG[PINNR(pin)].bit.DRVSTR=0 // Disable strong drive strength on a pin. (~1mA, twice for VCC=3.6V)
// The PMUX register is not defined here
// Tip: Registers that has no groups are much easier to access. Example: SYSCTRL->VREG.bit.RUNSTDBY = 1
......
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