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Commit 17346f07 authored by Bengt Ragnemalm's avatar Bengt Ragnemalm
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macros are now much better and tested.

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src/ArduinoZeroTemplate.c
+ 15
− 36
View file @ 17346f07
......@@ -36,44 +36,23 @@ void ArduinoZeroTemplate(void)
{
while (true)
{
/*
#define PORT_INPUT_PIN_EN(pin) PORT->Group[GROUPNR(pin)].PINCFG[PINMASK(pin)].bit.INEN = 1 // Enable input buffer (needed to be able to read a pin)
#define PORT_SET_CTRLSAMPLING(pin) PORT->Group[GROUPNR(pin)].CTRL.reg |= PINMASK(pin); // Enable continuous sampling of a pin group (always in groups of 8)
#define PORT_CLR_CTRLSAMPLING(pin) PORT->Group[GROUPNR(pin)].CTRL.reg &= ~PINMASK(pin); // Remove continuous sampling of a pins group
#define PORT_PULL_PIN_EN(pin) PORT->Group[GROUPNR(pin)].PINCFG[PINMASK(pin)].bit.PULLEN=1 // Enable pull on a pin (Typ 40 kohm). Data value defines pull-up (1) or pull-down (0). Not on PA24 and PA25
#define PORT_PULL_PIN_DIS(pin) PORT->Group[GROUPNR(pin)].PINCFG[PINMASK(pin)].bit.PULLEN=0 // Disable pull on a pin
#define PORT_PULL_PIN_DRIVE_STRONG(pin) PORT->Group[GROUPNR(pin)].PINCFG[PINMASK(pin)].bit.DRVSTR=1 // Enable strong drive strength on a pin. (~3mA, twice for VCC=3.6V). Not on PA24 and PA25
#define PORT_PULL_PIN_DRIVE_WEAK(pin) PORT->Group[GROUPNR(pin)].PINCFG[PINMASK(pin)].bit.DRVSTR=1 // Disable strong drive strength on a pin. (~1mA, twice for VCC=3.6V)
*/
PORT_INPUT_PIN_EN(PIN_PB10);
PORT_PIN_INPUT_EN(PIN_PB10);
PORT_SET_CTRLSAMPLING(PIN_PB10);
PORT_CLR_CTRLSAMPLING(PIN_PB10);
PORT->Group[GROUPNR(PIN_PB10)].CTRL.reg = 0;
PORT_PULL_PIN_EN(PIN_PB10);
PORT_PULL_PIN_DIS(PIN_PB10);
PORT_PULL_PIN_DRIVE_STRONG(PIN_PB10);
PORT_PULL_PIN_DRIVE_WEAK(PIN_PB10);
PORT->Group[GROUPNR(PIN_PB10)].CTRL.reg = 0;
PORT_PIN_PULL_EN(PIN_PB10);
PORT_PIN_PULL_DIS(PIN_PB10);
PORT_PIN_PULL_DRIVE_STRONG(PIN_PB10);
PORT_PIN_PULL_DRIVE_WEAK(PIN_PB10);
/*
#define PORT_SET_PIN(pin) PORT->Group[GROUPNR(pin)].OUTSET.reg = PINMASK(pin)
#define PORT_CLR_PIN(pin) PORT->Group[GROUPNR(pin)].OUTCLR.reg = PINMASK(pin)
#define PORT_TOGGLE_PIN(pin) PORT->Group[GROUPNR(pin)].OUTTGL.reg = PINMASK(pin)
#define PORT_PIN_TO_OUTPUT(pin) PORT->Group[GROUPNR(pin)].DIRSET.reg = PINMASK(pin)
#define PORT_PIN_TO_INPUT(pin) PORT->Group[GROUPNR(pin)].DIRCLR.reg = PINMASK(pin)
#define PORT_PIN_TOGGLE_DIRECTION(pin) PORT->Group[GROUPNR(pin)].DIRTGL.reg = PINMASK(pin)
#define PORT_READ_PORT(pin) (PORT->Group[GROUPNR(pin)].IN.reg // Returns entire port (all pins)
#define PORT_READ_PIN1(pin) (PORT->Group[GROUPNR(pin)].IN.reg & PINMASK(pin)) >> (pin & 31) // Returns pin value 0 or 1.
#define PORT_READ_PIN(pin) (PORT->Group[GROUPNR(pin)].IN[PINMASK(pin)].bit) >> (pin & 31) // Returns pin value 0 or 1.
*/
PORT_SET_PIN(LED_0_PIN);
PORT_CLR_PIN(LED_0_PIN);
PORT_TOGGLE_PIN(LED_0_PIN);
PORT_PIN_SET(LED_0_PIN);
PORT_PIN_CLR(LED_0_PIN);
PORT_PIN_TOGGLE(LED_0_PIN);
PORT_PIN_TO_INPUT(LED_0_PIN);
PORT_PIN_TO_OUTPUT(LED_0_PIN);
PORT_PIN_TOGGLE_DIRECTION(LED_0_PIN);
readport=PORT_READ_PORT(PIN_PA00);
readport=PORT_READ_PIN1(PIN_PA00);
// readport=PORT_READ_PIN(PIN_PA00);
readport=PORT_READ_PIN(PIN_PA00);
slask = readport;
slask++;
}// end while (true) infinite loop
......@@ -85,7 +64,7 @@ void ArduinoZeroTemplateInit(void)
struct rtc_count_config rtc_count_config_struct;
/* Other modules if used:
struct usart_config usart_config_struct;
struct dac_config dac_config_struct; // There are only one DAC SAMD21 but it can in other controller have more than one channel.
struct dac_config dac_config_struct;
struct dac_chan_config dac_chan_config_struct;
struct i2c_master_config i2c_master_config_struct;
struct spi_config spi_config_struct;
......@@ -105,15 +84,15 @@ void ArduinoZeroTemplateInit(void)
// Configure output pins
// To in all circumstances avoid glitches, set the default value of the pin before setting the direction.
PORT_CLR_PIN(LED_0_PIN); // LED
PORT_PIN_CLR(LED_0_PIN); // LED
PORT_PIN_TO_OUTPUT(LED_0_PIN);
PORT_SET_PIN(MY_OUTPUT_PIN); // MY_OUTPUT
PORT_PIN_SET(MY_OUTPUT_PIN); // MY_OUTPUT
PORT_PIN_TO_OUTPUT(MY_OUTPUT_PIN);
// Configure input pins
// All IN-buffers for pins used as inputs must be enabled. This is controlled through the PINCFG.INEN bit
// PORT_PIN_TO_INPUT(MY_INPUT_PIN); // MY_INPUT
// PORT_INPUT_PIN_EN(MY_INPUT_PIN);
PORT_PIN_TO_INPUT(MY_INPUT_PIN); // MY_INPUT
PORT_PIN_INPUT_EN(MY_INPUT_PIN);
// End I/O configuration
......
src/macros.h
+ 18
− 25
View file @ 17346f07
......@@ -96,25 +96,25 @@ set several pins at once.
// These registers can also can be accessed using IOBUS. (IOBUS only exist in Cortex M0+)
// GROUPNR sets which port register that is accessed
// PINMASK sets which pin (or pins but the PINMASK macro does only access one pin) in the port that is accessed
#define PORT_SET_PIN(pin) PORT->Group[GROUPNR(pin)].OUTSET.reg = PINMASK(pin)
#define PORT_CLR_PIN(pin) PORT->Group[GROUPNR(pin)].OUTCLR.reg = PINMASK(pin)
#define PORT_TOGGLE_PIN(pin) PORT->Group[GROUPNR(pin)].OUTTGL.reg = PINMASK(pin)
#define PORT_PIN_SET(pin) PORT->Group[GROUPNR(pin)].OUTSET.reg = PINMASK(pin)
#define PORT_PIN_CLR(pin) PORT->Group[GROUPNR(pin)].OUTCLR.reg = PINMASK(pin)
#define PORT_PIN_TOGGLE(pin) PORT->Group[GROUPNR(pin)].OUTTGL.reg = PINMASK(pin)
#define PORT_PIN_TO_OUTPUT(pin) PORT->Group[GROUPNR(pin)].DIRSET.reg = PINMASK(pin)
#define PORT_PIN_TO_INPUT(pin) PORT->Group[GROUPNR(pin)].DIRCLR.reg = PINMASK(pin)
#define PORT_PIN_TOGGLE_DIRECTION(pin) PORT->Group[GROUPNR(pin)].DIRTGL.reg = PINMASK(pin)
#define PORT_READ_PORT(pin) PORT->Group[GROUPNR(pin)].IN.reg // Returns entire port (all pins)
#define PORT_READ_PIN1(pin) (PORT->Group[GROUPNR(pin)].IN.reg & PINMASK(pin)) >> (pin & 31) // Returns pin value 0 or 1.
#define PORT_READ_PIN(pin) PORT->Group[GROUPNR(pin)].IN.bit.IN[PINNR(pin)]=1 // Returns pin value 0 or 1.
#define PORT_READ_PORT(pin) PORT->Group[GROUPNR(pin)].IN.reg // Returns entire port (all pins) that the pin belongs to. (Use for example PIN_A00)
#define PORT_READ_PIN(pin) (PORT->Group[GROUPNR(pin)].IN.reg & PINMASK(pin)) >> (pin & 31) // Returns pin value 0 or 1.
// Same as above but using IOBUS. (Only in Cortex M0+)
#ifdef PORT_IOBUS
#define PORT_IOB_SET_PIN(pin) PORT_IOBUS->Group[GROUPNR(pin)].OUTSET.reg = PINMASK(pin) // Set to 1; Time at 48 MHz is 190nsec
#define PORT_IOB_CLR_PIN(pin) PORT_IOBUS->Group[GROUPNR(pin)].OUTCLR.reg = PINMASK(pin)
#define PORT_IOB_TOGGLE_PIN(pin) PORT_IOBUS->Group[GROUPNR(pin)].OUTTGL.reg = PINMASK(pin)
#define PORT_IOB_PIN_SET(pin) PORT_IOBUS->Group[GROUPNR(pin)].OUTSET.reg = PINMASK(pin) // Set to 1; Time at 48 MHz is 190nsec
#define PORT_IOB_PIN_CLR(pin) PORT_IOBUS->Group[GROUPNR(pin)].OUTCLR.reg = PINMASK(pin)
#define PORT_IOB_PIN_TOGGLE(pin) PORT_IOBUS->Group[GROUPNR(pin)].OUTTGL.reg = PINMASK(pin)
#define PORT_IOB_PIN_TO_OUTPUT(pin) PORT_IOBUS->Group[GROUPNR(pin)].DIRSET.reg = PINMASK(pin)
#define PORT_IOB_PIN_TO_INPUT(pin) PORT_IOBUS->Group[GROUPNR(pin)].DIRCLR.reg = PINMASK(pin)
#define PORT_IOB_PIN_TOGGLE_DIRECTION(pin) PORT_IOBUS->Group[GROUPNR(pin)].DIRTGL.reg = PINMASK(pin)
#define PORT_IOB_READ_PIN1(pin) (PORT_IOBUS->Group[GROUPNR(pin)].IN.reg & PINMASK(pin)) >> (pin & 31) // Returns pin value 0 or 1.
#define PORT_IOB_READ_PORT(pin) PORT_IOBUS->Group[GROUPNR(pin)].IN.reg // Returns entire port (all pins) that the pin belongs to. (Use for example PIN_A00)
#define PORT_IOB_READ_PIN(pin) (PORT_IOBUS->Group[GROUPNR(pin)].IN.reg & PINMASK(pin)) >> (pin & 31) // Returns pin value 0 or 1.
#endif
// The remaining PORT registers of which there is only one register for the whole port (like above) but
......@@ -133,11 +133,14 @@ set several pins at once.
// PINNR sets which pin the register that is to be accessed belongs to.
// The number 1 or 0 is the modified bit value.
#define PORT_INPUT_PMUXEN_EN(pin) PORT->Group[GROUPNR(pin)].PINCFG[PINNR(pin)].bit.INEN = 1 // Enable the peripheral multiplexer
#define PORT_INPUT_PIN_EN(pin) PORT->Group[GROUPNR(pin)].PINCFG[PINNR(pin)].bit.INEN = 1 // Enable input buffer (needed to be able to read a pin)
#define PORT_PULL_PIN_EN(pin) PORT->Group[GROUPNR(pin)].PINCFG[PINNR(pin)].bit.PULLEN=1 // Enable pull on a pin (Typ 40 kohm). Data value defines pull-up (1) or pull-down (0). Not on PA24 and PA25
#define PORT_PULL_PIN_DIS(pin) PORT->Group[GROUPNR(pin)].PINCFG[PINNR(pin)].bit.PULLEN=0 // Disable pull on a pin
#define PORT_PULL_PIN_DRIVE_STRONG(pin) PORT->Group[GROUPNR(pin)].PINCFG[PINNR(pin)].bit.DRVSTR=1 // Enable strong drive strength on a pin. (~3mA, twice for VCC=3.6V). Not on PA24 and PA25
#define PORT_PULL_PIN_DRIVE_WEAK(pin) PORT->Group[GROUPNR(pin)].PINCFG[PINNR(pin)].bit.DRVSTR=0 // Disable strong drive strength on a pin. (~1mA, twice for VCC=3.6V)
#define PORT_PIN_INPUT_EN(pin) PORT->Group[GROUPNR(pin)].PINCFG[PINNR(pin)].bit.INEN = 1 // Enable input buffer (needed to be able to read a pin)
#define PORT_PIN_PULL_EN(pin) PORT->Group[GROUPNR(pin)].PINCFG[PINNR(pin)].bit.PULLEN=1;\
PORT->Group[GROUPNR(pin)].OUTSET.reg = PINMASK(pin) // Enable pull on a pin (Typ 40 kohm). Data value defines pull-up (1) or pull-down (0). Not on PA24 and PA25
// Both PULLEN and OUTSET needs to be written to to enable the pull-up.
#define PORT_PIN_PULL_DIS(pin) PORT->Group[GROUPNR(pin)].PINCFG[PINNR(pin)].bit.PULLEN=0;\
PORT->Group[GROUPNR(pin)].OUTCLR.reg = PINMASK(pin) // Disable pull on a pin
#define PORT_PIN_PULL_DRIVE_STRONG(pin) PORT->Group[GROUPNR(pin)].PINCFG[PINNR(pin)].bit.DRVSTR=1 // Enable strong drive strength on a pin. (~3mA, twice for VCC=3.6V). Not on PA24 and PA25
#define PORT_PIN_PULL_DRIVE_WEAK(pin) PORT->Group[GROUPNR(pin)].PINCFG[PINNR(pin)].bit.DRVSTR=0 // Disable strong drive strength on a pin. (~1mA, twice for VCC=3.6V)
// The PMUX register is not defined here
......@@ -145,15 +148,5 @@ set several pins at once.
#ifndef MACROS_H_
#define MACROS_H_
/*
#define PORT_READ(port_nr) PORT->Group[port_nr].IN.reg // Read a port
#define PORT_SET_CTRLSAMPLING(port_nr,port_pin) PORT->Group[port_nr].CTRL.reg |= port_pin; // Enable continuous sampling of a pin group (always in groups of 8)
#define PORT_CLR_CTRLSAMPLING(port_nr,port_pin) PORT->Group[port_nr].CTRL.reg &= ~port_pin; // Remove continuous sampling of a pin group
#define PORT_PULL_PIN_EN(port_nr,port_pin) PORT->Group[port_nr].PINCFG[port_pin].PULLEN=1 // Enable pull on a pin (Typ 40 kohm). Data value defines pull-up (1) or pull-down (0). Not on PA24 and PA25
#define PORT_PULL_PIN_DIS(port_nr,port_pin) PORT->Group[port_nr].PINCFG[port_pin].PULLEN=0 // Disable pull on a pin
#define PORT_PULL_PIN_DRIVE_STRONG(port_nr,port_pin) PORT->Group[port_nr].PINCFG[port_pin].DRVSTR=1 // Enable strong drive strength on a pin. (~3mA, twice for VCC=3.6V). Not on PA24 and PA25
#define PORT_PULL_PIN_DRIVE_WEAK(port_nr,port_pin) PORT->Group[port_nr].PINCFG[port_pin].DRVSTR=1 // Disable strong drive strength on a pin. (~1mA, twice for VCC=3.6V)
*/
// Tip: Example of other register or variable fiddling: SYSCTRL->VREG.bit.RUNSTDBY = 1
#endif /* MACROS_H_ */
\ No newline at end of file
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