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Computer Engineering
simuDAtor
Commits
f1e06874
Commit
f1e06874
authored
10 months ago
by
Martin
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merge
parents
81b85b36
0da8baff
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!40
started to seperate state and parameters, ended up doing more work on keeping private variables private
Changes
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3 changed files
src/simudator/core/module.py
+1
-1
1 addition, 1 deletion
src/simudator/core/module.py
src/simudator/core/modules/mux.py
+3
-3
3 additions, 3 deletions
src/simudator/core/modules/mux.py
src/simudator/core/modules/register.py
+1
-1
1 addition, 1 deletion
src/simudator/core/modules/register.py
with
5 additions
and
5 deletions
src/simudator/core/module.py
+
1
−
1
View file @
f1e06874
...
...
@@ -86,7 +86,7 @@ class Module:
Returns
-------
dict[str, Any]
Parameter of the module represented as a dictionary with one key for
Parameter
s
of the module represented as a dictionary with one key for
each parameter variable.
"""
param_dict
=
dict
()
...
...
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Click to expand it.
src/simudator/core/modules/mux.py
+
3
−
3
View file @
f1e06874
...
...
@@ -87,10 +87,10 @@ class Mux(Module):
return
state
def
get_parameter
(
self
)
->
dict
[
str
,
Any
]:
paramter
=
super
().
get_state
()
paramter
[
"
bit_length
"
]
=
self
.
_bit_length
param
e
ter
=
super
().
get_state
()
param
e
ter
[
"
bit_length
"
]
=
self
.
_bit_length
return
paramter
return
param
e
ter
def
save_state_to_file
(
self
,
file_path
:
str
)
->
bool
:
content
=
self
.
name
+
"
:
\n
value:
"
+
str
(
self
.
_value
)
+
"
\n\n
"
...
...
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src/simudator/core/modules/register.py
+
1
−
1
View file @
f1e06874
...
...
@@ -115,7 +115,7 @@ class IntegerRegister(Register):
name
:
str
|
None
=
None
,
)
->
None
:
# set the register
s
name
# set the register name
if
name
is
None
:
name
=
f
"
{
bit_length
}
-bit register
"
...
...
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