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Commit c3be0e2d authored by Martin's avatar Martin
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removed bit length

parent 538f2728
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1 merge request!26removed bit length
Pipeline #132079 failed
...@@ -20,12 +20,10 @@ class MicroPC(Module): ...@@ -20,12 +20,10 @@ class MicroPC(Module):
from_supc: Signal, from_supc: Signal,
to_um: Signal, to_um: Signal,
from_um: Signal, from_um: Signal,
bit_length: int = 8,
name: str = "uPC", name: str = "uPC",
) -> None: ) -> None:
self.value = 0 self.value = 0
self.bit_length = bit_length
# Signals # Signals
signals = { signals = {
...@@ -69,7 +67,6 @@ class MicroPC(Module): ...@@ -69,7 +67,6 @@ class MicroPC(Module):
def get_state(self) -> dict: def get_state(self) -> dict:
state = super().get_state() state = super().get_state()
state["value"] = self.value state["value"] = self.value
state["bit_length"] = self.bit_length
return state return state
def get_gui_state(self) -> dict: def get_gui_state(self) -> dict:
...@@ -82,8 +79,6 @@ class MicroPC(Module): ...@@ -82,8 +79,6 @@ class MicroPC(Module):
def set_state(self, state: dict) -> None: def set_state(self, state: dict) -> None:
super().set_state(state) super().set_state(state)
self.value = state["value"] self.value = state["value"]
if "bit_length" in state:
self.bit_length = state["bit_length"]
def reset(self) -> None: def reset(self) -> None:
""" """
......
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