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Computer Engineering
simuDAtor
Commits
02b7e4e6
Commit
02b7e4e6
authored
2 years ago
by
Elias Johansson
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updated ir
parent
92dc31ab
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Pipeline
#99374
failed
2 years ago
Stage: test
Changes
3
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1
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3 changed files
pyvenv.cfg
+3
-0
3 additions, 0 deletions
pyvenv.cfg
src/simudator/core/modules/module.py
+4
-0
4 additions, 0 deletions
src/simudator/core/modules/module.py
src/simudator/processor/mia/ir.py
+18
-10
18 additions, 10 deletions
src/simudator/processor/mia/ir.py
with
25 additions
and
10 deletions
pyvenv.cfg
0 → 100644
+
3
−
0
View file @
02b7e4e6
home
=
/usr/bin
include-system-site-packages
=
false
version
=
3.10.6
This diff is collapsed.
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src/simudator/core/modules/module.py
+
4
−
0
View file @
02b7e4e6
...
@@ -20,6 +20,10 @@ class Module:
...
@@ -20,6 +20,10 @@ class Module:
pass
pass
def
output_register
(
self
)
->
None
:
def
output_register
(
self
)
->
None
:
"""
Simulates module behaviour for giving data to output signals
during a clock tick. Exact behaviour is specifid in each module type.
"""
pass
pass
def
update_logic
(
self
)
->
None
:
def
update_logic
(
self
)
->
None
:
...
...
This diff is collapsed.
Click to expand it.
src/simudator/processor/mia/ir.py
+
18
−
10
View file @
02b7e4e6
...
@@ -26,14 +26,22 @@ class IR(Module):
...
@@ -26,14 +26,22 @@ class IR(Module):
# Register as destination of input signals
# Register as destination of input signals
from_bus
.
add_destination
(
self
)
from_bus
.
add_destination
(
self
)
def
update
(
self
)
->
None
:
# Internal values
self
.
op
=
0
self
.
grx
=
0
self
.
m
=
0
self
.
a
=
0
def
update_register
(
self
)
->
None
:
self
.
instruction
=
self
.
from_bus_s
.
get_value
()
self
.
instruction
=
self
.
from_bus_s
.
get_value
()
op
=
self
.
instruction
>>
12
self
.
op
=
self
.
instruction
>>
12
grx
=
(
self
.
instruction
>>
10
)
&
0b11
self
.
grx
=
(
self
.
instruction
>>
10
)
&
0b11
m
=
(
self
.
instruction
>>
8
)
&
0b11
self
.
m
=
(
self
.
instruction
>>
8
)
&
0b11
a
=
self
.
instruction
&
(
2
**
8
-
1
)
self
.
a
=
self
.
instruction
&
(
2
**
8
-
1
)
self
.
op_s
.
update_value
(
op
)
self
.
grx_s
.
update_value
(
grx
)
def
output_register
(
self
)
->
None
:
self
.
m_s
.
update_value
(
m
)
self
.
op_s
.
update_value
(
self
.
op
)
self
.
to_bus_s
.
update_value
(
a
)
self
.
grx_s
.
update_value
(
self
.
grx
)
self
.
m_s
.
update_value
(
self
.
m
)
self
.
to_bus_s
.
update_value
(
self
.
a
)
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