Skip to content

NorCAS2023 changes

Mikael Henriksson requested to merge NorCAS2023 into master

This merge request comes with the following changes:

  • Memory-based code generation supports automatic pipelining of address generation logic
  • A bug-fix in memory-based storage that fixes address signal widths, which in turn results in smaller designs when synthesized with Xilinx Vivado
  • More robust VHDL testbench for the memory-based and register-based storages.
  • Passing of **kwargs to draw_exclusion_graph_coloring() for possibly fancier exclusion graph drawing
Edited by Mikael Henriksson

Merge request reports