Fix linting issues

b_asic/codegen/vhdl/architecture.py

@@ -2,16 +2,18 @@
 Module for code generation of VHDL architectures.
 """
 from io import TextIOWrapper
-from typing import Dict, Set, Tuple, cast
+from typing import TYPE_CHECKING, Dict, Set, Tuple, cast
 
 from b_asic.codegen import vhdl
 from b_asic.process import MemoryVariable, PlainMemoryVariable
-from b_asic.resources import ProcessCollection, _ForwardBackwardTable
+
+if TYPE_CHECKING:
+    from b_asic.resources import ProcessCollection, _ForwardBackwardTable
 
 
 def write_memory_based_storage(
     f: TextIOWrapper,
-    assignment: Set[ProcessCollection],
+    assignment: Set["ProcessCollection"],
     entity_name: str,
     word_length: int,
     read_ports: int,
@@ -286,7 +288,7 @@ def write_memory_based_storage(
 
 def write_register_based_storage(
     f: TextIOWrapper,
-    forward_backward_table: _ForwardBackwardTable,
+    forward_backward_table: "_ForwardBackwardTable",
     entity_name: str,
     word_length: int,
     read_ports: int,