Fix linting issues

b_asic/codegen/vhdl/architecture.py

@@ -2,17 +2,18 @@
 Module for code generation of VHDL architectures.
 """
 from io import TextIOWrapper
-from typing import Dict, List, Set, Tuple, cast
+from typing import TYPE_CHECKING, Dict, Set, Tuple, cast
 
 from b_asic.codegen import vhdl
-from b_asic.codegen.vhdl import VHDL_TAB
 from b_asic.process import MemoryVariable, PlainMemoryVariable
-from b_asic.resources import ProcessCollection, _ForwardBackwardTable
+
+if TYPE_CHECKING:
+    from b_asic.resources import ProcessCollection, _ForwardBackwardTable
 
 
 def write_memory_based_storage(
     f: TextIOWrapper,
-    assignment: Set[ProcessCollection],
+    assignment: Set["ProcessCollection"],
     entity_name: str,
     word_length: int,
     read_ports: int,
@@ -91,7 +92,7 @@ def write_memory_based_storage(
         vhdl.common.write_signal_decl(f, f'write_en_{i}', 'std_logic', name_pad=14)
 
     # Schedule time counter
-    vhdl.write(f, 1, f'-- Schedule counter', start='\n')
+    vhdl.write(f, 1, '-- Schedule counter', start='\n')
     vhdl.common.write_signal_decl(
         f,
         name='schedule_cnt',
@@ -101,7 +102,7 @@ def write_memory_based_storage(
 
     # Input sync signals
     if input_sync:
-        vhdl.write(f, 1, f'-- Input synchronization', start='\n')
+        vhdl.write(f, 1, '-- Input synchronization', start='\n')
         for i in range(read_ports):
             vhdl.common.write_signal_decl(
                 f, f'p_{i}_in_sync', 'std_logic_vector(WL-1 downto 0)', name_pad=14
@@ -110,8 +111,8 @@ def write_memory_based_storage(
     #
     # Architecture body begin
     #
-    vhdl.write(f, 0, f'begin', start='\n', end='\n\n')
-    vhdl.write(f, 1, f'-- Schedule counter')
+    vhdl.write(f, 0, 'begin', start='\n', end='\n\n')
+    vhdl.write(f, 1, '-- Schedule counter')
     vhdl.common.write_synchronous_process_prologue(
         f=f,
         name='schedule_cnt_proc',
@@ -120,17 +121,17 @@ def write_memory_based_storage(
     vhdl.write_lines(
         f,
         [
-            (3, f'if rst = \'1\' then'),
-            (4, f'schedule_cnt <= 0;'),
-            (3, f'else'),
-            (4, f'if en = \'1\' then'),
+            (3, 'if rst = \'1\' then'),
+            (4, 'schedule_cnt <= 0;'),
+            (3, 'else'),
+            (4, 'if en = \'1\' then'),
             (5, f'if schedule_cnt = {schedule_time-1} then'),
-            (6, f'schedule_cnt <= 0;'),
-            (5, f'else'),
-            (6, f'schedule_cnt <= schedule_cnt + 1;'),
-            (5, f'end if;'),
-            (4, f'end if;'),
-            (3, f'end if;'),
+            (6, 'schedule_cnt <= 0;'),
+            (5, 'else'),
+            (6, 'schedule_cnt <= schedule_cnt + 1;'),
+            (5, 'end if;'),
+            (4, 'end if;'),
+            (3, 'end if;'),
         ],
     )
     vhdl.common.write_synchronous_process_epilogue(
@@ -140,7 +141,7 @@ def write_memory_based_storage(
     )
 
     if input_sync:
-        vhdl.write(f, 1, f'-- Input synchronization', start='\n')
+        vhdl.write(f, 1, '-- Input synchronization', start='\n')
         vhdl.common.write_synchronous_process_prologue(
             f=f,
             name='input_sync_proc',
@@ -155,7 +156,7 @@ def write_memory_based_storage(
         )
 
     # Infer memory
-    vhdl.write(f, 1, f'-- Memory', start='\n')
+    vhdl.write(f, 1, '-- Memory', start='\n')
     vhdl.common.write_asynchronous_read_memory(
         f=f,
         clk='clk',
@@ -171,7 +172,7 @@ def write_memory_based_storage(
     )
 
     # Write address generation
-    vhdl.write(f, 1, f'-- Memory write address generation', start='\n')
+    vhdl.write(f, 1, '-- Memory write address generation', start='\n')
     if input_sync:
         vhdl.common.write_synchronous_process_prologue(
             f, clk="clk", name="mem_write_address_proc"
@@ -180,7 +181,7 @@ def write_memory_based_storage(
         vhdl.common.write_process_prologue(
             f, sensitivity_list="schedule_cnt", name="mem_write_address_proc"
         )
-    vhdl.write(f, 3, f'case schedule_cnt is')
+    vhdl.write(f, 3, 'case schedule_cnt is')
     for i, collection in enumerate(assignment):
         for mv in collection:
             mv = cast(MemoryVariable, mv)
@@ -191,7 +192,7 @@ def write_memory_based_storage(
                         (4, f'-- {mv!r}'),
                         (4, f'when {(mv.start_time) % schedule_time} =>'),
                         (5, f'write_adr_0 <= {i};'),
-                        (5, f'write_en_0 <= \'1\';'),
+                        (5, 'write_en_0 <= \'1\';'),
                     ],
                 )
     vhdl.write_lines(
@@ -213,11 +214,11 @@ def write_memory_based_storage(
         )
 
     # Read address generation
-    vhdl.write(f, 1, f'-- Memory read address generation', start='\n')
+    vhdl.write(f, 1, '-- Memory read address generation', start='\n')
     vhdl.common.write_synchronous_process_prologue(
         f, clk="clk", name="mem_read_address_proc"
     )
-    vhdl.write(f, 3, f'case schedule_cnt is')
+    vhdl.write(f, 3, 'case schedule_cnt is')
     for i, collection in enumerate(assignment):
         for mv in collection:
             mv = cast(PlainMemoryVariable, mv)
@@ -233,27 +234,27 @@ def write_memory_based_storage(
                     f,
                     [
                         (5, f'read_adr_0 <= {i};'),
-                        (5, f'read_en_0 <= \'1\';'),
+                        (5, 'read_en_0 <= \'1\';'),
                     ],
                 )
     vhdl.write_lines(
         f,
         [
-            (4, f'when others =>'),
-            (5, f'read_adr_0 <= 0;'),
-            (5, f'read_en_0 <= \'0\';'),
-            (3, f'end case;'),
+            (4, 'when others =>'),
+            (5, 'read_adr_0 <= 0;'),
+            (5, 'read_en_0 <= \'0\';'),
+            (3, 'end case;'),
         ],
     )
     vhdl.common.write_synchronous_process_epilogue(
         f, clk="clk", name="mem_read_address_proc"
     )
 
-    vhdl.write(f, 1, f'-- Input and output assignmentn', start='\n')
+    vhdl.write(f, 1, '-- Input and output assignmentn', start='\n')
     if input_sync:
-        vhdl.write(f, 1, f'write_port_0 <= p_0_in_sync;')
+        vhdl.write(f, 1, 'write_port_0 <= p_0_in_sync;')
     else:
-        vhdl.write(f, 1, f'write_port_0 <= p_0_in;')
+        vhdl.write(f, 1, 'write_port_0 <= p_0_in;')
     p_zero_exec = filter(
         lambda p: p.execution_time == 0, (p for pc in assignment for p in pc)
     )
@@ -262,7 +263,7 @@ def write_memory_based_storage(
         clk='clk',
         name='output_reg_proc',
     )
-    vhdl.write(f, 3, f'case schedule_cnt is')
+    vhdl.write(f, 3, 'case schedule_cnt is')
     for p in p_zero_exec:
         if input_sync:
             write_time = (p.start_time + 1) % schedule_time
@@ -273,8 +274,8 @@ def write_memory_based_storage(
     vhdl.write_lines(
         f,
         [
-            (4, f'when others => p_0_out <= read_port_0;'),
-            (3, f'end case;'),
+            (4, 'when others => p_0_out <= read_port_0;'),
+            (3, 'end case;'),
         ],
     )
     vhdl.common.write_synchronous_process_epilogue(
@@ -287,7 +288,7 @@ def write_memory_based_storage(
 
 def write_register_based_storage(
     f: TextIOWrapper,
-    forward_backward_table: _ForwardBackwardTable,
+    forward_backward_table: "_ForwardBackwardTable",
     entity_name: str,
     word_length: int,
     read_ports: int,
@@ -330,7 +331,7 @@ def write_register_based_storage(
     )
 
     # Schedule time counter
-    vhdl.write(f, 1, f'-- Schedule counter')
+    vhdl.write(f, 1, '-- Schedule counter')
     vhdl.common.write_signal_decl(
         f,
         name='schedule_cnt',
@@ -340,7 +341,7 @@ def write_register_based_storage(
     )
 
     # Shift register
-    vhdl.write(f, 1, f'-- Shift register', start='\n')
+    vhdl.write(f, 1, '-- Shift register', start='\n')
     vhdl.common.write_type_decl(
         f,
         name='shift_reg_type',
@@ -354,7 +355,7 @@ def write_register_based_storage(
     )
 
     # Back edge mux decoder
-    vhdl.write(f, 1, f'-- Back-edge mux select signal', start='\n')
+    vhdl.write(f, 1, '-- Back-edge mux select signal', start='\n')
     vhdl.common.write_signal_decl(
         f,
         name='back_edge_mux_sel',
@@ -363,7 +364,7 @@ def write_register_based_storage(
     )
 
     # Output mux selector
-    vhdl.write(f, 1, f'-- Output mux select signal', start='\n')
+    vhdl.write(f, 1, '-- Output mux select signal', start='\n')
     vhdl.common.write_signal_decl(
         f,
         name='out_mux_sel',
@@ -374,8 +375,8 @@ def write_register_based_storage(
     #
     # Architecture body begin
     #
-    vhdl.write(f, 0, f'begin', start='\n', end='\n\n')
-    vhdl.write(f, 1, f'-- Schedule counter')
+    vhdl.write(f, 0, 'begin', start='\n', end='\n\n')
+    vhdl.write(f, 1, '-- Schedule counter')
     vhdl.common.write_synchronous_process_prologue(
         f=f,
         name='schedule_cnt_proc',
@@ -384,13 +385,13 @@ def write_register_based_storage(
     vhdl.write_lines(
         f,
         [
-            (4, f'if en = \'1\' then'),
+            (4, 'if en = \'1\' then'),
             (5, f'if schedule_cnt = {schedule_time}-1 then'),
-            (6, f'schedule_cnt <= 0;'),
-            (5, f'else'),
-            (6, f'schedule_cnt <= schedule_cnt + 1;'),
-            (5, f'end if;'),
-            (4, f'end if;'),
+            (6, 'schedule_cnt <= 0;'),
+            (5, 'else'),
+            (6, 'schedule_cnt <= schedule_cnt + 1;'),
+            (5, 'end if;'),
+            (4, 'end if;'),
         ],
     )
     vhdl.common.write_synchronous_process_epilogue(
@@ -400,13 +401,13 @@ def write_register_based_storage(
     )
 
     # Shift register back-edge decoding
-    vhdl.write(f, 1, f'-- Shift register back-edge decoding', start='\n')
+    vhdl.write(f, 1, '-- Shift register back-edge decoding', start='\n')
     vhdl.common.write_synchronous_process_prologue(
         f,
         clk='clk',
         name='shift_reg_back_edge_decode_proc',
     )
-    vhdl.write(f, 3, f'case schedule_cnt is')
+    vhdl.write(f, 3, 'case schedule_cnt is')
     for time, entry in enumerate(forward_backward_table):
         if entry.back_edge_to:
             assert len(entry.back_edge_to) == 1
@@ -423,9 +424,9 @@ def write_register_based_storage(
     vhdl.write_lines(
         f,
         [
-            (4, f'when others =>'),
-            (5, f'back_edge_mux_sel <= 0;'),
-            (3, f'end case;'),
+            (4, 'when others =>'),
+            (5, 'back_edge_mux_sel <= 0;'),
+            (3, 'end case;'),
         ],
     )
     vhdl.common.write_synchronous_process_epilogue(
@@ -435,28 +436,28 @@ def write_register_based_storage(
     )
 
     # Shift register multiplexer logic
-    vhdl.write(f, 1, f'-- Multiplexers for shift register', start='\n')
+    vhdl.write(f, 1, '-- Multiplexers for shift register', start='\n')
     vhdl.common.write_synchronous_process_prologue(
         f,
         clk='clk',
         name='shift_reg_proc',
     )
     if sync_rst:
-        vhdl.write(f, 3, f'if rst = \'1\' then')
+        vhdl.write(f, 3, 'if rst = \'1\' then')
         for reg_idx in range(reg_cnt):
             vhdl.write(f, 4, f'shift_reg({reg_idx}) <= (others => \'0\');')
-        vhdl.write(f, 3, f'else')
+        vhdl.write(f, 3, 'else')
 
     vhdl.write_lines(
         f,
         [
-            (3, f'-- Default case'),
-            (3, f'shift_reg(0) <= p_0_in;'),
+            (3, '-- Default case'),
+            (3, 'shift_reg(0) <= p_0_in;'),
         ],
     )
     for reg_idx in range(1, reg_cnt):
         vhdl.write(f, 3, f'shift_reg({reg_idx}) <= shift_reg({reg_idx-1});')
-    vhdl.write(f, 3, f'case back_edge_mux_sel is')
+    vhdl.write(f, 3, 'case back_edge_mux_sel is')
     for edge, mux_sel in back_edge_table.items():
         vhdl.write_lines(
             f,
@@ -468,13 +469,13 @@ def write_register_based_storage(
     vhdl.write_lines(
         f,
         [
-            (4, f'when others => null;'),
-            (3, f'end case;'),
+            (4, 'when others => null;'),
+            (3, 'end case;'),
         ],
     )
 
     if sync_rst:
-        vhdl.write(f, 3, f'end if;')
+        vhdl.write(f, 3, 'end if;')
 
     vhdl.common.write_synchronous_process_epilogue(
         f,
@@ -483,36 +484,36 @@ def write_register_based_storage(
     )
 
     # Output multiplexer decoding logic
-    vhdl.write(f, 1, f'-- Output muliplexer decoding logic', start='\n')
+    vhdl.write(f, 1, '-- Output muliplexer decoding logic', start='\n')
     vhdl.common.write_synchronous_process_prologue(
         f, clk='clk', name='out_mux_decode_proc'
     )
-    vhdl.write(f, 3, f'case schedule_cnt is')
+    vhdl.write(f, 3, 'case schedule_cnt is')
     for i, entry in enumerate(forward_backward_table):
         if entry.outputs_from is not None:
             sel = output_mux_table[entry.outputs_from]
             vhdl.write(f, 4, f'when {(i-1)%schedule_time} =>')
             vhdl.write(f, 5, f'out_mux_sel <= {sel};')
-    vhdl.write(f, 3, f'end case;')
+    vhdl.write(f, 3, 'end case;')
     vhdl.common.write_synchronous_process_epilogue(
         f, clk='clk', name='out_mux_decode_proc'
     )
 
     # Output multiplexer logic
-    vhdl.write(f, 1, f'-- Output muliplexer', start='\n')
+    vhdl.write(f, 1, '-- Output muliplexer', start='\n')
     vhdl.common.write_synchronous_process_prologue(
         f,
         clk='clk',
         name='out_mux_proc',
     )
-    vhdl.write(f, 3, f'case out_mux_sel is')
+    vhdl.write(f, 3, 'case out_mux_sel is')
     for reg_i, mux_i in output_mux_table.items():
         vhdl.write(f, 4, f'when {mux_i} =>')
         if reg_i < 0:
             vhdl.write(f, 5, f'p_0_out <= p_{-1-reg_i}_in;')
         else:
             vhdl.write(f, 5, f'p_0_out <= shift_reg({reg_i});')
-    vhdl.write(f, 3, f'end case;')
+    vhdl.write(f, 3, 'end case;')
     vhdl.common.write_synchronous_process_epilogue(
         f,
         clk='clk',