add print constant and all tests is passing

b_asic/signal_flow_graph.py

@@ -359,10 +359,17 @@ class SFG(AbstractOperation):
                 for key, value in self._components_by_id.items():
                     if value is comp:
                         output_string += "id: " + key + ", name: "
+                
                 if comp.name != None:
-                    output_string += comp.name + ", input: ["
+                    output_string += comp.name + ", "
+                else:
+                    output_string += "-, "
+                
+                if comp.type_name is "c":
+                    output_string += "value: " + str(comp.value) + ", input: ["
                 else:
-                    output_string += "-, input: ["
+                    output_string += "input: [" 
+
                 counter_input = 0
                 for input in comp.inputs:
                     counter_input += 1

test/test_print_sfg.py

 from b_asic.signal_flow_graph import SFG
-from b_asic.core_operations import Addition
+from b_asic.core_operations import Addition, Multiplication, Constant, ConstantAddition
 from b_asic.port import InputPort, OutputPort
 from b_asic.signal import Signal
 from b_asic.special_operations import Input, Output
@@ -16,23 +16,27 @@ class TestPrintSfg:
         out1 = Output(add1, "OUT1")
         sfg = SFG(inputs=[inp1, inp2], outputs=[out1], name="sf1")
 
-        assert print(sfg) == ("id: add1, name: ADD1, input: [s1, s2], output: [s3]\nid: in1, name: INP1, input: [], output: [s1]\nid: in2, name: INP2, input: [], output: [s2]\nid: out1, name: OUT1, input: [s3], output: []\n")
+        assert sfg.__str__() == ("id: add1, name: ADD1, input: [s1, s2], output: [s3]\nid: in1, name: INP1, input: [], output: [s1]\nid: in2, name: INP2, input: [], output: [s2]\nid: out1, name: OUT1, input: [s3], output: []\n")
 
-    def test_print_signal_id(self):
-        in_port1 = InputPort(0, None)
-        out_port1 = OutputPort(0, None)
+    def test_print_add_mul(self):
+        inp1 = Input("INP1")
+        inp2 = Input("INP2")
+        inp3 = Input("INP3")
+        add1 = Addition(inp1, inp2, "ADD1")
+        mul1 = Multiplication(add1, inp3, "MUL1")
+        out1 = Output(mul1, "OUT1")
+        sfg = SFG(inputs=[inp1, inp2, inp3], outputs=[out1], name="mac_sfg")
 
-        test_signal1 = Signal(out_port1, in_port1)
+        assert sfg.__str__() == ("id: add1, name: ADD1, input: [s1, s2], output: [s5]\nid: in1, name: INP1, input: [], output: [s1]\nid: in2, name: INP2, input: [], output: [s2]\nid: mul1, name: MUL1, input: [s5, s3], output: [s4]\nid: in3, name: INP3, input: [], output: [s3]\nid: out1, name: OUT1, input: [s4], output: []\n")
 
-        assert test_signal1.type_name == "s"
+    def test_print_constant(self):
+        inp1 = Input("INP1")
+        const1 = Constant(3, "CONST")
+        add1 = Addition(const1, inp1, "ADD1")
+        out1 = Output(add1, "OUT1")
 
-    def test_print_operation_id(self):
-        test_operation = Addition()
-        assert test_operation.type_name == "add"
+        sfg = SFG(inputs=[inp1], outputs=[out1], name="sfg")
 
-    def test_print_operation_name(self):
-        test_operation = Addition()
-        test_operation._name = "my_add"
-        assert test_operation._name == "my_add"
+        assert sfg.__str__() == ("id: add1, name: ADD1, input: [s3, s1], output: [s2]\nid: c1, name: CONST, value: 3, input: [], output: [s3]\nid: in1, name: INP1, input: [], output: [s1]\nid: out1, name: OUT1, input: [s2], output: []\n")
 
      
\ No newline at end of file