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stopwatch.vhdl

+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity stopwatch is
+	port(clk, reset : in std_logic; -- clk is "fast enough". reset is active high.
+	     hundradelspuls : in std_logic;
+	     muxfrekvens   : in std_logic; -- tic for multiplexing the display.
+	     start_stopp : in std_logic;
+	     nollstallning : in std_logic; -- restart from 00:00:00
+	     visningslage : in std_logic; -- 1:show min/sec. 0: show sec/centisec
+	     display : out unsigned(1 downto 0); -- 0=rightmost
+	     digit : out std_logic_vector(0 to 7); -- 0=A, 1=B, ..., 6=G, 7=DP
+	     raknar : out std_logic); -- Connected to a LED
+	attribute pin_assign : string;
+	attribute pin_assign of clk : signal is "P5";
+	attribute pin_assign of reset : signal is "P39";
+	attribute pin_assign of hundradelspuls : signal is "P22";
+	attribute pin_assign of muxfrekvens : signal is "P20"
+	attribute pin_assign of start_stopp : signal is "P19";
+	attribute pin_assign of nollstallning : signal is "P18";
+	attribute pin_assign of visningslage : signal is "P24";
+	attribute pin_assign of display : signal is "P44, P43";
+	attribute pin_assign of digit : signal is "P28, P29, P33, P34, P35, P36, P37, P38";
+	attribute pin_assign of raknar : signal is "P42";
+end entity;
+
+architecture rtl of stopwatch is
+	signal sync_hundra1 : std_logic;
+	signal sync_hundra2 : std_logic;
+	signal enpuls_hundra : std_logic;
+	signal sync_mux : std_logic;
+	signal sync_mux_old : std_logic
+	signal enpuls_mux : std_logic;
+	signal sync_start_stop : std_logic;
+	signal sync_start_stop_old : std_logic;
+	signal enpuls_start_stop : std_logic;
+	signal sync_nollstallning : std_logic;
+	signal sync_visningslage : std_logic;
+	signal cntr_100 : unsigned(3 downto 0);
+	signal cntr_10 : unsigned(3 downto 0);
+	signal cntr_sec : unsigned(3 downto 0);
+	signal cntr_sec_10 : unsigned(2 downto 0);
+	signal cntr_min : unsigned(3 downto 0);
+	signal cntr_min_10 : unsigned(2 downto 0);
+	signal CE_10 : std_logic;
+	signal CE_sec : std_logic;
+	signal CE_sec_10 : std_logic;
+	signal CE_min : std_logic;
+	signal CE_min_10 : std_logic;
+	
+	
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			sync_hundra1 <= hundradelspuls;
+			sync_hundra2 <= sync_hundra1;
+			sync_mux <= muxfrekvens;
+			sync_mux_old <= sync_mux;
+			sync_start_stop <= start_stopp;
+			sync_start_stop_old <= sync_start_stop;
+			sync_nollstallning <= nollstallning;
+			sync_visningslage <= visningslage;
+		end if;
+	end process;
+	-- enpulsning
+	enpuls_hundra <= sync_hundra1 and not sync_hundra2;
+	enpuls_start_stop <= sync_start_stop and not sync_start_stop_old;
+	enpuls_mux <= sync_mux and not sync_mux_old;
+	
+	-- hundradel
+	process(clk, reset) begin
+		if (reset = '1') then
+			cntr_100 <= to_unsigned(0, 4);
+		elsif rising_edge(clk) and (enpuls_hundra = '1') then
+			if (cntr_100 = "1001") then
+				cntr_100 <= "0000";
+				CE_10 <= '1';
+			else
+				cntr_100 <= cntr_100 + 1;
+				CE_10 <= '0';
+			end if; 
+		end if;
+
+	end process;
+	
+	-- tiondel
+	process(clk, reset) begin
+		if (reset = '1') then
+			cntr_10 <= to_unsigned(0, 4);
+		elsif rising_edge(clk) and (enpuls_hundra = '1') and (CE_10 = '1') then
+			if (cntr_10 = "1001") then
+				cntr_10 <= "0000";
+				CE_sec <= '1';
+			else
+				cntr_10 <= cntr_10 + 1;
+				CE_sec <= '0';
+			end if; 
+		end if;
+
+	end process;
+	
+	-- sekund
+	process(clk, reset) begin
+		if (reset = '1') then
+			cntr_sec <= to_unsigned(0, 4);
+		elsif rising_edge(clk) and (enpuls_hundra = '1') and (CE_sec = '1') then
+			if (cntr_sec = "1001") then
+				cntr_sec <= "0000";
+				CE_sec_10 <= '1';
+			else
+				cntr_sec <= cntr_sec + 1;
+				CE_sec_10 <= '0';
+			end if; 
+		end if;
+
+	end process;
+	
+	-- sekund 10
+	process(clk, reset) begin
+		if (reset = '1') then
+			cntr_sec_10 <= to_unsigned(0, 3);
+		elsif rising_edge(clk) and (enpuls_hundra = '1') and (CE_sec_10 = '1') then
+			if (cntr_sec_10 = "101") then
+				cntr_sec_10 <= "000";
+				CE_min <= '1';
+			else
+				cntr_sec_10 <= cntr_sec_10 + 1;
+				CE_min <= '0';
+			end if; 
+		end if;
+
+	end process;
+	
+	--minut 
+	process(clk, reset) begin
+		if (reset = '1') then
+			cntr_min <= to_unsigned(0, 4);
+		elsif rising_edge(clk) and (enpuls_hundra = '1') and (CE_min = '1') then
+			if (cntr_min = "1001") then
+				cntr_min <= "0000";
+				CE_min_10 <= '1';
+			else
+				cntr_min <= cntr_min + 1;
+				CE_min_10 <= '0';
+			end if; 
+		end if;
+
+	end process;
+	
+	--minut 10
+	process(clk, reset) begin
+		if (reset = '1') then
+			cntr_min_10 <= to_unsigned(0, 3);
+		elsif rising_edge(clk) and (enpuls_hundra = '1') and (CE_min_10 = '1') then
+			if (cntr_min_10 = "101") then
+				cntr_min_10 <= "000";
+			else
+				cntr_min_10 <= cntr_min_10 + 1;
+			end if; 
+		end if;
+
+	end process;
+	
+	
+	-- You might need to use the "keep" attribute to fit the design in an CPLD.
+	-- If you want to apply it on e.g. signal "blah", then it looks like this:
+	--attribute keep : string;
+	--attribute keep of blah : signal is "true";
+begin
+end architecture;
+
+with visningslage select
+y <= "0" when "0",
+	d(1) when others,
+
+
+cntr_5 <= visningslage & cntr_4; 
+	with cntr_5 select
+	display_number <= cntr_100 when "000",
+	display_number <= cntr_10 when "001",
+	display_number <= cntr_sec when "010",
+	display_number <= cntr_sec_10 when "011",
+	display_number <= cntr_sec when "100",
+	display_number <= cntr_sec_10 when "101",
+	display_number <= cntr_min when "110",
+	display_number <= cntr_min_10 when others,
+