diff --git a/cadence/genus/README b/cadence/genus/README
new file mode 100644
index 0000000000000000000000000000000000000000..e6e9b6e82e60ab15ebe2216c8f998de795803990
--- /dev/null
+++ b/cadence/genus/README
@@ -0,0 +1,95 @@
+# st28flow
+A collection of scripts used for synthesis and place and route in Cadence 
+Genus and Innovus. The scripts use a STMicroelectronics 28nm FD-SOI cell 
+library and are designed to be run on umbriel.cse.chalmers.se. 
+
+## Sofware versions
+The scripts use the following software versions.
+
+- Cadence Genus 16.22
+- Cadence Innovus 16.13
+- Cadence Virtuoso 6.1.7
+
+## Cloning
+The repo can be cloned on the umbriel server by executing:
+`git clone /Home/erikbor/git/st28flow.git`
+
+## Content
+The following sections describe the content of the repo.
+
+### Files
+- `config_pnr.tcl` Contains settings for the place and rout script.
+- `config_syn.tcl` Contains all synthesis settings for the synth script.
+- `pnr.sh`         Shell script used to start place and route. Takes the
+                   name of a previously synthesized design as an argument.
+- `README.md`      This read me file.
+- `synth.sh`       Shell script to start synthesis, takes a design name 
+                   as an argument.
+### Directories
+`./ex`      Contains example files.
+`./out`     Output files from both synthesis and place and route. The results
+            are place in a subdirectory named after the design name.
+`./tcl`     Contains all .tcl subscripts.
+`./lvs`     Files related to LVS in Cadence Virtuoso.
+
+## Usage
+
+### Synthesis
+1. Create a text file containing a list of your source .vhdl and .v files.
+2. Edit the `config_syn.tcl` script and configure the synthesis settings and
+   the path to your source code and source-code list file.
+3. Run `. synth.sh <design name>`. The results will be placed in 
+   `./out/<design name>/syn/`.
+
+### Place and Route
+1. Edit `config_pnr.tcl` and configure the tool settings for place and 
+   route.
+2. Run `. pnr.sh <design name>`. The results will be placed in
+   `./out/<design name>/pnr/`.
+
+### LVS
+1. In Virtuoso Library Manager:
+   - File -> New -> Library.
+   - Choose a library name and path and pess [OK].
+   - Choose "Attach to existing technology library" and press [OK].
+   - Select cmos32lp and press [OK].
+1. In Virtuoso:
+   - File -> Import -> Stream.
+   - Select .gds file as stream and choose destination library.
+   - Click [More Options].
+   - Select "Use all Libraries as Ref Lib".
+   - Under Geometry select "Keep Stream Cells"  and click [OK].
+   - Press [Translate].
+3. In a terminal:
+   - Run `gen_lvs_box`, in the `./lvs` folder, on a netlist generated 
+     in Innovus using `SaveNetlist -excludeLeafCell -includePhysicalInst`. 
+4. In Virtuoso Library Manager:
+   - Open a layout of your design.
+   - Add pins for vdd and gnd if needed.
+   - Calibre -> nmLVS.
+5. In Calibre:
+   - Press [Inputs] and select the Netlist tab.
+   - Change format to Verilog, deselect Export to schematic viewer and
+     enter the path to a netlist generated in Innovus using
+     `SaveNetlist -includePowerGround`
+   - Setup -> LVS Options.
+   - LVS Options -> Include -> Add the file that was output from gen_lvs_box
+     to the list.
+   - Run LVS.
+
+## Final Comments
+- Fixes not included in the original scripts are located in `./tcl/fix`.
+- To remove all routes with DRC violations in Innovus, run:
+   `verify_drc`
+   `editDeleteViolations`
+   `routeDesign`
+- After import of a synth-to-placed design in Innovus add well taps and 
+  do `refinePlace` to corrected overlap problems.
+- Using the alternative techology file might be a good choice, since the
+  routing directions are oriented in alternating directions.
+- Don't forget to leave room for the ST logo (approx. 160x80 um^2) and
+  eMetro structures. The large eMetro structures are approx. 50x50 um^2 
+  while the small ones can fit under the power ring. One structure of each
+  type is needed for each 1x1 mm^2.
+
+
diff --git a/cadence/genus/config_pnr.tcl b/cadence/genus/config_pnr.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..35f56f7b529d5eb3ca890e4ec8f679d3bda52399
--- /dev/null
+++ b/cadence/genus/config_pnr.tcl
@@ -0,0 +1,105 @@
+# Software settings
+set SW_MULTIPLE_CPUS 20
+
+# Name of top level module
+#set DESIGN_TOP_MODULE "top"
+set DESIGN_TOP_MODULE "ve"
+
+# Paths
+#set PATH_LIB_BASE "/usr/local/cad/stm-cmos28fdsoi-rf-1.0a"
+set PATH_LIB_BASE "/sw/cadence/libraries/CMOS28_FDSOI-2.5.d"
+
+# Files
+set FILE_PADS_WRAPPER ""
+set FILE_PADS_CELLS ""
+set FILE_PADS_ORDERING ""
+set FILE_DUMMY_SOURCE "./ex/top_dummy.v"
+set FILE_DUMMY_SDC "./ex/top_dummy.sdc"
+
+set DECOUPLING_CAPACITANCE 2000000
+
+# Library settings
+set LIB_TRACKS "12";               # Number of tracks in the cell library
+set LIB_TYPE "LL";                 # Cell library type, {LL | LR} 20130411.0
+set LIB_CORE_VERSION "1";          # Core library version {0 | 1} 
+set LIB_CLK_VERSION "5.1-03";      # Clock library version
+set LIB_PR_VERSION "5.3.a-00";     # Place and Route library version
+set LIB_DETAILS "ss28_0.90V_125C"; # Library characterization details
+#
+#set LIB_TRACKS "12"
+#set LIB_TYPE "LR"
+#set LIB_DETAILS "ss28_0.90V_125C"
+#set LIB_CORE_VERSION "5.1-03"
+#set LIB_CLK_VERSION "5.1-03"
+#set LIB_PR_VERSION "5.3.a-00"
+# Currently not used
+#set LIB_IO_STACKUP "6U1X2T8XLB"
+#set LIB_IO_BASIC_VERSION "7.0-02"
+#set LIB_IO_TESTMUX_VERSION "7.1-00"
+
+# Technokit settings
+set TECHNOKIT_VERSION "3.2.a-01"
+set TECHNOKIT_ALT false
+
+# Floorplan settings (um)
+set FLOORPLAN_WIDTH 1712
+set FLOORPLAN_HEIGHT 1712
+set FLOORPLAN_MARGIN 34
+set FLOORPLAN_USE_PADS false
+set FLOORPLAN_WAIT_FOR_MANUAL_INPUT false
+
+# VDD/GND power ring settings
+set POWER_RING_VDD_GND_ENABLE true
+set POWER_RING_VDD_GND_LAYER_TB "IA"
+set POWER_RING_VDD_GND_LAYER_LR "IB"
+set POWER_RING_VDD_GND_SPACING 4
+set POWER_RING_VDD_GND_WIDTH 12
+set POWER_RING_VDD_GND_OFFSET 2
+
+# VDDE/GNDE power ring settings
+set POWER_RING_VDDE_GNDE_ENABLE false
+set POWER_RING_VDDE_GNDE_LAYER_TB "IA"
+set POWER_RING_VDDE_GNDE_LAYER_LR "IB"
+set POWER_RING_VDDE_GNDE_SPACING 4
+set POWER_RING_VDDE_GNDE_WIDTH 12
+set POWER_RING_VDDE_GNDE_OFFSET 2
+
+# VDD/GND vertical power stripes settings
+set POWER_STRIPE_VERT_ENABLE true
+set POWER_STRIPE_VERT_LAYER "M3"
+set POWER_STRIPE_VERT_WIDTH 1.0
+set POWER_STRIPE_VERT_SET_SPACING 0.3
+set POWER_STRIPE_VERT_SET_TO_SET_DISTANCE 20
+set POWER_STRIPE_VERT_START_OFFSET 15
+set POWER_STRIPE_VERT_STOP_OFFSET 7.5
+set POWER_STRIPE_VERT_TOP_LAYER_LIMIT "M2"
+set POWER_STRIPE_VERT_BOTTOM_LAYER_LIMIT "M3"
+
+
+# VDD/GND horizonal power stripes settings
+set POWER_STRIPE_HORIZ_ENABLE true
+set POWER_STRIPE_HORIZ_LAYER "IA"
+set POWER_STRIPE_HORIZ_WIDTH 10.0
+set POWER_STRIPE_HORIZ_SET_SPACING 10
+set POWER_STRIPE_HORIZ_SET_TO_SET_DISTANCE 111
+set POWER_STRIPE_HORIZ_START_OFFSET 64
+set POWER_STRIPE_HORIZ_STOP_OFFSET 32
+set POWER_STRIPE_HORIZ_TOP_LAYER_LIMIT "IA"
+set POWER_STRIPE_HORIZ_BOTTOM_LAYER_LIMIT "IB"
+
+
+# Clock tree settings
+set CLOCK_TREE_EFFORT "medium"
+set CLOCK_TREE_LEAF_BOTTOM_LAYER "M3"
+set CLOCK_TREE_LEAF_TOP_LAYER "M4"
+set CLOCK_TREE_TRUNK_BOTTOM_LAYER "M5"
+set CLOCK_TREE_TRUNK_TOP_LAYER "M6"
+set CLOCK_TREE_TOP_BOTTOM_LAYER "IA"
+set CLOCK_TREE_TOP_TOP_LAYER "IB"
+
+# Routing settings
+set ROUTE_RESET_NET_FIRST true
+#set ROUTE_RESET_NET_NAME "reset_n"
+set ROUTE_RESET_NET_NAME "RST"
+
+
diff --git a/cadence/genus/config_syn.tcl b/cadence/genus/config_syn.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..626705457e686a9823243841eb1fe94597d696cf
--- /dev/null
+++ b/cadence/genus/config_syn.tcl
@@ -0,0 +1,69 @@
+# Paths
+# synth funkar, pnr hittar inte layer LVT
+set PATH_LIB_BASE "/sw/cadence/libraries/CMOS28_FDSOI-2.5.d"; # Base path to cell library
+# testar, LVT verkar finnas
+#set PATH_LIB_BASE "/sw/cadence/libraries/cmos28fdsoi_27a"; # Base path to cell library
+
+#set PATH_SRC_BASE "./ex";                                   # Base path to source files
+set PATH_SRC_BASE "../code/VE-LiU2";                                   # Base path to source files
+
+# Files
+#set FILE_SOURCE_LIST "./ex/$INSTANCE_NAME/sources.txt"; # List of source files
+set FILE_SOURCE_LIST "./ex/sources.txt"; # List of source files
+
+# Library settings
+set LIB_TRACKS "12";               # Number of tracks in the cell library
+set LIB_TYPE "LL";                 # Cell library type, {LL | LR} 20130411.0
+set LIB_CORE_VERSION "1";          # Core library version {0 | 1}
+#set LIB_CLK_VERSION "5.1-03";      # Clock library version
+#set LIB_PR_VERSION "5.3.a-00";     # Place and Route library version
+set LIB_DETAILS "ss28_0.90V_125C"; # Library characterization details
+
+# Technokit settings
+set TECHNOKIT_VERSION "3.2.a-01"; # Technokit version
+
+# Super thread settings
+set SUPER_THREAD_CACHE_SIZE 32000; # Super thread servers chache size (Mb)
+set SUPER_THREAD_SERVERS 8;       # Number of super thread servers to use
+set SUPER_THREAD_DEBUG false;      # Write separate log file for each server
+
+# Generic settings
+set GENERIC_INFORMATION_LEVEL 11;  # {0 to 11}
+set GENERIC_TRACK_FILENAMES true; # {true | false}
+set GENERIC_HDL_LOOP_LIMIT 20000;
+
+# Naming settings
+set NAMING_USE_IF_GENERATE_PREFIX true;  # {true | false}
+set NAMING_USE_FOR_GENERATE_PREFIX true; # {true | false}
+
+# Timing (ns)
+set TIMING_CLOCK_PORT "clk"
+#set TIMING_CLOCK_PORT "CLK_P"
+#set TIMING_CLOCK_PERIOD 1.0
+set TIMING_CLOCK_PERIOD 0.4
+set TIMING_INPUT_DELAY 0
+set TIMING_OUTPUT_DELAY 0
+
+# General synthesis settings
+set SYNTH_AUTO_UNGROUP both;   # {none | both}
+set SYNTH_GENERIC_EFFORT high; # {high | low | medium | express | none}
+set SYNTH_MAP_EFFORT high;     # {high | low | medium | express | none}
+set SYNTH_OPT_EFFORT high;     # {high | low | medium | express | none}
+
+# Physical flow settings (synth-to-placed)
+set PHYSICAL_ENABLE false
+set PHYSICAL_EFFORT high
+set PHYSICAL_UTILIZATION 0.65
+
+# Clock gating
+set CLOCK_GATING_ENABLE true; # {true | false}
+
+# Retiming
+set RETIMING_ENABLE true;   # {true | false}
+set RETIMING_DONT_RETIME {}; # List of registers to avoid moving when retiming
+
+# List of cells to avoid.
+set CELLS_AVOID {"*SDFP*"}
+
+# Multi cycle paths (list of 3 element lists {"from_inst" "to_inst" cycles})
+set MULTI_CYCLE_PATHS {}
diff --git a/cadence/genus/ex/sources.txt b/cadence/genus/ex/sources.txt
new file mode 100644
index 0000000000000000000000000000000000000000..13e1f24fd61bac4bf4b210a15f11c6f6003ab24f
--- /dev/null
+++ b/cadence/genus/ex/sources.txt
@@ -0,0 +1,34 @@
+# This file contains the names of all files used in the design. These files
+# should be located in the folder specified in the folder specified in
+# PATH_SRC_BASE set in settings.tcl.
+
+# VE-LiU2
+vetypes.vhdl
+instructiontypes.vhdl
+lzod.vhdl
+writebuff.vhdl
+ppshift.vhdl
+ppmap1.vhdl
+ctrlmap_acc.vhdl
+ctrlmap_alu.vhdl
+ppadd.vhdl
+accumulatoreven.vhdl
+accumulatorodd.vhdl
+addmul.vhdl
+vearith.vhdl
+memreg.vhdl
+vecore.vhdl
+ve_wctrlpipe.vhdl
+./ldl/ldlinvcontroller.vhdl
+ve_wctrl.vhdl
+
+
+# VE-LIU
+#./VE-LIU/VE.vhdl
+#./VE-LIU/Accumulator.vhdl
+#./VE-LIU/mul.vhdl
+
+
+# r2butterfly
+#./r2butterfly_syn/r2butterfly.vhdl
+#./r2butterfly_syn/r2butterfly_syn.vhdl
diff --git a/cadence/genus/lvs/control.tcl b/cadence/genus/lvs/control.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..2d35d27d7797b26ccefcd03a1fe772c42d54fd0f
--- /dev/null
+++ b/cadence/genus/lvs/control.tcl
@@ -0,0 +1,15 @@
+v2lvs::load_verilog -filename [lindex $argv 1]
+
+set modules [v2lvs::find_module -under [lindex $argv 0]]
+set filename [lindex $argv 2]
+set fileHandle [open $filename "w"]
+foreach m $modules {
+    puts $fileHandle "LVS BOX $m"
+    set ports [v2lvs::get_ports -module $m]
+    if {[llength $ports] == 0} {
+        puts $fileHandle "LVS FILTER $m OPEN LAYOUT"
+    }
+}
+close $fileHandle
+v2lvs::generate_empty_subckts -enable
+exit
diff --git a/cadence/genus/lvs/gen_lvs_box.sh b/cadence/genus/lvs/gen_lvs_box.sh
new file mode 100644
index 0000000000000000000000000000000000000000..b6c96fc3a77595a3e09b44705ae82eed3d2748a2
--- /dev/null
+++ b/cadence/genus/lvs/gen_lvs_box.sh
@@ -0,0 +1,24 @@
+#!/bin/bash
+if [ ! $# -eq 3 ]; then
+    echo "Usage: gen_lvs_box <module name> <input verilog file> <output lvs rules file>"
+    return 1
+fi
+if [ ! -f $2 ]; then
+    echo "Missing input file: $1"
+    return 1
+fi
+if [ ! -d ${3%/*} ] && ([[ $3 == .* ]] || [[ $3 == /* ]]) ; then
+    echo "Invalid path to output file".
+    return 1
+fi
+MODULE_NAME=$1
+INPUT_FILE=$2
+OUTPUT_FILE=$3
+
+set OLD_PATH=$PATH
+PATH=$PATH:/usr/local/cad/calibre-2017.4/aoi_cal_2017.4_19.14/bin
+export MGLS_LICENSE_FILE=5288@129.16.221.235
+export MGC_HOME=/usr/local/cad/calibre-2017.4/aoi_cal_2017.4_19.14
+
+v2lvs -- $MODULE_NAME $INPUT_FILE $OUTPUT_FILE -tcl control.tcl
+set PATH=$OLD_PATH
diff --git a/cadence/genus/pnr.sh b/cadence/genus/pnr.sh
new file mode 100644
index 0000000000000000000000000000000000000000..20c313d38cbbbe28a367f769e7d80728f5812a37
--- /dev/null
+++ b/cadence/genus/pnr.sh
@@ -0,0 +1,29 @@
+#!/bin/bash
+PATH_BASE=$(pwd)
+if [ $# -eq 0 ]; then
+    DESIGN_NAME="default"
+else
+    DESIGN_NAME=$1
+fi
+if [ ! -d "./out/$DESIGN_NAME/syn" ]; then
+    echo "ERROR: No design exists with that name."
+    return 1
+fi
+if [ ! -d "./out/$DESIGN_NAME/pnr" ]; then
+    mkdir ./out/$DESIGN_NAME/pnr
+fi
+cd ./out/$DESIGN_NAME/pnr
+OLD_PATH=$PATH
+
+PATH=$PATH:/usr/local/cad/innovus-17.13.000/bin
+export CDS_LIC_FILE=5280@cadence1.lic.chalmers.se:5280@cadence2.lic.chalmers.se:5280@cadence3.lic.chalmers.se
+ulimit unlimited
+
+module load cadence/innovus-19.10.000
+
+innovus -overwrite -execute "set DESIGN_NAME $DESIGN_NAME; set PATH_BASE $PATH_BASE" -file $PATH_BASE/tcl/pnr.tcl
+unset CDS_LIC_FILE
+PATH=$OLD_PATH
+unset OLD_PATH
+cd $PATH_BASE
+unset PATH_BASE
diff --git a/cadence/genus/power_analysis.sh b/cadence/genus/power_analysis.sh
new file mode 100644
index 0000000000000000000000000000000000000000..9ef896f25518959f908464a4b37296c6ef7632c4
--- /dev/null
+++ b/cadence/genus/power_analysis.sh
@@ -0,0 +1,69 @@
+PATH_BAS=$(pwd)
+
+eval `/sw/modules/bin/cmod sh add cadence/genus-19.10.000` # Module for genus
+eval `/sw/modules/bin/cmod sh add mentor/modeltech10.6d` # Module for modelsim
+
+FILE_LIB_CORE=/sw/cadence/libraries/CMOS28_FDSOI-2.5.d/C28SOI_SC_12_CORE_LL@2.2@20131004.0/behaviour/verilog/C28SOI_SC_12_CORE_LL.v
+FILE_LIB_CLK=/sw/cadence/libraries/CMOS28_FDSOI-2.5.d/C28SOI_SC_12_CLK_LL@2.2@20131004.0/behaviour/verilog/C28SOI_SC_12_CLK_LL.v
+#{C28SOI_SC_12_CORE_LL_allpins.v | C28SOI_SC_12_CORE_LL_emul.v | C28SOI_SC_12_CORE_LL_fm.v | C28SOI_SC_12_CORE_LL_tmax.v | C28SOI_SC_12_CORE_LL.v | C28SOI_SC_12_CORE_LL.verilog.map}
+# What is difference among above library files??
+
+gunzip -f $PATH_BAS/out/$1/syn/$1.sdf.gz
+
+FILE_NETLIST=$PATH_BAS/out/$1/syn/$1.v
+
+FILE_SDF=$PATH_BAS/out/$1/syn/$1.sdf
+
+FILE_TESTBENCH=$PATH_BAS/ex/$2/test_bench.sv
+
+TESTBENCH_ENTITY=top_level
+
+SCOPE=$2
+
+
+
+# Save old path and current directory
+
+OLD_PATH=$PATH
+
+CURR_DIR=${PWD}
+
+
+echo "SCRIPT : VCD Generation starts"
+
+# Check if run directory exists, otherwise create it.
+
+[ ! -d run ] && mkdir run
+
+cd run
+
+rm -fr INCA_libs
+
+rm vsim_booth.do
+(echo vlib work_power;
+echo vlog -work work_power -novopt $FILE_LIB_CORE
+echo vlog -work work_power -novopt $FILE_LIB_CLK
+echo vlog -work work_power  $FILE_NETLIST
+echo vlog -work work_power  $FILE_TESTBENCH
+echo vsim -wlf /tmp/vsim.wlf -sdfmax /top_level/$SCOPE/=$FILE_SDF -sdfreport=$PATH_BAS/out/$1/syn/sdfreport.txt -t ps work_power.top_level;
+echo vcd file $PATH_BAS/out/$1/syn/$1.vcd;
+echo vcd add -r /$TESTBENCH_ENTITY/$SCOPE/*;
+echo onbreak \{resume\};
+echo radix d;
+echo run -a;
+echo quit -f) > vsim_booth.do
+
+vsim -c -do vsim_booth.do
+
+cd $PATH_BAS
+
+echo "SCRIPT : VCD Generation done"
+
+genus -overwrite -execute "set DESIGN_NAME $1; set INSTANCE_NAME $2" -file $PATH_BAS/power_analysis.tcl
+
+gzip $FILE_SDF
+gzip $PATH_BAS/out/$1/syn/$1.vcd
+
+PATH=$OLD_PATH
+
+unset OLD_PATH
diff --git a/cadence/genus/power_analysis.tcl b/cadence/genus/power_analysis.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..1f8a35abfb984b101a75824fee863d9926165fd6
--- /dev/null
+++ b/cadence/genus/power_analysis.tcl
@@ -0,0 +1,17 @@
+
+puts "\nSCRIPT  : Starting power analysis.\n"
+
+
+
+cd ./out/$DESIGN_NAME/syn
+
+source ./session/$DESIGN_NAME.genus_setup.tcl
+
+read_vcd $DESIGN_NAME.vcd
+
+report_power > reports/power.vcd.txt
+
+
+puts "\nSCRIPT  : Power analysis finished.\n"
+
+exit
diff --git a/cadence/genus/synth.sh b/cadence/genus/synth.sh
new file mode 100644
index 0000000000000000000000000000000000000000..6d9c65369ce58d86449e9cf80ce8e17b6ea6313b
--- /dev/null
+++ b/cadence/genus/synth.sh
@@ -0,0 +1,44 @@
+#!/bin/bash
+PATH_BASE=$(pwd)
+if [ -z "$1" ]; then
+  echo "SCRIPT  :  No design name supplied"
+  exit 1
+else
+    DESIGN_NAME=$1
+fi
+if [ -z "$2" ]; then
+  echo "SCRIPT  :  No instance name supplied"
+  exit 1
+else
+    INSTANCE_NAME=$2
+fi
+if [ ! -d "./out" ]; then
+    mkdir ./out
+fi
+if [ ! -d "./out/$DESIGN_NAME" ]; then
+    mkdir ./out/$DESIGN_NAME
+fi
+if [ ! -d "./out/$DESIGN_NAME/syn" ]; then
+    mkdir ./out/$DESIGN_NAME/syn
+fi
+cd ./out/$DESIGN_NAME/syn
+OLD_PATH=$PATH
+
+#eval `/sw/modules/bin/cmod sh add cadence/genus-19.10.000`
+#eval `module load cadence/genus-19.10.000`
+#module load cadence/genus-19.10.000
+module load cadence/genus-21.10.000
+
+echo "SCRIPT  :  Genus start with Design name = $DESIGN_NAME, Instance name = $INSTANCE_NAME"
+
+genus -no_gui -overwrite -execute "set DESIGN_NAME $DESIGN_NAME; set PATH_BASE $PATH_BASE; set INSTANCE_NAME $INSTANCE_NAME" -file $PATH_BASE/tcl/synth.tcl
+
+cd $PATH_BASE
+
+#echo "SCRIPT  :  Power analysis starts with Design name = $DESIGN_NAME, Instance name = $INSTANCE_NAME"
+#source $PATH_BASE/power_analysis.sh $DESIGN_NAME $INSTANCE_NAME
+
+PATH=$OLD_PATH
+unset OLD_PATH
+cd $PATH_BASE
+unset PATH_BASE
diff --git a/cadence/genus/tcl/fp.tcl b/cadence/genus/tcl/fp.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..fb10cdce385028e5c64f34129931a06d57171e7e
--- /dev/null
+++ b/cadence/genus/tcl/fp.tcl
@@ -0,0 +1,91 @@
+# Load settings from  file
+source $PATH_BASE/config_pnr.tcl
+
+# Setup logging
+setMessageLimit 10
+
+# Set paths
+set PATH_LIB_CORE       "$PATH_LIB_BASE/C28SOI_SC_${LIB_TRACKS}_CORE_${LIB_TYPE}/${LIB_CORE_VERSION}"
+set PATH_LIB_CLK        "$PATH_LIB_BASE/C28SOI_SC_${LIB_TRACKS}_CLK_${LIB_TYPE}/${LIB_CLK_VERSION}"
+set PATH_LIB_PR         "$PATH_LIB_BASE/C28SOI_SC_${LIB_TRACKS}_PR_${LIB_TYPE}/${LIB_PR_VERSION}"
+set PATH_TECHNOKIT      "$PATH_LIB_BASE/Foundation_Cadence_TechnoKit_cmos028FDSOI_6U1x_2T8x_LB/${TECHNOKIT_VERSION}"
+set FILE_SDC            "$PATH_BASE/$FILE_DUMMY_SDC"
+if {![string match "/*" $FILE_PADS_WRAPPER]} {
+    set FILE_PADS_WRAPPER "$PATH_BASE/$FILE_PADS_WRAPPER"
+}
+
+# Multiple CPU usage
+setMultiCpuUsage -localCpu $SW_MULTIPLE_CPUS
+setDistributeHost -local
+
+# Settings specified by ST
+setDesignMode -process 28
+setAnalysisMode -analysisType onChipVariation
+set_global timing_cppr_transition_sense same_transition_expanded
+set_global timing_use_latch_early_launch_edge false
+set_global timing_enable_early_late_data_slews_for_setuphold_mode_checks false
+set_global timing_allow_input_delay_on_clock_source true
+set_global timing_enable_pessimistic_cppr_for_reconvergent_clock_paths true
+set_global timing_enable_power_ground_constants true
+setViaGenMode -optimize_cross_via true
+
+# Set hierachy delimiter
+set defHierChar /
+
+# Specify netlist file and name of top module
+if {$FLOORPLAN_USE_PADS} {
+    set init_verilog [list $PATH_BASE/$FILE_DUMMY_SOURCE $FILE_PADS_WRAPPER]
+} else {
+    set init_verilog $PATH_BASE/$FILE_DUMMY_SOURCE
+}
+set init_top_cell $DESIGN_TOP_MODULE
+set init_design_settop 1
+set init_design_netlisttype Verilog
+
+# Specify LEF files
+set LEF_FILES {}
+lappend LEF_FILES $PATH_TECHNOKIT/LEF/technology.lef
+lappend LEF_FILES $PATH_TECHNOKIT/LEF/viarule_generate.lef
+lappend LEF_FILES $PATH_TECHNOKIT/LEF/sites.lef
+lappend LEF_FILES $PATH_TECHNOKIT/LEF/lib_property.lef
+lappend LEF_FILES $PATH_LIB_CORE/CADENCE/LEF/C28SOI_SC_${LIB_TRACKS}_CORE_${LIB_TYPE}_soc.lef 
+lappend LEF_FILES $PATH_LIB_CLK/CADENCE/LEF/C28SOI_SC_${LIB_TRACKS}_CLK_${LIB_TYPE}_soc.lef
+lappend LEF_FILES $PATH_LIB_PR/CADENCE/LEF/C28SOI_SC_${LIB_TRACKS}_PR_${LIB_TYPE}_soc.lef
+set init_lef_file $LEF_FILES
+
+set init_design_uniquify 1
+set init_mmmc_file "$PATH_BASE/tcl/pnr/mmmc.tcl"
+
+# Empty modules should be retained
+set init_import_mode {-treatUndefinedCellAsBbox 0 -keepEmptyModule 1}
+
+# Specify power nets
+set init_pwr_net {vdd vdde}
+set init_gnd_net {gnd gnde}
+
+# Don't use OpenAccess reference libraries
+set init_oa_search_lib {}
+
+# Initialize design
+init_design
+
+# Add pads and die corners
+if {$FLOORPLAN_USE_PADS} {
+    loadECO $PATH_BASE/$FILE_PADS_CELLS
+}
+
+# Setup grid
+setPreference ConstraintUserXGrid 0.1
+setPreference ConstraintUserXOffset 0
+setPreference ConstraintUserYGrid 0.1
+setPreference ConstraintUserYOffset 0
+snapFPlanIO -usergrid
+
+redraw
+
+# Floorplan
+source $PATH_BASE/tcl/pnr/floorplan.tcl
+
+fit
+
+defOut -floorplan ${DESIGN_NAME}_fp.def
diff --git a/cadence/genus/tcl/pnr.tcl b/cadence/genus/tcl/pnr.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..d39e99a262e77bb510a298bdbd6eeadbb73438e5
--- /dev/null
+++ b/cadence/genus/tcl/pnr.tcl
@@ -0,0 +1,44 @@
+Puts "\nSCRIPT  : Starting init at: [clock format [clock seconds] -format {%x %X}].\n"
+source $PATH_BASE/tcl/pnr/init.tcl
+Puts "\nSCRIPT  : Finished init."
+
+Puts "\nSCRIPT  : Starting floorplan at: [clock format [clock seconds] -format {%x %X}].\n"
+source $PATH_BASE/tcl/pnr/floorplan.tcl
+Puts "\nSCRIPT  : Finished floorplan."
+saveDesign ${DESIGN_NAME}_floorplan
+
+Puts "\nSCRIPT  : Starting place at: [clock format [clock seconds] -format {%x %X}].\n"
+source $PATH_BASE/tcl/pnr/place.tcl
+Puts "\nSCRIPT  : Finished place."
+saveDesign ${DESIGN_NAME}_place
+
+Puts "\nSCRIPT  : Starting power at: [clock format [clock seconds] -format {%x %X}].\n"
+source $PATH_BASE/tcl/pnr/power.tcl
+Puts "\nSCRIPT  : Finished power."
+saveDesign ${DESIGN_NAME}_power
+
+Puts "\nSCRIPT  : Starting clock at: [clock format [clock seconds] -format {%x %X}].\n"
+source $PATH_BASE/tcl/pnr/clock.tcl
+saveDesign ${DESIGN_NAME}_clock
+
+Puts "\nSCRIPT  : Finished clock."
+Puts "\nSCRIPT  : Starting route at: [clock format [clock seconds] -format {%x %X}].\n"
+source $PATH_BASE/tcl/pnr/route.tcl
+saveDesign ${DESIGN_NAME}_route
+
+Puts "\nSCRIPT  : Finished route."
+Puts "\nSCRIPT  : Starting fillers at: [clock format [clock seconds] -format {%x %X}].\n"
+source $PATH_BASE/tcl/pnr/fillers.tcl
+saveDesign ${DESIGN_NAME}_fillers
+
+Puts "\nSCRIPT  : Finished fillers."
+Puts "\nSCRIPT  : Starting checks at: [clock format [clock seconds] -format {%x %X}].\n"
+source $PATH_BASE/tcl/pnr/checks.tcl
+saveDesign ${DESIGN_NAME}_checks
+
+Puts "\nSCRIPT  : Finished checks."
+Puts "\nSCRIPT  : Starting export at: [clock format [clock seconds] -format {%x %X}].\n"
+source $PATH_BASE/tcl/pnr/export.tcl
+saveDesign ${DESIGN_NAME}_export
+
+Puts "\nSCRIPT  : Finished export at: [clock format [clock seconds] -format {%x %X}].\n"
diff --git a/cadence/genus/tcl/pnr/checks.tcl b/cadence/genus/tcl/pnr/checks.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..eef6985ca7bdd1ab82bad8ccc6bd660c64354fc5
--- /dev/null
+++ b/cadence/genus/tcl/pnr/checks.tcl
@@ -0,0 +1,3 @@
+verify_drc
+verifyConnectivity -noSoftPGConnect
+verifyProcessAntenna
diff --git a/cadence/genus/tcl/pnr/clock.tcl b/cadence/genus/tcl/pnr/clock.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..89d76a06c07b596e6dab7934b99ed359d734dcda
--- /dev/null
+++ b/cadence/genus/tcl/pnr/clock.tcl
@@ -0,0 +1,54 @@
+# Avoid this cell, according to Kevin
+setDontUse C12T28SOI_LR_CNBFX133_P0 true
+
+# Pre-CTS optimization
+setTrialRouteMode -maxRouteLayer 8 
+setOptMode -fixCap true -fixTran true -fixFanoutLoad false
+optDesign -preCTS
+
+# Define in which layers to route the clock three
+create_route_type -name leaf_type  \
+-bottom_preferred_layer $CLOCK_TREE_LEAF_BOTTOM_LAYER \
+-top_preferred_layer $CLOCK_TREE_LEAF_TOP_LAYER
+create_route_type -name trunk_type \
+-bottom_preferred_layer $CLOCK_TREE_TRUNK_BOTTOM_LAYER  \
+-top_preferred_layer $CLOCK_TREE_TRUNK_TOP_LAYER \
+-shield_net gnd -bottom_shield_layer $CLOCK_TREE_TRUNK_BOTTOM_LAYER
+create_route_type -name top_type \
+-bottom_preferred_layer $CLOCK_TREE_TOP_BOTTOM_LAYER \
+-top_preferred_layer $CLOCK_TREE_TOP_TOP_LAYER \
+-shield_net gnd -bottom_shield_layer $CLOCK_TREE_TOP_BOTTOM_LAYER
+set_ccopt_property route_type -net_type leaf  leaf_type
+set_ccopt_property route_type -net_type trunk trunk_type
+set_ccopt_property route_type -net_type top   top_type
+
+# Clock tree settings
+set bufferCells [get_db [get_db lib_cells *CNBF*_P0] .base_name -unique] 
+set inverterCells [get_db [get_db lib_cells *CNIV*_P0] .base_name -unique] 
+set clockGatingCells [get_db [get_db lib_cells *CNHLS*_P0] .base_name -unique] 
+# Remove inverter cells with a drive strength < 9
+foreach i $inverterCells {
+    regexp (?:CNIVX)(.*)(?:_P) $i -> driveStrength
+    if {$driveStrength < 9} {
+        set inverterCells [lreplace $inverterCells [lsearch $inverterCells $i] [lsearch $inverterCells $i]]
+    }
+}
+set_ccopt_property buffer_cells $bufferCells 
+set_ccopt_property inverter_cells $inverterCells
+set_ccopt_property clock_gating_cells $clockGatingCells
+set_ccopt_property use_inverters true
+set_ccopt_property effort $CLOCK_TREE_EFFORT
+unset bufferCells
+unset inverterCells
+unset clockGatingCells
+
+# Generate clock tree
+create_ccopt_clock_tree_spec
+ccopt_design -cts
+
+setOptMode -maxLength 900
+optDesign -postCTS
+optDesign -postCTS -hold
+
+deleteTrialRoute
+redraw
diff --git a/cadence/genus/tcl/pnr/export.tcl b/cadence/genus/tcl/pnr/export.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..f445fbd7308ba5420e072b5f85e931eafa3b54e3
--- /dev/null
+++ b/cadence/genus/tcl/pnr/export.tcl
@@ -0,0 +1,16 @@
+#saveNetlist -includePowerGround ${DESIGN_NAME}_final.v
+#saveNetlist -excludeLeafCell -includePhysicalInst ${DESIGN_NAME}_physical.v
+saveNetlist -phys ${DESIGN_NAME}_phys.v
+saveNetlist -includePowerGround ${DESIGN_NAME}_pg.v
+saveNetlist -includePhysicalInst ${DESIGN_NAME}_pi.
+saveNetlist -excludeLeafCell ${DESIGN_NAME}_elc.v
+saveNetlist -flat -phys ${DESIGN_NAME}_flph.v
+suspend
+
+rcOut -rc_corner default_rc_corner_worst -spef ${DESIGN_NAME}_final.spef
+write_sdf ${DESIGN_NAME}_final.sdf
+#streamOut ${DESIGN_NAME}_final.gds -mapFile $PATH_TECHNOKIT/EDI/map_out -libName DesignLib -structureName $DESIGN_TOP_MODULE -units 1000 -mode ALL
+streamOut ${DESIGN_NAME}_final.gds -mapFile $PATH_TECHNOKIT/EDI/mapOut -libName DesignLib -structureName $DESIGN_TOP_MODULE -units 1000 -mode ALL
+
+
+
diff --git a/cadence/genus/tcl/pnr/fillers.tcl b/cadence/genus/tcl/pnr/fillers.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..1f850a29ac8fac0785acd7ddeb2e2a3e55a7822c
--- /dev/null
+++ b/cadence/genus/tcl/pnr/fillers.tcl
@@ -0,0 +1,50 @@
+if {$LIB_TYPE=="LL"} {
+    # Decoupling capacitors.
+    #addDeCapCellCandidates C12T28SOI_LLL_DECAPXT4 2.43 
+    addDeCapCellCandidates C12T28SOI_LL_DECAPXT4 2.43 
+    addDeCapCellCandidates C12T28SOI_LL_DECAPXT8 7.29 
+    #addDeCapCellCandidates C12T28SOI_LL_PDECAP16 20.3
+    addDeCapCellCandidates C12T28SOI_LL_DECAPXT16 20.3
+    #addDeCapCellCandidates C12T28SOI_LL_PDECAP32 45.0 
+    addDeCapCellCandidates C12T28SOI_LL_DECAPXT32 45.0 
+    #addDeCapCellCandidates C12T28SOI_LL_PDECAP64 91.0 
+    addDeCapCellCandidates C12T28SOI_LL_DECAPXT64 91.0 
+    addDeCap -totCap $DECOUPLING_CAPACITANCE -prefix DECAP -effort low 
+
+    # Filler Cell Between Std-Cells 
+    addFiller -prefix FILLER -cell \
+        C12T28SOI_LL_FILLERPFOP64 \
+        C12T28SOI_LL_FILLERPFOP32 \
+        C12T28SOI_LL_FILLERPFOP16 \
+        C12T28SOI_LL_FILLERPFOP8 \
+        C12T28SOI_LL_FILLERPFOP4 \
+        C12T28SOI_LL_FILLERPFOP2 \
+        C12T28SOI_LL_FILLERCELL1
+} elseif {$LIB_TYPE=="LR"} {
+    # Decoupling capacitors.
+    addDeCapCellCandidates C12T28SOI_LR_DECAPXT4 2.25 
+    addDeCapCellCandidates C12T28SOI_LR_DECAPXT8 5.86 
+    addDeCapCellCandidates C12T28SOI_LR_DECAPXT16 13.1
+    addDeCapCellCandidates C12T28SOI_LR_DECAPXT32 27.4 
+    addDeCapCellCandidates C12T28SOI_LR_DECAPXT64 54.9 
+    addDeCap -totCap $DECOUPLING_CAPACITANCE -prefix DECAP -effort low 
+
+    # Filler Cell Between Std-Cells 
+    addFiller -prefix FILLER -cell \
+        C12T28SOI_LR_FILLERPFOP64 \
+        C12T28SOI_LR_FILLERPFOP32 \
+        C12T28SOI_LR_FILLERPFOP16 \
+        C12T28SOI_LR_FILLERPFOP8 \
+        C12T28SOI_LR_FILLERPFOP4 \
+        C12T28SOI_LR_FILLERPFOP2 \
+        C12T28SOI_LR_FILLERCELL1
+}
+
+
+globalNetConnect vdd -type pgpin -pin {vdd} -inst * -module {}
+globalNetConnect gnd -type pgpin -pin {gnd} -inst * -module {}
+globalNetConnect vdd -type pgpin -pin {vdds} -inst * -module {}
+globalNetConnect gnd -type pgpin -pin {gnds} -inst * -module {}
+
+applyGlobalNets
+
diff --git a/cadence/genus/tcl/pnr/floorplan.tcl b/cadence/genus/tcl/pnr/floorplan.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..836ebc96ad05352f0b4ffb3a83b1d1f0b4b5e3d3
--- /dev/null
+++ b/cadence/genus/tcl/pnr/floorplan.tcl
@@ -0,0 +1,87 @@
+# Set core size
+floorPlan -adjustToSite -site CORE12T -s $FLOORPLAN_WIDTH $FLOORPLAN_HEIGHT \
+    $FLOORPLAN_MARGIN $FLOORPLAN_MARGIN $FLOORPLAN_MARGIN $FLOORPLAN_MARGIN
+snapFPlanIO -usergrid
+
+# Load pad/pin placement
+if {$FILE_PADS_ORDERING != ""} {
+    loadIoFile $PATH_BASE/$FILE_PADS_ORDERING
+}
+
+if {$FLOORPLAN_WAIT_FOR_MANUAL_INPUT} {
+    Puts "\nSCRIPT  : Waiting for manual input of floorplan at [clock format [clock seconds] -format {%x %X}].\n"
+    suspend
+    Puts "\nSCRIPT  : Resuming script at [clock format [clock seconds] -format {%x %X}].\n"
+}
+
+# Add power rings
+if {$POWER_RING_VDD_GND_ENABLE} {
+    addRing -nets {gnd vdd}\
+        -around power_domain \
+        -layer [list top $POWER_RING_VDD_GND_LAYER_TB bottom $POWER_RING_VDD_GND_LAYER_TB \
+                    left $POWER_RING_VDD_GND_LAYER_LR right $POWER_RING_VDD_GND_LAYER_LR] \
+        -spacing $POWER_RING_VDD_GND_SPACING \
+        -width $POWER_RING_VDD_GND_WIDTH \
+        -offset $POWER_RING_VDD_GND_OFFSET 
+}
+
+if {$POWER_RING_VDDE_GNDE_ENABLE} {
+    addRing -nets {gnde vdde }  \
+        -around power_domain \
+        -follow io \
+        -layer [list top $POWER_RING_VDDE_GNDE_LAYER_TB bottom $POWER_RING_VDDE_GNDE_LAYER_TB \
+                    left $POWER_RING_VDDE_GNDE_LAYER_LR right $POWER_RING_VDDE_GNDE_LAYER_LR] \
+        -spacing $POWER_RING_VDDE_GNDE_SPACING \
+        -width $POWER_RING_VDDE_GNDE_WIDTH \
+        -offset $POWER_RING_VDDE_GNDE_OFFSET 
+}
+
+# Add power stripes
+if {$POWER_STRIPE_VERT_ENABLE} {
+    addStripe -nets {gnd vdd} \
+        -layer $POWER_STRIPE_VERT_LAYER  \
+        -width $POWER_STRIPE_VERT_WIDTH  \
+        -spacing $POWER_STRIPE_VERT_SET_SPACING \
+        -set_to_set_distance $POWER_STRIPE_VERT_SET_TO_SET_DISTANCE \
+        -start_offset $POWER_STRIPE_VERT_START_OFFSET \
+        -stop_offset $POWER_STRIPE_VERT_STOP_OFFSET \
+        -block_ring_top_layer_limit $POWER_STRIPE_VERT_TOP_LAYER_LIMIT \
+        -block_ring_bottom_layer_limit $POWER_STRIPE_VERT_BOTTOM_LAYER_LIMIT \
+        -padcore_ring_top_layer_limit $POWER_STRIPE_VERT_TOP_LAYER_LIMIT \
+        -padcore_ring_bottom_layer_limit $POWER_STRIPE_VERT_BOTTOM_LAYER_LIMIT 
+}
+if {$POWER_STRIPE_HORIZ_ENABLE} {
+    addStripe -nets {gnd vdd} \
+        -layer $POWER_STRIPE_HORIZ_LAYER  \
+        -width $POWER_STRIPE_HORIZ_WIDTH  \
+        -spacing $POWER_STRIPE_HORIZ_SET_SPACING \
+        -set_to_set_distance $POWER_STRIPE_HORIZ_SET_TO_SET_DISTANCE \
+        -start_offset $POWER_STRIPE_HORIZ_START_OFFSET \
+        -stop_offset $POWER_STRIPE_HORIZ_STOP_OFFSET \
+        -block_ring_top_layer_limit $POWER_STRIPE_HORIZ_TOP_LAYER_LIMIT \
+        -block_ring_bottom_layer_limit $POWER_STRIPE_HORIZ_BOTTOM_LAYER_LIMIT \
+        -padcore_ring_top_layer_limit $POWER_STRIPE_HORIZ_TOP_LAYER_LIMIT \
+        -padcore_ring_bottom_layer_limit $POWER_STRIPE_HORIZ_BOTTOM_LAYER_LIMIT \
+        -direction horizontal
+}
+
+# Place welltps 
+addWellTap -cell C12T28SOI_${LIB_TYPE}_FILLERNPW4 -checkerboard -cellInterval 100 -prefix WELLTAP -inRowOffset 1
+
+# Place endcap cells
+set endcap_cell_list [get_db [get_db lib_cells *FILLERPFOP*] .base_name -unique]
+lappend endcap_cell_list "C12T28SOI_${LIB_TYPE}_FILLERCELL1"
+
+setEndCapMode -prefix ENDCAP_TOP_BOTTOM -bottomEdge $endcap_cell_list -topEdge $endcap_cell_list
+addEndCap
+
+
+setEndCapMode -prefix ENDCAP_LEFT_RIGHT \
+    -leftEdge [get_db [get_db lib_cells *FILLERPFOP2*] .base_name -unique] \
+    -rightEdge [get_db [get_db lib_cells *FILLERPFOP2*] .base_name -unique]
+addEndCap
+
+verify_drc
+clearDrc
+
+redraw
diff --git a/cadence/genus/tcl/pnr/init.tcl b/cadence/genus/tcl/pnr/init.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..e8b18348962bc6b7faaf930683469ec16599093a
--- /dev/null
+++ b/cadence/genus/tcl/pnr/init.tcl
@@ -0,0 +1,102 @@
+# Load settings from  file
+source $PATH_BASE/config_pnr.tcl
+
+# Setup logging
+setMessageLimit 10
+
+# Set paths
+#set PATH_LIB_CORE       "$PATH_LIB_BASE/C28SOI_SC_${LIB_TRACKS}_CORE_${LIB_TYPE}/${LIB_CORE_VERSION}"
+#set PATH_LIB_CLK        "$PATH_LIB_BASE/C28SOI_SC_${LIB_TRACKS}_CLK_${LIB_TYPE}/${LIB_CLK_VERSION}"
+#set PATH_LIB_PR         "$PATH_LIB_BASE/C28SOI_SC_${LIB_TRACKS}_PR_${LIB_TYPE}/${LIB_PR_VERSION}"
+set PATH_LIB_CORE       "$PATH_LIB_BASE/C28SOI_SC_${LIB_TRACKS}_CORE_${LIB_TYPE}@2.2@20131004.0"
+set PATH_LIB_CLK        "$PATH_LIB_BASE/C28SOI_SC_${LIB_TRACKS}_CLK_${LIB_TYPE}@2.2@20131004.0"
+set PATH_LIB_PR         "$PATH_LIB_BASE/C28SOI_SC_${LIB_TRACKS}_PR_${LIB_TYPE}@2.1@20131028.0"
+#set PATH_TECHNOKIT      "$PATH_LIB_BASE/Foundation_Cadence_TechnoKit_cmos028FDSOI_6U1x_2T8x_LB/${TECHNOKIT_VERSION}"
+set PATH_TECHNOKIT "$PATH_LIB_BASE/CadenceTechnoKit_cmos028FDSOI_6U1x_2U2x_2T8x_LB_LowPower@1.0.1@20121114.0"
+set PATH_REPORTS        "$PATH_BASE/out/$DESIGN_NAME/pnr/reports"
+set FILE_SDC            "$PATH_BASE/out/$DESIGN_NAME/syn/$DESIGN_NAME.sdc.gz"
+
+if {![string match "/*" $FILE_PADS_WRAPPER]} {
+    set FILE_PADS_WRAPPER "$PATH_BASE/$FILE_PADS_WRAPPER"
+}
+
+# Multiple CPU usage
+setMultiCpuUsage -localCpu $SW_MULTIPLE_CPUS
+setDistributeHost -local
+
+# Settings specified by ST
+setDesignMode -process 28
+setAnalysisMode -analysisType onChipVariation
+set_global timing_cppr_transition_sense same_transition_expanded
+set_global timing_use_latch_early_launch_edge false
+set_global timing_enable_early_late_data_slews_for_setuphold_mode_checks false
+set_global timing_allow_input_delay_on_clock_source true
+set_global timing_enable_pessimistic_cppr_for_reconvergent_clock_paths true
+set_global timing_enable_power_ground_constants true
+setViaGenMode -optimize_cross_via true
+
+# Set hierachy delimiter
+set defHierChar /
+
+# Specify netlist file and name of top module
+if {$FLOORPLAN_USE_PADS} {
+    set init_verilog [list $PATH_BASE/out/${DESIGN_NAME}/syn/${DESIGN_NAME}.v $FILE_PADS_WRAPPER]
+} else {
+    set init_verilog $PATH_BASE/out/${DESIGN_NAME}/syn/${DESIGN_NAME}.v
+}
+set init_top_cell $DESIGN_TOP_MODULE
+set init_design_settop 1
+set init_design_netlisttype Verilog
+
+# Specify LEF files
+set LEF_FILES {}
+if {$TECHNOKIT_ALT} {
+    lappend LEF_FILES $PATH_TECHNOKIT/LEF/technology_alternative.lef
+} else {
+    #lappend LEF_FILES $PATH_TECHNOKIT/LEF/technology.lef
+    lappend LEF_FILES /sw/cadence/libraries/cmos28fdsoi_27a/Foundation_Cadence_TechnoKit_cmos028FDSOI_6U1x_2U2x_2T8x_LB/2.8.b-00/LEF/technology.lef
+}
+lappend LEF_FILES $PATH_TECHNOKIT/LEF/viarule_generate.lef
+#lappend LEF_FILES $PATH_TECHNOKIT/LEF/sites.lef
+lappend LEF_FILES /sw/cadence/libraries/CMOS28_FDSOI-2.5.d/SiteDefKit_cmos28@1.4@20120720.0/LEF/sites.lef
+#lappend LEF_FILES $PATH_TECHNOKIT/LEF/lib_property.lef
+lappend LEF_FILES /sw/cadence/libraries/CMOS28_FDSOI-2.5.d/SiteDefKit_cmos28@1.4@20120720.0/LEF/lib_property.lef
+#
+lappend LEF_FILES $PATH_LIB_CORE/CADENCE/LEF/C28SOI_SC_${LIB_TRACKS}_CORE_${LIB_TYPE}_soc.lef 
+lappend LEF_FILES $PATH_LIB_CLK/CADENCE/LEF/C28SOI_SC_${LIB_TRACKS}_CLK_${LIB_TYPE}_soc.lef
+lappend LEF_FILES $PATH_LIB_PR/CADENCE/LEF/C28SOI_SC_${LIB_TRACKS}_PR_${LIB_TYPE}_soc.lef
+set init_lef_file $LEF_FILES
+
+set init_design_uniquify 1
+set init_mmmc_file "$PATH_BASE/tcl/pnr/mmmc.tcl"
+# Empty modules should be retained
+set init_import_mode {-treatUndefinedCellAsBbox 0 -keepEmptyModule 1}
+
+# Specify power nets
+set init_pwr_net {vdd vdde}
+set init_gnd_net {gnd gnde}
+
+# Don't use OpenAccess reference libraries
+set init_oa_search_lib {}
+
+# Initialize design
+init_design
+
+# Add pads and die corners
+if {$FLOORPLAN_USE_PADS} {
+    loadECO $PATH_BASE/$FILE_PADS_CELLS
+}
+
+# Don't use cells with poly bias.
+set_dont_use [get_lib_cells {*_P4*}]
+set_dont_use [get_lib_cells {*_P16*}]
+set_dont_use [get_lib_cells {*_P10*}]
+
+# Setup grid
+setPreference ConstraintUserXGrid 0.1
+setPreference ConstraintUserXOffset 0
+setPreference ConstraintUserYGrid 0.1
+setPreference ConstraintUserYOffset 0
+snapFPlanIO -usergrid
+
+redraw
diff --git a/cadence/genus/tcl/pnr/mmmc.tcl b/cadence/genus/tcl/pnr/mmmc.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..10a8cd1c7a12e26ee836b5f03569c6e71316966c
--- /dev/null
+++ b/cadence/genus/tcl/pnr/mmmc.tcl
@@ -0,0 +1,51 @@
+# Load SDC file from synthesis
+create_constraint_mode -name default_constraint_mode -sdc_files $FILE_SDC
+
+# Create corners
+if { $LIB_TYPE == "LR" } {
+    set slow_libs {}
+    lappend slow_libs $PATH_LIB_CORE/libs/C28SOI_SC_${LIB_TRACKS}_CORE_${LIB_TYPE}_ss28_0.90V_125C.lib
+    lappend slow_libs $PATH_LIB_CLK/libs/C28SOI_SC_${LIB_TRACKS}_CLK_${LIB_TYPE}_ss28_0.90V_125C.lib
+    lappend slow_libs $PATH_LIB_PR/libs/C28SOI_SC_${LIB_TRACKS}_PR_${LIB_TYPE}_ss28_0.90V_125C.lib
+    set fast_libs {}
+    lappend fast_libs $PATH_LIB_CORE/libs/C28SOI_SC_${LIB_TRACKS}_CORE_${LIB_TYPE}_ff28_1.00V_m40C.lib
+    lappend fast_libs $PATH_LIB_CLK/libs/C28SOI_SC_${LIB_TRACKS}_CLK_${LIB_TYPE}_ff28_1.00V_m40C.lib
+    lappend fast_libs $PATH_LIB_PR/libs/C28SOI_SC_${LIB_TRACKS}_PR_${LIB_TYPE}_ff28_1.00V_m40C.lib
+    create_library_set -name default_libset_max -timing $slow_libs
+    create_library_set -name default_libset_min -timing $fast_libs
+
+} else {
+    set slow_libs {}
+    lappend slow_libs $PATH_LIB_CORE/libs/C28SOI_SC_${LIB_TRACKS}_CORE_${LIB_TYPE}_ss28_0.90V_0.00V_0.00V_0.00V_125C.lib
+    lappend slow_libs $PATH_LIB_CLK/libs/C28SOI_SC_${LIB_TRACKS}_CLK_${LIB_TYPE}_ss28_0.90V_0.00V_0.00V_0.00V_125C.lib
+    lappend slow_libs $PATH_LIB_PR/libs/C28SOI_SC_${LIB_TRACKS}_PR_${LIB_TYPE}_ss28_0.90V_0.00V_0.00V_0.00V_125C.lib
+    set fast_libs {}
+    lappend fast_libs $PATH_LIB_CORE/libs/C28SOI_SC_${LIB_TRACKS}_CORE_${LIB_TYPE}_ff28_1.00V_0.00V_0.00V_0.00V_m40C.lib
+    lappend fast_libs $PATH_LIB_CLK/libs/C28SOI_SC_${LIB_TRACKS}_CLK_${LIB_TYPE}_ff28_1.00V_0.00V_0.00V_0.00V_m40C.lib
+    lappend fast_libs $PATH_LIB_PR/libs/C28SOI_SC_${LIB_TRACKS}_PR_${LIB_TYPE}_ff28_1.00V_0.00V_0.00V_0.00V_m40C.lib
+    create_library_set -name default_libset_max -timing $slow_libs
+    create_library_set -name default_libset_min -timing $fast_libs
+}
+
+create_rc_corner -name default_rc_corner_worst -qx_tech_file $PATH_LIB_BASE/CadenceTechnoKit_cmos028FDSOI_6U1x_2U2x_2T8x_LB_LowPower@1.0.1@20121114.0/QRC_TECHFILE/FuncRCmax.tech
+    #-qx_tech_file ${PATH_TECHNOKIT}/QRC_TECHFILE/SigRCmax/qrcTechFile
+
+create_rc_corner -name default_rc_corner_best -qx_tech_file $PATH_LIB_BASE/CadenceTechnoKit_cmos028FDSOI_6U1x_2U2x_2T8x_LB_LowPower@1.0.1@20121114.0/QRC_TECHFILE/FuncRCmin.tech
+    #-qx_tech_file ${PATH_TECHNOKIT}/QRC_TECHFILE/SigRCmin/qrcTechFile
+    
+
+
+create_delay_corner -name default_delay_corner_max \
+   -library_set default_libset_max \
+   -rc_corner default_rc_corner_worst
+create_delay_corner -name default_delay_corner_ocv \
+   -rc_corner default_rc_corner_worst \
+   -early_library_set default_libset_min \
+   -late_library_set default_libset_max
+create_delay_corner -name default_delay_corner_min \
+   -library_set default_libset_min \
+   -rc_corner default_rc_corner_best
+
+create_analysis_view -name default_analysis_view_setup -constraint_mode default_constraint_mode -delay_corner default_delay_corner_max
+create_analysis_view -name default_analysis_view_hold -constraint_mode default_constraint_mode -delay_corner default_delay_corner_min
+set_analysis_view -setup [list default_analysis_view_setup] -hold [list default_analysis_view_hold]
diff --git a/cadence/genus/tcl/pnr/place.tcl b/cadence/genus/tcl/pnr/place.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..bac1d1358ad1948a9d85fa288c81ab3ebc08b692
--- /dev/null
+++ b/cadence/genus/tcl/pnr/place.tcl
@@ -0,0 +1,7 @@
+# Place design
+place_opt_design
+place_opt_design -incremental
+
+# Change from floor plan to place view.
+setDrawView place
+redraw
diff --git a/cadence/genus/tcl/pnr/power.tcl b/cadence/genus/tcl/pnr/power.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..3bedae99a55c3d367fbda6cf736f064c268a66ee
--- /dev/null
+++ b/cadence/genus/tcl/pnr/power.tcl
@@ -0,0 +1,52 @@
+# Set power routing to io pads
+if {$FLOORPLAN_USE_PADS} {
+    globalNetConnect vdd -type pgpin -pin {vdd} -inst io_* 
+    globalNetConnect gnd -type pgpin -pin {gnd} -inst io_* 
+
+    globalNetConnect vdde -type pgpin -pin {vdde} -inst io_vdde_gnde
+    globalNetConnect gnde -type pgpin -pin {gnde} -inst io_vdde_gnde
+
+    globalNetConnect vdde -type tiehi -pin {ASRCN*} -inst io_asrc -override -verbose
+    globalNetConnect gnde -type tielo -pin {ASRCP*} -inst io_asrc -override -verbose
+
+    applyGlobalNets
+    
+    # This will make 5 evenly-spaced stripes 6.6um wide to each 40um pad
+    setSrouteMode -padPinSplit "6.6 1.75"
+    # Pad pin routing
+    sroute -nets { vdd gnd vdde gnde } \
+        -connect { padPin } \
+        -padPinPortConnect { allPort oneGeom } \
+        -layerChangeRange { M2 IB } \
+        -allowJogging 1 \
+        -checkAlignedSecondaryPin 1 \
+        -allowLayerChange 1 \
+        -crossoverViaBottomLayer M2 \
+        -crossoverViaTopLayer IB \
+        -targetViaBottomLayer M2 \
+        -targetViaTopLayer IB \
+        -splitLongVia { 2 0 -1 }
+
+}
+
+
+
+globalNetConnect vdd -type pgpin -pin {vdd} -inst * 
+globalNetConnect gnd -type pgpin -pin {gnd} -inst * 
+globalNetConnect vdd -type pgpin -pin {vdds} -inst * 
+globalNetConnect gnd -type pgpin -pin {gnds} -inst * 
+
+globalNetConnect vdd -type tiehi 
+globalNetConnect gnd -type tielo 
+
+# Core pin routing
+sroute -nets { vdd gnd } \
+    -connect { corePin } \
+    -layerChangeRange { M2 IB } \
+    -allowJogging 1 \
+    -allowLayerChange 1 \
+    -crossoverViaLayerRange {M2 IB} \
+    -targetViaLayerRange {M2 IB} \
+    -viaConnectToShape { ring stripe }
+
+redraw
diff --git a/cadence/genus/tcl/pnr/route.tcl b/cadence/genus/tcl/pnr/route.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..4a20a0fb511c3223cfdafe26321b40d2ba0d7f41
--- /dev/null
+++ b/cadence/genus/tcl/pnr/route.tcl
@@ -0,0 +1,45 @@
+# Clear errors and check that all cells are places
+clearDrc
+checkPlace
+verify_drc
+
+
+# Routing settings recommended by ST
+setNanoRouteMode -drouteUseMultiCutViaEffort high
+setNanoRouteMode -droutePostRouteSwapVia multicut
+setNanoRouteMode -routeInsertAntennaDiode true -drouteAntennaFactor 0.98
+setNanoRouteMode -routeAntennaCellName [get_db [get_db lib_cells *ANTPROT4*] .base_name -unique] 
+
+# High multi cut via effort
+setNanoRouteMode -quiet -drouteUseMultiCutViaEffort high
+
+# Other options
+setNanoRouteMode -quiet -drouteStartIteration default
+setNanoRouteMode -quiet -drouteEndIteration default
+setNanoRouteMode -quiet -routeBottomRoutingLayer default
+setNanoRouteMode -quiet -routeTopRoutingLayer 8
+setNanoRouteMode -quiet -routeWithTimingDriven true 
+setNanoRouteMode -quiet -routeWithSiDriven true 
+
+# Route reset nets first
+if {$ROUTE_RESET_NET_FIRST} {
+    setNanoRouteMode -routeSelectedNetOnly true
+    deselectAll
+    selectNet $ROUTE_RESET_NET_NAME
+    routeDesign -global
+    routeDesign -detail
+    deselectAll
+}
+
+# Route all nets
+setNanoRouteMode -routeSelectedNetOnly false
+routeDesign -global
+routeDesign -detail
+
+# PostRoute optimization
+setAnalysisMode -analysisType onChipVariation -cppr both
+optDesign -postRoute
+optDesign -postRoute -hold
+optDesign -postRoute -drv
+
+
diff --git a/cadence/genus/tcl/synth.tcl b/cadence/genus/tcl/synth.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..185639c23f6518d971d37700a28c9a64eefb50d9
--- /dev/null
+++ b/cadence/genus/tcl/synth.tcl
@@ -0,0 +1,230 @@
+# Load settings from file
+source $PATH_BASE/config_syn.tcl
+
+# Setup logging
+set_db -quiet / .information_level $GENERIC_INFORMATION_LEVEL
+set_db -quiet [get_db messages *] .max_print 10
+set_db -quiet / .verification_directory_naming_style fv/%s
+if {$SUPER_THREAD_DEBUG} {
+    set_db -quiet / .super_thread_debug_directory st_debug
+}
+
+# Set paths
+# We have libraries with "fdsoi_24", "fdsoi_27a", "lp_42"
+
+# LL
+# CMOS28_FDSOI-2.5.d
+set PATH_LIB_CORE "$PATH_LIB_BASE/C28SOI_SC_${LIB_TRACKS}_CORE_${LIB_TYPE}@2.2@20131004.0"
+set PATH_LIB_CLK  "$PATH_LIB_BASE/C28SOI_SC_${LIB_TRACKS}_CLK_${LIB_TYPE}@2.2@20131004.0"
+set PATH_LIB_PR   "$PATH_LIB_BASE/C28SOI_SC_${LIB_TRACKS}_PR_${LIB_TYPE}@2.1@20131028.0"
+# cmos28fdsoi_27a, CLK funkar inte
+#set PATH_LIB_CORE "$PATH_LIB_BASE/C28SOI_SC_12_CORE_LR/5.1-03"
+# LR
+#set PATH_LIB_CORE "$PATH_LIB_BASE/C28SOI_SC_${LIB_TRACKS}_CORE_${LIB_TYPE}@2.0@20130411.0"
+#set PATH_LIB_CLK  "$PATH_LIB_BASE/C28SOI_SC_${LIB_TRACKS}_CLK_${LIB_TYPE}@2.1@20130621.0"
+#set PATH_LIB_PR   "$PATH_LIB_BASE/C28SOI_SC_${LIB_TRACKS}_PR_${LIB_TYPE}@2.0@20130412.0"
+
+set PATH_TECHNOKIT "$PATH_LIB_BASE/CadenceTechnoKit_cmos028FDSOI_6U1x_2U2x_2T8x_LB_LowPower@1.0.1@20121114.0"
+# /${TECHNOKIT_VERSION}"
+if {[string match "/*" $PATH_SRC_BASE]} {
+    set PATH_SRC "$PATH_SRC_BASE"
+} else {
+    set PATH_SRC "$PATH_BASE/$PATH_SRC_BASE"
+}
+if {![string match "/*" $FILE_SOURCE_LIST]} {
+    set FILE_SOURCE_LIST "$PATH_BASE/$FILE_SOURCE_LIST"
+}
+
+# Setup super threading
+set_db / .auto_partition true
+set_db / .max_super_thread_cache_size $SUPER_THREAD_CACHE_SIZE
+set_db / .max_cpus_per_server $SUPER_THREAD_SERVERS
+
+# Create list of LIB files
+set LIB_FILES {}
+
+#C28SOI_SC_12_CORE_LL_ss28_0.90V_0.00V_0.00V_0.00V_125C
+# LL
+lappend LIB_FILES $PATH_LIB_CORE/libs/C28SOI_SC_12_CORE_LL_ss28_0.90V_0.00V_0.00V_0.00V_125C.lib
+lappend LIB_FILES $PATH_LIB_CLK/libs/C28SOI_SC_12_CLK_LL_ss28_0.90V_0.00V_0.00V_0.00V_125C.lib
+lappend LIB_FILES $PATH_LIB_PR/libs/C28SOI_SC_12_PR_LL_ss28_0.90V_0.00V_0.00V_0.00V_125C.lib
+# LR
+#lappend LIB_FILES $PATH_LIB_CORE/libs/C28SOI_SC_12_CORE_LR_ss28_0.90V_125C.lib
+#lappend LIB_FILES $PATH_LIB_CLK/libs/C28SOI_SC_12_CLK_LR_ss28_0.90V_125C.lib
+#lappend LIB_FILES $PATH_LIB_PR/libs/C28SOI_SC_12_PR_LR_ss28_0.90V_125C.lib
+
+
+#lappend LIB_FILES $PATH_LIB_CORE/libs/C32_SC_${LIB_TRACKS}_CORE_${LIB_TYPE}_${LIB_DETAILS}.lib
+#lappend LIB_FILES $PATH_LIB_CLK/libs/C32_SC_${LIB_TRACKS}_CLK_${LIB_TYPE}_${LIB_DETAILS}.lib
+#lappend LIB_FILES $PATH_LIB_PR/libs/C32_SC_${LIB_TRACKS}_PR_${LIB_DETAILS}.lib
+
+# Create list of LEF files
+set LEF_FILES {}
+lappend LEF_FILES $PATH_TECHNOKIT/LEF/technology.12T.lef
+lappend LEF_FILES $PATH_TECHNOKIT/LEF/viarule_generate.lef
+lappend LEF_FILES $PATH_LIB_BASE/SiteDefKit_cmos28@1.4@20120720.0/LEF/sites.lef
+lappend LEF_FILES $PATH_LIB_BASE/SiteDefKit_cmos28@1.4@20120720.0/LEF/lib_property.lef
+lappend LEF_FILES $PATH_LIB_CORE/CADENCE/LEF/C28SOI_SC_${LIB_TRACKS}_CORE_${LIB_TYPE}_soc.lef
+lappend LEF_FILES $PATH_LIB_CLK/CADENCE/LEF/C28SOI_SC_${LIB_TRACKS}_CLK_${LIB_TYPE}_soc.lef
+lappend LEF_FILES $PATH_LIB_PR/CADENCE/LEF/C28SOI_SC_${LIB_TRACKS}_PR_${LIB_TYPE}_soc.lef
+
+
+# Create list of QRC files
+set QRC_FILES {}
+#lappend QRC_FILES $PATH_TECHNOKIT/QRC_TECHFILE/FuncCmax.tech
+#lappend QRC_FILES $PATH_TECHNOKIT/QRC_TECHFILE/FuncCmin.tech
+lappend QRC_FILES $PATH_TECHNOKIT/QRC_TECHFILE/FuncRCmax.tech
+#lappend QRC_FILES $PATH_TECHNOKIT/QRC_TECHFILE/FuncRCmin.tech
+#lappend QRC_FILES $PATH_TECHNOKIT/QRC_TECHFILE/nominal.tech
+
+# Setup design libraries
+set_db / .library $LIB_FILES
+set_db / .lef_library $LEF_FILES
+set_db / .qrc_tech_file $QRC_FILES
+
+# Netlist naming settings
+set_db / .hdl_use_if_generate_prefix $NAMING_USE_IF_GENERATE_PREFIX
+set_db / .hdl_use_for_generate_prefix $NAMING_USE_FOR_GENERATE_PREFIX
+set_db / .hdl_array_naming_style %s_%d_
+set_db / .hdl_generate_separator "___"
+set_db / .hdl_generate_index_style %s_G_%d_
+set_db / .hdl_interface_separator "__"
+
+# Other elaboration settings
+set_db / .hdl_track_filename_row_col $GENERIC_TRACK_FILENAMES
+set_db / .hdl_max_loop_limit $GENERIC_HDL_LOOP_LIMIT
+
+# Clock gating
+if {$CLOCK_GATING_ENABLE} {
+    set_db / .lp_insert_clock_gating true
+}
+
+# Read source files
+set fh [open $FILE_SOURCE_LIST r]
+while {[gets ${fh} line]>=0} {
+    puts $line
+    if {[string match "#*" $line]} {
+        # Comment
+    } elseif {[string match "*.vhdl" $line] || [string match "*.vhd" $line]} {
+        read_hdl -vhdl $PATH_SRC/$line
+    } elseif {[string match "*.v" $line]} {
+        read_hdl $PATH_SRC/$line
+    } else {
+        puts "\nSCRIPT  : Invalid file type: $line.\n"
+    }
+}
+close ${fh}
+
+
+# Elaborate
+puts "\nSCRIPT  : Starting elaboration at: [clock format [clock seconds] -format {%x %X}].\n"
+elaborate
+puts "\nSCRIPT  : Elaboration finished at: [clock format [clock seconds] -format {%x %X}]."
+puts "SCRIPT  :   Runtime:      [get_db / .real_runtime] s"
+puts "SCRIPT  :   Memory usage: [get_db / .memory_usage] MB\n"
+
+# Synthesis settings
+set_db / .auto_ungroup $SYNTH_AUTO_UNGROUP
+
+# Clock gating settings
+if {$CLOCK_GATING_ENABLE} {
+    set_db [get_lib_cells *CNHLS*_P0] .dont_use false
+    set_db / .lp_clock_gating_prefix "CLKGATE"
+}
+
+# TODO
+#set_top_module ve_wctrl
+
+# Setup timing
+create_clock -name $TIMING_CLOCK_PORT -period $TIMING_CLOCK_PERIOD [get_ports $TIMING_CLOCK_PORT]
+#set_input_delay -clock [get_clocks $TIMING_CLOCK_PORT] -name InputDelay $TIMING_INPUT_DELAY [get_ports -filter "direction==in && name != clk"]
+#set_output_delay -clock [get_clocks $TIMING_CLOCK_PORT] -name OutputDelay $TIMING_OUTPUT_DELAY [get_ports -filter "direction==out"]
+
+# Retiming
+if {$RETIMING_ENABLE} {
+    set_db [get_design design:*] .retime true
+    foreach e $RETIMING_DONT_RETIME {
+        set_db [get_db insts $e*] .dont_retime true
+    }
+}
+
+# Set multi sycle paths
+foreach l $MULTI_CYCLE_PATHS {
+    # Setup time
+    set_multicycle_path -setup -from [get_db insts *[lindex $l 0]*] -to [get_db insts *[lindex $l 1]*] [lindex $l 2]
+    # Hold time
+    set_multicycle_path -hold - from [get_db insts *[lindex $l 0]*] -to [get_db insts *[lindex $l 1]*] [expr [lindex $l 2] - 1]
+}
+
+# Set cells to avoid
+foreach l $CELLS_AVOID {
+    #set_db [get_lib_cells $l] .avoid true
+}
+
+# Syntesis settings
+set_db / .syn_generic_effort $SYNTH_GENERIC_EFFORT
+set_db / .syn_map_effort $SYNTH_OPT_EFFORT
+set_db / .syn_opt_effort $SYNTH_MAP_EFFORT
+if {$PHYSICAL_ENABLE} {
+    set_db / .phys_checkout_innovus_license true
+    set_db / .phys_flow_effort $PHYSICAL_EFFORT
+    set_db [get_db designs] .utilization_threshold $PHYSICAL_UTILIZATION
+    read_def -keep_all_instances $PATH_BASE/out/$DESIGN_NAME/fp/${DESIGN_NAME}_fp.def
+}
+
+# Synthesis
+puts "\nSCRIPT  : Starting generic synthesis at: [clock format [clock seconds] -format {%x %X}].\n"
+if {$PHYSICAL_ENABLE} {
+    syn_generic -physical
+} else {
+    syn_generic
+}
+puts "\nSCRIPT  : Generic synthesis finished at: [clock format [clock seconds] -format {%x %X}]."
+puts "SCRIPT  :   Runtime:      [get_db / .real_runtime] s"
+puts "SCRIPT  :   Memory usage: [get_db / .memory_usage] MB\n"
+
+puts "\nSCRIPT  : Starting synthesis top mapped at: [clock format [clock seconds] -format {%x %X}].\n"
+if {$PHYSICAL_ENABLE} {
+    syn_map -physical
+} else {
+    syn_map
+}
+puts "\nSCRIPT  : Synthesis to mapped finished at: [clock format [clock seconds] -format {%x %X}]."
+puts "SCRIPT  :   Runtime:      [get_db / .real_runtime] s"
+puts "SCRIPT  :   Memory usage: [get_db / .memory_usage] MB\n"
+
+puts "\nSCRIPT  : Starting gate level optimization at: [clock format [clock seconds] -format {%x %X}].\n"
+if {$PHYSICAL_ENABLE} {
+    syn_opt -physical
+    syn_opt -physical -incremental
+} else {
+    syn_opt
+    syn_opt -incremental
+}
+puts "\nSCRIPT  : Gate level optimization finished at: [clock format [clock seconds] -format {%x %X}]."
+puts "SCRIPT  :   Runtime:      [get_db / .real_runtime] s"
+puts "SCRIPT  :   Memory usage: [get_db / .memory_usage] MB\n"
+
+puts "\nSCRIPT  : Starting generation of design files and reports at: [clock format [clock seconds] -format {%x %X}].\n"
+write_hdl > $DESIGN_NAME.v
+#write_sdf -delimiter / -edges check_edge -no_escape -setuphold split -recrem split > $DESIGN_NAME.sdf.gz
+write_sdf -delimiter / -no_escape -interconn interconnect -setuphold split -recrem split > $DESIGN_NAME.sdf.gz
+write_spef -power > $DESIGN_NAME.spef
+write_sdc > $DESIGN_NAME.sdc.gz
+write_design -innovus -base_name session/$DESIGN_NAME
+
+#report_timing > reports/timing.txt
+report_timing -max_paths 2 > reports/timing.txt
+report_gates > reports/gates.txt
+report_area > reports/area.txt
+report_dp > reports/datapath.txt
+report_power > reports/power.txt
+report_sequential > reports/sequential.txt
+if {$CLOCK_GATING_ENABLE} {
+    report_clock_gating > reports/clock_gating.txt
+}
+puts "\nSCRIPT  : Output generation finished at: [clock format [clock seconds] -format {%x %X}]."
+puts "SCRIPT  :   Runtime:      [get_db / .real_runtime] s"
+puts "SCRIPT  :   Memory usage: [get_db / .memory_usage] MB\n"
+
+exit
diff --git a/synopsys/.synopsys_dc.setup b/synopsys/.synopsys_dc.setup
new file mode 100644
index 0000000000000000000000000000000000000000..cb73419a67f7a8815df868ad022a18e12f78f1e4
--- /dev/null
+++ b/synopsys/.synopsys_dc.setup
@@ -0,0 +1,5 @@
+set search_path [list "./" "/sw/cadence/libraries/CMOS28_FDSOI-2.5.d/C28SOI_SC_12_CORE_LR@2.0@20130411.0/libs/" "/sw/synopsys/DC-P-2019.03-SP5/libraries/syn/"]
+set target_library [list C28SOI_SC_12_CORE_LR_ss28_1.00V_125C.db]
+set synthetic_library [list dw_foundation.sldb standard.sldb]
+set link_library [concat  $target_library $synthetic_library]
+define_design_lib work -path ./design_lib