diff --git a/UsbReceive/.vs/UsbReceive/v14/.atsuo b/UsbReceive/.vs/UsbReceive/v14/.atsuo
new file mode 100644
index 0000000000000000000000000000000000000000..907637630aa6f019c475cb7a9c66ba41ab36cc70
Binary files /dev/null and b/UsbReceive/.vs/UsbReceive/v14/.atsuo differ
diff --git a/UsbReceive/UsbReceive.atsln b/UsbReceive/UsbReceive.atsln
new file mode 100644
index 0000000000000000000000000000000000000000..37476428a69c88b18cafa1b84c8b15294ac69534
--- /dev/null
+++ b/UsbReceive/UsbReceive.atsln
@@ -0,0 +1,28 @@
+
+Microsoft Visual Studio Solution File, Format Version 12.00
+# Atmel Studio Solution File, Format Version 11.00
+VisualStudioVersion = 14.0.23107.0
+MinimumVisualStudioVersion = 10.0.40219.1
+Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "UsbReceive", "UsbReceive\UsbReceive\UsbReceive.cppproj", "{DCE6C7E3-EE26-4D79-826B-08594B9AD897}"
+EndProject
+Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "ArduinoCore", "UsbReceive\ArduinoCore\ArduinoCore.cppproj", "{3CF7A0AB-B365-4936-958E-A8B73130CCDE}"
+EndProject
+Global
+ GlobalSection(SolutionConfigurationPlatforms) = preSolution
+ Debug|ARM = Debug|ARM
+ Release|ARM = Release|ARM
+ EndGlobalSection
+ GlobalSection(ProjectConfigurationPlatforms) = postSolution
+ {DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Debug|ARM.ActiveCfg = Debug|ARM
+ {DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Debug|ARM.Build.0 = Debug|ARM
+ {DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Release|ARM.ActiveCfg = Release|ARM
+ {DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Release|ARM.Build.0 = Release|ARM
+ {3CF7A0AB-B365-4936-958E-A8B73130CCDE}.Debug|ARM.ActiveCfg = Debug|ARM
+ {3CF7A0AB-B365-4936-958E-A8B73130CCDE}.Debug|ARM.Build.0 = Debug|ARM
+ {3CF7A0AB-B365-4936-958E-A8B73130CCDE}.Release|ARM.ActiveCfg = Release|ARM
+ {3CF7A0AB-B365-4936-958E-A8B73130CCDE}.Release|ARM.Build.0 = Release|ARM
+ EndGlobalSection
+ GlobalSection(SolutionProperties) = preSolution
+ HideSolutionNode = FALSE
+ EndGlobalSection
+EndGlobal
diff --git a/UsbReceive/UsbReceive.ino b/UsbReceive/UsbReceive.ino
new file mode 100644
index 0000000000000000000000000000000000000000..94da7ff94e59e553bf5d284aa76b8d0ce602031f
--- /dev/null
+++ b/UsbReceive/UsbReceive.ino
@@ -0,0 +1,59 @@
+/*************************************************************************
+* Code that reads values sent from python through serial
+ ************************************************************************/
+
+#include <Wire.h> // For I2C communication with sensor
+#include <Wireling.h> // For interfacing with Wirelings
+
+// Make Serial Monitor compatible for all TinyCircuits processors
+#if defined(ARDUINO_ARCH_AVR)
+ #define SerialMonitorInterface Serial
+#elif defined(ARDUINO_ARCH_SAMD)
+ #define SerialMonitorInterface SerialUSB
+#endif
+
+
+void setup() {
+
+ SerialMonitorInterface.begin(115200);
+ Wire.begin();
+
+ // Initialize Wireling
+ Wireling.begin();
+ Wireling.selectPort(0);
+
+ analogWriteResolution(10); //Change the DAC resolution to 10-bits
+ analogWrite(A0, 0); // Initialize Dac to Zero
+
+}
+
+void loop() {
+ int output;
+ //static float x = 270; // Current degrees for sine wave (initially 270 so that
+ // the sine wave is initially zero).
+
+ // output = (int) (512.0 * sin(0.017453 * x) + 512); // Sine Wave
+ if (SerialMonitorInterface.available()> -1) {
+ output = SerialMonitorInterface.parseInt();
+
+ analogWrite(A0, output);
+
+ }// end if serial available
+ //analogWrite(A0, output); // Write the analog output to A0
+ //SerialMonitorInterface.print(output);
+ //SerialMonitorInterface.println();
+
+ /*
+ * Increment Degrees for the Next Wave Point
+ *
+ * To utilize the entire resolution of the 10-bit DAC, at least 1024
+ * values must be used between 0 and 360 degrees. Therefore, a step
+ * value greater than 360/1024 will not utilize the entier resolution
+ * of the DAC.
+ */
+ //x += 0.35;
+ //if(x>=360.0) x -= 360.0;
+
+
+ //delay(1);
+}
diff --git a/UsbReceive/UsbReceive/ArduinoCore/ArduinoCore.componentinfo.xml b/UsbReceive/UsbReceive/ArduinoCore/ArduinoCore.componentinfo.xml
new file mode 100644
index 0000000000000000000000000000000000000000..38e8cde7d0d74696e2ffc30488c41f1072b79add
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/ArduinoCore.componentinfo.xml
@@ -0,0 +1,125 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Store xmlns:i="http://www.w3.org/2001/XMLSchema-instance" xmlns="AtmelPackComponentManagement">
+ <ProjectComponents>
+ <ProjectComponent z:Id="i1" xmlns:z="http://schemas.microsoft.com/2003/10/Serialization/">
+ <CApiVersion></CApiVersion>
+ <CBundle></CBundle>
+ <CClass>CMSIS</CClass>
+ <CGroup>CORE</CGroup>
+ <CSub></CSub>
+ <CVariant></CVariant>
+ <CVendor>ARM</CVendor>
+ <CVersion>5.1.2</CVersion>
+ <DefaultRepoPath>C:/Program Files (x86)\Atmel\Studio\7.0\Packs</DefaultRepoPath>
+ <DependentComponents xmlns:d4p1="http://schemas.microsoft.com/2003/10/Serialization/Arrays" />
+ <Description></Description>
+ <Files xmlns:d4p1="http://schemas.microsoft.com/2003/10/Serialization/Arrays">
+ <d4p1:anyType i:type="FileInfo">
+ <AbsolutePath>C:/Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Documentation\Core\html\index.html</AbsolutePath>
+ <Attribute></Attribute>
+ <Category>doc</Category>
+ <Condition></Condition>
+ <FileContentHash i:nil="true" />
+ <FileVersion></FileVersion>
+ <Name>CMSIS/Documentation/Core/html/index.html</Name>
+ <SelectString></SelectString>
+ <SourcePath></SourcePath>
+ </d4p1:anyType>
+ <d4p1:anyType i:type="FileInfo">
+ <AbsolutePath>C:/Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include\</AbsolutePath>
+ <Attribute></Attribute>
+ <Category>include</Category>
+ <Condition></Condition>
+ <FileContentHash i:nil="true" />
+ <FileVersion></FileVersion>
+ <Name>CMSIS/Core/Include/</Name>
+ <SelectString></SelectString>
+ <SourcePath></SourcePath>
+ </d4p1:anyType>
+ </Files>
+ <PackName>CMSIS</PackName>
+ <PackPath>C:/Program Files (x86)/Atmel/Studio/7.0/Packs/arm/CMSIS/5.4.0/ARM.CMSIS.pdsc</PackPath>
+ <PackVersion>5.4.0</PackVersion>
+ <PresentInProject>true</PresentInProject>
+ <ReferenceConditionId>ARMv6_7_8-M Device</ReferenceConditionId>
+ <RteComponents xmlns:d4p1="http://schemas.microsoft.com/2003/10/Serialization/Arrays">
+ <d4p1:string></d4p1:string>
+ </RteComponents>
+ <Status>Resolved</Status>
+ <VersionMode>Fixed</VersionMode>
+ <IsComponentInAtProject>true</IsComponentInAtProject>
+ </ProjectComponent>
+ <ProjectComponent z:Id="i2" xmlns:z="http://schemas.microsoft.com/2003/10/Serialization/">
+ <CApiVersion></CApiVersion>
+ <CBundle></CBundle>
+ <CClass>Device</CClass>
+ <CGroup>Startup</CGroup>
+ <CSub></CSub>
+ <CVariant></CVariant>
+ <CVendor>Atmel</CVendor>
+ <CVersion>1.3.0</CVersion>
+ <DefaultRepoPath>C:/Program Files (x86)\Atmel\Studio\7.0\Packs</DefaultRepoPath>
+ <DependentComponents xmlns:d4p1="http://schemas.microsoft.com/2003/10/Serialization/Arrays">
+ <d4p1:anyType z:Ref="i1" />
+ </DependentComponents>
+ <Description></Description>
+ <Files xmlns:d4p1="http://schemas.microsoft.com/2003/10/Serialization/Arrays">
+ <d4p1:anyType i:type="FileInfo">
+ <AbsolutePath>C:/Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAMD21_DFP\1.3.395\samd21a\include</AbsolutePath>
+ <Attribute></Attribute>
+ <Category>include</Category>
+ <Condition>C</Condition>
+ <FileContentHash i:nil="true" />
+ <FileVersion></FileVersion>
+ <Name>samd21a/include</Name>
+ <SelectString></SelectString>
+ <SourcePath></SourcePath>
+ </d4p1:anyType>
+ <d4p1:anyType i:type="FileInfo">
+ <AbsolutePath>C:/Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAMD21_DFP\1.3.395\samd21a\include\sam.h</AbsolutePath>
+ <Attribute></Attribute>
+ <Category>header</Category>
+ <Condition>C</Condition>
+ <FileContentHash>V54vVU6riwaXcelmdQefHA==</FileContentHash>
+ <FileVersion></FileVersion>
+ <Name>samd21a/include/sam.h</Name>
+ <SelectString></SelectString>
+ <SourcePath></SourcePath>
+ </d4p1:anyType>
+ <d4p1:anyType i:type="FileInfo">
+ <AbsolutePath>C:/Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAMD21_DFP\1.3.395\samd21a\templates\library.c</AbsolutePath>
+ <Attribute>template</Attribute>
+ <Category>source</Category>
+ <Condition>C Lib</Condition>
+ <FileContentHash>Uuf63uKt4ieOmYoYXl4EtA==</FileContentHash>
+ <FileVersion></FileVersion>
+ <Name>samd21a/templates/library.c</Name>
+ <SelectString>Main file (.c)</SelectString>
+ <SourcePath></SourcePath>
+ </d4p1:anyType>
+ <d4p1:anyType i:type="FileInfo">
+ <AbsolutePath>C:/Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAMD21_DFP\1.3.395\samd21a\templates\library.cpp</AbsolutePath>
+ <Attribute>template</Attribute>
+ <Category>source</Category>
+ <Condition>C Lib</Condition>
+ <FileContentHash>dpWyIjCXKdZ0h+C1ySnhAA==</FileContentHash>
+ <FileVersion></FileVersion>
+ <Name>samd21a/templates/library.cpp</Name>
+ <SelectString>Main file (.cpp)</SelectString>
+ <SourcePath></SourcePath>
+ </d4p1:anyType>
+ </Files>
+ <PackName>SAMD21_DFP</PackName>
+ <PackPath>C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/SAMD21_DFP/1.3.395/Atmel.SAMD21_DFP.pdsc</PackPath>
+ <PackVersion>1.3.395</PackVersion>
+ <PresentInProject>true</PresentInProject>
+ <ReferenceConditionId>ATSAMD21G18A</ReferenceConditionId>
+ <RteComponents xmlns:d4p1="http://schemas.microsoft.com/2003/10/Serialization/Arrays">
+ <d4p1:string></d4p1:string>
+ </RteComponents>
+ <Status>Resolved</Status>
+ <VersionMode>Fixed</VersionMode>
+ <IsComponentInAtProject>true</IsComponentInAtProject>
+ </ProjectComponent>
+ </ProjectComponents>
+</Store>
\ No newline at end of file
diff --git a/UsbReceive/UsbReceive/ArduinoCore/ArduinoCore.cppproj b/UsbReceive/UsbReceive/ArduinoCore/ArduinoCore.cppproj
new file mode 100644
index 0000000000000000000000000000000000000000..b9d4d678a8a6f44595c6a5366600aac9e7b39bad
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/ArduinoCore.cppproj
@@ -0,0 +1,502 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Project DefaultTargets="Build" xmlns="http://schemas.microsoft.com/developer/msbuild/2003" ToolsVersion="14.0">
+ <PropertyGroup>
+ <SchemaVersion>2.0</SchemaVersion>
+ <ProjectVersion>7.0</ProjectVersion>
+ <ToolchainName>com.Atmel.ARMGCC.CPP</ToolchainName>
+ <ProjectGuid>3cf7a0ab-b365-4936-958e-a8b73130ccde</ProjectGuid>
+ <avrdevice>ATSAMD21G18A</avrdevice>
+ <avrdeviceseries>none</avrdeviceseries>
+ <OutputType>StaticLibrary</OutputType>
+ <Language>CPP</Language>
+ <OutputFileName>lib$(MSBuildProjectName)</OutputFileName>
+ <OutputFileExtension>.a</OutputFileExtension>
+ <OutputDirectory>$(MSBuildProjectDirectory)\$(Configuration)</OutputDirectory>
+ <Name>ArduinoCore</Name>
+ <ArduinoIdeDir>C:\Program Files (x86)\Arduino</ArduinoIdeDir>
+ <ArduinoProjectType>Core</ArduinoProjectType>
+ <ToolchainFlavour>Native</ToolchainFlavour>
+ <AssemblyName>ArduinoCore</AssemblyName>
+ <RootNamespace>ArduinoCore</RootNamespace>
+ <KeepTimersRunning>true</KeepTimersRunning>
+ <OverrideVtor>false</OverrideVtor>
+ <CacheFlash>true</CacheFlash>
+ <ProgFlashFromRam>true</ProgFlashFromRam>
+ <RamSnippetAddress />
+ <UncachedRange />
+ <preserveEEPROM>true</preserveEEPROM>
+ <OverrideVtorValue />
+ <BootSegment>2</BootSegment>
+ <ResetRule>0</ResetRule>
+ <eraseonlaunchrule>0</eraseonlaunchrule>
+ <EraseKey />
+ <AsfFrameworkConfig>
+ <framework-data xmlns="">
+ <options />
+ <configurations />
+ <files />
+ <documentation help="" />
+ <offline-documentation help="" />
+ <dependencies>
+ <content-extension eid="atmel.asf" uuidref="Atmel.ASF" version="3.49.1" />
+ </dependencies>
+</framework-data>
+ </AsfFrameworkConfig>
+ </PropertyGroup>
+ <PropertyGroup Condition=" '$(Configuration)' == 'Release' ">
+ <ToolchainSettings>
+ <ArmGccCpp>
+ <armgcc.common.outputfiles.hex>True</armgcc.common.outputfiles.hex>
+ <armgcc.common.outputfiles.lss>True</armgcc.common.outputfiles.lss>
+ <armgcc.common.outputfiles.eep>True</armgcc.common.outputfiles.eep>
+ <armgcc.common.outputfiles.bin>True</armgcc.common.outputfiles.bin>
+ <armgcc.common.outputfiles.srec>True</armgcc.common.outputfiles.srec>
+ <armgcc.compiler.symbols.DefSymbols>
+ <ListValues>
+ <Value>NDEBUG</Value>
+ <Value>F_CPU=48000000L</Value>
+ <Value>ARDUINO=108019</Value>
+ <Value>ARDUINO_SAMD_ZERO</Value>
+ <Value>ARDUINO_ARCH_SAMD</Value>
+ <Value>USB_VID=0x03EB</Value>
+ <Value>USB_PID=0x8009</Value>
+ <Value>USB_PRODUCT="\"TinyZero\""</Value>
+ <Value>USB_MANUFACTURER="\"TinyCircuits\""</Value>
+ <Value>USBCON</Value>
+ <Value>SAMD_SERIES</Value>
+ </ListValues>
+ </armgcc.compiler.symbols.DefSymbols>
+ <armgcc.compiler.directories.IncludePaths>
+ <ListValues>
+ <Value>%24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\</Value>
+ <Value>..\include\libraries\wire</Value>
+ <Value>..\include\core</Value>
+ <Value>..\include\core\avr</Value>
+ <Value>..\include\core\USB</Value>
+ <Value>..\include\variants</Value>
+ </ListValues>
+ </armgcc.compiler.directories.IncludePaths>
+ <armgcc.compiler.optimization.level>Optimize for size (-Os)</armgcc.compiler.optimization.level>
+ <armgcc.compiler.optimization.OtherFlags>-fno-threadsafe-statics -fno-exceptions</armgcc.compiler.optimization.OtherFlags>
+ <armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>
+ <armgcc.compiler.optimization.PrepareDataForGarbageCollection>True</armgcc.compiler.optimization.PrepareDataForGarbageCollection>
+ <armgcc.compiler.optimization.EnableLongCalls>False</armgcc.compiler.optimization.EnableLongCalls>
+ <armgcc.compiler.optimization.DebugLevel>Maximum (-g3)</armgcc.compiler.optimization.DebugLevel>
+ <armgcc.compiler.warnings.InhibitAllWarnings>True</armgcc.compiler.warnings.InhibitAllWarnings>
+ <armgcc.compiler.miscellaneous.OtherFlags>-std=gnu11 --param max-inline-insns-single=500 -nostdlib</armgcc.compiler.miscellaneous.OtherFlags>
+ <armgcccpp.compiler.symbols.DefSymbols>
+ <ListValues>
+ <Value>NDEBUG</Value>
+ <Value>F_CPU=48000000L</Value>
+ <Value>ARDUINO=108019</Value>
+ <Value>ARDUINO_SAMD_ZERO</Value>
+ <Value>ARDUINO_ARCH_SAMD</Value>
+ <Value>USB_VID=0x03EB</Value>
+ <Value>USB_PID=0x8009</Value>
+ <Value>USB_PRODUCT="\"TinyZero\""</Value>
+ <Value>USB_MANUFACTURER="\"TinyCircuits\""</Value>
+ <Value>USBCON</Value>
+ <Value>SAMD_SERIES</Value>
+ </ListValues>
+ </armgcccpp.compiler.symbols.DefSymbols>
+ <armgcccpp.compiler.directories.IncludePaths>
+ <ListValues>
+ <Value>%24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\</Value>
+ <Value>..\include\libraries\wire</Value>
+ <Value>..\include\core</Value>
+ <Value>..\include\core\avr</Value>
+ <Value>..\include\core\USB</Value>
+ <Value>..\include\variants</Value>
+ </ListValues>
+ </armgcccpp.compiler.directories.IncludePaths>
+ <armgcccpp.compiler.optimization.level>Optimize for size (-Os)</armgcccpp.compiler.optimization.level>
+ <armgcccpp.compiler.optimization.OtherFlags>-fno-threadsafe-statics -fno-exceptions</armgcccpp.compiler.optimization.OtherFlags>
+ <armgcccpp.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcccpp.compiler.optimization.PrepareFunctionsForGarbageCollection>
+ <armgcccpp.compiler.optimization.PrepareDataForGarbageCollection>True</armgcccpp.compiler.optimization.PrepareDataForGarbageCollection>
+ <armgcccpp.compiler.optimization.EnableLongCalls>False</armgcccpp.compiler.optimization.EnableLongCalls>
+ <armgcccpp.compiler.optimization.DebugLevel>Maximum (-g3)</armgcccpp.compiler.optimization.DebugLevel>
+ <armgcccpp.compiler.warnings.InhibitAllWarnings>True</armgcccpp.compiler.warnings.InhibitAllWarnings>
+ <armgcccpp.compiler.miscellaneous.OtherFlags>-std=gnu++11 --param max-inline-insns-single=500 -nostdlib</armgcccpp.compiler.miscellaneous.OtherFlags>
+ <armgcccpp.linker.general.UseNewlibNano>True</armgcccpp.linker.general.UseNewlibNano>
+ <armgcccpp.linker.general.AdditionalSpecs>Use syscall stubs (--specs=nosys.specs)</armgcccpp.linker.general.AdditionalSpecs>
+ <armgcccpp.linker.libraries.Libraries>
+ <ListValues>
+ <Value>libm</Value>
+ </ListValues>
+ </armgcccpp.linker.libraries.Libraries>
+ <armgcccpp.linker.optimization.GarbageCollectUnusedSections>True</armgcccpp.linker.optimization.GarbageCollectUnusedSections>
+ <armgcccpp.linker.miscellaneous.LinkerFlags>-Wl,--cref -Os -Wl,--check-sections -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align</armgcccpp.linker.miscellaneous.LinkerFlags>
+ <armgcccpp.assembler.general.IncludePaths>
+ <ListValues>
+ <Value>%24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\</Value>
+ <Value>%24(PackRepoDir)\atmel\SAMD21_DFP\1.3.395\samd21a\include</Value>
+ </ListValues>
+ </armgcccpp.assembler.general.IncludePaths>
+ <armgcccpp.assembler.debugging.DebugLevel>Default (-Wa,-g)</armgcccpp.assembler.debugging.DebugLevel>
+ <armgcccpp.preprocessingassembler.general.IncludePaths>
+ <ListValues>
+ <Value>%24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\</Value>
+ <Value>%24(PackRepoDir)\atmel\SAMD21_DFP\1.3.395\samd21a\include</Value>
+ </ListValues>
+ </armgcccpp.preprocessingassembler.general.IncludePaths>
+ </ArmGccCpp>
+ </ToolchainSettings>
+ </PropertyGroup>
+ <PropertyGroup Condition=" '$(Configuration)' == 'Debug' ">
+ <ToolchainSettings>
+ <ArmGccCpp>
+ <armgcc.common.outputfiles.hex>True</armgcc.common.outputfiles.hex>
+ <armgcc.common.outputfiles.lss>True</armgcc.common.outputfiles.lss>
+ <armgcc.common.outputfiles.eep>True</armgcc.common.outputfiles.eep>
+ <armgcc.common.outputfiles.bin>True</armgcc.common.outputfiles.bin>
+ <armgcc.common.outputfiles.srec>True</armgcc.common.outputfiles.srec>
+ <armgcc.compiler.symbols.DefSymbols>
+ <ListValues>
+ <Value>DEBUG</Value>
+ <Value>F_CPU=48000000L</Value>
+ <Value>ARDUINO=108019</Value>
+ <Value>ARDUINO_SAMD_ZERO</Value>
+ <Value>ARDUINO_ARCH_SAMD</Value>
+ <Value>USB_VID=0x03EB</Value>
+ <Value>USB_PID=0x8009</Value>
+ <Value>USB_PRODUCT="\"TinyZero\""</Value>
+ <Value>USB_MANUFACTURER="\"TinyCircuits\""</Value>
+ <Value>USBCON</Value>
+ <Value>SAMD_SERIES</Value>
+ </ListValues>
+ </armgcc.compiler.symbols.DefSymbols>
+ <armgcc.compiler.directories.IncludePaths>
+ <ListValues>
+ <Value>%24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\</Value>
+ <Value>..\include\libraries\wire</Value>
+ <Value>..\include\core</Value>
+ <Value>..\include\core\avr</Value>
+ <Value>..\include\core\USB</Value>
+ <Value>..\include\variants</Value>
+ </ListValues>
+ </armgcc.compiler.directories.IncludePaths>
+ <armgcc.compiler.optimization.level>Optimize for size (-Os)</armgcc.compiler.optimization.level>
+ <armgcc.compiler.optimization.OtherFlags>-fno-threadsafe-statics -fno-exceptions</armgcc.compiler.optimization.OtherFlags>
+ <armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>
+ <armgcc.compiler.optimization.PrepareDataForGarbageCollection>True</armgcc.compiler.optimization.PrepareDataForGarbageCollection>
+ <armgcc.compiler.optimization.EnableLongCalls>False</armgcc.compiler.optimization.EnableLongCalls>
+ <armgcc.compiler.optimization.DebugLevel>Maximum (-g3)</armgcc.compiler.optimization.DebugLevel>
+ <armgcc.compiler.warnings.InhibitAllWarnings>True</armgcc.compiler.warnings.InhibitAllWarnings>
+ <armgcc.compiler.miscellaneous.OtherFlags>-std=gnu11 --param max-inline-insns-single=500 -nostdlib</armgcc.compiler.miscellaneous.OtherFlags>
+ <armgcccpp.compiler.symbols.DefSymbols>
+ <ListValues>
+ <Value>DEBUG</Value>
+ <Value>F_CPU=48000000L</Value>
+ <Value>ARDUINO=108019</Value>
+ <Value>ARDUINO_SAMD_ZERO</Value>
+ <Value>ARDUINO_ARCH_SAMD</Value>
+ <Value>USB_VID=0x03EB</Value>
+ <Value>USB_PID=0x8009</Value>
+ <Value>USB_PRODUCT="\"TinyZero\""</Value>
+ <Value>USB_MANUFACTURER="\"TinyCircuits\""</Value>
+ <Value>USBCON</Value>
+ <Value>SAMD_SERIES</Value>
+ </ListValues>
+ </armgcccpp.compiler.symbols.DefSymbols>
+ <armgcccpp.compiler.directories.IncludePaths>
+ <ListValues>
+ <Value>%24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\</Value>
+ <Value>..\include\libraries\wire</Value>
+ <Value>..\include\core</Value>
+ <Value>..\include\core\avr</Value>
+ <Value>..\include\core\USB</Value>
+ <Value>..\include\variants</Value>
+ </ListValues>
+ </armgcccpp.compiler.directories.IncludePaths>
+ <armgcccpp.compiler.optimization.level>Optimize for size (-Os)</armgcccpp.compiler.optimization.level>
+ <armgcccpp.compiler.optimization.OtherFlags>-fno-threadsafe-statics -fno-exceptions</armgcccpp.compiler.optimization.OtherFlags>
+ <armgcccpp.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcccpp.compiler.optimization.PrepareFunctionsForGarbageCollection>
+ <armgcccpp.compiler.optimization.PrepareDataForGarbageCollection>True</armgcccpp.compiler.optimization.PrepareDataForGarbageCollection>
+ <armgcccpp.compiler.optimization.EnableLongCalls>False</armgcccpp.compiler.optimization.EnableLongCalls>
+ <armgcccpp.compiler.optimization.DebugLevel>Maximum (-g3)</armgcccpp.compiler.optimization.DebugLevel>
+ <armgcccpp.compiler.warnings.InhibitAllWarnings>True</armgcccpp.compiler.warnings.InhibitAllWarnings>
+ <armgcccpp.compiler.miscellaneous.OtherFlags>-std=gnu++11 --param max-inline-insns-single=500 -nostdlib</armgcccpp.compiler.miscellaneous.OtherFlags>
+ <armgcccpp.linker.general.UseNewlibNano>True</armgcccpp.linker.general.UseNewlibNano>
+ <armgcccpp.linker.general.AdditionalSpecs>Use syscall stubs (--specs=nosys.specs)</armgcccpp.linker.general.AdditionalSpecs>
+ <armgcccpp.linker.libraries.Libraries>
+ <ListValues>
+ <Value>libm</Value>
+ </ListValues>
+ </armgcccpp.linker.libraries.Libraries>
+ <armgcccpp.linker.optimization.GarbageCollectUnusedSections>True</armgcccpp.linker.optimization.GarbageCollectUnusedSections>
+ <armgcccpp.linker.miscellaneous.LinkerFlags>-Wl,--cref -Os -Wl,--check-sections -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align</armgcccpp.linker.miscellaneous.LinkerFlags>
+ <armgcccpp.assembler.general.IncludePaths>
+ <ListValues>
+ <Value>%24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\</Value>
+ <Value>%24(PackRepoDir)\atmel\SAMD21_DFP\1.3.395\samd21a\include</Value>
+ </ListValues>
+ </armgcccpp.assembler.general.IncludePaths>
+ <armgcccpp.assembler.debugging.DebugLevel>Default (-Wa,-g)</armgcccpp.assembler.debugging.DebugLevel>
+ <armgcccpp.preprocessingassembler.general.IncludePaths>
+ <ListValues>
+ <Value>%24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\</Value>
+ <Value>%24(PackRepoDir)\atmel\SAMD21_DFP\1.3.395\samd21a\include</Value>
+ </ListValues>
+ </armgcccpp.preprocessingassembler.general.IncludePaths>
+ <armgcccpp.preprocessingassembler.debugging.DebugLevel>Default (-Wa,-g)</armgcccpp.preprocessingassembler.debugging.DebugLevel>
+ </ArmGccCpp>
+ </ToolchainSettings>
+ </PropertyGroup>
+ <ItemGroup>
+ <Compile Include="include\core\Arduino.h">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="include\core\avr\dtostrf.h">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="include\core\avr\interrupt.h">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="include\core\avr\io.h">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="include\core\avr\pgmspace.h">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="include\core\binary.h">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="include\core\Client.h">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="include\core\delay.h">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="include\core\HardwareSerial.h">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="include\core\IPAddress.h">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="include\core\itoa.h">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="include\core\Print.h">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="include\core\Printable.h">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="include\core\pulse.h">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="include\core\Reset.h">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="include\core\RingBuffer.h">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="include\core\SERCOM.h">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="include\core\Server.h">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="include\core\Stream.h">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="include\core\Tone.h">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="include\core\Uart.h">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="include\core\Udp.h">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="include\core\USB\CDC.h">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="include\core\USB\PluggableUSB.h">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="include\core\USB\samd21_host.h">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="include\core\USB\SAMD21_USBDevice.h">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="include\core\USB\USBAPI.h">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="include\core\USB\USBCore.h">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="include\core\USB\USBDesc.h">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="include\core\USB\USB_host.h">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="include\core\WCharacter.h">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="include\core\WInterrupts.h">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="include\core\wiring.h">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="include\core\wiring_analog.h">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="include\core\wiring_constants.h">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="include\core\wiring_digital.h">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="include\core\wiring_private.h">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="include\core\wiring_shift.h">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="include\core\WMath.h">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="include\core\WString.h">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="include\core\WVariant.h">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="include\libraries\wire\Wire.h">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="include\variants\pins_arduino.h">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="include\variants\variant.h">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="src\core\abi.cpp">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="src\core\avr\dtostrf.c">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="src\core\cortex_handlers.c">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="src\core\delay.c">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="src\core\hooks.c">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="src\core\IPAddress.cpp">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="src\core\itoa.c">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="src\core\main.cpp">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="src\core\new.cpp">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="src\core\PreprocessingAssembly\pulse_asm.S">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="src\core\Print.cpp">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="src\core\pulse.c">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="src\core\pulse_asm.S">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="src\core\Reset.cpp">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="src\core\SERCOM.cpp">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="src\core\startup.c">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="src\core\Stream.cpp">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="src\core\Tone.cpp">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="src\core\Uart.cpp">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="src\core\USB\CDC.cpp">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="src\core\USB\PluggableUSB.cpp">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="src\core\USB\samd21_host.c">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="src\core\USB\USBCore.cpp">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="src\core\WInterrupts.c">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="src\core\wiring.c">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="src\core\wiring_analog.c">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="src\core\wiring_digital.c">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="src\core\wiring_private.c">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="src\core\wiring_shift.c">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="src\core\WMath.cpp">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="src\core\WString.cpp">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="src\libraries\wire\Wire.cpp">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="src\variants\variant.cpp">
+ <SubType>compile</SubType>
+ </Compile>
+ </ItemGroup>
+ <ItemGroup>
+ <Folder Include="include\" />
+ <Folder Include="include\core\" />
+ <Folder Include="include\core\avr\" />
+ <Folder Include="include\core\USB\" />
+ <Folder Include="include\libraries\" />
+ <Folder Include="include\libraries\wire\" />
+ <Folder Include="include\variants\" />
+ <Folder Include="src\" />
+ <Folder Include="src\core\" />
+ <Folder Include="src\core\avr\" />
+ <Folder Include="src\core\PreprocessingAssembly\" />
+ <Folder Include="src\core\USB\" />
+ <Folder Include="src\libraries\" />
+ <Folder Include="src\libraries\wire\" />
+ <Folder Include="src\variants\" />
+ <Folder Include="src\variants\openocd_scripts\" />
+ </ItemGroup>
+ <ItemGroup>
+ <None Include="src\variants\openocd_scripts\arduino_zero.cfg">
+ <SubType>compile</SubType>
+ </None>
+ </ItemGroup>
+ <Import Project="$(AVRSTUDIO_EXE_PATH)\\Vs\\Compiler.targets" />
+</Project>
\ No newline at end of file
diff --git a/UsbReceive/UsbReceive/ArduinoCore/Debug/Makefile b/UsbReceive/UsbReceive/ArduinoCore/Debug/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..bea3ae15b712117ceb8885ccf206d7a09e46ae18
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/Debug/Makefile
@@ -0,0 +1,522 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+SHELL := cmd.exe
+RM := rm -rf
+
+USER_OBJS :=
+
+LIBS :=
+PROJ :=
+
+O_SRCS :=
+C_SRCS :=
+S_SRCS :=
+S_UPPER_SRCS :=
+OBJ_SRCS :=
+ASM_SRCS :=
+PREPROCESSING_SRCS :=
+OBJS :=
+OBJS_AS_ARGS :=
+C_DEPS :=
+C_DEPS_AS_ARGS :=
+EXECUTABLES :=
+OUTPUT_FILE_PATH :=
+OUTPUT_FILE_PATH_AS_ARGS :=
+AVR_APP_PATH :=$$$AVR_APP_PATH$$$
+QUOTE := "
+ADDITIONAL_DEPENDENCIES:=
+OUTPUT_FILE_DEP:=
+LIB_DEP:=
+LINKER_SCRIPT_DEP:=
+
+# Every subdirectory with source files must be described here
+SUBDIRS := \
+../include/ \
+../include/core/ \
+../include/core/avr/ \
+../include/core/USB/ \
+../include/libraries/ \
+../include/libraries/wire/ \
+../include/variants/ \
+../src/ \
+../src/core/ \
+../src/core/avr/ \
+../src/core/PreprocessingAssembly/ \
+../src/core/USB/ \
+../src/libraries/ \
+../src/libraries/wire/ \
+../src/variants/ \
+../src/variants/openocd_scripts/
+
+
+# Add inputs and outputs from these tool invocations to the build variables
+C_SRCS += \
+../src/core/abi.cpp \
+../src/core/avr/dtostrf.c \
+../src/core/cortex_handlers.c \
+../src/core/delay.c \
+../src/core/hooks.c \
+../src/core/IPAddress.cpp \
+../src/core/itoa.c \
+../src/core/main.cpp \
+../src/core/new.cpp \
+../src/core/Print.cpp \
+../src/core/pulse.c \
+../src/core/Reset.cpp \
+../src/core/SERCOM.cpp \
+../src/core/startup.c \
+../src/core/Stream.cpp \
+../src/core/Tone.cpp \
+../src/core/Uart.cpp \
+../src/core/USB/CDC.cpp \
+../src/core/USB/PluggableUSB.cpp \
+../src/core/USB/samd21_host.c \
+../src/core/USB/USBCore.cpp \
+../src/core/WInterrupts.c \
+../src/core/wiring.c \
+../src/core/wiring_analog.c \
+../src/core/wiring_digital.c \
+../src/core/wiring_private.c \
+../src/core/wiring_shift.c \
+../src/core/WMath.cpp \
+../src/core/WString.cpp \
+../src/libraries/wire/Wire.cpp \
+../src/variants/variant.cpp
+
+
+PREPROCESSING_SRCS += \
+../src/core/PreprocessingAssembly/pulse_asm.S \
+../src/core/pulse_asm.S
+
+
+ASM_SRCS +=
+
+
+OBJS += \
+src/core/abi.o \
+src/core/avr/dtostrf.o \
+src/core/cortex_handlers.o \
+src/core/delay.o \
+src/core/hooks.o \
+src/core/IPAddress.o \
+src/core/itoa.o \
+src/core/main.o \
+src/core/new.o \
+src/core/PreprocessingAssembly/pulse_asm.o \
+src/core/Print.o \
+src/core/pulse.o \
+src/core/pulse_asm.o \
+src/core/Reset.o \
+src/core/SERCOM.o \
+src/core/startup.o \
+src/core/Stream.o \
+src/core/Tone.o \
+src/core/Uart.o \
+src/core/USB/CDC.o \
+src/core/USB/PluggableUSB.o \
+src/core/USB/samd21_host.o \
+src/core/USB/USBCore.o \
+src/core/WInterrupts.o \
+src/core/wiring.o \
+src/core/wiring_analog.o \
+src/core/wiring_digital.o \
+src/core/wiring_private.o \
+src/core/wiring_shift.o \
+src/core/WMath.o \
+src/core/WString.o \
+src/libraries/wire/Wire.o \
+src/variants/variant.o
+
+OBJS_AS_ARGS += \
+src/core/abi.o \
+src/core/avr/dtostrf.o \
+src/core/cortex_handlers.o \
+src/core/delay.o \
+src/core/hooks.o \
+src/core/IPAddress.o \
+src/core/itoa.o \
+src/core/main.o \
+src/core/new.o \
+src/core/PreprocessingAssembly/pulse_asm.o \
+src/core/Print.o \
+src/core/pulse.o \
+src/core/pulse_asm.o \
+src/core/Reset.o \
+src/core/SERCOM.o \
+src/core/startup.o \
+src/core/Stream.o \
+src/core/Tone.o \
+src/core/Uart.o \
+src/core/USB/CDC.o \
+src/core/USB/PluggableUSB.o \
+src/core/USB/samd21_host.o \
+src/core/USB/USBCore.o \
+src/core/WInterrupts.o \
+src/core/wiring.o \
+src/core/wiring_analog.o \
+src/core/wiring_digital.o \
+src/core/wiring_private.o \
+src/core/wiring_shift.o \
+src/core/WMath.o \
+src/core/WString.o \
+src/libraries/wire/Wire.o \
+src/variants/variant.o
+
+C_DEPS += \
+src/core/abi.d \
+src/core/avr/dtostrf.d \
+src/core/cortex_handlers.d \
+src/core/delay.d \
+src/core/hooks.d \
+src/core/IPAddress.d \
+src/core/itoa.d \
+src/core/main.d \
+src/core/new.d \
+src/core/PreprocessingAssembly/pulse_asm.d \
+src/core/Print.d \
+src/core/pulse.d \
+src/core/pulse_asm.d \
+src/core/Reset.d \
+src/core/SERCOM.d \
+src/core/startup.d \
+src/core/Stream.d \
+src/core/Tone.d \
+src/core/Uart.d \
+src/core/USB/CDC.d \
+src/core/USB/PluggableUSB.d \
+src/core/USB/samd21_host.d \
+src/core/USB/USBCore.d \
+src/core/WInterrupts.d \
+src/core/wiring.d \
+src/core/wiring_analog.d \
+src/core/wiring_digital.d \
+src/core/wiring_private.d \
+src/core/wiring_shift.d \
+src/core/WMath.d \
+src/core/WString.d \
+src/libraries/wire/Wire.d \
+src/variants/variant.d
+
+C_DEPS_AS_ARGS += \
+src/core/abi.d \
+src/core/avr/dtostrf.d \
+src/core/cortex_handlers.d \
+src/core/delay.d \
+src/core/hooks.d \
+src/core/IPAddress.d \
+src/core/itoa.d \
+src/core/main.d \
+src/core/new.d \
+src/core/PreprocessingAssembly/pulse_asm.d \
+src/core/Print.d \
+src/core/pulse.d \
+src/core/pulse_asm.d \
+src/core/Reset.d \
+src/core/SERCOM.d \
+src/core/startup.d \
+src/core/Stream.d \
+src/core/Tone.d \
+src/core/Uart.d \
+src/core/USB/CDC.d \
+src/core/USB/PluggableUSB.d \
+src/core/USB/samd21_host.d \
+src/core/USB/USBCore.d \
+src/core/WInterrupts.d \
+src/core/wiring.d \
+src/core/wiring_analog.d \
+src/core/wiring_digital.d \
+src/core/wiring_private.d \
+src/core/wiring_shift.d \
+src/core/WMath.d \
+src/core/WString.d \
+src/libraries/wire/Wire.d \
+src/variants/variant.d
+
+OUTPUT_FILE_PATH +=libArduinoCore.a
+
+OUTPUT_FILE_PATH_AS_ARGS +=libArduinoCore.a
+
+ADDITIONAL_DEPENDENCIES:=
+
+OUTPUT_FILE_DEP:= ./makedep.mk
+
+LIB_DEP+=
+
+LINKER_SCRIPT_DEP+=
+
+
+# AVR32/GNU C Compiler
+src/core/abi.o: ../src/core/abi.cpp
+ @echo Building file: $<
+ @echo Invoking: ARM/GNU C Compiler : 6.3.1
+ $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-g++.exe$(QUOTE) -mthumb -D__SAMD21G18A__ -DDEBUG -DF_CPU=48000000L -DARDUINO=108019 -DARDUINO_SAMD_ZERO -DARDUINO_ARCH_SAMD -DUSB_VID=0x03EB -DUSB_PID=0x8009 -DUSB_PRODUCT="\"TinyZero\"" -DUSB_MANUFACTURER="\"TinyCircuits\"" -DUSBCON -DSAMD_SERIES -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"..\include\libraries\wire" -I"..\include\core" -I"..\include\core\avr" -I"..\include\core\USB" -I"..\include\variants" -Os -fno-threadsafe-statics -fno-exceptions -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -g3 -w -mcpu=cortex-m0plus -c -std=gnu++11 --param max-inline-insns-single=500 -nostdlib -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
+ @echo Finished building: $<
+
+
+src/core/avr/dtostrf.o: ../src/core/avr/dtostrf.c
+ @echo Building file: $<
+ @echo Invoking: ARM/GNU C Compiler : 6.3.1
+ $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAMD21G18A__ -DDEBUG -DF_CPU=48000000L -DARDUINO=108019 -DARDUINO_SAMD_ZERO -DARDUINO_ARCH_SAMD -DUSB_VID=0x03EB -DUSB_PID=0x8009 -DUSB_PRODUCT="\"TinyZero\"" -DUSB_MANUFACTURER="\"TinyCircuits\"" -DUSBCON -DSAMD_SERIES -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"..\include\libraries\wire" -I"..\include\core" -I"..\include\core\avr" -I"..\include\core\USB" -I"..\include\variants" -Os -fno-threadsafe-statics -fno-exceptions -ffunction-sections -fdata-sections -g3 -w -mcpu=cortex-m0plus -c -std=gnu11 --param max-inline-insns-single=500 -nostdlib -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
+ @echo Finished building: $<
+
+
+src/core/cortex_handlers.o: ../src/core/cortex_handlers.c
+ @echo Building file: $<
+ @echo Invoking: ARM/GNU C Compiler : 6.3.1
+ $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAMD21G18A__ -DDEBUG -DF_CPU=48000000L -DARDUINO=108019 -DARDUINO_SAMD_ZERO -DARDUINO_ARCH_SAMD -DUSB_VID=0x03EB -DUSB_PID=0x8009 -DUSB_PRODUCT="\"TinyZero\"" -DUSB_MANUFACTURER="\"TinyCircuits\"" -DUSBCON -DSAMD_SERIES -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"..\include\libraries\wire" -I"..\include\core" -I"..\include\core\avr" -I"..\include\core\USB" -I"..\include\variants" -Os -fno-threadsafe-statics -fno-exceptions -ffunction-sections -fdata-sections -g3 -w -mcpu=cortex-m0plus -c -std=gnu11 --param max-inline-insns-single=500 -nostdlib -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
+ @echo Finished building: $<
+
+
+src/core/delay.o: ../src/core/delay.c
+ @echo Building file: $<
+ @echo Invoking: ARM/GNU C Compiler : 6.3.1
+ $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAMD21G18A__ -DDEBUG -DF_CPU=48000000L -DARDUINO=108019 -DARDUINO_SAMD_ZERO -DARDUINO_ARCH_SAMD -DUSB_VID=0x03EB -DUSB_PID=0x8009 -DUSB_PRODUCT="\"TinyZero\"" -DUSB_MANUFACTURER="\"TinyCircuits\"" -DUSBCON -DSAMD_SERIES -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"..\include\libraries\wire" -I"..\include\core" -I"..\include\core\avr" -I"..\include\core\USB" -I"..\include\variants" -Os -fno-threadsafe-statics -fno-exceptions -ffunction-sections -fdata-sections -g3 -w -mcpu=cortex-m0plus -c -std=gnu11 --param max-inline-insns-single=500 -nostdlib -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
+ @echo Finished building: $<
+
+
+src/core/hooks.o: ../src/core/hooks.c
+ @echo Building file: $<
+ @echo Invoking: ARM/GNU C Compiler : 6.3.1
+ $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAMD21G18A__ -DDEBUG -DF_CPU=48000000L -DARDUINO=108019 -DARDUINO_SAMD_ZERO -DARDUINO_ARCH_SAMD -DUSB_VID=0x03EB -DUSB_PID=0x8009 -DUSB_PRODUCT="\"TinyZero\"" -DUSB_MANUFACTURER="\"TinyCircuits\"" -DUSBCON -DSAMD_SERIES -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"..\include\libraries\wire" -I"..\include\core" -I"..\include\core\avr" -I"..\include\core\USB" -I"..\include\variants" -Os -fno-threadsafe-statics -fno-exceptions -ffunction-sections -fdata-sections -g3 -w -mcpu=cortex-m0plus -c -std=gnu11 --param max-inline-insns-single=500 -nostdlib -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
+ @echo Finished building: $<
+
+
+src/core/IPAddress.o: ../src/core/IPAddress.cpp
+ @echo Building file: $<
+ @echo Invoking: ARM/GNU C Compiler : 6.3.1
+ $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-g++.exe$(QUOTE) -mthumb -D__SAMD21G18A__ -DDEBUG -DF_CPU=48000000L -DARDUINO=108019 -DARDUINO_SAMD_ZERO -DARDUINO_ARCH_SAMD -DUSB_VID=0x03EB -DUSB_PID=0x8009 -DUSB_PRODUCT="\"TinyZero\"" -DUSB_MANUFACTURER="\"TinyCircuits\"" -DUSBCON -DSAMD_SERIES -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"..\include\libraries\wire" -I"..\include\core" -I"..\include\core\avr" -I"..\include\core\USB" -I"..\include\variants" -Os -fno-threadsafe-statics -fno-exceptions -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -g3 -w -mcpu=cortex-m0plus -c -std=gnu++11 --param max-inline-insns-single=500 -nostdlib -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
+ @echo Finished building: $<
+
+
+src/core/itoa.o: ../src/core/itoa.c
+ @echo Building file: $<
+ @echo Invoking: ARM/GNU C Compiler : 6.3.1
+ $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAMD21G18A__ -DDEBUG -DF_CPU=48000000L -DARDUINO=108019 -DARDUINO_SAMD_ZERO -DARDUINO_ARCH_SAMD -DUSB_VID=0x03EB -DUSB_PID=0x8009 -DUSB_PRODUCT="\"TinyZero\"" -DUSB_MANUFACTURER="\"TinyCircuits\"" -DUSBCON -DSAMD_SERIES -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"..\include\libraries\wire" -I"..\include\core" -I"..\include\core\avr" -I"..\include\core\USB" -I"..\include\variants" -Os -fno-threadsafe-statics -fno-exceptions -ffunction-sections -fdata-sections -g3 -w -mcpu=cortex-m0plus -c -std=gnu11 --param max-inline-insns-single=500 -nostdlib -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
+ @echo Finished building: $<
+
+
+src/core/main.o: ../src/core/main.cpp
+ @echo Building file: $<
+ @echo Invoking: ARM/GNU C Compiler : 6.3.1
+ $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-g++.exe$(QUOTE) -mthumb -D__SAMD21G18A__ -DDEBUG -DF_CPU=48000000L -DARDUINO=108019 -DARDUINO_SAMD_ZERO -DARDUINO_ARCH_SAMD -DUSB_VID=0x03EB -DUSB_PID=0x8009 -DUSB_PRODUCT="\"TinyZero\"" -DUSB_MANUFACTURER="\"TinyCircuits\"" -DUSBCON -DSAMD_SERIES -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"..\include\libraries\wire" -I"..\include\core" -I"..\include\core\avr" -I"..\include\core\USB" -I"..\include\variants" -Os -fno-threadsafe-statics -fno-exceptions -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -g3 -w -mcpu=cortex-m0plus -c -std=gnu++11 --param max-inline-insns-single=500 -nostdlib -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
+ @echo Finished building: $<
+
+
+src/core/new.o: ../src/core/new.cpp
+ @echo Building file: $<
+ @echo Invoking: ARM/GNU C Compiler : 6.3.1
+ $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-g++.exe$(QUOTE) -mthumb -D__SAMD21G18A__ -DDEBUG -DF_CPU=48000000L -DARDUINO=108019 -DARDUINO_SAMD_ZERO -DARDUINO_ARCH_SAMD -DUSB_VID=0x03EB -DUSB_PID=0x8009 -DUSB_PRODUCT="\"TinyZero\"" -DUSB_MANUFACTURER="\"TinyCircuits\"" -DUSBCON -DSAMD_SERIES -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"..\include\libraries\wire" -I"..\include\core" -I"..\include\core\avr" -I"..\include\core\USB" -I"..\include\variants" -Os -fno-threadsafe-statics -fno-exceptions -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -g3 -w -mcpu=cortex-m0plus -c -std=gnu++11 --param max-inline-insns-single=500 -nostdlib -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
+ @echo Finished building: $<
+
+
+src/core/Print.o: ../src/core/Print.cpp
+ @echo Building file: $<
+ @echo Invoking: ARM/GNU C Compiler : 6.3.1
+ $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-g++.exe$(QUOTE) -mthumb -D__SAMD21G18A__ -DDEBUG -DF_CPU=48000000L -DARDUINO=108019 -DARDUINO_SAMD_ZERO -DARDUINO_ARCH_SAMD -DUSB_VID=0x03EB -DUSB_PID=0x8009 -DUSB_PRODUCT="\"TinyZero\"" -DUSB_MANUFACTURER="\"TinyCircuits\"" -DUSBCON -DSAMD_SERIES -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"..\include\libraries\wire" -I"..\include\core" -I"..\include\core\avr" -I"..\include\core\USB" -I"..\include\variants" -Os -fno-threadsafe-statics -fno-exceptions -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -g3 -w -mcpu=cortex-m0plus -c -std=gnu++11 --param max-inline-insns-single=500 -nostdlib -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
+ @echo Finished building: $<
+
+
+src/core/pulse.o: ../src/core/pulse.c
+ @echo Building file: $<
+ @echo Invoking: ARM/GNU C Compiler : 6.3.1
+ $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAMD21G18A__ -DDEBUG -DF_CPU=48000000L -DARDUINO=108019 -DARDUINO_SAMD_ZERO -DARDUINO_ARCH_SAMD -DUSB_VID=0x03EB -DUSB_PID=0x8009 -DUSB_PRODUCT="\"TinyZero\"" -DUSB_MANUFACTURER="\"TinyCircuits\"" -DUSBCON -DSAMD_SERIES -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"..\include\libraries\wire" -I"..\include\core" -I"..\include\core\avr" -I"..\include\core\USB" -I"..\include\variants" -Os -fno-threadsafe-statics -fno-exceptions -ffunction-sections -fdata-sections -g3 -w -mcpu=cortex-m0plus -c -std=gnu11 --param max-inline-insns-single=500 -nostdlib -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
+ @echo Finished building: $<
+
+
+src/core/Reset.o: ../src/core/Reset.cpp
+ @echo Building file: $<
+ @echo Invoking: ARM/GNU C Compiler : 6.3.1
+ $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-g++.exe$(QUOTE) -mthumb -D__SAMD21G18A__ -DDEBUG -DF_CPU=48000000L -DARDUINO=108019 -DARDUINO_SAMD_ZERO -DARDUINO_ARCH_SAMD -DUSB_VID=0x03EB -DUSB_PID=0x8009 -DUSB_PRODUCT="\"TinyZero\"" -DUSB_MANUFACTURER="\"TinyCircuits\"" -DUSBCON -DSAMD_SERIES -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"..\include\libraries\wire" -I"..\include\core" -I"..\include\core\avr" -I"..\include\core\USB" -I"..\include\variants" -Os -fno-threadsafe-statics -fno-exceptions -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -g3 -w -mcpu=cortex-m0plus -c -std=gnu++11 --param max-inline-insns-single=500 -nostdlib -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
+ @echo Finished building: $<
+
+
+src/core/SERCOM.o: ../src/core/SERCOM.cpp
+ @echo Building file: $<
+ @echo Invoking: ARM/GNU C Compiler : 6.3.1
+ $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-g++.exe$(QUOTE) -mthumb -D__SAMD21G18A__ -DDEBUG -DF_CPU=48000000L -DARDUINO=108019 -DARDUINO_SAMD_ZERO -DARDUINO_ARCH_SAMD -DUSB_VID=0x03EB -DUSB_PID=0x8009 -DUSB_PRODUCT="\"TinyZero\"" -DUSB_MANUFACTURER="\"TinyCircuits\"" -DUSBCON -DSAMD_SERIES -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"..\include\libraries\wire" -I"..\include\core" -I"..\include\core\avr" -I"..\include\core\USB" -I"..\include\variants" -Os -fno-threadsafe-statics -fno-exceptions -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -g3 -w -mcpu=cortex-m0plus -c -std=gnu++11 --param max-inline-insns-single=500 -nostdlib -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
+ @echo Finished building: $<
+
+
+src/core/startup.o: ../src/core/startup.c
+ @echo Building file: $<
+ @echo Invoking: ARM/GNU C Compiler : 6.3.1
+ $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAMD21G18A__ -DDEBUG -DF_CPU=48000000L -DARDUINO=108019 -DARDUINO_SAMD_ZERO -DARDUINO_ARCH_SAMD -DUSB_VID=0x03EB -DUSB_PID=0x8009 -DUSB_PRODUCT="\"TinyZero\"" -DUSB_MANUFACTURER="\"TinyCircuits\"" -DUSBCON -DSAMD_SERIES -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"..\include\libraries\wire" -I"..\include\core" -I"..\include\core\avr" -I"..\include\core\USB" -I"..\include\variants" -Os -fno-threadsafe-statics -fno-exceptions -ffunction-sections -fdata-sections -g3 -w -mcpu=cortex-m0plus -c -std=gnu11 --param max-inline-insns-single=500 -nostdlib -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
+ @echo Finished building: $<
+
+
+src/core/Stream.o: ../src/core/Stream.cpp
+ @echo Building file: $<
+ @echo Invoking: ARM/GNU C Compiler : 6.3.1
+ $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-g++.exe$(QUOTE) -mthumb -D__SAMD21G18A__ -DDEBUG -DF_CPU=48000000L -DARDUINO=108019 -DARDUINO_SAMD_ZERO -DARDUINO_ARCH_SAMD -DUSB_VID=0x03EB -DUSB_PID=0x8009 -DUSB_PRODUCT="\"TinyZero\"" -DUSB_MANUFACTURER="\"TinyCircuits\"" -DUSBCON -DSAMD_SERIES -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"..\include\libraries\wire" -I"..\include\core" -I"..\include\core\avr" -I"..\include\core\USB" -I"..\include\variants" -Os -fno-threadsafe-statics -fno-exceptions -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -g3 -w -mcpu=cortex-m0plus -c -std=gnu++11 --param max-inline-insns-single=500 -nostdlib -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
+ @echo Finished building: $<
+
+
+src/core/Tone.o: ../src/core/Tone.cpp
+ @echo Building file: $<
+ @echo Invoking: ARM/GNU C Compiler : 6.3.1
+ $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-g++.exe$(QUOTE) -mthumb -D__SAMD21G18A__ -DDEBUG -DF_CPU=48000000L -DARDUINO=108019 -DARDUINO_SAMD_ZERO -DARDUINO_ARCH_SAMD -DUSB_VID=0x03EB -DUSB_PID=0x8009 -DUSB_PRODUCT="\"TinyZero\"" -DUSB_MANUFACTURER="\"TinyCircuits\"" -DUSBCON -DSAMD_SERIES -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"..\include\libraries\wire" -I"..\include\core" -I"..\include\core\avr" -I"..\include\core\USB" -I"..\include\variants" -Os -fno-threadsafe-statics -fno-exceptions -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -g3 -w -mcpu=cortex-m0plus -c -std=gnu++11 --param max-inline-insns-single=500 -nostdlib -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
+ @echo Finished building: $<
+
+
+src/core/Uart.o: ../src/core/Uart.cpp
+ @echo Building file: $<
+ @echo Invoking: ARM/GNU C Compiler : 6.3.1
+ $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-g++.exe$(QUOTE) -mthumb -D__SAMD21G18A__ -DDEBUG -DF_CPU=48000000L -DARDUINO=108019 -DARDUINO_SAMD_ZERO -DARDUINO_ARCH_SAMD -DUSB_VID=0x03EB -DUSB_PID=0x8009 -DUSB_PRODUCT="\"TinyZero\"" -DUSB_MANUFACTURER="\"TinyCircuits\"" -DUSBCON -DSAMD_SERIES -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"..\include\libraries\wire" -I"..\include\core" -I"..\include\core\avr" -I"..\include\core\USB" -I"..\include\variants" -Os -fno-threadsafe-statics -fno-exceptions -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -g3 -w -mcpu=cortex-m0plus -c -std=gnu++11 --param max-inline-insns-single=500 -nostdlib -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
+ @echo Finished building: $<
+
+
+src/core/USB/CDC.o: ../src/core/USB/CDC.cpp
+ @echo Building file: $<
+ @echo Invoking: ARM/GNU C Compiler : 6.3.1
+ $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-g++.exe$(QUOTE) -mthumb -D__SAMD21G18A__ -DDEBUG -DF_CPU=48000000L -DARDUINO=108019 -DARDUINO_SAMD_ZERO -DARDUINO_ARCH_SAMD -DUSB_VID=0x03EB -DUSB_PID=0x8009 -DUSB_PRODUCT="\"TinyZero\"" -DUSB_MANUFACTURER="\"TinyCircuits\"" -DUSBCON -DSAMD_SERIES -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"..\include\libraries\wire" -I"..\include\core" -I"..\include\core\avr" -I"..\include\core\USB" -I"..\include\variants" -Os -fno-threadsafe-statics -fno-exceptions -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -g3 -w -mcpu=cortex-m0plus -c -std=gnu++11 --param max-inline-insns-single=500 -nostdlib -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
+ @echo Finished building: $<
+
+
+src/core/USB/PluggableUSB.o: ../src/core/USB/PluggableUSB.cpp
+ @echo Building file: $<
+ @echo Invoking: ARM/GNU C Compiler : 6.3.1
+ $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-g++.exe$(QUOTE) -mthumb -D__SAMD21G18A__ -DDEBUG -DF_CPU=48000000L -DARDUINO=108019 -DARDUINO_SAMD_ZERO -DARDUINO_ARCH_SAMD -DUSB_VID=0x03EB -DUSB_PID=0x8009 -DUSB_PRODUCT="\"TinyZero\"" -DUSB_MANUFACTURER="\"TinyCircuits\"" -DUSBCON -DSAMD_SERIES -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"..\include\libraries\wire" -I"..\include\core" -I"..\include\core\avr" -I"..\include\core\USB" -I"..\include\variants" -Os -fno-threadsafe-statics -fno-exceptions -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -g3 -w -mcpu=cortex-m0plus -c -std=gnu++11 --param max-inline-insns-single=500 -nostdlib -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
+ @echo Finished building: $<
+
+
+src/core/USB/samd21_host.o: ../src/core/USB/samd21_host.c
+ @echo Building file: $<
+ @echo Invoking: ARM/GNU C Compiler : 6.3.1
+ $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAMD21G18A__ -DDEBUG -DF_CPU=48000000L -DARDUINO=108019 -DARDUINO_SAMD_ZERO -DARDUINO_ARCH_SAMD -DUSB_VID=0x03EB -DUSB_PID=0x8009 -DUSB_PRODUCT="\"TinyZero\"" -DUSB_MANUFACTURER="\"TinyCircuits\"" -DUSBCON -DSAMD_SERIES -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"..\include\libraries\wire" -I"..\include\core" -I"..\include\core\avr" -I"..\include\core\USB" -I"..\include\variants" -Os -fno-threadsafe-statics -fno-exceptions -ffunction-sections -fdata-sections -g3 -w -mcpu=cortex-m0plus -c -std=gnu11 --param max-inline-insns-single=500 -nostdlib -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
+ @echo Finished building: $<
+
+
+src/core/USB/USBCore.o: ../src/core/USB/USBCore.cpp
+ @echo Building file: $<
+ @echo Invoking: ARM/GNU C Compiler : 6.3.1
+ $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-g++.exe$(QUOTE) -mthumb -D__SAMD21G18A__ -DDEBUG -DF_CPU=48000000L -DARDUINO=108019 -DARDUINO_SAMD_ZERO -DARDUINO_ARCH_SAMD -DUSB_VID=0x03EB -DUSB_PID=0x8009 -DUSB_PRODUCT="\"TinyZero\"" -DUSB_MANUFACTURER="\"TinyCircuits\"" -DUSBCON -DSAMD_SERIES -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"..\include\libraries\wire" -I"..\include\core" -I"..\include\core\avr" -I"..\include\core\USB" -I"..\include\variants" -Os -fno-threadsafe-statics -fno-exceptions -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -g3 -w -mcpu=cortex-m0plus -c -std=gnu++11 --param max-inline-insns-single=500 -nostdlib -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
+ @echo Finished building: $<
+
+
+src/core/WInterrupts.o: ../src/core/WInterrupts.c
+ @echo Building file: $<
+ @echo Invoking: ARM/GNU C Compiler : 6.3.1
+ $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAMD21G18A__ -DDEBUG -DF_CPU=48000000L -DARDUINO=108019 -DARDUINO_SAMD_ZERO -DARDUINO_ARCH_SAMD -DUSB_VID=0x03EB -DUSB_PID=0x8009 -DUSB_PRODUCT="\"TinyZero\"" -DUSB_MANUFACTURER="\"TinyCircuits\"" -DUSBCON -DSAMD_SERIES -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"..\include\libraries\wire" -I"..\include\core" -I"..\include\core\avr" -I"..\include\core\USB" -I"..\include\variants" -Os -fno-threadsafe-statics -fno-exceptions -ffunction-sections -fdata-sections -g3 -w -mcpu=cortex-m0plus -c -std=gnu11 --param max-inline-insns-single=500 -nostdlib -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
+ @echo Finished building: $<
+
+
+src/core/wiring.o: ../src/core/wiring.c
+ @echo Building file: $<
+ @echo Invoking: ARM/GNU C Compiler : 6.3.1
+ $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAMD21G18A__ -DDEBUG -DF_CPU=48000000L -DARDUINO=108019 -DARDUINO_SAMD_ZERO -DARDUINO_ARCH_SAMD -DUSB_VID=0x03EB -DUSB_PID=0x8009 -DUSB_PRODUCT="\"TinyZero\"" -DUSB_MANUFACTURER="\"TinyCircuits\"" -DUSBCON -DSAMD_SERIES -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"..\include\libraries\wire" -I"..\include\core" -I"..\include\core\avr" -I"..\include\core\USB" -I"..\include\variants" -Os -fno-threadsafe-statics -fno-exceptions -ffunction-sections -fdata-sections -g3 -w -mcpu=cortex-m0plus -c -std=gnu11 --param max-inline-insns-single=500 -nostdlib -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
+ @echo Finished building: $<
+
+
+src/core/wiring_analog.o: ../src/core/wiring_analog.c
+ @echo Building file: $<
+ @echo Invoking: ARM/GNU C Compiler : 6.3.1
+ $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAMD21G18A__ -DDEBUG -DF_CPU=48000000L -DARDUINO=108019 -DARDUINO_SAMD_ZERO -DARDUINO_ARCH_SAMD -DUSB_VID=0x03EB -DUSB_PID=0x8009 -DUSB_PRODUCT="\"TinyZero\"" -DUSB_MANUFACTURER="\"TinyCircuits\"" -DUSBCON -DSAMD_SERIES -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"..\include\libraries\wire" -I"..\include\core" -I"..\include\core\avr" -I"..\include\core\USB" -I"..\include\variants" -Os -fno-threadsafe-statics -fno-exceptions -ffunction-sections -fdata-sections -g3 -w -mcpu=cortex-m0plus -c -std=gnu11 --param max-inline-insns-single=500 -nostdlib -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
+ @echo Finished building: $<
+
+
+src/core/wiring_digital.o: ../src/core/wiring_digital.c
+ @echo Building file: $<
+ @echo Invoking: ARM/GNU C Compiler : 6.3.1
+ $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAMD21G18A__ -DDEBUG -DF_CPU=48000000L -DARDUINO=108019 -DARDUINO_SAMD_ZERO -DARDUINO_ARCH_SAMD -DUSB_VID=0x03EB -DUSB_PID=0x8009 -DUSB_PRODUCT="\"TinyZero\"" -DUSB_MANUFACTURER="\"TinyCircuits\"" -DUSBCON -DSAMD_SERIES -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"..\include\libraries\wire" -I"..\include\core" -I"..\include\core\avr" -I"..\include\core\USB" -I"..\include\variants" -Os -fno-threadsafe-statics -fno-exceptions -ffunction-sections -fdata-sections -g3 -w -mcpu=cortex-m0plus -c -std=gnu11 --param max-inline-insns-single=500 -nostdlib -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
+ @echo Finished building: $<
+
+
+src/core/wiring_private.o: ../src/core/wiring_private.c
+ @echo Building file: $<
+ @echo Invoking: ARM/GNU C Compiler : 6.3.1
+ $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAMD21G18A__ -DDEBUG -DF_CPU=48000000L -DARDUINO=108019 -DARDUINO_SAMD_ZERO -DARDUINO_ARCH_SAMD -DUSB_VID=0x03EB -DUSB_PID=0x8009 -DUSB_PRODUCT="\"TinyZero\"" -DUSB_MANUFACTURER="\"TinyCircuits\"" -DUSBCON -DSAMD_SERIES -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"..\include\libraries\wire" -I"..\include\core" -I"..\include\core\avr" -I"..\include\core\USB" -I"..\include\variants" -Os -fno-threadsafe-statics -fno-exceptions -ffunction-sections -fdata-sections -g3 -w -mcpu=cortex-m0plus -c -std=gnu11 --param max-inline-insns-single=500 -nostdlib -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
+ @echo Finished building: $<
+
+
+src/core/wiring_shift.o: ../src/core/wiring_shift.c
+ @echo Building file: $<
+ @echo Invoking: ARM/GNU C Compiler : 6.3.1
+ $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAMD21G18A__ -DDEBUG -DF_CPU=48000000L -DARDUINO=108019 -DARDUINO_SAMD_ZERO -DARDUINO_ARCH_SAMD -DUSB_VID=0x03EB -DUSB_PID=0x8009 -DUSB_PRODUCT="\"TinyZero\"" -DUSB_MANUFACTURER="\"TinyCircuits\"" -DUSBCON -DSAMD_SERIES -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"..\include\libraries\wire" -I"..\include\core" -I"..\include\core\avr" -I"..\include\core\USB" -I"..\include\variants" -Os -fno-threadsafe-statics -fno-exceptions -ffunction-sections -fdata-sections -g3 -w -mcpu=cortex-m0plus -c -std=gnu11 --param max-inline-insns-single=500 -nostdlib -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
+ @echo Finished building: $<
+
+
+src/core/WMath.o: ../src/core/WMath.cpp
+ @echo Building file: $<
+ @echo Invoking: ARM/GNU C Compiler : 6.3.1
+ $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-g++.exe$(QUOTE) -mthumb -D__SAMD21G18A__ -DDEBUG -DF_CPU=48000000L -DARDUINO=108019 -DARDUINO_SAMD_ZERO -DARDUINO_ARCH_SAMD -DUSB_VID=0x03EB -DUSB_PID=0x8009 -DUSB_PRODUCT="\"TinyZero\"" -DUSB_MANUFACTURER="\"TinyCircuits\"" -DUSBCON -DSAMD_SERIES -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"..\include\libraries\wire" -I"..\include\core" -I"..\include\core\avr" -I"..\include\core\USB" -I"..\include\variants" -Os -fno-threadsafe-statics -fno-exceptions -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -g3 -w -mcpu=cortex-m0plus -c -std=gnu++11 --param max-inline-insns-single=500 -nostdlib -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
+ @echo Finished building: $<
+
+
+src/core/WString.o: ../src/core/WString.cpp
+ @echo Building file: $<
+ @echo Invoking: ARM/GNU C Compiler : 6.3.1
+ $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-g++.exe$(QUOTE) -mthumb -D__SAMD21G18A__ -DDEBUG -DF_CPU=48000000L -DARDUINO=108019 -DARDUINO_SAMD_ZERO -DARDUINO_ARCH_SAMD -DUSB_VID=0x03EB -DUSB_PID=0x8009 -DUSB_PRODUCT="\"TinyZero\"" -DUSB_MANUFACTURER="\"TinyCircuits\"" -DUSBCON -DSAMD_SERIES -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"..\include\libraries\wire" -I"..\include\core" -I"..\include\core\avr" -I"..\include\core\USB" -I"..\include\variants" -Os -fno-threadsafe-statics -fno-exceptions -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -g3 -w -mcpu=cortex-m0plus -c -std=gnu++11 --param max-inline-insns-single=500 -nostdlib -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
+ @echo Finished building: $<
+
+
+src/libraries/wire/Wire.o: ../src/libraries/wire/Wire.cpp
+ @echo Building file: $<
+ @echo Invoking: ARM/GNU C Compiler : 6.3.1
+ $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-g++.exe$(QUOTE) -mthumb -D__SAMD21G18A__ -DDEBUG -DF_CPU=48000000L -DARDUINO=108019 -DARDUINO_SAMD_ZERO -DARDUINO_ARCH_SAMD -DUSB_VID=0x03EB -DUSB_PID=0x8009 -DUSB_PRODUCT="\"TinyZero\"" -DUSB_MANUFACTURER="\"TinyCircuits\"" -DUSBCON -DSAMD_SERIES -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"..\include\libraries\wire" -I"..\include\core" -I"..\include\core\avr" -I"..\include\core\USB" -I"..\include\variants" -Os -fno-threadsafe-statics -fno-exceptions -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -g3 -w -mcpu=cortex-m0plus -c -std=gnu++11 --param max-inline-insns-single=500 -nostdlib -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
+ @echo Finished building: $<
+
+
+src/variants/variant.o: ../src/variants/variant.cpp
+ @echo Building file: $<
+ @echo Invoking: ARM/GNU C Compiler : 6.3.1
+ $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-g++.exe$(QUOTE) -mthumb -D__SAMD21G18A__ -DDEBUG -DF_CPU=48000000L -DARDUINO=108019 -DARDUINO_SAMD_ZERO -DARDUINO_ARCH_SAMD -DUSB_VID=0x03EB -DUSB_PID=0x8009 -DUSB_PRODUCT="\"TinyZero\"" -DUSB_MANUFACTURER="\"TinyCircuits\"" -DUSBCON -DSAMD_SERIES -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"..\include\libraries\wire" -I"..\include\core" -I"..\include\core\avr" -I"..\include\core\USB" -I"..\include\variants" -Os -fno-threadsafe-statics -fno-exceptions -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -g3 -w -mcpu=cortex-m0plus -c -std=gnu++11 --param max-inline-insns-single=500 -nostdlib -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
+ @echo Finished building: $<
+
+
+
+
+
+# AVR32/GNU Preprocessing Assembler
+src/core/PreprocessingAssembly/pulse_asm.o: ../src/core/PreprocessingAssembly/pulse_asm.S
+ @echo Building file: $<
+ @echo Invoking: ARM/GNU Preprocessing Assembler : 6.3.1
+ $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -mthumb -x assembler-with-cpp -c -mcpu=cortex-m0plus -I "C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I "C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAMD21_DFP\1.3.395\samd21a\include" -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -D__SAMD21G18A__ -Wa,-g -o "$@" "$<"
+ @echo Finished building: $<
+
+
+src/core/pulse_asm.o: ../src/core/pulse_asm.S
+ @echo Building file: $<
+ @echo Invoking: ARM/GNU Preprocessing Assembler : 6.3.1
+ $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -mthumb -x assembler-with-cpp -c -mcpu=cortex-m0plus -I "C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I "C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAMD21_DFP\1.3.395\samd21a\include" -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -D__SAMD21G18A__ -Wa,-g -o "$@" "$<"
+ @echo Finished building: $<
+
+
+
+
+
+# AVR32/GNU Assembler
+
+
+
+
+ifneq ($(MAKECMDGOALS),clean)
+ifneq ($(strip $(C_DEPS)),)
+-include $(C_DEPS)
+endif
+endif
+
+# Add inputs and outputs from these tool invocations to the build variables
+
+# All Target
+all: $(OUTPUT_FILE_PATH) $(ADDITIONAL_DEPENDENCIES)
+
+
+$(OUTPUT_FILE_PATH): $(OBJS) $(USER_OBJS) $(OUTPUT_FILE_DEP)
+ @echo Building target: $@
+ @echo Invoking: ARM/GNU Archiver : 6.3.1
+ $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-ar.exe$(QUOTE) -r -o$(OUTPUT_FILE_PATH_AS_ARGS) $(OBJS_AS_ARGS) $(USER_OBJS) $(LIBS)
+ @echo Finished building target: $@
+
+
+
+
+
+
+# Other Targets
+clean:
+ -$(RM) $(OBJS_AS_ARGS) $(EXECUTABLES)
+ -$(RM) $(C_DEPS_AS_ARGS)
+ rm -rf "libArduinoCore.elf" "libArduinoCore.a" "libArduinoCore.hex" "libArduinoCore.bin" "libArduinoCore.lss" "libArduinoCore.eep" "libArduinoCore.map" "libArduinoCore.srec"
+
\ No newline at end of file
diff --git a/UsbReceive/UsbReceive/ArduinoCore/Debug/libArduinoCore.a b/UsbReceive/UsbReceive/ArduinoCore/Debug/libArduinoCore.a
new file mode 100644
index 0000000000000000000000000000000000000000..a859a05ab06f1cd6c06edadf76adc67c54535f8a
Binary files /dev/null and b/UsbReceive/UsbReceive/ArduinoCore/Debug/libArduinoCore.a differ
diff --git a/UsbReceive/UsbReceive/ArduinoCore/Debug/makedep.mk b/UsbReceive/UsbReceive/ArduinoCore/Debug/makedep.mk
new file mode 100644
index 0000000000000000000000000000000000000000..ce6516771829b7e70a91e8db101a89b3f5f82ba6
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/Debug/makedep.mk
@@ -0,0 +1,70 @@
+################################################################################
+# Automatically-generated file. Do not edit or delete the file
+################################################################################
+
+src\core\abi.cpp
+
+src\core\avr\dtostrf.c
+
+src\core\cortex_handlers.c
+
+src\core\delay.c
+
+src\core\hooks.c
+
+src\core\IPAddress.cpp
+
+src\core\itoa.c
+
+src\core\main.cpp
+
+src\core\new.cpp
+
+src\core\PreprocessingAssembly\pulse_asm.S
+
+src\core\Print.cpp
+
+src\core\pulse.c
+
+src\core\pulse_asm.S
+
+src\core\Reset.cpp
+
+src\core\SERCOM.cpp
+
+src\core\startup.c
+
+src\core\Stream.cpp
+
+src\core\Tone.cpp
+
+src\core\Uart.cpp
+
+src\core\USB\CDC.cpp
+
+src\core\USB\PluggableUSB.cpp
+
+src\core\USB\samd21_host.c
+
+src\core\USB\USBCore.cpp
+
+src\core\WInterrupts.c
+
+src\core\wiring.c
+
+src\core\wiring_analog.c
+
+src\core\wiring_digital.c
+
+src\core\wiring_private.c
+
+src\core\wiring_shift.c
+
+src\core\WMath.cpp
+
+src\core\WString.cpp
+
+src\libraries\wire\Wire.cpp
+
+src\variants\variant.cpp
+
diff --git a/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/IPAddress.d b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/IPAddress.d
new file mode 100644
index 0000000000000000000000000000000000000000..35db1df82449d1ef235a391690d9acfe3d58df07
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/IPAddress.d
@@ -0,0 +1,451 @@
+src/core/IPAddress.d src/core/IPAddress.o: ../src/core/IPAddress.cpp \
+ ..\include\core/Arduino.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cstdlib \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\c++config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\os_defines.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\cpu_defines.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\string.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\xlocale.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\string.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\math.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cmath \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\bits\cpp_type_traits.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\ext\type_traits.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\math.h \
+ ..\include\core/avr/pgmspace.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\inttypes.h \
+ ..\include\core/avr/interrupt.h ..\include\core/avr/io.h \
+ ..\include\core/binary.h ..\include\core/itoa.h ..\include\core/sam.h \
+ ..\include\core/samd.h ..\include\core/samd21/include/samd21.h \
+ ..\include\core/samd21/include/samd21g18a.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h \
+ ..\include\core/samd21/include/system_samd21.h \
+ ..\include\core/samd21/include/component/ac.h \
+ ..\include\core/samd21/include/component/adc.h \
+ ..\include\core/samd21/include/component/dac.h \
+ ..\include\core/samd21/include/component/dmac.h \
+ ..\include\core/samd21/include/component/dsu.h \
+ ..\include\core/samd21/include/component/eic.h \
+ ..\include\core/samd21/include/component/evsys.h \
+ ..\include\core/samd21/include/component/gclk.h \
+ ..\include\core/samd21/include/component/hmatrixb.h \
+ ..\include\core/samd21/include/component/i2s.h \
+ ..\include\core/samd21/include/component/mtb.h \
+ ..\include\core/samd21/include/component/nvmctrl.h \
+ ..\include\core/samd21/include/component/pac.h \
+ ..\include\core/samd21/include/component/pm.h \
+ ..\include\core/samd21/include/component/port.h \
+ ..\include\core/samd21/include/component/rtc.h \
+ ..\include\core/samd21/include/component/sercom.h \
+ ..\include\core/samd21/include/component/sysctrl.h \
+ ..\include\core/samd21/include/component/tc.h \
+ ..\include\core/samd21/include/component/tcc.h \
+ ..\include\core/samd21/include/component/usb.h \
+ ..\include\core/samd21/include/component/wdt.h \
+ ..\include\core/samd21/include/instance/ac.h \
+ ..\include\core/samd21/include/instance/adc.h \
+ ..\include\core/samd21/include/instance/dac.h \
+ ..\include\core/samd21/include/instance/dmac.h \
+ ..\include\core/samd21/include/instance/dsu.h \
+ ..\include\core/samd21/include/instance/eic.h \
+ ..\include\core/samd21/include/instance/evsys.h \
+ ..\include\core/samd21/include/instance/gclk.h \
+ ..\include\core/samd21/include/instance/sbmatrix.h \
+ ..\include\core/samd21/include/instance/i2s.h \
+ ..\include\core/samd21/include/instance/mtb.h \
+ ..\include\core/samd21/include/instance/nvmctrl.h \
+ ..\include\core/samd21/include/instance/pac0.h \
+ ..\include\core/samd21/include/instance/pac1.h \
+ ..\include\core/samd21/include/instance/pac2.h \
+ ..\include\core/samd21/include/instance/pm.h \
+ ..\include\core/samd21/include/instance/port.h \
+ ..\include\core/samd21/include/instance/rtc.h \
+ ..\include\core/samd21/include/instance/sercom0.h \
+ ..\include\core/samd21/include/instance/sercom1.h \
+ ..\include\core/samd21/include/instance/sercom2.h \
+ ..\include\core/samd21/include/instance/sercom3.h \
+ ..\include\core/samd21/include/instance/sercom4.h \
+ ..\include\core/samd21/include/instance/sercom5.h \
+ ..\include\core/samd21/include/instance/sysctrl.h \
+ ..\include\core/samd21/include/instance/tc3.h \
+ ..\include\core/samd21/include/instance/tc4.h \
+ ..\include\core/samd21/include/instance/tc5.h \
+ ..\include\core/samd21/include/instance/tcc0.h \
+ ..\include\core/samd21/include/instance/tcc1.h \
+ ..\include\core/samd21/include/instance/tcc2.h \
+ ..\include\core/samd21/include/instance/usb.h \
+ ..\include\core/samd21/include/instance/wdt.h \
+ ..\include\core/samd21/include/pio/samd21g18a.h \
+ ..\include\core/wiring_constants.h ..\include\core/WVariant.h \
+ ..\include\core/WCharacter.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\ctype.h \
+ ..\include\core/WString.h ..\include\core/avr/pgmspace.h \
+ ..\include\core/Tone.h ..\include\core/Arduino.h ..\include\core/WMath.h \
+ ..\include\core/HardwareSerial.h ..\include\core/Stream.h \
+ ..\include\core/Print.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
+ ..\include\core/Printable.h ..\include\core/pulse.h \
+ ..\include\core/delay.h ..\include\variants/variant.h \
+ ..\include\core/SERCOM.h ..\include\core/Uart.h ..\include\core/SERCOM.h \
+ ..\include\core/RingBuffer.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cstddef \
+ ..\include\core/wiring.h ..\include\core/wiring_digital.h \
+ ..\include\core/wiring_analog.h ..\include\core/wiring_shift.h \
+ ..\include\core/WInterrupts.h ..\include\core/USB/USBDesc.h \
+ ..\include\core/USB/USBCore.h ..\include\core/USB/USBAPI.h \
+ ..\include\core/Stream.h ..\include\core/RingBuffer.h \
+ ..\include\core/USB/USB_host.h ..\include\core/USB/samd21_host.h \
+ ..\include\core/USB/CDC.h ..\include\core/USB/USBDesc.h \
+ ..\include\core/USB/PluggableUSB.h ..\include\core/IPAddress.h
+
+..\include\core/Arduino.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cstdlib:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\c++config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\os_defines.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\cpu_defines.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\string.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\xlocale.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\string.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\math.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cmath:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\bits\cpp_type_traits.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\ext\type_traits.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\math.h:
+
+..\include\core/avr/pgmspace.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\inttypes.h:
+
+..\include\core/avr/interrupt.h:
+
+..\include\core/avr/io.h:
+
+..\include\core/binary.h:
+
+..\include\core/itoa.h:
+
+..\include\core/sam.h:
+
+..\include\core/samd.h:
+
+..\include\core/samd21/include/samd21.h:
+
+..\include\core/samd21/include/samd21g18a.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h:
+
+..\include\core/samd21/include/system_samd21.h:
+
+..\include\core/samd21/include/component/ac.h:
+
+..\include\core/samd21/include/component/adc.h:
+
+..\include\core/samd21/include/component/dac.h:
+
+..\include\core/samd21/include/component/dmac.h:
+
+..\include\core/samd21/include/component/dsu.h:
+
+..\include\core/samd21/include/component/eic.h:
+
+..\include\core/samd21/include/component/evsys.h:
+
+..\include\core/samd21/include/component/gclk.h:
+
+..\include\core/samd21/include/component/hmatrixb.h:
+
+..\include\core/samd21/include/component/i2s.h:
+
+..\include\core/samd21/include/component/mtb.h:
+
+..\include\core/samd21/include/component/nvmctrl.h:
+
+..\include\core/samd21/include/component/pac.h:
+
+..\include\core/samd21/include/component/pm.h:
+
+..\include\core/samd21/include/component/port.h:
+
+..\include\core/samd21/include/component/rtc.h:
+
+..\include\core/samd21/include/component/sercom.h:
+
+..\include\core/samd21/include/component/sysctrl.h:
+
+..\include\core/samd21/include/component/tc.h:
+
+..\include\core/samd21/include/component/tcc.h:
+
+..\include\core/samd21/include/component/usb.h:
+
+..\include\core/samd21/include/component/wdt.h:
+
+..\include\core/samd21/include/instance/ac.h:
+
+..\include\core/samd21/include/instance/adc.h:
+
+..\include\core/samd21/include/instance/dac.h:
+
+..\include\core/samd21/include/instance/dmac.h:
+
+..\include\core/samd21/include/instance/dsu.h:
+
+..\include\core/samd21/include/instance/eic.h:
+
+..\include\core/samd21/include/instance/evsys.h:
+
+..\include\core/samd21/include/instance/gclk.h:
+
+..\include\core/samd21/include/instance/sbmatrix.h:
+
+..\include\core/samd21/include/instance/i2s.h:
+
+..\include\core/samd21/include/instance/mtb.h:
+
+..\include\core/samd21/include/instance/nvmctrl.h:
+
+..\include\core/samd21/include/instance/pac0.h:
+
+..\include\core/samd21/include/instance/pac1.h:
+
+..\include\core/samd21/include/instance/pac2.h:
+
+..\include\core/samd21/include/instance/pm.h:
+
+..\include\core/samd21/include/instance/port.h:
+
+..\include\core/samd21/include/instance/rtc.h:
+
+..\include\core/samd21/include/instance/sercom0.h:
+
+..\include\core/samd21/include/instance/sercom1.h:
+
+..\include\core/samd21/include/instance/sercom2.h:
+
+..\include\core/samd21/include/instance/sercom3.h:
+
+..\include\core/samd21/include/instance/sercom4.h:
+
+..\include\core/samd21/include/instance/sercom5.h:
+
+..\include\core/samd21/include/instance/sysctrl.h:
+
+..\include\core/samd21/include/instance/tc3.h:
+
+..\include\core/samd21/include/instance/tc4.h:
+
+..\include\core/samd21/include/instance/tc5.h:
+
+..\include\core/samd21/include/instance/tcc0.h:
+
+..\include\core/samd21/include/instance/tcc1.h:
+
+..\include\core/samd21/include/instance/tcc2.h:
+
+..\include\core/samd21/include/instance/usb.h:
+
+..\include\core/samd21/include/instance/wdt.h:
+
+..\include\core/samd21/include/pio/samd21g18a.h:
+
+..\include\core/wiring_constants.h:
+
+..\include\core/WVariant.h:
+
+..\include\core/WCharacter.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\ctype.h:
+
+..\include\core/WString.h:
+
+..\include\core/avr/pgmspace.h:
+
+..\include\core/Tone.h:
+
+..\include\core/Arduino.h:
+
+..\include\core/WMath.h:
+
+..\include\core/HardwareSerial.h:
+
+..\include\core/Stream.h:
+
+..\include\core/Print.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
+
+..\include\core/Printable.h:
+
+..\include\core/pulse.h:
+
+..\include\core/delay.h:
+
+..\include\variants/variant.h:
+
+..\include\core/SERCOM.h:
+
+..\include\core/Uart.h:
+
+..\include\core/SERCOM.h:
+
+..\include\core/RingBuffer.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cstddef:
+
+..\include\core/wiring.h:
+
+..\include\core/wiring_digital.h:
+
+..\include\core/wiring_analog.h:
+
+..\include\core/wiring_shift.h:
+
+..\include\core/WInterrupts.h:
+
+..\include\core/USB/USBDesc.h:
+
+..\include\core/USB/USBCore.h:
+
+..\include\core/USB/USBAPI.h:
+
+..\include\core/Stream.h:
+
+..\include\core/RingBuffer.h:
+
+..\include\core/USB/USB_host.h:
+
+..\include\core/USB/samd21_host.h:
+
+..\include\core/USB/CDC.h:
+
+..\include\core/USB/USBDesc.h:
+
+..\include\core/USB/PluggableUSB.h:
+
+..\include\core/IPAddress.h:
diff --git a/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/IPAddress.o b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/IPAddress.o
new file mode 100644
index 0000000000000000000000000000000000000000..4568eea3d99420b36b73cbd9909c72ff3d5219cb
Binary files /dev/null and b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/IPAddress.o differ
diff --git a/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/PreprocessingAssembly/pulse_asm.d b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/PreprocessingAssembly/pulse_asm.d
new file mode 100644
index 0000000000000000000000000000000000000000..08cf523ad24ce097d7ca4666236cc378fcae6d67
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/PreprocessingAssembly/pulse_asm.d
@@ -0,0 +1,3 @@
+src/core/PreprocessingAssembly/pulse_asm.d \
+ src/core/PreprocessingAssembly/pulse_asm.o: \
+ ../src/core/PreprocessingAssembly/pulse_asm.S
diff --git a/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/PreprocessingAssembly/pulse_asm.o b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/PreprocessingAssembly/pulse_asm.o
new file mode 100644
index 0000000000000000000000000000000000000000..5db8ad729ced4064a8157c357bb164e5dbff2fe0
Binary files /dev/null and b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/PreprocessingAssembly/pulse_asm.o differ
diff --git a/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/Print.d b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/Print.d
new file mode 100644
index 0000000000000000000000000000000000000000..2fd3c89a918746b350f22c8b473e971fc429e523
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/Print.d
@@ -0,0 +1,451 @@
+src/core/Print.d src/core/Print.o: ../src/core/Print.cpp \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\math.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cmath \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\c++config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\os_defines.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\cpu_defines.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\bits\cpp_type_traits.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\ext\type_traits.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\math.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ ..\include\core/Arduino.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cstdlib \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\string.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\xlocale.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\string.h \
+ ..\include\core/avr/pgmspace.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\inttypes.h \
+ ..\include\core/avr/interrupt.h ..\include\core/avr/io.h \
+ ..\include\core/binary.h ..\include\core/itoa.h ..\include\core/sam.h \
+ ..\include\core/samd.h ..\include\core/samd21/include/samd21.h \
+ ..\include\core/samd21/include/samd21g18a.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h \
+ ..\include\core/samd21/include/system_samd21.h \
+ ..\include\core/samd21/include/component/ac.h \
+ ..\include\core/samd21/include/component/adc.h \
+ ..\include\core/samd21/include/component/dac.h \
+ ..\include\core/samd21/include/component/dmac.h \
+ ..\include\core/samd21/include/component/dsu.h \
+ ..\include\core/samd21/include/component/eic.h \
+ ..\include\core/samd21/include/component/evsys.h \
+ ..\include\core/samd21/include/component/gclk.h \
+ ..\include\core/samd21/include/component/hmatrixb.h \
+ ..\include\core/samd21/include/component/i2s.h \
+ ..\include\core/samd21/include/component/mtb.h \
+ ..\include\core/samd21/include/component/nvmctrl.h \
+ ..\include\core/samd21/include/component/pac.h \
+ ..\include\core/samd21/include/component/pm.h \
+ ..\include\core/samd21/include/component/port.h \
+ ..\include\core/samd21/include/component/rtc.h \
+ ..\include\core/samd21/include/component/sercom.h \
+ ..\include\core/samd21/include/component/sysctrl.h \
+ ..\include\core/samd21/include/component/tc.h \
+ ..\include\core/samd21/include/component/tcc.h \
+ ..\include\core/samd21/include/component/usb.h \
+ ..\include\core/samd21/include/component/wdt.h \
+ ..\include\core/samd21/include/instance/ac.h \
+ ..\include\core/samd21/include/instance/adc.h \
+ ..\include\core/samd21/include/instance/dac.h \
+ ..\include\core/samd21/include/instance/dmac.h \
+ ..\include\core/samd21/include/instance/dsu.h \
+ ..\include\core/samd21/include/instance/eic.h \
+ ..\include\core/samd21/include/instance/evsys.h \
+ ..\include\core/samd21/include/instance/gclk.h \
+ ..\include\core/samd21/include/instance/sbmatrix.h \
+ ..\include\core/samd21/include/instance/i2s.h \
+ ..\include\core/samd21/include/instance/mtb.h \
+ ..\include\core/samd21/include/instance/nvmctrl.h \
+ ..\include\core/samd21/include/instance/pac0.h \
+ ..\include\core/samd21/include/instance/pac1.h \
+ ..\include\core/samd21/include/instance/pac2.h \
+ ..\include\core/samd21/include/instance/pm.h \
+ ..\include\core/samd21/include/instance/port.h \
+ ..\include\core/samd21/include/instance/rtc.h \
+ ..\include\core/samd21/include/instance/sercom0.h \
+ ..\include\core/samd21/include/instance/sercom1.h \
+ ..\include\core/samd21/include/instance/sercom2.h \
+ ..\include\core/samd21/include/instance/sercom3.h \
+ ..\include\core/samd21/include/instance/sercom4.h \
+ ..\include\core/samd21/include/instance/sercom5.h \
+ ..\include\core/samd21/include/instance/sysctrl.h \
+ ..\include\core/samd21/include/instance/tc3.h \
+ ..\include\core/samd21/include/instance/tc4.h \
+ ..\include\core/samd21/include/instance/tc5.h \
+ ..\include\core/samd21/include/instance/tcc0.h \
+ ..\include\core/samd21/include/instance/tcc1.h \
+ ..\include\core/samd21/include/instance/tcc2.h \
+ ..\include\core/samd21/include/instance/usb.h \
+ ..\include\core/samd21/include/instance/wdt.h \
+ ..\include\core/samd21/include/pio/samd21g18a.h \
+ ..\include\core/wiring_constants.h ..\include\core/WVariant.h \
+ ..\include\core/WCharacter.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\ctype.h \
+ ..\include\core/WString.h ..\include\core/avr/pgmspace.h \
+ ..\include\core/Tone.h ..\include\core/Arduino.h ..\include\core/WMath.h \
+ ..\include\core/HardwareSerial.h ..\include\core/Stream.h \
+ ..\include\core/Print.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
+ ..\include\core/Printable.h ..\include\core/pulse.h \
+ ..\include\core/delay.h ..\include\variants/variant.h \
+ ..\include\core/SERCOM.h ..\include\core/Uart.h ..\include\core/SERCOM.h \
+ ..\include\core/RingBuffer.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cstddef \
+ ..\include\core/wiring.h ..\include\core/wiring_digital.h \
+ ..\include\core/wiring_analog.h ..\include\core/wiring_shift.h \
+ ..\include\core/WInterrupts.h ..\include\core/USB/USBDesc.h \
+ ..\include\core/USB/USBCore.h ..\include\core/USB/USBAPI.h \
+ ..\include\core/Stream.h ..\include\core/RingBuffer.h \
+ ..\include\core/USB/USB_host.h ..\include\core/USB/samd21_host.h \
+ ..\include\core/USB/CDC.h ..\include\core/USB/USBDesc.h \
+ ..\include\core/USB/PluggableUSB.h ..\include\core/Print.h
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\math.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cmath:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\c++config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\os_defines.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\cpu_defines.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\bits\cpp_type_traits.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\ext\type_traits.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\math.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+..\include\core/Arduino.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cstdlib:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\string.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\xlocale.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\string.h:
+
+..\include\core/avr/pgmspace.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\inttypes.h:
+
+..\include\core/avr/interrupt.h:
+
+..\include\core/avr/io.h:
+
+..\include\core/binary.h:
+
+..\include\core/itoa.h:
+
+..\include\core/sam.h:
+
+..\include\core/samd.h:
+
+..\include\core/samd21/include/samd21.h:
+
+..\include\core/samd21/include/samd21g18a.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h:
+
+..\include\core/samd21/include/system_samd21.h:
+
+..\include\core/samd21/include/component/ac.h:
+
+..\include\core/samd21/include/component/adc.h:
+
+..\include\core/samd21/include/component/dac.h:
+
+..\include\core/samd21/include/component/dmac.h:
+
+..\include\core/samd21/include/component/dsu.h:
+
+..\include\core/samd21/include/component/eic.h:
+
+..\include\core/samd21/include/component/evsys.h:
+
+..\include\core/samd21/include/component/gclk.h:
+
+..\include\core/samd21/include/component/hmatrixb.h:
+
+..\include\core/samd21/include/component/i2s.h:
+
+..\include\core/samd21/include/component/mtb.h:
+
+..\include\core/samd21/include/component/nvmctrl.h:
+
+..\include\core/samd21/include/component/pac.h:
+
+..\include\core/samd21/include/component/pm.h:
+
+..\include\core/samd21/include/component/port.h:
+
+..\include\core/samd21/include/component/rtc.h:
+
+..\include\core/samd21/include/component/sercom.h:
+
+..\include\core/samd21/include/component/sysctrl.h:
+
+..\include\core/samd21/include/component/tc.h:
+
+..\include\core/samd21/include/component/tcc.h:
+
+..\include\core/samd21/include/component/usb.h:
+
+..\include\core/samd21/include/component/wdt.h:
+
+..\include\core/samd21/include/instance/ac.h:
+
+..\include\core/samd21/include/instance/adc.h:
+
+..\include\core/samd21/include/instance/dac.h:
+
+..\include\core/samd21/include/instance/dmac.h:
+
+..\include\core/samd21/include/instance/dsu.h:
+
+..\include\core/samd21/include/instance/eic.h:
+
+..\include\core/samd21/include/instance/evsys.h:
+
+..\include\core/samd21/include/instance/gclk.h:
+
+..\include\core/samd21/include/instance/sbmatrix.h:
+
+..\include\core/samd21/include/instance/i2s.h:
+
+..\include\core/samd21/include/instance/mtb.h:
+
+..\include\core/samd21/include/instance/nvmctrl.h:
+
+..\include\core/samd21/include/instance/pac0.h:
+
+..\include\core/samd21/include/instance/pac1.h:
+
+..\include\core/samd21/include/instance/pac2.h:
+
+..\include\core/samd21/include/instance/pm.h:
+
+..\include\core/samd21/include/instance/port.h:
+
+..\include\core/samd21/include/instance/rtc.h:
+
+..\include\core/samd21/include/instance/sercom0.h:
+
+..\include\core/samd21/include/instance/sercom1.h:
+
+..\include\core/samd21/include/instance/sercom2.h:
+
+..\include\core/samd21/include/instance/sercom3.h:
+
+..\include\core/samd21/include/instance/sercom4.h:
+
+..\include\core/samd21/include/instance/sercom5.h:
+
+..\include\core/samd21/include/instance/sysctrl.h:
+
+..\include\core/samd21/include/instance/tc3.h:
+
+..\include\core/samd21/include/instance/tc4.h:
+
+..\include\core/samd21/include/instance/tc5.h:
+
+..\include\core/samd21/include/instance/tcc0.h:
+
+..\include\core/samd21/include/instance/tcc1.h:
+
+..\include\core/samd21/include/instance/tcc2.h:
+
+..\include\core/samd21/include/instance/usb.h:
+
+..\include\core/samd21/include/instance/wdt.h:
+
+..\include\core/samd21/include/pio/samd21g18a.h:
+
+..\include\core/wiring_constants.h:
+
+..\include\core/WVariant.h:
+
+..\include\core/WCharacter.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\ctype.h:
+
+..\include\core/WString.h:
+
+..\include\core/avr/pgmspace.h:
+
+..\include\core/Tone.h:
+
+..\include\core/Arduino.h:
+
+..\include\core/WMath.h:
+
+..\include\core/HardwareSerial.h:
+
+..\include\core/Stream.h:
+
+..\include\core/Print.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
+
+..\include\core/Printable.h:
+
+..\include\core/pulse.h:
+
+..\include\core/delay.h:
+
+..\include\variants/variant.h:
+
+..\include\core/SERCOM.h:
+
+..\include\core/Uart.h:
+
+..\include\core/SERCOM.h:
+
+..\include\core/RingBuffer.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cstddef:
+
+..\include\core/wiring.h:
+
+..\include\core/wiring_digital.h:
+
+..\include\core/wiring_analog.h:
+
+..\include\core/wiring_shift.h:
+
+..\include\core/WInterrupts.h:
+
+..\include\core/USB/USBDesc.h:
+
+..\include\core/USB/USBCore.h:
+
+..\include\core/USB/USBAPI.h:
+
+..\include\core/Stream.h:
+
+..\include\core/RingBuffer.h:
+
+..\include\core/USB/USB_host.h:
+
+..\include\core/USB/samd21_host.h:
+
+..\include\core/USB/CDC.h:
+
+..\include\core/USB/USBDesc.h:
+
+..\include\core/USB/PluggableUSB.h:
+
+..\include\core/Print.h:
diff --git a/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/Print.o b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/Print.o
new file mode 100644
index 0000000000000000000000000000000000000000..b7805fb31e178b1d050489bb07dd634f5555764e
Binary files /dev/null and b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/Print.o differ
diff --git a/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/Reset.d b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/Reset.d
new file mode 100644
index 0000000000000000000000000000000000000000..53f9e7274b24eacc6aeec6b783b9834259bb9486
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/Reset.d
@@ -0,0 +1,451 @@
+src/core/Reset.d src/core/Reset.o: ../src/core/Reset.cpp \
+ ..\include\core/Arduino.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cstdlib \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\c++config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\os_defines.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\cpu_defines.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\string.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\xlocale.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\string.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\math.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cmath \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\bits\cpp_type_traits.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\ext\type_traits.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\math.h \
+ ..\include\core/avr/pgmspace.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\inttypes.h \
+ ..\include\core/avr/interrupt.h ..\include\core/avr/io.h \
+ ..\include\core/binary.h ..\include\core/itoa.h ..\include\core/sam.h \
+ ..\include\core/samd.h ..\include\core/samd21/include/samd21.h \
+ ..\include\core/samd21/include/samd21g18a.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h \
+ ..\include\core/samd21/include/system_samd21.h \
+ ..\include\core/samd21/include/component/ac.h \
+ ..\include\core/samd21/include/component/adc.h \
+ ..\include\core/samd21/include/component/dac.h \
+ ..\include\core/samd21/include/component/dmac.h \
+ ..\include\core/samd21/include/component/dsu.h \
+ ..\include\core/samd21/include/component/eic.h \
+ ..\include\core/samd21/include/component/evsys.h \
+ ..\include\core/samd21/include/component/gclk.h \
+ ..\include\core/samd21/include/component/hmatrixb.h \
+ ..\include\core/samd21/include/component/i2s.h \
+ ..\include\core/samd21/include/component/mtb.h \
+ ..\include\core/samd21/include/component/nvmctrl.h \
+ ..\include\core/samd21/include/component/pac.h \
+ ..\include\core/samd21/include/component/pm.h \
+ ..\include\core/samd21/include/component/port.h \
+ ..\include\core/samd21/include/component/rtc.h \
+ ..\include\core/samd21/include/component/sercom.h \
+ ..\include\core/samd21/include/component/sysctrl.h \
+ ..\include\core/samd21/include/component/tc.h \
+ ..\include\core/samd21/include/component/tcc.h \
+ ..\include\core/samd21/include/component/usb.h \
+ ..\include\core/samd21/include/component/wdt.h \
+ ..\include\core/samd21/include/instance/ac.h \
+ ..\include\core/samd21/include/instance/adc.h \
+ ..\include\core/samd21/include/instance/dac.h \
+ ..\include\core/samd21/include/instance/dmac.h \
+ ..\include\core/samd21/include/instance/dsu.h \
+ ..\include\core/samd21/include/instance/eic.h \
+ ..\include\core/samd21/include/instance/evsys.h \
+ ..\include\core/samd21/include/instance/gclk.h \
+ ..\include\core/samd21/include/instance/sbmatrix.h \
+ ..\include\core/samd21/include/instance/i2s.h \
+ ..\include\core/samd21/include/instance/mtb.h \
+ ..\include\core/samd21/include/instance/nvmctrl.h \
+ ..\include\core/samd21/include/instance/pac0.h \
+ ..\include\core/samd21/include/instance/pac1.h \
+ ..\include\core/samd21/include/instance/pac2.h \
+ ..\include\core/samd21/include/instance/pm.h \
+ ..\include\core/samd21/include/instance/port.h \
+ ..\include\core/samd21/include/instance/rtc.h \
+ ..\include\core/samd21/include/instance/sercom0.h \
+ ..\include\core/samd21/include/instance/sercom1.h \
+ ..\include\core/samd21/include/instance/sercom2.h \
+ ..\include\core/samd21/include/instance/sercom3.h \
+ ..\include\core/samd21/include/instance/sercom4.h \
+ ..\include\core/samd21/include/instance/sercom5.h \
+ ..\include\core/samd21/include/instance/sysctrl.h \
+ ..\include\core/samd21/include/instance/tc3.h \
+ ..\include\core/samd21/include/instance/tc4.h \
+ ..\include\core/samd21/include/instance/tc5.h \
+ ..\include\core/samd21/include/instance/tcc0.h \
+ ..\include\core/samd21/include/instance/tcc1.h \
+ ..\include\core/samd21/include/instance/tcc2.h \
+ ..\include\core/samd21/include/instance/usb.h \
+ ..\include\core/samd21/include/instance/wdt.h \
+ ..\include\core/samd21/include/pio/samd21g18a.h \
+ ..\include\core/wiring_constants.h ..\include\core/WVariant.h \
+ ..\include\core/WCharacter.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\ctype.h \
+ ..\include\core/WString.h ..\include\core/avr/pgmspace.h \
+ ..\include\core/Tone.h ..\include\core/Arduino.h ..\include\core/WMath.h \
+ ..\include\core/HardwareSerial.h ..\include\core/Stream.h \
+ ..\include\core/Print.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
+ ..\include\core/Printable.h ..\include\core/pulse.h \
+ ..\include\core/delay.h ..\include\variants/variant.h \
+ ..\include\core/SERCOM.h ..\include\core/Uart.h ..\include\core/SERCOM.h \
+ ..\include\core/RingBuffer.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cstddef \
+ ..\include\core/wiring.h ..\include\core/wiring_digital.h \
+ ..\include\core/wiring_analog.h ..\include\core/wiring_shift.h \
+ ..\include\core/WInterrupts.h ..\include\core/USB/USBDesc.h \
+ ..\include\core/USB/USBCore.h ..\include\core/USB/USBAPI.h \
+ ..\include\core/Stream.h ..\include\core/RingBuffer.h \
+ ..\include\core/USB/USB_host.h ..\include\core/USB/samd21_host.h \
+ ..\include\core/USB/CDC.h ..\include\core/USB/USBDesc.h \
+ ..\include\core/USB/PluggableUSB.h ..\include\core/Reset.h
+
+..\include\core/Arduino.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cstdlib:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\c++config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\os_defines.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\cpu_defines.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\string.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\xlocale.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\string.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\math.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cmath:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\bits\cpp_type_traits.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\ext\type_traits.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\math.h:
+
+..\include\core/avr/pgmspace.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\inttypes.h:
+
+..\include\core/avr/interrupt.h:
+
+..\include\core/avr/io.h:
+
+..\include\core/binary.h:
+
+..\include\core/itoa.h:
+
+..\include\core/sam.h:
+
+..\include\core/samd.h:
+
+..\include\core/samd21/include/samd21.h:
+
+..\include\core/samd21/include/samd21g18a.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h:
+
+..\include\core/samd21/include/system_samd21.h:
+
+..\include\core/samd21/include/component/ac.h:
+
+..\include\core/samd21/include/component/adc.h:
+
+..\include\core/samd21/include/component/dac.h:
+
+..\include\core/samd21/include/component/dmac.h:
+
+..\include\core/samd21/include/component/dsu.h:
+
+..\include\core/samd21/include/component/eic.h:
+
+..\include\core/samd21/include/component/evsys.h:
+
+..\include\core/samd21/include/component/gclk.h:
+
+..\include\core/samd21/include/component/hmatrixb.h:
+
+..\include\core/samd21/include/component/i2s.h:
+
+..\include\core/samd21/include/component/mtb.h:
+
+..\include\core/samd21/include/component/nvmctrl.h:
+
+..\include\core/samd21/include/component/pac.h:
+
+..\include\core/samd21/include/component/pm.h:
+
+..\include\core/samd21/include/component/port.h:
+
+..\include\core/samd21/include/component/rtc.h:
+
+..\include\core/samd21/include/component/sercom.h:
+
+..\include\core/samd21/include/component/sysctrl.h:
+
+..\include\core/samd21/include/component/tc.h:
+
+..\include\core/samd21/include/component/tcc.h:
+
+..\include\core/samd21/include/component/usb.h:
+
+..\include\core/samd21/include/component/wdt.h:
+
+..\include\core/samd21/include/instance/ac.h:
+
+..\include\core/samd21/include/instance/adc.h:
+
+..\include\core/samd21/include/instance/dac.h:
+
+..\include\core/samd21/include/instance/dmac.h:
+
+..\include\core/samd21/include/instance/dsu.h:
+
+..\include\core/samd21/include/instance/eic.h:
+
+..\include\core/samd21/include/instance/evsys.h:
+
+..\include\core/samd21/include/instance/gclk.h:
+
+..\include\core/samd21/include/instance/sbmatrix.h:
+
+..\include\core/samd21/include/instance/i2s.h:
+
+..\include\core/samd21/include/instance/mtb.h:
+
+..\include\core/samd21/include/instance/nvmctrl.h:
+
+..\include\core/samd21/include/instance/pac0.h:
+
+..\include\core/samd21/include/instance/pac1.h:
+
+..\include\core/samd21/include/instance/pac2.h:
+
+..\include\core/samd21/include/instance/pm.h:
+
+..\include\core/samd21/include/instance/port.h:
+
+..\include\core/samd21/include/instance/rtc.h:
+
+..\include\core/samd21/include/instance/sercom0.h:
+
+..\include\core/samd21/include/instance/sercom1.h:
+
+..\include\core/samd21/include/instance/sercom2.h:
+
+..\include\core/samd21/include/instance/sercom3.h:
+
+..\include\core/samd21/include/instance/sercom4.h:
+
+..\include\core/samd21/include/instance/sercom5.h:
+
+..\include\core/samd21/include/instance/sysctrl.h:
+
+..\include\core/samd21/include/instance/tc3.h:
+
+..\include\core/samd21/include/instance/tc4.h:
+
+..\include\core/samd21/include/instance/tc5.h:
+
+..\include\core/samd21/include/instance/tcc0.h:
+
+..\include\core/samd21/include/instance/tcc1.h:
+
+..\include\core/samd21/include/instance/tcc2.h:
+
+..\include\core/samd21/include/instance/usb.h:
+
+..\include\core/samd21/include/instance/wdt.h:
+
+..\include\core/samd21/include/pio/samd21g18a.h:
+
+..\include\core/wiring_constants.h:
+
+..\include\core/WVariant.h:
+
+..\include\core/WCharacter.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\ctype.h:
+
+..\include\core/WString.h:
+
+..\include\core/avr/pgmspace.h:
+
+..\include\core/Tone.h:
+
+..\include\core/Arduino.h:
+
+..\include\core/WMath.h:
+
+..\include\core/HardwareSerial.h:
+
+..\include\core/Stream.h:
+
+..\include\core/Print.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
+
+..\include\core/Printable.h:
+
+..\include\core/pulse.h:
+
+..\include\core/delay.h:
+
+..\include\variants/variant.h:
+
+..\include\core/SERCOM.h:
+
+..\include\core/Uart.h:
+
+..\include\core/SERCOM.h:
+
+..\include\core/RingBuffer.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cstddef:
+
+..\include\core/wiring.h:
+
+..\include\core/wiring_digital.h:
+
+..\include\core/wiring_analog.h:
+
+..\include\core/wiring_shift.h:
+
+..\include\core/WInterrupts.h:
+
+..\include\core/USB/USBDesc.h:
+
+..\include\core/USB/USBCore.h:
+
+..\include\core/USB/USBAPI.h:
+
+..\include\core/Stream.h:
+
+..\include\core/RingBuffer.h:
+
+..\include\core/USB/USB_host.h:
+
+..\include\core/USB/samd21_host.h:
+
+..\include\core/USB/CDC.h:
+
+..\include\core/USB/USBDesc.h:
+
+..\include\core/USB/PluggableUSB.h:
+
+..\include\core/Reset.h:
diff --git a/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/Reset.o b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/Reset.o
new file mode 100644
index 0000000000000000000000000000000000000000..4e6f475e1153704146eeb341cb602ad6826308fa
Binary files /dev/null and b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/Reset.o differ
diff --git a/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/SERCOM.d b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/SERCOM.d
new file mode 100644
index 0000000000000000000000000000000000000000..df351013950fd3591fdf53b7318e397369d65f91
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/SERCOM.d
@@ -0,0 +1,449 @@
+src/core/SERCOM.d src/core/SERCOM.o: ../src/core/SERCOM.cpp \
+ ..\include\core/Arduino.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cstdlib \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\c++config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\os_defines.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\cpu_defines.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\string.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\xlocale.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\string.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\math.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cmath \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\bits\cpp_type_traits.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\ext\type_traits.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\math.h \
+ ..\include\core/avr/pgmspace.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\inttypes.h \
+ ..\include\core/avr/interrupt.h ..\include\core/avr/io.h \
+ ..\include\core/binary.h ..\include\core/itoa.h ..\include\core/sam.h \
+ ..\include\core/samd.h ..\include\core/samd21/include/samd21.h \
+ ..\include\core/samd21/include/samd21g18a.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h \
+ ..\include\core/samd21/include/system_samd21.h \
+ ..\include\core/samd21/include/component/ac.h \
+ ..\include\core/samd21/include/component/adc.h \
+ ..\include\core/samd21/include/component/dac.h \
+ ..\include\core/samd21/include/component/dmac.h \
+ ..\include\core/samd21/include/component/dsu.h \
+ ..\include\core/samd21/include/component/eic.h \
+ ..\include\core/samd21/include/component/evsys.h \
+ ..\include\core/samd21/include/component/gclk.h \
+ ..\include\core/samd21/include/component/hmatrixb.h \
+ ..\include\core/samd21/include/component/i2s.h \
+ ..\include\core/samd21/include/component/mtb.h \
+ ..\include\core/samd21/include/component/nvmctrl.h \
+ ..\include\core/samd21/include/component/pac.h \
+ ..\include\core/samd21/include/component/pm.h \
+ ..\include\core/samd21/include/component/port.h \
+ ..\include\core/samd21/include/component/rtc.h \
+ ..\include\core/samd21/include/component/sercom.h \
+ ..\include\core/samd21/include/component/sysctrl.h \
+ ..\include\core/samd21/include/component/tc.h \
+ ..\include\core/samd21/include/component/tcc.h \
+ ..\include\core/samd21/include/component/usb.h \
+ ..\include\core/samd21/include/component/wdt.h \
+ ..\include\core/samd21/include/instance/ac.h \
+ ..\include\core/samd21/include/instance/adc.h \
+ ..\include\core/samd21/include/instance/dac.h \
+ ..\include\core/samd21/include/instance/dmac.h \
+ ..\include\core/samd21/include/instance/dsu.h \
+ ..\include\core/samd21/include/instance/eic.h \
+ ..\include\core/samd21/include/instance/evsys.h \
+ ..\include\core/samd21/include/instance/gclk.h \
+ ..\include\core/samd21/include/instance/sbmatrix.h \
+ ..\include\core/samd21/include/instance/i2s.h \
+ ..\include\core/samd21/include/instance/mtb.h \
+ ..\include\core/samd21/include/instance/nvmctrl.h \
+ ..\include\core/samd21/include/instance/pac0.h \
+ ..\include\core/samd21/include/instance/pac1.h \
+ ..\include\core/samd21/include/instance/pac2.h \
+ ..\include\core/samd21/include/instance/pm.h \
+ ..\include\core/samd21/include/instance/port.h \
+ ..\include\core/samd21/include/instance/rtc.h \
+ ..\include\core/samd21/include/instance/sercom0.h \
+ ..\include\core/samd21/include/instance/sercom1.h \
+ ..\include\core/samd21/include/instance/sercom2.h \
+ ..\include\core/samd21/include/instance/sercom3.h \
+ ..\include\core/samd21/include/instance/sercom4.h \
+ ..\include\core/samd21/include/instance/sercom5.h \
+ ..\include\core/samd21/include/instance/sysctrl.h \
+ ..\include\core/samd21/include/instance/tc3.h \
+ ..\include\core/samd21/include/instance/tc4.h \
+ ..\include\core/samd21/include/instance/tc5.h \
+ ..\include\core/samd21/include/instance/tcc0.h \
+ ..\include\core/samd21/include/instance/tcc1.h \
+ ..\include\core/samd21/include/instance/tcc2.h \
+ ..\include\core/samd21/include/instance/usb.h \
+ ..\include\core/samd21/include/instance/wdt.h \
+ ..\include\core/samd21/include/pio/samd21g18a.h \
+ ..\include\core/wiring_constants.h ..\include\core/WVariant.h \
+ ..\include\core/WCharacter.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\ctype.h \
+ ..\include\core/WString.h ..\include\core/avr/pgmspace.h \
+ ..\include\core/Tone.h ..\include\core/Arduino.h ..\include\core/WMath.h \
+ ..\include\core/HardwareSerial.h ..\include\core/Stream.h \
+ ..\include\core/Print.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
+ ..\include\core/Printable.h ..\include\core/pulse.h \
+ ..\include\core/delay.h ..\include\variants/variant.h \
+ ..\include\core/SERCOM.h ..\include\core/Uart.h ..\include\core/SERCOM.h \
+ ..\include\core/RingBuffer.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cstddef \
+ ..\include\core/wiring.h ..\include\core/wiring_digital.h \
+ ..\include\core/wiring_analog.h ..\include\core/wiring_shift.h \
+ ..\include\core/WInterrupts.h ..\include\core/USB/USBDesc.h \
+ ..\include\core/USB/USBCore.h ..\include\core/USB/USBAPI.h \
+ ..\include\core/Stream.h ..\include\core/RingBuffer.h \
+ ..\include\core/USB/USB_host.h ..\include\core/USB/samd21_host.h \
+ ..\include\core/USB/CDC.h ..\include\core/USB/USBDesc.h \
+ ..\include\core/USB/PluggableUSB.h
+
+..\include\core/Arduino.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cstdlib:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\c++config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\os_defines.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\cpu_defines.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\string.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\xlocale.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\string.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\math.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cmath:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\bits\cpp_type_traits.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\ext\type_traits.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\math.h:
+
+..\include\core/avr/pgmspace.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\inttypes.h:
+
+..\include\core/avr/interrupt.h:
+
+..\include\core/avr/io.h:
+
+..\include\core/binary.h:
+
+..\include\core/itoa.h:
+
+..\include\core/sam.h:
+
+..\include\core/samd.h:
+
+..\include\core/samd21/include/samd21.h:
+
+..\include\core/samd21/include/samd21g18a.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h:
+
+..\include\core/samd21/include/system_samd21.h:
+
+..\include\core/samd21/include/component/ac.h:
+
+..\include\core/samd21/include/component/adc.h:
+
+..\include\core/samd21/include/component/dac.h:
+
+..\include\core/samd21/include/component/dmac.h:
+
+..\include\core/samd21/include/component/dsu.h:
+
+..\include\core/samd21/include/component/eic.h:
+
+..\include\core/samd21/include/component/evsys.h:
+
+..\include\core/samd21/include/component/gclk.h:
+
+..\include\core/samd21/include/component/hmatrixb.h:
+
+..\include\core/samd21/include/component/i2s.h:
+
+..\include\core/samd21/include/component/mtb.h:
+
+..\include\core/samd21/include/component/nvmctrl.h:
+
+..\include\core/samd21/include/component/pac.h:
+
+..\include\core/samd21/include/component/pm.h:
+
+..\include\core/samd21/include/component/port.h:
+
+..\include\core/samd21/include/component/rtc.h:
+
+..\include\core/samd21/include/component/sercom.h:
+
+..\include\core/samd21/include/component/sysctrl.h:
+
+..\include\core/samd21/include/component/tc.h:
+
+..\include\core/samd21/include/component/tcc.h:
+
+..\include\core/samd21/include/component/usb.h:
+
+..\include\core/samd21/include/component/wdt.h:
+
+..\include\core/samd21/include/instance/ac.h:
+
+..\include\core/samd21/include/instance/adc.h:
+
+..\include\core/samd21/include/instance/dac.h:
+
+..\include\core/samd21/include/instance/dmac.h:
+
+..\include\core/samd21/include/instance/dsu.h:
+
+..\include\core/samd21/include/instance/eic.h:
+
+..\include\core/samd21/include/instance/evsys.h:
+
+..\include\core/samd21/include/instance/gclk.h:
+
+..\include\core/samd21/include/instance/sbmatrix.h:
+
+..\include\core/samd21/include/instance/i2s.h:
+
+..\include\core/samd21/include/instance/mtb.h:
+
+..\include\core/samd21/include/instance/nvmctrl.h:
+
+..\include\core/samd21/include/instance/pac0.h:
+
+..\include\core/samd21/include/instance/pac1.h:
+
+..\include\core/samd21/include/instance/pac2.h:
+
+..\include\core/samd21/include/instance/pm.h:
+
+..\include\core/samd21/include/instance/port.h:
+
+..\include\core/samd21/include/instance/rtc.h:
+
+..\include\core/samd21/include/instance/sercom0.h:
+
+..\include\core/samd21/include/instance/sercom1.h:
+
+..\include\core/samd21/include/instance/sercom2.h:
+
+..\include\core/samd21/include/instance/sercom3.h:
+
+..\include\core/samd21/include/instance/sercom4.h:
+
+..\include\core/samd21/include/instance/sercom5.h:
+
+..\include\core/samd21/include/instance/sysctrl.h:
+
+..\include\core/samd21/include/instance/tc3.h:
+
+..\include\core/samd21/include/instance/tc4.h:
+
+..\include\core/samd21/include/instance/tc5.h:
+
+..\include\core/samd21/include/instance/tcc0.h:
+
+..\include\core/samd21/include/instance/tcc1.h:
+
+..\include\core/samd21/include/instance/tcc2.h:
+
+..\include\core/samd21/include/instance/usb.h:
+
+..\include\core/samd21/include/instance/wdt.h:
+
+..\include\core/samd21/include/pio/samd21g18a.h:
+
+..\include\core/wiring_constants.h:
+
+..\include\core/WVariant.h:
+
+..\include\core/WCharacter.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\ctype.h:
+
+..\include\core/WString.h:
+
+..\include\core/avr/pgmspace.h:
+
+..\include\core/Tone.h:
+
+..\include\core/Arduino.h:
+
+..\include\core/WMath.h:
+
+..\include\core/HardwareSerial.h:
+
+..\include\core/Stream.h:
+
+..\include\core/Print.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
+
+..\include\core/Printable.h:
+
+..\include\core/pulse.h:
+
+..\include\core/delay.h:
+
+..\include\variants/variant.h:
+
+..\include\core/SERCOM.h:
+
+..\include\core/Uart.h:
+
+..\include\core/SERCOM.h:
+
+..\include\core/RingBuffer.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cstddef:
+
+..\include\core/wiring.h:
+
+..\include\core/wiring_digital.h:
+
+..\include\core/wiring_analog.h:
+
+..\include\core/wiring_shift.h:
+
+..\include\core/WInterrupts.h:
+
+..\include\core/USB/USBDesc.h:
+
+..\include\core/USB/USBCore.h:
+
+..\include\core/USB/USBAPI.h:
+
+..\include\core/Stream.h:
+
+..\include\core/RingBuffer.h:
+
+..\include\core/USB/USB_host.h:
+
+..\include\core/USB/samd21_host.h:
+
+..\include\core/USB/CDC.h:
+
+..\include\core/USB/USBDesc.h:
+
+..\include\core/USB/PluggableUSB.h:
diff --git a/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/SERCOM.o b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/SERCOM.o
new file mode 100644
index 0000000000000000000000000000000000000000..e43ad5e95f7936eedd185bd34a30e5170a28800c
Binary files /dev/null and b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/SERCOM.o differ
diff --git a/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/Stream.d b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/Stream.d
new file mode 100644
index 0000000000000000000000000000000000000000..f42072cb7babc4335b2863fa3f3958e06bf4b1f6
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/Stream.d
@@ -0,0 +1,449 @@
+src/core/Stream.d src/core/Stream.o: ../src/core/Stream.cpp \
+ ..\include\core/Arduino.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cstdlib \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\c++config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\os_defines.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\cpu_defines.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\string.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\xlocale.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\string.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\math.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cmath \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\bits\cpp_type_traits.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\ext\type_traits.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\math.h \
+ ..\include\core/avr/pgmspace.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\inttypes.h \
+ ..\include\core/avr/interrupt.h ..\include\core/avr/io.h \
+ ..\include\core/binary.h ..\include\core/itoa.h ..\include\core/sam.h \
+ ..\include\core/samd.h ..\include\core/samd21/include/samd21.h \
+ ..\include\core/samd21/include/samd21g18a.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h \
+ ..\include\core/samd21/include/system_samd21.h \
+ ..\include\core/samd21/include/component/ac.h \
+ ..\include\core/samd21/include/component/adc.h \
+ ..\include\core/samd21/include/component/dac.h \
+ ..\include\core/samd21/include/component/dmac.h \
+ ..\include\core/samd21/include/component/dsu.h \
+ ..\include\core/samd21/include/component/eic.h \
+ ..\include\core/samd21/include/component/evsys.h \
+ ..\include\core/samd21/include/component/gclk.h \
+ ..\include\core/samd21/include/component/hmatrixb.h \
+ ..\include\core/samd21/include/component/i2s.h \
+ ..\include\core/samd21/include/component/mtb.h \
+ ..\include\core/samd21/include/component/nvmctrl.h \
+ ..\include\core/samd21/include/component/pac.h \
+ ..\include\core/samd21/include/component/pm.h \
+ ..\include\core/samd21/include/component/port.h \
+ ..\include\core/samd21/include/component/rtc.h \
+ ..\include\core/samd21/include/component/sercom.h \
+ ..\include\core/samd21/include/component/sysctrl.h \
+ ..\include\core/samd21/include/component/tc.h \
+ ..\include\core/samd21/include/component/tcc.h \
+ ..\include\core/samd21/include/component/usb.h \
+ ..\include\core/samd21/include/component/wdt.h \
+ ..\include\core/samd21/include/instance/ac.h \
+ ..\include\core/samd21/include/instance/adc.h \
+ ..\include\core/samd21/include/instance/dac.h \
+ ..\include\core/samd21/include/instance/dmac.h \
+ ..\include\core/samd21/include/instance/dsu.h \
+ ..\include\core/samd21/include/instance/eic.h \
+ ..\include\core/samd21/include/instance/evsys.h \
+ ..\include\core/samd21/include/instance/gclk.h \
+ ..\include\core/samd21/include/instance/sbmatrix.h \
+ ..\include\core/samd21/include/instance/i2s.h \
+ ..\include\core/samd21/include/instance/mtb.h \
+ ..\include\core/samd21/include/instance/nvmctrl.h \
+ ..\include\core/samd21/include/instance/pac0.h \
+ ..\include\core/samd21/include/instance/pac1.h \
+ ..\include\core/samd21/include/instance/pac2.h \
+ ..\include\core/samd21/include/instance/pm.h \
+ ..\include\core/samd21/include/instance/port.h \
+ ..\include\core/samd21/include/instance/rtc.h \
+ ..\include\core/samd21/include/instance/sercom0.h \
+ ..\include\core/samd21/include/instance/sercom1.h \
+ ..\include\core/samd21/include/instance/sercom2.h \
+ ..\include\core/samd21/include/instance/sercom3.h \
+ ..\include\core/samd21/include/instance/sercom4.h \
+ ..\include\core/samd21/include/instance/sercom5.h \
+ ..\include\core/samd21/include/instance/sysctrl.h \
+ ..\include\core/samd21/include/instance/tc3.h \
+ ..\include\core/samd21/include/instance/tc4.h \
+ ..\include\core/samd21/include/instance/tc5.h \
+ ..\include\core/samd21/include/instance/tcc0.h \
+ ..\include\core/samd21/include/instance/tcc1.h \
+ ..\include\core/samd21/include/instance/tcc2.h \
+ ..\include\core/samd21/include/instance/usb.h \
+ ..\include\core/samd21/include/instance/wdt.h \
+ ..\include\core/samd21/include/pio/samd21g18a.h \
+ ..\include\core/wiring_constants.h ..\include\core/WVariant.h \
+ ..\include\core/WCharacter.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\ctype.h \
+ ..\include\core/WString.h ..\include\core/avr/pgmspace.h \
+ ..\include\core/Tone.h ..\include\core/Arduino.h ..\include\core/WMath.h \
+ ..\include\core/HardwareSerial.h ..\include\core/Stream.h \
+ ..\include\core/Print.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
+ ..\include\core/Printable.h ..\include\core/pulse.h \
+ ..\include\core/delay.h ..\include\variants/variant.h \
+ ..\include\core/SERCOM.h ..\include\core/Uart.h ..\include\core/SERCOM.h \
+ ..\include\core/RingBuffer.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cstddef \
+ ..\include\core/wiring.h ..\include\core/wiring_digital.h \
+ ..\include\core/wiring_analog.h ..\include\core/wiring_shift.h \
+ ..\include\core/WInterrupts.h ..\include\core/USB/USBDesc.h \
+ ..\include\core/USB/USBCore.h ..\include\core/USB/USBAPI.h \
+ ..\include\core/Stream.h ..\include\core/RingBuffer.h \
+ ..\include\core/USB/USB_host.h ..\include\core/USB/samd21_host.h \
+ ..\include\core/USB/CDC.h ..\include\core/USB/USBDesc.h \
+ ..\include\core/USB/PluggableUSB.h
+
+..\include\core/Arduino.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cstdlib:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\c++config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\os_defines.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\cpu_defines.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\string.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\xlocale.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\string.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\math.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cmath:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\bits\cpp_type_traits.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\ext\type_traits.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\math.h:
+
+..\include\core/avr/pgmspace.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\inttypes.h:
+
+..\include\core/avr/interrupt.h:
+
+..\include\core/avr/io.h:
+
+..\include\core/binary.h:
+
+..\include\core/itoa.h:
+
+..\include\core/sam.h:
+
+..\include\core/samd.h:
+
+..\include\core/samd21/include/samd21.h:
+
+..\include\core/samd21/include/samd21g18a.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h:
+
+..\include\core/samd21/include/system_samd21.h:
+
+..\include\core/samd21/include/component/ac.h:
+
+..\include\core/samd21/include/component/adc.h:
+
+..\include\core/samd21/include/component/dac.h:
+
+..\include\core/samd21/include/component/dmac.h:
+
+..\include\core/samd21/include/component/dsu.h:
+
+..\include\core/samd21/include/component/eic.h:
+
+..\include\core/samd21/include/component/evsys.h:
+
+..\include\core/samd21/include/component/gclk.h:
+
+..\include\core/samd21/include/component/hmatrixb.h:
+
+..\include\core/samd21/include/component/i2s.h:
+
+..\include\core/samd21/include/component/mtb.h:
+
+..\include\core/samd21/include/component/nvmctrl.h:
+
+..\include\core/samd21/include/component/pac.h:
+
+..\include\core/samd21/include/component/pm.h:
+
+..\include\core/samd21/include/component/port.h:
+
+..\include\core/samd21/include/component/rtc.h:
+
+..\include\core/samd21/include/component/sercom.h:
+
+..\include\core/samd21/include/component/sysctrl.h:
+
+..\include\core/samd21/include/component/tc.h:
+
+..\include\core/samd21/include/component/tcc.h:
+
+..\include\core/samd21/include/component/usb.h:
+
+..\include\core/samd21/include/component/wdt.h:
+
+..\include\core/samd21/include/instance/ac.h:
+
+..\include\core/samd21/include/instance/adc.h:
+
+..\include\core/samd21/include/instance/dac.h:
+
+..\include\core/samd21/include/instance/dmac.h:
+
+..\include\core/samd21/include/instance/dsu.h:
+
+..\include\core/samd21/include/instance/eic.h:
+
+..\include\core/samd21/include/instance/evsys.h:
+
+..\include\core/samd21/include/instance/gclk.h:
+
+..\include\core/samd21/include/instance/sbmatrix.h:
+
+..\include\core/samd21/include/instance/i2s.h:
+
+..\include\core/samd21/include/instance/mtb.h:
+
+..\include\core/samd21/include/instance/nvmctrl.h:
+
+..\include\core/samd21/include/instance/pac0.h:
+
+..\include\core/samd21/include/instance/pac1.h:
+
+..\include\core/samd21/include/instance/pac2.h:
+
+..\include\core/samd21/include/instance/pm.h:
+
+..\include\core/samd21/include/instance/port.h:
+
+..\include\core/samd21/include/instance/rtc.h:
+
+..\include\core/samd21/include/instance/sercom0.h:
+
+..\include\core/samd21/include/instance/sercom1.h:
+
+..\include\core/samd21/include/instance/sercom2.h:
+
+..\include\core/samd21/include/instance/sercom3.h:
+
+..\include\core/samd21/include/instance/sercom4.h:
+
+..\include\core/samd21/include/instance/sercom5.h:
+
+..\include\core/samd21/include/instance/sysctrl.h:
+
+..\include\core/samd21/include/instance/tc3.h:
+
+..\include\core/samd21/include/instance/tc4.h:
+
+..\include\core/samd21/include/instance/tc5.h:
+
+..\include\core/samd21/include/instance/tcc0.h:
+
+..\include\core/samd21/include/instance/tcc1.h:
+
+..\include\core/samd21/include/instance/tcc2.h:
+
+..\include\core/samd21/include/instance/usb.h:
+
+..\include\core/samd21/include/instance/wdt.h:
+
+..\include\core/samd21/include/pio/samd21g18a.h:
+
+..\include\core/wiring_constants.h:
+
+..\include\core/WVariant.h:
+
+..\include\core/WCharacter.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\ctype.h:
+
+..\include\core/WString.h:
+
+..\include\core/avr/pgmspace.h:
+
+..\include\core/Tone.h:
+
+..\include\core/Arduino.h:
+
+..\include\core/WMath.h:
+
+..\include\core/HardwareSerial.h:
+
+..\include\core/Stream.h:
+
+..\include\core/Print.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
+
+..\include\core/Printable.h:
+
+..\include\core/pulse.h:
+
+..\include\core/delay.h:
+
+..\include\variants/variant.h:
+
+..\include\core/SERCOM.h:
+
+..\include\core/Uart.h:
+
+..\include\core/SERCOM.h:
+
+..\include\core/RingBuffer.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cstddef:
+
+..\include\core/wiring.h:
+
+..\include\core/wiring_digital.h:
+
+..\include\core/wiring_analog.h:
+
+..\include\core/wiring_shift.h:
+
+..\include\core/WInterrupts.h:
+
+..\include\core/USB/USBDesc.h:
+
+..\include\core/USB/USBCore.h:
+
+..\include\core/USB/USBAPI.h:
+
+..\include\core/Stream.h:
+
+..\include\core/RingBuffer.h:
+
+..\include\core/USB/USB_host.h:
+
+..\include\core/USB/samd21_host.h:
+
+..\include\core/USB/CDC.h:
+
+..\include\core/USB/USBDesc.h:
+
+..\include\core/USB/PluggableUSB.h:
diff --git a/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/Stream.o b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/Stream.o
new file mode 100644
index 0000000000000000000000000000000000000000..6c6a5d5ccdb65ddceef263c7d952ad7a98cb82c1
Binary files /dev/null and b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/Stream.o differ
diff --git a/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/Tone.d b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/Tone.d
new file mode 100644
index 0000000000000000000000000000000000000000..cf3854f772394e05b15dc9e4332cda5304fda86a
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/Tone.d
@@ -0,0 +1,446 @@
+src/core/Tone.d src/core/Tone.o: ../src/core/Tone.cpp \
+ ..\include\core/Tone.h ..\include\core/Arduino.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cstdlib \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\c++config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\os_defines.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\cpu_defines.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\string.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\xlocale.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\string.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\math.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cmath \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\bits\cpp_type_traits.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\ext\type_traits.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\math.h \
+ ..\include\core/avr/pgmspace.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\inttypes.h \
+ ..\include\core/avr/interrupt.h ..\include\core/avr/io.h \
+ ..\include\core/binary.h ..\include\core/itoa.h ..\include\core/sam.h \
+ ..\include\core/samd.h ..\include\core/samd21/include/samd21.h \
+ ..\include\core/samd21/include/samd21g18a.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h \
+ ..\include\core/samd21/include/system_samd21.h \
+ ..\include\core/samd21/include/component/ac.h \
+ ..\include\core/samd21/include/component/adc.h \
+ ..\include\core/samd21/include/component/dac.h \
+ ..\include\core/samd21/include/component/dmac.h \
+ ..\include\core/samd21/include/component/dsu.h \
+ ..\include\core/samd21/include/component/eic.h \
+ ..\include\core/samd21/include/component/evsys.h \
+ ..\include\core/samd21/include/component/gclk.h \
+ ..\include\core/samd21/include/component/hmatrixb.h \
+ ..\include\core/samd21/include/component/i2s.h \
+ ..\include\core/samd21/include/component/mtb.h \
+ ..\include\core/samd21/include/component/nvmctrl.h \
+ ..\include\core/samd21/include/component/pac.h \
+ ..\include\core/samd21/include/component/pm.h \
+ ..\include\core/samd21/include/component/port.h \
+ ..\include\core/samd21/include/component/rtc.h \
+ ..\include\core/samd21/include/component/sercom.h \
+ ..\include\core/samd21/include/component/sysctrl.h \
+ ..\include\core/samd21/include/component/tc.h \
+ ..\include\core/samd21/include/component/tcc.h \
+ ..\include\core/samd21/include/component/usb.h \
+ ..\include\core/samd21/include/component/wdt.h \
+ ..\include\core/samd21/include/instance/ac.h \
+ ..\include\core/samd21/include/instance/adc.h \
+ ..\include\core/samd21/include/instance/dac.h \
+ ..\include\core/samd21/include/instance/dmac.h \
+ ..\include\core/samd21/include/instance/dsu.h \
+ ..\include\core/samd21/include/instance/eic.h \
+ ..\include\core/samd21/include/instance/evsys.h \
+ ..\include\core/samd21/include/instance/gclk.h \
+ ..\include\core/samd21/include/instance/sbmatrix.h \
+ ..\include\core/samd21/include/instance/i2s.h \
+ ..\include\core/samd21/include/instance/mtb.h \
+ ..\include\core/samd21/include/instance/nvmctrl.h \
+ ..\include\core/samd21/include/instance/pac0.h \
+ ..\include\core/samd21/include/instance/pac1.h \
+ ..\include\core/samd21/include/instance/pac2.h \
+ ..\include\core/samd21/include/instance/pm.h \
+ ..\include\core/samd21/include/instance/port.h \
+ ..\include\core/samd21/include/instance/rtc.h \
+ ..\include\core/samd21/include/instance/sercom0.h \
+ ..\include\core/samd21/include/instance/sercom1.h \
+ ..\include\core/samd21/include/instance/sercom2.h \
+ ..\include\core/samd21/include/instance/sercom3.h \
+ ..\include\core/samd21/include/instance/sercom4.h \
+ ..\include\core/samd21/include/instance/sercom5.h \
+ ..\include\core/samd21/include/instance/sysctrl.h \
+ ..\include\core/samd21/include/instance/tc3.h \
+ ..\include\core/samd21/include/instance/tc4.h \
+ ..\include\core/samd21/include/instance/tc5.h \
+ ..\include\core/samd21/include/instance/tcc0.h \
+ ..\include\core/samd21/include/instance/tcc1.h \
+ ..\include\core/samd21/include/instance/tcc2.h \
+ ..\include\core/samd21/include/instance/usb.h \
+ ..\include\core/samd21/include/instance/wdt.h \
+ ..\include\core/samd21/include/pio/samd21g18a.h \
+ ..\include\core/wiring_constants.h ..\include\core/WVariant.h \
+ ..\include\core/WCharacter.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\ctype.h \
+ ..\include\core/WString.h ..\include\core/avr/pgmspace.h \
+ ..\include\core/WMath.h ..\include\core/HardwareSerial.h \
+ ..\include\core/Stream.h ..\include\core/Print.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
+ ..\include\core/Printable.h ..\include\core/pulse.h \
+ ..\include\core/delay.h ..\include\variants/variant.h \
+ ..\include\core/SERCOM.h ..\include\core/Uart.h ..\include\core/SERCOM.h \
+ ..\include\core/RingBuffer.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cstddef \
+ ..\include\core/wiring.h ..\include\core/wiring_digital.h \
+ ..\include\core/wiring_analog.h ..\include\core/wiring_shift.h \
+ ..\include\core/WInterrupts.h ..\include\core/USB/USBDesc.h \
+ ..\include\core/USB/USBCore.h ..\include\core/USB/USBAPI.h \
+ ..\include\core/Stream.h ..\include\core/RingBuffer.h \
+ ..\include\core/USB/USB_host.h ..\include\core/USB/samd21_host.h \
+ ..\include\core/USB/CDC.h ..\include\core/USB/USBDesc.h \
+ ..\include\core/USB/PluggableUSB.h
+
+..\include\core/Tone.h:
+
+..\include\core/Arduino.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cstdlib:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\c++config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\os_defines.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\cpu_defines.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\string.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\xlocale.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\string.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\math.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cmath:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\bits\cpp_type_traits.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\ext\type_traits.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\math.h:
+
+..\include\core/avr/pgmspace.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\inttypes.h:
+
+..\include\core/avr/interrupt.h:
+
+..\include\core/avr/io.h:
+
+..\include\core/binary.h:
+
+..\include\core/itoa.h:
+
+..\include\core/sam.h:
+
+..\include\core/samd.h:
+
+..\include\core/samd21/include/samd21.h:
+
+..\include\core/samd21/include/samd21g18a.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h:
+
+..\include\core/samd21/include/system_samd21.h:
+
+..\include\core/samd21/include/component/ac.h:
+
+..\include\core/samd21/include/component/adc.h:
+
+..\include\core/samd21/include/component/dac.h:
+
+..\include\core/samd21/include/component/dmac.h:
+
+..\include\core/samd21/include/component/dsu.h:
+
+..\include\core/samd21/include/component/eic.h:
+
+..\include\core/samd21/include/component/evsys.h:
+
+..\include\core/samd21/include/component/gclk.h:
+
+..\include\core/samd21/include/component/hmatrixb.h:
+
+..\include\core/samd21/include/component/i2s.h:
+
+..\include\core/samd21/include/component/mtb.h:
+
+..\include\core/samd21/include/component/nvmctrl.h:
+
+..\include\core/samd21/include/component/pac.h:
+
+..\include\core/samd21/include/component/pm.h:
+
+..\include\core/samd21/include/component/port.h:
+
+..\include\core/samd21/include/component/rtc.h:
+
+..\include\core/samd21/include/component/sercom.h:
+
+..\include\core/samd21/include/component/sysctrl.h:
+
+..\include\core/samd21/include/component/tc.h:
+
+..\include\core/samd21/include/component/tcc.h:
+
+..\include\core/samd21/include/component/usb.h:
+
+..\include\core/samd21/include/component/wdt.h:
+
+..\include\core/samd21/include/instance/ac.h:
+
+..\include\core/samd21/include/instance/adc.h:
+
+..\include\core/samd21/include/instance/dac.h:
+
+..\include\core/samd21/include/instance/dmac.h:
+
+..\include\core/samd21/include/instance/dsu.h:
+
+..\include\core/samd21/include/instance/eic.h:
+
+..\include\core/samd21/include/instance/evsys.h:
+
+..\include\core/samd21/include/instance/gclk.h:
+
+..\include\core/samd21/include/instance/sbmatrix.h:
+
+..\include\core/samd21/include/instance/i2s.h:
+
+..\include\core/samd21/include/instance/mtb.h:
+
+..\include\core/samd21/include/instance/nvmctrl.h:
+
+..\include\core/samd21/include/instance/pac0.h:
+
+..\include\core/samd21/include/instance/pac1.h:
+
+..\include\core/samd21/include/instance/pac2.h:
+
+..\include\core/samd21/include/instance/pm.h:
+
+..\include\core/samd21/include/instance/port.h:
+
+..\include\core/samd21/include/instance/rtc.h:
+
+..\include\core/samd21/include/instance/sercom0.h:
+
+..\include\core/samd21/include/instance/sercom1.h:
+
+..\include\core/samd21/include/instance/sercom2.h:
+
+..\include\core/samd21/include/instance/sercom3.h:
+
+..\include\core/samd21/include/instance/sercom4.h:
+
+..\include\core/samd21/include/instance/sercom5.h:
+
+..\include\core/samd21/include/instance/sysctrl.h:
+
+..\include\core/samd21/include/instance/tc3.h:
+
+..\include\core/samd21/include/instance/tc4.h:
+
+..\include\core/samd21/include/instance/tc5.h:
+
+..\include\core/samd21/include/instance/tcc0.h:
+
+..\include\core/samd21/include/instance/tcc1.h:
+
+..\include\core/samd21/include/instance/tcc2.h:
+
+..\include\core/samd21/include/instance/usb.h:
+
+..\include\core/samd21/include/instance/wdt.h:
+
+..\include\core/samd21/include/pio/samd21g18a.h:
+
+..\include\core/wiring_constants.h:
+
+..\include\core/WVariant.h:
+
+..\include\core/WCharacter.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\ctype.h:
+
+..\include\core/WString.h:
+
+..\include\core/avr/pgmspace.h:
+
+..\include\core/WMath.h:
+
+..\include\core/HardwareSerial.h:
+
+..\include\core/Stream.h:
+
+..\include\core/Print.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
+
+..\include\core/Printable.h:
+
+..\include\core/pulse.h:
+
+..\include\core/delay.h:
+
+..\include\variants/variant.h:
+
+..\include\core/SERCOM.h:
+
+..\include\core/Uart.h:
+
+..\include\core/SERCOM.h:
+
+..\include\core/RingBuffer.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cstddef:
+
+..\include\core/wiring.h:
+
+..\include\core/wiring_digital.h:
+
+..\include\core/wiring_analog.h:
+
+..\include\core/wiring_shift.h:
+
+..\include\core/WInterrupts.h:
+
+..\include\core/USB/USBDesc.h:
+
+..\include\core/USB/USBCore.h:
+
+..\include\core/USB/USBAPI.h:
+
+..\include\core/Stream.h:
+
+..\include\core/RingBuffer.h:
+
+..\include\core/USB/USB_host.h:
+
+..\include\core/USB/samd21_host.h:
+
+..\include\core/USB/CDC.h:
+
+..\include\core/USB/USBDesc.h:
+
+..\include\core/USB/PluggableUSB.h:
diff --git a/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/Tone.o b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/Tone.o
new file mode 100644
index 0000000000000000000000000000000000000000..22e7e0e169942de9adb8ef2d170b3d18d2a5bb98
Binary files /dev/null and b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/Tone.o differ
diff --git a/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/USB/CDC.d b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/USB/CDC.d
new file mode 100644
index 0000000000000000000000000000000000000000..5047d5bd8043113ee1dc03dbfb237924402ebefb
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/USB/CDC.d
@@ -0,0 +1,456 @@
+src/core/USB/CDC.d src/core/USB/CDC.o: ../src/core/USB/CDC.cpp \
+ ..\include\core/Arduino.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cstdlib \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\c++config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\os_defines.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\cpu_defines.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\string.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\xlocale.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\string.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\math.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cmath \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\bits\cpp_type_traits.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\ext\type_traits.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\math.h \
+ ..\include\core/avr/pgmspace.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\inttypes.h \
+ ..\include\core/avr/interrupt.h ..\include\core/avr/io.h \
+ ..\include\core/binary.h ..\include\core/itoa.h ..\include\core/sam.h \
+ ..\include\core/samd.h ..\include\core/samd21/include/samd21.h \
+ ..\include\core/samd21/include/samd21g18a.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h \
+ ..\include\core/samd21/include/system_samd21.h \
+ ..\include\core/samd21/include/component/ac.h \
+ ..\include\core/samd21/include/component/adc.h \
+ ..\include\core/samd21/include/component/dac.h \
+ ..\include\core/samd21/include/component/dmac.h \
+ ..\include\core/samd21/include/component/dsu.h \
+ ..\include\core/samd21/include/component/eic.h \
+ ..\include\core/samd21/include/component/evsys.h \
+ ..\include\core/samd21/include/component/gclk.h \
+ ..\include\core/samd21/include/component/hmatrixb.h \
+ ..\include\core/samd21/include/component/i2s.h \
+ ..\include\core/samd21/include/component/mtb.h \
+ ..\include\core/samd21/include/component/nvmctrl.h \
+ ..\include\core/samd21/include/component/pac.h \
+ ..\include\core/samd21/include/component/pm.h \
+ ..\include\core/samd21/include/component/port.h \
+ ..\include\core/samd21/include/component/rtc.h \
+ ..\include\core/samd21/include/component/sercom.h \
+ ..\include\core/samd21/include/component/sysctrl.h \
+ ..\include\core/samd21/include/component/tc.h \
+ ..\include\core/samd21/include/component/tcc.h \
+ ..\include\core/samd21/include/component/usb.h \
+ ..\include\core/samd21/include/component/wdt.h \
+ ..\include\core/samd21/include/instance/ac.h \
+ ..\include\core/samd21/include/instance/adc.h \
+ ..\include\core/samd21/include/instance/dac.h \
+ ..\include\core/samd21/include/instance/dmac.h \
+ ..\include\core/samd21/include/instance/dsu.h \
+ ..\include\core/samd21/include/instance/eic.h \
+ ..\include\core/samd21/include/instance/evsys.h \
+ ..\include\core/samd21/include/instance/gclk.h \
+ ..\include\core/samd21/include/instance/sbmatrix.h \
+ ..\include\core/samd21/include/instance/i2s.h \
+ ..\include\core/samd21/include/instance/mtb.h \
+ ..\include\core/samd21/include/instance/nvmctrl.h \
+ ..\include\core/samd21/include/instance/pac0.h \
+ ..\include\core/samd21/include/instance/pac1.h \
+ ..\include\core/samd21/include/instance/pac2.h \
+ ..\include\core/samd21/include/instance/pm.h \
+ ..\include\core/samd21/include/instance/port.h \
+ ..\include\core/samd21/include/instance/rtc.h \
+ ..\include\core/samd21/include/instance/sercom0.h \
+ ..\include\core/samd21/include/instance/sercom1.h \
+ ..\include\core/samd21/include/instance/sercom2.h \
+ ..\include\core/samd21/include/instance/sercom3.h \
+ ..\include\core/samd21/include/instance/sercom4.h \
+ ..\include\core/samd21/include/instance/sercom5.h \
+ ..\include\core/samd21/include/instance/sysctrl.h \
+ ..\include\core/samd21/include/instance/tc3.h \
+ ..\include\core/samd21/include/instance/tc4.h \
+ ..\include\core/samd21/include/instance/tc5.h \
+ ..\include\core/samd21/include/instance/tcc0.h \
+ ..\include\core/samd21/include/instance/tcc1.h \
+ ..\include\core/samd21/include/instance/tcc2.h \
+ ..\include\core/samd21/include/instance/usb.h \
+ ..\include\core/samd21/include/instance/wdt.h \
+ ..\include\core/samd21/include/pio/samd21g18a.h \
+ ..\include\core/wiring_constants.h ..\include\core/WVariant.h \
+ ..\include\core/WCharacter.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\ctype.h \
+ ..\include\core/WString.h ..\include\core/avr/pgmspace.h \
+ ..\include\core/Tone.h ..\include\core/Arduino.h ..\include\core/WMath.h \
+ ..\include\core/HardwareSerial.h ..\include\core/Stream.h \
+ ..\include\core/Print.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
+ ..\include\core/Printable.h ..\include\core/pulse.h \
+ ..\include\core/delay.h ..\include\variants/variant.h \
+ ..\include\core/SERCOM.h ..\include\core/Uart.h ..\include\core/SERCOM.h \
+ ..\include\core/RingBuffer.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cstddef \
+ ..\include\core/wiring.h ..\include\core/wiring_digital.h \
+ ..\include\core/wiring_analog.h ..\include\core/wiring_shift.h \
+ ..\include\core/WInterrupts.h ..\include\core/USB/USBDesc.h \
+ ..\include\core/USB/USBCore.h ..\include\core/USB/USBAPI.h \
+ ..\include\core/Stream.h ..\include\core/RingBuffer.h \
+ ..\include\core/USB/USB_host.h ..\include\core/USB/samd21_host.h \
+ ..\include\core/USB/CDC.h ..\include\core/USB/USBDesc.h \
+ ..\include\core/USB/PluggableUSB.h ..\include\core/Reset.h \
+ ..\include\core\USB/CDC.h ..\include\core\USB/SAMD21_USBDevice.h
+
+..\include\core/Arduino.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cstdlib:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\c++config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\os_defines.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\cpu_defines.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\string.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\xlocale.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\string.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\math.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cmath:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\bits\cpp_type_traits.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\ext\type_traits.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\math.h:
+
+..\include\core/avr/pgmspace.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\inttypes.h:
+
+..\include\core/avr/interrupt.h:
+
+..\include\core/avr/io.h:
+
+..\include\core/binary.h:
+
+..\include\core/itoa.h:
+
+..\include\core/sam.h:
+
+..\include\core/samd.h:
+
+..\include\core/samd21/include/samd21.h:
+
+..\include\core/samd21/include/samd21g18a.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h:
+
+..\include\core/samd21/include/system_samd21.h:
+
+..\include\core/samd21/include/component/ac.h:
+
+..\include\core/samd21/include/component/adc.h:
+
+..\include\core/samd21/include/component/dac.h:
+
+..\include\core/samd21/include/component/dmac.h:
+
+..\include\core/samd21/include/component/dsu.h:
+
+..\include\core/samd21/include/component/eic.h:
+
+..\include\core/samd21/include/component/evsys.h:
+
+..\include\core/samd21/include/component/gclk.h:
+
+..\include\core/samd21/include/component/hmatrixb.h:
+
+..\include\core/samd21/include/component/i2s.h:
+
+..\include\core/samd21/include/component/mtb.h:
+
+..\include\core/samd21/include/component/nvmctrl.h:
+
+..\include\core/samd21/include/component/pac.h:
+
+..\include\core/samd21/include/component/pm.h:
+
+..\include\core/samd21/include/component/port.h:
+
+..\include\core/samd21/include/component/rtc.h:
+
+..\include\core/samd21/include/component/sercom.h:
+
+..\include\core/samd21/include/component/sysctrl.h:
+
+..\include\core/samd21/include/component/tc.h:
+
+..\include\core/samd21/include/component/tcc.h:
+
+..\include\core/samd21/include/component/usb.h:
+
+..\include\core/samd21/include/component/wdt.h:
+
+..\include\core/samd21/include/instance/ac.h:
+
+..\include\core/samd21/include/instance/adc.h:
+
+..\include\core/samd21/include/instance/dac.h:
+
+..\include\core/samd21/include/instance/dmac.h:
+
+..\include\core/samd21/include/instance/dsu.h:
+
+..\include\core/samd21/include/instance/eic.h:
+
+..\include\core/samd21/include/instance/evsys.h:
+
+..\include\core/samd21/include/instance/gclk.h:
+
+..\include\core/samd21/include/instance/sbmatrix.h:
+
+..\include\core/samd21/include/instance/i2s.h:
+
+..\include\core/samd21/include/instance/mtb.h:
+
+..\include\core/samd21/include/instance/nvmctrl.h:
+
+..\include\core/samd21/include/instance/pac0.h:
+
+..\include\core/samd21/include/instance/pac1.h:
+
+..\include\core/samd21/include/instance/pac2.h:
+
+..\include\core/samd21/include/instance/pm.h:
+
+..\include\core/samd21/include/instance/port.h:
+
+..\include\core/samd21/include/instance/rtc.h:
+
+..\include\core/samd21/include/instance/sercom0.h:
+
+..\include\core/samd21/include/instance/sercom1.h:
+
+..\include\core/samd21/include/instance/sercom2.h:
+
+..\include\core/samd21/include/instance/sercom3.h:
+
+..\include\core/samd21/include/instance/sercom4.h:
+
+..\include\core/samd21/include/instance/sercom5.h:
+
+..\include\core/samd21/include/instance/sysctrl.h:
+
+..\include\core/samd21/include/instance/tc3.h:
+
+..\include\core/samd21/include/instance/tc4.h:
+
+..\include\core/samd21/include/instance/tc5.h:
+
+..\include\core/samd21/include/instance/tcc0.h:
+
+..\include\core/samd21/include/instance/tcc1.h:
+
+..\include\core/samd21/include/instance/tcc2.h:
+
+..\include\core/samd21/include/instance/usb.h:
+
+..\include\core/samd21/include/instance/wdt.h:
+
+..\include\core/samd21/include/pio/samd21g18a.h:
+
+..\include\core/wiring_constants.h:
+
+..\include\core/WVariant.h:
+
+..\include\core/WCharacter.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\ctype.h:
+
+..\include\core/WString.h:
+
+..\include\core/avr/pgmspace.h:
+
+..\include\core/Tone.h:
+
+..\include\core/Arduino.h:
+
+..\include\core/WMath.h:
+
+..\include\core/HardwareSerial.h:
+
+..\include\core/Stream.h:
+
+..\include\core/Print.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
+
+..\include\core/Printable.h:
+
+..\include\core/pulse.h:
+
+..\include\core/delay.h:
+
+..\include\variants/variant.h:
+
+..\include\core/SERCOM.h:
+
+..\include\core/Uart.h:
+
+..\include\core/SERCOM.h:
+
+..\include\core/RingBuffer.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cstddef:
+
+..\include\core/wiring.h:
+
+..\include\core/wiring_digital.h:
+
+..\include\core/wiring_analog.h:
+
+..\include\core/wiring_shift.h:
+
+..\include\core/WInterrupts.h:
+
+..\include\core/USB/USBDesc.h:
+
+..\include\core/USB/USBCore.h:
+
+..\include\core/USB/USBAPI.h:
+
+..\include\core/Stream.h:
+
+..\include\core/RingBuffer.h:
+
+..\include\core/USB/USB_host.h:
+
+..\include\core/USB/samd21_host.h:
+
+..\include\core/USB/CDC.h:
+
+..\include\core/USB/USBDesc.h:
+
+..\include\core/USB/PluggableUSB.h:
+
+..\include\core/Reset.h:
+
+..\include\core\USB/CDC.h:
+
+..\include\core\USB/SAMD21_USBDevice.h:
diff --git a/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/USB/CDC.o b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/USB/CDC.o
new file mode 100644
index 0000000000000000000000000000000000000000..6fd14d9224ce4dd04f16cc1762eba9c213506683
Binary files /dev/null and b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/USB/CDC.o differ
diff --git a/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/USB/PluggableUSB.d b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/USB/PluggableUSB.d
new file mode 100644
index 0000000000000000000000000000000000000000..22683f62369defb27a90a1722f14c04c164df9a9
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/USB/PluggableUSB.d
@@ -0,0 +1,163 @@
+src/core/USB/PluggableUSB.d src/core/USB/PluggableUSB.o: \
+ ../src/core/USB/PluggableUSB.cpp ..\include\core\USB/USBAPI.h \
+ ..\include\core/Stream.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\inttypes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ ..\include\core/Print.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
+ ..\include\core/WString.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cstdlib \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\c++config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\os_defines.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\cpu_defines.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\string.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\xlocale.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\string.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\ctype.h \
+ ..\include\core/avr/pgmspace.h ..\include\core/Printable.h \
+ ..\include\core/RingBuffer.h ..\include\core\USB/USBDesc.h \
+ ..\include\core\USB/USBCore.h ..\include\core\USB/PluggableUSB.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cstddef
+
+..\include\core\USB/USBAPI.h:
+
+..\include\core/Stream.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\inttypes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+..\include\core/Print.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
+
+..\include\core/WString.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cstdlib:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\c++config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\os_defines.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\cpu_defines.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\string.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\xlocale.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\string.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\ctype.h:
+
+..\include\core/avr/pgmspace.h:
+
+..\include\core/Printable.h:
+
+..\include\core/RingBuffer.h:
+
+..\include\core\USB/USBDesc.h:
+
+..\include\core\USB/USBCore.h:
+
+..\include\core\USB/PluggableUSB.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cstddef:
diff --git a/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/USB/PluggableUSB.o b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/USB/PluggableUSB.o
new file mode 100644
index 0000000000000000000000000000000000000000..64e2b205407a15ab8efce27c1aa6785f64b05d88
Binary files /dev/null and b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/USB/PluggableUSB.o differ
diff --git a/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/USB/USBCore.d b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/USB/USBCore.d
new file mode 100644
index 0000000000000000000000000000000000000000..3b1d47568a3313eb56b3c7854949db7a293522e3
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/USB/USBCore.d
@@ -0,0 +1,466 @@
+src/core/USB/USBCore.d src/core/USB/USBCore.o: \
+ ../src/core/USB/USBCore.cpp ..\include\core/Arduino.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cstdlib \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\c++config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\os_defines.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\cpu_defines.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\string.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\xlocale.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\string.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\math.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cmath \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\bits\cpp_type_traits.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\ext\type_traits.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\math.h \
+ ..\include\core/avr/pgmspace.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\inttypes.h \
+ ..\include\core/avr/interrupt.h ..\include\core/avr/io.h \
+ ..\include\core/binary.h ..\include\core/itoa.h ..\include\core/sam.h \
+ ..\include\core/samd.h ..\include\core/samd21/include/samd21.h \
+ ..\include\core/samd21/include/samd21g18a.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h \
+ ..\include\core/samd21/include/system_samd21.h \
+ ..\include\core/samd21/include/component/ac.h \
+ ..\include\core/samd21/include/component/adc.h \
+ ..\include\core/samd21/include/component/dac.h \
+ ..\include\core/samd21/include/component/dmac.h \
+ ..\include\core/samd21/include/component/dsu.h \
+ ..\include\core/samd21/include/component/eic.h \
+ ..\include\core/samd21/include/component/evsys.h \
+ ..\include\core/samd21/include/component/gclk.h \
+ ..\include\core/samd21/include/component/hmatrixb.h \
+ ..\include\core/samd21/include/component/i2s.h \
+ ..\include\core/samd21/include/component/mtb.h \
+ ..\include\core/samd21/include/component/nvmctrl.h \
+ ..\include\core/samd21/include/component/pac.h \
+ ..\include\core/samd21/include/component/pm.h \
+ ..\include\core/samd21/include/component/port.h \
+ ..\include\core/samd21/include/component/rtc.h \
+ ..\include\core/samd21/include/component/sercom.h \
+ ..\include\core/samd21/include/component/sysctrl.h \
+ ..\include\core/samd21/include/component/tc.h \
+ ..\include\core/samd21/include/component/tcc.h \
+ ..\include\core/samd21/include/component/usb.h \
+ ..\include\core/samd21/include/component/wdt.h \
+ ..\include\core/samd21/include/instance/ac.h \
+ ..\include\core/samd21/include/instance/adc.h \
+ ..\include\core/samd21/include/instance/dac.h \
+ ..\include\core/samd21/include/instance/dmac.h \
+ ..\include\core/samd21/include/instance/dsu.h \
+ ..\include\core/samd21/include/instance/eic.h \
+ ..\include\core/samd21/include/instance/evsys.h \
+ ..\include\core/samd21/include/instance/gclk.h \
+ ..\include\core/samd21/include/instance/sbmatrix.h \
+ ..\include\core/samd21/include/instance/i2s.h \
+ ..\include\core/samd21/include/instance/mtb.h \
+ ..\include\core/samd21/include/instance/nvmctrl.h \
+ ..\include\core/samd21/include/instance/pac0.h \
+ ..\include\core/samd21/include/instance/pac1.h \
+ ..\include\core/samd21/include/instance/pac2.h \
+ ..\include\core/samd21/include/instance/pm.h \
+ ..\include\core/samd21/include/instance/port.h \
+ ..\include\core/samd21/include/instance/rtc.h \
+ ..\include\core/samd21/include/instance/sercom0.h \
+ ..\include\core/samd21/include/instance/sercom1.h \
+ ..\include\core/samd21/include/instance/sercom2.h \
+ ..\include\core/samd21/include/instance/sercom3.h \
+ ..\include\core/samd21/include/instance/sercom4.h \
+ ..\include\core/samd21/include/instance/sercom5.h \
+ ..\include\core/samd21/include/instance/sysctrl.h \
+ ..\include\core/samd21/include/instance/tc3.h \
+ ..\include\core/samd21/include/instance/tc4.h \
+ ..\include\core/samd21/include/instance/tc5.h \
+ ..\include\core/samd21/include/instance/tcc0.h \
+ ..\include\core/samd21/include/instance/tcc1.h \
+ ..\include\core/samd21/include/instance/tcc2.h \
+ ..\include\core/samd21/include/instance/usb.h \
+ ..\include\core/samd21/include/instance/wdt.h \
+ ..\include\core/samd21/include/pio/samd21g18a.h \
+ ..\include\core/wiring_constants.h ..\include\core/WVariant.h \
+ ..\include\core/WCharacter.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\ctype.h \
+ ..\include\core/WString.h ..\include\core/avr/pgmspace.h \
+ ..\include\core/Tone.h ..\include\core/Arduino.h ..\include\core/WMath.h \
+ ..\include\core/HardwareSerial.h ..\include\core/Stream.h \
+ ..\include\core/Print.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
+ ..\include\core/Printable.h ..\include\core/pulse.h \
+ ..\include\core/delay.h ..\include\variants/variant.h \
+ ..\include\core/SERCOM.h ..\include\core/Uart.h ..\include\core/SERCOM.h \
+ ..\include\core/RingBuffer.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cstddef \
+ ..\include\core/wiring.h ..\include\core/wiring_digital.h \
+ ..\include\core/wiring_analog.h ..\include\core/wiring_shift.h \
+ ..\include\core/WInterrupts.h ..\include\core/USB/USBDesc.h \
+ ..\include\core/USB/USBCore.h ..\include\core/USB/USBAPI.h \
+ ..\include\core/Stream.h ..\include\core/RingBuffer.h \
+ ..\include\core/USB/USB_host.h ..\include\core/USB/samd21_host.h \
+ ..\include\core/USB/CDC.h ..\include\core/USB/USBDesc.h \
+ ..\include\core/USB/PluggableUSB.h \
+ ..\include\core\USB/SAMD21_USBDevice.h \
+ ..\include\core\USB/PluggableUSB.h ..\include\core\USB/CDC.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include-fixed\limits.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include-fixed\syslimits.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\limits.h
+
+..\include\core/Arduino.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cstdlib:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\c++config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\os_defines.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\cpu_defines.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\string.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\xlocale.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\string.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\math.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cmath:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\bits\cpp_type_traits.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\ext\type_traits.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\math.h:
+
+..\include\core/avr/pgmspace.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\inttypes.h:
+
+..\include\core/avr/interrupt.h:
+
+..\include\core/avr/io.h:
+
+..\include\core/binary.h:
+
+..\include\core/itoa.h:
+
+..\include\core/sam.h:
+
+..\include\core/samd.h:
+
+..\include\core/samd21/include/samd21.h:
+
+..\include\core/samd21/include/samd21g18a.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h:
+
+..\include\core/samd21/include/system_samd21.h:
+
+..\include\core/samd21/include/component/ac.h:
+
+..\include\core/samd21/include/component/adc.h:
+
+..\include\core/samd21/include/component/dac.h:
+
+..\include\core/samd21/include/component/dmac.h:
+
+..\include\core/samd21/include/component/dsu.h:
+
+..\include\core/samd21/include/component/eic.h:
+
+..\include\core/samd21/include/component/evsys.h:
+
+..\include\core/samd21/include/component/gclk.h:
+
+..\include\core/samd21/include/component/hmatrixb.h:
+
+..\include\core/samd21/include/component/i2s.h:
+
+..\include\core/samd21/include/component/mtb.h:
+
+..\include\core/samd21/include/component/nvmctrl.h:
+
+..\include\core/samd21/include/component/pac.h:
+
+..\include\core/samd21/include/component/pm.h:
+
+..\include\core/samd21/include/component/port.h:
+
+..\include\core/samd21/include/component/rtc.h:
+
+..\include\core/samd21/include/component/sercom.h:
+
+..\include\core/samd21/include/component/sysctrl.h:
+
+..\include\core/samd21/include/component/tc.h:
+
+..\include\core/samd21/include/component/tcc.h:
+
+..\include\core/samd21/include/component/usb.h:
+
+..\include\core/samd21/include/component/wdt.h:
+
+..\include\core/samd21/include/instance/ac.h:
+
+..\include\core/samd21/include/instance/adc.h:
+
+..\include\core/samd21/include/instance/dac.h:
+
+..\include\core/samd21/include/instance/dmac.h:
+
+..\include\core/samd21/include/instance/dsu.h:
+
+..\include\core/samd21/include/instance/eic.h:
+
+..\include\core/samd21/include/instance/evsys.h:
+
+..\include\core/samd21/include/instance/gclk.h:
+
+..\include\core/samd21/include/instance/sbmatrix.h:
+
+..\include\core/samd21/include/instance/i2s.h:
+
+..\include\core/samd21/include/instance/mtb.h:
+
+..\include\core/samd21/include/instance/nvmctrl.h:
+
+..\include\core/samd21/include/instance/pac0.h:
+
+..\include\core/samd21/include/instance/pac1.h:
+
+..\include\core/samd21/include/instance/pac2.h:
+
+..\include\core/samd21/include/instance/pm.h:
+
+..\include\core/samd21/include/instance/port.h:
+
+..\include\core/samd21/include/instance/rtc.h:
+
+..\include\core/samd21/include/instance/sercom0.h:
+
+..\include\core/samd21/include/instance/sercom1.h:
+
+..\include\core/samd21/include/instance/sercom2.h:
+
+..\include\core/samd21/include/instance/sercom3.h:
+
+..\include\core/samd21/include/instance/sercom4.h:
+
+..\include\core/samd21/include/instance/sercom5.h:
+
+..\include\core/samd21/include/instance/sysctrl.h:
+
+..\include\core/samd21/include/instance/tc3.h:
+
+..\include\core/samd21/include/instance/tc4.h:
+
+..\include\core/samd21/include/instance/tc5.h:
+
+..\include\core/samd21/include/instance/tcc0.h:
+
+..\include\core/samd21/include/instance/tcc1.h:
+
+..\include\core/samd21/include/instance/tcc2.h:
+
+..\include\core/samd21/include/instance/usb.h:
+
+..\include\core/samd21/include/instance/wdt.h:
+
+..\include\core/samd21/include/pio/samd21g18a.h:
+
+..\include\core/wiring_constants.h:
+
+..\include\core/WVariant.h:
+
+..\include\core/WCharacter.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\ctype.h:
+
+..\include\core/WString.h:
+
+..\include\core/avr/pgmspace.h:
+
+..\include\core/Tone.h:
+
+..\include\core/Arduino.h:
+
+..\include\core/WMath.h:
+
+..\include\core/HardwareSerial.h:
+
+..\include\core/Stream.h:
+
+..\include\core/Print.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
+
+..\include\core/Printable.h:
+
+..\include\core/pulse.h:
+
+..\include\core/delay.h:
+
+..\include\variants/variant.h:
+
+..\include\core/SERCOM.h:
+
+..\include\core/Uart.h:
+
+..\include\core/SERCOM.h:
+
+..\include\core/RingBuffer.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cstddef:
+
+..\include\core/wiring.h:
+
+..\include\core/wiring_digital.h:
+
+..\include\core/wiring_analog.h:
+
+..\include\core/wiring_shift.h:
+
+..\include\core/WInterrupts.h:
+
+..\include\core/USB/USBDesc.h:
+
+..\include\core/USB/USBCore.h:
+
+..\include\core/USB/USBAPI.h:
+
+..\include\core/Stream.h:
+
+..\include\core/RingBuffer.h:
+
+..\include\core/USB/USB_host.h:
+
+..\include\core/USB/samd21_host.h:
+
+..\include\core/USB/CDC.h:
+
+..\include\core/USB/USBDesc.h:
+
+..\include\core/USB/PluggableUSB.h:
+
+..\include\core\USB/SAMD21_USBDevice.h:
+
+..\include\core\USB/PluggableUSB.h:
+
+..\include\core\USB/CDC.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include-fixed\limits.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include-fixed\syslimits.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\limits.h:
diff --git a/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/USB/USBCore.o b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/USB/USBCore.o
new file mode 100644
index 0000000000000000000000000000000000000000..6ea580799c23e65431872ef5e0114db6120e1cc1
Binary files /dev/null and b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/USB/USBCore.o differ
diff --git a/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/USB/samd21_host.d b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/USB/samd21_host.d
new file mode 100644
index 0000000000000000000000000000000000000000..b9076f40043b7247997da74fde2696c4e47f3c73
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/USB/samd21_host.d
@@ -0,0 +1,373 @@
+src/core/USB/samd21_host.d src/core/USB/samd21_host.o: \
+ ../src/core/USB/samd21_host.c ..\include\core/Arduino.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\string.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\xlocale.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\string.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\math.h \
+ ..\include\core/avr/pgmspace.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\inttypes.h \
+ ..\include\core/avr/interrupt.h ..\include\core/avr/io.h \
+ ..\include\core/binary.h ..\include\core/itoa.h ..\include\core/sam.h \
+ ..\include\core/samd.h ..\include\core/samd21/include/samd21.h \
+ ..\include\core/samd21/include/samd21g18a.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h \
+ ..\include\core/samd21/include/system_samd21.h \
+ ..\include\core/samd21/include/component/ac.h \
+ ..\include\core/samd21/include/component/adc.h \
+ ..\include\core/samd21/include/component/dac.h \
+ ..\include\core/samd21/include/component/dmac.h \
+ ..\include\core/samd21/include/component/dsu.h \
+ ..\include\core/samd21/include/component/eic.h \
+ ..\include\core/samd21/include/component/evsys.h \
+ ..\include\core/samd21/include/component/gclk.h \
+ ..\include\core/samd21/include/component/hmatrixb.h \
+ ..\include\core/samd21/include/component/i2s.h \
+ ..\include\core/samd21/include/component/mtb.h \
+ ..\include\core/samd21/include/component/nvmctrl.h \
+ ..\include\core/samd21/include/component/pac.h \
+ ..\include\core/samd21/include/component/pm.h \
+ ..\include\core/samd21/include/component/port.h \
+ ..\include\core/samd21/include/component/rtc.h \
+ ..\include\core/samd21/include/component/sercom.h \
+ ..\include\core/samd21/include/component/sysctrl.h \
+ ..\include\core/samd21/include/component/tc.h \
+ ..\include\core/samd21/include/component/tcc.h \
+ ..\include\core/samd21/include/component/usb.h \
+ ..\include\core/samd21/include/component/wdt.h \
+ ..\include\core/samd21/include/instance/ac.h \
+ ..\include\core/samd21/include/instance/adc.h \
+ ..\include\core/samd21/include/instance/dac.h \
+ ..\include\core/samd21/include/instance/dmac.h \
+ ..\include\core/samd21/include/instance/dsu.h \
+ ..\include\core/samd21/include/instance/eic.h \
+ ..\include\core/samd21/include/instance/evsys.h \
+ ..\include\core/samd21/include/instance/gclk.h \
+ ..\include\core/samd21/include/instance/sbmatrix.h \
+ ..\include\core/samd21/include/instance/i2s.h \
+ ..\include\core/samd21/include/instance/mtb.h \
+ ..\include\core/samd21/include/instance/nvmctrl.h \
+ ..\include\core/samd21/include/instance/pac0.h \
+ ..\include\core/samd21/include/instance/pac1.h \
+ ..\include\core/samd21/include/instance/pac2.h \
+ ..\include\core/samd21/include/instance/pm.h \
+ ..\include\core/samd21/include/instance/port.h \
+ ..\include\core/samd21/include/instance/rtc.h \
+ ..\include\core/samd21/include/instance/sercom0.h \
+ ..\include\core/samd21/include/instance/sercom1.h \
+ ..\include\core/samd21/include/instance/sercom2.h \
+ ..\include\core/samd21/include/instance/sercom3.h \
+ ..\include\core/samd21/include/instance/sercom4.h \
+ ..\include\core/samd21/include/instance/sercom5.h \
+ ..\include\core/samd21/include/instance/sysctrl.h \
+ ..\include\core/samd21/include/instance/tc3.h \
+ ..\include\core/samd21/include/instance/tc4.h \
+ ..\include\core/samd21/include/instance/tc5.h \
+ ..\include\core/samd21/include/instance/tcc0.h \
+ ..\include\core/samd21/include/instance/tcc1.h \
+ ..\include\core/samd21/include/instance/tcc2.h \
+ ..\include\core/samd21/include/instance/usb.h \
+ ..\include\core/samd21/include/instance/wdt.h \
+ ..\include\core/samd21/include/pio/samd21g18a.h \
+ ..\include\core/wiring_constants.h ..\include\core/WVariant.h \
+ ..\include\core/delay.h ..\include\variants/variant.h \
+ ..\include\core/wiring.h ..\include\core/wiring_digital.h \
+ ..\include\core/wiring_analog.h ..\include\core/wiring_shift.h \
+ ..\include\core/WInterrupts.h ..\include\core/USB/USBDesc.h \
+ ..\include\core/USB/USBCore.h ..\include\core/USB/USBAPI.h \
+ ..\include\core/USB/USB_host.h ..\include\core/USB/samd21_host.h \
+ ..\include\core\USB/USB_host.h ..\include\core\USB/samd21_host.h \
+ ..\include\core/wiring_private.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h
+
+..\include\core/Arduino.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\string.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\xlocale.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\string.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\math.h:
+
+..\include\core/avr/pgmspace.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\inttypes.h:
+
+..\include\core/avr/interrupt.h:
+
+..\include\core/avr/io.h:
+
+..\include\core/binary.h:
+
+..\include\core/itoa.h:
+
+..\include\core/sam.h:
+
+..\include\core/samd.h:
+
+..\include\core/samd21/include/samd21.h:
+
+..\include\core/samd21/include/samd21g18a.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h:
+
+..\include\core/samd21/include/system_samd21.h:
+
+..\include\core/samd21/include/component/ac.h:
+
+..\include\core/samd21/include/component/adc.h:
+
+..\include\core/samd21/include/component/dac.h:
+
+..\include\core/samd21/include/component/dmac.h:
+
+..\include\core/samd21/include/component/dsu.h:
+
+..\include\core/samd21/include/component/eic.h:
+
+..\include\core/samd21/include/component/evsys.h:
+
+..\include\core/samd21/include/component/gclk.h:
+
+..\include\core/samd21/include/component/hmatrixb.h:
+
+..\include\core/samd21/include/component/i2s.h:
+
+..\include\core/samd21/include/component/mtb.h:
+
+..\include\core/samd21/include/component/nvmctrl.h:
+
+..\include\core/samd21/include/component/pac.h:
+
+..\include\core/samd21/include/component/pm.h:
+
+..\include\core/samd21/include/component/port.h:
+
+..\include\core/samd21/include/component/rtc.h:
+
+..\include\core/samd21/include/component/sercom.h:
+
+..\include\core/samd21/include/component/sysctrl.h:
+
+..\include\core/samd21/include/component/tc.h:
+
+..\include\core/samd21/include/component/tcc.h:
+
+..\include\core/samd21/include/component/usb.h:
+
+..\include\core/samd21/include/component/wdt.h:
+
+..\include\core/samd21/include/instance/ac.h:
+
+..\include\core/samd21/include/instance/adc.h:
+
+..\include\core/samd21/include/instance/dac.h:
+
+..\include\core/samd21/include/instance/dmac.h:
+
+..\include\core/samd21/include/instance/dsu.h:
+
+..\include\core/samd21/include/instance/eic.h:
+
+..\include\core/samd21/include/instance/evsys.h:
+
+..\include\core/samd21/include/instance/gclk.h:
+
+..\include\core/samd21/include/instance/sbmatrix.h:
+
+..\include\core/samd21/include/instance/i2s.h:
+
+..\include\core/samd21/include/instance/mtb.h:
+
+..\include\core/samd21/include/instance/nvmctrl.h:
+
+..\include\core/samd21/include/instance/pac0.h:
+
+..\include\core/samd21/include/instance/pac1.h:
+
+..\include\core/samd21/include/instance/pac2.h:
+
+..\include\core/samd21/include/instance/pm.h:
+
+..\include\core/samd21/include/instance/port.h:
+
+..\include\core/samd21/include/instance/rtc.h:
+
+..\include\core/samd21/include/instance/sercom0.h:
+
+..\include\core/samd21/include/instance/sercom1.h:
+
+..\include\core/samd21/include/instance/sercom2.h:
+
+..\include\core/samd21/include/instance/sercom3.h:
+
+..\include\core/samd21/include/instance/sercom4.h:
+
+..\include\core/samd21/include/instance/sercom5.h:
+
+..\include\core/samd21/include/instance/sysctrl.h:
+
+..\include\core/samd21/include/instance/tc3.h:
+
+..\include\core/samd21/include/instance/tc4.h:
+
+..\include\core/samd21/include/instance/tc5.h:
+
+..\include\core/samd21/include/instance/tcc0.h:
+
+..\include\core/samd21/include/instance/tcc1.h:
+
+..\include\core/samd21/include/instance/tcc2.h:
+
+..\include\core/samd21/include/instance/usb.h:
+
+..\include\core/samd21/include/instance/wdt.h:
+
+..\include\core/samd21/include/pio/samd21g18a.h:
+
+..\include\core/wiring_constants.h:
+
+..\include\core/WVariant.h:
+
+..\include\core/delay.h:
+
+..\include\variants/variant.h:
+
+..\include\core/wiring.h:
+
+..\include\core/wiring_digital.h:
+
+..\include\core/wiring_analog.h:
+
+..\include\core/wiring_shift.h:
+
+..\include\core/WInterrupts.h:
+
+..\include\core/USB/USBDesc.h:
+
+..\include\core/USB/USBCore.h:
+
+..\include\core/USB/USBAPI.h:
+
+..\include\core/USB/USB_host.h:
+
+..\include\core/USB/samd21_host.h:
+
+..\include\core\USB/USB_host.h:
+
+..\include\core\USB/samd21_host.h:
+
+..\include\core/wiring_private.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
diff --git a/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/USB/samd21_host.o b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/USB/samd21_host.o
new file mode 100644
index 0000000000000000000000000000000000000000..9825938ce4b37efaf1cb1ec725bf254d8e7be06b
Binary files /dev/null and b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/USB/samd21_host.o differ
diff --git a/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/Uart.d b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/Uart.d
new file mode 100644
index 0000000000000000000000000000000000000000..f91f3f371576aeca1ba2ca2f65bd5890aa1ddf97
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/Uart.d
@@ -0,0 +1,451 @@
+src/core/Uart.d src/core/Uart.o: ../src/core/Uart.cpp \
+ ..\include\core/Arduino.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cstdlib \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\c++config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\os_defines.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\cpu_defines.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\string.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\xlocale.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\string.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\math.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cmath \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\bits\cpp_type_traits.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\ext\type_traits.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\math.h \
+ ..\include\core/avr/pgmspace.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\inttypes.h \
+ ..\include\core/avr/interrupt.h ..\include\core/avr/io.h \
+ ..\include\core/binary.h ..\include\core/itoa.h ..\include\core/sam.h \
+ ..\include\core/samd.h ..\include\core/samd21/include/samd21.h \
+ ..\include\core/samd21/include/samd21g18a.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h \
+ ..\include\core/samd21/include/system_samd21.h \
+ ..\include\core/samd21/include/component/ac.h \
+ ..\include\core/samd21/include/component/adc.h \
+ ..\include\core/samd21/include/component/dac.h \
+ ..\include\core/samd21/include/component/dmac.h \
+ ..\include\core/samd21/include/component/dsu.h \
+ ..\include\core/samd21/include/component/eic.h \
+ ..\include\core/samd21/include/component/evsys.h \
+ ..\include\core/samd21/include/component/gclk.h \
+ ..\include\core/samd21/include/component/hmatrixb.h \
+ ..\include\core/samd21/include/component/i2s.h \
+ ..\include\core/samd21/include/component/mtb.h \
+ ..\include\core/samd21/include/component/nvmctrl.h \
+ ..\include\core/samd21/include/component/pac.h \
+ ..\include\core/samd21/include/component/pm.h \
+ ..\include\core/samd21/include/component/port.h \
+ ..\include\core/samd21/include/component/rtc.h \
+ ..\include\core/samd21/include/component/sercom.h \
+ ..\include\core/samd21/include/component/sysctrl.h \
+ ..\include\core/samd21/include/component/tc.h \
+ ..\include\core/samd21/include/component/tcc.h \
+ ..\include\core/samd21/include/component/usb.h \
+ ..\include\core/samd21/include/component/wdt.h \
+ ..\include\core/samd21/include/instance/ac.h \
+ ..\include\core/samd21/include/instance/adc.h \
+ ..\include\core/samd21/include/instance/dac.h \
+ ..\include\core/samd21/include/instance/dmac.h \
+ ..\include\core/samd21/include/instance/dsu.h \
+ ..\include\core/samd21/include/instance/eic.h \
+ ..\include\core/samd21/include/instance/evsys.h \
+ ..\include\core/samd21/include/instance/gclk.h \
+ ..\include\core/samd21/include/instance/sbmatrix.h \
+ ..\include\core/samd21/include/instance/i2s.h \
+ ..\include\core/samd21/include/instance/mtb.h \
+ ..\include\core/samd21/include/instance/nvmctrl.h \
+ ..\include\core/samd21/include/instance/pac0.h \
+ ..\include\core/samd21/include/instance/pac1.h \
+ ..\include\core/samd21/include/instance/pac2.h \
+ ..\include\core/samd21/include/instance/pm.h \
+ ..\include\core/samd21/include/instance/port.h \
+ ..\include\core/samd21/include/instance/rtc.h \
+ ..\include\core/samd21/include/instance/sercom0.h \
+ ..\include\core/samd21/include/instance/sercom1.h \
+ ..\include\core/samd21/include/instance/sercom2.h \
+ ..\include\core/samd21/include/instance/sercom3.h \
+ ..\include\core/samd21/include/instance/sercom4.h \
+ ..\include\core/samd21/include/instance/sercom5.h \
+ ..\include\core/samd21/include/instance/sysctrl.h \
+ ..\include\core/samd21/include/instance/tc3.h \
+ ..\include\core/samd21/include/instance/tc4.h \
+ ..\include\core/samd21/include/instance/tc5.h \
+ ..\include\core/samd21/include/instance/tcc0.h \
+ ..\include\core/samd21/include/instance/tcc1.h \
+ ..\include\core/samd21/include/instance/tcc2.h \
+ ..\include\core/samd21/include/instance/usb.h \
+ ..\include\core/samd21/include/instance/wdt.h \
+ ..\include\core/samd21/include/pio/samd21g18a.h \
+ ..\include\core/wiring_constants.h ..\include\core/WVariant.h \
+ ..\include\core/WCharacter.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\ctype.h \
+ ..\include\core/WString.h ..\include\core/avr/pgmspace.h \
+ ..\include\core/Tone.h ..\include\core/Arduino.h ..\include\core/WMath.h \
+ ..\include\core/HardwareSerial.h ..\include\core/Stream.h \
+ ..\include\core/Print.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
+ ..\include\core/Printable.h ..\include\core/pulse.h \
+ ..\include\core/delay.h ..\include\variants/variant.h \
+ ..\include\core/SERCOM.h ..\include\core/Uart.h ..\include\core/SERCOM.h \
+ ..\include\core/RingBuffer.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cstddef \
+ ..\include\core/wiring.h ..\include\core/wiring_digital.h \
+ ..\include\core/wiring_analog.h ..\include\core/wiring_shift.h \
+ ..\include\core/WInterrupts.h ..\include\core/USB/USBDesc.h \
+ ..\include\core/USB/USBCore.h ..\include\core/USB/USBAPI.h \
+ ..\include\core/Stream.h ..\include\core/RingBuffer.h \
+ ..\include\core/USB/USB_host.h ..\include\core/USB/samd21_host.h \
+ ..\include\core/USB/CDC.h ..\include\core/USB/USBDesc.h \
+ ..\include\core/USB/PluggableUSB.h ..\include\core/wiring_private.h
+
+..\include\core/Arduino.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cstdlib:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\c++config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\os_defines.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\cpu_defines.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\string.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\xlocale.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\string.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\math.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cmath:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\bits\cpp_type_traits.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\ext\type_traits.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\math.h:
+
+..\include\core/avr/pgmspace.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\inttypes.h:
+
+..\include\core/avr/interrupt.h:
+
+..\include\core/avr/io.h:
+
+..\include\core/binary.h:
+
+..\include\core/itoa.h:
+
+..\include\core/sam.h:
+
+..\include\core/samd.h:
+
+..\include\core/samd21/include/samd21.h:
+
+..\include\core/samd21/include/samd21g18a.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h:
+
+..\include\core/samd21/include/system_samd21.h:
+
+..\include\core/samd21/include/component/ac.h:
+
+..\include\core/samd21/include/component/adc.h:
+
+..\include\core/samd21/include/component/dac.h:
+
+..\include\core/samd21/include/component/dmac.h:
+
+..\include\core/samd21/include/component/dsu.h:
+
+..\include\core/samd21/include/component/eic.h:
+
+..\include\core/samd21/include/component/evsys.h:
+
+..\include\core/samd21/include/component/gclk.h:
+
+..\include\core/samd21/include/component/hmatrixb.h:
+
+..\include\core/samd21/include/component/i2s.h:
+
+..\include\core/samd21/include/component/mtb.h:
+
+..\include\core/samd21/include/component/nvmctrl.h:
+
+..\include\core/samd21/include/component/pac.h:
+
+..\include\core/samd21/include/component/pm.h:
+
+..\include\core/samd21/include/component/port.h:
+
+..\include\core/samd21/include/component/rtc.h:
+
+..\include\core/samd21/include/component/sercom.h:
+
+..\include\core/samd21/include/component/sysctrl.h:
+
+..\include\core/samd21/include/component/tc.h:
+
+..\include\core/samd21/include/component/tcc.h:
+
+..\include\core/samd21/include/component/usb.h:
+
+..\include\core/samd21/include/component/wdt.h:
+
+..\include\core/samd21/include/instance/ac.h:
+
+..\include\core/samd21/include/instance/adc.h:
+
+..\include\core/samd21/include/instance/dac.h:
+
+..\include\core/samd21/include/instance/dmac.h:
+
+..\include\core/samd21/include/instance/dsu.h:
+
+..\include\core/samd21/include/instance/eic.h:
+
+..\include\core/samd21/include/instance/evsys.h:
+
+..\include\core/samd21/include/instance/gclk.h:
+
+..\include\core/samd21/include/instance/sbmatrix.h:
+
+..\include\core/samd21/include/instance/i2s.h:
+
+..\include\core/samd21/include/instance/mtb.h:
+
+..\include\core/samd21/include/instance/nvmctrl.h:
+
+..\include\core/samd21/include/instance/pac0.h:
+
+..\include\core/samd21/include/instance/pac1.h:
+
+..\include\core/samd21/include/instance/pac2.h:
+
+..\include\core/samd21/include/instance/pm.h:
+
+..\include\core/samd21/include/instance/port.h:
+
+..\include\core/samd21/include/instance/rtc.h:
+
+..\include\core/samd21/include/instance/sercom0.h:
+
+..\include\core/samd21/include/instance/sercom1.h:
+
+..\include\core/samd21/include/instance/sercom2.h:
+
+..\include\core/samd21/include/instance/sercom3.h:
+
+..\include\core/samd21/include/instance/sercom4.h:
+
+..\include\core/samd21/include/instance/sercom5.h:
+
+..\include\core/samd21/include/instance/sysctrl.h:
+
+..\include\core/samd21/include/instance/tc3.h:
+
+..\include\core/samd21/include/instance/tc4.h:
+
+..\include\core/samd21/include/instance/tc5.h:
+
+..\include\core/samd21/include/instance/tcc0.h:
+
+..\include\core/samd21/include/instance/tcc1.h:
+
+..\include\core/samd21/include/instance/tcc2.h:
+
+..\include\core/samd21/include/instance/usb.h:
+
+..\include\core/samd21/include/instance/wdt.h:
+
+..\include\core/samd21/include/pio/samd21g18a.h:
+
+..\include\core/wiring_constants.h:
+
+..\include\core/WVariant.h:
+
+..\include\core/WCharacter.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\ctype.h:
+
+..\include\core/WString.h:
+
+..\include\core/avr/pgmspace.h:
+
+..\include\core/Tone.h:
+
+..\include\core/Arduino.h:
+
+..\include\core/WMath.h:
+
+..\include\core/HardwareSerial.h:
+
+..\include\core/Stream.h:
+
+..\include\core/Print.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
+
+..\include\core/Printable.h:
+
+..\include\core/pulse.h:
+
+..\include\core/delay.h:
+
+..\include\variants/variant.h:
+
+..\include\core/SERCOM.h:
+
+..\include\core/Uart.h:
+
+..\include\core/SERCOM.h:
+
+..\include\core/RingBuffer.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cstddef:
+
+..\include\core/wiring.h:
+
+..\include\core/wiring_digital.h:
+
+..\include\core/wiring_analog.h:
+
+..\include\core/wiring_shift.h:
+
+..\include\core/WInterrupts.h:
+
+..\include\core/USB/USBDesc.h:
+
+..\include\core/USB/USBCore.h:
+
+..\include\core/USB/USBAPI.h:
+
+..\include\core/Stream.h:
+
+..\include\core/RingBuffer.h:
+
+..\include\core/USB/USB_host.h:
+
+..\include\core/USB/samd21_host.h:
+
+..\include\core/USB/CDC.h:
+
+..\include\core/USB/USBDesc.h:
+
+..\include\core/USB/PluggableUSB.h:
+
+..\include\core/wiring_private.h:
diff --git a/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/Uart.o b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/Uart.o
new file mode 100644
index 0000000000000000000000000000000000000000..3fae231051b85541b1ac62fb764db62796aaeb17
Binary files /dev/null and b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/Uart.o differ
diff --git a/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/WInterrupts.d b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/WInterrupts.d
new file mode 100644
index 0000000000000000000000000000000000000000..789f3524c0a3d3eef58860a4cbaef312a1460ef7
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/WInterrupts.d
@@ -0,0 +1,368 @@
+src/core/WInterrupts.d src/core/WInterrupts.o: ../src/core/WInterrupts.c \
+ ..\include\core/Arduino.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\string.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\xlocale.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\string.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\math.h \
+ ..\include\core/avr/pgmspace.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\inttypes.h \
+ ..\include\core/avr/interrupt.h ..\include\core/avr/io.h \
+ ..\include\core/binary.h ..\include\core/itoa.h ..\include\core/sam.h \
+ ..\include\core/samd.h ..\include\core/samd21/include/samd21.h \
+ ..\include\core/samd21/include/samd21g18a.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h \
+ ..\include\core/samd21/include/system_samd21.h \
+ ..\include\core/samd21/include/component/ac.h \
+ ..\include\core/samd21/include/component/adc.h \
+ ..\include\core/samd21/include/component/dac.h \
+ ..\include\core/samd21/include/component/dmac.h \
+ ..\include\core/samd21/include/component/dsu.h \
+ ..\include\core/samd21/include/component/eic.h \
+ ..\include\core/samd21/include/component/evsys.h \
+ ..\include\core/samd21/include/component/gclk.h \
+ ..\include\core/samd21/include/component/hmatrixb.h \
+ ..\include\core/samd21/include/component/i2s.h \
+ ..\include\core/samd21/include/component/mtb.h \
+ ..\include\core/samd21/include/component/nvmctrl.h \
+ ..\include\core/samd21/include/component/pac.h \
+ ..\include\core/samd21/include/component/pm.h \
+ ..\include\core/samd21/include/component/port.h \
+ ..\include\core/samd21/include/component/rtc.h \
+ ..\include\core/samd21/include/component/sercom.h \
+ ..\include\core/samd21/include/component/sysctrl.h \
+ ..\include\core/samd21/include/component/tc.h \
+ ..\include\core/samd21/include/component/tcc.h \
+ ..\include\core/samd21/include/component/usb.h \
+ ..\include\core/samd21/include/component/wdt.h \
+ ..\include\core/samd21/include/instance/ac.h \
+ ..\include\core/samd21/include/instance/adc.h \
+ ..\include\core/samd21/include/instance/dac.h \
+ ..\include\core/samd21/include/instance/dmac.h \
+ ..\include\core/samd21/include/instance/dsu.h \
+ ..\include\core/samd21/include/instance/eic.h \
+ ..\include\core/samd21/include/instance/evsys.h \
+ ..\include\core/samd21/include/instance/gclk.h \
+ ..\include\core/samd21/include/instance/sbmatrix.h \
+ ..\include\core/samd21/include/instance/i2s.h \
+ ..\include\core/samd21/include/instance/mtb.h \
+ ..\include\core/samd21/include/instance/nvmctrl.h \
+ ..\include\core/samd21/include/instance/pac0.h \
+ ..\include\core/samd21/include/instance/pac1.h \
+ ..\include\core/samd21/include/instance/pac2.h \
+ ..\include\core/samd21/include/instance/pm.h \
+ ..\include\core/samd21/include/instance/port.h \
+ ..\include\core/samd21/include/instance/rtc.h \
+ ..\include\core/samd21/include/instance/sercom0.h \
+ ..\include\core/samd21/include/instance/sercom1.h \
+ ..\include\core/samd21/include/instance/sercom2.h \
+ ..\include\core/samd21/include/instance/sercom3.h \
+ ..\include\core/samd21/include/instance/sercom4.h \
+ ..\include\core/samd21/include/instance/sercom5.h \
+ ..\include\core/samd21/include/instance/sysctrl.h \
+ ..\include\core/samd21/include/instance/tc3.h \
+ ..\include\core/samd21/include/instance/tc4.h \
+ ..\include\core/samd21/include/instance/tc5.h \
+ ..\include\core/samd21/include/instance/tcc0.h \
+ ..\include\core/samd21/include/instance/tcc1.h \
+ ..\include\core/samd21/include/instance/tcc2.h \
+ ..\include\core/samd21/include/instance/usb.h \
+ ..\include\core/samd21/include/instance/wdt.h \
+ ..\include\core/samd21/include/pio/samd21g18a.h \
+ ..\include\core/wiring_constants.h ..\include\core/WVariant.h \
+ ..\include\core/delay.h ..\include\variants/variant.h \
+ ..\include\core/wiring.h ..\include\core/wiring_digital.h \
+ ..\include\core/wiring_analog.h ..\include\core/wiring_shift.h \
+ ..\include\core/WInterrupts.h ..\include\core/USB/USBDesc.h \
+ ..\include\core/USB/USBCore.h ..\include\core/USB/USBAPI.h \
+ ..\include\core/USB/USB_host.h ..\include\core/USB/samd21_host.h \
+ ..\include\core/wiring_private.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h
+
+..\include\core/Arduino.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\string.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\xlocale.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\string.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\math.h:
+
+..\include\core/avr/pgmspace.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\inttypes.h:
+
+..\include\core/avr/interrupt.h:
+
+..\include\core/avr/io.h:
+
+..\include\core/binary.h:
+
+..\include\core/itoa.h:
+
+..\include\core/sam.h:
+
+..\include\core/samd.h:
+
+..\include\core/samd21/include/samd21.h:
+
+..\include\core/samd21/include/samd21g18a.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h:
+
+..\include\core/samd21/include/system_samd21.h:
+
+..\include\core/samd21/include/component/ac.h:
+
+..\include\core/samd21/include/component/adc.h:
+
+..\include\core/samd21/include/component/dac.h:
+
+..\include\core/samd21/include/component/dmac.h:
+
+..\include\core/samd21/include/component/dsu.h:
+
+..\include\core/samd21/include/component/eic.h:
+
+..\include\core/samd21/include/component/evsys.h:
+
+..\include\core/samd21/include/component/gclk.h:
+
+..\include\core/samd21/include/component/hmatrixb.h:
+
+..\include\core/samd21/include/component/i2s.h:
+
+..\include\core/samd21/include/component/mtb.h:
+
+..\include\core/samd21/include/component/nvmctrl.h:
+
+..\include\core/samd21/include/component/pac.h:
+
+..\include\core/samd21/include/component/pm.h:
+
+..\include\core/samd21/include/component/port.h:
+
+..\include\core/samd21/include/component/rtc.h:
+
+..\include\core/samd21/include/component/sercom.h:
+
+..\include\core/samd21/include/component/sysctrl.h:
+
+..\include\core/samd21/include/component/tc.h:
+
+..\include\core/samd21/include/component/tcc.h:
+
+..\include\core/samd21/include/component/usb.h:
+
+..\include\core/samd21/include/component/wdt.h:
+
+..\include\core/samd21/include/instance/ac.h:
+
+..\include\core/samd21/include/instance/adc.h:
+
+..\include\core/samd21/include/instance/dac.h:
+
+..\include\core/samd21/include/instance/dmac.h:
+
+..\include\core/samd21/include/instance/dsu.h:
+
+..\include\core/samd21/include/instance/eic.h:
+
+..\include\core/samd21/include/instance/evsys.h:
+
+..\include\core/samd21/include/instance/gclk.h:
+
+..\include\core/samd21/include/instance/sbmatrix.h:
+
+..\include\core/samd21/include/instance/i2s.h:
+
+..\include\core/samd21/include/instance/mtb.h:
+
+..\include\core/samd21/include/instance/nvmctrl.h:
+
+..\include\core/samd21/include/instance/pac0.h:
+
+..\include\core/samd21/include/instance/pac1.h:
+
+..\include\core/samd21/include/instance/pac2.h:
+
+..\include\core/samd21/include/instance/pm.h:
+
+..\include\core/samd21/include/instance/port.h:
+
+..\include\core/samd21/include/instance/rtc.h:
+
+..\include\core/samd21/include/instance/sercom0.h:
+
+..\include\core/samd21/include/instance/sercom1.h:
+
+..\include\core/samd21/include/instance/sercom2.h:
+
+..\include\core/samd21/include/instance/sercom3.h:
+
+..\include\core/samd21/include/instance/sercom4.h:
+
+..\include\core/samd21/include/instance/sercom5.h:
+
+..\include\core/samd21/include/instance/sysctrl.h:
+
+..\include\core/samd21/include/instance/tc3.h:
+
+..\include\core/samd21/include/instance/tc4.h:
+
+..\include\core/samd21/include/instance/tc5.h:
+
+..\include\core/samd21/include/instance/tcc0.h:
+
+..\include\core/samd21/include/instance/tcc1.h:
+
+..\include\core/samd21/include/instance/tcc2.h:
+
+..\include\core/samd21/include/instance/usb.h:
+
+..\include\core/samd21/include/instance/wdt.h:
+
+..\include\core/samd21/include/pio/samd21g18a.h:
+
+..\include\core/wiring_constants.h:
+
+..\include\core/WVariant.h:
+
+..\include\core/delay.h:
+
+..\include\variants/variant.h:
+
+..\include\core/wiring.h:
+
+..\include\core/wiring_digital.h:
+
+..\include\core/wiring_analog.h:
+
+..\include\core/wiring_shift.h:
+
+..\include\core/WInterrupts.h:
+
+..\include\core/USB/USBDesc.h:
+
+..\include\core/USB/USBCore.h:
+
+..\include\core/USB/USBAPI.h:
+
+..\include\core/USB/USB_host.h:
+
+..\include\core/USB/samd21_host.h:
+
+..\include\core/wiring_private.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
diff --git a/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/WInterrupts.o b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/WInterrupts.o
new file mode 100644
index 0000000000000000000000000000000000000000..d64fd7b772d190d158fbcef7a8797fa51bcff5ed
Binary files /dev/null and b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/WInterrupts.o differ
diff --git a/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/WMath.d b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/WMath.d
new file mode 100644
index 0000000000000000000000000000000000000000..c008822860789678fd441dcbcef9780c631eab46
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/WMath.d
@@ -0,0 +1,82 @@
+src/core/WMath.d src/core/WMath.o: ../src/core/WMath.cpp \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cstdlib \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\c++config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\os_defines.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\cpu_defines.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ ..\include\core/WMath.h
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cstdlib:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\c++config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\os_defines.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\cpu_defines.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+..\include\core/WMath.h:
diff --git a/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/WMath.o b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/WMath.o
new file mode 100644
index 0000000000000000000000000000000000000000..8625745c601118535e9ad33b8bafb6f936162574
Binary files /dev/null and b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/WMath.o differ
diff --git a/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/WString.d b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/WString.d
new file mode 100644
index 0000000000000000000000000000000000000000..cdceb9f48cf94175637d82d1f8f394481ae9a8d5
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/WString.d
@@ -0,0 +1,105 @@
+src/core/WString.d src/core/WString.o: ../src/core/WString.cpp \
+ ..\include\core/WString.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cstdlib \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\c++config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\os_defines.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\cpu_defines.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\string.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\xlocale.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\string.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\ctype.h \
+ ..\include\core/avr/pgmspace.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\inttypes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ ..\include\core/itoa.h ..\include\core/avr/dtostrf.h
+
+..\include\core/WString.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cstdlib:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\c++config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\os_defines.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\cpu_defines.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\string.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\xlocale.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\string.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\ctype.h:
+
+..\include\core/avr/pgmspace.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\inttypes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+..\include\core/itoa.h:
+
+..\include\core/avr/dtostrf.h:
diff --git a/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/WString.o b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/WString.o
new file mode 100644
index 0000000000000000000000000000000000000000..a626113ad0f41efcfafd90957fae9fb4b57ce2a9
Binary files /dev/null and b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/WString.o differ
diff --git a/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/abi.d b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/abi.d
new file mode 100644
index 0000000000000000000000000000000000000000..4967b8ea5cec90817c7b9deb42b82a4f5077d59b
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/abi.d
@@ -0,0 +1,67 @@
+src/core/abi.d src/core/abi.o: ../src/core/abi.cpp \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cstdlib \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\c++config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\os_defines.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\cpu_defines.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cstdlib:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\c++config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\os_defines.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\cpu_defines.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
diff --git a/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/abi.o b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/abi.o
new file mode 100644
index 0000000000000000000000000000000000000000..55b4651e58854874391f721fa5b77acc2f50afce
Binary files /dev/null and b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/abi.o differ
diff --git a/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/avr/dtostrf.d b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/avr/dtostrf.d
new file mode 100644
index 0000000000000000000000000000000000000000..6b04cf315377001f785bf07d1857a5ae3323ad10
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/avr/dtostrf.d
@@ -0,0 +1,85 @@
+src/core/avr/dtostrf.d src/core/avr/dtostrf.o: ../src/core/avr/dtostrf.c \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
diff --git a/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/avr/dtostrf.o b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/avr/dtostrf.o
new file mode 100644
index 0000000000000000000000000000000000000000..8320ec0f0cc8b9191224ad504f5d17afbf21e3db
Binary files /dev/null and b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/avr/dtostrf.o differ
diff --git a/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/cortex_handlers.d b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/cortex_handlers.d
new file mode 100644
index 0000000000000000000000000000000000000000..a12f0627b0b495c2c0578f2f783a24b19902e57a
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/cortex_handlers.d
@@ -0,0 +1,296 @@
+src/core/cortex_handlers.d src/core/cortex_handlers.o: \
+ ../src/core/cortex_handlers.c ..\include\core/sam.h \
+ ..\include\core/samd.h ..\include\core/samd21/include/samd21.h \
+ ..\include\core/samd21/include/samd21g18a.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h \
+ ..\include\core/samd21/include/system_samd21.h \
+ ..\include\core/samd21/include/component/ac.h \
+ ..\include\core/samd21/include/component/adc.h \
+ ..\include\core/samd21/include/component/dac.h \
+ ..\include\core/samd21/include/component/dmac.h \
+ ..\include\core/samd21/include/component/dsu.h \
+ ..\include\core/samd21/include/component/eic.h \
+ ..\include\core/samd21/include/component/evsys.h \
+ ..\include\core/samd21/include/component/gclk.h \
+ ..\include\core/samd21/include/component/hmatrixb.h \
+ ..\include\core/samd21/include/component/i2s.h \
+ ..\include\core/samd21/include/component/mtb.h \
+ ..\include\core/samd21/include/component/nvmctrl.h \
+ ..\include\core/samd21/include/component/pac.h \
+ ..\include\core/samd21/include/component/pm.h \
+ ..\include\core/samd21/include/component/port.h \
+ ..\include\core/samd21/include/component/rtc.h \
+ ..\include\core/samd21/include/component/sercom.h \
+ ..\include\core/samd21/include/component/sysctrl.h \
+ ..\include\core/samd21/include/component/tc.h \
+ ..\include\core/samd21/include/component/tcc.h \
+ ..\include\core/samd21/include/component/usb.h \
+ ..\include\core/samd21/include/component/wdt.h \
+ ..\include\core/samd21/include/instance/ac.h \
+ ..\include\core/samd21/include/instance/adc.h \
+ ..\include\core/samd21/include/instance/dac.h \
+ ..\include\core/samd21/include/instance/dmac.h \
+ ..\include\core/samd21/include/instance/dsu.h \
+ ..\include\core/samd21/include/instance/eic.h \
+ ..\include\core/samd21/include/instance/evsys.h \
+ ..\include\core/samd21/include/instance/gclk.h \
+ ..\include\core/samd21/include/instance/sbmatrix.h \
+ ..\include\core/samd21/include/instance/i2s.h \
+ ..\include\core/samd21/include/instance/mtb.h \
+ ..\include\core/samd21/include/instance/nvmctrl.h \
+ ..\include\core/samd21/include/instance/pac0.h \
+ ..\include\core/samd21/include/instance/pac1.h \
+ ..\include\core/samd21/include/instance/pac2.h \
+ ..\include\core/samd21/include/instance/pm.h \
+ ..\include\core/samd21/include/instance/port.h \
+ ..\include\core/samd21/include/instance/rtc.h \
+ ..\include\core/samd21/include/instance/sercom0.h \
+ ..\include\core/samd21/include/instance/sercom1.h \
+ ..\include\core/samd21/include/instance/sercom2.h \
+ ..\include\core/samd21/include/instance/sercom3.h \
+ ..\include\core/samd21/include/instance/sercom4.h \
+ ..\include\core/samd21/include/instance/sercom5.h \
+ ..\include\core/samd21/include/instance/sysctrl.h \
+ ..\include\core/samd21/include/instance/tc3.h \
+ ..\include\core/samd21/include/instance/tc4.h \
+ ..\include\core/samd21/include/instance/tc5.h \
+ ..\include\core/samd21/include/instance/tcc0.h \
+ ..\include\core/samd21/include/instance/tcc1.h \
+ ..\include\core/samd21/include/instance/tcc2.h \
+ ..\include\core/samd21/include/instance/usb.h \
+ ..\include\core/samd21/include/instance/wdt.h \
+ ..\include\core/samd21/include/pio/samd21g18a.h \
+ ..\include\variants/variant.h ..\include\core/WVariant.h \
+ ..\include\core/sam.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h
+
+..\include\core/sam.h:
+
+..\include\core/samd.h:
+
+..\include\core/samd21/include/samd21.h:
+
+..\include\core/samd21/include/samd21g18a.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h:
+
+..\include\core/samd21/include/system_samd21.h:
+
+..\include\core/samd21/include/component/ac.h:
+
+..\include\core/samd21/include/component/adc.h:
+
+..\include\core/samd21/include/component/dac.h:
+
+..\include\core/samd21/include/component/dmac.h:
+
+..\include\core/samd21/include/component/dsu.h:
+
+..\include\core/samd21/include/component/eic.h:
+
+..\include\core/samd21/include/component/evsys.h:
+
+..\include\core/samd21/include/component/gclk.h:
+
+..\include\core/samd21/include/component/hmatrixb.h:
+
+..\include\core/samd21/include/component/i2s.h:
+
+..\include\core/samd21/include/component/mtb.h:
+
+..\include\core/samd21/include/component/nvmctrl.h:
+
+..\include\core/samd21/include/component/pac.h:
+
+..\include\core/samd21/include/component/pm.h:
+
+..\include\core/samd21/include/component/port.h:
+
+..\include\core/samd21/include/component/rtc.h:
+
+..\include\core/samd21/include/component/sercom.h:
+
+..\include\core/samd21/include/component/sysctrl.h:
+
+..\include\core/samd21/include/component/tc.h:
+
+..\include\core/samd21/include/component/tcc.h:
+
+..\include\core/samd21/include/component/usb.h:
+
+..\include\core/samd21/include/component/wdt.h:
+
+..\include\core/samd21/include/instance/ac.h:
+
+..\include\core/samd21/include/instance/adc.h:
+
+..\include\core/samd21/include/instance/dac.h:
+
+..\include\core/samd21/include/instance/dmac.h:
+
+..\include\core/samd21/include/instance/dsu.h:
+
+..\include\core/samd21/include/instance/eic.h:
+
+..\include\core/samd21/include/instance/evsys.h:
+
+..\include\core/samd21/include/instance/gclk.h:
+
+..\include\core/samd21/include/instance/sbmatrix.h:
+
+..\include\core/samd21/include/instance/i2s.h:
+
+..\include\core/samd21/include/instance/mtb.h:
+
+..\include\core/samd21/include/instance/nvmctrl.h:
+
+..\include\core/samd21/include/instance/pac0.h:
+
+..\include\core/samd21/include/instance/pac1.h:
+
+..\include\core/samd21/include/instance/pac2.h:
+
+..\include\core/samd21/include/instance/pm.h:
+
+..\include\core/samd21/include/instance/port.h:
+
+..\include\core/samd21/include/instance/rtc.h:
+
+..\include\core/samd21/include/instance/sercom0.h:
+
+..\include\core/samd21/include/instance/sercom1.h:
+
+..\include\core/samd21/include/instance/sercom2.h:
+
+..\include\core/samd21/include/instance/sercom3.h:
+
+..\include\core/samd21/include/instance/sercom4.h:
+
+..\include\core/samd21/include/instance/sercom5.h:
+
+..\include\core/samd21/include/instance/sysctrl.h:
+
+..\include\core/samd21/include/instance/tc3.h:
+
+..\include\core/samd21/include/instance/tc4.h:
+
+..\include\core/samd21/include/instance/tc5.h:
+
+..\include\core/samd21/include/instance/tcc0.h:
+
+..\include\core/samd21/include/instance/tcc1.h:
+
+..\include\core/samd21/include/instance/tcc2.h:
+
+..\include\core/samd21/include/instance/usb.h:
+
+..\include\core/samd21/include/instance/wdt.h:
+
+..\include\core/samd21/include/pio/samd21g18a.h:
+
+..\include\variants/variant.h:
+
+..\include\core/WVariant.h:
+
+..\include\core/sam.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
diff --git a/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/cortex_handlers.o b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/cortex_handlers.o
new file mode 100644
index 0000000000000000000000000000000000000000..fbfd937eb9dede64333f9bfd3056c7560af3500d
Binary files /dev/null and b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/cortex_handlers.o differ
diff --git a/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/delay.d b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/delay.d
new file mode 100644
index 0000000000000000000000000000000000000000..ff72e81c34fa54bb466c742f1d282a87cce6be93
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/delay.d
@@ -0,0 +1,333 @@
+src/core/delay.d src/core/delay.o: ../src/core/delay.c \
+ ..\include\core/delay.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ ..\include\variants/variant.h ..\include\core/WVariant.h \
+ ..\include\core/sam.h ..\include\core/samd.h \
+ ..\include\core/samd21/include/samd21.h \
+ ..\include\core/samd21/include/samd21g18a.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h \
+ ..\include\core/samd21/include/system_samd21.h \
+ ..\include\core/samd21/include/component/ac.h \
+ ..\include\core/samd21/include/component/adc.h \
+ ..\include\core/samd21/include/component/dac.h \
+ ..\include\core/samd21/include/component/dmac.h \
+ ..\include\core/samd21/include/component/dsu.h \
+ ..\include\core/samd21/include/component/eic.h \
+ ..\include\core/samd21/include/component/evsys.h \
+ ..\include\core/samd21/include/component/gclk.h \
+ ..\include\core/samd21/include/component/hmatrixb.h \
+ ..\include\core/samd21/include/component/i2s.h \
+ ..\include\core/samd21/include/component/mtb.h \
+ ..\include\core/samd21/include/component/nvmctrl.h \
+ ..\include\core/samd21/include/component/pac.h \
+ ..\include\core/samd21/include/component/pm.h \
+ ..\include\core/samd21/include/component/port.h \
+ ..\include\core/samd21/include/component/rtc.h \
+ ..\include\core/samd21/include/component/sercom.h \
+ ..\include\core/samd21/include/component/sysctrl.h \
+ ..\include\core/samd21/include/component/tc.h \
+ ..\include\core/samd21/include/component/tcc.h \
+ ..\include\core/samd21/include/component/usb.h \
+ ..\include\core/samd21/include/component/wdt.h \
+ ..\include\core/samd21/include/instance/ac.h \
+ ..\include\core/samd21/include/instance/adc.h \
+ ..\include\core/samd21/include/instance/dac.h \
+ ..\include\core/samd21/include/instance/dmac.h \
+ ..\include\core/samd21/include/instance/dsu.h \
+ ..\include\core/samd21/include/instance/eic.h \
+ ..\include\core/samd21/include/instance/evsys.h \
+ ..\include\core/samd21/include/instance/gclk.h \
+ ..\include\core/samd21/include/instance/sbmatrix.h \
+ ..\include\core/samd21/include/instance/i2s.h \
+ ..\include\core/samd21/include/instance/mtb.h \
+ ..\include\core/samd21/include/instance/nvmctrl.h \
+ ..\include\core/samd21/include/instance/pac0.h \
+ ..\include\core/samd21/include/instance/pac1.h \
+ ..\include\core/samd21/include/instance/pac2.h \
+ ..\include\core/samd21/include/instance/pm.h \
+ ..\include\core/samd21/include/instance/port.h \
+ ..\include\core/samd21/include/instance/rtc.h \
+ ..\include\core/samd21/include/instance/sercom0.h \
+ ..\include\core/samd21/include/instance/sercom1.h \
+ ..\include\core/samd21/include/instance/sercom2.h \
+ ..\include\core/samd21/include/instance/sercom3.h \
+ ..\include\core/samd21/include/instance/sercom4.h \
+ ..\include\core/samd21/include/instance/sercom5.h \
+ ..\include\core/samd21/include/instance/sysctrl.h \
+ ..\include\core/samd21/include/instance/tc3.h \
+ ..\include\core/samd21/include/instance/tc4.h \
+ ..\include\core/samd21/include/instance/tc5.h \
+ ..\include\core/samd21/include/instance/tcc0.h \
+ ..\include\core/samd21/include/instance/tcc1.h \
+ ..\include\core/samd21/include/instance/tcc2.h \
+ ..\include\core/samd21/include/instance/usb.h \
+ ..\include\core/samd21/include/instance/wdt.h \
+ ..\include\core/samd21/include/pio/samd21g18a.h \
+ ..\include\core/Arduino.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\string.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\xlocale.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\string.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\math.h \
+ ..\include\core/avr/pgmspace.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\inttypes.h \
+ ..\include\core/avr/interrupt.h ..\include\core/avr/io.h \
+ ..\include\core/binary.h ..\include\core/itoa.h \
+ ..\include\core/wiring_constants.h ..\include\core/delay.h \
+ ..\include\core/wiring.h ..\include\core/wiring_digital.h \
+ ..\include\core/wiring_analog.h ..\include\core/wiring_shift.h \
+ ..\include\core/WInterrupts.h ..\include\core/USB/USBDesc.h \
+ ..\include\core/USB/USBCore.h ..\include\core/USB/USBAPI.h \
+ ..\include\core/USB/USB_host.h ..\include\core/USB/samd21_host.h \
+ ..\include\core/Reset.h
+
+..\include\core/delay.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+..\include\variants/variant.h:
+
+..\include\core/WVariant.h:
+
+..\include\core/sam.h:
+
+..\include\core/samd.h:
+
+..\include\core/samd21/include/samd21.h:
+
+..\include\core/samd21/include/samd21g18a.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h:
+
+..\include\core/samd21/include/system_samd21.h:
+
+..\include\core/samd21/include/component/ac.h:
+
+..\include\core/samd21/include/component/adc.h:
+
+..\include\core/samd21/include/component/dac.h:
+
+..\include\core/samd21/include/component/dmac.h:
+
+..\include\core/samd21/include/component/dsu.h:
+
+..\include\core/samd21/include/component/eic.h:
+
+..\include\core/samd21/include/component/evsys.h:
+
+..\include\core/samd21/include/component/gclk.h:
+
+..\include\core/samd21/include/component/hmatrixb.h:
+
+..\include\core/samd21/include/component/i2s.h:
+
+..\include\core/samd21/include/component/mtb.h:
+
+..\include\core/samd21/include/component/nvmctrl.h:
+
+..\include\core/samd21/include/component/pac.h:
+
+..\include\core/samd21/include/component/pm.h:
+
+..\include\core/samd21/include/component/port.h:
+
+..\include\core/samd21/include/component/rtc.h:
+
+..\include\core/samd21/include/component/sercom.h:
+
+..\include\core/samd21/include/component/sysctrl.h:
+
+..\include\core/samd21/include/component/tc.h:
+
+..\include\core/samd21/include/component/tcc.h:
+
+..\include\core/samd21/include/component/usb.h:
+
+..\include\core/samd21/include/component/wdt.h:
+
+..\include\core/samd21/include/instance/ac.h:
+
+..\include\core/samd21/include/instance/adc.h:
+
+..\include\core/samd21/include/instance/dac.h:
+
+..\include\core/samd21/include/instance/dmac.h:
+
+..\include\core/samd21/include/instance/dsu.h:
+
+..\include\core/samd21/include/instance/eic.h:
+
+..\include\core/samd21/include/instance/evsys.h:
+
+..\include\core/samd21/include/instance/gclk.h:
+
+..\include\core/samd21/include/instance/sbmatrix.h:
+
+..\include\core/samd21/include/instance/i2s.h:
+
+..\include\core/samd21/include/instance/mtb.h:
+
+..\include\core/samd21/include/instance/nvmctrl.h:
+
+..\include\core/samd21/include/instance/pac0.h:
+
+..\include\core/samd21/include/instance/pac1.h:
+
+..\include\core/samd21/include/instance/pac2.h:
+
+..\include\core/samd21/include/instance/pm.h:
+
+..\include\core/samd21/include/instance/port.h:
+
+..\include\core/samd21/include/instance/rtc.h:
+
+..\include\core/samd21/include/instance/sercom0.h:
+
+..\include\core/samd21/include/instance/sercom1.h:
+
+..\include\core/samd21/include/instance/sercom2.h:
+
+..\include\core/samd21/include/instance/sercom3.h:
+
+..\include\core/samd21/include/instance/sercom4.h:
+
+..\include\core/samd21/include/instance/sercom5.h:
+
+..\include\core/samd21/include/instance/sysctrl.h:
+
+..\include\core/samd21/include/instance/tc3.h:
+
+..\include\core/samd21/include/instance/tc4.h:
+
+..\include\core/samd21/include/instance/tc5.h:
+
+..\include\core/samd21/include/instance/tcc0.h:
+
+..\include\core/samd21/include/instance/tcc1.h:
+
+..\include\core/samd21/include/instance/tcc2.h:
+
+..\include\core/samd21/include/instance/usb.h:
+
+..\include\core/samd21/include/instance/wdt.h:
+
+..\include\core/samd21/include/pio/samd21g18a.h:
+
+..\include\core/Arduino.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\string.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\xlocale.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\string.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\math.h:
+
+..\include\core/avr/pgmspace.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\inttypes.h:
+
+..\include\core/avr/interrupt.h:
+
+..\include\core/avr/io.h:
+
+..\include\core/binary.h:
+
+..\include\core/itoa.h:
+
+..\include\core/wiring_constants.h:
+
+..\include\core/delay.h:
+
+..\include\core/wiring.h:
+
+..\include\core/wiring_digital.h:
+
+..\include\core/wiring_analog.h:
+
+..\include\core/wiring_shift.h:
+
+..\include\core/WInterrupts.h:
+
+..\include\core/USB/USBDesc.h:
+
+..\include\core/USB/USBCore.h:
+
+..\include\core/USB/USBAPI.h:
+
+..\include\core/USB/USB_host.h:
+
+..\include\core/USB/samd21_host.h:
+
+..\include\core/Reset.h:
diff --git a/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/delay.o b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/delay.o
new file mode 100644
index 0000000000000000000000000000000000000000..57204b6fd8c4240030d455b9a0ef10ff0b54dfb3
Binary files /dev/null and b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/delay.o differ
diff --git a/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/hooks.d b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/hooks.d
new file mode 100644
index 0000000000000000000000000000000000000000..a3f48944021e9c55d43644ab5ed2d123ffb8293c
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/hooks.d
@@ -0,0 +1 @@
+src/core/hooks.d src/core/hooks.o: ../src/core/hooks.c
diff --git a/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/hooks.o b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/hooks.o
new file mode 100644
index 0000000000000000000000000000000000000000..cdcd63a4af55a629bcc6d86252e5f4139deae7a2
Binary files /dev/null and b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/hooks.o differ
diff --git a/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/itoa.d b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/itoa.d
new file mode 100644
index 0000000000000000000000000000000000000000..271b6d296e460e3f110a743076045092e478e488
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/itoa.d
@@ -0,0 +1,55 @@
+src/core/itoa.d src/core/itoa.o: ../src/core/itoa.c \
+ ..\include\core/itoa.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\string.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\xlocale.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\string.h
+
+..\include\core/itoa.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\string.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\xlocale.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\string.h:
diff --git a/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/itoa.o b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/itoa.o
new file mode 100644
index 0000000000000000000000000000000000000000..dfab3119e82804522ba2cf6ec1a7867591b89839
Binary files /dev/null and b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/itoa.o differ
diff --git a/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/main.d b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/main.d
new file mode 100644
index 0000000000000000000000000000000000000000..8c456ec5234a3592251df9cc3c11cbfe032ee092
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/main.d
@@ -0,0 +1,449 @@
+src/core/main.d src/core/main.o: ../src/core/main.cpp \
+ ..\include\core/Arduino.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cstdlib \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\c++config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\os_defines.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\cpu_defines.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\string.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\xlocale.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\string.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\math.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cmath \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\bits\cpp_type_traits.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\ext\type_traits.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\math.h \
+ ..\include\core/avr/pgmspace.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\inttypes.h \
+ ..\include\core/avr/interrupt.h ..\include\core/avr/io.h \
+ ..\include\core/binary.h ..\include\core/itoa.h ..\include\core/sam.h \
+ ..\include\core/samd.h ..\include\core/samd21/include/samd21.h \
+ ..\include\core/samd21/include/samd21g18a.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h \
+ ..\include\core/samd21/include/system_samd21.h \
+ ..\include\core/samd21/include/component/ac.h \
+ ..\include\core/samd21/include/component/adc.h \
+ ..\include\core/samd21/include/component/dac.h \
+ ..\include\core/samd21/include/component/dmac.h \
+ ..\include\core/samd21/include/component/dsu.h \
+ ..\include\core/samd21/include/component/eic.h \
+ ..\include\core/samd21/include/component/evsys.h \
+ ..\include\core/samd21/include/component/gclk.h \
+ ..\include\core/samd21/include/component/hmatrixb.h \
+ ..\include\core/samd21/include/component/i2s.h \
+ ..\include\core/samd21/include/component/mtb.h \
+ ..\include\core/samd21/include/component/nvmctrl.h \
+ ..\include\core/samd21/include/component/pac.h \
+ ..\include\core/samd21/include/component/pm.h \
+ ..\include\core/samd21/include/component/port.h \
+ ..\include\core/samd21/include/component/rtc.h \
+ ..\include\core/samd21/include/component/sercom.h \
+ ..\include\core/samd21/include/component/sysctrl.h \
+ ..\include\core/samd21/include/component/tc.h \
+ ..\include\core/samd21/include/component/tcc.h \
+ ..\include\core/samd21/include/component/usb.h \
+ ..\include\core/samd21/include/component/wdt.h \
+ ..\include\core/samd21/include/instance/ac.h \
+ ..\include\core/samd21/include/instance/adc.h \
+ ..\include\core/samd21/include/instance/dac.h \
+ ..\include\core/samd21/include/instance/dmac.h \
+ ..\include\core/samd21/include/instance/dsu.h \
+ ..\include\core/samd21/include/instance/eic.h \
+ ..\include\core/samd21/include/instance/evsys.h \
+ ..\include\core/samd21/include/instance/gclk.h \
+ ..\include\core/samd21/include/instance/sbmatrix.h \
+ ..\include\core/samd21/include/instance/i2s.h \
+ ..\include\core/samd21/include/instance/mtb.h \
+ ..\include\core/samd21/include/instance/nvmctrl.h \
+ ..\include\core/samd21/include/instance/pac0.h \
+ ..\include\core/samd21/include/instance/pac1.h \
+ ..\include\core/samd21/include/instance/pac2.h \
+ ..\include\core/samd21/include/instance/pm.h \
+ ..\include\core/samd21/include/instance/port.h \
+ ..\include\core/samd21/include/instance/rtc.h \
+ ..\include\core/samd21/include/instance/sercom0.h \
+ ..\include\core/samd21/include/instance/sercom1.h \
+ ..\include\core/samd21/include/instance/sercom2.h \
+ ..\include\core/samd21/include/instance/sercom3.h \
+ ..\include\core/samd21/include/instance/sercom4.h \
+ ..\include\core/samd21/include/instance/sercom5.h \
+ ..\include\core/samd21/include/instance/sysctrl.h \
+ ..\include\core/samd21/include/instance/tc3.h \
+ ..\include\core/samd21/include/instance/tc4.h \
+ ..\include\core/samd21/include/instance/tc5.h \
+ ..\include\core/samd21/include/instance/tcc0.h \
+ ..\include\core/samd21/include/instance/tcc1.h \
+ ..\include\core/samd21/include/instance/tcc2.h \
+ ..\include\core/samd21/include/instance/usb.h \
+ ..\include\core/samd21/include/instance/wdt.h \
+ ..\include\core/samd21/include/pio/samd21g18a.h \
+ ..\include\core/wiring_constants.h ..\include\core/WVariant.h \
+ ..\include\core/WCharacter.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\ctype.h \
+ ..\include\core/WString.h ..\include\core/avr/pgmspace.h \
+ ..\include\core/Tone.h ..\include\core/Arduino.h ..\include\core/WMath.h \
+ ..\include\core/HardwareSerial.h ..\include\core/Stream.h \
+ ..\include\core/Print.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
+ ..\include\core/Printable.h ..\include\core/pulse.h \
+ ..\include\core/delay.h ..\include\variants/variant.h \
+ ..\include\core/SERCOM.h ..\include\core/Uart.h ..\include\core/SERCOM.h \
+ ..\include\core/RingBuffer.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cstddef \
+ ..\include\core/wiring.h ..\include\core/wiring_digital.h \
+ ..\include\core/wiring_analog.h ..\include\core/wiring_shift.h \
+ ..\include\core/WInterrupts.h ..\include\core/USB/USBDesc.h \
+ ..\include\core/USB/USBCore.h ..\include\core/USB/USBAPI.h \
+ ..\include\core/Stream.h ..\include\core/RingBuffer.h \
+ ..\include\core/USB/USB_host.h ..\include\core/USB/samd21_host.h \
+ ..\include\core/USB/CDC.h ..\include\core/USB/USBDesc.h \
+ ..\include\core/USB/PluggableUSB.h
+
+..\include\core/Arduino.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cstdlib:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\c++config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\os_defines.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\cpu_defines.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\string.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\xlocale.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\string.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\math.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cmath:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\bits\cpp_type_traits.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\ext\type_traits.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\math.h:
+
+..\include\core/avr/pgmspace.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\inttypes.h:
+
+..\include\core/avr/interrupt.h:
+
+..\include\core/avr/io.h:
+
+..\include\core/binary.h:
+
+..\include\core/itoa.h:
+
+..\include\core/sam.h:
+
+..\include\core/samd.h:
+
+..\include\core/samd21/include/samd21.h:
+
+..\include\core/samd21/include/samd21g18a.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h:
+
+..\include\core/samd21/include/system_samd21.h:
+
+..\include\core/samd21/include/component/ac.h:
+
+..\include\core/samd21/include/component/adc.h:
+
+..\include\core/samd21/include/component/dac.h:
+
+..\include\core/samd21/include/component/dmac.h:
+
+..\include\core/samd21/include/component/dsu.h:
+
+..\include\core/samd21/include/component/eic.h:
+
+..\include\core/samd21/include/component/evsys.h:
+
+..\include\core/samd21/include/component/gclk.h:
+
+..\include\core/samd21/include/component/hmatrixb.h:
+
+..\include\core/samd21/include/component/i2s.h:
+
+..\include\core/samd21/include/component/mtb.h:
+
+..\include\core/samd21/include/component/nvmctrl.h:
+
+..\include\core/samd21/include/component/pac.h:
+
+..\include\core/samd21/include/component/pm.h:
+
+..\include\core/samd21/include/component/port.h:
+
+..\include\core/samd21/include/component/rtc.h:
+
+..\include\core/samd21/include/component/sercom.h:
+
+..\include\core/samd21/include/component/sysctrl.h:
+
+..\include\core/samd21/include/component/tc.h:
+
+..\include\core/samd21/include/component/tcc.h:
+
+..\include\core/samd21/include/component/usb.h:
+
+..\include\core/samd21/include/component/wdt.h:
+
+..\include\core/samd21/include/instance/ac.h:
+
+..\include\core/samd21/include/instance/adc.h:
+
+..\include\core/samd21/include/instance/dac.h:
+
+..\include\core/samd21/include/instance/dmac.h:
+
+..\include\core/samd21/include/instance/dsu.h:
+
+..\include\core/samd21/include/instance/eic.h:
+
+..\include\core/samd21/include/instance/evsys.h:
+
+..\include\core/samd21/include/instance/gclk.h:
+
+..\include\core/samd21/include/instance/sbmatrix.h:
+
+..\include\core/samd21/include/instance/i2s.h:
+
+..\include\core/samd21/include/instance/mtb.h:
+
+..\include\core/samd21/include/instance/nvmctrl.h:
+
+..\include\core/samd21/include/instance/pac0.h:
+
+..\include\core/samd21/include/instance/pac1.h:
+
+..\include\core/samd21/include/instance/pac2.h:
+
+..\include\core/samd21/include/instance/pm.h:
+
+..\include\core/samd21/include/instance/port.h:
+
+..\include\core/samd21/include/instance/rtc.h:
+
+..\include\core/samd21/include/instance/sercom0.h:
+
+..\include\core/samd21/include/instance/sercom1.h:
+
+..\include\core/samd21/include/instance/sercom2.h:
+
+..\include\core/samd21/include/instance/sercom3.h:
+
+..\include\core/samd21/include/instance/sercom4.h:
+
+..\include\core/samd21/include/instance/sercom5.h:
+
+..\include\core/samd21/include/instance/sysctrl.h:
+
+..\include\core/samd21/include/instance/tc3.h:
+
+..\include\core/samd21/include/instance/tc4.h:
+
+..\include\core/samd21/include/instance/tc5.h:
+
+..\include\core/samd21/include/instance/tcc0.h:
+
+..\include\core/samd21/include/instance/tcc1.h:
+
+..\include\core/samd21/include/instance/tcc2.h:
+
+..\include\core/samd21/include/instance/usb.h:
+
+..\include\core/samd21/include/instance/wdt.h:
+
+..\include\core/samd21/include/pio/samd21g18a.h:
+
+..\include\core/wiring_constants.h:
+
+..\include\core/WVariant.h:
+
+..\include\core/WCharacter.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\ctype.h:
+
+..\include\core/WString.h:
+
+..\include\core/avr/pgmspace.h:
+
+..\include\core/Tone.h:
+
+..\include\core/Arduino.h:
+
+..\include\core/WMath.h:
+
+..\include\core/HardwareSerial.h:
+
+..\include\core/Stream.h:
+
+..\include\core/Print.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
+
+..\include\core/Printable.h:
+
+..\include\core/pulse.h:
+
+..\include\core/delay.h:
+
+..\include\variants/variant.h:
+
+..\include\core/SERCOM.h:
+
+..\include\core/Uart.h:
+
+..\include\core/SERCOM.h:
+
+..\include\core/RingBuffer.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cstddef:
+
+..\include\core/wiring.h:
+
+..\include\core/wiring_digital.h:
+
+..\include\core/wiring_analog.h:
+
+..\include\core/wiring_shift.h:
+
+..\include\core/WInterrupts.h:
+
+..\include\core/USB/USBDesc.h:
+
+..\include\core/USB/USBCore.h:
+
+..\include\core/USB/USBAPI.h:
+
+..\include\core/Stream.h:
+
+..\include\core/RingBuffer.h:
+
+..\include\core/USB/USB_host.h:
+
+..\include\core/USB/samd21_host.h:
+
+..\include\core/USB/CDC.h:
+
+..\include\core/USB/USBDesc.h:
+
+..\include\core/USB/PluggableUSB.h:
diff --git a/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/main.o b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/main.o
new file mode 100644
index 0000000000000000000000000000000000000000..2d2e7aeacd675220e5483851acdc9a32151f61d7
Binary files /dev/null and b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/main.o differ
diff --git a/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/new.d b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/new.d
new file mode 100644
index 0000000000000000000000000000000000000000..5f482c3203c83bfe5979d0ac8791d22155b573e9
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/new.d
@@ -0,0 +1,67 @@
+src/core/new.d src/core/new.o: ../src/core/new.cpp \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cstdlib \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\c++config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\os_defines.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\cpu_defines.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cstdlib:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\c++config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\os_defines.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\cpu_defines.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
diff --git a/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/new.o b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/new.o
new file mode 100644
index 0000000000000000000000000000000000000000..1887f48ee063eeb2b247d3b25f95945da578df6f
Binary files /dev/null and b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/new.o differ
diff --git a/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/pulse.d b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/pulse.d
new file mode 100644
index 0000000000000000000000000000000000000000..820673b466a38c0b3af9addac4eb31a40366f707
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/pulse.d
@@ -0,0 +1,326 @@
+src/core/pulse.d src/core/pulse.o: ../src/core/pulse.c \
+ ..\include\core/Arduino.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\string.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\xlocale.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\string.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\math.h \
+ ..\include\core/avr/pgmspace.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\inttypes.h \
+ ..\include\core/avr/interrupt.h ..\include\core/avr/io.h \
+ ..\include\core/binary.h ..\include\core/itoa.h ..\include\core/sam.h \
+ ..\include\core/samd.h ..\include\core/samd21/include/samd21.h \
+ ..\include\core/samd21/include/samd21g18a.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h \
+ ..\include\core/samd21/include/system_samd21.h \
+ ..\include\core/samd21/include/component/ac.h \
+ ..\include\core/samd21/include/component/adc.h \
+ ..\include\core/samd21/include/component/dac.h \
+ ..\include\core/samd21/include/component/dmac.h \
+ ..\include\core/samd21/include/component/dsu.h \
+ ..\include\core/samd21/include/component/eic.h \
+ ..\include\core/samd21/include/component/evsys.h \
+ ..\include\core/samd21/include/component/gclk.h \
+ ..\include\core/samd21/include/component/hmatrixb.h \
+ ..\include\core/samd21/include/component/i2s.h \
+ ..\include\core/samd21/include/component/mtb.h \
+ ..\include\core/samd21/include/component/nvmctrl.h \
+ ..\include\core/samd21/include/component/pac.h \
+ ..\include\core/samd21/include/component/pm.h \
+ ..\include\core/samd21/include/component/port.h \
+ ..\include\core/samd21/include/component/rtc.h \
+ ..\include\core/samd21/include/component/sercom.h \
+ ..\include\core/samd21/include/component/sysctrl.h \
+ ..\include\core/samd21/include/component/tc.h \
+ ..\include\core/samd21/include/component/tcc.h \
+ ..\include\core/samd21/include/component/usb.h \
+ ..\include\core/samd21/include/component/wdt.h \
+ ..\include\core/samd21/include/instance/ac.h \
+ ..\include\core/samd21/include/instance/adc.h \
+ ..\include\core/samd21/include/instance/dac.h \
+ ..\include\core/samd21/include/instance/dmac.h \
+ ..\include\core/samd21/include/instance/dsu.h \
+ ..\include\core/samd21/include/instance/eic.h \
+ ..\include\core/samd21/include/instance/evsys.h \
+ ..\include\core/samd21/include/instance/gclk.h \
+ ..\include\core/samd21/include/instance/sbmatrix.h \
+ ..\include\core/samd21/include/instance/i2s.h \
+ ..\include\core/samd21/include/instance/mtb.h \
+ ..\include\core/samd21/include/instance/nvmctrl.h \
+ ..\include\core/samd21/include/instance/pac0.h \
+ ..\include\core/samd21/include/instance/pac1.h \
+ ..\include\core/samd21/include/instance/pac2.h \
+ ..\include\core/samd21/include/instance/pm.h \
+ ..\include\core/samd21/include/instance/port.h \
+ ..\include\core/samd21/include/instance/rtc.h \
+ ..\include\core/samd21/include/instance/sercom0.h \
+ ..\include\core/samd21/include/instance/sercom1.h \
+ ..\include\core/samd21/include/instance/sercom2.h \
+ ..\include\core/samd21/include/instance/sercom3.h \
+ ..\include\core/samd21/include/instance/sercom4.h \
+ ..\include\core/samd21/include/instance/sercom5.h \
+ ..\include\core/samd21/include/instance/sysctrl.h \
+ ..\include\core/samd21/include/instance/tc3.h \
+ ..\include\core/samd21/include/instance/tc4.h \
+ ..\include\core/samd21/include/instance/tc5.h \
+ ..\include\core/samd21/include/instance/tcc0.h \
+ ..\include\core/samd21/include/instance/tcc1.h \
+ ..\include\core/samd21/include/instance/tcc2.h \
+ ..\include\core/samd21/include/instance/usb.h \
+ ..\include\core/samd21/include/instance/wdt.h \
+ ..\include\core/samd21/include/pio/samd21g18a.h \
+ ..\include\core/wiring_constants.h ..\include\core/WVariant.h \
+ ..\include\core/delay.h ..\include\variants/variant.h \
+ ..\include\core/wiring.h ..\include\core/wiring_digital.h \
+ ..\include\core/wiring_analog.h ..\include\core/wiring_shift.h \
+ ..\include\core/WInterrupts.h ..\include\core/USB/USBDesc.h \
+ ..\include\core/USB/USBCore.h ..\include\core/USB/USBAPI.h \
+ ..\include\core/USB/USB_host.h ..\include\core/USB/samd21_host.h
+
+..\include\core/Arduino.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\string.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\xlocale.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\string.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\math.h:
+
+..\include\core/avr/pgmspace.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\inttypes.h:
+
+..\include\core/avr/interrupt.h:
+
+..\include\core/avr/io.h:
+
+..\include\core/binary.h:
+
+..\include\core/itoa.h:
+
+..\include\core/sam.h:
+
+..\include\core/samd.h:
+
+..\include\core/samd21/include/samd21.h:
+
+..\include\core/samd21/include/samd21g18a.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h:
+
+..\include\core/samd21/include/system_samd21.h:
+
+..\include\core/samd21/include/component/ac.h:
+
+..\include\core/samd21/include/component/adc.h:
+
+..\include\core/samd21/include/component/dac.h:
+
+..\include\core/samd21/include/component/dmac.h:
+
+..\include\core/samd21/include/component/dsu.h:
+
+..\include\core/samd21/include/component/eic.h:
+
+..\include\core/samd21/include/component/evsys.h:
+
+..\include\core/samd21/include/component/gclk.h:
+
+..\include\core/samd21/include/component/hmatrixb.h:
+
+..\include\core/samd21/include/component/i2s.h:
+
+..\include\core/samd21/include/component/mtb.h:
+
+..\include\core/samd21/include/component/nvmctrl.h:
+
+..\include\core/samd21/include/component/pac.h:
+
+..\include\core/samd21/include/component/pm.h:
+
+..\include\core/samd21/include/component/port.h:
+
+..\include\core/samd21/include/component/rtc.h:
+
+..\include\core/samd21/include/component/sercom.h:
+
+..\include\core/samd21/include/component/sysctrl.h:
+
+..\include\core/samd21/include/component/tc.h:
+
+..\include\core/samd21/include/component/tcc.h:
+
+..\include\core/samd21/include/component/usb.h:
+
+..\include\core/samd21/include/component/wdt.h:
+
+..\include\core/samd21/include/instance/ac.h:
+
+..\include\core/samd21/include/instance/adc.h:
+
+..\include\core/samd21/include/instance/dac.h:
+
+..\include\core/samd21/include/instance/dmac.h:
+
+..\include\core/samd21/include/instance/dsu.h:
+
+..\include\core/samd21/include/instance/eic.h:
+
+..\include\core/samd21/include/instance/evsys.h:
+
+..\include\core/samd21/include/instance/gclk.h:
+
+..\include\core/samd21/include/instance/sbmatrix.h:
+
+..\include\core/samd21/include/instance/i2s.h:
+
+..\include\core/samd21/include/instance/mtb.h:
+
+..\include\core/samd21/include/instance/nvmctrl.h:
+
+..\include\core/samd21/include/instance/pac0.h:
+
+..\include\core/samd21/include/instance/pac1.h:
+
+..\include\core/samd21/include/instance/pac2.h:
+
+..\include\core/samd21/include/instance/pm.h:
+
+..\include\core/samd21/include/instance/port.h:
+
+..\include\core/samd21/include/instance/rtc.h:
+
+..\include\core/samd21/include/instance/sercom0.h:
+
+..\include\core/samd21/include/instance/sercom1.h:
+
+..\include\core/samd21/include/instance/sercom2.h:
+
+..\include\core/samd21/include/instance/sercom3.h:
+
+..\include\core/samd21/include/instance/sercom4.h:
+
+..\include\core/samd21/include/instance/sercom5.h:
+
+..\include\core/samd21/include/instance/sysctrl.h:
+
+..\include\core/samd21/include/instance/tc3.h:
+
+..\include\core/samd21/include/instance/tc4.h:
+
+..\include\core/samd21/include/instance/tc5.h:
+
+..\include\core/samd21/include/instance/tcc0.h:
+
+..\include\core/samd21/include/instance/tcc1.h:
+
+..\include\core/samd21/include/instance/tcc2.h:
+
+..\include\core/samd21/include/instance/usb.h:
+
+..\include\core/samd21/include/instance/wdt.h:
+
+..\include\core/samd21/include/pio/samd21g18a.h:
+
+..\include\core/wiring_constants.h:
+
+..\include\core/WVariant.h:
+
+..\include\core/delay.h:
+
+..\include\variants/variant.h:
+
+..\include\core/wiring.h:
+
+..\include\core/wiring_digital.h:
+
+..\include\core/wiring_analog.h:
+
+..\include\core/wiring_shift.h:
+
+..\include\core/WInterrupts.h:
+
+..\include\core/USB/USBDesc.h:
+
+..\include\core/USB/USBCore.h:
+
+..\include\core/USB/USBAPI.h:
+
+..\include\core/USB/USB_host.h:
+
+..\include\core/USB/samd21_host.h:
diff --git a/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/pulse.o b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/pulse.o
new file mode 100644
index 0000000000000000000000000000000000000000..035cf9894609003dc88eb3b022d3a10cd862549b
Binary files /dev/null and b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/pulse.o differ
diff --git a/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/pulse_asm.d b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/pulse_asm.d
new file mode 100644
index 0000000000000000000000000000000000000000..e05b9d94ea53fa1fcf9bf367773e1082de070513
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/pulse_asm.d
@@ -0,0 +1 @@
+src/core/pulse_asm.d src/core/pulse_asm.o: ../src/core/pulse_asm.S
diff --git a/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/pulse_asm.o b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/pulse_asm.o
new file mode 100644
index 0000000000000000000000000000000000000000..5db8ad729ced4064a8157c357bb164e5dbff2fe0
Binary files /dev/null and b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/pulse_asm.o differ
diff --git a/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/startup.d b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/startup.d
new file mode 100644
index 0000000000000000000000000000000000000000..b06bd2096963ecf1e4fa175973f51afd924d46f5
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/startup.d
@@ -0,0 +1,296 @@
+src/core/startup.d src/core/startup.o: ../src/core/startup.c \
+ ..\include\core/sam.h ..\include\core/samd.h \
+ ..\include\core/samd21/include/samd21.h \
+ ..\include\core/samd21/include/samd21g18a.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h \
+ ..\include\core/samd21/include/system_samd21.h \
+ ..\include\core/samd21/include/component/ac.h \
+ ..\include\core/samd21/include/component/adc.h \
+ ..\include\core/samd21/include/component/dac.h \
+ ..\include\core/samd21/include/component/dmac.h \
+ ..\include\core/samd21/include/component/dsu.h \
+ ..\include\core/samd21/include/component/eic.h \
+ ..\include\core/samd21/include/component/evsys.h \
+ ..\include\core/samd21/include/component/gclk.h \
+ ..\include\core/samd21/include/component/hmatrixb.h \
+ ..\include\core/samd21/include/component/i2s.h \
+ ..\include\core/samd21/include/component/mtb.h \
+ ..\include\core/samd21/include/component/nvmctrl.h \
+ ..\include\core/samd21/include/component/pac.h \
+ ..\include\core/samd21/include/component/pm.h \
+ ..\include\core/samd21/include/component/port.h \
+ ..\include\core/samd21/include/component/rtc.h \
+ ..\include\core/samd21/include/component/sercom.h \
+ ..\include\core/samd21/include/component/sysctrl.h \
+ ..\include\core/samd21/include/component/tc.h \
+ ..\include\core/samd21/include/component/tcc.h \
+ ..\include\core/samd21/include/component/usb.h \
+ ..\include\core/samd21/include/component/wdt.h \
+ ..\include\core/samd21/include/instance/ac.h \
+ ..\include\core/samd21/include/instance/adc.h \
+ ..\include\core/samd21/include/instance/dac.h \
+ ..\include\core/samd21/include/instance/dmac.h \
+ ..\include\core/samd21/include/instance/dsu.h \
+ ..\include\core/samd21/include/instance/eic.h \
+ ..\include\core/samd21/include/instance/evsys.h \
+ ..\include\core/samd21/include/instance/gclk.h \
+ ..\include\core/samd21/include/instance/sbmatrix.h \
+ ..\include\core/samd21/include/instance/i2s.h \
+ ..\include\core/samd21/include/instance/mtb.h \
+ ..\include\core/samd21/include/instance/nvmctrl.h \
+ ..\include\core/samd21/include/instance/pac0.h \
+ ..\include\core/samd21/include/instance/pac1.h \
+ ..\include\core/samd21/include/instance/pac2.h \
+ ..\include\core/samd21/include/instance/pm.h \
+ ..\include\core/samd21/include/instance/port.h \
+ ..\include\core/samd21/include/instance/rtc.h \
+ ..\include\core/samd21/include/instance/sercom0.h \
+ ..\include\core/samd21/include/instance/sercom1.h \
+ ..\include\core/samd21/include/instance/sercom2.h \
+ ..\include\core/samd21/include/instance/sercom3.h \
+ ..\include\core/samd21/include/instance/sercom4.h \
+ ..\include\core/samd21/include/instance/sercom5.h \
+ ..\include\core/samd21/include/instance/sysctrl.h \
+ ..\include\core/samd21/include/instance/tc3.h \
+ ..\include\core/samd21/include/instance/tc4.h \
+ ..\include\core/samd21/include/instance/tc5.h \
+ ..\include\core/samd21/include/instance/tcc0.h \
+ ..\include\core/samd21/include/instance/tcc1.h \
+ ..\include\core/samd21/include/instance/tcc2.h \
+ ..\include\core/samd21/include/instance/usb.h \
+ ..\include\core/samd21/include/instance/wdt.h \
+ ..\include\core/samd21/include/pio/samd21g18a.h \
+ ..\include\variants/variant.h ..\include\core/WVariant.h \
+ ..\include\core/sam.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h
+
+..\include\core/sam.h:
+
+..\include\core/samd.h:
+
+..\include\core/samd21/include/samd21.h:
+
+..\include\core/samd21/include/samd21g18a.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h:
+
+..\include\core/samd21/include/system_samd21.h:
+
+..\include\core/samd21/include/component/ac.h:
+
+..\include\core/samd21/include/component/adc.h:
+
+..\include\core/samd21/include/component/dac.h:
+
+..\include\core/samd21/include/component/dmac.h:
+
+..\include\core/samd21/include/component/dsu.h:
+
+..\include\core/samd21/include/component/eic.h:
+
+..\include\core/samd21/include/component/evsys.h:
+
+..\include\core/samd21/include/component/gclk.h:
+
+..\include\core/samd21/include/component/hmatrixb.h:
+
+..\include\core/samd21/include/component/i2s.h:
+
+..\include\core/samd21/include/component/mtb.h:
+
+..\include\core/samd21/include/component/nvmctrl.h:
+
+..\include\core/samd21/include/component/pac.h:
+
+..\include\core/samd21/include/component/pm.h:
+
+..\include\core/samd21/include/component/port.h:
+
+..\include\core/samd21/include/component/rtc.h:
+
+..\include\core/samd21/include/component/sercom.h:
+
+..\include\core/samd21/include/component/sysctrl.h:
+
+..\include\core/samd21/include/component/tc.h:
+
+..\include\core/samd21/include/component/tcc.h:
+
+..\include\core/samd21/include/component/usb.h:
+
+..\include\core/samd21/include/component/wdt.h:
+
+..\include\core/samd21/include/instance/ac.h:
+
+..\include\core/samd21/include/instance/adc.h:
+
+..\include\core/samd21/include/instance/dac.h:
+
+..\include\core/samd21/include/instance/dmac.h:
+
+..\include\core/samd21/include/instance/dsu.h:
+
+..\include\core/samd21/include/instance/eic.h:
+
+..\include\core/samd21/include/instance/evsys.h:
+
+..\include\core/samd21/include/instance/gclk.h:
+
+..\include\core/samd21/include/instance/sbmatrix.h:
+
+..\include\core/samd21/include/instance/i2s.h:
+
+..\include\core/samd21/include/instance/mtb.h:
+
+..\include\core/samd21/include/instance/nvmctrl.h:
+
+..\include\core/samd21/include/instance/pac0.h:
+
+..\include\core/samd21/include/instance/pac1.h:
+
+..\include\core/samd21/include/instance/pac2.h:
+
+..\include\core/samd21/include/instance/pm.h:
+
+..\include\core/samd21/include/instance/port.h:
+
+..\include\core/samd21/include/instance/rtc.h:
+
+..\include\core/samd21/include/instance/sercom0.h:
+
+..\include\core/samd21/include/instance/sercom1.h:
+
+..\include\core/samd21/include/instance/sercom2.h:
+
+..\include\core/samd21/include/instance/sercom3.h:
+
+..\include\core/samd21/include/instance/sercom4.h:
+
+..\include\core/samd21/include/instance/sercom5.h:
+
+..\include\core/samd21/include/instance/sysctrl.h:
+
+..\include\core/samd21/include/instance/tc3.h:
+
+..\include\core/samd21/include/instance/tc4.h:
+
+..\include\core/samd21/include/instance/tc5.h:
+
+..\include\core/samd21/include/instance/tcc0.h:
+
+..\include\core/samd21/include/instance/tcc1.h:
+
+..\include\core/samd21/include/instance/tcc2.h:
+
+..\include\core/samd21/include/instance/usb.h:
+
+..\include\core/samd21/include/instance/wdt.h:
+
+..\include\core/samd21/include/pio/samd21g18a.h:
+
+..\include\variants/variant.h:
+
+..\include\core/WVariant.h:
+
+..\include\core/sam.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
diff --git a/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/startup.o b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/startup.o
new file mode 100644
index 0000000000000000000000000000000000000000..f324d756cb227a71043accedcdb6e0404241a185
Binary files /dev/null and b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/startup.o differ
diff --git a/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/wiring.d b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/wiring.d
new file mode 100644
index 0000000000000000000000000000000000000000..850586cf82a00b94724f1db69a6f9e5f0587455b
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/wiring.d
@@ -0,0 +1,326 @@
+src/core/wiring.d src/core/wiring.o: ../src/core/wiring.c \
+ ..\include\core/Arduino.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\string.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\xlocale.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\string.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\math.h \
+ ..\include\core/avr/pgmspace.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\inttypes.h \
+ ..\include\core/avr/interrupt.h ..\include\core/avr/io.h \
+ ..\include\core/binary.h ..\include\core/itoa.h ..\include\core/sam.h \
+ ..\include\core/samd.h ..\include\core/samd21/include/samd21.h \
+ ..\include\core/samd21/include/samd21g18a.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h \
+ ..\include\core/samd21/include/system_samd21.h \
+ ..\include\core/samd21/include/component/ac.h \
+ ..\include\core/samd21/include/component/adc.h \
+ ..\include\core/samd21/include/component/dac.h \
+ ..\include\core/samd21/include/component/dmac.h \
+ ..\include\core/samd21/include/component/dsu.h \
+ ..\include\core/samd21/include/component/eic.h \
+ ..\include\core/samd21/include/component/evsys.h \
+ ..\include\core/samd21/include/component/gclk.h \
+ ..\include\core/samd21/include/component/hmatrixb.h \
+ ..\include\core/samd21/include/component/i2s.h \
+ ..\include\core/samd21/include/component/mtb.h \
+ ..\include\core/samd21/include/component/nvmctrl.h \
+ ..\include\core/samd21/include/component/pac.h \
+ ..\include\core/samd21/include/component/pm.h \
+ ..\include\core/samd21/include/component/port.h \
+ ..\include\core/samd21/include/component/rtc.h \
+ ..\include\core/samd21/include/component/sercom.h \
+ ..\include\core/samd21/include/component/sysctrl.h \
+ ..\include\core/samd21/include/component/tc.h \
+ ..\include\core/samd21/include/component/tcc.h \
+ ..\include\core/samd21/include/component/usb.h \
+ ..\include\core/samd21/include/component/wdt.h \
+ ..\include\core/samd21/include/instance/ac.h \
+ ..\include\core/samd21/include/instance/adc.h \
+ ..\include\core/samd21/include/instance/dac.h \
+ ..\include\core/samd21/include/instance/dmac.h \
+ ..\include\core/samd21/include/instance/dsu.h \
+ ..\include\core/samd21/include/instance/eic.h \
+ ..\include\core/samd21/include/instance/evsys.h \
+ ..\include\core/samd21/include/instance/gclk.h \
+ ..\include\core/samd21/include/instance/sbmatrix.h \
+ ..\include\core/samd21/include/instance/i2s.h \
+ ..\include\core/samd21/include/instance/mtb.h \
+ ..\include\core/samd21/include/instance/nvmctrl.h \
+ ..\include\core/samd21/include/instance/pac0.h \
+ ..\include\core/samd21/include/instance/pac1.h \
+ ..\include\core/samd21/include/instance/pac2.h \
+ ..\include\core/samd21/include/instance/pm.h \
+ ..\include\core/samd21/include/instance/port.h \
+ ..\include\core/samd21/include/instance/rtc.h \
+ ..\include\core/samd21/include/instance/sercom0.h \
+ ..\include\core/samd21/include/instance/sercom1.h \
+ ..\include\core/samd21/include/instance/sercom2.h \
+ ..\include\core/samd21/include/instance/sercom3.h \
+ ..\include\core/samd21/include/instance/sercom4.h \
+ ..\include\core/samd21/include/instance/sercom5.h \
+ ..\include\core/samd21/include/instance/sysctrl.h \
+ ..\include\core/samd21/include/instance/tc3.h \
+ ..\include\core/samd21/include/instance/tc4.h \
+ ..\include\core/samd21/include/instance/tc5.h \
+ ..\include\core/samd21/include/instance/tcc0.h \
+ ..\include\core/samd21/include/instance/tcc1.h \
+ ..\include\core/samd21/include/instance/tcc2.h \
+ ..\include\core/samd21/include/instance/usb.h \
+ ..\include\core/samd21/include/instance/wdt.h \
+ ..\include\core/samd21/include/pio/samd21g18a.h \
+ ..\include\core/wiring_constants.h ..\include\core/WVariant.h \
+ ..\include\core/delay.h ..\include\variants/variant.h \
+ ..\include\core/wiring.h ..\include\core/wiring_digital.h \
+ ..\include\core/wiring_analog.h ..\include\core/wiring_shift.h \
+ ..\include\core/WInterrupts.h ..\include\core/USB/USBDesc.h \
+ ..\include\core/USB/USBCore.h ..\include\core/USB/USBAPI.h \
+ ..\include\core/USB/USB_host.h ..\include\core/USB/samd21_host.h
+
+..\include\core/Arduino.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\string.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\xlocale.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\string.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\math.h:
+
+..\include\core/avr/pgmspace.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\inttypes.h:
+
+..\include\core/avr/interrupt.h:
+
+..\include\core/avr/io.h:
+
+..\include\core/binary.h:
+
+..\include\core/itoa.h:
+
+..\include\core/sam.h:
+
+..\include\core/samd.h:
+
+..\include\core/samd21/include/samd21.h:
+
+..\include\core/samd21/include/samd21g18a.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h:
+
+..\include\core/samd21/include/system_samd21.h:
+
+..\include\core/samd21/include/component/ac.h:
+
+..\include\core/samd21/include/component/adc.h:
+
+..\include\core/samd21/include/component/dac.h:
+
+..\include\core/samd21/include/component/dmac.h:
+
+..\include\core/samd21/include/component/dsu.h:
+
+..\include\core/samd21/include/component/eic.h:
+
+..\include\core/samd21/include/component/evsys.h:
+
+..\include\core/samd21/include/component/gclk.h:
+
+..\include\core/samd21/include/component/hmatrixb.h:
+
+..\include\core/samd21/include/component/i2s.h:
+
+..\include\core/samd21/include/component/mtb.h:
+
+..\include\core/samd21/include/component/nvmctrl.h:
+
+..\include\core/samd21/include/component/pac.h:
+
+..\include\core/samd21/include/component/pm.h:
+
+..\include\core/samd21/include/component/port.h:
+
+..\include\core/samd21/include/component/rtc.h:
+
+..\include\core/samd21/include/component/sercom.h:
+
+..\include\core/samd21/include/component/sysctrl.h:
+
+..\include\core/samd21/include/component/tc.h:
+
+..\include\core/samd21/include/component/tcc.h:
+
+..\include\core/samd21/include/component/usb.h:
+
+..\include\core/samd21/include/component/wdt.h:
+
+..\include\core/samd21/include/instance/ac.h:
+
+..\include\core/samd21/include/instance/adc.h:
+
+..\include\core/samd21/include/instance/dac.h:
+
+..\include\core/samd21/include/instance/dmac.h:
+
+..\include\core/samd21/include/instance/dsu.h:
+
+..\include\core/samd21/include/instance/eic.h:
+
+..\include\core/samd21/include/instance/evsys.h:
+
+..\include\core/samd21/include/instance/gclk.h:
+
+..\include\core/samd21/include/instance/sbmatrix.h:
+
+..\include\core/samd21/include/instance/i2s.h:
+
+..\include\core/samd21/include/instance/mtb.h:
+
+..\include\core/samd21/include/instance/nvmctrl.h:
+
+..\include\core/samd21/include/instance/pac0.h:
+
+..\include\core/samd21/include/instance/pac1.h:
+
+..\include\core/samd21/include/instance/pac2.h:
+
+..\include\core/samd21/include/instance/pm.h:
+
+..\include\core/samd21/include/instance/port.h:
+
+..\include\core/samd21/include/instance/rtc.h:
+
+..\include\core/samd21/include/instance/sercom0.h:
+
+..\include\core/samd21/include/instance/sercom1.h:
+
+..\include\core/samd21/include/instance/sercom2.h:
+
+..\include\core/samd21/include/instance/sercom3.h:
+
+..\include\core/samd21/include/instance/sercom4.h:
+
+..\include\core/samd21/include/instance/sercom5.h:
+
+..\include\core/samd21/include/instance/sysctrl.h:
+
+..\include\core/samd21/include/instance/tc3.h:
+
+..\include\core/samd21/include/instance/tc4.h:
+
+..\include\core/samd21/include/instance/tc5.h:
+
+..\include\core/samd21/include/instance/tcc0.h:
+
+..\include\core/samd21/include/instance/tcc1.h:
+
+..\include\core/samd21/include/instance/tcc2.h:
+
+..\include\core/samd21/include/instance/usb.h:
+
+..\include\core/samd21/include/instance/wdt.h:
+
+..\include\core/samd21/include/pio/samd21g18a.h:
+
+..\include\core/wiring_constants.h:
+
+..\include\core/WVariant.h:
+
+..\include\core/delay.h:
+
+..\include\variants/variant.h:
+
+..\include\core/wiring.h:
+
+..\include\core/wiring_digital.h:
+
+..\include\core/wiring_analog.h:
+
+..\include\core/wiring_shift.h:
+
+..\include\core/WInterrupts.h:
+
+..\include\core/USB/USBDesc.h:
+
+..\include\core/USB/USBCore.h:
+
+..\include\core/USB/USBAPI.h:
+
+..\include\core/USB/USB_host.h:
+
+..\include\core/USB/samd21_host.h:
diff --git a/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/wiring.o b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/wiring.o
new file mode 100644
index 0000000000000000000000000000000000000000..9828a4b5147ed8ea4d9de137bdedcaea92234142
Binary files /dev/null and b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/wiring.o differ
diff --git a/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/wiring_analog.d b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/wiring_analog.d
new file mode 100644
index 0000000000000000000000000000000000000000..1b47f328db778d3bfd9037cda88f0069ad829e06
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/wiring_analog.d
@@ -0,0 +1,368 @@
+src/core/wiring_analog.d src/core/wiring_analog.o: \
+ ../src/core/wiring_analog.c ..\include\core/Arduino.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\string.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\xlocale.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\string.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\math.h \
+ ..\include\core/avr/pgmspace.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\inttypes.h \
+ ..\include\core/avr/interrupt.h ..\include\core/avr/io.h \
+ ..\include\core/binary.h ..\include\core/itoa.h ..\include\core/sam.h \
+ ..\include\core/samd.h ..\include\core/samd21/include/samd21.h \
+ ..\include\core/samd21/include/samd21g18a.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h \
+ ..\include\core/samd21/include/system_samd21.h \
+ ..\include\core/samd21/include/component/ac.h \
+ ..\include\core/samd21/include/component/adc.h \
+ ..\include\core/samd21/include/component/dac.h \
+ ..\include\core/samd21/include/component/dmac.h \
+ ..\include\core/samd21/include/component/dsu.h \
+ ..\include\core/samd21/include/component/eic.h \
+ ..\include\core/samd21/include/component/evsys.h \
+ ..\include\core/samd21/include/component/gclk.h \
+ ..\include\core/samd21/include/component/hmatrixb.h \
+ ..\include\core/samd21/include/component/i2s.h \
+ ..\include\core/samd21/include/component/mtb.h \
+ ..\include\core/samd21/include/component/nvmctrl.h \
+ ..\include\core/samd21/include/component/pac.h \
+ ..\include\core/samd21/include/component/pm.h \
+ ..\include\core/samd21/include/component/port.h \
+ ..\include\core/samd21/include/component/rtc.h \
+ ..\include\core/samd21/include/component/sercom.h \
+ ..\include\core/samd21/include/component/sysctrl.h \
+ ..\include\core/samd21/include/component/tc.h \
+ ..\include\core/samd21/include/component/tcc.h \
+ ..\include\core/samd21/include/component/usb.h \
+ ..\include\core/samd21/include/component/wdt.h \
+ ..\include\core/samd21/include/instance/ac.h \
+ ..\include\core/samd21/include/instance/adc.h \
+ ..\include\core/samd21/include/instance/dac.h \
+ ..\include\core/samd21/include/instance/dmac.h \
+ ..\include\core/samd21/include/instance/dsu.h \
+ ..\include\core/samd21/include/instance/eic.h \
+ ..\include\core/samd21/include/instance/evsys.h \
+ ..\include\core/samd21/include/instance/gclk.h \
+ ..\include\core/samd21/include/instance/sbmatrix.h \
+ ..\include\core/samd21/include/instance/i2s.h \
+ ..\include\core/samd21/include/instance/mtb.h \
+ ..\include\core/samd21/include/instance/nvmctrl.h \
+ ..\include\core/samd21/include/instance/pac0.h \
+ ..\include\core/samd21/include/instance/pac1.h \
+ ..\include\core/samd21/include/instance/pac2.h \
+ ..\include\core/samd21/include/instance/pm.h \
+ ..\include\core/samd21/include/instance/port.h \
+ ..\include\core/samd21/include/instance/rtc.h \
+ ..\include\core/samd21/include/instance/sercom0.h \
+ ..\include\core/samd21/include/instance/sercom1.h \
+ ..\include\core/samd21/include/instance/sercom2.h \
+ ..\include\core/samd21/include/instance/sercom3.h \
+ ..\include\core/samd21/include/instance/sercom4.h \
+ ..\include\core/samd21/include/instance/sercom5.h \
+ ..\include\core/samd21/include/instance/sysctrl.h \
+ ..\include\core/samd21/include/instance/tc3.h \
+ ..\include\core/samd21/include/instance/tc4.h \
+ ..\include\core/samd21/include/instance/tc5.h \
+ ..\include\core/samd21/include/instance/tcc0.h \
+ ..\include\core/samd21/include/instance/tcc1.h \
+ ..\include\core/samd21/include/instance/tcc2.h \
+ ..\include\core/samd21/include/instance/usb.h \
+ ..\include\core/samd21/include/instance/wdt.h \
+ ..\include\core/samd21/include/pio/samd21g18a.h \
+ ..\include\core/wiring_constants.h ..\include\core/WVariant.h \
+ ..\include\core/delay.h ..\include\variants/variant.h \
+ ..\include\core/wiring.h ..\include\core/wiring_digital.h \
+ ..\include\core/wiring_analog.h ..\include\core/wiring_shift.h \
+ ..\include\core/WInterrupts.h ..\include\core/USB/USBDesc.h \
+ ..\include\core/USB/USBCore.h ..\include\core/USB/USBAPI.h \
+ ..\include\core/USB/USB_host.h ..\include\core/USB/samd21_host.h \
+ ..\include\core/wiring_private.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h
+
+..\include\core/Arduino.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\string.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\xlocale.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\string.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\math.h:
+
+..\include\core/avr/pgmspace.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\inttypes.h:
+
+..\include\core/avr/interrupt.h:
+
+..\include\core/avr/io.h:
+
+..\include\core/binary.h:
+
+..\include\core/itoa.h:
+
+..\include\core/sam.h:
+
+..\include\core/samd.h:
+
+..\include\core/samd21/include/samd21.h:
+
+..\include\core/samd21/include/samd21g18a.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h:
+
+..\include\core/samd21/include/system_samd21.h:
+
+..\include\core/samd21/include/component/ac.h:
+
+..\include\core/samd21/include/component/adc.h:
+
+..\include\core/samd21/include/component/dac.h:
+
+..\include\core/samd21/include/component/dmac.h:
+
+..\include\core/samd21/include/component/dsu.h:
+
+..\include\core/samd21/include/component/eic.h:
+
+..\include\core/samd21/include/component/evsys.h:
+
+..\include\core/samd21/include/component/gclk.h:
+
+..\include\core/samd21/include/component/hmatrixb.h:
+
+..\include\core/samd21/include/component/i2s.h:
+
+..\include\core/samd21/include/component/mtb.h:
+
+..\include\core/samd21/include/component/nvmctrl.h:
+
+..\include\core/samd21/include/component/pac.h:
+
+..\include\core/samd21/include/component/pm.h:
+
+..\include\core/samd21/include/component/port.h:
+
+..\include\core/samd21/include/component/rtc.h:
+
+..\include\core/samd21/include/component/sercom.h:
+
+..\include\core/samd21/include/component/sysctrl.h:
+
+..\include\core/samd21/include/component/tc.h:
+
+..\include\core/samd21/include/component/tcc.h:
+
+..\include\core/samd21/include/component/usb.h:
+
+..\include\core/samd21/include/component/wdt.h:
+
+..\include\core/samd21/include/instance/ac.h:
+
+..\include\core/samd21/include/instance/adc.h:
+
+..\include\core/samd21/include/instance/dac.h:
+
+..\include\core/samd21/include/instance/dmac.h:
+
+..\include\core/samd21/include/instance/dsu.h:
+
+..\include\core/samd21/include/instance/eic.h:
+
+..\include\core/samd21/include/instance/evsys.h:
+
+..\include\core/samd21/include/instance/gclk.h:
+
+..\include\core/samd21/include/instance/sbmatrix.h:
+
+..\include\core/samd21/include/instance/i2s.h:
+
+..\include\core/samd21/include/instance/mtb.h:
+
+..\include\core/samd21/include/instance/nvmctrl.h:
+
+..\include\core/samd21/include/instance/pac0.h:
+
+..\include\core/samd21/include/instance/pac1.h:
+
+..\include\core/samd21/include/instance/pac2.h:
+
+..\include\core/samd21/include/instance/pm.h:
+
+..\include\core/samd21/include/instance/port.h:
+
+..\include\core/samd21/include/instance/rtc.h:
+
+..\include\core/samd21/include/instance/sercom0.h:
+
+..\include\core/samd21/include/instance/sercom1.h:
+
+..\include\core/samd21/include/instance/sercom2.h:
+
+..\include\core/samd21/include/instance/sercom3.h:
+
+..\include\core/samd21/include/instance/sercom4.h:
+
+..\include\core/samd21/include/instance/sercom5.h:
+
+..\include\core/samd21/include/instance/sysctrl.h:
+
+..\include\core/samd21/include/instance/tc3.h:
+
+..\include\core/samd21/include/instance/tc4.h:
+
+..\include\core/samd21/include/instance/tc5.h:
+
+..\include\core/samd21/include/instance/tcc0.h:
+
+..\include\core/samd21/include/instance/tcc1.h:
+
+..\include\core/samd21/include/instance/tcc2.h:
+
+..\include\core/samd21/include/instance/usb.h:
+
+..\include\core/samd21/include/instance/wdt.h:
+
+..\include\core/samd21/include/pio/samd21g18a.h:
+
+..\include\core/wiring_constants.h:
+
+..\include\core/WVariant.h:
+
+..\include\core/delay.h:
+
+..\include\variants/variant.h:
+
+..\include\core/wiring.h:
+
+..\include\core/wiring_digital.h:
+
+..\include\core/wiring_analog.h:
+
+..\include\core/wiring_shift.h:
+
+..\include\core/WInterrupts.h:
+
+..\include\core/USB/USBDesc.h:
+
+..\include\core/USB/USBCore.h:
+
+..\include\core/USB/USBAPI.h:
+
+..\include\core/USB/USB_host.h:
+
+..\include\core/USB/samd21_host.h:
+
+..\include\core/wiring_private.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
diff --git a/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/wiring_analog.o b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/wiring_analog.o
new file mode 100644
index 0000000000000000000000000000000000000000..1a224409b623450bee552ecea91a285778bd1c10
Binary files /dev/null and b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/wiring_analog.o differ
diff --git a/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/wiring_digital.d b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/wiring_digital.d
new file mode 100644
index 0000000000000000000000000000000000000000..b3079ae31be41877919466055b67ec58b9f54e7b
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/wiring_digital.d
@@ -0,0 +1,326 @@
+src/core/wiring_digital.d src/core/wiring_digital.o: \
+ ../src/core/wiring_digital.c ..\include\core/Arduino.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\string.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\xlocale.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\string.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\math.h \
+ ..\include\core/avr/pgmspace.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\inttypes.h \
+ ..\include\core/avr/interrupt.h ..\include\core/avr/io.h \
+ ..\include\core/binary.h ..\include\core/itoa.h ..\include\core/sam.h \
+ ..\include\core/samd.h ..\include\core/samd21/include/samd21.h \
+ ..\include\core/samd21/include/samd21g18a.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h \
+ ..\include\core/samd21/include/system_samd21.h \
+ ..\include\core/samd21/include/component/ac.h \
+ ..\include\core/samd21/include/component/adc.h \
+ ..\include\core/samd21/include/component/dac.h \
+ ..\include\core/samd21/include/component/dmac.h \
+ ..\include\core/samd21/include/component/dsu.h \
+ ..\include\core/samd21/include/component/eic.h \
+ ..\include\core/samd21/include/component/evsys.h \
+ ..\include\core/samd21/include/component/gclk.h \
+ ..\include\core/samd21/include/component/hmatrixb.h \
+ ..\include\core/samd21/include/component/i2s.h \
+ ..\include\core/samd21/include/component/mtb.h \
+ ..\include\core/samd21/include/component/nvmctrl.h \
+ ..\include\core/samd21/include/component/pac.h \
+ ..\include\core/samd21/include/component/pm.h \
+ ..\include\core/samd21/include/component/port.h \
+ ..\include\core/samd21/include/component/rtc.h \
+ ..\include\core/samd21/include/component/sercom.h \
+ ..\include\core/samd21/include/component/sysctrl.h \
+ ..\include\core/samd21/include/component/tc.h \
+ ..\include\core/samd21/include/component/tcc.h \
+ ..\include\core/samd21/include/component/usb.h \
+ ..\include\core/samd21/include/component/wdt.h \
+ ..\include\core/samd21/include/instance/ac.h \
+ ..\include\core/samd21/include/instance/adc.h \
+ ..\include\core/samd21/include/instance/dac.h \
+ ..\include\core/samd21/include/instance/dmac.h \
+ ..\include\core/samd21/include/instance/dsu.h \
+ ..\include\core/samd21/include/instance/eic.h \
+ ..\include\core/samd21/include/instance/evsys.h \
+ ..\include\core/samd21/include/instance/gclk.h \
+ ..\include\core/samd21/include/instance/sbmatrix.h \
+ ..\include\core/samd21/include/instance/i2s.h \
+ ..\include\core/samd21/include/instance/mtb.h \
+ ..\include\core/samd21/include/instance/nvmctrl.h \
+ ..\include\core/samd21/include/instance/pac0.h \
+ ..\include\core/samd21/include/instance/pac1.h \
+ ..\include\core/samd21/include/instance/pac2.h \
+ ..\include\core/samd21/include/instance/pm.h \
+ ..\include\core/samd21/include/instance/port.h \
+ ..\include\core/samd21/include/instance/rtc.h \
+ ..\include\core/samd21/include/instance/sercom0.h \
+ ..\include\core/samd21/include/instance/sercom1.h \
+ ..\include\core/samd21/include/instance/sercom2.h \
+ ..\include\core/samd21/include/instance/sercom3.h \
+ ..\include\core/samd21/include/instance/sercom4.h \
+ ..\include\core/samd21/include/instance/sercom5.h \
+ ..\include\core/samd21/include/instance/sysctrl.h \
+ ..\include\core/samd21/include/instance/tc3.h \
+ ..\include\core/samd21/include/instance/tc4.h \
+ ..\include\core/samd21/include/instance/tc5.h \
+ ..\include\core/samd21/include/instance/tcc0.h \
+ ..\include\core/samd21/include/instance/tcc1.h \
+ ..\include\core/samd21/include/instance/tcc2.h \
+ ..\include\core/samd21/include/instance/usb.h \
+ ..\include\core/samd21/include/instance/wdt.h \
+ ..\include\core/samd21/include/pio/samd21g18a.h \
+ ..\include\core/wiring_constants.h ..\include\core/WVariant.h \
+ ..\include\core/delay.h ..\include\variants/variant.h \
+ ..\include\core/wiring.h ..\include\core/wiring_digital.h \
+ ..\include\core/wiring_analog.h ..\include\core/wiring_shift.h \
+ ..\include\core/WInterrupts.h ..\include\core/USB/USBDesc.h \
+ ..\include\core/USB/USBCore.h ..\include\core/USB/USBAPI.h \
+ ..\include\core/USB/USB_host.h ..\include\core/USB/samd21_host.h
+
+..\include\core/Arduino.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\string.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\xlocale.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\string.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\math.h:
+
+..\include\core/avr/pgmspace.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\inttypes.h:
+
+..\include\core/avr/interrupt.h:
+
+..\include\core/avr/io.h:
+
+..\include\core/binary.h:
+
+..\include\core/itoa.h:
+
+..\include\core/sam.h:
+
+..\include\core/samd.h:
+
+..\include\core/samd21/include/samd21.h:
+
+..\include\core/samd21/include/samd21g18a.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h:
+
+..\include\core/samd21/include/system_samd21.h:
+
+..\include\core/samd21/include/component/ac.h:
+
+..\include\core/samd21/include/component/adc.h:
+
+..\include\core/samd21/include/component/dac.h:
+
+..\include\core/samd21/include/component/dmac.h:
+
+..\include\core/samd21/include/component/dsu.h:
+
+..\include\core/samd21/include/component/eic.h:
+
+..\include\core/samd21/include/component/evsys.h:
+
+..\include\core/samd21/include/component/gclk.h:
+
+..\include\core/samd21/include/component/hmatrixb.h:
+
+..\include\core/samd21/include/component/i2s.h:
+
+..\include\core/samd21/include/component/mtb.h:
+
+..\include\core/samd21/include/component/nvmctrl.h:
+
+..\include\core/samd21/include/component/pac.h:
+
+..\include\core/samd21/include/component/pm.h:
+
+..\include\core/samd21/include/component/port.h:
+
+..\include\core/samd21/include/component/rtc.h:
+
+..\include\core/samd21/include/component/sercom.h:
+
+..\include\core/samd21/include/component/sysctrl.h:
+
+..\include\core/samd21/include/component/tc.h:
+
+..\include\core/samd21/include/component/tcc.h:
+
+..\include\core/samd21/include/component/usb.h:
+
+..\include\core/samd21/include/component/wdt.h:
+
+..\include\core/samd21/include/instance/ac.h:
+
+..\include\core/samd21/include/instance/adc.h:
+
+..\include\core/samd21/include/instance/dac.h:
+
+..\include\core/samd21/include/instance/dmac.h:
+
+..\include\core/samd21/include/instance/dsu.h:
+
+..\include\core/samd21/include/instance/eic.h:
+
+..\include\core/samd21/include/instance/evsys.h:
+
+..\include\core/samd21/include/instance/gclk.h:
+
+..\include\core/samd21/include/instance/sbmatrix.h:
+
+..\include\core/samd21/include/instance/i2s.h:
+
+..\include\core/samd21/include/instance/mtb.h:
+
+..\include\core/samd21/include/instance/nvmctrl.h:
+
+..\include\core/samd21/include/instance/pac0.h:
+
+..\include\core/samd21/include/instance/pac1.h:
+
+..\include\core/samd21/include/instance/pac2.h:
+
+..\include\core/samd21/include/instance/pm.h:
+
+..\include\core/samd21/include/instance/port.h:
+
+..\include\core/samd21/include/instance/rtc.h:
+
+..\include\core/samd21/include/instance/sercom0.h:
+
+..\include\core/samd21/include/instance/sercom1.h:
+
+..\include\core/samd21/include/instance/sercom2.h:
+
+..\include\core/samd21/include/instance/sercom3.h:
+
+..\include\core/samd21/include/instance/sercom4.h:
+
+..\include\core/samd21/include/instance/sercom5.h:
+
+..\include\core/samd21/include/instance/sysctrl.h:
+
+..\include\core/samd21/include/instance/tc3.h:
+
+..\include\core/samd21/include/instance/tc4.h:
+
+..\include\core/samd21/include/instance/tc5.h:
+
+..\include\core/samd21/include/instance/tcc0.h:
+
+..\include\core/samd21/include/instance/tcc1.h:
+
+..\include\core/samd21/include/instance/tcc2.h:
+
+..\include\core/samd21/include/instance/usb.h:
+
+..\include\core/samd21/include/instance/wdt.h:
+
+..\include\core/samd21/include/pio/samd21g18a.h:
+
+..\include\core/wiring_constants.h:
+
+..\include\core/WVariant.h:
+
+..\include\core/delay.h:
+
+..\include\variants/variant.h:
+
+..\include\core/wiring.h:
+
+..\include\core/wiring_digital.h:
+
+..\include\core/wiring_analog.h:
+
+..\include\core/wiring_shift.h:
+
+..\include\core/WInterrupts.h:
+
+..\include\core/USB/USBDesc.h:
+
+..\include\core/USB/USBCore.h:
+
+..\include\core/USB/USBAPI.h:
+
+..\include\core/USB/USB_host.h:
+
+..\include\core/USB/samd21_host.h:
diff --git a/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/wiring_digital.o b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/wiring_digital.o
new file mode 100644
index 0000000000000000000000000000000000000000..d910312de32784d03f2dc4dd2b153d4a05788996
Binary files /dev/null and b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/wiring_digital.o differ
diff --git a/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/wiring_private.d b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/wiring_private.d
new file mode 100644
index 0000000000000000000000000000000000000000..824d71ba34275ecf4846caa3631648e035f67cf4
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/wiring_private.d
@@ -0,0 +1,368 @@
+src/core/wiring_private.d src/core/wiring_private.o: \
+ ../src/core/wiring_private.c ..\include\core/Arduino.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\string.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\xlocale.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\string.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\math.h \
+ ..\include\core/avr/pgmspace.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\inttypes.h \
+ ..\include\core/avr/interrupt.h ..\include\core/avr/io.h \
+ ..\include\core/binary.h ..\include\core/itoa.h ..\include\core/sam.h \
+ ..\include\core/samd.h ..\include\core/samd21/include/samd21.h \
+ ..\include\core/samd21/include/samd21g18a.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h \
+ ..\include\core/samd21/include/system_samd21.h \
+ ..\include\core/samd21/include/component/ac.h \
+ ..\include\core/samd21/include/component/adc.h \
+ ..\include\core/samd21/include/component/dac.h \
+ ..\include\core/samd21/include/component/dmac.h \
+ ..\include\core/samd21/include/component/dsu.h \
+ ..\include\core/samd21/include/component/eic.h \
+ ..\include\core/samd21/include/component/evsys.h \
+ ..\include\core/samd21/include/component/gclk.h \
+ ..\include\core/samd21/include/component/hmatrixb.h \
+ ..\include\core/samd21/include/component/i2s.h \
+ ..\include\core/samd21/include/component/mtb.h \
+ ..\include\core/samd21/include/component/nvmctrl.h \
+ ..\include\core/samd21/include/component/pac.h \
+ ..\include\core/samd21/include/component/pm.h \
+ ..\include\core/samd21/include/component/port.h \
+ ..\include\core/samd21/include/component/rtc.h \
+ ..\include\core/samd21/include/component/sercom.h \
+ ..\include\core/samd21/include/component/sysctrl.h \
+ ..\include\core/samd21/include/component/tc.h \
+ ..\include\core/samd21/include/component/tcc.h \
+ ..\include\core/samd21/include/component/usb.h \
+ ..\include\core/samd21/include/component/wdt.h \
+ ..\include\core/samd21/include/instance/ac.h \
+ ..\include\core/samd21/include/instance/adc.h \
+ ..\include\core/samd21/include/instance/dac.h \
+ ..\include\core/samd21/include/instance/dmac.h \
+ ..\include\core/samd21/include/instance/dsu.h \
+ ..\include\core/samd21/include/instance/eic.h \
+ ..\include\core/samd21/include/instance/evsys.h \
+ ..\include\core/samd21/include/instance/gclk.h \
+ ..\include\core/samd21/include/instance/sbmatrix.h \
+ ..\include\core/samd21/include/instance/i2s.h \
+ ..\include\core/samd21/include/instance/mtb.h \
+ ..\include\core/samd21/include/instance/nvmctrl.h \
+ ..\include\core/samd21/include/instance/pac0.h \
+ ..\include\core/samd21/include/instance/pac1.h \
+ ..\include\core/samd21/include/instance/pac2.h \
+ ..\include\core/samd21/include/instance/pm.h \
+ ..\include\core/samd21/include/instance/port.h \
+ ..\include\core/samd21/include/instance/rtc.h \
+ ..\include\core/samd21/include/instance/sercom0.h \
+ ..\include\core/samd21/include/instance/sercom1.h \
+ ..\include\core/samd21/include/instance/sercom2.h \
+ ..\include\core/samd21/include/instance/sercom3.h \
+ ..\include\core/samd21/include/instance/sercom4.h \
+ ..\include\core/samd21/include/instance/sercom5.h \
+ ..\include\core/samd21/include/instance/sysctrl.h \
+ ..\include\core/samd21/include/instance/tc3.h \
+ ..\include\core/samd21/include/instance/tc4.h \
+ ..\include\core/samd21/include/instance/tc5.h \
+ ..\include\core/samd21/include/instance/tcc0.h \
+ ..\include\core/samd21/include/instance/tcc1.h \
+ ..\include\core/samd21/include/instance/tcc2.h \
+ ..\include\core/samd21/include/instance/usb.h \
+ ..\include\core/samd21/include/instance/wdt.h \
+ ..\include\core/samd21/include/pio/samd21g18a.h \
+ ..\include\core/wiring_constants.h ..\include\core/WVariant.h \
+ ..\include\core/delay.h ..\include\variants/variant.h \
+ ..\include\core/wiring.h ..\include\core/wiring_digital.h \
+ ..\include\core/wiring_analog.h ..\include\core/wiring_shift.h \
+ ..\include\core/WInterrupts.h ..\include\core/USB/USBDesc.h \
+ ..\include\core/USB/USBCore.h ..\include\core/USB/USBAPI.h \
+ ..\include\core/USB/USB_host.h ..\include\core/USB/samd21_host.h \
+ ..\include\core/wiring_private.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h
+
+..\include\core/Arduino.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\string.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\xlocale.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\string.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\math.h:
+
+..\include\core/avr/pgmspace.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\inttypes.h:
+
+..\include\core/avr/interrupt.h:
+
+..\include\core/avr/io.h:
+
+..\include\core/binary.h:
+
+..\include\core/itoa.h:
+
+..\include\core/sam.h:
+
+..\include\core/samd.h:
+
+..\include\core/samd21/include/samd21.h:
+
+..\include\core/samd21/include/samd21g18a.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h:
+
+..\include\core/samd21/include/system_samd21.h:
+
+..\include\core/samd21/include/component/ac.h:
+
+..\include\core/samd21/include/component/adc.h:
+
+..\include\core/samd21/include/component/dac.h:
+
+..\include\core/samd21/include/component/dmac.h:
+
+..\include\core/samd21/include/component/dsu.h:
+
+..\include\core/samd21/include/component/eic.h:
+
+..\include\core/samd21/include/component/evsys.h:
+
+..\include\core/samd21/include/component/gclk.h:
+
+..\include\core/samd21/include/component/hmatrixb.h:
+
+..\include\core/samd21/include/component/i2s.h:
+
+..\include\core/samd21/include/component/mtb.h:
+
+..\include\core/samd21/include/component/nvmctrl.h:
+
+..\include\core/samd21/include/component/pac.h:
+
+..\include\core/samd21/include/component/pm.h:
+
+..\include\core/samd21/include/component/port.h:
+
+..\include\core/samd21/include/component/rtc.h:
+
+..\include\core/samd21/include/component/sercom.h:
+
+..\include\core/samd21/include/component/sysctrl.h:
+
+..\include\core/samd21/include/component/tc.h:
+
+..\include\core/samd21/include/component/tcc.h:
+
+..\include\core/samd21/include/component/usb.h:
+
+..\include\core/samd21/include/component/wdt.h:
+
+..\include\core/samd21/include/instance/ac.h:
+
+..\include\core/samd21/include/instance/adc.h:
+
+..\include\core/samd21/include/instance/dac.h:
+
+..\include\core/samd21/include/instance/dmac.h:
+
+..\include\core/samd21/include/instance/dsu.h:
+
+..\include\core/samd21/include/instance/eic.h:
+
+..\include\core/samd21/include/instance/evsys.h:
+
+..\include\core/samd21/include/instance/gclk.h:
+
+..\include\core/samd21/include/instance/sbmatrix.h:
+
+..\include\core/samd21/include/instance/i2s.h:
+
+..\include\core/samd21/include/instance/mtb.h:
+
+..\include\core/samd21/include/instance/nvmctrl.h:
+
+..\include\core/samd21/include/instance/pac0.h:
+
+..\include\core/samd21/include/instance/pac1.h:
+
+..\include\core/samd21/include/instance/pac2.h:
+
+..\include\core/samd21/include/instance/pm.h:
+
+..\include\core/samd21/include/instance/port.h:
+
+..\include\core/samd21/include/instance/rtc.h:
+
+..\include\core/samd21/include/instance/sercom0.h:
+
+..\include\core/samd21/include/instance/sercom1.h:
+
+..\include\core/samd21/include/instance/sercom2.h:
+
+..\include\core/samd21/include/instance/sercom3.h:
+
+..\include\core/samd21/include/instance/sercom4.h:
+
+..\include\core/samd21/include/instance/sercom5.h:
+
+..\include\core/samd21/include/instance/sysctrl.h:
+
+..\include\core/samd21/include/instance/tc3.h:
+
+..\include\core/samd21/include/instance/tc4.h:
+
+..\include\core/samd21/include/instance/tc5.h:
+
+..\include\core/samd21/include/instance/tcc0.h:
+
+..\include\core/samd21/include/instance/tcc1.h:
+
+..\include\core/samd21/include/instance/tcc2.h:
+
+..\include\core/samd21/include/instance/usb.h:
+
+..\include\core/samd21/include/instance/wdt.h:
+
+..\include\core/samd21/include/pio/samd21g18a.h:
+
+..\include\core/wiring_constants.h:
+
+..\include\core/WVariant.h:
+
+..\include\core/delay.h:
+
+..\include\variants/variant.h:
+
+..\include\core/wiring.h:
+
+..\include\core/wiring_digital.h:
+
+..\include\core/wiring_analog.h:
+
+..\include\core/wiring_shift.h:
+
+..\include\core/WInterrupts.h:
+
+..\include\core/USB/USBDesc.h:
+
+..\include\core/USB/USBCore.h:
+
+..\include\core/USB/USBAPI.h:
+
+..\include\core/USB/USB_host.h:
+
+..\include\core/USB/samd21_host.h:
+
+..\include\core/wiring_private.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
diff --git a/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/wiring_private.o b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/wiring_private.o
new file mode 100644
index 0000000000000000000000000000000000000000..5c7109fae29e51bc1f265fd518ef8b4a391dba06
Binary files /dev/null and b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/wiring_private.o differ
diff --git a/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/wiring_shift.d b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/wiring_shift.d
new file mode 100644
index 0000000000000000000000000000000000000000..50b6722bd4e5e7ee58b1e59cc3b648cc722d5758
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/wiring_shift.d
@@ -0,0 +1,302 @@
+src/core/wiring_shift.d src/core/wiring_shift.o: \
+ ../src/core/wiring_shift.c \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ ..\include\core/wiring_shift.h ..\include\core/wiring_digital.h \
+ ..\include\core/WVariant.h ..\include\core/sam.h ..\include\core/samd.h \
+ ..\include\core/samd21/include/samd21.h \
+ ..\include\core/samd21/include/samd21g18a.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h \
+ ..\include\core/samd21/include/system_samd21.h \
+ ..\include\core/samd21/include/component/ac.h \
+ ..\include\core/samd21/include/component/adc.h \
+ ..\include\core/samd21/include/component/dac.h \
+ ..\include\core/samd21/include/component/dmac.h \
+ ..\include\core/samd21/include/component/dsu.h \
+ ..\include\core/samd21/include/component/eic.h \
+ ..\include\core/samd21/include/component/evsys.h \
+ ..\include\core/samd21/include/component/gclk.h \
+ ..\include\core/samd21/include/component/hmatrixb.h \
+ ..\include\core/samd21/include/component/i2s.h \
+ ..\include\core/samd21/include/component/mtb.h \
+ ..\include\core/samd21/include/component/nvmctrl.h \
+ ..\include\core/samd21/include/component/pac.h \
+ ..\include\core/samd21/include/component/pm.h \
+ ..\include\core/samd21/include/component/port.h \
+ ..\include\core/samd21/include/component/rtc.h \
+ ..\include\core/samd21/include/component/sercom.h \
+ ..\include\core/samd21/include/component/sysctrl.h \
+ ..\include\core/samd21/include/component/tc.h \
+ ..\include\core/samd21/include/component/tcc.h \
+ ..\include\core/samd21/include/component/usb.h \
+ ..\include\core/samd21/include/component/wdt.h \
+ ..\include\core/samd21/include/instance/ac.h \
+ ..\include\core/samd21/include/instance/adc.h \
+ ..\include\core/samd21/include/instance/dac.h \
+ ..\include\core/samd21/include/instance/dmac.h \
+ ..\include\core/samd21/include/instance/dsu.h \
+ ..\include\core/samd21/include/instance/eic.h \
+ ..\include\core/samd21/include/instance/evsys.h \
+ ..\include\core/samd21/include/instance/gclk.h \
+ ..\include\core/samd21/include/instance/sbmatrix.h \
+ ..\include\core/samd21/include/instance/i2s.h \
+ ..\include\core/samd21/include/instance/mtb.h \
+ ..\include\core/samd21/include/instance/nvmctrl.h \
+ ..\include\core/samd21/include/instance/pac0.h \
+ ..\include\core/samd21/include/instance/pac1.h \
+ ..\include\core/samd21/include/instance/pac2.h \
+ ..\include\core/samd21/include/instance/pm.h \
+ ..\include\core/samd21/include/instance/port.h \
+ ..\include\core/samd21/include/instance/rtc.h \
+ ..\include\core/samd21/include/instance/sercom0.h \
+ ..\include\core/samd21/include/instance/sercom1.h \
+ ..\include\core/samd21/include/instance/sercom2.h \
+ ..\include\core/samd21/include/instance/sercom3.h \
+ ..\include\core/samd21/include/instance/sercom4.h \
+ ..\include\core/samd21/include/instance/sercom5.h \
+ ..\include\core/samd21/include/instance/sysctrl.h \
+ ..\include\core/samd21/include/instance/tc3.h \
+ ..\include\core/samd21/include/instance/tc4.h \
+ ..\include\core/samd21/include/instance/tc5.h \
+ ..\include\core/samd21/include/instance/tcc0.h \
+ ..\include\core/samd21/include/instance/tcc1.h \
+ ..\include\core/samd21/include/instance/tcc2.h \
+ ..\include\core/samd21/include/instance/usb.h \
+ ..\include\core/samd21/include/instance/wdt.h \
+ ..\include\core/samd21/include/pio/samd21g18a.h \
+ ..\include\core/wiring_private.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
+ ..\include\core/wiring_constants.h
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+..\include\core/wiring_shift.h:
+
+..\include\core/wiring_digital.h:
+
+..\include\core/WVariant.h:
+
+..\include\core/sam.h:
+
+..\include\core/samd.h:
+
+..\include\core/samd21/include/samd21.h:
+
+..\include\core/samd21/include/samd21g18a.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h:
+
+..\include\core/samd21/include/system_samd21.h:
+
+..\include\core/samd21/include/component/ac.h:
+
+..\include\core/samd21/include/component/adc.h:
+
+..\include\core/samd21/include/component/dac.h:
+
+..\include\core/samd21/include/component/dmac.h:
+
+..\include\core/samd21/include/component/dsu.h:
+
+..\include\core/samd21/include/component/eic.h:
+
+..\include\core/samd21/include/component/evsys.h:
+
+..\include\core/samd21/include/component/gclk.h:
+
+..\include\core/samd21/include/component/hmatrixb.h:
+
+..\include\core/samd21/include/component/i2s.h:
+
+..\include\core/samd21/include/component/mtb.h:
+
+..\include\core/samd21/include/component/nvmctrl.h:
+
+..\include\core/samd21/include/component/pac.h:
+
+..\include\core/samd21/include/component/pm.h:
+
+..\include\core/samd21/include/component/port.h:
+
+..\include\core/samd21/include/component/rtc.h:
+
+..\include\core/samd21/include/component/sercom.h:
+
+..\include\core/samd21/include/component/sysctrl.h:
+
+..\include\core/samd21/include/component/tc.h:
+
+..\include\core/samd21/include/component/tcc.h:
+
+..\include\core/samd21/include/component/usb.h:
+
+..\include\core/samd21/include/component/wdt.h:
+
+..\include\core/samd21/include/instance/ac.h:
+
+..\include\core/samd21/include/instance/adc.h:
+
+..\include\core/samd21/include/instance/dac.h:
+
+..\include\core/samd21/include/instance/dmac.h:
+
+..\include\core/samd21/include/instance/dsu.h:
+
+..\include\core/samd21/include/instance/eic.h:
+
+..\include\core/samd21/include/instance/evsys.h:
+
+..\include\core/samd21/include/instance/gclk.h:
+
+..\include\core/samd21/include/instance/sbmatrix.h:
+
+..\include\core/samd21/include/instance/i2s.h:
+
+..\include\core/samd21/include/instance/mtb.h:
+
+..\include\core/samd21/include/instance/nvmctrl.h:
+
+..\include\core/samd21/include/instance/pac0.h:
+
+..\include\core/samd21/include/instance/pac1.h:
+
+..\include\core/samd21/include/instance/pac2.h:
+
+..\include\core/samd21/include/instance/pm.h:
+
+..\include\core/samd21/include/instance/port.h:
+
+..\include\core/samd21/include/instance/rtc.h:
+
+..\include\core/samd21/include/instance/sercom0.h:
+
+..\include\core/samd21/include/instance/sercom1.h:
+
+..\include\core/samd21/include/instance/sercom2.h:
+
+..\include\core/samd21/include/instance/sercom3.h:
+
+..\include\core/samd21/include/instance/sercom4.h:
+
+..\include\core/samd21/include/instance/sercom5.h:
+
+..\include\core/samd21/include/instance/sysctrl.h:
+
+..\include\core/samd21/include/instance/tc3.h:
+
+..\include\core/samd21/include/instance/tc4.h:
+
+..\include\core/samd21/include/instance/tc5.h:
+
+..\include\core/samd21/include/instance/tcc0.h:
+
+..\include\core/samd21/include/instance/tcc1.h:
+
+..\include\core/samd21/include/instance/tcc2.h:
+
+..\include\core/samd21/include/instance/usb.h:
+
+..\include\core/samd21/include/instance/wdt.h:
+
+..\include\core/samd21/include/pio/samd21g18a.h:
+
+..\include\core/wiring_private.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
+
+..\include\core/wiring_constants.h:
diff --git a/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/wiring_shift.o b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/wiring_shift.o
new file mode 100644
index 0000000000000000000000000000000000000000..bb1216afc4ee43958a0667a0e04e1ffa25ef75f3
Binary files /dev/null and b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/core/wiring_shift.o differ
diff --git a/UsbReceive/UsbReceive/ArduinoCore/Debug/src/libraries/wire/Wire.d b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/libraries/wire/Wire.d
new file mode 100644
index 0000000000000000000000000000000000000000..08a9b20bdf45bac0767d5be0b9820927520e7c95
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/libraries/wire/Wire.d
@@ -0,0 +1,455 @@
+src/libraries/wire/Wire.d src/libraries/wire/Wire.o: \
+ ../src/libraries/wire/Wire.cpp \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\string.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\xlocale.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\string.h \
+ ..\include\core/Arduino.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cstdlib \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\c++config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\os_defines.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\cpu_defines.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\math.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cmath \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\bits\cpp_type_traits.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\ext\type_traits.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\math.h \
+ ..\include\core/avr/pgmspace.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\inttypes.h \
+ ..\include\core/avr/interrupt.h ..\include\core/avr/io.h \
+ ..\include\core/binary.h ..\include\core/itoa.h ..\include\core/sam.h \
+ ..\include\core/samd.h ..\include\core/samd21/include/samd21.h \
+ ..\include\core/samd21/include/samd21g18a.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h \
+ ..\include\core/samd21/include/system_samd21.h \
+ ..\include\core/samd21/include/component/ac.h \
+ ..\include\core/samd21/include/component/adc.h \
+ ..\include\core/samd21/include/component/dac.h \
+ ..\include\core/samd21/include/component/dmac.h \
+ ..\include\core/samd21/include/component/dsu.h \
+ ..\include\core/samd21/include/component/eic.h \
+ ..\include\core/samd21/include/component/evsys.h \
+ ..\include\core/samd21/include/component/gclk.h \
+ ..\include\core/samd21/include/component/hmatrixb.h \
+ ..\include\core/samd21/include/component/i2s.h \
+ ..\include\core/samd21/include/component/mtb.h \
+ ..\include\core/samd21/include/component/nvmctrl.h \
+ ..\include\core/samd21/include/component/pac.h \
+ ..\include\core/samd21/include/component/pm.h \
+ ..\include\core/samd21/include/component/port.h \
+ ..\include\core/samd21/include/component/rtc.h \
+ ..\include\core/samd21/include/component/sercom.h \
+ ..\include\core/samd21/include/component/sysctrl.h \
+ ..\include\core/samd21/include/component/tc.h \
+ ..\include\core/samd21/include/component/tcc.h \
+ ..\include\core/samd21/include/component/usb.h \
+ ..\include\core/samd21/include/component/wdt.h \
+ ..\include\core/samd21/include/instance/ac.h \
+ ..\include\core/samd21/include/instance/adc.h \
+ ..\include\core/samd21/include/instance/dac.h \
+ ..\include\core/samd21/include/instance/dmac.h \
+ ..\include\core/samd21/include/instance/dsu.h \
+ ..\include\core/samd21/include/instance/eic.h \
+ ..\include\core/samd21/include/instance/evsys.h \
+ ..\include\core/samd21/include/instance/gclk.h \
+ ..\include\core/samd21/include/instance/sbmatrix.h \
+ ..\include\core/samd21/include/instance/i2s.h \
+ ..\include\core/samd21/include/instance/mtb.h \
+ ..\include\core/samd21/include/instance/nvmctrl.h \
+ ..\include\core/samd21/include/instance/pac0.h \
+ ..\include\core/samd21/include/instance/pac1.h \
+ ..\include\core/samd21/include/instance/pac2.h \
+ ..\include\core/samd21/include/instance/pm.h \
+ ..\include\core/samd21/include/instance/port.h \
+ ..\include\core/samd21/include/instance/rtc.h \
+ ..\include\core/samd21/include/instance/sercom0.h \
+ ..\include\core/samd21/include/instance/sercom1.h \
+ ..\include\core/samd21/include/instance/sercom2.h \
+ ..\include\core/samd21/include/instance/sercom3.h \
+ ..\include\core/samd21/include/instance/sercom4.h \
+ ..\include\core/samd21/include/instance/sercom5.h \
+ ..\include\core/samd21/include/instance/sysctrl.h \
+ ..\include\core/samd21/include/instance/tc3.h \
+ ..\include\core/samd21/include/instance/tc4.h \
+ ..\include\core/samd21/include/instance/tc5.h \
+ ..\include\core/samd21/include/instance/tcc0.h \
+ ..\include\core/samd21/include/instance/tcc1.h \
+ ..\include\core/samd21/include/instance/tcc2.h \
+ ..\include\core/samd21/include/instance/usb.h \
+ ..\include\core/samd21/include/instance/wdt.h \
+ ..\include\core/samd21/include/pio/samd21g18a.h \
+ ..\include\core/wiring_constants.h ..\include\core/WVariant.h \
+ ..\include\core/WCharacter.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\ctype.h \
+ ..\include\core/WString.h ..\include\core/avr/pgmspace.h \
+ ..\include\core/Tone.h ..\include\core/Arduino.h ..\include\core/WMath.h \
+ ..\include\core/HardwareSerial.h ..\include\core/Stream.h \
+ ..\include\core/Print.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
+ ..\include\core/Printable.h ..\include\core/pulse.h \
+ ..\include\core/delay.h ..\include\variants/variant.h \
+ ..\include\core/SERCOM.h ..\include\core/Uart.h ..\include\core/SERCOM.h \
+ ..\include\core/RingBuffer.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cstddef \
+ ..\include\core/wiring.h ..\include\core/wiring_digital.h \
+ ..\include\core/wiring_analog.h ..\include\core/wiring_shift.h \
+ ..\include\core/WInterrupts.h ..\include\core/USB/USBDesc.h \
+ ..\include\core/USB/USBCore.h ..\include\core/USB/USBAPI.h \
+ ..\include\core/Stream.h ..\include\core/RingBuffer.h \
+ ..\include\core/USB/USB_host.h ..\include\core/USB/samd21_host.h \
+ ..\include\core/USB/CDC.h ..\include\core/USB/USBDesc.h \
+ ..\include\core/USB/PluggableUSB.h ..\include\core/wiring_private.h \
+ ..\include\libraries\wire/Wire.h
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\string.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\xlocale.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\string.h:
+
+..\include\core/Arduino.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cstdlib:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\c++config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\os_defines.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\cpu_defines.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\math.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cmath:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\bits\cpp_type_traits.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\ext\type_traits.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\math.h:
+
+..\include\core/avr/pgmspace.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\inttypes.h:
+
+..\include\core/avr/interrupt.h:
+
+..\include\core/avr/io.h:
+
+..\include\core/binary.h:
+
+..\include\core/itoa.h:
+
+..\include\core/sam.h:
+
+..\include\core/samd.h:
+
+..\include\core/samd21/include/samd21.h:
+
+..\include\core/samd21/include/samd21g18a.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h:
+
+..\include\core/samd21/include/system_samd21.h:
+
+..\include\core/samd21/include/component/ac.h:
+
+..\include\core/samd21/include/component/adc.h:
+
+..\include\core/samd21/include/component/dac.h:
+
+..\include\core/samd21/include/component/dmac.h:
+
+..\include\core/samd21/include/component/dsu.h:
+
+..\include\core/samd21/include/component/eic.h:
+
+..\include\core/samd21/include/component/evsys.h:
+
+..\include\core/samd21/include/component/gclk.h:
+
+..\include\core/samd21/include/component/hmatrixb.h:
+
+..\include\core/samd21/include/component/i2s.h:
+
+..\include\core/samd21/include/component/mtb.h:
+
+..\include\core/samd21/include/component/nvmctrl.h:
+
+..\include\core/samd21/include/component/pac.h:
+
+..\include\core/samd21/include/component/pm.h:
+
+..\include\core/samd21/include/component/port.h:
+
+..\include\core/samd21/include/component/rtc.h:
+
+..\include\core/samd21/include/component/sercom.h:
+
+..\include\core/samd21/include/component/sysctrl.h:
+
+..\include\core/samd21/include/component/tc.h:
+
+..\include\core/samd21/include/component/tcc.h:
+
+..\include\core/samd21/include/component/usb.h:
+
+..\include\core/samd21/include/component/wdt.h:
+
+..\include\core/samd21/include/instance/ac.h:
+
+..\include\core/samd21/include/instance/adc.h:
+
+..\include\core/samd21/include/instance/dac.h:
+
+..\include\core/samd21/include/instance/dmac.h:
+
+..\include\core/samd21/include/instance/dsu.h:
+
+..\include\core/samd21/include/instance/eic.h:
+
+..\include\core/samd21/include/instance/evsys.h:
+
+..\include\core/samd21/include/instance/gclk.h:
+
+..\include\core/samd21/include/instance/sbmatrix.h:
+
+..\include\core/samd21/include/instance/i2s.h:
+
+..\include\core/samd21/include/instance/mtb.h:
+
+..\include\core/samd21/include/instance/nvmctrl.h:
+
+..\include\core/samd21/include/instance/pac0.h:
+
+..\include\core/samd21/include/instance/pac1.h:
+
+..\include\core/samd21/include/instance/pac2.h:
+
+..\include\core/samd21/include/instance/pm.h:
+
+..\include\core/samd21/include/instance/port.h:
+
+..\include\core/samd21/include/instance/rtc.h:
+
+..\include\core/samd21/include/instance/sercom0.h:
+
+..\include\core/samd21/include/instance/sercom1.h:
+
+..\include\core/samd21/include/instance/sercom2.h:
+
+..\include\core/samd21/include/instance/sercom3.h:
+
+..\include\core/samd21/include/instance/sercom4.h:
+
+..\include\core/samd21/include/instance/sercom5.h:
+
+..\include\core/samd21/include/instance/sysctrl.h:
+
+..\include\core/samd21/include/instance/tc3.h:
+
+..\include\core/samd21/include/instance/tc4.h:
+
+..\include\core/samd21/include/instance/tc5.h:
+
+..\include\core/samd21/include/instance/tcc0.h:
+
+..\include\core/samd21/include/instance/tcc1.h:
+
+..\include\core/samd21/include/instance/tcc2.h:
+
+..\include\core/samd21/include/instance/usb.h:
+
+..\include\core/samd21/include/instance/wdt.h:
+
+..\include\core/samd21/include/pio/samd21g18a.h:
+
+..\include\core/wiring_constants.h:
+
+..\include\core/WVariant.h:
+
+..\include\core/WCharacter.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\ctype.h:
+
+..\include\core/WString.h:
+
+..\include\core/avr/pgmspace.h:
+
+..\include\core/Tone.h:
+
+..\include\core/Arduino.h:
+
+..\include\core/WMath.h:
+
+..\include\core/HardwareSerial.h:
+
+..\include\core/Stream.h:
+
+..\include\core/Print.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
+
+..\include\core/Printable.h:
+
+..\include\core/pulse.h:
+
+..\include\core/delay.h:
+
+..\include\variants/variant.h:
+
+..\include\core/SERCOM.h:
+
+..\include\core/Uart.h:
+
+..\include\core/SERCOM.h:
+
+..\include\core/RingBuffer.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cstddef:
+
+..\include\core/wiring.h:
+
+..\include\core/wiring_digital.h:
+
+..\include\core/wiring_analog.h:
+
+..\include\core/wiring_shift.h:
+
+..\include\core/WInterrupts.h:
+
+..\include\core/USB/USBDesc.h:
+
+..\include\core/USB/USBCore.h:
+
+..\include\core/USB/USBAPI.h:
+
+..\include\core/Stream.h:
+
+..\include\core/RingBuffer.h:
+
+..\include\core/USB/USB_host.h:
+
+..\include\core/USB/samd21_host.h:
+
+..\include\core/USB/CDC.h:
+
+..\include\core/USB/USBDesc.h:
+
+..\include\core/USB/PluggableUSB.h:
+
+..\include\core/wiring_private.h:
+
+..\include\libraries\wire/Wire.h:
diff --git a/UsbReceive/UsbReceive/ArduinoCore/Debug/src/libraries/wire/Wire.o b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/libraries/wire/Wire.o
new file mode 100644
index 0000000000000000000000000000000000000000..411ea7bf3d847a65ed4f93674c8435b283ed2a72
Binary files /dev/null and b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/libraries/wire/Wire.o differ
diff --git a/UsbReceive/UsbReceive/ArduinoCore/Debug/src/variants/variant.d b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/variants/variant.d
new file mode 100644
index 0000000000000000000000000000000000000000..015a18e7151109e668103feea2f6e688fd485677
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/variants/variant.d
@@ -0,0 +1,361 @@
+src/variants/variant.d src/variants/variant.o: \
+ ../src/variants/variant.cpp ..\include\variants/variant.h \
+ ..\include\core/WVariant.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ ..\include\core/sam.h ..\include\core/samd.h \
+ ..\include\core/samd21/include/samd21.h \
+ ..\include\core/samd21/include/samd21g18a.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h \
+ ..\include\core/samd21/include/system_samd21.h \
+ ..\include\core/samd21/include/component/ac.h \
+ ..\include\core/samd21/include/component/adc.h \
+ ..\include\core/samd21/include/component/dac.h \
+ ..\include\core/samd21/include/component/dmac.h \
+ ..\include\core/samd21/include/component/dsu.h \
+ ..\include\core/samd21/include/component/eic.h \
+ ..\include\core/samd21/include/component/evsys.h \
+ ..\include\core/samd21/include/component/gclk.h \
+ ..\include\core/samd21/include/component/hmatrixb.h \
+ ..\include\core/samd21/include/component/i2s.h \
+ ..\include\core/samd21/include/component/mtb.h \
+ ..\include\core/samd21/include/component/nvmctrl.h \
+ ..\include\core/samd21/include/component/pac.h \
+ ..\include\core/samd21/include/component/pm.h \
+ ..\include\core/samd21/include/component/port.h \
+ ..\include\core/samd21/include/component/rtc.h \
+ ..\include\core/samd21/include/component/sercom.h \
+ ..\include\core/samd21/include/component/sysctrl.h \
+ ..\include\core/samd21/include/component/tc.h \
+ ..\include\core/samd21/include/component/tcc.h \
+ ..\include\core/samd21/include/component/usb.h \
+ ..\include\core/samd21/include/component/wdt.h \
+ ..\include\core/samd21/include/instance/ac.h \
+ ..\include\core/samd21/include/instance/adc.h \
+ ..\include\core/samd21/include/instance/dac.h \
+ ..\include\core/samd21/include/instance/dmac.h \
+ ..\include\core/samd21/include/instance/dsu.h \
+ ..\include\core/samd21/include/instance/eic.h \
+ ..\include\core/samd21/include/instance/evsys.h \
+ ..\include\core/samd21/include/instance/gclk.h \
+ ..\include\core/samd21/include/instance/sbmatrix.h \
+ ..\include\core/samd21/include/instance/i2s.h \
+ ..\include\core/samd21/include/instance/mtb.h \
+ ..\include\core/samd21/include/instance/nvmctrl.h \
+ ..\include\core/samd21/include/instance/pac0.h \
+ ..\include\core/samd21/include/instance/pac1.h \
+ ..\include\core/samd21/include/instance/pac2.h \
+ ..\include\core/samd21/include/instance/pm.h \
+ ..\include\core/samd21/include/instance/port.h \
+ ..\include\core/samd21/include/instance/rtc.h \
+ ..\include\core/samd21/include/instance/sercom0.h \
+ ..\include\core/samd21/include/instance/sercom1.h \
+ ..\include\core/samd21/include/instance/sercom2.h \
+ ..\include\core/samd21/include/instance/sercom3.h \
+ ..\include\core/samd21/include/instance/sercom4.h \
+ ..\include\core/samd21/include/instance/sercom5.h \
+ ..\include\core/samd21/include/instance/sysctrl.h \
+ ..\include\core/samd21/include/instance/tc3.h \
+ ..\include\core/samd21/include/instance/tc4.h \
+ ..\include\core/samd21/include/instance/tc5.h \
+ ..\include\core/samd21/include/instance/tcc0.h \
+ ..\include\core/samd21/include/instance/tcc1.h \
+ ..\include\core/samd21/include/instance/tcc2.h \
+ ..\include\core/samd21/include/instance/usb.h \
+ ..\include\core/samd21/include/instance/wdt.h \
+ ..\include\core/samd21/include/pio/samd21g18a.h ..\include\core/SERCOM.h \
+ ..\include\core/Uart.h ..\include\core/HardwareSerial.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\inttypes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ ..\include\core/Stream.h ..\include\core/Print.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
+ ..\include\core/WString.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cstdlib \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\c++config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\os_defines.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\cpu_defines.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\string.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\xlocale.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\string.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\ctype.h \
+ ..\include\core/avr/pgmspace.h ..\include\core/Printable.h \
+ ..\include\core/SERCOM.h ..\include\core/RingBuffer.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cstddef
+
+..\include\variants/variant.h:
+
+..\include\core/WVariant.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+..\include\core/sam.h:
+
+..\include\core/samd.h:
+
+..\include\core/samd21/include/samd21.h:
+
+..\include\core/samd21/include/samd21g18a.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h:
+
+..\include\core/samd21/include/system_samd21.h:
+
+..\include\core/samd21/include/component/ac.h:
+
+..\include\core/samd21/include/component/adc.h:
+
+..\include\core/samd21/include/component/dac.h:
+
+..\include\core/samd21/include/component/dmac.h:
+
+..\include\core/samd21/include/component/dsu.h:
+
+..\include\core/samd21/include/component/eic.h:
+
+..\include\core/samd21/include/component/evsys.h:
+
+..\include\core/samd21/include/component/gclk.h:
+
+..\include\core/samd21/include/component/hmatrixb.h:
+
+..\include\core/samd21/include/component/i2s.h:
+
+..\include\core/samd21/include/component/mtb.h:
+
+..\include\core/samd21/include/component/nvmctrl.h:
+
+..\include\core/samd21/include/component/pac.h:
+
+..\include\core/samd21/include/component/pm.h:
+
+..\include\core/samd21/include/component/port.h:
+
+..\include\core/samd21/include/component/rtc.h:
+
+..\include\core/samd21/include/component/sercom.h:
+
+..\include\core/samd21/include/component/sysctrl.h:
+
+..\include\core/samd21/include/component/tc.h:
+
+..\include\core/samd21/include/component/tcc.h:
+
+..\include\core/samd21/include/component/usb.h:
+
+..\include\core/samd21/include/component/wdt.h:
+
+..\include\core/samd21/include/instance/ac.h:
+
+..\include\core/samd21/include/instance/adc.h:
+
+..\include\core/samd21/include/instance/dac.h:
+
+..\include\core/samd21/include/instance/dmac.h:
+
+..\include\core/samd21/include/instance/dsu.h:
+
+..\include\core/samd21/include/instance/eic.h:
+
+..\include\core/samd21/include/instance/evsys.h:
+
+..\include\core/samd21/include/instance/gclk.h:
+
+..\include\core/samd21/include/instance/sbmatrix.h:
+
+..\include\core/samd21/include/instance/i2s.h:
+
+..\include\core/samd21/include/instance/mtb.h:
+
+..\include\core/samd21/include/instance/nvmctrl.h:
+
+..\include\core/samd21/include/instance/pac0.h:
+
+..\include\core/samd21/include/instance/pac1.h:
+
+..\include\core/samd21/include/instance/pac2.h:
+
+..\include\core/samd21/include/instance/pm.h:
+
+..\include\core/samd21/include/instance/port.h:
+
+..\include\core/samd21/include/instance/rtc.h:
+
+..\include\core/samd21/include/instance/sercom0.h:
+
+..\include\core/samd21/include/instance/sercom1.h:
+
+..\include\core/samd21/include/instance/sercom2.h:
+
+..\include\core/samd21/include/instance/sercom3.h:
+
+..\include\core/samd21/include/instance/sercom4.h:
+
+..\include\core/samd21/include/instance/sercom5.h:
+
+..\include\core/samd21/include/instance/sysctrl.h:
+
+..\include\core/samd21/include/instance/tc3.h:
+
+..\include\core/samd21/include/instance/tc4.h:
+
+..\include\core/samd21/include/instance/tc5.h:
+
+..\include\core/samd21/include/instance/tcc0.h:
+
+..\include\core/samd21/include/instance/tcc1.h:
+
+..\include\core/samd21/include/instance/tcc2.h:
+
+..\include\core/samd21/include/instance/usb.h:
+
+..\include\core/samd21/include/instance/wdt.h:
+
+..\include\core/samd21/include/pio/samd21g18a.h:
+
+..\include\core/SERCOM.h:
+
+..\include\core/Uart.h:
+
+..\include\core/HardwareSerial.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\inttypes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+..\include\core/Stream.h:
+
+..\include\core/Print.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
+
+..\include\core/WString.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cstdlib:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\c++config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\os_defines.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\cpu_defines.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\string.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\xlocale.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\string.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\ctype.h:
+
+..\include\core/avr/pgmspace.h:
+
+..\include\core/Printable.h:
+
+..\include\core/SERCOM.h:
+
+..\include\core/RingBuffer.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cstddef:
diff --git a/UsbReceive/UsbReceive/ArduinoCore/Debug/src/variants/variant.o b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/variants/variant.o
new file mode 100644
index 0000000000000000000000000000000000000000..b69889caccf50731655a37ed1aa4a464558c2798
Binary files /dev/null and b/UsbReceive/UsbReceive/ArduinoCore/Debug/src/variants/variant.o differ
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/Arduino.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/Arduino.h
new file mode 100644
index 0000000000000000000000000000000000000000..c374c964b87348fea966afc9accb9f84e67900b9
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/Arduino.h
@@ -0,0 +1,142 @@
+/*
+ Arduino.h - Main include file for the Arduino SDK
+ Copyright (c) 2014 Arduino LLC. All right reserved.
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#ifndef Arduino_h
+#define Arduino_h
+
+#include <stdbool.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include <string.h>
+#include <math.h>
+
+typedef bool boolean;
+typedef uint8_t byte;
+typedef uint16_t word;
+
+// some libraries and sketches depend on this AVR stuff,
+// assuming Arduino.h or WProgram.h automatically includes it...
+//
+#include "avr/pgmspace.h"
+#include "avr/interrupt.h"
+#include "avr/io.h"
+
+#include "binary.h"
+#include "itoa.h"
+
+#ifdef __cplusplus
+extern "C"{
+#endif // __cplusplus
+
+// Include Atmel headers
+#include "sam.h"
+
+#include "wiring_constants.h"
+
+#define clockCyclesPerMicrosecond() ( SystemCoreClock / 1000000L )
+#define clockCyclesToMicroseconds(a) ( ((a) * 1000L) / (SystemCoreClock / 1000L) )
+#define microsecondsToClockCycles(a) ( (a) * (SystemCoreClock / 1000000L) )
+
+void yield( void ) ;
+
+/* system functions */
+int main( void );
+void init( void );
+
+/* sketch */
+void setup( void ) ;
+void loop( void ) ;
+
+#include "WVariant.h"
+
+#ifdef __cplusplus
+} // extern "C"
+#endif
+
+// The following headers are for C++ only compilation
+#ifdef __cplusplus
+ #include "WCharacter.h"
+ #include "WString.h"
+ #include "Tone.h"
+ #include "WMath.h"
+ #include "HardwareSerial.h"
+ #include "pulse.h"
+#endif
+#include "delay.h"
+#ifdef __cplusplus
+ #include "Uart.h"
+#endif
+
+// Include board variant
+#include "variant.h"
+
+#include "wiring.h"
+#include "wiring_digital.h"
+#include "wiring_analog.h"
+#include "wiring_shift.h"
+#include "WInterrupts.h"
+
+// undefine stdlib's abs if encountered
+#ifdef abs
+#undef abs
+#endif // abs
+
+#define min(a,b) ((a)<(b)?(a):(b))
+#define max(a,b) ((a)>(b)?(a):(b))
+#define abs(x) ((x)>0?(x):-(x))
+#define constrain(amt,low,high) ((amt)<(low)?(low):((amt)>(high)?(high):(amt)))
+#define round(x) ((x)>=0?(long)((x)+0.5):(long)((x)-0.5))
+#define radians(deg) ((deg)*DEG_TO_RAD)
+#define degrees(rad) ((rad)*RAD_TO_DEG)
+#define sq(x) ((x)*(x))
+
+#define interrupts() __enable_irq()
+#define noInterrupts() __disable_irq()
+
+#define lowByte(w) ((uint8_t) ((w) & 0xff))
+#define highByte(w) ((uint8_t) ((w) >> 8))
+
+#define bitRead(value, bit) (((value) >> (bit)) & 0x01)
+#define bitSet(value, bit) ((value) |= (1UL << (bit)))
+#define bitClear(value, bit) ((value) &= ~(1UL << (bit)))
+#define bitWrite(value, bit, bitvalue) (bitvalue ? bitSet(value, bit) : bitClear(value, bit))
+
+#define bit(b) (1UL << (b))
+
+#if (ARDUINO_SAMD_VARIANT_COMPLIANCE >= 10606)
+// Interrupts
+#define digitalPinToInterrupt(P) ( P )
+#endif
+
+// Allows publishing the Beta core under samd-beta / arduino organization
+#ifndef ARDUINO_ARCH_SAMD
+#define ARDUINO_ARCH_SAMD
+#endif
+
+// USB Device
+#include "USB/USBDesc.h"
+#include "USB/USBCore.h"
+#include "USB/USBAPI.h"
+#include "USB/USB_host.h"
+
+#ifdef __cplusplus
+ #include "USB/CDC.h"
+#endif
+
+#endif // Arduino_h
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/Client.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/Client.h
new file mode 100644
index 0000000000000000000000000000000000000000..b8e5d935f2a4d4dec9aad8ac6d849c2a8daf667d
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/Client.h
@@ -0,0 +1,45 @@
+/*
+ Client.h - Base class that provides Client
+ Copyright (c) 2011 Adrian McEwen. All right reserved.
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#ifndef client_h
+#define client_h
+#include "Print.h"
+#include "Stream.h"
+#include "IPAddress.h"
+
+class Client : public Stream {
+
+public:
+ virtual int connect(IPAddress ip, uint16_t port) =0;
+ virtual int connect(const char *host, uint16_t port) =0;
+ virtual size_t write(uint8_t) =0;
+ virtual size_t write(const uint8_t *buf, size_t size) =0;
+ virtual int available() = 0;
+ virtual int read() = 0;
+ virtual int read(uint8_t *buf, size_t size) = 0;
+ virtual int peek() = 0;
+ virtual void flush() = 0;
+ virtual void stop() = 0;
+ virtual uint8_t connected() = 0;
+ virtual operator bool() = 0;
+protected:
+ uint8_t* rawIPAddress(IPAddress& addr) { return addr.raw_address(); };
+};
+
+#endif
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/HardwareSerial.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/HardwareSerial.h
new file mode 100644
index 0000000000000000000000000000000000000000..62508e78643c6bf5e364e827833491085c54f501
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/HardwareSerial.h
@@ -0,0 +1,84 @@
+/*
+ Copyright (c) 2015 Arduino LLC. All right reserved.
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ See the GNU Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#ifndef HardwareSerial_h
+#define HardwareSerial_h
+
+#include <inttypes.h>
+
+#include "Stream.h"
+
+#define HARDSER_PARITY_EVEN (0x1ul)
+#define HARDSER_PARITY_ODD (0x2ul)
+#define HARDSER_PARITY_NONE (0x3ul)
+#define HARDSER_PARITY_MASK (0xFul)
+
+#define HARDSER_STOP_BIT_1 (0x10ul)
+#define HARDSER_STOP_BIT_1_5 (0x20ul)
+#define HARDSER_STOP_BIT_2 (0x30ul)
+#define HARDSER_STOP_BIT_MASK (0xF0ul)
+
+#define HARDSER_DATA_5 (0x100ul)
+#define HARDSER_DATA_6 (0x200ul)
+#define HARDSER_DATA_7 (0x300ul)
+#define HARDSER_DATA_8 (0x400ul)
+#define HARDSER_DATA_MASK (0xF00ul)
+
+#define SERIAL_5N1 (HARDSER_STOP_BIT_1 | HARDSER_PARITY_NONE | HARDSER_DATA_5)
+#define SERIAL_6N1 (HARDSER_STOP_BIT_1 | HARDSER_PARITY_NONE | HARDSER_DATA_6)
+#define SERIAL_7N1 (HARDSER_STOP_BIT_1 | HARDSER_PARITY_NONE | HARDSER_DATA_7)
+#define SERIAL_8N1 (HARDSER_STOP_BIT_1 | HARDSER_PARITY_NONE | HARDSER_DATA_8)
+#define SERIAL_5N2 (HARDSER_STOP_BIT_2 | HARDSER_PARITY_NONE | HARDSER_DATA_5)
+#define SERIAL_6N2 (HARDSER_STOP_BIT_2 | HARDSER_PARITY_NONE | HARDSER_DATA_6)
+#define SERIAL_7N2 (HARDSER_STOP_BIT_2 | HARDSER_PARITY_NONE | HARDSER_DATA_7)
+#define SERIAL_8N2 (HARDSER_STOP_BIT_2 | HARDSER_PARITY_NONE | HARDSER_DATA_8)
+#define SERIAL_5E1 (HARDSER_STOP_BIT_1 | HARDSER_PARITY_EVEN | HARDSER_DATA_5)
+#define SERIAL_6E1 (HARDSER_STOP_BIT_1 | HARDSER_PARITY_EVEN | HARDSER_DATA_6)
+#define SERIAL_7E1 (HARDSER_STOP_BIT_1 | HARDSER_PARITY_EVEN | HARDSER_DATA_7)
+#define SERIAL_8E1 (HARDSER_STOP_BIT_1 | HARDSER_PARITY_EVEN | HARDSER_DATA_8)
+#define SERIAL_5E2 (HARDSER_STOP_BIT_2 | HARDSER_PARITY_EVEN | HARDSER_DATA_5)
+#define SERIAL_6E2 (HARDSER_STOP_BIT_2 | HARDSER_PARITY_EVEN | HARDSER_DATA_6)
+#define SERIAL_7E2 (HARDSER_STOP_BIT_2 | HARDSER_PARITY_EVEN | HARDSER_DATA_7)
+#define SERIAL_8E2 (HARDSER_STOP_BIT_2 | HARDSER_PARITY_EVEN | HARDSER_DATA_8)
+#define SERIAL_5O1 (HARDSER_STOP_BIT_1 | HARDSER_PARITY_ODD | HARDSER_DATA_5)
+#define SERIAL_6O1 (HARDSER_STOP_BIT_1 | HARDSER_PARITY_ODD | HARDSER_DATA_6)
+#define SERIAL_7O1 (HARDSER_STOP_BIT_1 | HARDSER_PARITY_ODD | HARDSER_DATA_7)
+#define SERIAL_8O1 (HARDSER_STOP_BIT_1 | HARDSER_PARITY_ODD | HARDSER_DATA_8)
+#define SERIAL_5O2 (HARDSER_STOP_BIT_2 | HARDSER_PARITY_ODD | HARDSER_DATA_5)
+#define SERIAL_6O2 (HARDSER_STOP_BIT_2 | HARDSER_PARITY_ODD | HARDSER_DATA_6)
+#define SERIAL_7O2 (HARDSER_STOP_BIT_2 | HARDSER_PARITY_ODD | HARDSER_DATA_7)
+#define SERIAL_8O2 (HARDSER_STOP_BIT_2 | HARDSER_PARITY_ODD | HARDSER_DATA_8)
+
+class HardwareSerial : public Stream
+{
+ public:
+ virtual void begin(unsigned long);
+ virtual void begin(unsigned long baudrate, uint16_t config);
+ virtual void end();
+ virtual int available(void) = 0;
+ virtual int peek(void) = 0;
+ virtual int read(void) = 0;
+ virtual void flush(void) = 0;
+ virtual size_t write(uint8_t) = 0;
+ using Print::write; // pull in write(str) and write(buf, size) from Print
+ virtual operator bool() = 0;
+};
+
+extern void serialEventRun(void) __attribute__((weak));
+
+#endif
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/IPAddress.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/IPAddress.h
new file mode 100644
index 0000000000000000000000000000000000000000..d762f2c02b505288430370b011da0aa1ae2697a3
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/IPAddress.h
@@ -0,0 +1,78 @@
+/*
+ IPAddress.h - Base class that provides IPAddress
+ Copyright (c) 2011 Adrian McEwen. All right reserved.
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#ifndef IPAddress_h
+#define IPAddress_h
+
+#include <stdint.h>
+#include "Printable.h"
+#include "WString.h"
+
+// A class to make it easier to handle and pass around IP addresses
+
+class IPAddress : public Printable {
+private:
+ union {
+ uint8_t bytes[4]; // IPv4 address
+ uint32_t dword;
+ } _address;
+
+ // Access the raw byte array containing the address. Because this returns a pointer
+ // to the internal structure rather than a copy of the address this function should only
+ // be used when you know that the usage of the returned uint8_t* will be transient and not
+ // stored.
+ uint8_t* raw_address() { return _address.bytes; };
+
+public:
+ // Constructors
+ IPAddress();
+ IPAddress(uint8_t first_octet, uint8_t second_octet, uint8_t third_octet, uint8_t fourth_octet);
+ IPAddress(uint32_t address);
+ IPAddress(const uint8_t *address);
+
+ bool fromString(const char *address);
+ bool fromString(const String &address) { return fromString(address.c_str()); }
+
+ // Overloaded cast operator to allow IPAddress objects to be used where a pointer
+ // to a four-byte uint8_t array is expected
+ operator uint32_t() const { return _address.dword; };
+ bool operator==(const IPAddress& addr) const { return _address.dword == addr._address.dword; };
+ bool operator==(const uint8_t* addr) const;
+
+ // Overloaded index operator to allow getting and setting individual octets of the address
+ uint8_t operator[](int index) const { return _address.bytes[index]; };
+ uint8_t& operator[](int index) { return _address.bytes[index]; };
+
+ // Overloaded copy operators to allow initialisation of IPAddress objects from other types
+ IPAddress& operator=(const uint8_t *address);
+ IPAddress& operator=(uint32_t address);
+
+ virtual size_t printTo(Print& p) const;
+
+ friend class EthernetClass;
+ friend class UDP;
+ friend class Client;
+ friend class Server;
+ friend class DhcpClass;
+ friend class DNSClient;
+};
+
+const IPAddress INADDR_NONE(0,0,0,0);
+
+#endif
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/Print.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/Print.h
new file mode 100644
index 0000000000000000000000000000000000000000..dfb645cbbde8f5ede97627bf2c059b136674da77
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/Print.h
@@ -0,0 +1,92 @@
+/*
+ Copyright (c) 2014 Arduino. All right reserved.
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ See the GNU Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#ifndef Print_h
+#define Print_h
+
+#include <inttypes.h>
+#include <stdio.h> // for size_t
+
+#include "WString.h"
+#include "Printable.h"
+
+#define DEC 10
+#define HEX 16
+#define OCT 8
+#ifdef BIN // Prevent warnings if BIN is previously defined in "iotnx4.h" or similar
+#undef BIN
+#endif
+#define BIN 2
+
+class Print
+{
+ private:
+ int write_error;
+ size_t printNumber(unsigned long, uint8_t);
+ size_t printFloat(double, uint8_t);
+ protected:
+ void setWriteError(int err = 1) { write_error = err; }
+ public:
+ Print() : write_error(0) {}
+
+ int getWriteError() { return write_error; }
+ void clearWriteError() { setWriteError(0); }
+
+ virtual size_t write(uint8_t) = 0;
+ size_t write(const char *str) {
+ if (str == NULL) return 0;
+ return write((const uint8_t *)str, strlen(str));
+ }
+ virtual size_t write(const uint8_t *buffer, size_t size);
+ size_t write(const char *buffer, size_t size) {
+ return write((const uint8_t *)buffer, size);
+ }
+
+ // default to zero, meaning "a single write may block"
+ // should be overriden by subclasses with buffering
+ virtual int availableForWrite() { return 0; }
+
+ size_t print(const __FlashStringHelper *);
+ size_t print(const String &);
+ size_t print(const char[]);
+ size_t print(char);
+ size_t print(unsigned char, int = DEC);
+ size_t print(int, int = DEC);
+ size_t print(unsigned int, int = DEC);
+ size_t print(long, int = DEC);
+ size_t print(unsigned long, int = DEC);
+ size_t print(double, int = 2);
+ size_t print(const Printable&);
+
+ size_t println(const __FlashStringHelper *);
+ size_t println(const String &s);
+ size_t println(const char[]);
+ size_t println(char);
+ size_t println(unsigned char, int = DEC);
+ size_t println(int, int = DEC);
+ size_t println(unsigned int, int = DEC);
+ size_t println(long, int = DEC);
+ size_t println(unsigned long, int = DEC);
+ size_t println(double, int = 2);
+ size_t println(const Printable&);
+ size_t println(void);
+
+ virtual void flush() { /* Empty implementation for backward compatibility */ }
+};
+
+#endif
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/Printable.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/Printable.h
new file mode 100644
index 0000000000000000000000000000000000000000..34ad5b4dc02e056445b1dc68cd632a35d12d9960
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/Printable.h
@@ -0,0 +1,39 @@
+/*
+ Copyright (c) 2014 Arduino. All right reserved.
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ See the GNU Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#ifndef Printable_h
+#define Printable_h
+
+#include <stdlib.h>
+
+class Print;
+
+/** The Printable class provides a way for new classes to allow themselves to be printed.
+ By deriving from Printable and implementing the printTo method, it will then be possible
+ for users to print out instances of this class by passing them into the usual
+ Print::print and Print::println methods.
+*/
+
+class Printable
+{
+ public:
+ virtual size_t printTo(Print& p) const = 0;
+};
+
+#endif
+
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/Reset.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/Reset.h
new file mode 100644
index 0000000000000000000000000000000000000000..3b7e9fa69a7cb2e8a83b3fbd62c98de65696c761
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/Reset.h
@@ -0,0 +1,33 @@
+/*
+ Copyright (c) 2015 Arduino LLC. All right reserved.
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ See the GNU Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void initiateReset(int ms);
+void tickReset();
+void cancelReset();
+
+ __attribute__ ((weak)) void resetExternalChip() {};
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/RingBuffer.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/RingBuffer.h
new file mode 100644
index 0000000000000000000000000000000000000000..e706cc4f24ae0103597112c553e61a45fd607056
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/RingBuffer.h
@@ -0,0 +1,144 @@
+/*
+ Copyright (c) 2014 Arduino. All right reserved.
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ See the GNU Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#ifdef __cplusplus
+
+#ifndef _RING_BUFFER_
+#define _RING_BUFFER_
+
+#include <stdint.h>
+
+// Define constants and variables for buffering incoming serial data. We're
+// using a ring buffer (I think), in which head is the index of the location
+// to which to write the next incoming character and tail is the index of the
+// location from which to read.
+#ifndef SERIAL_BUFFER_SIZE
+#define SERIAL_BUFFER_SIZE 256
+#endif
+
+template <int N>
+class RingBufferN
+{
+ public:
+ uint8_t _aucBuffer[N] ;
+ volatile int _iHead ;
+ volatile int _iTail ;
+
+ public:
+ RingBufferN( void ) ;
+ void store_char( uint8_t c ) ;
+ void clear();
+ int read_char();
+ int available();
+ int availableForStore();
+ int peek();
+ bool isFull();
+
+ private:
+ int nextIndex(int index);
+};
+
+typedef RingBufferN<SERIAL_BUFFER_SIZE> RingBuffer;
+
+
+template <int N>
+RingBufferN<N>::RingBufferN( void )
+{
+ memset( _aucBuffer, 0, N ) ;
+ clear();
+}
+
+template <int N>
+void RingBufferN<N>::store_char( uint8_t c )
+{
+ int i = nextIndex(_iHead);
+
+ // if we should be storing the received character into the location
+ // just before the tail (meaning that the head would advance to the
+ // current location of the tail), we're about to overflow the buffer
+ // and so we don't write the character or advance the head.
+ if ( i != _iTail )
+ {
+ _aucBuffer[_iHead] = c ;
+ _iHead = i ;
+ }
+}
+
+template <int N>
+void RingBufferN<N>::clear()
+{
+ _iHead = 0;
+ _iTail = 0;
+}
+
+template <int N>
+int RingBufferN<N>::read_char()
+{
+ if(_iTail == _iHead)
+ return -1;
+
+ uint8_t value = _aucBuffer[_iTail];
+ _iTail = nextIndex(_iTail);
+
+ return value;
+}
+
+template <int N>
+int RingBufferN<N>::available()
+{
+ int delta = _iHead - _iTail;
+
+ if(delta < 0)
+ return N + delta;
+ else
+ return delta;
+}
+
+template <int N>
+int RingBufferN<N>::availableForStore()
+{
+ if (_iHead >= _iTail)
+ return N - 1 - _iHead + _iTail;
+ else
+ return _iTail - _iHead - 1;
+}
+
+template <int N>
+int RingBufferN<N>::peek()
+{
+ if(_iTail == _iHead)
+ return -1;
+
+ return _aucBuffer[_iTail];
+}
+
+template <int N>
+int RingBufferN<N>::nextIndex(int index)
+{
+ return (uint32_t)(index + 1) % N;
+}
+
+template <int N>
+bool RingBufferN<N>::isFull()
+{
+ return (nextIndex(_iHead) == _iTail);
+}
+
+#endif /* _RING_BUFFER_ */
+
+#endif /* __cplusplus */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/SERCOM.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/SERCOM.h
new file mode 100644
index 0000000000000000000000000000000000000000..6f855af1935d91c73ea9bd2e0f64e9176e77d4df
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/SERCOM.h
@@ -0,0 +1,223 @@
+/*
+ Copyright (c) 2014 Arduino. All right reserved.
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ See the GNU Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#ifndef _SERCOM_CLASS_
+#define _SERCOM_CLASS_
+
+#include "sam.h"
+
+#define SERCOM_FREQ_REF 48000000
+#define SERCOM_NVIC_PRIORITY ((1<<__NVIC_PRIO_BITS) - 1)
+
+typedef enum
+{
+ UART_EXT_CLOCK = 0,
+ UART_INT_CLOCK = 0x1u
+} SercomUartMode;
+
+typedef enum
+{
+ SPI_SLAVE_OPERATION = 0x2u,
+ SPI_MASTER_OPERATION = 0x3u
+} SercomSpiMode;
+
+typedef enum
+{
+ I2C_SLAVE_OPERATION = 0x4u,
+ I2C_MASTER_OPERATION = 0x5u
+} SercomI2CMode;
+
+typedef enum
+{
+ SERCOM_EVEN_PARITY = 0,
+ SERCOM_ODD_PARITY,
+ SERCOM_NO_PARITY
+} SercomParityMode;
+
+typedef enum
+{
+ SERCOM_STOP_BIT_1 = 0,
+ SERCOM_STOP_BITS_2
+} SercomNumberStopBit;
+
+typedef enum
+{
+ MSB_FIRST = 0,
+ LSB_FIRST
+} SercomDataOrder;
+
+typedef enum
+{
+ UART_CHAR_SIZE_8_BITS = 0,
+ UART_CHAR_SIZE_9_BITS,
+ UART_CHAR_SIZE_5_BITS = 0x5u,
+ UART_CHAR_SIZE_6_BITS,
+ UART_CHAR_SIZE_7_BITS
+} SercomUartCharSize;
+
+typedef enum
+{
+ SERCOM_RX_PAD_0 = 0,
+ SERCOM_RX_PAD_1,
+ SERCOM_RX_PAD_2,
+ SERCOM_RX_PAD_3
+} SercomRXPad;
+
+typedef enum
+{
+ UART_TX_PAD_0 = 0x0ul, // Only for UART
+ UART_TX_PAD_2 = 0x1ul, // Only for UART
+ UART_TX_RTS_CTS_PAD_0_2_3 = 0x2ul, // Only for UART with TX on PAD0, RTS on PAD2 and CTS on PAD3
+} SercomUartTXPad;
+
+typedef enum
+{
+ SAMPLE_RATE_x16 = 0x1, //Fractional
+ SAMPLE_RATE_x8 = 0x3, //Fractional
+} SercomUartSampleRate;
+
+typedef enum
+{
+ SERCOM_SPI_MODE_0 = 0, // CPOL : 0 | CPHA : 0
+ SERCOM_SPI_MODE_1, // CPOL : 0 | CPHA : 1
+ SERCOM_SPI_MODE_2, // CPOL : 1 | CPHA : 0
+ SERCOM_SPI_MODE_3 // CPOL : 1 | CPHA : 1
+} SercomSpiClockMode;
+
+typedef enum
+{
+ SPI_PAD_0_SCK_1 = 0,
+ SPI_PAD_2_SCK_3,
+ SPI_PAD_3_SCK_1,
+ SPI_PAD_0_SCK_3
+} SercomSpiTXPad;
+
+typedef enum
+{
+ SPI_CHAR_SIZE_8_BITS = 0x0ul,
+ SPI_CHAR_SIZE_9_BITS
+} SercomSpiCharSize;
+
+typedef enum
+{
+ WIRE_UNKNOWN_STATE = 0x0ul,
+ WIRE_IDLE_STATE,
+ WIRE_OWNER_STATE,
+ WIRE_BUSY_STATE
+} SercomWireBusState;
+
+typedef enum
+{
+ WIRE_WRITE_FLAG = 0x0ul,
+ WIRE_READ_FLAG
+} SercomWireReadWriteFlag;
+
+typedef enum
+{
+ WIRE_MASTER_ACT_NO_ACTION = 0,
+ WIRE_MASTER_ACT_REPEAT_START,
+ WIRE_MASTER_ACT_READ,
+ WIRE_MASTER_ACT_STOP
+} SercomMasterCommandWire;
+
+typedef enum
+{
+ WIRE_MASTER_ACK_ACTION = 0,
+ WIRE_MASTER_NACK_ACTION
+} SercomMasterAckActionWire;
+
+class SERCOM
+{
+ public:
+ SERCOM(Sercom* s) ;
+
+ /* ========== UART ========== */
+ void initUART(SercomUartMode mode, SercomUartSampleRate sampleRate, uint32_t baudrate=0) ;
+ void initFrame(SercomUartCharSize charSize, SercomDataOrder dataOrder, SercomParityMode parityMode, SercomNumberStopBit nbStopBits) ;
+ void initPads(SercomUartTXPad txPad, SercomRXPad rxPad) ;
+
+ void resetUART( void ) ;
+ void enableUART( void ) ;
+ void flushUART( void ) ;
+ void clearStatusUART( void ) ;
+ bool availableDataUART( void ) ;
+ bool isBufferOverflowErrorUART( void ) ;
+ bool isFrameErrorUART( void ) ;
+ void clearFrameErrorUART( void ) ;
+ bool isParityErrorUART( void ) ;
+ bool isDataRegisterEmptyUART( void ) ;
+ uint8_t readDataUART( void ) ;
+ int writeDataUART(uint8_t data) ;
+ bool isUARTError() ;
+ void acknowledgeUARTError() ;
+ void enableDataRegisterEmptyInterruptUART();
+ void disableDataRegisterEmptyInterruptUART();
+
+ /* ========== SPI ========== */
+ void initSPI(SercomSpiTXPad mosi, SercomRXPad miso, SercomSpiCharSize charSize, SercomDataOrder dataOrder) ;
+ void initSPIClock(SercomSpiClockMode clockMode, uint32_t baudrate) ;
+
+ void resetSPI( void ) ;
+ void enableSPI( void ) ;
+ void disableSPI( void ) ;
+ void setDataOrderSPI(SercomDataOrder dataOrder) ;
+ SercomDataOrder getDataOrderSPI( void ) ;
+ void setBaudrateSPI(uint8_t divider) ;
+ void setClockModeSPI(SercomSpiClockMode clockMode) ;
+ uint8_t transferDataSPI(uint8_t data) ;
+ bool isBufferOverflowErrorSPI( void ) ;
+ bool isDataRegisterEmptySPI( void ) ;
+ bool isTransmitCompleteSPI( void ) ;
+ bool isReceiveCompleteSPI( void ) ;
+
+ /* ========== WIRE ========== */
+ void initSlaveWIRE(uint8_t address, bool enableGeneralCall = false) ;
+ void initMasterWIRE(uint32_t baudrate) ;
+
+ void resetWIRE( void ) ;
+ void enableWIRE( void ) ;
+ void disableWIRE( void );
+ void prepareNackBitWIRE( void ) ;
+ void prepareAckBitWIRE( void ) ;
+ void prepareCommandBitsWire(uint8_t cmd);
+ bool startTransmissionWIRE(uint8_t address, SercomWireReadWriteFlag flag) ;
+ bool sendDataMasterWIRE(uint8_t data) ;
+ bool sendDataSlaveWIRE(uint8_t data) ;
+ bool isMasterWIRE( void ) ;
+ bool isSlaveWIRE( void ) ;
+ bool isBusIdleWIRE( void ) ;
+ bool isBusOwnerWIRE( void ) ;
+ bool isArbLostWIRE( void );
+ bool isBusBusyWIRE( void );
+ bool isDataReadyWIRE( void ) ;
+ bool isStopDetectedWIRE( void ) ;
+ bool isRestartDetectedWIRE( void ) ;
+ bool isAddressMatch( void ) ;
+ bool isMasterReadOperationWIRE( void ) ;
+ bool isRXNackReceivedWIRE( void ) ;
+ int availableWIRE( void ) ;
+ uint8_t readDataWIRE( void ) ;
+
+ private:
+ Sercom* sercom;
+ uint8_t calculateBaudrateSynchronous(uint32_t baudrate) ;
+ uint32_t division(uint32_t dividend, uint32_t divisor) ;
+ void initClockNVIC( void ) ;
+};
+
+#endif
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/Server.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/Server.h
new file mode 100644
index 0000000000000000000000000000000000000000..69e3e39fe68a8a519b104ce6a83b8d094a6953da
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/Server.h
@@ -0,0 +1,30 @@
+/*
+ Server.h - Base class that provides Server
+ Copyright (c) 2011 Adrian McEwen. All right reserved.
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#ifndef server_h
+#define server_h
+
+#include "Print.h"
+
+class Server : public Print {
+public:
+ virtual void begin() =0;
+};
+
+#endif
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/Stream.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/Stream.h
new file mode 100644
index 0000000000000000000000000000000000000000..c3311c3cd4080f58e24badf8917c3d3fcf9accf3
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/Stream.h
@@ -0,0 +1,129 @@
+/*
+ Stream.h - base class for character-based streams.
+ Copyright (c) 2010 David A. Mellis. All right reserved.
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+
+ parsing functions based on TextFinder library by Michael Margolis
+*/
+
+#ifndef Stream_h
+#define Stream_h
+
+#include <inttypes.h>
+#include "Print.h"
+
+// compatability macros for testing
+/*
+#define getInt() parseInt()
+#define getInt(ignore) parseInt(ignore)
+#define getFloat() parseFloat()
+#define getFloat(ignore) parseFloat(ignore)
+#define getString( pre_string, post_string, buffer, length)
+readBytesBetween( pre_string, terminator, buffer, length)
+*/
+
+// This enumeration provides the lookahead options for parseInt(), parseFloat()
+// The rules set out here are used until either the first valid character is found
+// or a time out occurs due to lack of input.
+enum LookaheadMode{
+ SKIP_ALL, // All invalid characters are ignored.
+ SKIP_NONE, // Nothing is skipped, and the stream is not touched unless the first waiting character is valid.
+ SKIP_WHITESPACE // Only tabs, spaces, line feeds & carriage returns are skipped.
+};
+
+#define NO_IGNORE_CHAR '\x01' // a char not found in a valid ASCII numeric field
+
+class Stream : public Print
+{
+ protected:
+ unsigned long _timeout; // number of milliseconds to wait for the next char before aborting timed read
+ unsigned long _startMillis; // used for timeout measurement
+ int timedRead(); // read stream with timeout
+ int timedPeek(); // peek stream with timeout
+ int peekNextDigit(LookaheadMode lookahead, bool detectDecimal); // returns the next numeric digit in the stream or -1 if timeout
+
+ public:
+ virtual int available() = 0;
+ virtual int read() = 0;
+ virtual int peek() = 0;
+
+ Stream() {_timeout=1000;}
+
+// parsing methods
+
+ void setTimeout(unsigned long timeout); // sets maximum milliseconds to wait for stream data, default is 1 second
+ unsigned long getTimeout(void) { return _timeout; }
+
+ bool find(char *target); // reads data from the stream until the target string is found
+ bool find(uint8_t *target) { return find ((char *)target); }
+ // returns true if target string is found, false if timed out (see setTimeout)
+
+ bool find(char *target, size_t length); // reads data from the stream until the target string of given length is found
+ bool find(uint8_t *target, size_t length) { return find ((char *)target, length); }
+ // returns true if target string is found, false if timed out
+
+ bool find(char target) { return find (&target, 1); }
+
+ bool findUntil(char *target, char *terminator); // as find but search ends if the terminator string is found
+ bool findUntil(uint8_t *target, char *terminator) { return findUntil((char *)target, terminator); }
+
+ bool findUntil(char *target, size_t targetLen, char *terminate, size_t termLen); // as above but search ends if the terminate string is found
+ bool findUntil(uint8_t *target, size_t targetLen, char *terminate, size_t termLen) {return findUntil((char *)target, targetLen, terminate, termLen); }
+
+ long parseInt(LookaheadMode lookahead = SKIP_ALL, char ignore = NO_IGNORE_CHAR);
+ // returns the first valid (long) integer value from the current position.
+ // lookahead determines how parseInt looks ahead in the stream.
+ // See LookaheadMode enumeration at the top of the file.
+ // Lookahead is terminated by the first character that is not a valid part of an integer.
+ // Once parsing commences, 'ignore' will be skipped in the stream.
+
+ float parseFloat(LookaheadMode lookahead = SKIP_ALL, char ignore = NO_IGNORE_CHAR);
+ // float version of parseInt
+
+ size_t readBytes( char *buffer, size_t length); // read chars from stream into buffer
+ size_t readBytes( uint8_t *buffer, size_t length) { return readBytes((char *)buffer, length); }
+ // terminates if length characters have been read or timeout (see setTimeout)
+ // returns the number of characters placed in the buffer (0 means no valid data found)
+
+ size_t readBytesUntil( char terminator, char *buffer, size_t length); // as readBytes with terminator character
+ size_t readBytesUntil( char terminator, uint8_t *buffer, size_t length) { return readBytesUntil(terminator, (char *)buffer, length); }
+ // terminates if length characters have been read, timeout, or if the terminator character detected
+ // returns the number of characters placed in the buffer (0 means no valid data found)
+
+ // Arduino String functions to be added here
+ String readString();
+ String readStringUntil(char terminator);
+
+ protected:
+ long parseInt(char ignore) { return parseInt(SKIP_ALL, ignore); }
+ float parseFloat(char ignore) { return parseFloat(SKIP_ALL, ignore); }
+ // These overload exists for compatibility with any class that has derived
+ // Stream and used parseFloat/Int with a custom ignore character. To keep
+ // the public API simple, these overload remains protected.
+
+ struct MultiTarget {
+ const char *str; // string you're searching for
+ size_t len; // length of string you're searching for
+ size_t index; // index used by the search routine.
+ };
+
+ // This allows you to search for an arbitrary number of strings.
+ // Returns index of the target that is found first or -1 if timeout occurs.
+ int findMulti(struct MultiTarget *targets, int tCount);
+};
+
+#undef NO_IGNORE_CHAR
+#endif
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/Tone.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/Tone.h
new file mode 100644
index 0000000000000000000000000000000000000000..cf27051602f766fe2b62bb38aeb8383ee3fdcab6
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/Tone.h
@@ -0,0 +1,28 @@
+/*
+ Copyright (c) 2015 Arduino LLC. All right reserved.
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ See the GNU Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#pragma once
+
+#ifdef __cplusplus
+
+#include "Arduino.h"
+
+void tone(uint32_t _pin, uint32_t frequency, uint32_t duration = 0);
+void noTone(uint32_t _pin);
+
+#endif
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/USB/CDC.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/USB/CDC.h
new file mode 100644
index 0000000000000000000000000000000000000000..a19f588f3e45a25cd94a93e4231edbe4cfe44d8a
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/USB/CDC.h
@@ -0,0 +1,161 @@
+#ifndef __CDC_H__
+#define __CDC_H__
+
+#ifdef CDC_ENABLED
+
+#include "USBDesc.h"
+#include "USBAPI.h"
+#include "PluggableUSB.h"
+
+
+#define CDC_V1_10 0x0110
+#define CDC_COMMUNICATION_INTERFACE_CLASS 0x02
+
+#define CDC_CALL_MANAGEMENT 0x01
+#define CDC_ABSTRACT_CONTROL_MODEL 0x02
+#define CDC_HEADER 0x00
+#define CDC_ABSTRACT_CONTROL_MANAGEMENT 0x02
+#define CDC_UNION 0x06
+#define CDC_CS_INTERFACE 0x24
+#define CDC_CS_ENDPOINT 0x25
+#define CDC_DATA_INTERFACE_CLASS 0x0A
+
+// CDC CS interface descriptor
+typedef struct
+{
+ uint8_t len; // 5
+ uint8_t dtype; // 0x24
+ uint8_t subtype;
+ uint8_t d0;
+ uint8_t d1;
+} CDCCSInterfaceDescriptor;
+
+typedef struct
+{
+ uint8_t len; // 4
+ uint8_t dtype; // 0x24
+ uint8_t subtype;
+ uint8_t d0;
+} CDCCSInterfaceDescriptor4;
+
+typedef struct
+{
+ uint8_t len;
+ uint8_t dtype; // 0x24
+ uint8_t subtype; // 1
+ uint8_t bmCapabilities;
+ uint8_t bDataInterface;
+} CMFunctionalDescriptor;
+
+typedef struct
+{
+ uint8_t len;
+ uint8_t dtype; // 0x24
+ uint8_t subtype; // 1
+ uint8_t bmCapabilities;
+} ACMFunctionalDescriptor;
+
+typedef struct
+{
+ // IAD
+ IADDescriptor iad; // Only needed on compound device
+ // Control
+ InterfaceDescriptor cif;
+ CDCCSInterfaceDescriptor header;
+ ACMFunctionalDescriptor controlManagement; // ACM
+ CDCCSInterfaceDescriptor functionalDescriptor; // CDC_UNION
+ CMFunctionalDescriptor callManagement; // Call Management
+ EndpointDescriptor cifin;
+
+ // Data
+ InterfaceDescriptor dif;
+ EndpointDescriptor in;
+ EndpointDescriptor out;
+} CDCDescriptor;
+
+
+//================================================================================
+// Serial over CDC (Serial1 is the physical port)
+
+class Serial_ : public Stream, public PluggableUSBModule {
+public:
+ Serial_(USBDeviceClass &_usb);
+
+ void begin(uint32_t baud_count);
+ void begin(unsigned long, uint8_t);
+ void end(void);
+
+ virtual int available(void);
+ virtual int availableForWrite(void);
+ virtual int peek(void);
+ virtual int read(void);
+ virtual void flush(void);
+ virtual void clear(void);
+ virtual size_t write(uint8_t);
+ virtual size_t write(const uint8_t *buffer, size_t size);
+ using Print::write; // pull in write(str) from Print
+ operator bool();
+
+ size_t readBytes(char *buffer, size_t length);
+
+ // This method allows processing "SEND_BREAK" requests sent by
+ // the USB host. Those requests indicate that the host wants to
+ // send a BREAK signal and are accompanied by a single uint16_t
+ // value, specifying the duration of the break. The value 0
+ // means to end any current break, while the value 0xffff means
+ // to start an indefinite break.
+ // readBreak() will return the value of the most recent break
+ // request, but will return it at most once, returning -1 when
+ // readBreak() is called again (until another break request is
+ // received, which is again returned once).
+ // This also mean that if two break requests are received
+ // without readBreak() being called in between, the value of the
+ // first request is lost.
+ // Note that the value returned is a long, so it can return
+ // 0-0xffff as well as -1.
+ int32_t readBreak();
+
+ // These return the settings specified by the USB host for the
+ // serial port. These aren't really used, but are offered here
+ // in case a sketch wants to act on these settings.
+ uint32_t baud();
+ uint8_t stopbits();
+ uint8_t paritytype();
+ uint8_t numbits();
+ bool dtr();
+ bool rts();
+ enum {
+ ONE_STOP_BIT = 0,
+ ONE_AND_HALF_STOP_BIT = 1,
+ TWO_STOP_BITS = 2,
+ };
+ enum {
+ NO_PARITY = 0,
+ ODD_PARITY = 1,
+ EVEN_PARITY = 2,
+ MARK_PARITY = 3,
+ SPACE_PARITY = 4,
+ };
+
+protected:
+ // Implementation of the PUSBListNode
+ int getInterface(uint8_t* interfaceNum);
+ int getDescriptor(USBSetup& setup);
+ bool setup(USBSetup& setup);
+ uint8_t getShortName(char* name);
+ void handleEndpoint(int ep);
+ void enableInterrupt();
+
+friend USBDeviceClass;
+
+private:
+ int availableForStore(void);
+
+ USBDeviceClass &usb;
+ bool stalled;
+ uint32_t epType[3];
+};
+extern Serial_ SerialUSB;
+
+#endif
+#endif
\ No newline at end of file
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/USB/PluggableUSB.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/USB/PluggableUSB.h
new file mode 100644
index 0000000000000000000000000000000000000000..e1d8cfa3a6fa26f8aaf6a4313b6716e338c8fd1d
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/USB/PluggableUSB.h
@@ -0,0 +1,76 @@
+/*
+ PluggableUSB.h
+ Copyright (c) 2015 Arduino LLC
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#ifndef PUSB_h
+#define PUSB_h
+
+#include "USBAPI.h"
+#include <cstddef>
+
+#if defined(USBCON)
+
+class PluggableUSBModule {
+public:
+ PluggableUSBModule(uint8_t numEps, uint8_t numIfs, uint32_t *epType) :
+ numEndpoints(numEps), numInterfaces(numIfs), endpointType(epType)
+ { }
+
+protected:
+ virtual bool setup(USBSetup& setup) = 0;
+ virtual int getInterface(uint8_t* interfaceCount) = 0;
+ virtual int getDescriptor(USBSetup& setup) = 0;
+ virtual void handleEndpoint(int /* ep */) { /* Do nothing */ }
+ virtual uint8_t getShortName(char *name) { name[0] = 'A'+pluggedInterface; return 1; }
+
+ uint8_t pluggedInterface;
+ uint8_t pluggedEndpoint;
+
+ const uint8_t numEndpoints;
+ const uint8_t numInterfaces;
+ const uint32_t *endpointType;
+
+ PluggableUSBModule *next = NULL;
+
+ friend class PluggableUSB_;
+};
+
+class PluggableUSB_ {
+public:
+ PluggableUSB_();
+ bool plug(PluggableUSBModule *node);
+ int getInterface(uint8_t* interfaceCount);
+ int getDescriptor(USBSetup& setup);
+ bool setup(USBSetup& setup);
+ void handleEndpoint(int ep);
+ uint8_t getShortName(char *iSerialNum);
+
+private:
+ uint8_t lastIf;
+ uint8_t lastEp;
+ PluggableUSBModule* rootNode;
+};
+
+// Replacement for global singleton.
+// This function prevents static-initialization-order-fiasco
+// https://isocpp.org/wiki/faq/ctors#static-init-order-on-first-use
+PluggableUSB_& PluggableUSB();
+
+#endif
+
+#endif
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/USB/SAMD21_USBDevice.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/USB/SAMD21_USBDevice.h
new file mode 100644
index 0000000000000000000000000000000000000000..2bb71a408e932dc24800d4f1fe0468279cc796ba
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/USB/SAMD21_USBDevice.h
@@ -0,0 +1,436 @@
+/*
+ Copyright (c) 2015 Arduino LLC. All right reserved.
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ See the GNU Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#pragma once
+
+#include <Arduino.h>
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <stdint.h>
+
+typedef uint8_t ep_t;
+
+class USBDevice_SAMD21G18x {
+public:
+ USBDevice_SAMD21G18x() : usb(USB->DEVICE) {
+ // Empty
+ }
+
+ // USB Device function mapping
+ // ---------------------------
+
+ // Reset USB Device
+ inline void reset();
+
+ // Enable
+ inline void enable() { usb.CTRLA.bit.ENABLE = 1; }
+ inline void disable() { usb.CTRLA.bit.ENABLE = 0; }
+
+ // USB mode (device/host)
+ inline void setUSBDeviceMode() { usb.CTRLA.bit.MODE = USB_CTRLA_MODE_DEVICE_Val; }
+ inline void setUSBHostMode() { usb.CTRLA.bit.MODE = USB_CTRLA_MODE_HOST_Val; }
+
+ inline void runInStandby() { usb.CTRLA.bit.RUNSTDBY = 1; }
+ inline void noRunInStandby() { usb.CTRLA.bit.RUNSTDBY = 0; }
+ inline void wakeupHost() { usb.CTRLB.bit.UPRSM = 1; }
+
+ // USB speed
+ inline void setFullSpeed() { usb.CTRLB.bit.SPDCONF = USB_DEVICE_CTRLB_SPDCONF_FS_Val; }
+ inline void setLowSpeed() { usb.CTRLB.bit.SPDCONF = USB_DEVICE_CTRLB_SPDCONF_LS_Val; }
+ inline void setHiSpeed() { usb.CTRLB.bit.SPDCONF = USB_DEVICE_CTRLB_SPDCONF_HS_Val; }
+ inline void setHiSpeedTestMode() { usb.CTRLB.bit.SPDCONF = USB_DEVICE_CTRLB_SPDCONF_HSTM_Val; }
+
+ // Authorize attach if Vbus is present
+ inline void attach() { usb.CTRLB.bit.DETACH = 0; }
+ inline void detach() { usb.CTRLB.bit.DETACH = 1; }
+
+ // USB Interrupts
+ inline bool isEndOfResetInterrupt() { return usb.INTFLAG.bit.EORST; }
+ inline void ackEndOfResetInterrupt() { usb.INTFLAG.reg = USB_DEVICE_INTFLAG_EORST; }
+ inline void enableEndOfResetInterrupt() { usb.INTENSET.bit.EORST = 1; }
+ inline void disableEndOfResetInterrupt() { usb.INTENCLR.bit.EORST = 1; }
+
+ inline bool isStartOfFrameInterrupt() { return usb.INTFLAG.bit.SOF; }
+ inline void ackStartOfFrameInterrupt() { usb.INTFLAG.reg = USB_DEVICE_INTFLAG_SOF; }
+ inline void enableStartOfFrameInterrupt() { usb.INTENSET.bit.SOF = 1; }
+ inline void disableStartOfFrameInterrupt() { usb.INTENCLR.bit.SOF = 1; }
+
+ // USB Address
+ inline void setAddress(uint32_t addr) { usb.DADD.bit.DADD = addr; usb.DADD.bit.ADDEN = 1; }
+ inline void unsetAddress() { usb.DADD.bit.DADD = 0; usb.DADD.bit.ADDEN = 0; }
+
+ // Frame number
+ inline uint16_t frameNumber() { return usb.FNUM.bit.FNUM; }
+
+ // Load calibration values
+ inline void calibrate();
+
+ // USB Device Endpoints function mapping
+ // -------------------------------------
+
+ // Config
+ inline void epBank0SetType(ep_t ep, uint8_t type) { usb.DeviceEndpoint[ep].EPCFG.bit.EPTYPE0 = type; }
+ inline void epBank1SetType(ep_t ep, uint8_t type) { usb.DeviceEndpoint[ep].EPCFG.bit.EPTYPE1 = type; }
+
+ // Interrupts
+ inline uint16_t epInterruptSummary() { return usb.EPINTSMRY.reg; }
+
+ inline bool epHasPendingInterrupts(ep_t ep) { return usb.DeviceEndpoint[ep].EPINTFLAG.reg != 0; }
+ inline bool epBank0IsSetupReceived(ep_t ep) { return usb.DeviceEndpoint[ep].EPINTFLAG.bit.RXSTP; }
+ inline bool epBank0IsStalled(ep_t ep) { return usb.DeviceEndpoint[ep].EPINTFLAG.bit.STALL0; }
+ inline bool epBank1IsStalled(ep_t ep) { return usb.DeviceEndpoint[ep].EPINTFLAG.bit.STALL1; }
+ inline bool epBank0IsTransferFailed(ep_t ep) { return usb.DeviceEndpoint[ep].EPINTFLAG.bit.TRFAIL0; }
+ inline bool epBank1IsTransferFailed(ep_t ep) { return usb.DeviceEndpoint[ep].EPINTFLAG.bit.TRFAIL1; }
+ inline bool epBank0IsTransferComplete(ep_t ep) { return usb.DeviceEndpoint[ep].EPINTFLAG.bit.TRCPT0; }
+ inline bool epBank1IsTransferComplete(ep_t ep) { return usb.DeviceEndpoint[ep].EPINTFLAG.bit.TRCPT1; }
+
+ inline void epAckPendingInterrupts(ep_t ep) { usb.DeviceEndpoint[ep].EPINTFLAG.reg = 0x7F; }
+ inline void epBank0AckSetupReceived(ep_t ep) { usb.DeviceEndpoint[ep].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP; }
+ inline void epBank0AckStalled(ep_t ep) { usb.DeviceEndpoint[ep].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL(1); }
+ inline void epBank1AckStalled(ep_t ep) { usb.DeviceEndpoint[ep].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL(2); }
+ inline void epBank0AckTransferFailed(ep_t ep) { usb.DeviceEndpoint[ep].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL(1); }
+ inline void epBank1AckTransferFailed(ep_t ep) { usb.DeviceEndpoint[ep].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL(2); }
+ inline void epBank0AckTransferComplete(ep_t ep) { usb.DeviceEndpoint[ep].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT(1); }
+ inline void epBank1AckTransferComplete(ep_t ep) { usb.DeviceEndpoint[ep].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT(2); }
+
+ inline void epBank0EnableSetupReceived(ep_t ep) { usb.DeviceEndpoint[ep].EPINTENSET.bit.RXSTP = 1; }
+ inline void epBank0EnableStalled(ep_t ep) { usb.DeviceEndpoint[ep].EPINTENSET.bit.STALL0 = 1; }
+ inline void epBank1EnableStalled(ep_t ep) { usb.DeviceEndpoint[ep].EPINTENSET.bit.STALL1 = 1; }
+ inline void epBank0EnableTransferFailed(ep_t ep) { usb.DeviceEndpoint[ep].EPINTENSET.bit.TRFAIL0 = 1; }
+ inline void epBank1EnableTransferFailed(ep_t ep) { usb.DeviceEndpoint[ep].EPINTENSET.bit.TRFAIL1 = 1; }
+ inline void epBank0EnableTransferComplete(ep_t ep) { usb.DeviceEndpoint[ep].EPINTENSET.bit.TRCPT0 = 1; }
+ inline void epBank1EnableTransferComplete(ep_t ep) { usb.DeviceEndpoint[ep].EPINTENSET.bit.TRCPT1 = 1; }
+
+ inline void epBank0DisableSetupReceived(ep_t ep) { usb.DeviceEndpoint[ep].EPINTENCLR.bit.RXSTP = 1; }
+ inline void epBank0DisableStalled(ep_t ep) { usb.DeviceEndpoint[ep].EPINTENCLR.bit.STALL0 = 1; }
+ inline void epBank1DisableStalled(ep_t ep) { usb.DeviceEndpoint[ep].EPINTENCLR.bit.STALL1 = 1; }
+ inline void epBank0DisableTransferFailed(ep_t ep) { usb.DeviceEndpoint[ep].EPINTENCLR.bit.TRFAIL0 = 1; }
+ inline void epBank1DisableTransferFailed(ep_t ep) { usb.DeviceEndpoint[ep].EPINTENCLR.bit.TRFAIL1 = 1; }
+ inline void epBank0DisableTransferComplete(ep_t ep) { usb.DeviceEndpoint[ep].EPINTENCLR.bit.TRCPT0 = 1; }
+ inline void epBank1DisableTransferComplete(ep_t ep) { usb.DeviceEndpoint[ep].EPINTENCLR.bit.TRCPT1 = 1; }
+
+ // Status
+ inline bool epBank0IsReady(ep_t ep) { return usb.DeviceEndpoint[ep].EPSTATUS.bit.BK0RDY; }
+ inline bool epBank1IsReady(ep_t ep) { return usb.DeviceEndpoint[ep].EPSTATUS.bit.BK1RDY; }
+ inline void epBank0SetReady(ep_t ep) { usb.DeviceEndpoint[ep].EPSTATUSSET.bit.BK0RDY = 1; }
+ inline void epBank1SetReady(ep_t ep) { usb.DeviceEndpoint[ep].EPSTATUSSET.bit.BK1RDY = 1; }
+ inline void epBank0ResetReady(ep_t ep) { usb.DeviceEndpoint[ep].EPSTATUSCLR.bit.BK0RDY = 1; }
+ inline void epBank1ResetReady(ep_t ep) { usb.DeviceEndpoint[ep].EPSTATUSCLR.bit.BK1RDY = 1; }
+
+ inline void epBank0SetStallReq(ep_t ep) { usb.DeviceEndpoint[ep].EPSTATUSSET.bit.STALLRQ0 = 1; }
+ inline void epBank1SetStallReq(ep_t ep) { usb.DeviceEndpoint[ep].EPSTATUSSET.bit.STALLRQ1 = 1; }
+ inline void epBank0ResetStallReq(ep_t ep) { usb.DeviceEndpoint[ep].EPSTATUSCLR.bit.STALLRQ0 = 1; }
+ inline void epBank1ResetStallReq(ep_t ep) { usb.DeviceEndpoint[ep].EPSTATUSCLR.bit.STALLRQ1 = 1; }
+
+ // Packet
+ inline uint16_t epBank0ByteCount(ep_t ep) { return EP[ep].DeviceDescBank[0].PCKSIZE.bit.BYTE_COUNT; }
+ inline uint16_t epBank1ByteCount(ep_t ep) { return EP[ep].DeviceDescBank[1].PCKSIZE.bit.BYTE_COUNT; }
+ inline void epBank0SetByteCount(ep_t ep, uint16_t bc) { EP[ep].DeviceDescBank[0].PCKSIZE.bit.BYTE_COUNT = bc; }
+ inline void epBank1SetByteCount(ep_t ep, uint16_t bc) { EP[ep].DeviceDescBank[1].PCKSIZE.bit.BYTE_COUNT = bc; }
+ inline void epBank0SetMultiPacketSize(ep_t ep, uint16_t s) { EP[ep].DeviceDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE = s; }
+ inline void epBank1SetMultiPacketSize(ep_t ep, uint16_t s) { EP[ep].DeviceDescBank[1].PCKSIZE.bit.MULTI_PACKET_SIZE = s; }
+
+ inline void epBank0SetAddress(ep_t ep, void *addr) { EP[ep].DeviceDescBank[0].ADDR.reg = (uint32_t)addr; }
+ inline void epBank1SetAddress(ep_t ep, void *addr) { EP[ep].DeviceDescBank[1].ADDR.reg = (uint32_t)addr; }
+ inline void epBank0SetSize(ep_t ep, uint16_t size) { EP[ep].DeviceDescBank[0].PCKSIZE.bit.SIZE = EP_PCKSIZE_SIZE(size); }
+ inline void epBank1SetSize(ep_t ep, uint16_t size) { EP[ep].DeviceDescBank[1].PCKSIZE.bit.SIZE = EP_PCKSIZE_SIZE(size); }
+ inline uint8_t EP_PCKSIZE_SIZE(uint16_t size) {
+ switch (size) {
+ case 8: return 0;
+ case 16: return 1;
+ case 32: return 2;
+ case 64: return 3;
+ case 128: return 4;
+ case 256: return 5;
+ case 512: return 6;
+ case 1023: return 7;
+ default: return 0;
+ }
+ }
+
+ inline void epBank0DisableAutoZLP(ep_t ep) { EP[ep].DeviceDescBank[0].PCKSIZE.bit.AUTO_ZLP = 0; }
+ inline void epBank1DisableAutoZLP(ep_t ep) { EP[ep].DeviceDescBank[1].PCKSIZE.bit.AUTO_ZLP = 0; }
+ inline void epBank0EnableAutoZLP(ep_t ep) { EP[ep].DeviceDescBank[0].PCKSIZE.bit.AUTO_ZLP = 1; }
+ inline void epBank1EnableAutoZLP(ep_t ep) { EP[ep].DeviceDescBank[1].PCKSIZE.bit.AUTO_ZLP = 1; }
+
+ // USB Device Endpoint transactions helpers
+ // ----------------------------------------
+
+ inline void epReleaseOutBank0(ep_t ep, uint16_t s) {
+ epBank0SetMultiPacketSize(ep, s);
+ epBank0SetByteCount(ep, 0);
+ epBank0ResetReady(ep);
+ }
+
+private:
+ // USB Device registers
+ UsbDevice &usb;
+
+ // Endpoints descriptors table
+ __attribute__((__aligned__(4))) UsbDeviceDescriptor EP[USB_EPT_NUM];
+};
+
+void USBDevice_SAMD21G18x::reset() {
+ usb.CTRLA.bit.SWRST = 1;
+ memset(EP, 0, sizeof(EP));
+ while (usb.SYNCBUSY.bit.SWRST) {}
+ usb.DESCADD.reg = (uint32_t)(&EP);
+}
+
+void USBDevice_SAMD21G18x::calibrate() {
+ // Load Pad Calibration data from non-volatile memory
+ uint32_t *pad_transn_p = (uint32_t *) USB_FUSES_TRANSN_ADDR;
+ uint32_t *pad_transp_p = (uint32_t *) USB_FUSES_TRANSP_ADDR;
+ uint32_t *pad_trim_p = (uint32_t *) USB_FUSES_TRIM_ADDR;
+
+ uint32_t pad_transn = (*pad_transn_p & USB_FUSES_TRANSN_Msk) >> USB_FUSES_TRANSN_Pos;
+ uint32_t pad_transp = (*pad_transp_p & USB_FUSES_TRANSP_Msk) >> USB_FUSES_TRANSP_Pos;
+ uint32_t pad_trim = (*pad_trim_p & USB_FUSES_TRIM_Msk ) >> USB_FUSES_TRIM_Pos;
+
+ if (pad_transn == 0x1F) // maximum value (31)
+ pad_transn = 5;
+ if (pad_transp == 0x1F) // maximum value (31)
+ pad_transp = 29;
+ if (pad_trim == 0x7) // maximum value (7)
+ pad_trim = 3;
+
+ usb.PADCAL.bit.TRANSN = pad_transn;
+ usb.PADCAL.bit.TRANSP = pad_transp;
+ usb.PADCAL.bit.TRIM = pad_trim;
+}
+
+/*
+ * Synchronization primitives.
+ * TODO: Move into a separate header file and make an API out of it
+ */
+
+class __Guard {
+public:
+ __Guard() : primask(__get_PRIMASK()), loops(1) {
+ __disable_irq();
+ }
+ ~__Guard() {
+ if (primask == 0) {
+ __enable_irq();
+ // http://infocenter.arm.com/help/topic/com.arm.doc.dai0321a/BIHBFEIB.html
+ __ISB();
+ }
+ }
+ uint32_t enter() { return loops--; }
+private:
+ uint32_t primask;
+ uint32_t loops;
+};
+
+#define synchronized for (__Guard __guard; __guard.enter(); )
+
+
+/*
+ * USB EP generic handlers.
+ */
+
+class EPHandler {
+public:
+ virtual void handleEndpoint() = 0;
+ virtual uint32_t recv(void *_data, uint32_t len) = 0;
+ virtual uint32_t available() = 0;
+ virtual int peek() = 0;
+};
+
+class DoubleBufferedEPOutHandler : public EPHandler {
+public:
+ enum { size = 64 };
+
+ DoubleBufferedEPOutHandler(USBDevice_SAMD21G18x &usbDev, uint32_t endPoint) :
+ usbd(usbDev),
+ ep(endPoint),
+ current(0), incoming(0),
+ first0(0), last0(0), ready0(false),
+ first1(0), last1(0), ready1(false),
+ notify(false)
+ {
+ usbd.epBank0SetSize(ep, 64);
+ usbd.epBank0SetType(ep, 3); // BULK OUT
+ usbd.epBank0SetAddress(ep, const_cast<uint8_t *>(data0));
+ usbd.epBank0EnableTransferComplete(ep);
+
+ release();
+ }
+
+ virtual ~DoubleBufferedEPOutHandler() {
+ }
+
+ uint32_t _recv()
+ {
+ uint32_t i = 0;
+ uint32_t len = 0;
+
+ synchronized {
+ len = _rx_buffer.availableForStore();
+ }
+
+ // R/W: current, first0/1, ready0/1, notify
+ // R : last0/1, data0/1
+ if (current == 0) {
+ synchronized {
+ if (!ready0) {
+ return 0;
+ }
+ }
+ // when ready0==true the buffer is not being filled and last0 is constant
+ for (; i<len && first0 < last0; i++) {
+ _rx_buffer.store_char(data0[first0++]);
+ }
+ if (first0 == last0) {
+ first0 = 0;
+ current = 1;
+ synchronized {
+ ready0 = false;
+ if (notify) {
+ notify = false;
+ release();
+ }
+ }
+ }
+ } else {
+ synchronized {
+ if (!ready1) {
+ return 0;
+ }
+ }
+ // when ready1==true the buffer is not being filled and last1 is constant
+ for (; i<len && first1 < last1; i++) {
+ _rx_buffer.store_char(data1[first1++]);
+ }
+ if (first1 == last1) {
+ first1 = 0;
+ current = 0;
+ synchronized {
+ ready1 = false;
+ if (notify) {
+ notify = false;
+ release();
+ }
+ }
+ }
+ }
+ return i;
+ }
+
+ virtual uint32_t recv(void *_data, uint32_t len) {
+ _recv();
+ uint32_t i = 0;
+ uint8_t *data = reinterpret_cast<uint8_t *>(_data);
+ synchronized {
+ for (; i < len && _rx_buffer.available(); i++) {
+ data[i] = _rx_buffer.read_char();
+ }
+ }
+ return i;
+ }
+
+ virtual uint32_t _available() const {
+ if (current == 0) {
+ bool ready = ready0;
+ synchronized {
+ ready = ready0;
+ }
+ return ready ? (last0 - first0) : 0;
+ } else {
+ bool ready = false;
+ synchronized {
+ ready = ready1;
+ }
+ return ready ? (last1 - first1) : 0;
+ }
+ }
+
+ virtual void handleEndpoint()
+ {
+ // R/W : incoming, ready0/1
+ // W : last0/1, notify
+ if (usbd.epBank0IsTransferComplete(ep))
+ {
+ uint32_t received = usbd.epBank0ByteCount(ep);
+ if (received == 0) {
+ release();
+ } else if (incoming == 0) {
+ // Update counters and swap banks for non-ZLP's
+ last0 = received;
+ incoming = 1;
+ usbd.epBank0SetAddress(ep, const_cast<uint8_t *>(data1));
+ synchronized {
+ ready0 = true;
+ notify = ready1;
+ if (!notify) {
+ release();
+ }
+ }
+ } else {
+ last1 = received;
+ incoming = 0;
+ usbd.epBank0SetAddress(ep, const_cast<uint8_t *>(data0));
+ synchronized {
+ ready1 = true;
+ notify = ready0;
+ if (!notify) {
+ release();
+ }
+ }
+ }
+ usbd.epAckPendingInterrupts(ep);
+ }
+ }
+
+ // Returns how many bytes are stored in the buffers
+ virtual uint32_t available() {
+ _recv();
+ return _rx_buffer.available();
+ }
+
+ virtual int peek() {
+ _recv();
+ return _rx_buffer.peek();
+ }
+
+ void release() {
+ usbd.epReleaseOutBank0(ep, size);
+ }
+
+private:
+ USBDevice_SAMD21G18x &usbd;
+
+ RingBuffer _rx_buffer;
+
+ const uint32_t ep;
+ volatile uint32_t current, incoming;
+
+ __attribute__((__aligned__(4))) volatile uint8_t data0[size];
+ uint32_t first0;
+ volatile uint32_t last0;
+ volatile bool ready0;
+
+ __attribute__((__aligned__(4))) volatile uint8_t data1[size];
+ uint32_t first1;
+ volatile uint32_t last1;
+ volatile bool ready1;
+
+ volatile bool notify;
+};
+
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/USB/USBAPI.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/USB/USBAPI.h
new file mode 100644
index 0000000000000000000000000000000000000000..30455acfc58ce7b7bb32449d483c27809d0b2154
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/USB/USBAPI.h
@@ -0,0 +1,120 @@
+/*
+ Copyright (c) 2015 Arduino LLC. All right reserved.
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ See the GNU Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#pragma once
+
+#define HSTPIPCFG_PTYPE_BLK 1
+#define HSTPIPCFG_PTOKEN_IN 2
+#define HSTPIPCFG_PTOKEN_OUT 3
+#define HSTPIPCFG_PBK_1_BANK 4
+#define HSTPIPCFG_PTYPE_INTRPT 5
+
+#define EP0 0
+#define EPX_SIZE 64 // 64 for Full Speed, EPT size max is 1024
+
+#if defined __cplusplus
+
+#include "Stream.h"
+#include "RingBuffer.h"
+
+//================================================================================
+// USB
+
+// Low level API
+typedef struct __attribute__((packed)) {
+ union {
+ uint8_t bmRequestType;
+ struct {
+ uint8_t direction : 5;
+ uint8_t type : 2;
+ uint8_t transferDirection : 1;
+ };
+ };
+ uint8_t bRequest;
+ uint8_t wValueL;
+ uint8_t wValueH;
+ uint16_t wIndex;
+ uint16_t wLength;
+} USBSetup;
+
+class USBDeviceClass {
+public:
+ USBDeviceClass() {};
+
+ // USB Device API
+ void init();
+ bool end();
+ bool attach();
+ bool detach();
+ void setAddress(uint32_t addr);
+
+ bool configured();
+ bool connected();
+
+ void standby();
+
+ // Setup API
+ bool handleClassInterfaceSetup(USBSetup &setup);
+ bool handleStandardSetup(USBSetup &setup);
+ bool sendDescriptor(USBSetup &setup);
+
+ // Control EndPoint API
+ uint32_t sendControl(const void *data, uint32_t len);
+ uint32_t sendControl(int /* ep */, const void *data, uint32_t len) { return sendControl(data, len); }
+ uint32_t recvControl(void *data, uint32_t len);
+ uint32_t sendConfiguration(uint32_t maxlen);
+ bool sendStringDescriptor(const uint8_t *string, uint32_t maxlen);
+ void initControl(int end);
+ uint8_t SendInterfaces(uint32_t* total);
+ void packMessages(bool val);
+
+ // Generic EndPoint API
+ void initEndpoints(void);
+ void initEP(uint32_t ep, uint32_t type);
+
+ uint32_t send(uint32_t ep, const void *data, uint32_t len);
+ void sendZlp(uint32_t ep);
+ uint32_t recv(uint32_t ep, void *data, uint32_t len);
+ int recv(uint32_t ep);
+ uint32_t available(uint32_t ep);
+ void flush(uint32_t ep);
+ void clear(uint32_t ep);
+ void stall(uint32_t ep);
+
+ // private?
+ uint32_t armSend(uint32_t ep, const void *data, uint32_t len);
+ uint8_t armRecvCtrlOUT(uint32_t ep);
+
+ void ISRHandler();
+
+private:
+ bool initialized;
+};
+
+extern USBDeviceClass USBDevice;
+
+//================================================================================
+//================================================================================
+// MSC 'Driver'
+
+uint32_t MSC_GetInterface(uint8_t* interfaceNum);
+uint32_t MSC_GetDescriptor(uint32_t i);
+bool MSC_Setup(USBSetup& setup);
+bool MSC_Data(uint8_t rx,uint8_t tx);
+
+#endif // __cplusplus
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/USB/USBCore.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/USB/USBCore.h
new file mode 100644
index 0000000000000000000000000000000000000000..8018ae3e2b8641837630d2f4129ae1c11d834160
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/USB/USBCore.h
@@ -0,0 +1,218 @@
+/*
+ Copyright (c) 2014 Arduino LLC. All right reserved.
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ See the GNU Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#ifndef __USBCORE_H__
+#define __USBCORE_H__
+
+// Standard requests
+#define GET_STATUS 0
+#define CLEAR_FEATURE 1
+#define SET_FEATURE 3
+#define SET_ADDRESS 5
+#define GET_DESCRIPTOR 6
+#define SET_DESCRIPTOR 7
+#define GET_CONFIGURATION 8
+#define SET_CONFIGURATION 9
+#define GET_INTERFACE 10
+#define SET_INTERFACE 11
+
+// bEndpointAddress in Endpoint Descriptor
+#define USB_ENDPOINT_DIRECTION_MASK 0x80
+#define USB_ENDPOINT_OUT(addr) uint8_t((addr) | 0x00)
+#define USB_ENDPOINT_IN(addr) uint8_t((addr) | 0x80)
+
+#define USB_ENDPOINTS 7
+
+#define USB_ENDPOINT_TYPE_MASK 0x03
+#define USB_ENDPOINT_TYPE_CONTROL 0x00
+#define USB_ENDPOINT_TYPE_ISOCHRONOUS 0x01
+#define USB_ENDPOINT_TYPE_BULK 0x02
+#define USB_ENDPOINT_TYPE_INTERRUPT 0x03
+
+// bmRequestType
+#define REQUEST_HOSTTODEVICE 0x00
+#define REQUEST_DEVICETOHOST 0x80
+#define REQUEST_DIRECTION 0x80
+
+#define REQUEST_STANDARD 0x00
+#define REQUEST_CLASS 0x20
+#define REQUEST_VENDOR 0x40
+#define REQUEST_TYPE 0x60
+
+#define REQUEST_DEVICE 0x00
+#define REQUEST_INTERFACE 0x01
+#define REQUEST_ENDPOINT 0x02
+#define REQUEST_OTHER 0x03
+#define REQUEST_RECIPIENT 0x1F
+
+#define REQUEST_DEVICETOHOST_CLASS_INTERFACE (REQUEST_DEVICETOHOST | REQUEST_CLASS | REQUEST_INTERFACE)
+#define REQUEST_HOSTTODEVICE_CLASS_INTERFACE (REQUEST_HOSTTODEVICE | REQUEST_CLASS | REQUEST_INTERFACE)
+#define REQUEST_DEVICETOHOST_STANDARD_INTERFACE (REQUEST_DEVICETOHOST | REQUEST_STANDARD | REQUEST_INTERFACE)
+// Class requests
+
+#define CDC_SET_LINE_CODING 0x20
+#define CDC_GET_LINE_CODING 0x21
+#define CDC_SET_CONTROL_LINE_STATE 0x22
+#define CDC_SEND_BREAK 0x23
+
+#define MSC_RESET 0xFF
+#define MSC_GET_MAX_LUN 0xFE
+
+// Descriptors
+
+// #define USB_DEVICE_DESC_SIZE 18
+// #define USB_CONFIGUARTION_DESC_SIZE 9
+// #define USB_INTERFACE_DESC_SIZE 9
+// #define USB_ENDPOINT_DESC_SIZE 7
+
+#define USB_DEVICE_DESCRIPTOR_TYPE 1
+#define USB_CONFIGURATION_DESCRIPTOR_TYPE 2
+#define USB_STRING_DESCRIPTOR_TYPE 3
+#define USB_INTERFACE_DESCRIPTOR_TYPE 4
+#define USB_ENDPOINT_DESCRIPTOR_TYPE 5
+#define USB_DEVICE_QUALIFIER 6
+#define USB_OTHER_SPEED_CONFIGURATION 7
+
+#define USB_DEVICE_CLASS_COMMUNICATIONS 0x02
+#define USB_DEVICE_CLASS_HUMAN_INTERFACE 0x03
+#define USB_DEVICE_CLASS_STORAGE 0x08
+#define USB_DEVICE_CLASS_VENDOR_SPECIFIC 0xFF
+
+#define USB_CONFIG_POWERED_MASK 0x40
+#define USB_CONFIG_BUS_POWERED 0x80
+#define USB_CONFIG_SELF_POWERED 0xC0
+#define USB_CONFIG_REMOTE_WAKEUP 0x20
+
+// bMaxPower in Configuration Descriptor
+#define USB_CONFIG_POWER_MA(mA) ((mA)/2)
+#ifndef USB_CONFIG_POWER
+ #define USB_CONFIG_POWER (500)
+#endif
+
+#define MSC_SUBCLASS_SCSI 0x06
+#define MSC_PROTOCOL_BULK_ONLY 0x50
+
+// Device
+typedef struct __attribute__((packed)) {
+ uint8_t len; // 18
+ uint8_t dtype; // 1 USB_DEVICE_DESCRIPTOR_TYPE
+ uint16_t usbVersion; // 0x200
+ uint8_t deviceClass;
+ uint8_t deviceSubClass;
+ uint8_t deviceProtocol;
+ uint8_t packetSize0; // Packet 0
+ uint16_t idVendor;
+ uint16_t idProduct;
+ uint16_t deviceVersion; // 0x100
+ uint8_t iManufacturer;
+ uint8_t iProduct;
+ uint8_t iSerialNumber;
+ uint8_t bNumConfigurations;
+} DeviceDescriptor;
+
+// Config
+typedef struct __attribute__((packed)) {
+ uint8_t len; // 9
+ uint8_t dtype; // 2
+ uint16_t clen; // total length
+ uint8_t numInterfaces;
+ uint8_t config;
+ uint8_t iconfig;
+ uint8_t attributes;
+ uint8_t maxPower;
+} ConfigDescriptor;
+
+// String
+
+// Interface
+typedef struct __attribute__((packed)) {
+ uint8_t len; // 9
+ uint8_t dtype; // 4
+ uint8_t number;
+ uint8_t alternate;
+ uint8_t numEndpoints;
+ uint8_t interfaceClass;
+ uint8_t interfaceSubClass;
+ uint8_t protocol;
+ uint8_t iInterface;
+} InterfaceDescriptor;
+
+// Endpoint
+typedef struct __attribute__((packed)) {
+ uint8_t len; // 7
+ uint8_t dtype; // 5
+ uint8_t addr;
+ uint8_t attr;
+ uint16_t packetSize;
+ uint8_t interval;
+} EndpointDescriptor;
+
+// Interface Association Descriptor
+// Used to bind 2 interfaces together in CDC compostite device
+typedef struct __attribute__((packed)) {
+ uint8_t len; // 8
+ uint8_t dtype; // 11
+ uint8_t firstInterface;
+ uint8_t interfaceCount;
+ uint8_t functionClass;
+ uint8_t funtionSubClass;
+ uint8_t functionProtocol;
+ uint8_t iInterface;
+} IADDescriptor;
+
+typedef struct __attribute__((packed)) {
+ InterfaceDescriptor msc;
+ EndpointDescriptor in;
+ EndpointDescriptor out;
+} MSCDescriptor;
+
+#define D_DEVICE(_class,_subClass,_proto,_packetSize0,_vid,_pid,_version,_im,_ip,_is,_configs) \
+ { 18, 1, 0x200, _class,_subClass,_proto,_packetSize0,_vid,_pid,_version,_im,_ip,_is,_configs }
+/* Table 9-8. Standard Device Descriptor
+ * bLength, bDescriptorType, bcdUSB, bDeviceClass, bDeviceSubClass, bDeviceProtocol, bMaxPacketSize0,
+ * idVendor, idProduct, bcdDevice, iManufacturer, iProduct, iSerialNumber, bNumConfigurations */
+
+#define D_CONFIG(_totalLength,_interfaces) \
+ { 9, 2, _totalLength,_interfaces, 1, 0, USB_CONFIG_BUS_POWERED | USB_CONFIG_REMOTE_WAKEUP, USB_CONFIG_POWER_MA(USB_CONFIG_POWER) }
+/* Table 9-10. Standard Configuration Descriptor
+ * bLength, bDescriptorType, wTotalLength, bNumInterfaces, bConfigurationValue, iConfiguration
+ * bmAttributes, bMaxPower */
+
+#define D_INTERFACE(_n,_numEndpoints,_class,_subClass,_protocol) \
+ { 9, 4, _n, 0, _numEndpoints, _class,_subClass, _protocol, 0 }
+/* Table 9-12. Standard Interface Descriptor
+ * bLength, bDescriptorType, bInterfaceNumber, bAlternateSetting, bNumEndpoints, bInterfaceClass,
+ * bInterfaceSubClass, bInterfaceProtocol, iInterface */
+
+#define D_ENDPOINT(_addr,_attr,_packetSize, _interval) \
+ { 7, 5, _addr,_attr,_packetSize, _interval }
+/* Table 9-13. Standard Endpoint Descriptor
+ * bLength, bDescriptorType, bEndpointAddress, bmAttributes, wMaxPacketSize, bInterval */
+
+#define D_IAD(_firstInterface, _count, _class, _subClass, _protocol) \
+ { 8, 11, _firstInterface, _count, _class, _subClass, _protocol, 0 }
+/* iadclasscode_r10.pdf, Table 9\96Z. Standard Interface Association Descriptor
+ * bLength, bDescriptorType, bFirstInterface, bInterfaceCount, bFunctionClass, bFunctionSubClass, bFunctionProtocol, iFunction */
+
+// Functional Descriptor General Format
+#define D_CDCCS(_subtype,_d0,_d1) { 5, 0x24, _subtype, _d0, _d1 }
+#define D_CDCCS4(_subtype,_d0) { 4, 0x24, _subtype, _d0 }
+/* bFunctionLength, bDescriptorType, bDescriptorSubtype, function specific data0, functional specific data N-1
+ * CS_INTERFACE 24h */
+
+#endif
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/USB/USBDesc.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/USB/USBDesc.h
new file mode 100644
index 0000000000000000000000000000000000000000..05f420c9f5c86702f52df35bac80431da22a448b
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/USB/USBDesc.h
@@ -0,0 +1,42 @@
+/*
+ Copyright (c) 2014 Arduino LLC. All right reserved.
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ See the GNU Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#ifndef __USBDESC_H__
+#define __USBDESC_H__
+
+#ifdef USBCON
+
+// CDC or HID can be enabled together.
+#ifndef CDC_DISABLED
+#define CDC_ENABLED
+#endif
+
+#ifndef PLUGGABLE_USB_DISABLED
+#define PLUGGABLE_USB_ENABLED
+#endif
+
+#define ISERIAL_MAX_LEN 65
+
+// Defined string description
+#define IMANUFACTURER 1
+#define IPRODUCT 2
+#define ISERIAL 3
+
+#endif /* USBCON */
+
+#endif /* __USBDESC_H__ */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/USB/USB_host.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/USB/USB_host.h
new file mode 100644
index 0000000000000000000000000000000000000000..319dffea5861bc1becd325e588f7327703d9b1f6
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/USB/USB_host.h
@@ -0,0 +1,66 @@
+/*
+ Copyright (c) 2014 Arduino LLC. All right reserved.
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ See the GNU Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#ifndef USB_HOST_H_INCLUDED
+#define USB_HOST_H_INCLUDED
+
+#include <stdint.h>
+#include "samd21_host.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define tokSETUP USB_HOST_PCFG_PTOKEN_SETUP
+#define tokIN USB_HOST_PCFG_PTOKEN_IN
+#define tokOUT USB_HOST_PCFG_PTOKEN_OUT
+#define tokINHS USB_HOST_PCFG_PTOKEN_IN
+#define tokOUTHS USB_HOST_PCFG_PTOKEN_OUT
+
+//! \brief Device speed
+/*typedef enum {
+ UHD_SPEED_LOW = 0,
+ UHD_SPEED_FULL = 1,
+ UHD_SPEED_HIGH = 2,
+} uhd_speed_t;*/
+
+//! States of USBB interface
+typedef enum {
+ UHD_STATE_NO_VBUS = 0,
+ UHD_STATE_DISCONNECTED = 1,
+ UHD_STATE_CONNECTED = 2,
+ UHD_STATE_ERROR = 3,
+} uhd_vbus_state_t;
+
+extern void UHD_Init(void);
+extern void UHD_Handler(void);
+extern void USB_SetHandler(void (*pf_isr)(void));
+extern uhd_vbus_state_t UHD_GetVBUSState(void);
+extern uint32_t UHD_Pipe0_Alloc(uint32_t ul_add, uint32_t ul_ep_size);
+extern uint32_t UHD_Pipe_Alloc(uint32_t ul_dev_addr, uint32_t ul_dev_ep, uint32_t ul_type, uint32_t ul_dir, uint32_t ul_maxsize, uint32_t ul_interval, uint32_t ul_nb_bank);
+extern void UHD_Pipe_CountZero(uint32_t ul_pipe);
+extern void UHD_Pipe_Free(uint32_t ul_pipe);
+extern uint32_t UHD_Pipe_Read(uint32_t ul_pipe, uint32_t ul_size, uint8_t* data);
+extern void UHD_Pipe_Write(uint32_t ul_pipe, uint32_t ul_size, uint8_t* data);
+extern void UHD_Pipe_Send(uint32_t ul_pipe, uint32_t ul_token_type);
+extern uint32_t UHD_Pipe_Is_Transfer_Complete(uint32_t ul_pipe, uint32_t ul_token_type);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* USB_HOST_H_INCLUDED */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/USB/samd21_host.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/USB/samd21_host.h
new file mode 100644
index 0000000000000000000000000000000000000000..d2d9c9e0930481cc5e37b13cf20f63c447009aaa
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/USB/samd21_host.h
@@ -0,0 +1,129 @@
+/*
+ Copyright (c) 2014 Arduino LLC. All right reserved.
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ See the GNU Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#ifndef SAMD21_HOST_H_INCLUDED
+#define SAMD21_HOST_H_INCLUDED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern __attribute__((__aligned__(4))) volatile UsbHostDescriptor usb_pipe_table[USB_EPT_NUM];
+
+#define USB_EP_DIR_IN 0x80 // USB_SETUP_DEVICE_TO_HOST
+#define USB_EP_DIR_OUT 0x00 // USB_SETUP_HOST_TO_DEVICE
+
+#define USB_HOST_PTYPE_DIS USB_HOST_PCFG_PTYPE(0x0) // Pipe is disabled
+#define USB_HOST_PTYPE_CTRL USB_HOST_PCFG_PTYPE(0x1) // Pipe is enabled and configured as CONTROL
+#define USB_HOST_PTYPE_ISO USB_HOST_PCFG_PTYPE(0x2) // Pipe is enabled and configured as ISO
+#define USB_HOST_PTYPE_BULK USB_HOST_PCFG_PTYPE(0x3) // Pipe is enabled and configured as BULK
+#define USB_HOST_PTYPE_INT USB_HOST_PCFG_PTYPE(0x4) // Pipe is enabled and configured as INTERRUPT
+#define USB_HOST_PTYPE_EXT USB_HOST_PCFG_PTYPE(0x5) // Pipe is enabled and configured as EXTENDED
+
+#define USB_HOST_NB_BK_1 1
+
+#define USB_HOST_PCFG_PTOKEN_SETUP USB_HOST_PCFG_PTOKEN(0x0)
+#define USB_HOST_PCFG_PTOKEN_IN USB_HOST_PCFG_PTOKEN(0x1)
+#define USB_HOST_PCFG_PTOKEN_OUT USB_HOST_PCFG_PTOKEN(0x2)
+
+#define USB_ERRORFLOW USB_HOST_STATUS_BK_ERRORFLOW
+#define USB_ERRORTIMEOUT USB_HOST_STATUS_PIPE_TOUTER
+#define USB_ERROR_DATATOGGLE USB_HOST_STATUS_PIPE_DTGLER
+
+#define USB_PCKSIZE_SIZE_8_BYTES 0
+#define USB_PCKSIZE_SIZE_16_BYTES 1
+#define USB_PCKSIZE_SIZE_32_BYTES 2
+#define USB_PCKSIZE_SIZE_64_BYTES 3
+#define USB_PCKSIZE_SIZE_128_BYTES 4
+#define USB_PCKSIZE_SIZE_256_BYTES 5
+#define USB_PCKSIZE_SIZE_512_BYTES 6
+#define USB_PCKSIZE_SIZE_1023_BYTES_FS 7
+#define USB_PCKSIZE_SIZE_1024_BYTES_HS 7
+
+#define USB_HOST_DTGL(p) (USB->HOST.HostPipe[p].PSTATUS.reg & USB_HOST_PSTATUS_DTGL)>>USB_HOST_PSTATUS_DTGL_Pos
+
+// USB host connection/disconnection monitoring
+#define uhd_enable_connection_int() USB->HOST.INTENSET.reg = USB_HOST_INTENSET_DCONN
+#define uhd_disable_connection_int() USB->HOST.INTENCLR.reg = USB_HOST_INTENCLR_DCONN
+#define uhd_ack_connection() USB->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DCONN
+
+#define uhd_enable_disconnection_int() USB->HOST.INTENSET.reg = USB_HOST_INTENSET_DDISC
+#define uhd_disable_disconnection_int() USB->HOST.INTENCLR.reg = USB_HOST_INTENCLR_DDISC
+#define uhd_ack_disconnection() USB->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DDISC
+
+// Initiates a USB register reset
+#define uhd_start_USB_reg_reset() USB->HOST.CTRLA.bit.SWRST = 1;
+
+// Bus Reset
+#define Is_uhd_starting_reset() (USB->HOST.CTRLB.bit.BUSRESET == 1)
+#define UHD_BusReset() USB->HOST.CTRLB.bit.BUSRESET = 1
+#define uhd_stop_reset() // nothing to do
+
+#define uhd_ack_reset_sent() USB->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RST
+#define Is_uhd_reset_sent() (USB->HOST.INTFLAG.reg & USB_HOST_INTFLAG_RST)
+
+// Initiates a SOF events
+#define uhd_enable_sof() USB->HOST.CTRLB.bit.SOFE = 1
+#define uhd_disable_sof() USB->HOST.CTRLB.bit.SOFE = 0
+#define Is_uhd_sof_enabled() (USB->HOST.CTRLB & USB_HOST_CTRLB_SOFE)
+#define Is_uhd_sof() (USB->HOST.INTFLAG.reg & USB_HOST_INTFLAG_HSOF)
+
+// USB address of pipes
+#define uhd_configure_address(pipe_num, addr) usb_pipe_table[pipe_num].HostDescBank[0].CTRL_PIPE.bit.PDADDR = addr
+#define uhd_get_configured_address(pipe_num) usb_pipe_table[pipe_num].HostDescBank[0].CTRL_PIPE.bit.PDADDR
+
+// Pipes
+#define uhd_freeze_pipe(p) USB->HOST.HostPipe[p].PSTATUSSET.reg = USB_HOST_PSTATUSSET_PFREEZE
+#define uhd_unfreeze_pipe(p) USB->HOST.HostPipe[p].PSTATUSCLR.reg = USB_HOST_PSTATUSCLR_PFREEZE
+#define Is_uhd_pipe_frozen(p) ((USB->HOST.HostPipe[p].PSTATUS.reg&USB_HOST_PSTATUS_PFREEZE)==USB_HOST_PSTATUS_PFREEZE)
+
+// Pipe configuration
+#define uhd_configure_pipe_token(p, token) USB->HOST.HostPipe[p].PCFG.bit.PTOKEN = token
+
+// Pipe data management
+#define uhd_byte_count(p) usb_pipe_table[p].HostDescBank[0].PCKSIZE.bit.BYTE_COUNT
+#define uhd_ack_setup_ready(p) USB->HOST.HostPipe[p].PINTFLAG.reg = USB_HOST_PINTFLAG_TXSTP
+#define Is_uhd_setup_ready(p) ((USB->HOST.HostPipe[p].PINTFLAG.reg&USB_HOST_PINTFLAG_TXSTP) == USB_HOST_PINTFLAG_TXSTP)
+#define uhd_ack_in_received(p) USB->HOST.HostPipe[p].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT(1)
+#define Is_uhd_in_received(p) ((USB->HOST.HostPipe[p].PINTFLAG.reg&USB_HOST_PINTFLAG_TRCPT(1)) == USB_HOST_PINTFLAG_TRCPT(1))
+#define uhd_ack_out_ready(p) USB->HOST.HostPipe[p].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT(1)
+#define Is_uhd_out_ready(p) ((USB->HOST.HostPipe[p].PINTFLAG.reg&USB_HOST_PINTFLAG_TRCPT(1)) == USB_HOST_PINTFLAG_TRCPT(1))
+#define uhd_ack_nak_received(p) usb_pipe_table[p].HostDescBank[1].STATUS_BK.reg &= ~USB_HOST_STATUS_BK_ERRORFLOW
+#define Is_uhd_nak_received(p) (usb_pipe_table[p].HostDescBank[1].STATUS_BK.reg & USB_HOST_STATUS_BK_ERRORFLOW)
+
+// Endpoint Interrupt Summary
+#define uhd_endpoint_interrupt() USB->HOST.PINTSMRY.reg
+
+// Run in Standby
+#define uhd_run_in_standby() USB->HOST.CTRLA.reg |= USB_CTRLA_RUNSTDBY
+// Force host mode
+#define uhd_force_host_mode() USB->HOST.CTRLA.reg |= USB_CTRLA_MODE
+
+// Enable USB macro
+#define uhd_enable() USB->HOST.CTRLA.reg |= USB_CTRLA_ENABLE
+// Disable USB macro
+#define uhd_disable() USB->HOST.CTRLA.reg &= ~USB_CTRLA_ENABLE
+
+// Force full speed mode
+#define uhd_force_full_speed() USB->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_SPDCONF_Msk
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SAMD21_HOST_H_INCLUDED */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/Uart.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/Uart.h
new file mode 100644
index 0000000000000000000000000000000000000000..8f80ea9cef78c13318943cab92a7872a58a83efa
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/Uart.h
@@ -0,0 +1,65 @@
+/*
+ Copyright (c) 2015 Arduino LLC. All right reserved.
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ See the GNU Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#pragma once
+
+#include "HardwareSerial.h"
+#include "SERCOM.h"
+#include "RingBuffer.h"
+
+#include <cstddef>
+
+class Uart : public HardwareSerial
+{
+ public:
+ Uart(SERCOM *_s, uint8_t _pinRX, uint8_t _pinTX, SercomRXPad _padRX, SercomUartTXPad _padTX);
+ Uart(SERCOM *_s, uint8_t _pinRX, uint8_t _pinTX, SercomRXPad _padRX, SercomUartTXPad _padTX, uint8_t _pinRTS, uint8_t _pinCTS);
+ void begin(unsigned long baudRate);
+ void begin(unsigned long baudrate, uint16_t config);
+ void end();
+ int available();
+ int availableForWrite();
+ int peek();
+ int read();
+ void flush();
+ size_t write(const uint8_t data);
+ using Print::write; // pull in write(str) and write(buf, size) from Print
+
+ void IrqHandler();
+
+ operator bool() { return true; }
+
+ private:
+ SERCOM *sercom;
+ RingBuffer rxBuffer;
+ RingBuffer txBuffer;
+
+ uint8_t uc_pinRX;
+ uint8_t uc_pinTX;
+ SercomRXPad uc_padRX;
+ SercomUartTXPad uc_padTX;
+ uint8_t uc_pinRTS;
+ volatile uint32_t* pul_outsetRTS;
+ volatile uint32_t* pul_outclrRTS;
+ uint32_t ul_pinMaskRTS;
+ uint8_t uc_pinCTS;
+
+ SercomNumberStopBit extractNbStopBit(uint16_t config);
+ SercomUartCharSize extractCharSize(uint16_t config);
+ SercomParityMode extractParity(uint16_t config);
+};
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/Udp.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/Udp.h
new file mode 100644
index 0000000000000000000000000000000000000000..89f31c676da0fac7e48a9d2b9d57d41c0701f96c
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/Udp.h
@@ -0,0 +1,89 @@
+/*
+ * Udp.cpp: Library to send/receive UDP packets.
+ *
+ * NOTE: UDP is fast, but has some important limitations (thanks to Warren Gray for mentioning these)
+ * 1) UDP does not guarantee the order in which assembled UDP packets are received. This
+ * might not happen often in practice, but in larger network topologies, a UDP
+ * packet can be received out of sequence.
+ * 2) UDP does not guard against lost packets - so packets *can* disappear without the sender being
+ * aware of it. Again, this may not be a concern in practice on small local networks.
+ * For more information, see http://www.cafeaulait.org/course/week12/35.html
+ *
+ * MIT License:
+ * Copyright (c) 2008 Bjoern Hartmann
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * bjoern@cs.stanford.edu 12/30/2008
+ */
+
+#ifndef udp_h
+#define udp_h
+
+#include <Stream.h>
+#include <IPAddress.h>
+
+class UDP : public Stream {
+
+public:
+ virtual uint8_t begin(uint16_t) =0; // initialize, start listening on specified port. Returns 1 if successful, 0 if there are no sockets available to use
+ virtual uint8_t beginMulticast(IPAddress, uint16_t) { return 0; } // initialize, start listening on specified multicast IP address and port. Returns 1 if successful, 0 on failure
+ virtual void stop() =0; // Finish with the UDP socket
+
+ // Sending UDP packets
+
+ // Start building up a packet to send to the remote host specific in ip and port
+ // Returns 1 if successful, 0 if there was a problem with the supplied IP address or port
+ virtual int beginPacket(IPAddress ip, uint16_t port) =0;
+ // Start building up a packet to send to the remote host specific in host and port
+ // Returns 1 if successful, 0 if there was a problem resolving the hostname or port
+ virtual int beginPacket(const char *host, uint16_t port) =0;
+ // Finish off this packet and send it
+ // Returns 1 if the packet was sent successfully, 0 if there was an error
+ virtual int endPacket() =0;
+ // Write a single byte into the packet
+ virtual size_t write(uint8_t) =0;
+ // Write size bytes from buffer into the packet
+ virtual size_t write(const uint8_t *buffer, size_t size) =0;
+
+ // Start processing the next available incoming packet
+ // Returns the size of the packet in bytes, or 0 if no packets are available
+ virtual int parsePacket() =0;
+ // Number of bytes remaining in the current packet
+ virtual int available() =0;
+ // Read a single byte from the current packet
+ virtual int read() =0;
+ // Read up to len bytes from the current packet and place them into buffer
+ // Returns the number of bytes read, or 0 if none are available
+ virtual int read(unsigned char* buffer, size_t len) =0;
+ // Read up to len characters from the current packet and place them into buffer
+ // Returns the number of characters read, or 0 if none are available
+ virtual int read(char* buffer, size_t len) =0;
+ // Return the next byte from the current packet without moving on to the next byte
+ virtual int peek() =0;
+ virtual void flush() =0; // Finish reading the current packet
+
+ // Return the IP address of the host who sent the current incoming packet
+ virtual IPAddress remoteIP() =0;
+ // Return the port of the host who sent the current incoming packet
+ virtual uint16_t remotePort() =0;
+protected:
+ uint8_t* rawIPAddress(IPAddress& addr) { return addr.raw_address(); };
+};
+
+#endif
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/WCharacter.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/WCharacter.h
new file mode 100644
index 0000000000000000000000000000000000000000..c0cbec7ae6ab0469c1fe756b75e62da24b42af42
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/WCharacter.h
@@ -0,0 +1,179 @@
+/*
+ Copyright (c) 2014 Arduino. All right reserved.
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ See the GNU Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#ifndef Character_h
+#define Character_h
+
+#include <ctype.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// WCharacter.h prototypes
+#if defined ( __GNUC__ )
+inline boolean isAlphaNumeric(int c) __attribute__((always_inline));
+inline boolean isAlpha(int c) __attribute__((always_inline));
+inline boolean isAscii(int c) __attribute__((always_inline));
+inline boolean isWhitespace(int c) __attribute__((always_inline));
+inline boolean isControl(int c) __attribute__((always_inline));
+inline boolean isDigit(int c) __attribute__((always_inline));
+inline boolean isGraph(int c) __attribute__((always_inline));
+inline boolean isLowerCase(int c) __attribute__((always_inline));
+inline boolean isPrintable(int c) __attribute__((always_inline));
+inline boolean isPunct(int c) __attribute__((always_inline));
+inline boolean isSpace(int c) __attribute__((always_inline));
+inline boolean isUpperCase(int c) __attribute__((always_inline));
+inline boolean isHexadecimalDigit(int c) __attribute__((always_inline));
+inline int toAscii(int c) __attribute__((always_inline));
+inline int toLowerCase(int c) __attribute__((always_inline));
+inline int toUpperCase(int c)__attribute__((always_inline));
+#elif defined ( __ICCARM__ )
+#endif
+
+// Checks for an alphanumeric character.
+// It is equivalent to (isalpha(c) || isdigit(c)).
+inline boolean isAlphaNumeric(int c)
+{
+ return ( isalnum(c) == 0 ? false : true);
+}
+
+
+// Checks for an alphabetic character.
+// It is equivalent to (isupper(c) || islower(c)).
+inline boolean isAlpha(int c)
+{
+ return ( isalpha(c) == 0 ? false : true);
+}
+
+
+// Checks whether c is a 7-bit unsigned char value
+// that fits into the ASCII character set.
+inline boolean isAscii(int c)
+{
+/* return ( isascii(c) == 0 ? false : true); */
+ return ( (c & ~0x7f) != 0 ? false : true);
+}
+
+
+// Checks for a blank character, that is, a space or a tab.
+inline boolean isWhitespace(int c)
+{
+ return ( isblank (c) == 0 ? false : true);
+}
+
+
+// Checks for a control character.
+inline boolean isControl(int c)
+{
+ return ( iscntrl (c) == 0 ? false : true);
+}
+
+
+// Checks for a digit (0 through 9).
+inline boolean isDigit(int c)
+{
+ return ( isdigit (c) == 0 ? false : true);
+}
+
+
+// Checks for any printable character except space.
+inline boolean isGraph(int c)
+{
+ return ( isgraph (c) == 0 ? false : true);
+}
+
+
+// Checks for a lower-case character.
+inline boolean isLowerCase(int c)
+{
+ return (islower (c) == 0 ? false : true);
+}
+
+
+// Checks for any printable character including space.
+inline boolean isPrintable(int c)
+{
+ return ( isprint (c) == 0 ? false : true);
+}
+
+
+// Checks for any printable character which is not a space
+// or an alphanumeric character.
+inline boolean isPunct(int c)
+{
+ return ( ispunct (c) == 0 ? false : true);
+}
+
+
+// Checks for white-space characters. For the avr-libc library,
+// these are: space, formfeed ('\f'), newline ('\n'), carriage
+// return ('\r'), horizontal tab ('\t'), and vertical tab ('\v').
+inline boolean isSpace(int c)
+{
+ return ( isspace (c) == 0 ? false : true);
+}
+
+
+// Checks for an uppercase letter.
+inline boolean isUpperCase(int c)
+{
+ return ( isupper (c) == 0 ? false : true);
+}
+
+
+// Checks for a hexadecimal digits, i.e. one of 0 1 2 3 4 5 6 7
+// 8 9 a b c d e f A B C D E F.
+inline boolean isHexadecimalDigit(int c)
+{
+ return ( isxdigit (c) == 0 ? false : true);
+}
+
+
+// Converts c to a 7-bit unsigned char value that fits into the
+// ASCII character set, by clearing the high-order bits.
+inline int toAscii(int c)
+{
+/* return toascii (c); */
+ return (c & 0x7f);
+}
+
+
+// Warning:
+// Many people will be unhappy if you use this function.
+// This function will convert accented letters into random
+// characters.
+
+// Converts the letter c to lower case, if possible.
+inline int toLowerCase(int c)
+{
+ return tolower (c);
+}
+
+
+// Converts the letter c to upper case, if possible.
+inline int toUpperCase(int c)
+{
+ return toupper (c);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/WInterrupts.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/WInterrupts.h
new file mode 100644
index 0000000000000000000000000000000000000000..5d2b24a0da647a52ed1c154a94668c7831fa32f4
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/WInterrupts.h
@@ -0,0 +1,54 @@
+/*
+ Copyright (c) 2015 Arduino LLC. All right reserved.
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ See the GNU Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#ifndef _WIRING_INTERRUPTS_
+#define _WIRING_INTERRUPTS_
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// LOW 0
+// HIGH 1
+#define CHANGE 2
+#define FALLING 3
+#define RISING 4
+
+#define DEFAULT 1
+#define EXTERNAL 0
+
+typedef void (*voidFuncPtr)(void);
+
+/*
+ * \brief Specifies a named Interrupt Service Routine (ISR) to call when an interrupt occurs.
+ * Replaces any previous function that was attached to the interrupt.
+ */
+void attachInterrupt(uint32_t pin, voidFuncPtr callback, uint32_t mode);
+
+/*
+ * \brief Turns off the given interrupt.
+ */
+void detachInterrupt(uint32_t pin);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/WMath.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/WMath.h
new file mode 100644
index 0000000000000000000000000000000000000000..1893955cbe2724dc941e11df45ff158d6484ce75
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/WMath.h
@@ -0,0 +1,33 @@
+/*
+ Copyright (c) 2014 Arduino. All right reserved.
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ See the GNU Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#ifndef _WIRING_MATH_
+#define _WIRING_MATH_
+
+extern long random( long ) ;
+extern long random( long, long ) ;
+extern void randomSeed( uint32_t dwSeed ) ;
+extern long map( long, long, long, long, long ) ;
+
+extern uint16_t makeWord( uint16_t w ) ;
+extern uint16_t makeWord( uint8_t h, uint8_t l ) ;
+
+#define word(...) makeWord(__VA_ARGS__)
+
+
+#endif /* _WIRING_MATH_ */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/WString.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/WString.h
new file mode 100644
index 0000000000000000000000000000000000000000..77709c3ba42f902c4598adece829c004ec6d4d34
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/WString.h
@@ -0,0 +1,229 @@
+/*
+ WString.h - String library for Wiring & Arduino
+ ...mostly rewritten by Paul Stoffregen...
+ Copyright (c) 2009-10 Hernando Barragan. All right reserved.
+ Copyright 2011, Paul Stoffregen, paul@pjrc.com
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#ifndef String_class_h
+#define String_class_h
+#ifdef __cplusplus
+
+#include <stdlib.h>
+#include <string.h>
+#include <ctype.h>
+#include <avr/pgmspace.h>
+
+// When compiling programs with this class, the following gcc parameters
+// dramatically increase performance and memory (RAM) efficiency, typically
+// with little or no increase in code size.
+// -felide-constructors
+// -std=c++0x
+
+class __FlashStringHelper;
+#define F(string_literal) (reinterpret_cast<const __FlashStringHelper *>(PSTR(string_literal)))
+
+// An inherited class for holding the result of a concatenation. These
+// result objects are assumed to be writable by subsequent concatenations.
+class StringSumHelper;
+
+// The string class
+class String
+{
+ // use a function pointer to allow for "if (s)" without the
+ // complications of an operator bool(). for more information, see:
+ // http://www.artima.com/cppsource/safebool.html
+ typedef void (String::*StringIfHelperType)() const;
+ void StringIfHelper() const {}
+
+public:
+ // constructors
+ // creates a copy of the initial value.
+ // if the initial value is null or invalid, or if memory allocation
+ // fails, the string will be marked as invalid (i.e. "if (s)" will
+ // be false).
+ String(const char *cstr = "");
+ String(const String &str);
+ String(const __FlashStringHelper *str);
+ #if __cplusplus >= 201103L || defined(__GXX_EXPERIMENTAL_CXX0X__)
+ String(String &&rval);
+ String(StringSumHelper &&rval);
+ #endif
+ explicit String(char c);
+ explicit String(unsigned char, unsigned char base=10);
+ explicit String(int, unsigned char base=10);
+ explicit String(unsigned int, unsigned char base=10);
+ explicit String(long, unsigned char base=10);
+ explicit String(unsigned long, unsigned char base=10);
+ explicit String(float, unsigned char decimalPlaces=2);
+ explicit String(double, unsigned char decimalPlaces=2);
+ ~String(void);
+
+ // memory management
+ // return true on success, false on failure (in which case, the string
+ // is left unchanged). reserve(0), if successful, will validate an
+ // invalid string (i.e., "if (s)" will be true afterwards)
+ unsigned char reserve(unsigned int size);
+ inline unsigned int length(void) const {return len;}
+
+ // creates a copy of the assigned value. if the value is null or
+ // invalid, or if the memory allocation fails, the string will be
+ // marked as invalid ("if (s)" will be false).
+ String & operator = (const String &rhs);
+ String & operator = (const char *cstr);
+ String & operator = (const __FlashStringHelper *str);
+ #if __cplusplus >= 201103L || defined(__GXX_EXPERIMENTAL_CXX0X__)
+ String & operator = (String &&rval);
+ String & operator = (StringSumHelper &&rval);
+ #endif
+
+ // concatenate (works w/ built-in types)
+
+ // returns true on success, false on failure (in which case, the string
+ // is left unchanged). if the argument is null or invalid, the
+ // concatenation is considered unsucessful.
+ unsigned char concat(const String &str);
+ unsigned char concat(const char *cstr);
+ unsigned char concat(char c);
+ unsigned char concat(unsigned char c);
+ unsigned char concat(int num);
+ unsigned char concat(unsigned int num);
+ unsigned char concat(long num);
+ unsigned char concat(unsigned long num);
+ unsigned char concat(float num);
+ unsigned char concat(double num);
+ unsigned char concat(const __FlashStringHelper * str);
+
+ // if there's not enough memory for the concatenated value, the string
+ // will be left unchanged (but this isn't signalled in any way)
+ String & operator += (const String &rhs) {concat(rhs); return (*this);}
+ String & operator += (const char *cstr) {concat(cstr); return (*this);}
+ String & operator += (char c) {concat(c); return (*this);}
+ String & operator += (unsigned char num) {concat(num); return (*this);}
+ String & operator += (int num) {concat(num); return (*this);}
+ String & operator += (unsigned int num) {concat(num); return (*this);}
+ String & operator += (long num) {concat(num); return (*this);}
+ String & operator += (unsigned long num) {concat(num); return (*this);}
+ String & operator += (float num) {concat(num); return (*this);}
+ String & operator += (double num) {concat(num); return (*this);}
+ String & operator += (const __FlashStringHelper *str){concat(str); return (*this);}
+
+ friend StringSumHelper & operator + (const StringSumHelper &lhs, const String &rhs);
+ friend StringSumHelper & operator + (const StringSumHelper &lhs, const char *cstr);
+ friend StringSumHelper & operator + (const StringSumHelper &lhs, char c);
+ friend StringSumHelper & operator + (const StringSumHelper &lhs, unsigned char num);
+ friend StringSumHelper & operator + (const StringSumHelper &lhs, int num);
+ friend StringSumHelper & operator + (const StringSumHelper &lhs, unsigned int num);
+ friend StringSumHelper & operator + (const StringSumHelper &lhs, long num);
+ friend StringSumHelper & operator + (const StringSumHelper &lhs, unsigned long num);
+ friend StringSumHelper & operator + (const StringSumHelper &lhs, float num);
+ friend StringSumHelper & operator + (const StringSumHelper &lhs, double num);
+ friend StringSumHelper & operator + (const StringSumHelper &lhs, const __FlashStringHelper *rhs);
+
+ // comparison (only works w/ Strings and "strings")
+ operator StringIfHelperType() const { return buffer ? &String::StringIfHelper : 0; }
+ int compareTo(const String &s) const;
+ unsigned char equals(const String &s) const;
+ unsigned char equals(const char *cstr) const;
+ unsigned char operator == (const String &rhs) const {return equals(rhs);}
+ unsigned char operator == (const char *cstr) const {return equals(cstr);}
+ unsigned char operator != (const String &rhs) const {return !equals(rhs);}
+ unsigned char operator != (const char *cstr) const {return !equals(cstr);}
+ unsigned char operator < (const String &rhs) const;
+ unsigned char operator > (const String &rhs) const;
+ unsigned char operator <= (const String &rhs) const;
+ unsigned char operator >= (const String &rhs) const;
+ unsigned char equalsIgnoreCase(const String &s) const;
+ unsigned char startsWith( const String &prefix) const;
+ unsigned char startsWith(const String &prefix, unsigned int offset) const;
+ unsigned char endsWith(const String &suffix) const;
+
+ // character acccess
+ char charAt(unsigned int index) const;
+ void setCharAt(unsigned int index, char c);
+ char operator [] (unsigned int index) const;
+ char& operator [] (unsigned int index);
+ void getBytes(unsigned char *buf, unsigned int bufsize, unsigned int index=0) const;
+ void toCharArray(char *buf, unsigned int bufsize, unsigned int index=0) const
+ { getBytes((unsigned char *)buf, bufsize, index); }
+ const char* c_str() const { return buffer; }
+ char* begin() { return buffer; }
+ char* end() { return buffer + length(); }
+ const char* begin() const { return c_str(); }
+ const char* end() const { return c_str() + length(); }
+
+ // search
+ int indexOf( char ch ) const;
+ int indexOf( char ch, unsigned int fromIndex ) const;
+ int indexOf( const String &str ) const;
+ int indexOf( const String &str, unsigned int fromIndex ) const;
+ int lastIndexOf( char ch ) const;
+ int lastIndexOf( char ch, unsigned int fromIndex ) const;
+ int lastIndexOf( const String &str ) const;
+ int lastIndexOf( const String &str, unsigned int fromIndex ) const;
+ String substring( unsigned int beginIndex ) const { return substring(beginIndex, len); };
+ String substring( unsigned int beginIndex, unsigned int endIndex ) const;
+
+ // modification
+ void replace(char find, char replace);
+ void replace(const String& find, const String& replace);
+ void remove(unsigned int index);
+ void remove(unsigned int index, unsigned int count);
+ void toLowerCase(void);
+ void toUpperCase(void);
+ void trim(void);
+
+ // parsing/conversion
+ long toInt(void) const;
+ float toFloat(void) const;
+ double toDouble(void) const;
+
+protected:
+ char *buffer; // the actual char array
+ unsigned int capacity; // the array length minus one (for the '\0')
+ unsigned int len; // the String length (not counting the '\0')
+protected:
+ void init(void);
+ void invalidate(void);
+ unsigned char changeBuffer(unsigned int maxStrLen);
+ unsigned char concat(const char *cstr, unsigned int length);
+
+ // copy and move
+ String & copy(const char *cstr, unsigned int length);
+ String & copy(const __FlashStringHelper *pstr, unsigned int length);
+ #if __cplusplus >= 201103L || defined(__GXX_EXPERIMENTAL_CXX0X__)
+ void move(String &rhs);
+ #endif
+};
+
+class StringSumHelper : public String
+{
+public:
+ StringSumHelper(const String &s) : String(s) {}
+ StringSumHelper(const char *p) : String(p) {}
+ StringSumHelper(char c) : String(c) {}
+ StringSumHelper(unsigned char num) : String(num) {}
+ StringSumHelper(int num) : String(num) {}
+ StringSumHelper(unsigned int num) : String(num) {}
+ StringSumHelper(long num) : String(num) {}
+ StringSumHelper(unsigned long num) : String(num) {}
+ StringSumHelper(float num) : String(num) {}
+ StringSumHelper(double num) : String(num) {}
+};
+
+#endif // __cplusplus
+#endif // String_class_h
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/WVariant.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/WVariant.h
new file mode 100644
index 0000000000000000000000000000000000000000..bbe2e0c4e26541ab9fb2a97c70650b044cd6c1f5
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/WVariant.h
@@ -0,0 +1,257 @@
+/*
+ Copyright (c) 2015 Arduino LLC. All right reserved.
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ See the GNU Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#pragma once
+
+#include <stdint.h>
+#include "sam.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Definitions and types for pins */
+typedef enum _EAnalogChannel
+{
+ No_ADC_Channel=-1,
+ ADC_Channel0=0,
+ ADC_Channel1=1,
+ ADC_Channel2=2,
+ ADC_Channel3=3,
+ ADC_Channel4=4,
+ ADC_Channel5=5,
+ ADC_Channel6=6,
+ ADC_Channel7=7,
+#if defined __SAMD21J18A__
+ ADC_Channel8=8,
+ ADC_Channel9=9,
+#endif // __SAMD21J18A__
+ ADC_Channel10=10,
+ ADC_Channel11=11,
+#if defined __SAMD21J18A__
+ ADC_Channel12=12,
+ ADC_Channel13=13,
+ ADC_Channel14=14,
+ ADC_Channel15=15,
+#endif // __SAMD21J18A__
+ ADC_Channel16=16,
+ ADC_Channel17=17,
+ ADC_Channel18=18,
+ ADC_Channel19=19,
+ DAC_Channel0,
+} EAnalogChannel ;
+
+// Definitions for TC channels
+typedef enum _ETCChannel
+{
+ NOT_ON_TIMER=-1,
+ TCC0_CH0 = (0<<8)|(0),
+ TCC0_CH1 = (0<<8)|(1),
+ TCC0_CH2 = (0<<8)|(2),
+ TCC0_CH3 = (0<<8)|(3),
+ TCC0_CH4 = (0<<8)|(0), // Channel 4 is 0!
+ TCC0_CH5 = (0<<8)|(1), // Channel 5 is 1!
+ TCC0_CH6 = (0<<8)|(2), // Channel 6 is 2!
+ TCC0_CH7 = (0<<8)|(3), // Channel 7 is 3!
+ TCC1_CH0 = (1<<8)|(0),
+ TCC1_CH1 = (1<<8)|(1),
+ TCC1_CH2 = (1<<8)|(0), // Channel 2 is 0!
+ TCC1_CH3 = (1<<8)|(1), // Channel 3 is 1!
+ TCC2_CH0 = (2<<8)|(0),
+ TCC2_CH1 = (2<<8)|(1),
+ TCC2_CH2 = (2<<8)|(0), // Channel 2 is 0!
+ TCC2_CH3 = (2<<8)|(1), // Channel 3 is 1!
+ TC3_CH0 = (3<<8)|(0),
+ TC3_CH1 = (3<<8)|(1),
+ TC4_CH0 = (4<<8)|(0),
+ TC4_CH1 = (4<<8)|(1),
+ TC5_CH0 = (5<<8)|(0),
+ TC5_CH1 = (5<<8)|(1),
+#if defined __SAMD21J18A__
+ TC6_CH0 = (6<<8)|(0),
+ TC6_CH1 = (6<<8)|(1),
+ TC7_CH0 = (7<<8)|(0),
+ TC7_CH1 = (7<<8)|(1),
+#endif // __SAMD21J18A__
+} ETCChannel ;
+
+extern const void* g_apTCInstances[TCC_INST_NUM+TC_INST_NUM] ;
+
+#define GetTCNumber( x ) ( (x) >> 8 )
+#define GetTCChannelNumber( x ) ( (x) & 0xff )
+#define GetTC( x ) ( g_apTCInstances[(x) >> 8] )
+
+// Definitions for PWM channels
+typedef enum _EPWMChannel
+{
+ NOT_ON_PWM=-1,
+ PWM0_CH0=TCC0_CH0,
+ PWM0_CH1=TCC0_CH1,
+ PWM0_CH2=TCC0_CH2,
+ PWM0_CH3=TCC0_CH3,
+ PWM0_CH4=TCC0_CH4,
+ PWM0_CH5=TCC0_CH5,
+ PWM0_CH6=TCC0_CH6,
+ PWM0_CH7=TCC0_CH7,
+ PWM1_CH0=TCC1_CH0,
+ PWM1_CH1=TCC1_CH1,
+ PWM1_CH2=TCC1_CH2,
+ PWM1_CH3=TCC1_CH3,
+ PWM2_CH0=TCC2_CH0,
+ PWM2_CH1=TCC2_CH1,
+ PWM2_CH2=TCC2_CH2,
+ PWM2_CH3=TCC2_CH3,
+ PWM3_CH0=TC3_CH0,
+ PWM3_CH1=TC3_CH1,
+ PWM4_CH0=TC4_CH0,
+ PWM4_CH1=TC4_CH1,
+ PWM5_CH0=TC5_CH0,
+ PWM5_CH1=TC5_CH1,
+#if defined __SAMD21J18A__
+ PWM6_CH0=TC6_CH0,
+ PWM6_CH1=TC6_CH1,
+ PWM7_CH0=TC7_CH0,
+ PWM7_CH1=TC7_CH1,
+#endif // __SAMD21J18A__
+} EPWMChannel ;
+
+typedef enum _EPortType
+{
+ NOT_A_PORT=-1,
+ PORTA=0,
+ PORTB=1,
+ PORTC=2,
+} EPortType ;
+
+typedef enum
+{
+ EXTERNAL_INT_0 = 0,
+ EXTERNAL_INT_1,
+ EXTERNAL_INT_2,
+ EXTERNAL_INT_3,
+ EXTERNAL_INT_4,
+ EXTERNAL_INT_5,
+ EXTERNAL_INT_6,
+ EXTERNAL_INT_7,
+ EXTERNAL_INT_8,
+ EXTERNAL_INT_9,
+ EXTERNAL_INT_10,
+ EXTERNAL_INT_11,
+ EXTERNAL_INT_12,
+ EXTERNAL_INT_13,
+ EXTERNAL_INT_14,
+ EXTERNAL_INT_15,
+ EXTERNAL_INT_NMI,
+ EXTERNAL_NUM_INTERRUPTS,
+ NOT_AN_INTERRUPT = -1,
+ EXTERNAL_INT_NONE = NOT_AN_INTERRUPT,
+} EExt_Interrupts ;
+
+//A B C D E F G H
+//EIC REF ADC AC PTC DAC SERCOM SERCOM_ALT TC/TCC TCC COM AC/GCLK
+
+typedef enum _EPioType
+{
+ PIO_NOT_A_PIN=-1, /* Not under control of a peripheral. */
+ PIO_EXTINT=0, /* The pin is controlled by the associated signal of peripheral A. */
+ PIO_ANALOG, /* The pin is controlled by the associated signal of peripheral B. */
+ PIO_SERCOM, /* The pin is controlled by the associated signal of peripheral C. */
+ PIO_SERCOM_ALT, /* The pin is controlled by the associated signal of peripheral D. */
+ PIO_TIMER, /* The pin is controlled by the associated signal of peripheral E. */
+ PIO_TIMER_ALT, /* The pin is controlled by the associated signal of peripheral F. */
+ PIO_COM, /* The pin is controlled by the associated signal of peripheral G. */
+ PIO_AC_CLK, /* The pin is controlled by the associated signal of peripheral H. */
+ PIO_DIGITAL, /* The pin is controlled by PORT. */
+ PIO_INPUT, /* The pin is controlled by PORT and is an input. */
+ PIO_INPUT_PULLUP, /* The pin is controlled by PORT and is an input with internal pull-up resistor enabled. */
+ PIO_OUTPUT, /* The pin is controlled by PORT and is an output. */
+
+ PIO_PWM=PIO_TIMER,
+ PIO_PWM_ALT=PIO_TIMER_ALT,
+} EPioType ;
+
+/**
+ * Pin Attributes to be OR-ed
+ */
+#define PIN_ATTR_NONE (0UL<<0)
+#define PIN_ATTR_COMBO (1UL<<0)
+#define PIN_ATTR_ANALOG (1UL<<1)
+#define PIN_ATTR_DIGITAL (1UL<<2)
+#define PIN_ATTR_PWM (1UL<<3)
+#define PIN_ATTR_TIMER (1UL<<4)
+#define PIN_ATTR_TIMER_ALT (1UL<<5)
+#define PIN_ATTR_EXTINT (1UL<<6)
+
+/* Types used for the table below */
+typedef struct _PinDescription
+{
+ EPortType ulPort ;
+ uint32_t ulPin ;
+ EPioType ulPinType ;
+ uint32_t ulPinAttribute ;
+ EAnalogChannel ulADCChannelNumber ; /* ADC Channel number in the SAM device */
+ EPWMChannel ulPWMChannel ;
+ ETCChannel ulTCChannel ;
+ EExt_Interrupts ulExtInt ;
+} PinDescription ;
+
+/* Pins table to be instantiated into variant.cpp */
+extern const PinDescription g_APinDescription[] ;
+
+/* Generic Clock Multiplexer IDs */
+#define GCM_DFLL48M_REF (0x00U)
+#define GCM_FDPLL96M_INPUT (0x01U)
+#define GCM_FDPLL96M_32K (0x02U)
+#define GCM_WDT (0x03U)
+#define GCM_RTC (0x04U)
+#define GCM_EIC (0x05U)
+#define GCM_USB (0x06U)
+#define GCM_EVSYS_CHANNEL_0 (0x07U)
+#define GCM_EVSYS_CHANNEL_1 (0x08U)
+#define GCM_EVSYS_CHANNEL_2 (0x09U)
+#define GCM_EVSYS_CHANNEL_3 (0x0AU)
+#define GCM_EVSYS_CHANNEL_4 (0x0BU)
+#define GCM_EVSYS_CHANNEL_5 (0x0CU)
+#define GCM_EVSYS_CHANNEL_6 (0x0DU)
+#define GCM_EVSYS_CHANNEL_7 (0x0EU)
+#define GCM_EVSYS_CHANNEL_8 (0x0FU)
+#define GCM_EVSYS_CHANNEL_9 (0x10U)
+#define GCM_EVSYS_CHANNEL_10 (0x11U)
+#define GCM_EVSYS_CHANNEL_11 (0x12U)
+#define GCM_SERCOMx_SLOW (0x13U)
+#define GCM_SERCOM0_CORE (0x14U)
+#define GCM_SERCOM1_CORE (0x15U)
+#define GCM_SERCOM2_CORE (0x16U)
+#define GCM_SERCOM3_CORE (0x17U)
+#define GCM_SERCOM4_CORE (0x18U)
+#define GCM_SERCOM5_CORE (0x19U)
+#define GCM_TCC0_TCC1 (0x1AU)
+#define GCM_TCC2_TC3 (0x1BU)
+#define GCM_TC4_TC5 (0x1CU)
+#define GCM_TC6_TC7 (0x1DU)
+#define GCM_ADC (0x1EU)
+#define GCM_AC_DIG (0x1FU)
+#define GCM_AC_ANA (0x20U)
+#define GCM_DAC (0x21U)
+#define GCM_PTC (0x22U)
+#define GCM_I2S_0 (0x23U)
+#define GCM_I2S_1 (0x24U)
+
+#ifdef __cplusplus
+} // extern "C"
+#endif
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/avr/dtostrf.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/avr/dtostrf.h
new file mode 100644
index 0000000000000000000000000000000000000000..762a8864ad50f5c65c36912d7879ab34f83d61f7
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/avr/dtostrf.h
@@ -0,0 +1,30 @@
+/*
+ dtostrf - Emulation for dtostrf function from avr-libc
+ Copyright (c) 2015 Arduino LLC. All rights reserved.
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+char *dtostrf(double val, signed char width, unsigned char prec, char *sout);
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/avr/interrupt.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/avr/interrupt.h
new file mode 100644
index 0000000000000000000000000000000000000000..950509ddefd5a4136e1ad924272023b023cbb24f
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/avr/interrupt.h
@@ -0,0 +1,23 @@
+/*
+ Copyright (c) 2015 Arduino LCC. All right reserved.
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ See the GNU Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+/*
+ Empty file.
+ This file is here to allow compatibility with sketches (made for AVR)
+ that includes <AVR/interrupt.h>
+*/
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/avr/io.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/avr/io.h
new file mode 100644
index 0000000000000000000000000000000000000000..33d20cdd261558b2e627d4a6d2fc2d69a2e5f881
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/avr/io.h
@@ -0,0 +1,32 @@
+/*
+ io.h - Definitions for compatibility with AVR io macros
+
+ Copyright (c) 2016 Arduino LLC
+
+ Permission is hereby granted, free of charge, to any person obtaining a copy
+ of this software and associated documentation files (the "Software"), to deal
+ in the Software without restriction, including without limitation the rights
+ to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ copies of the Software, and to permit persons to whom the Software is
+ furnished to do so, subject to the following conditions:
+
+ The above copyright notice and this permission notice shall be included in
+ all copies or substantial portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ THE SOFTWARE
+*/
+
+#ifndef _IO_H_
+#define _IO_H_
+
+#define RAMSTART (HMCRAMC0_ADDR)
+#define RAMSIZE (HMCRAMC0_SIZE)
+#define RAMEND (RAMSTART + RAMSIZE - 1)
+
+#endif
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/avr/pgmspace.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/avr/pgmspace.h
new file mode 100644
index 0000000000000000000000000000000000000000..de92051a9637e7275e66147d5cefa0fded9bbdd1
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/avr/pgmspace.h
@@ -0,0 +1,122 @@
+/*
+ pgmspace.h - Definitions for compatibility with AVR pgmspace macros
+
+ Copyright (c) 2015 Arduino LLC
+
+ Based on work of Paul Stoffregen on Teensy 3 (http://pjrc.com)
+
+ Permission is hereby granted, free of charge, to any person obtaining a copy
+ of this software and associated documentation files (the "Software"), to deal
+ in the Software without restriction, including without limitation the rights
+ to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ copies of the Software, and to permit persons to whom the Software is
+ furnished to do so, subject to the following conditions:
+
+ The above copyright notice and this permission notice shall be included in
+ all copies or substantial portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ THE SOFTWARE
+*/
+
+#ifndef __PGMSPACE_H_
+#define __PGMSPACE_H_ 1
+
+#include <inttypes.h>
+
+#define PROGMEM
+#define PGM_P const char *
+#define PSTR(str) (str)
+
+#define _SFR_BYTE(n) (n)
+
+typedef void prog_void;
+typedef char prog_char;
+typedef unsigned char prog_uchar;
+typedef int8_t prog_int8_t;
+typedef uint8_t prog_uint8_t;
+typedef int16_t prog_int16_t;
+typedef uint16_t prog_uint16_t;
+typedef int32_t prog_int32_t;
+typedef uint32_t prog_uint32_t;
+typedef int64_t prog_int64_t;
+typedef uint64_t prog_uint64_t;
+
+typedef const void* int_farptr_t;
+typedef const void* uint_farptr_t;
+
+#define memchr_P(s, c, n) memchr((s), (c), (n))
+#define memcmp_P(s1, s2, n) memcmp((s1), (s2), (n))
+#define memccpy_P(dest, src, c, n) memccpy((dest), (src), (c), (n))
+#define memcpy_P(dest, src, n) memcpy((dest), (src), (n))
+#define memmem_P(haystack, haystacklen, needle, needlelen) memmem((haystack), (haystacklen), (needle), (needlelen))
+#define memrchr_P(s, c, n) memrchr((s), (c), (n))
+#define strcat_P(dest, src) strcat((dest), (src))
+#define strchr_P(s, c) strchr((s), (c))
+#define strchrnul_P(s, c) strchrnul((s), (c))
+#define strcmp_P(a, b) strcmp((a), (b))
+#define strcpy_P(dest, src) strcpy((dest), (src))
+#define strcasecmp_P(s1, s2) strcasecmp((s1), (s2))
+#define strcasestr_P(haystack, needle) strcasestr((haystack), (needle))
+#define strcspn_P(s, accept) strcspn((s), (accept))
+#define strlcat_P(s1, s2, n) strlcat((s1), (s2), (n))
+#define strlcpy_P(s1, s2, n) strlcpy((s1), (s2), (n))
+#define strlen_P(a) strlen((a))
+#define strnlen_P(s, n) strnlen((s), (n))
+#define strncmp_P(s1, s2, n) strncmp((s1), (s2), (n))
+#define strncasecmp_P(s1, s2, n) strncasecmp((s1), (s2), (n))
+#define strncat_P(s1, s2, n) strncat((s1), (s2), (n))
+#define strncpy_P(s1, s2, n) strncpy((s1), (s2), (n))
+#define strpbrk_P(s, accept) strpbrk((s), (accept))
+#define strrchr_P(s, c) strrchr((s), (c))
+#define strsep_P(sp, delim) strsep((sp), (delim))
+#define strspn_P(s, accept) strspn((s), (accept))
+#define strstr_P(a, b) strstr((a), (b))
+#define strtok_P(s, delim) strtok((s), (delim))
+#define strtok_rP(s, delim, last) strtok((s), (delim), (last))
+
+#define strlen_PF(a) strlen((a))
+#define strnlen_PF(src, len) strnlen((src), (len))
+#define memcpy_PF(dest, src, len) memcpy((dest), (src), (len))
+#define strcpy_PF(dest, src) strcpy((dest), (src))
+#define strncpy_PF(dest, src, len) strncpy((dest), (src), (len))
+#define strcat_PF(dest, src) strcat((dest), (src))
+#define strlcat_PF(dest, src, len) strlcat((dest), (src), (len))
+#define strncat_PF(dest, src, len) strncat((dest), (src), (len))
+#define strcmp_PF(s1, s2) strcmp((s1), (s2))
+#define strncmp_PF(s1, s2, n) strncmp((s1), (s2), (n))
+#define strcasecmp_PF(s1, s2) strcasecmp((s1), (s2))
+#define strncasecmp_PF(s1, s2, n) strncasecmp((s1), (s2), (n))
+#define strstr_PF(s1, s2) strstr((s1), (s2))
+#define strlcpy_PF(dest, src, n) strlcpy((dest), (src), (n))
+#define memcmp_PF(s1, s2, n) memcmp((s1), (s2), (n))
+
+#define sprintf_P(s, f, ...) sprintf((s), (f), __VA_ARGS__)
+#define snprintf_P(s, f, ...) snprintf((s), (f), __VA_ARGS__)
+
+#define pgm_read_byte(addr) (*(const unsigned char *)(addr))
+#define pgm_read_word(addr) (*(const unsigned short *)(addr))
+#define pgm_read_dword(addr) (*(const unsigned long *)(addr))
+#define pgm_read_float(addr) (*(const float *)(addr))
+#define pgm_read_ptr(addr) (*(const void **)(addr))
+
+#define pgm_read_byte_near(addr) pgm_read_byte(addr)
+#define pgm_read_word_near(addr) pgm_read_word(addr)
+#define pgm_read_dword_near(addr) pgm_read_dword(addr)
+#define pgm_read_float_near(addr) pgm_read_float(addr)
+#define pgm_read_ptr_near(addr) pgm_read_ptr(addr)
+
+#define pgm_read_byte_far(addr) pgm_read_byte(addr)
+#define pgm_read_word_far(addr) pgm_read_word(addr)
+#define pgm_read_dword_far(addr) pgm_read_dword(addr)
+#define pgm_read_float_far(addr) pgm_read_float(addr)
+#define pgm_read_ptr_far(addr) pgm_read_ptr(addr)
+
+#define pgm_get_far_address(addr) (&(addr))
+
+#endif
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/binary.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/binary.h
new file mode 100644
index 0000000000000000000000000000000000000000..aec4c733d4c0a944d371b10ce42a1e1a9de4e016
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/binary.h
@@ -0,0 +1,534 @@
+/*
+ binary.h - Definitions for binary constants
+ Copyright (c) 2006 David A. Mellis. All right reserved.
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#ifndef Binary_h
+#define Binary_h
+
+#define B0 0
+#define B00 0
+#define B000 0
+#define B0000 0
+#define B00000 0
+#define B000000 0
+#define B0000000 0
+#define B00000000 0
+#define B1 1
+#define B01 1
+#define B001 1
+#define B0001 1
+#define B00001 1
+#define B000001 1
+#define B0000001 1
+#define B00000001 1
+#define B10 2
+#define B010 2
+#define B0010 2
+#define B00010 2
+#define B000010 2
+#define B0000010 2
+#define B00000010 2
+#define B11 3
+#define B011 3
+#define B0011 3
+#define B00011 3
+#define B000011 3
+#define B0000011 3
+#define B00000011 3
+#define B100 4
+#define B0100 4
+#define B00100 4
+#define B000100 4
+#define B0000100 4
+#define B00000100 4
+#define B101 5
+#define B0101 5
+#define B00101 5
+#define B000101 5
+#define B0000101 5
+#define B00000101 5
+#define B110 6
+#define B0110 6
+#define B00110 6
+#define B000110 6
+#define B0000110 6
+#define B00000110 6
+#define B111 7
+#define B0111 7
+#define B00111 7
+#define B000111 7
+#define B0000111 7
+#define B00000111 7
+#define B1000 8
+#define B01000 8
+#define B001000 8
+#define B0001000 8
+#define B00001000 8
+#define B1001 9
+#define B01001 9
+#define B001001 9
+#define B0001001 9
+#define B00001001 9
+#define B1010 10
+#define B01010 10
+#define B001010 10
+#define B0001010 10
+#define B00001010 10
+#define B1011 11
+#define B01011 11
+#define B001011 11
+#define B0001011 11
+#define B00001011 11
+#define B1100 12
+#define B01100 12
+#define B001100 12
+#define B0001100 12
+#define B00001100 12
+#define B1101 13
+#define B01101 13
+#define B001101 13
+#define B0001101 13
+#define B00001101 13
+#define B1110 14
+#define B01110 14
+#define B001110 14
+#define B0001110 14
+#define B00001110 14
+#define B1111 15
+#define B01111 15
+#define B001111 15
+#define B0001111 15
+#define B00001111 15
+#define B10000 16
+#define B010000 16
+#define B0010000 16
+#define B00010000 16
+#define B10001 17
+#define B010001 17
+#define B0010001 17
+#define B00010001 17
+#define B10010 18
+#define B010010 18
+#define B0010010 18
+#define B00010010 18
+#define B10011 19
+#define B010011 19
+#define B0010011 19
+#define B00010011 19
+#define B10100 20
+#define B010100 20
+#define B0010100 20
+#define B00010100 20
+#define B10101 21
+#define B010101 21
+#define B0010101 21
+#define B00010101 21
+#define B10110 22
+#define B010110 22
+#define B0010110 22
+#define B00010110 22
+#define B10111 23
+#define B010111 23
+#define B0010111 23
+#define B00010111 23
+#define B11000 24
+#define B011000 24
+#define B0011000 24
+#define B00011000 24
+#define B11001 25
+#define B011001 25
+#define B0011001 25
+#define B00011001 25
+#define B11010 26
+#define B011010 26
+#define B0011010 26
+#define B00011010 26
+#define B11011 27
+#define B011011 27
+#define B0011011 27
+#define B00011011 27
+#define B11100 28
+#define B011100 28
+#define B0011100 28
+#define B00011100 28
+#define B11101 29
+#define B011101 29
+#define B0011101 29
+#define B00011101 29
+#define B11110 30
+#define B011110 30
+#define B0011110 30
+#define B00011110 30
+#define B11111 31
+#define B011111 31
+#define B0011111 31
+#define B00011111 31
+#define B100000 32
+#define B0100000 32
+#define B00100000 32
+#define B100001 33
+#define B0100001 33
+#define B00100001 33
+#define B100010 34
+#define B0100010 34
+#define B00100010 34
+#define B100011 35
+#define B0100011 35
+#define B00100011 35
+#define B100100 36
+#define B0100100 36
+#define B00100100 36
+#define B100101 37
+#define B0100101 37
+#define B00100101 37
+#define B100110 38
+#define B0100110 38
+#define B00100110 38
+#define B100111 39
+#define B0100111 39
+#define B00100111 39
+#define B101000 40
+#define B0101000 40
+#define B00101000 40
+#define B101001 41
+#define B0101001 41
+#define B00101001 41
+#define B101010 42
+#define B0101010 42
+#define B00101010 42
+#define B101011 43
+#define B0101011 43
+#define B00101011 43
+#define B101100 44
+#define B0101100 44
+#define B00101100 44
+#define B101101 45
+#define B0101101 45
+#define B00101101 45
+#define B101110 46
+#define B0101110 46
+#define B00101110 46
+#define B101111 47
+#define B0101111 47
+#define B00101111 47
+#define B110000 48
+#define B0110000 48
+#define B00110000 48
+#define B110001 49
+#define B0110001 49
+#define B00110001 49
+#define B110010 50
+#define B0110010 50
+#define B00110010 50
+#define B110011 51
+#define B0110011 51
+#define B00110011 51
+#define B110100 52
+#define B0110100 52
+#define B00110100 52
+#define B110101 53
+#define B0110101 53
+#define B00110101 53
+#define B110110 54
+#define B0110110 54
+#define B00110110 54
+#define B110111 55
+#define B0110111 55
+#define B00110111 55
+#define B111000 56
+#define B0111000 56
+#define B00111000 56
+#define B111001 57
+#define B0111001 57
+#define B00111001 57
+#define B111010 58
+#define B0111010 58
+#define B00111010 58
+#define B111011 59
+#define B0111011 59
+#define B00111011 59
+#define B111100 60
+#define B0111100 60
+#define B00111100 60
+#define B111101 61
+#define B0111101 61
+#define B00111101 61
+#define B111110 62
+#define B0111110 62
+#define B00111110 62
+#define B111111 63
+#define B0111111 63
+#define B00111111 63
+#define B1000000 64
+#define B01000000 64
+#define B1000001 65
+#define B01000001 65
+#define B1000010 66
+#define B01000010 66
+#define B1000011 67
+#define B01000011 67
+#define B1000100 68
+#define B01000100 68
+#define B1000101 69
+#define B01000101 69
+#define B1000110 70
+#define B01000110 70
+#define B1000111 71
+#define B01000111 71
+#define B1001000 72
+#define B01001000 72
+#define B1001001 73
+#define B01001001 73
+#define B1001010 74
+#define B01001010 74
+#define B1001011 75
+#define B01001011 75
+#define B1001100 76
+#define B01001100 76
+#define B1001101 77
+#define B01001101 77
+#define B1001110 78
+#define B01001110 78
+#define B1001111 79
+#define B01001111 79
+#define B1010000 80
+#define B01010000 80
+#define B1010001 81
+#define B01010001 81
+#define B1010010 82
+#define B01010010 82
+#define B1010011 83
+#define B01010011 83
+#define B1010100 84
+#define B01010100 84
+#define B1010101 85
+#define B01010101 85
+#define B1010110 86
+#define B01010110 86
+#define B1010111 87
+#define B01010111 87
+#define B1011000 88
+#define B01011000 88
+#define B1011001 89
+#define B01011001 89
+#define B1011010 90
+#define B01011010 90
+#define B1011011 91
+#define B01011011 91
+#define B1011100 92
+#define B01011100 92
+#define B1011101 93
+#define B01011101 93
+#define B1011110 94
+#define B01011110 94
+#define B1011111 95
+#define B01011111 95
+#define B1100000 96
+#define B01100000 96
+#define B1100001 97
+#define B01100001 97
+#define B1100010 98
+#define B01100010 98
+#define B1100011 99
+#define B01100011 99
+#define B1100100 100
+#define B01100100 100
+#define B1100101 101
+#define B01100101 101
+#define B1100110 102
+#define B01100110 102
+#define B1100111 103
+#define B01100111 103
+#define B1101000 104
+#define B01101000 104
+#define B1101001 105
+#define B01101001 105
+#define B1101010 106
+#define B01101010 106
+#define B1101011 107
+#define B01101011 107
+#define B1101100 108
+#define B01101100 108
+#define B1101101 109
+#define B01101101 109
+#define B1101110 110
+#define B01101110 110
+#define B1101111 111
+#define B01101111 111
+#define B1110000 112
+#define B01110000 112
+#define B1110001 113
+#define B01110001 113
+#define B1110010 114
+#define B01110010 114
+#define B1110011 115
+#define B01110011 115
+#define B1110100 116
+#define B01110100 116
+#define B1110101 117
+#define B01110101 117
+#define B1110110 118
+#define B01110110 118
+#define B1110111 119
+#define B01110111 119
+#define B1111000 120
+#define B01111000 120
+#define B1111001 121
+#define B01111001 121
+#define B1111010 122
+#define B01111010 122
+#define B1111011 123
+#define B01111011 123
+#define B1111100 124
+#define B01111100 124
+#define B1111101 125
+#define B01111101 125
+#define B1111110 126
+#define B01111110 126
+#define B1111111 127
+#define B01111111 127
+#define B10000000 128
+#define B10000001 129
+#define B10000010 130
+#define B10000011 131
+#define B10000100 132
+#define B10000101 133
+#define B10000110 134
+#define B10000111 135
+#define B10001000 136
+#define B10001001 137
+#define B10001010 138
+#define B10001011 139
+#define B10001100 140
+#define B10001101 141
+#define B10001110 142
+#define B10001111 143
+#define B10010000 144
+#define B10010001 145
+#define B10010010 146
+#define B10010011 147
+#define B10010100 148
+#define B10010101 149
+#define B10010110 150
+#define B10010111 151
+#define B10011000 152
+#define B10011001 153
+#define B10011010 154
+#define B10011011 155
+#define B10011100 156
+#define B10011101 157
+#define B10011110 158
+#define B10011111 159
+#define B10100000 160
+#define B10100001 161
+#define B10100010 162
+#define B10100011 163
+#define B10100100 164
+#define B10100101 165
+#define B10100110 166
+#define B10100111 167
+#define B10101000 168
+#define B10101001 169
+#define B10101010 170
+#define B10101011 171
+#define B10101100 172
+#define B10101101 173
+#define B10101110 174
+#define B10101111 175
+#define B10110000 176
+#define B10110001 177
+#define B10110010 178
+#define B10110011 179
+#define B10110100 180
+#define B10110101 181
+#define B10110110 182
+#define B10110111 183
+#define B10111000 184
+#define B10111001 185
+#define B10111010 186
+#define B10111011 187
+#define B10111100 188
+#define B10111101 189
+#define B10111110 190
+#define B10111111 191
+#define B11000000 192
+#define B11000001 193
+#define B11000010 194
+#define B11000011 195
+#define B11000100 196
+#define B11000101 197
+#define B11000110 198
+#define B11000111 199
+#define B11001000 200
+#define B11001001 201
+#define B11001010 202
+#define B11001011 203
+#define B11001100 204
+#define B11001101 205
+#define B11001110 206
+#define B11001111 207
+#define B11010000 208
+#define B11010001 209
+#define B11010010 210
+#define B11010011 211
+#define B11010100 212
+#define B11010101 213
+#define B11010110 214
+#define B11010111 215
+#define B11011000 216
+#define B11011001 217
+#define B11011010 218
+#define B11011011 219
+#define B11011100 220
+#define B11011101 221
+#define B11011110 222
+#define B11011111 223
+#define B11100000 224
+#define B11100001 225
+#define B11100010 226
+#define B11100011 227
+#define B11100100 228
+#define B11100101 229
+#define B11100110 230
+#define B11100111 231
+#define B11101000 232
+#define B11101001 233
+#define B11101010 234
+#define B11101011 235
+#define B11101100 236
+#define B11101101 237
+#define B11101110 238
+#define B11101111 239
+#define B11110000 240
+#define B11110001 241
+#define B11110010 242
+#define B11110011 243
+#define B11110100 244
+#define B11110101 245
+#define B11110110 246
+#define B11110111 247
+#define B11111000 248
+#define B11111001 249
+#define B11111010 250
+#define B11111011 251
+#define B11111100 252
+#define B11111101 253
+#define B11111110 254
+#define B11111111 255
+
+#endif
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/delay.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/delay.h
new file mode 100644
index 0000000000000000000000000000000000000000..64f39b13f17a60cfef54a19e925eb988ba74696b
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/delay.h
@@ -0,0 +1,104 @@
+/*
+ Copyright (c) 2015 Arduino LLC. All right reserved.
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ See the GNU Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#ifndef _DELAY_
+#define _DELAY_
+
+#include <stdint.h>
+#include "variant.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief Returns the number of milliseconds since the Arduino board began running the current program.
+ *
+ * This number will overflow (go back to zero), after approximately 50 days.
+ *
+ * \return Number of milliseconds since the program started (uint32_t)
+ */
+extern unsigned long millis( void ) ;
+
+/**
+ * \brief Returns the number of microseconds since the Arduino board began running the current program.
+ *
+ * This number will overflow (go back to zero), after approximately 70 minutes. On 16 MHz Arduino boards
+ * (e.g. Duemilanove and Nano), this function has a resolution of four microseconds (i.e. the value returned is
+ * always a multiple of four). On 8 MHz Arduino boards (e.g. the LilyPad), this function has a resolution
+ * of eight microseconds.
+ *
+ * \note There are 1,000 microseconds in a millisecond and 1,000,000 microseconds in a second.
+ */
+extern unsigned long micros( void ) ;
+
+/**
+ * \brief Pauses the program for the amount of time (in miliseconds) specified as parameter.
+ * (There are 1000 milliseconds in a second.)
+ *
+ * \param dwMs the number of milliseconds to pause (uint32_t)
+ */
+extern void delay( unsigned long dwMs ) ;
+
+/**
+ * \brief Pauses the program for the amount of time (in microseconds) specified as parameter.
+ *
+ * \param dwUs the number of microseconds to pause (uint32_t)
+ */
+static __inline__ void delayMicroseconds( unsigned int ) __attribute__((always_inline, unused)) ;
+static __inline__ void delayMicroseconds( unsigned int usec )
+{
+ if ( usec == 0 )
+ {
+ return ;
+ }
+
+ /*
+ * The following loop:
+ *
+ * for (; ul; ul--) {
+ * __asm__ volatile("");
+ * }
+ *
+ * produce the following assembly code:
+ *
+ * loop:
+ * subs r3, #1 // 1 Core cycle
+ * bne.n loop // 1 Core cycle + 1 if branch is taken
+ */
+
+ // VARIANT_MCK / 1000000 == cycles needed to delay 1uS
+ // 3 == cycles used in a loop
+ uint32_t n = usec * (VARIANT_MCK / 1000000) / 3;
+ __asm__ __volatile__(
+ "1: \n"
+ " sub %0, #1 \n" // substract 1 from %0 (n)
+ " bne 1b \n" // if result is not 0 jump to 1
+ : "+r" (n) // '%0' is n variable with RW constraints
+ : // no input
+ : // no clobber
+ );
+ // https://gcc.gnu.org/onlinedocs/gcc/Extended-Asm.html
+ // https://gcc.gnu.org/onlinedocs/gcc/Extended-Asm.html#Volatile
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DELAY_ */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/itoa.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/itoa.h
new file mode 100644
index 0000000000000000000000000000000000000000..6752864cce1df33712286f9bd282410df5a56746
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/itoa.h
@@ -0,0 +1,35 @@
+
+ /*
+ Copyright (c) 2015 Arduino LLC. All right reserved.
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ See the GNU Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#pragma once
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+//extern void itoa( int n, char s[] ) ;
+
+extern char* itoa(int value, char*string, int radix);
+ extern char* ltoa(long value, char*string, int radix);
+ extern char* utoa(unsigned value, char*string, int radix);
+ extern char* ultoa(unsigned long value, char*string, int radix);
+
+# ifdef __cplusplus
+ } // extern "C"
+#endif
\ No newline at end of file
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/pulse.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/pulse.h
new file mode 100644
index 0000000000000000000000000000000000000000..9c620f12adb0dfe1acaa059d4d9b63fa936f6872
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/pulse.h
@@ -0,0 +1,39 @@
+/*
+ Copyright (c) 2015 Arduino LLC. All right reserved.
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ See the GNU Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * \brief Measures the length (in microseconds) of a pulse on the pin; state is HIGH
+ * or LOW, the type of pulse to measure. Works on pulses from 2-3 microseconds
+ * to 3 minutes in length, but must be called at least a few dozen microseconds
+ * before the start of the pulse.
+ */
+uint32_t pulseIn(uint32_t pin, uint32_t state, uint32_t timeout);
+
+#ifdef __cplusplus
+// Provides a version of pulseIn with a default argument (C++ only)
+uint32_t pulseIn(uint32_t pin, uint32_t state, uint32_t timeout = 1000000L);
+
+} // extern "C"
+#endif
+
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/sam.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/sam.h
new file mode 100644
index 0000000000000000000000000000000000000000..80a1c486cda80fa9ddd3dc896e11824ae8e9a006
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/sam.h
@@ -0,0 +1,567 @@
+/* ----------------------------------------------------------------------------
+ * SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2015, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+#ifndef _SAM_INCLUDED_
+#define _SAM_INCLUDED_
+
+#define part_is_defined(part) (defined(__ ## part ## __))
+
+/*
+ * ----------------------------------------------------------------------------
+ * SAMG family
+ * ----------------------------------------------------------------------------
+ */
+
+/* SAMG55 series */
+#define SAMG55J1 ( \
+ part_is_defined( SAMG55J19 ) )
+
+#define SAMG55G1 ( \
+ part_is_defined( SAMG55G19 ) )
+
+/* Entire SAMG55 series */
+#define SAMG55_SERIES (SAMG55J1 || SAMG55G1)
+
+/* SAMG54 series */
+#define SAMG54N1 ( \
+ part_is_defined( SAMG54N19 ) )
+
+#define SAMG54J1 ( \
+ part_is_defined( SAMG54J19 ) )
+
+#define SAMG54G1 ( \
+ part_is_defined( SAMG54G19 ) )
+
+/* Entire SAMG54 series */
+#define SAMG54_SERIES (SAMG54N1 || SAMG54J1 || SAMG54G1)
+
+
+
+/* Entire SAMG family */
+#define SAMG_SERIES ( SAMG55_SERIES || SAMG54_SERIES)
+
+/*
+ * ----------------------------------------------------------------------------
+ * SAMD family
+ * ----------------------------------------------------------------------------
+ */
+
+/* SAMD10 series */
+#define SAMD10C14 ( \
+ part_is_defined( SAMD10C14A ) )
+
+#define SAMD10C13 ( \
+ part_is_defined( SAMD10C13A ) )
+
+#define SAMD10D13A ( \
+ part_is_defined( SAMD10D13AS ) || \
+ part_is_defined( SAMD10D13AM ) )
+
+#define SAMD10D14A ( \
+ part_is_defined( SAMD10D14AS ) || \
+ part_is_defined( SAMD10D14AM ) )
+
+/* Entire SAMD10 series */
+#define SAMD10_SERIES (SAMD10C14 || SAMD10C13 || SAMD10D13A || SAMD10D14A)
+
+/* SAMD11 series */
+#define SAMD11C14 ( \
+ part_is_defined( SAMD11C14A ) )
+
+#define SAMD11D14A ( \
+ part_is_defined( SAMD11D14AS ) || \
+ part_is_defined( SAMD11D14AM ) )
+
+/* Entire SAMD11 series */
+#define SAMD11_SERIES (SAMD11C14 || SAMD11D14A)
+
+/* SAMD21 series */
+#define SAMD21J17 ( \
+ part_is_defined( SAMD21J17A ) )
+
+#define SAMD21G17A ( \
+ part_is_defined( SAMD21G17AU ) )
+
+#define SAMD21E15B ( \
+ part_is_defined( SAMD21E15BU ) )
+
+#define SAMD21E15 ( \
+ part_is_defined( SAMD21E15A ) || \
+ part_is_defined( SAMD21E15B ) || \
+ part_is_defined( SAMD21E15L ) )
+
+#define SAMD21E16 ( \
+ part_is_defined( SAMD21E16A ) || \
+ part_is_defined( SAMD21E16B ) || \
+ part_is_defined( SAMD21E16L ) )
+
+#define SAMD21E17 ( \
+ part_is_defined( SAMD21E17A ) )
+
+#define SAMD21E18 ( \
+ part_is_defined( SAMD21E18A ) )
+
+#define SAMD21E16B ( \
+ part_is_defined( SAMD21E16BU ) )
+
+#define SAMD21J15 ( \
+ part_is_defined( SAMD21J15A ) || \
+ part_is_defined( SAMD21J15B ) )
+
+#define SAMD21J16 ( \
+ part_is_defined( SAMD21J16A ) || \
+ part_is_defined( SAMD21J16B ) )
+
+#define SAMD21G16 ( \
+ part_is_defined( SAMD21G16A ) || \
+ part_is_defined( SAMD21G16B ) )
+
+#define SAMD21G17 ( \
+ part_is_defined( SAMD21G17A ) )
+
+#define SAMD21G18A ( \
+ part_is_defined( SAMD21G18AU ) )
+
+#define SAMD21G15 ( \
+ part_is_defined( SAMD21G15A ) || \
+ part_is_defined( SAMD21G15B ) )
+
+#define SAMD21G18 ( \
+ part_is_defined( SAMD21G18A ) )
+
+#define SAMD21J18 ( \
+ part_is_defined( SAMD21J18A ) )
+
+#define SAMD51G18A ( \
+ part_is_defined( SAMD51G18A ) )
+
+#define SAMD51G19A ( \
+ part_is_defined( SAMD51G19A ) )
+
+#define SAMD51J19A ( \
+ part_is_defined( SAMD51J19A ) )
+
+#define SAMD51J20A ( \
+ part_is_defined( SAMD51J20A ) )
+
+#define SAMD51N19A ( \
+ part_is_defined( SAMD51N19A ) )
+
+#define SAMD51N20A ( \
+ part_is_defined( SAMD51N20A ) )
+
+#define SAMD51P19A ( \
+ part_is_defined( SAMD51P19A ) )
+
+#define SAMD51P20A ( \
+ part_is_defined( SAMD51P20A ) )
+
+
+/* Entire SAMD21 series */
+#define SAMD21_SERIES (SAMD21J17 || SAMD21G17A || SAMD21E15B || SAMD21E15 || SAMD21E16 || SAMD21E17 || SAMD21E18 || SAMD21E16B || SAMD21J15 || SAMD21J16 || SAMD21G16 || SAMD21G17 || SAMD21G18A || SAMD21G15 || SAMD21G18 || SAMD21J18)
+
+/* Entire SAMD51 series */
+#define SAMD51_SERIES (SAMD51G18A || SAMD51G19A || SAMD51J19A || SAMD51J20A || SAMD51N19A || SAMD51N20A || SAMD51P19A || SAMD51P20A)
+
+/* Entire SAMD family */
+#define SAMD_SERIES (SAMD10_SERIES || SAMD11_SERIES || SAMD21_SERIES || SAMD51_SERIES)
+
+/*
+ * ----------------------------------------------------------------------------
+ * SAML family
+ * ----------------------------------------------------------------------------
+ */
+
+/* SAML21 series */
+#define SAML21E18A ( \
+ part_is_defined( SAML21E18A ) )
+#define SAML21G18A ( \
+ part_is_defined( SAML21G18A ) )
+#define SAML21J18A ( \
+ part_is_defined( SAML21J18A ) )
+
+#define SAML21E15B ( \
+ part_is_defined( SAML21E15B ) )
+#define SAML21E16B ( \
+ part_is_defined( SAML21E16B ) )
+#define SAML21E17B ( \
+ part_is_defined( SAML21E17B ) )
+#define SAML21E18B ( \
+ part_is_defined( SAML21E18B ) )
+#define SAML21G16B ( \
+ part_is_defined( SAML21G16B ) )
+#define SAML21G17B ( \
+ part_is_defined( SAML21G17B ) )
+#define SAML21G18B ( \
+ part_is_defined( SAML21G18B ) )
+#define SAML21J16B ( \
+ part_is_defined( SAML21J16B ) )
+#define SAML21J17B ( \
+ part_is_defined( SAML21J17B ) )
+#define SAML21J18B ( \
+ part_is_defined( SAML21J18B ) )
+#define SAML21J18BU ( \
+ part_is_defined( SAML21J18BU ) )
+
+/* Entire SAML21A series */
+#define SAML21_SERIES (SAML21E18A || SAML21G18A || SAML21J18A)
+
+/* Entire SAML21B series */
+#define SAML21B_SERIES (SAML21E15B || SAML21E16B || SAML21E17B || SAML21E18B || SAML21G16B || SAML21G17B || SAML21G18B || SAML21J16B || SAML21J17B || SAML21J18B || SAML21J18BU)
+
+/* Entire SAMD family */
+#define SAML_SERIES (SAML21A_SERIES || SAML21B_SERIES)
+
+/*
+ * ----------------------------------------------------------------------------
+ * SAMC family
+ * ----------------------------------------------------------------------------
+ */
+
+/* SAMC21 series */
+#define SAMC21E15A ( \
+ part_is_defined( SAMC21E15A ) )
+#define SAMC21E16A ( \
+ part_is_defined( SAMC21E16A ) )
+#define SAMC21E17A ( \
+ part_is_defined( SAMC21E17A ) )
+#define SAMC21E18A ( \
+ part_is_defined( SAMC21E18A ) )
+#define SAMC21G15A ( \
+ part_is_defined( SAMC21G15A ) )
+#define SAMC21G16A ( \
+ part_is_defined( SAMC21G16A ) )
+#define SAMC21G17A ( \
+ part_is_defined( SAMC21G17A ) )
+#define SAMC21G18A ( \
+ part_is_defined( SAMC21G18A ) )
+#define SAMC21J15A ( \
+ part_is_defined( SAMC21J15A ) )
+#define SAMC21J16A ( \
+ part_is_defined( SAMC21J16A ) )
+#define SAMC21J17A ( \
+ part_is_defined( SAMC21J17A ) )
+#define SAMC21J18A ( \
+ part_is_defined( SAMC21J18A ) )
+#define SAMC21J18AU ( \
+ part_is_defined( SAMC21J18AU ) )
+
+
+/* Entire SAMC21 series */
+#define SAMC21_SERIES (SAMC21E15A || SAMC21E16A || SAMC21E17A || SAMC21E18A || SAMC21G15A || SAMC21G16A || SAMC21G17A || SAMC21G18A || SAMC21J15A || SAMC21J16A || SAMC21J17A || SAMC21J18A || SAMC21J18AU)
+
+/* Entire SAMC family */
+#define SAMC_SERIES SAMC21_SERIES
+
+
+/*
+ * ----------------------------------------------------------------------------
+ * SAMS family
+ * ----------------------------------------------------------------------------
+ */
+
+/* SAMS70 series */
+#define SAMS70Q2 ( \
+ part_is_defined( SAMS70Q20 ) || \
+ part_is_defined( SAMS70Q21 ) )
+
+#define SAMS70Q1 ( \
+ part_is_defined( SAMS70Q19 ) )
+
+#define SAMS70N2 ( \
+ part_is_defined( SAMS70N20 ) || \
+ part_is_defined( SAMS70N21 ) )
+
+#define SAMS70N1 ( \
+ part_is_defined( SAMS70N19 ) )
+
+#define SAMS70J2 ( \
+ part_is_defined( SAMS70J20 ) || \
+ part_is_defined( SAMS70J21 ) )
+
+#define SAMS70J1 ( \
+ part_is_defined( SAMS70J19 ) )
+
+/* Entire SAMS70 series */
+#define SAMS70_SERIES (SAMS70Q2 || SAMS70Q1 || SAMS70N2 || SAMS70N1 || SAMS70J2 || SAMS70J1)
+
+/* Entire SAMS family */
+#define SAMS_SERIES (SAMS70_SERIES)
+
+/*
+ * ----------------------------------------------------------------------------
+ * SAME family
+ * ----------------------------------------------------------------------------
+ */
+
+/* SAME70 series */
+#define SAME70N1 ( \
+ part_is_defined( SAME70N19 ) )
+
+#define SAME70N2 ( \
+ part_is_defined( SAME70N20 ) || \
+ part_is_defined( SAME70N21 ) )
+
+#define SAME70J1 ( \
+ part_is_defined( SAME70J19 ) )
+
+#define SAME70J2 ( \
+ part_is_defined( SAME70J20 ) || \
+ part_is_defined( SAME70J21 ) )
+
+#define SAME70Q1 ( \
+ part_is_defined( SAME70Q19 ) )
+
+#define SAME70Q2 ( \
+ part_is_defined( SAME70Q20 ) || \
+ part_is_defined( SAME70Q21 ) )
+
+/* Entire SAME70 series */
+#define SAME70_SERIES (SAME70N1 || SAME70N2 || SAME70J1 || SAME70J2 || SAME70Q1 || SAME70Q2)
+
+/* Entire SAME family */
+#define SAME_SERIES (SAME70_SERIES)
+
+/*
+ * ----------------------------------------------------------------------------
+ * SAM3 family
+ * ----------------------------------------------------------------------------
+ */
+
+/* SAM3U series */
+#define SAM3U1 ( \
+ part_is_defined( SAM3U1E ) || \
+ part_is_defined( SAM3U1C ) )
+
+#define SAM3U2 ( \
+ part_is_defined( SAM3U2E ) || \
+ part_is_defined( SAM3U2C ) )
+
+#define SAM3U4 ( \
+ part_is_defined( SAM3U4E ) || \
+ part_is_defined( SAM3U4C ) )
+
+/* Entire SAM3U series */
+#define SAM3U_SERIES (SAM3U1 || SAM3U2 || SAM3U4)
+
+/* SAM3XA series */
+#define SAM3A4 ( \
+ part_is_defined( SAM3A4C ) )
+
+#define SAM3X4 ( \
+ part_is_defined( SAM3X4C ) || \
+ part_is_defined( SAM3X4E ) )
+
+#define SAM3A8 ( \
+ part_is_defined( SAM3A8C ) )
+
+#define SAM3X8 ( \
+ part_is_defined( SAM3X8C ) || \
+ part_is_defined( SAM3X8E ) || \
+ part_is_defined( SAM3X8H ) )
+
+/* Entire SAM3XA series */
+#define SAM3XA_SERIES (SAM3A4 || SAM3X4 || SAM3A8 || SAM3X8)
+
+/* Entire SAM3 family */
+#define SAM3_SERIES (SAM3U_SERIES || SAM3XA_SERIES)
+
+/*
+ * ----------------------------------------------------------------------------
+ * SAMR family
+ * ----------------------------------------------------------------------------
+ */
+
+/* SAMR21 series */
+#define SAMR21E16 ( \
+ part_is_defined( SAMR21E16A ) )
+
+#define SAMR21E18 ( \
+ part_is_defined( SAMR21E18A ) )
+
+#define SAMR21G16 ( \
+ part_is_defined( SAMR21G16A ) )
+
+#define SAMR21G17 ( \
+ part_is_defined( SAMR21G17A ) )
+
+#define SAMR21G18 ( \
+ part_is_defined( SAMR21G18A ) )
+
+#define SAMR21E17 ( \
+ part_is_defined( SAMR21E17A ) )
+
+/* Entire SAMR21 series */
+#define SAMR21_SERIES (SAMR21E16 || SAMR21E18 || SAMR21G16 || SAMR21G17 || SAMR21G18 || SAMR21E17)
+
+/* Entire SAMR family */
+#define SAMR_SERIES (SAMR21_SERIES)
+
+/*
+ * ----------------------------------------------------------------------------
+ * SAM4 family
+ * ----------------------------------------------------------------------------
+ */
+
+/* SAM4N series */
+#define SAM4N8 ( \
+ part_is_defined( SAM4N8A ) || \
+ part_is_defined( SAM4N8B ) || \
+ part_is_defined( SAM4N8C ) )
+
+#define SAM4N16 ( \
+ part_is_defined( SAM4N16B ) || \
+ part_is_defined( SAM4N16C ) )
+
+/* Entire SAM4N series */
+#define SAM4N_SERIES (SAM4N8 || SAM4N16)
+
+/* SAM4S series */
+#define SAM4S8 ( \
+ part_is_defined( SAM4S8C ) || \
+ part_is_defined( SAM4S8B ) )
+
+#define SAM4S2 ( \
+ part_is_defined( SAM4S2A ) || \
+ part_is_defined( SAM4S2B ) || \
+ part_is_defined( SAM4S2C ) )
+
+#define SAM4S4 ( \
+ part_is_defined( SAM4S4A ) || \
+ part_is_defined( SAM4S4B ) || \
+ part_is_defined( SAM4S4C ) )
+
+#define SAM4SD16 ( \
+ part_is_defined( SAM4SD16B ) || \
+ part_is_defined( SAM4SD16C ) )
+
+#define SAM4S16 ( \
+ part_is_defined( SAM4S16C ) || \
+ part_is_defined( SAM4S16B ) )
+
+#define SAM4SD32 ( \
+ part_is_defined( SAM4SD32B ) || \
+ part_is_defined( SAM4SD32C ) )
+
+#define SAM4SA16 ( \
+ part_is_defined( SAM4SA16B ) || \
+ part_is_defined( SAM4SA16C ) )
+
+/* Entire SAM4S series */
+#define SAM4S_SERIES (SAM4S8 || SAM4S2 || SAM4S4 || SAM4SD16 || SAM4S16 || SAM4SD32 || SAM4SA16)
+
+/* SAM4E series */
+#define SAM4E16 ( \
+ part_is_defined( SAM4E16E ) || \
+ part_is_defined( SAM4E16C ) )
+
+#define SAM4E8 ( \
+ part_is_defined( SAM4E8E ) || \
+ part_is_defined( SAM4E8C ) )
+
+/* Entire SAM4E series */
+#define SAM4E_SERIES (SAM4E16 || SAM4E8)
+
+/* SAM4C series */
+#define SAM4C4C_ ( \
+ part_is_defined( SAM4C4C_0 ) || \
+ part_is_defined( SAM4C4C_1 ) )
+
+#define SAM4C8C_ ( \
+ part_is_defined( SAM4C8C_0 ) || \
+ part_is_defined( SAM4C8C_1 ) )
+
+#define SAM4C16C_ ( \
+ part_is_defined( SAM4C16C_0 ) || \
+ part_is_defined( SAM4C16C_1 ) )
+
+#define SAM4C32C_ ( \
+ part_is_defined( SAM4C32C_0 ) || \
+ part_is_defined( SAM4C32C_1 ) )
+
+#define SAM4C32E_ ( \
+ part_is_defined( SAM4C32E_0 ) || \
+ part_is_defined( SAM4C32E_1 ) )
+
+/* Entire SAM4C series */
+#define SAM4C_SERIES (SAM4C4C_ || SAM4C8C_ || SAM4C16C_ || SAM4C32C_ || SAM4C32E_)
+
+/* Entire SAM4 family */
+#define SAM4_SERIES (SAM4N_SERIES || SAM4S_SERIES || SAM4E_SERIES || SAM4C_SERIES)
+
+/*
+ * ----------------------------------------------------------------------------
+ * Whole SAM product line
+ * ----------------------------------------------------------------------------
+ */
+
+#define SAM (SAM4_SERIES || SAMR_SERIES || SAM3_SERIES || SAMS_SERIES || SAME_SERIES || SAMD_SERIES || SAML_SERIES || SAMG_SERIES ||SAMC_SERIES)
+
+/*
+ * ----------------------------------------------------------------------------
+ * Header inclusion
+ * ----------------------------------------------------------------------------
+ */
+
+#if SAMG_SERIES
+#include "samg.h"
+#endif /* SAMG_SERIES */
+
+#if SAME_SERIES
+#include "same.h"
+#endif /* SAME_SERIES */
+
+#if SAMD_SERIES
+#include "samd.h"
+#endif /* SAMD_SERIES */
+
+#if SAML_SERIES
+#include "saml.h"
+#endif /* SAML_SERIES */
+
+#if SAMC_SERIES
+#include "samc.h"
+#endif /* SAMC_SERIES */
+
+#if SAMS_SERIES
+#include "sams.h"
+#endif /* SAMS_SERIES */
+
+#if SAM3_SERIES
+#include "sam3.h"
+#endif /* SAM3_SERIES */
+
+#if SAMR_SERIES
+#include "samr.h"
+#endif /* SAMR_SERIES */
+
+#if SAM4_SERIES
+#include "sam4.h"
+#endif /* SAM4_SERIES */
+
+#endif
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd.h
new file mode 100644
index 0000000000000000000000000000000000000000..7e304e6aecdf2dda3620231b105d03fe12a91e76
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd.h
@@ -0,0 +1,156 @@
+/* ----------------------------------------------------------------------------
+ * SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2015, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+#ifndef _SAMD_INCLUDED_
+#define _SAMD_INCLUDED_
+
+#if defined (__SAMD20E14__)
+#include "samd20/include/samd20.h"
+#elif defined (__SAMD20E15__)
+#include "samd20/include/samd20.h"
+#elif defined (__SAMD20E16__)
+#include "samd20/include/samd20.h"
+#elif defined (__SAMD20E17__)
+#include "samd20/include/samd20.h"
+#elif defined (__SAMD20E18__)
+#include "samd20/include/samd20.h"
+#elif defined (__SAMD20E1F__)
+#include "samd20/include/samd20.h"
+#elif defined (__SAMD20G14__)
+#include "samd20/include/samd20.h"
+#elif defined (__SAMD20G15__)
+#include "samd20/include/samd20.h"
+#elif defined (__SAMD20G16__)
+#include "samd20/include/samd20.h"
+#elif defined (__SAMD20G17__)
+#include "samd20/include/samd20.h"
+#elif defined (__SAMD20G18__)
+#include "samd20/include/samd20.h"
+#elif defined (__SAMD20G17U__)
+#include "samd20/include/samd20.h"
+#elif defined (__SAMD20G18U__)
+#include "samd20/include/samd20.h"
+#elif defined (__SAMD20J14__)
+#include "samd20/include/samd20.h"
+#elif defined (__SAMD20J15__)
+#include "samd20/include/samd20.h"
+#elif defined (__SAMD20J16__)
+#include "samd20/include/samd20.h"
+#elif defined (__SAMD20J17__)
+#include "samd20/include/samd20.h"
+#elif defined (__SAMD20J18__)
+#include "samd20/include/samd20.h"
+#elif defined (__SAMD21E15A__)
+#include "samd21/include/samd21.h"
+#elif defined (__SAMD21E15B__)
+#include "samd21/include/samd21.h"
+#elif defined (__SAMD21E15BU__)
+#include "samd21/include/samd21.h"
+#elif defined (__SAMD21E15L__)
+#include "samd21/include/samd21.h"
+#elif defined (__SAMD21E16A__)
+#include "samd21/include/samd21.h"
+#elif defined (__SAMD21E16B__)
+#include "samd21/include/samd21.h"
+#elif defined (__SAMD21E16BU__)
+#include "samd21/include/samd21.h"
+#elif defined (__SAMD21E16L__)
+#include "samd21/include/samd21.h"
+#elif defined (__SAMD21E17A__)
+#include "samd21/include/samd21.h"
+#elif defined (__SAMD21E18A__)
+#include "samd21/include/samd21.h"
+#elif defined (__SAMD21G15A__)
+#include "samd21/include/samd21.h"
+#elif defined (__SAMD21G15B__)
+#include "samd21/include/samd21.h"
+#elif defined (__SAMD21G15L__)
+#include "samd21/include/samd21.h"
+#elif defined (__SAMD21G16A__)
+#include "samd21/include/samd21.h"
+#elif defined (__SAMD21G16B__)
+#include "samd21/include/samd21.h"
+#elif defined (__SAMD21G16L__)
+#include "samd21/include/samd21.h"
+#elif defined (__SAMD21G17A__)
+#include "samd21/include/samd21.h"
+#elif defined (__SAMD21G17AU__)
+#include "samd21/include/samd21.h"
+#elif defined (__SAMD21G18A__)
+#include "samd21/include/samd21.h"
+#elif defined (__SAMD21G18AU__)
+#include "samd21/include/samd21.h"
+#elif defined (__SAMD21J15A__)
+#include "samd21/include/samd21.h"
+#elif defined (__SAMD21J15B__)
+#include "samd21/include/samd21.h"
+#elif defined (__SAMD21J16A__)
+#include "samd21/include/samd21.h"
+#elif defined (__SAMD21J17A__)
+#include "samd21/include/samd21.h"
+#elif defined (__SAMD21J18A__)
+#include "samd21/include/samd21.h"
+#elif defined (__SAMD21J16B__)
+#include "samd21/include/samd21.h"
+#elif defined (__SAMD10C13A__)
+#include "samd10/include/samd10.h"
+#elif defined (__SAMD10C14A__)
+#include "samd10/include/samd10.h"
+#elif defined (__SAMD10D13AS__)
+#include "samd10/include/samd10.h"
+#elif defined (__SAMD10D14AS__)
+#include "samd10/include/samd10.h"
+#elif defined (__SAMD10D13AM__)
+#include "samd10/include/samd10.h"
+#elif defined (__SAMD10D14AM__)
+#include "samd10/include/samd10.h"
+#elif defined (__SAMD11C14A__)
+#include "samd11/include/samd11.h"
+#elif defined (__SAMD11D14AS__)
+#include "samd11/include/samd11.h"
+#elif defined (__SAMD11D14AM__)
+#include "samd11/include/samd11.h"
+#elif defined (__SAMD51G18A__)
+#include "samd51/include/samd51.h"
+#elif defined (__SAMD51G19A__)
+#include "samd51/include/samd51.h"
+#elif defined (__SAMD51J19A__)
+#include "samd51/include/samd51.h"
+#elif defined (__SAMD51J20A__)
+#include "samd51/include/samd51.h"
+#elif defined (__SAMD51N19A__)
+#include "samd51/include/samd51.h"
+#elif defined (__SAMD51N20A__)
+#include "samd51/include/samd51.h"
+#elif defined (__SAMD51P19A__)
+#include "samd51/include/samd51.h"
+#elif defined (__SAMD51P20A__)
+#include "samd51/include/samd51.h"
+#endif
+
+#endif /* _SAMD_INCLUDED_ */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/component-version.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/component-version.h
new file mode 100644
index 0000000000000000000000000000000000000000..f388feb0b447e9f19964250ea00a75b75341c62b
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/component-version.h
@@ -0,0 +1,72 @@
+/*****************************************************************************
+ *
+ * Copyright (C) 2015 Atmel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ****************************************************************************/
+
+
+#ifndef _COMPONENT_VERSION_H_INCLUDED
+#define _COMPONENT_VERSION_H_INCLUDED
+
+#define COMPONENT_VERSION_MAJOR 1
+#define COMPONENT_VERSION_MINOR 0
+
+//
+// The COMPONENT_VERSION define is composed of the major and the minor version number.
+//
+// The last four digits of the COMPONENT_VERSION is the minor version with leading zeros.
+// The rest of the COMPONENT_VERSION is the major version, with leading zeros. The COMPONENT_VERSION
+// is at least 8 digits long.
+//
+#define COMPONENT_VERSION 00010000
+
+//
+// The build number does not refer to the component, but to the build number
+// of the device pack that provides the component.
+//
+#define BUILD_NUMBER 222
+
+//
+// The COMPONENT_VERSION_STRING is a string (enclosed in ") that can be used for logging or embedding.
+//
+#define COMPONENT_VERSION_STRING "1.0"
+
+//
+// The COMPONENT_DATE_STRING contains a timestamp of when the pack was generated.
+//
+// The COMPONENT_DATE_STRING is written out using the following strftime pattern.
+//
+// "%Y-%m-%d %H:%M:%S"
+//
+//
+#define COMPONENT_DATE_STRING "2015-09-09 22:27:54"
+
+#endif/* #ifndef _COMPONENT_VERSION_H_INCLUDED */
+
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/component/ac.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/component/ac.h
new file mode 100644
index 0000000000000000000000000000000000000000..54882c62c8a482712632933db0da431c90e95b56
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/component/ac.h
@@ -0,0 +1,559 @@
+/**
+ * \file
+ *
+ * \brief Component description for AC
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_AC_COMPONENT_
+#define _SAMD21_AC_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR AC */
+/* ========================================================================== */
+/** \addtogroup SAMD21_AC Analog Comparators */
+/*@{*/
+
+#define AC_U2205
+#define REV_AC 0x111
+
+/* -------- AC_CTRLA : (AC Offset: 0x00) (R/W 8) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t ENABLE:1; /*!< bit: 1 Enable */
+ uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */
+ uint8_t :4; /*!< bit: 3.. 6 Reserved */
+ uint8_t LPMUX:1; /*!< bit: 7 Low-Power Mux */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} AC_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_CTRLA_OFFSET 0x00 /**< \brief (AC_CTRLA offset) Control A */
+#define AC_CTRLA_RESETVALUE 0x00ul /**< \brief (AC_CTRLA reset_value) Control A */
+
+#define AC_CTRLA_SWRST_Pos 0 /**< \brief (AC_CTRLA) Software Reset */
+#define AC_CTRLA_SWRST (0x1ul << AC_CTRLA_SWRST_Pos)
+#define AC_CTRLA_ENABLE_Pos 1 /**< \brief (AC_CTRLA) Enable */
+#define AC_CTRLA_ENABLE (0x1ul << AC_CTRLA_ENABLE_Pos)
+#define AC_CTRLA_RUNSTDBY_Pos 2 /**< \brief (AC_CTRLA) Run in Standby */
+#define AC_CTRLA_RUNSTDBY_Msk (0x1ul << AC_CTRLA_RUNSTDBY_Pos)
+#define AC_CTRLA_RUNSTDBY(value) (AC_CTRLA_RUNSTDBY_Msk & ((value) << AC_CTRLA_RUNSTDBY_Pos))
+#define AC_CTRLA_LPMUX_Pos 7 /**< \brief (AC_CTRLA) Low-Power Mux */
+#define AC_CTRLA_LPMUX (0x1ul << AC_CTRLA_LPMUX_Pos)
+#define AC_CTRLA_MASK 0x87ul /**< \brief (AC_CTRLA) MASK Register */
+
+/* -------- AC_CTRLB : (AC Offset: 0x01) ( /W 8) Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t START0:1; /*!< bit: 0 Comparator 0 Start Comparison */
+ uint8_t START1:1; /*!< bit: 1 Comparator 1 Start Comparison */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t START:2; /*!< bit: 0.. 1 Comparator x Start Comparison */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} AC_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_CTRLB_OFFSET 0x01 /**< \brief (AC_CTRLB offset) Control B */
+#define AC_CTRLB_RESETVALUE 0x00ul /**< \brief (AC_CTRLB reset_value) Control B */
+
+#define AC_CTRLB_START0_Pos 0 /**< \brief (AC_CTRLB) Comparator 0 Start Comparison */
+#define AC_CTRLB_START0 (1 << AC_CTRLB_START0_Pos)
+#define AC_CTRLB_START1_Pos 1 /**< \brief (AC_CTRLB) Comparator 1 Start Comparison */
+#define AC_CTRLB_START1 (1 << AC_CTRLB_START1_Pos)
+#define AC_CTRLB_START_Pos 0 /**< \brief (AC_CTRLB) Comparator x Start Comparison */
+#define AC_CTRLB_START_Msk (0x3ul << AC_CTRLB_START_Pos)
+#define AC_CTRLB_START(value) (AC_CTRLB_START_Msk & ((value) << AC_CTRLB_START_Pos))
+#define AC_CTRLB_MASK 0x03ul /**< \brief (AC_CTRLB) MASK Register */
+
+/* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t COMPEO0:1; /*!< bit: 0 Comparator 0 Event Output Enable */
+ uint16_t COMPEO1:1; /*!< bit: 1 Comparator 1 Event Output Enable */
+ uint16_t :2; /*!< bit: 2.. 3 Reserved */
+ uint16_t WINEO0:1; /*!< bit: 4 Window 0 Event Output Enable */
+ uint16_t :3; /*!< bit: 5.. 7 Reserved */
+ uint16_t COMPEI0:1; /*!< bit: 8 Comparator 0 Event Input */
+ uint16_t COMPEI1:1; /*!< bit: 9 Comparator 1 Event Input */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t COMPEO:2; /*!< bit: 0.. 1 Comparator x Event Output Enable */
+ uint16_t :2; /*!< bit: 2.. 3 Reserved */
+ uint16_t WINEO:1; /*!< bit: 4 Window x Event Output Enable */
+ uint16_t :3; /*!< bit: 5.. 7 Reserved */
+ uint16_t COMPEI:2; /*!< bit: 8.. 9 Comparator x Event Input */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} AC_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_EVCTRL_OFFSET 0x02 /**< \brief (AC_EVCTRL offset) Event Control */
+#define AC_EVCTRL_RESETVALUE 0x0000ul /**< \brief (AC_EVCTRL reset_value) Event Control */
+
+#define AC_EVCTRL_COMPEO0_Pos 0 /**< \brief (AC_EVCTRL) Comparator 0 Event Output Enable */
+#define AC_EVCTRL_COMPEO0 (1 << AC_EVCTRL_COMPEO0_Pos)
+#define AC_EVCTRL_COMPEO1_Pos 1 /**< \brief (AC_EVCTRL) Comparator 1 Event Output Enable */
+#define AC_EVCTRL_COMPEO1 (1 << AC_EVCTRL_COMPEO1_Pos)
+#define AC_EVCTRL_COMPEO_Pos 0 /**< \brief (AC_EVCTRL) Comparator x Event Output Enable */
+#define AC_EVCTRL_COMPEO_Msk (0x3ul << AC_EVCTRL_COMPEO_Pos)
+#define AC_EVCTRL_COMPEO(value) (AC_EVCTRL_COMPEO_Msk & ((value) << AC_EVCTRL_COMPEO_Pos))
+#define AC_EVCTRL_WINEO0_Pos 4 /**< \brief (AC_EVCTRL) Window 0 Event Output Enable */
+#define AC_EVCTRL_WINEO0 (1 << AC_EVCTRL_WINEO0_Pos)
+#define AC_EVCTRL_WINEO_Pos 4 /**< \brief (AC_EVCTRL) Window x Event Output Enable */
+#define AC_EVCTRL_WINEO_Msk (0x1ul << AC_EVCTRL_WINEO_Pos)
+#define AC_EVCTRL_WINEO(value) (AC_EVCTRL_WINEO_Msk & ((value) << AC_EVCTRL_WINEO_Pos))
+#define AC_EVCTRL_COMPEI0_Pos 8 /**< \brief (AC_EVCTRL) Comparator 0 Event Input */
+#define AC_EVCTRL_COMPEI0 (1 << AC_EVCTRL_COMPEI0_Pos)
+#define AC_EVCTRL_COMPEI1_Pos 9 /**< \brief (AC_EVCTRL) Comparator 1 Event Input */
+#define AC_EVCTRL_COMPEI1 (1 << AC_EVCTRL_COMPEI1_Pos)
+#define AC_EVCTRL_COMPEI_Pos 8 /**< \brief (AC_EVCTRL) Comparator x Event Input */
+#define AC_EVCTRL_COMPEI_Msk (0x3ul << AC_EVCTRL_COMPEI_Pos)
+#define AC_EVCTRL_COMPEI(value) (AC_EVCTRL_COMPEI_Msk & ((value) << AC_EVCTRL_COMPEI_Pos))
+#define AC_EVCTRL_MASK 0x0313ul /**< \brief (AC_EVCTRL) MASK Register */
+
+/* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */
+ uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} AC_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_INTENCLR_OFFSET 0x04 /**< \brief (AC_INTENCLR offset) Interrupt Enable Clear */
+#define AC_INTENCLR_RESETVALUE 0x00ul /**< \brief (AC_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define AC_INTENCLR_COMP0_Pos 0 /**< \brief (AC_INTENCLR) Comparator 0 Interrupt Enable */
+#define AC_INTENCLR_COMP0 (1 << AC_INTENCLR_COMP0_Pos)
+#define AC_INTENCLR_COMP1_Pos 1 /**< \brief (AC_INTENCLR) Comparator 1 Interrupt Enable */
+#define AC_INTENCLR_COMP1 (1 << AC_INTENCLR_COMP1_Pos)
+#define AC_INTENCLR_COMP_Pos 0 /**< \brief (AC_INTENCLR) Comparator x Interrupt Enable */
+#define AC_INTENCLR_COMP_Msk (0x3ul << AC_INTENCLR_COMP_Pos)
+#define AC_INTENCLR_COMP(value) (AC_INTENCLR_COMP_Msk & ((value) << AC_INTENCLR_COMP_Pos))
+#define AC_INTENCLR_WIN0_Pos 4 /**< \brief (AC_INTENCLR) Window 0 Interrupt Enable */
+#define AC_INTENCLR_WIN0 (1 << AC_INTENCLR_WIN0_Pos)
+#define AC_INTENCLR_WIN_Pos 4 /**< \brief (AC_INTENCLR) Window x Interrupt Enable */
+#define AC_INTENCLR_WIN_Msk (0x1ul << AC_INTENCLR_WIN_Pos)
+#define AC_INTENCLR_WIN(value) (AC_INTENCLR_WIN_Msk & ((value) << AC_INTENCLR_WIN_Pos))
+#define AC_INTENCLR_MASK 0x13ul /**< \brief (AC_INTENCLR) MASK Register */
+
+/* -------- AC_INTENSET : (AC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */
+ uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} AC_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_INTENSET_OFFSET 0x05 /**< \brief (AC_INTENSET offset) Interrupt Enable Set */
+#define AC_INTENSET_RESETVALUE 0x00ul /**< \brief (AC_INTENSET reset_value) Interrupt Enable Set */
+
+#define AC_INTENSET_COMP0_Pos 0 /**< \brief (AC_INTENSET) Comparator 0 Interrupt Enable */
+#define AC_INTENSET_COMP0 (1 << AC_INTENSET_COMP0_Pos)
+#define AC_INTENSET_COMP1_Pos 1 /**< \brief (AC_INTENSET) Comparator 1 Interrupt Enable */
+#define AC_INTENSET_COMP1 (1 << AC_INTENSET_COMP1_Pos)
+#define AC_INTENSET_COMP_Pos 0 /**< \brief (AC_INTENSET) Comparator x Interrupt Enable */
+#define AC_INTENSET_COMP_Msk (0x3ul << AC_INTENSET_COMP_Pos)
+#define AC_INTENSET_COMP(value) (AC_INTENSET_COMP_Msk & ((value) << AC_INTENSET_COMP_Pos))
+#define AC_INTENSET_WIN0_Pos 4 /**< \brief (AC_INTENSET) Window 0 Interrupt Enable */
+#define AC_INTENSET_WIN0 (1 << AC_INTENSET_WIN0_Pos)
+#define AC_INTENSET_WIN_Pos 4 /**< \brief (AC_INTENSET) Window x Interrupt Enable */
+#define AC_INTENSET_WIN_Msk (0x1ul << AC_INTENSET_WIN_Pos)
+#define AC_INTENSET_WIN(value) (AC_INTENSET_WIN_Msk & ((value) << AC_INTENSET_WIN_Pos))
+#define AC_INTENSET_MASK 0x13ul /**< \brief (AC_INTENSET) MASK Register */
+
+/* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint8_t COMP0:1; /*!< bit: 0 Comparator 0 */
+ __I uint8_t COMP1:1; /*!< bit: 1 Comparator 1 */
+ __I uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ __I uint8_t WIN0:1; /*!< bit: 4 Window 0 */
+ __I uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ __I uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x */
+ __I uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ __I uint8_t WIN:1; /*!< bit: 4 Window x */
+ __I uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} AC_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_INTFLAG_OFFSET 0x06 /**< \brief (AC_INTFLAG offset) Interrupt Flag Status and Clear */
+#define AC_INTFLAG_RESETVALUE 0x00ul /**< \brief (AC_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define AC_INTFLAG_COMP0_Pos 0 /**< \brief (AC_INTFLAG) Comparator 0 */
+#define AC_INTFLAG_COMP0 (1 << AC_INTFLAG_COMP0_Pos)
+#define AC_INTFLAG_COMP1_Pos 1 /**< \brief (AC_INTFLAG) Comparator 1 */
+#define AC_INTFLAG_COMP1 (1 << AC_INTFLAG_COMP1_Pos)
+#define AC_INTFLAG_COMP_Pos 0 /**< \brief (AC_INTFLAG) Comparator x */
+#define AC_INTFLAG_COMP_Msk (0x3ul << AC_INTFLAG_COMP_Pos)
+#define AC_INTFLAG_COMP(value) (AC_INTFLAG_COMP_Msk & ((value) << AC_INTFLAG_COMP_Pos))
+#define AC_INTFLAG_WIN0_Pos 4 /**< \brief (AC_INTFLAG) Window 0 */
+#define AC_INTFLAG_WIN0 (1 << AC_INTFLAG_WIN0_Pos)
+#define AC_INTFLAG_WIN_Pos 4 /**< \brief (AC_INTFLAG) Window x */
+#define AC_INTFLAG_WIN_Msk (0x1ul << AC_INTFLAG_WIN_Pos)
+#define AC_INTFLAG_WIN(value) (AC_INTFLAG_WIN_Msk & ((value) << AC_INTFLAG_WIN_Pos))
+#define AC_INTFLAG_MASK 0x13ul /**< \brief (AC_INTFLAG) MASK Register */
+
+/* -------- AC_STATUSA : (AC Offset: 0x08) (R/ 8) Status A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */
+ uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} AC_STATUSA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_STATUSA_OFFSET 0x08 /**< \brief (AC_STATUSA offset) Status A */
+#define AC_STATUSA_RESETVALUE 0x00ul /**< \brief (AC_STATUSA reset_value) Status A */
+
+#define AC_STATUSA_STATE0_Pos 0 /**< \brief (AC_STATUSA) Comparator 0 Current State */
+#define AC_STATUSA_STATE0 (1 << AC_STATUSA_STATE0_Pos)
+#define AC_STATUSA_STATE1_Pos 1 /**< \brief (AC_STATUSA) Comparator 1 Current State */
+#define AC_STATUSA_STATE1 (1 << AC_STATUSA_STATE1_Pos)
+#define AC_STATUSA_STATE_Pos 0 /**< \brief (AC_STATUSA) Comparator x Current State */
+#define AC_STATUSA_STATE_Msk (0x3ul << AC_STATUSA_STATE_Pos)
+#define AC_STATUSA_STATE(value) (AC_STATUSA_STATE_Msk & ((value) << AC_STATUSA_STATE_Pos))
+#define AC_STATUSA_WSTATE0_Pos 4 /**< \brief (AC_STATUSA) Window 0 Current State */
+#define AC_STATUSA_WSTATE0_Msk (0x3ul << AC_STATUSA_WSTATE0_Pos)
+#define AC_STATUSA_WSTATE0(value) (AC_STATUSA_WSTATE0_Msk & ((value) << AC_STATUSA_WSTATE0_Pos))
+#define AC_STATUSA_WSTATE0_ABOVE_Val 0x0ul /**< \brief (AC_STATUSA) Signal is above window */
+#define AC_STATUSA_WSTATE0_INSIDE_Val 0x1ul /**< \brief (AC_STATUSA) Signal is inside window */
+#define AC_STATUSA_WSTATE0_BELOW_Val 0x2ul /**< \brief (AC_STATUSA) Signal is below window */
+#define AC_STATUSA_WSTATE0_ABOVE (AC_STATUSA_WSTATE0_ABOVE_Val << AC_STATUSA_WSTATE0_Pos)
+#define AC_STATUSA_WSTATE0_INSIDE (AC_STATUSA_WSTATE0_INSIDE_Val << AC_STATUSA_WSTATE0_Pos)
+#define AC_STATUSA_WSTATE0_BELOW (AC_STATUSA_WSTATE0_BELOW_Val << AC_STATUSA_WSTATE0_Pos)
+#define AC_STATUSA_MASK 0x33ul /**< \brief (AC_STATUSA) MASK Register */
+
+/* -------- AC_STATUSB : (AC Offset: 0x09) (R/ 8) Status B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t READY0:1; /*!< bit: 0 Comparator 0 Ready */
+ uint8_t READY1:1; /*!< bit: 1 Comparator 1 Ready */
+ uint8_t :5; /*!< bit: 2.. 6 Reserved */
+ uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t READY:2; /*!< bit: 0.. 1 Comparator x Ready */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} AC_STATUSB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_STATUSB_OFFSET 0x09 /**< \brief (AC_STATUSB offset) Status B */
+#define AC_STATUSB_RESETVALUE 0x00ul /**< \brief (AC_STATUSB reset_value) Status B */
+
+#define AC_STATUSB_READY0_Pos 0 /**< \brief (AC_STATUSB) Comparator 0 Ready */
+#define AC_STATUSB_READY0 (1 << AC_STATUSB_READY0_Pos)
+#define AC_STATUSB_READY1_Pos 1 /**< \brief (AC_STATUSB) Comparator 1 Ready */
+#define AC_STATUSB_READY1 (1 << AC_STATUSB_READY1_Pos)
+#define AC_STATUSB_READY_Pos 0 /**< \brief (AC_STATUSB) Comparator x Ready */
+#define AC_STATUSB_READY_Msk (0x3ul << AC_STATUSB_READY_Pos)
+#define AC_STATUSB_READY(value) (AC_STATUSB_READY_Msk & ((value) << AC_STATUSB_READY_Pos))
+#define AC_STATUSB_SYNCBUSY_Pos 7 /**< \brief (AC_STATUSB) Synchronization Busy */
+#define AC_STATUSB_SYNCBUSY (0x1ul << AC_STATUSB_SYNCBUSY_Pos)
+#define AC_STATUSB_MASK 0x83ul /**< \brief (AC_STATUSB) MASK Register */
+
+/* -------- AC_STATUSC : (AC Offset: 0x0A) (R/ 8) Status C -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */
+ uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} AC_STATUSC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_STATUSC_OFFSET 0x0A /**< \brief (AC_STATUSC offset) Status C */
+#define AC_STATUSC_RESETVALUE 0x00ul /**< \brief (AC_STATUSC reset_value) Status C */
+
+#define AC_STATUSC_STATE0_Pos 0 /**< \brief (AC_STATUSC) Comparator 0 Current State */
+#define AC_STATUSC_STATE0 (1 << AC_STATUSC_STATE0_Pos)
+#define AC_STATUSC_STATE1_Pos 1 /**< \brief (AC_STATUSC) Comparator 1 Current State */
+#define AC_STATUSC_STATE1 (1 << AC_STATUSC_STATE1_Pos)
+#define AC_STATUSC_STATE_Pos 0 /**< \brief (AC_STATUSC) Comparator x Current State */
+#define AC_STATUSC_STATE_Msk (0x3ul << AC_STATUSC_STATE_Pos)
+#define AC_STATUSC_STATE(value) (AC_STATUSC_STATE_Msk & ((value) << AC_STATUSC_STATE_Pos))
+#define AC_STATUSC_WSTATE0_Pos 4 /**< \brief (AC_STATUSC) Window 0 Current State */
+#define AC_STATUSC_WSTATE0_Msk (0x3ul << AC_STATUSC_WSTATE0_Pos)
+#define AC_STATUSC_WSTATE0(value) (AC_STATUSC_WSTATE0_Msk & ((value) << AC_STATUSC_WSTATE0_Pos))
+#define AC_STATUSC_WSTATE0_ABOVE_Val 0x0ul /**< \brief (AC_STATUSC) Signal is above window */
+#define AC_STATUSC_WSTATE0_INSIDE_Val 0x1ul /**< \brief (AC_STATUSC) Signal is inside window */
+#define AC_STATUSC_WSTATE0_BELOW_Val 0x2ul /**< \brief (AC_STATUSC) Signal is below window */
+#define AC_STATUSC_WSTATE0_ABOVE (AC_STATUSC_WSTATE0_ABOVE_Val << AC_STATUSC_WSTATE0_Pos)
+#define AC_STATUSC_WSTATE0_INSIDE (AC_STATUSC_WSTATE0_INSIDE_Val << AC_STATUSC_WSTATE0_Pos)
+#define AC_STATUSC_WSTATE0_BELOW (AC_STATUSC_WSTATE0_BELOW_Val << AC_STATUSC_WSTATE0_Pos)
+#define AC_STATUSC_MASK 0x33ul /**< \brief (AC_STATUSC) MASK Register */
+
+/* -------- AC_WINCTRL : (AC Offset: 0x0C) (R/W 8) Window Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t WEN0:1; /*!< bit: 0 Window 0 Mode Enable */
+ uint8_t WINTSEL0:2; /*!< bit: 1.. 2 Window 0 Interrupt Selection */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} AC_WINCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_WINCTRL_OFFSET 0x0C /**< \brief (AC_WINCTRL offset) Window Control */
+#define AC_WINCTRL_RESETVALUE 0x00ul /**< \brief (AC_WINCTRL reset_value) Window Control */
+
+#define AC_WINCTRL_WEN0_Pos 0 /**< \brief (AC_WINCTRL) Window 0 Mode Enable */
+#define AC_WINCTRL_WEN0 (0x1ul << AC_WINCTRL_WEN0_Pos)
+#define AC_WINCTRL_WINTSEL0_Pos 1 /**< \brief (AC_WINCTRL) Window 0 Interrupt Selection */
+#define AC_WINCTRL_WINTSEL0_Msk (0x3ul << AC_WINCTRL_WINTSEL0_Pos)
+#define AC_WINCTRL_WINTSEL0(value) (AC_WINCTRL_WINTSEL0_Msk & ((value) << AC_WINCTRL_WINTSEL0_Pos))
+#define AC_WINCTRL_WINTSEL0_ABOVE_Val 0x0ul /**< \brief (AC_WINCTRL) Interrupt on signal above window */
+#define AC_WINCTRL_WINTSEL0_INSIDE_Val 0x1ul /**< \brief (AC_WINCTRL) Interrupt on signal inside window */
+#define AC_WINCTRL_WINTSEL0_BELOW_Val 0x2ul /**< \brief (AC_WINCTRL) Interrupt on signal below window */
+#define AC_WINCTRL_WINTSEL0_OUTSIDE_Val 0x3ul /**< \brief (AC_WINCTRL) Interrupt on signal outside window */
+#define AC_WINCTRL_WINTSEL0_ABOVE (AC_WINCTRL_WINTSEL0_ABOVE_Val << AC_WINCTRL_WINTSEL0_Pos)
+#define AC_WINCTRL_WINTSEL0_INSIDE (AC_WINCTRL_WINTSEL0_INSIDE_Val << AC_WINCTRL_WINTSEL0_Pos)
+#define AC_WINCTRL_WINTSEL0_BELOW (AC_WINCTRL_WINTSEL0_BELOW_Val << AC_WINCTRL_WINTSEL0_Pos)
+#define AC_WINCTRL_WINTSEL0_OUTSIDE (AC_WINCTRL_WINTSEL0_OUTSIDE_Val << AC_WINCTRL_WINTSEL0_Pos)
+#define AC_WINCTRL_MASK 0x07ul /**< \brief (AC_WINCTRL) MASK Register */
+
+/* -------- AC_COMPCTRL : (AC Offset: 0x10) (R/W 32) Comparator Control n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ENABLE:1; /*!< bit: 0 Enable */
+ uint32_t SINGLE:1; /*!< bit: 1 Single-Shot Mode */
+ uint32_t SPEED:2; /*!< bit: 2.. 3 Speed Selection */
+ uint32_t :1; /*!< bit: 4 Reserved */
+ uint32_t INTSEL:2; /*!< bit: 5.. 6 Interrupt Selection */
+ uint32_t :1; /*!< bit: 7 Reserved */
+ uint32_t MUXNEG:3; /*!< bit: 8..10 Negative Input Mux Selection */
+ uint32_t :1; /*!< bit: 11 Reserved */
+ uint32_t MUXPOS:2; /*!< bit: 12..13 Positive Input Mux Selection */
+ uint32_t :1; /*!< bit: 14 Reserved */
+ uint32_t SWAP:1; /*!< bit: 15 Swap Inputs and Invert */
+ uint32_t OUT:2; /*!< bit: 16..17 Output */
+ uint32_t :1; /*!< bit: 18 Reserved */
+ uint32_t HYST:1; /*!< bit: 19 Hysteresis Enable */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t FLEN:3; /*!< bit: 24..26 Filter Length */
+ uint32_t :5; /*!< bit: 27..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} AC_COMPCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_COMPCTRL_OFFSET 0x10 /**< \brief (AC_COMPCTRL offset) Comparator Control n */
+#define AC_COMPCTRL_RESETVALUE 0x00000000ul /**< \brief (AC_COMPCTRL reset_value) Comparator Control n */
+
+#define AC_COMPCTRL_ENABLE_Pos 0 /**< \brief (AC_COMPCTRL) Enable */
+#define AC_COMPCTRL_ENABLE (0x1ul << AC_COMPCTRL_ENABLE_Pos)
+#define AC_COMPCTRL_SINGLE_Pos 1 /**< \brief (AC_COMPCTRL) Single-Shot Mode */
+#define AC_COMPCTRL_SINGLE (0x1ul << AC_COMPCTRL_SINGLE_Pos)
+#define AC_COMPCTRL_SPEED_Pos 2 /**< \brief (AC_COMPCTRL) Speed Selection */
+#define AC_COMPCTRL_SPEED_Msk (0x3ul << AC_COMPCTRL_SPEED_Pos)
+#define AC_COMPCTRL_SPEED(value) (AC_COMPCTRL_SPEED_Msk & ((value) << AC_COMPCTRL_SPEED_Pos))
+#define AC_COMPCTRL_SPEED_LOW_Val 0x0ul /**< \brief (AC_COMPCTRL) Low speed */
+#define AC_COMPCTRL_SPEED_HIGH_Val 0x1ul /**< \brief (AC_COMPCTRL) High speed */
+#define AC_COMPCTRL_SPEED_LOW (AC_COMPCTRL_SPEED_LOW_Val << AC_COMPCTRL_SPEED_Pos)
+#define AC_COMPCTRL_SPEED_HIGH (AC_COMPCTRL_SPEED_HIGH_Val << AC_COMPCTRL_SPEED_Pos)
+#define AC_COMPCTRL_INTSEL_Pos 5 /**< \brief (AC_COMPCTRL) Interrupt Selection */
+#define AC_COMPCTRL_INTSEL_Msk (0x3ul << AC_COMPCTRL_INTSEL_Pos)
+#define AC_COMPCTRL_INTSEL(value) (AC_COMPCTRL_INTSEL_Msk & ((value) << AC_COMPCTRL_INTSEL_Pos))
+#define AC_COMPCTRL_INTSEL_TOGGLE_Val 0x0ul /**< \brief (AC_COMPCTRL) Interrupt on comparator output toggle */
+#define AC_COMPCTRL_INTSEL_RISING_Val 0x1ul /**< \brief (AC_COMPCTRL) Interrupt on comparator output rising */
+#define AC_COMPCTRL_INTSEL_FALLING_Val 0x2ul /**< \brief (AC_COMPCTRL) Interrupt on comparator output falling */
+#define AC_COMPCTRL_INTSEL_EOC_Val 0x3ul /**< \brief (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only) */
+#define AC_COMPCTRL_INTSEL_TOGGLE (AC_COMPCTRL_INTSEL_TOGGLE_Val << AC_COMPCTRL_INTSEL_Pos)
+#define AC_COMPCTRL_INTSEL_RISING (AC_COMPCTRL_INTSEL_RISING_Val << AC_COMPCTRL_INTSEL_Pos)
+#define AC_COMPCTRL_INTSEL_FALLING (AC_COMPCTRL_INTSEL_FALLING_Val << AC_COMPCTRL_INTSEL_Pos)
+#define AC_COMPCTRL_INTSEL_EOC (AC_COMPCTRL_INTSEL_EOC_Val << AC_COMPCTRL_INTSEL_Pos)
+#define AC_COMPCTRL_MUXNEG_Pos 8 /**< \brief (AC_COMPCTRL) Negative Input Mux Selection */
+#define AC_COMPCTRL_MUXNEG_Msk (0x7ul << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG(value) (AC_COMPCTRL_MUXNEG_Msk & ((value) << AC_COMPCTRL_MUXNEG_Pos))
+#define AC_COMPCTRL_MUXNEG_PIN0_Val 0x0ul /**< \brief (AC_COMPCTRL) I/O pin 0 */
+#define AC_COMPCTRL_MUXNEG_PIN1_Val 0x1ul /**< \brief (AC_COMPCTRL) I/O pin 1 */
+#define AC_COMPCTRL_MUXNEG_PIN2_Val 0x2ul /**< \brief (AC_COMPCTRL) I/O pin 2 */
+#define AC_COMPCTRL_MUXNEG_PIN3_Val 0x3ul /**< \brief (AC_COMPCTRL) I/O pin 3 */
+#define AC_COMPCTRL_MUXNEG_GND_Val 0x4ul /**< \brief (AC_COMPCTRL) Ground */
+#define AC_COMPCTRL_MUXNEG_VSCALE_Val 0x5ul /**< \brief (AC_COMPCTRL) VDD scaler */
+#define AC_COMPCTRL_MUXNEG_BANDGAP_Val 0x6ul /**< \brief (AC_COMPCTRL) Internal bandgap voltage */
+#define AC_COMPCTRL_MUXNEG_DAC_Val 0x7ul /**< \brief (AC_COMPCTRL) DAC output */
+#define AC_COMPCTRL_MUXNEG_PIN0 (AC_COMPCTRL_MUXNEG_PIN0_Val << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_PIN1 (AC_COMPCTRL_MUXNEG_PIN1_Val << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_PIN2 (AC_COMPCTRL_MUXNEG_PIN2_Val << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_PIN3 (AC_COMPCTRL_MUXNEG_PIN3_Val << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_GND (AC_COMPCTRL_MUXNEG_GND_Val << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_VSCALE (AC_COMPCTRL_MUXNEG_VSCALE_Val << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_BANDGAP (AC_COMPCTRL_MUXNEG_BANDGAP_Val << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXNEG_DAC (AC_COMPCTRL_MUXNEG_DAC_Val << AC_COMPCTRL_MUXNEG_Pos)
+#define AC_COMPCTRL_MUXPOS_Pos 12 /**< \brief (AC_COMPCTRL) Positive Input Mux Selection */
+#define AC_COMPCTRL_MUXPOS_Msk (0x3ul << AC_COMPCTRL_MUXPOS_Pos)
+#define AC_COMPCTRL_MUXPOS(value) (AC_COMPCTRL_MUXPOS_Msk & ((value) << AC_COMPCTRL_MUXPOS_Pos))
+#define AC_COMPCTRL_MUXPOS_PIN0_Val 0x0ul /**< \brief (AC_COMPCTRL) I/O pin 0 */
+#define AC_COMPCTRL_MUXPOS_PIN1_Val 0x1ul /**< \brief (AC_COMPCTRL) I/O pin 1 */
+#define AC_COMPCTRL_MUXPOS_PIN2_Val 0x2ul /**< \brief (AC_COMPCTRL) I/O pin 2 */
+#define AC_COMPCTRL_MUXPOS_PIN3_Val 0x3ul /**< \brief (AC_COMPCTRL) I/O pin 3 */
+#define AC_COMPCTRL_MUXPOS_PIN0 (AC_COMPCTRL_MUXPOS_PIN0_Val << AC_COMPCTRL_MUXPOS_Pos)
+#define AC_COMPCTRL_MUXPOS_PIN1 (AC_COMPCTRL_MUXPOS_PIN1_Val << AC_COMPCTRL_MUXPOS_Pos)
+#define AC_COMPCTRL_MUXPOS_PIN2 (AC_COMPCTRL_MUXPOS_PIN2_Val << AC_COMPCTRL_MUXPOS_Pos)
+#define AC_COMPCTRL_MUXPOS_PIN3 (AC_COMPCTRL_MUXPOS_PIN3_Val << AC_COMPCTRL_MUXPOS_Pos)
+#define AC_COMPCTRL_SWAP_Pos 15 /**< \brief (AC_COMPCTRL) Swap Inputs and Invert */
+#define AC_COMPCTRL_SWAP (0x1ul << AC_COMPCTRL_SWAP_Pos)
+#define AC_COMPCTRL_OUT_Pos 16 /**< \brief (AC_COMPCTRL) Output */
+#define AC_COMPCTRL_OUT_Msk (0x3ul << AC_COMPCTRL_OUT_Pos)
+#define AC_COMPCTRL_OUT(value) (AC_COMPCTRL_OUT_Msk & ((value) << AC_COMPCTRL_OUT_Pos))
+#define AC_COMPCTRL_OUT_OFF_Val 0x0ul /**< \brief (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port */
+#define AC_COMPCTRL_OUT_ASYNC_Val 0x1ul /**< \brief (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port */
+#define AC_COMPCTRL_OUT_SYNC_Val 0x2ul /**< \brief (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port */
+#define AC_COMPCTRL_OUT_OFF (AC_COMPCTRL_OUT_OFF_Val << AC_COMPCTRL_OUT_Pos)
+#define AC_COMPCTRL_OUT_ASYNC (AC_COMPCTRL_OUT_ASYNC_Val << AC_COMPCTRL_OUT_Pos)
+#define AC_COMPCTRL_OUT_SYNC (AC_COMPCTRL_OUT_SYNC_Val << AC_COMPCTRL_OUT_Pos)
+#define AC_COMPCTRL_HYST_Pos 19 /**< \brief (AC_COMPCTRL) Hysteresis Enable */
+#define AC_COMPCTRL_HYST (0x1ul << AC_COMPCTRL_HYST_Pos)
+#define AC_COMPCTRL_FLEN_Pos 24 /**< \brief (AC_COMPCTRL) Filter Length */
+#define AC_COMPCTRL_FLEN_Msk (0x7ul << AC_COMPCTRL_FLEN_Pos)
+#define AC_COMPCTRL_FLEN(value) (AC_COMPCTRL_FLEN_Msk & ((value) << AC_COMPCTRL_FLEN_Pos))
+#define AC_COMPCTRL_FLEN_OFF_Val 0x0ul /**< \brief (AC_COMPCTRL) No filtering */
+#define AC_COMPCTRL_FLEN_MAJ3_Val 0x1ul /**< \brief (AC_COMPCTRL) 3-bit majority function (2 of 3) */
+#define AC_COMPCTRL_FLEN_MAJ5_Val 0x2ul /**< \brief (AC_COMPCTRL) 5-bit majority function (3 of 5) */
+#define AC_COMPCTRL_FLEN_OFF (AC_COMPCTRL_FLEN_OFF_Val << AC_COMPCTRL_FLEN_Pos)
+#define AC_COMPCTRL_FLEN_MAJ3 (AC_COMPCTRL_FLEN_MAJ3_Val << AC_COMPCTRL_FLEN_Pos)
+#define AC_COMPCTRL_FLEN_MAJ5 (AC_COMPCTRL_FLEN_MAJ5_Val << AC_COMPCTRL_FLEN_Pos)
+#define AC_COMPCTRL_MASK 0x070BB76Ful /**< \brief (AC_COMPCTRL) MASK Register */
+
+/* -------- AC_SCALER : (AC Offset: 0x20) (R/W 8) Scaler n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t VALUE:6; /*!< bit: 0.. 5 Scaler Value */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} AC_SCALER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define AC_SCALER_OFFSET 0x20 /**< \brief (AC_SCALER offset) Scaler n */
+#define AC_SCALER_RESETVALUE 0x00ul /**< \brief (AC_SCALER reset_value) Scaler n */
+
+#define AC_SCALER_VALUE_Pos 0 /**< \brief (AC_SCALER) Scaler Value */
+#define AC_SCALER_VALUE_Msk (0x3Ful << AC_SCALER_VALUE_Pos)
+#define AC_SCALER_VALUE(value) (AC_SCALER_VALUE_Msk & ((value) << AC_SCALER_VALUE_Pos))
+#define AC_SCALER_MASK 0x3Ful /**< \brief (AC_SCALER) MASK Register */
+
+/** \brief AC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO AC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
+ __O AC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B */
+ __IO AC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 16) Event Control */
+ __IO AC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */
+ __IO AC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */
+ __IO AC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */
+ RoReg8 Reserved1[0x1];
+ __I AC_STATUSA_Type STATUSA; /**< \brief Offset: 0x08 (R/ 8) Status A */
+ __I AC_STATUSB_Type STATUSB; /**< \brief Offset: 0x09 (R/ 8) Status B */
+ __I AC_STATUSC_Type STATUSC; /**< \brief Offset: 0x0A (R/ 8) Status C */
+ RoReg8 Reserved2[0x1];
+ __IO AC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x0C (R/W 8) Window Control */
+ RoReg8 Reserved3[0x3];
+ __IO AC_COMPCTRL_Type COMPCTRL[2]; /**< \brief Offset: 0x10 (R/W 32) Comparator Control n */
+ RoReg8 Reserved4[0x8];
+ __IO AC_SCALER_Type SCALER[2]; /**< \brief Offset: 0x20 (R/W 8) Scaler n */
+} Ac;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_AC_COMPONENT_ */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/component/adc.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/component/adc.h
new file mode 100644
index 0000000000000000000000000000000000000000..e7e488a488a7fb73376b6a0c2284d016a2c6feb4
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/component/adc.h
@@ -0,0 +1,699 @@
+/**
+ * \file
+ *
+ * \brief Component description for ADC
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_ADC_COMPONENT_
+#define _SAMD21_ADC_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR ADC */
+/* ========================================================================== */
+/** \addtogroup SAMD21_ADC Analog Digital Converter */
+/*@{*/
+
+#define ADC_U2204
+#define REV_ADC 0x120
+
+/* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W 8) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t ENABLE:1; /*!< bit: 1 Enable */
+ uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} ADC_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_CTRLA_OFFSET 0x00 /**< \brief (ADC_CTRLA offset) Control A */
+#define ADC_CTRLA_RESETVALUE 0x00ul /**< \brief (ADC_CTRLA reset_value) Control A */
+
+#define ADC_CTRLA_SWRST_Pos 0 /**< \brief (ADC_CTRLA) Software Reset */
+#define ADC_CTRLA_SWRST (0x1ul << ADC_CTRLA_SWRST_Pos)
+#define ADC_CTRLA_ENABLE_Pos 1 /**< \brief (ADC_CTRLA) Enable */
+#define ADC_CTRLA_ENABLE (0x1ul << ADC_CTRLA_ENABLE_Pos)
+#define ADC_CTRLA_RUNSTDBY_Pos 2 /**< \brief (ADC_CTRLA) Run in Standby */
+#define ADC_CTRLA_RUNSTDBY (0x1ul << ADC_CTRLA_RUNSTDBY_Pos)
+#define ADC_CTRLA_MASK 0x07ul /**< \brief (ADC_CTRLA) MASK Register */
+
+/* -------- ADC_REFCTRL : (ADC Offset: 0x01) (R/W 8) Reference Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t REFSEL:4; /*!< bit: 0.. 3 Reference Selection */
+ uint8_t :3; /*!< bit: 4.. 6 Reserved */
+ uint8_t REFCOMP:1; /*!< bit: 7 Reference Buffer Offset Compensation Enable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} ADC_REFCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_REFCTRL_OFFSET 0x01 /**< \brief (ADC_REFCTRL offset) Reference Control */
+#define ADC_REFCTRL_RESETVALUE 0x00ul /**< \brief (ADC_REFCTRL reset_value) Reference Control */
+
+#define ADC_REFCTRL_REFSEL_Pos 0 /**< \brief (ADC_REFCTRL) Reference Selection */
+#define ADC_REFCTRL_REFSEL_Msk (0xFul << ADC_REFCTRL_REFSEL_Pos)
+#define ADC_REFCTRL_REFSEL(value) (ADC_REFCTRL_REFSEL_Msk & ((value) << ADC_REFCTRL_REFSEL_Pos))
+#define ADC_REFCTRL_REFSEL_INT1V_Val 0x0ul /**< \brief (ADC_REFCTRL) 1.0V voltage reference */
+#define ADC_REFCTRL_REFSEL_INTVCC0_Val 0x1ul /**< \brief (ADC_REFCTRL) 1/1.48 VDDANA */
+#define ADC_REFCTRL_REFSEL_INTVCC1_Val 0x2ul /**< \brief (ADC_REFCTRL) 1/2 VDDANA (only for VDDANA > 2.0V) */
+#define ADC_REFCTRL_REFSEL_AREFA_Val 0x3ul /**< \brief (ADC_REFCTRL) External reference */
+#define ADC_REFCTRL_REFSEL_AREFB_Val 0x4ul /**< \brief (ADC_REFCTRL) External reference */
+#define ADC_REFCTRL_REFSEL_INT1V (ADC_REFCTRL_REFSEL_INT1V_Val << ADC_REFCTRL_REFSEL_Pos)
+#define ADC_REFCTRL_REFSEL_INTVCC0 (ADC_REFCTRL_REFSEL_INTVCC0_Val << ADC_REFCTRL_REFSEL_Pos)
+#define ADC_REFCTRL_REFSEL_INTVCC1 (ADC_REFCTRL_REFSEL_INTVCC1_Val << ADC_REFCTRL_REFSEL_Pos)
+#define ADC_REFCTRL_REFSEL_AREFA (ADC_REFCTRL_REFSEL_AREFA_Val << ADC_REFCTRL_REFSEL_Pos)
+#define ADC_REFCTRL_REFSEL_AREFB (ADC_REFCTRL_REFSEL_AREFB_Val << ADC_REFCTRL_REFSEL_Pos)
+#define ADC_REFCTRL_REFCOMP_Pos 7 /**< \brief (ADC_REFCTRL) Reference Buffer Offset Compensation Enable */
+#define ADC_REFCTRL_REFCOMP (0x1ul << ADC_REFCTRL_REFCOMP_Pos)
+#define ADC_REFCTRL_MASK 0x8Ful /**< \brief (ADC_REFCTRL) MASK Register */
+
+/* -------- ADC_AVGCTRL : (ADC Offset: 0x02) (R/W 8) Average Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SAMPLENUM:4; /*!< bit: 0.. 3 Number of Samples to be Collected */
+ uint8_t ADJRES:3; /*!< bit: 4.. 6 Adjusting Result / Division Coefficient */
+ uint8_t :1; /*!< bit: 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} ADC_AVGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_AVGCTRL_OFFSET 0x02 /**< \brief (ADC_AVGCTRL offset) Average Control */
+#define ADC_AVGCTRL_RESETVALUE 0x00ul /**< \brief (ADC_AVGCTRL reset_value) Average Control */
+
+#define ADC_AVGCTRL_SAMPLENUM_Pos 0 /**< \brief (ADC_AVGCTRL) Number of Samples to be Collected */
+#define ADC_AVGCTRL_SAMPLENUM_Msk (0xFul << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM(value) (ADC_AVGCTRL_SAMPLENUM_Msk & ((value) << ADC_AVGCTRL_SAMPLENUM_Pos))
+#define ADC_AVGCTRL_SAMPLENUM_1_Val 0x0ul /**< \brief (ADC_AVGCTRL) 1 sample */
+#define ADC_AVGCTRL_SAMPLENUM_2_Val 0x1ul /**< \brief (ADC_AVGCTRL) 2 samples */
+#define ADC_AVGCTRL_SAMPLENUM_4_Val 0x2ul /**< \brief (ADC_AVGCTRL) 4 samples */
+#define ADC_AVGCTRL_SAMPLENUM_8_Val 0x3ul /**< \brief (ADC_AVGCTRL) 8 samples */
+#define ADC_AVGCTRL_SAMPLENUM_16_Val 0x4ul /**< \brief (ADC_AVGCTRL) 16 samples */
+#define ADC_AVGCTRL_SAMPLENUM_32_Val 0x5ul /**< \brief (ADC_AVGCTRL) 32 samples */
+#define ADC_AVGCTRL_SAMPLENUM_64_Val 0x6ul /**< \brief (ADC_AVGCTRL) 64 samples */
+#define ADC_AVGCTRL_SAMPLENUM_128_Val 0x7ul /**< \brief (ADC_AVGCTRL) 128 samples */
+#define ADC_AVGCTRL_SAMPLENUM_256_Val 0x8ul /**< \brief (ADC_AVGCTRL) 256 samples */
+#define ADC_AVGCTRL_SAMPLENUM_512_Val 0x9ul /**< \brief (ADC_AVGCTRL) 512 samples */
+#define ADC_AVGCTRL_SAMPLENUM_1024_Val 0xAul /**< \brief (ADC_AVGCTRL) 1024 samples */
+#define ADC_AVGCTRL_SAMPLENUM_1 (ADC_AVGCTRL_SAMPLENUM_1_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_2 (ADC_AVGCTRL_SAMPLENUM_2_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_4 (ADC_AVGCTRL_SAMPLENUM_4_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_8 (ADC_AVGCTRL_SAMPLENUM_8_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_16 (ADC_AVGCTRL_SAMPLENUM_16_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_32 (ADC_AVGCTRL_SAMPLENUM_32_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_64 (ADC_AVGCTRL_SAMPLENUM_64_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_128 (ADC_AVGCTRL_SAMPLENUM_128_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_256 (ADC_AVGCTRL_SAMPLENUM_256_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_512 (ADC_AVGCTRL_SAMPLENUM_512_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_SAMPLENUM_1024 (ADC_AVGCTRL_SAMPLENUM_1024_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
+#define ADC_AVGCTRL_ADJRES_Pos 4 /**< \brief (ADC_AVGCTRL) Adjusting Result / Division Coefficient */
+#define ADC_AVGCTRL_ADJRES_Msk (0x7ul << ADC_AVGCTRL_ADJRES_Pos)
+#define ADC_AVGCTRL_ADJRES(value) (ADC_AVGCTRL_ADJRES_Msk & ((value) << ADC_AVGCTRL_ADJRES_Pos))
+#define ADC_AVGCTRL_MASK 0x7Ful /**< \brief (ADC_AVGCTRL) MASK Register */
+
+/* -------- ADC_SAMPCTRL : (ADC Offset: 0x03) (R/W 8) Sampling Time Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SAMPLEN:6; /*!< bit: 0.. 5 Sampling Time Length */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} ADC_SAMPCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_SAMPCTRL_OFFSET 0x03 /**< \brief (ADC_SAMPCTRL offset) Sampling Time Control */
+#define ADC_SAMPCTRL_RESETVALUE 0x00ul /**< \brief (ADC_SAMPCTRL reset_value) Sampling Time Control */
+
+#define ADC_SAMPCTRL_SAMPLEN_Pos 0 /**< \brief (ADC_SAMPCTRL) Sampling Time Length */
+#define ADC_SAMPCTRL_SAMPLEN_Msk (0x3Ful << ADC_SAMPCTRL_SAMPLEN_Pos)
+#define ADC_SAMPCTRL_SAMPLEN(value) (ADC_SAMPCTRL_SAMPLEN_Msk & ((value) << ADC_SAMPCTRL_SAMPLEN_Pos))
+#define ADC_SAMPCTRL_MASK 0x3Ful /**< \brief (ADC_SAMPCTRL) MASK Register */
+
+/* -------- ADC_CTRLB : (ADC Offset: 0x04) (R/W 16) Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t DIFFMODE:1; /*!< bit: 0 Differential Mode */
+ uint16_t LEFTADJ:1; /*!< bit: 1 Left-Adjusted Result */
+ uint16_t FREERUN:1; /*!< bit: 2 Free Running Mode */
+ uint16_t CORREN:1; /*!< bit: 3 Digital Correction Logic Enabled */
+ uint16_t RESSEL:2; /*!< bit: 4.. 5 Conversion Result Resolution */
+ uint16_t :2; /*!< bit: 6.. 7 Reserved */
+ uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler Configuration */
+ uint16_t :5; /*!< bit: 11..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} ADC_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_CTRLB_OFFSET 0x04 /**< \brief (ADC_CTRLB offset) Control B */
+#define ADC_CTRLB_RESETVALUE 0x0000ul /**< \brief (ADC_CTRLB reset_value) Control B */
+
+#define ADC_CTRLB_DIFFMODE_Pos 0 /**< \brief (ADC_CTRLB) Differential Mode */
+#define ADC_CTRLB_DIFFMODE (0x1ul << ADC_CTRLB_DIFFMODE_Pos)
+#define ADC_CTRLB_LEFTADJ_Pos 1 /**< \brief (ADC_CTRLB) Left-Adjusted Result */
+#define ADC_CTRLB_LEFTADJ (0x1ul << ADC_CTRLB_LEFTADJ_Pos)
+#define ADC_CTRLB_FREERUN_Pos 2 /**< \brief (ADC_CTRLB) Free Running Mode */
+#define ADC_CTRLB_FREERUN (0x1ul << ADC_CTRLB_FREERUN_Pos)
+#define ADC_CTRLB_CORREN_Pos 3 /**< \brief (ADC_CTRLB) Digital Correction Logic Enabled */
+#define ADC_CTRLB_CORREN (0x1ul << ADC_CTRLB_CORREN_Pos)
+#define ADC_CTRLB_RESSEL_Pos 4 /**< \brief (ADC_CTRLB) Conversion Result Resolution */
+#define ADC_CTRLB_RESSEL_Msk (0x3ul << ADC_CTRLB_RESSEL_Pos)
+#define ADC_CTRLB_RESSEL(value) (ADC_CTRLB_RESSEL_Msk & ((value) << ADC_CTRLB_RESSEL_Pos))
+#define ADC_CTRLB_RESSEL_12BIT_Val 0x0ul /**< \brief (ADC_CTRLB) 12-bit result */
+#define ADC_CTRLB_RESSEL_16BIT_Val 0x1ul /**< \brief (ADC_CTRLB) For averaging mode output */
+#define ADC_CTRLB_RESSEL_10BIT_Val 0x2ul /**< \brief (ADC_CTRLB) 10-bit result */
+#define ADC_CTRLB_RESSEL_8BIT_Val 0x3ul /**< \brief (ADC_CTRLB) 8-bit result */
+#define ADC_CTRLB_RESSEL_12BIT (ADC_CTRLB_RESSEL_12BIT_Val << ADC_CTRLB_RESSEL_Pos)
+#define ADC_CTRLB_RESSEL_16BIT (ADC_CTRLB_RESSEL_16BIT_Val << ADC_CTRLB_RESSEL_Pos)
+#define ADC_CTRLB_RESSEL_10BIT (ADC_CTRLB_RESSEL_10BIT_Val << ADC_CTRLB_RESSEL_Pos)
+#define ADC_CTRLB_RESSEL_8BIT (ADC_CTRLB_RESSEL_8BIT_Val << ADC_CTRLB_RESSEL_Pos)
+#define ADC_CTRLB_PRESCALER_Pos 8 /**< \brief (ADC_CTRLB) Prescaler Configuration */
+#define ADC_CTRLB_PRESCALER_Msk (0x7ul << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_PRESCALER(value) (ADC_CTRLB_PRESCALER_Msk & ((value) << ADC_CTRLB_PRESCALER_Pos))
+#define ADC_CTRLB_PRESCALER_DIV4_Val 0x0ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 4 */
+#define ADC_CTRLB_PRESCALER_DIV8_Val 0x1ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 8 */
+#define ADC_CTRLB_PRESCALER_DIV16_Val 0x2ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 16 */
+#define ADC_CTRLB_PRESCALER_DIV32_Val 0x3ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 32 */
+#define ADC_CTRLB_PRESCALER_DIV64_Val 0x4ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 64 */
+#define ADC_CTRLB_PRESCALER_DIV128_Val 0x5ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 128 */
+#define ADC_CTRLB_PRESCALER_DIV256_Val 0x6ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 256 */
+#define ADC_CTRLB_PRESCALER_DIV512_Val 0x7ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 512 */
+#define ADC_CTRLB_PRESCALER_DIV4 (ADC_CTRLB_PRESCALER_DIV4_Val << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_PRESCALER_DIV8 (ADC_CTRLB_PRESCALER_DIV8_Val << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_PRESCALER_DIV16 (ADC_CTRLB_PRESCALER_DIV16_Val << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_PRESCALER_DIV32 (ADC_CTRLB_PRESCALER_DIV32_Val << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_PRESCALER_DIV64 (ADC_CTRLB_PRESCALER_DIV64_Val << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_PRESCALER_DIV128 (ADC_CTRLB_PRESCALER_DIV128_Val << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_PRESCALER_DIV256 (ADC_CTRLB_PRESCALER_DIV256_Val << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_PRESCALER_DIV512 (ADC_CTRLB_PRESCALER_DIV512_Val << ADC_CTRLB_PRESCALER_Pos)
+#define ADC_CTRLB_MASK 0x073Ful /**< \brief (ADC_CTRLB) MASK Register */
+
+/* -------- ADC_WINCTRL : (ADC Offset: 0x08) (R/W 8) Window Monitor Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t WINMODE:3; /*!< bit: 0.. 2 Window Monitor Mode */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} ADC_WINCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_WINCTRL_OFFSET 0x08 /**< \brief (ADC_WINCTRL offset) Window Monitor Control */
+#define ADC_WINCTRL_RESETVALUE 0x00ul /**< \brief (ADC_WINCTRL reset_value) Window Monitor Control */
+
+#define ADC_WINCTRL_WINMODE_Pos 0 /**< \brief (ADC_WINCTRL) Window Monitor Mode */
+#define ADC_WINCTRL_WINMODE_Msk (0x7ul << ADC_WINCTRL_WINMODE_Pos)
+#define ADC_WINCTRL_WINMODE(value) (ADC_WINCTRL_WINMODE_Msk & ((value) << ADC_WINCTRL_WINMODE_Pos))
+#define ADC_WINCTRL_WINMODE_DISABLE_Val 0x0ul /**< \brief (ADC_WINCTRL) No window mode (default) */
+#define ADC_WINCTRL_WINMODE_MODE1_Val 0x1ul /**< \brief (ADC_WINCTRL) Mode 1: RESULT > WINLT */
+#define ADC_WINCTRL_WINMODE_MODE2_Val 0x2ul /**< \brief (ADC_WINCTRL) Mode 2: RESULT < WINUT */
+#define ADC_WINCTRL_WINMODE_MODE3_Val 0x3ul /**< \brief (ADC_WINCTRL) Mode 3: WINLT < RESULT < WINUT */
+#define ADC_WINCTRL_WINMODE_MODE4_Val 0x4ul /**< \brief (ADC_WINCTRL) Mode 4: !(WINLT < RESULT < WINUT) */
+#define ADC_WINCTRL_WINMODE_DISABLE (ADC_WINCTRL_WINMODE_DISABLE_Val << ADC_WINCTRL_WINMODE_Pos)
+#define ADC_WINCTRL_WINMODE_MODE1 (ADC_WINCTRL_WINMODE_MODE1_Val << ADC_WINCTRL_WINMODE_Pos)
+#define ADC_WINCTRL_WINMODE_MODE2 (ADC_WINCTRL_WINMODE_MODE2_Val << ADC_WINCTRL_WINMODE_Pos)
+#define ADC_WINCTRL_WINMODE_MODE3 (ADC_WINCTRL_WINMODE_MODE3_Val << ADC_WINCTRL_WINMODE_Pos)
+#define ADC_WINCTRL_WINMODE_MODE4 (ADC_WINCTRL_WINMODE_MODE4_Val << ADC_WINCTRL_WINMODE_Pos)
+#define ADC_WINCTRL_MASK 0x07ul /**< \brief (ADC_WINCTRL) MASK Register */
+
+/* -------- ADC_SWTRIG : (ADC Offset: 0x0C) (R/W 8) Software Trigger -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t FLUSH:1; /*!< bit: 0 ADC Conversion Flush */
+ uint8_t START:1; /*!< bit: 1 ADC Start Conversion */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} ADC_SWTRIG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_SWTRIG_OFFSET 0x0C /**< \brief (ADC_SWTRIG offset) Software Trigger */
+#define ADC_SWTRIG_RESETVALUE 0x00ul /**< \brief (ADC_SWTRIG reset_value) Software Trigger */
+
+#define ADC_SWTRIG_FLUSH_Pos 0 /**< \brief (ADC_SWTRIG) ADC Conversion Flush */
+#define ADC_SWTRIG_FLUSH (0x1ul << ADC_SWTRIG_FLUSH_Pos)
+#define ADC_SWTRIG_START_Pos 1 /**< \brief (ADC_SWTRIG) ADC Start Conversion */
+#define ADC_SWTRIG_START (0x1ul << ADC_SWTRIG_START_Pos)
+#define ADC_SWTRIG_MASK 0x03ul /**< \brief (ADC_SWTRIG) MASK Register */
+
+/* -------- ADC_INPUTCTRL : (ADC Offset: 0x10) (R/W 32) Input Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t MUXPOS:5; /*!< bit: 0.. 4 Positive Mux Input Selection */
+ uint32_t :3; /*!< bit: 5.. 7 Reserved */
+ uint32_t MUXNEG:5; /*!< bit: 8..12 Negative Mux Input Selection */
+ uint32_t :3; /*!< bit: 13..15 Reserved */
+ uint32_t INPUTSCAN:4; /*!< bit: 16..19 Number of Input Channels Included in Scan */
+ uint32_t INPUTOFFSET:4; /*!< bit: 20..23 Positive Mux Setting Offset */
+ uint32_t GAIN:4; /*!< bit: 24..27 Gain Factor Selection */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} ADC_INPUTCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_INPUTCTRL_OFFSET 0x10 /**< \brief (ADC_INPUTCTRL offset) Input Control */
+#define ADC_INPUTCTRL_RESETVALUE 0x00000000ul /**< \brief (ADC_INPUTCTRL reset_value) Input Control */
+
+#define ADC_INPUTCTRL_MUXPOS_Pos 0 /**< \brief (ADC_INPUTCTRL) Positive Mux Input Selection */
+#define ADC_INPUTCTRL_MUXPOS_Msk (0x1Ful << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS(value) (ADC_INPUTCTRL_MUXPOS_Msk & ((value) << ADC_INPUTCTRL_MUXPOS_Pos))
+#define ADC_INPUTCTRL_MUXPOS_PIN0_Val 0x0ul /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */
+#define ADC_INPUTCTRL_MUXPOS_PIN1_Val 0x1ul /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */
+#define ADC_INPUTCTRL_MUXPOS_PIN2_Val 0x2ul /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */
+#define ADC_INPUTCTRL_MUXPOS_PIN3_Val 0x3ul /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */
+#define ADC_INPUTCTRL_MUXPOS_PIN4_Val 0x4ul /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */
+#define ADC_INPUTCTRL_MUXPOS_PIN5_Val 0x5ul /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */
+#define ADC_INPUTCTRL_MUXPOS_PIN6_Val 0x6ul /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */
+#define ADC_INPUTCTRL_MUXPOS_PIN7_Val 0x7ul /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */
+#define ADC_INPUTCTRL_MUXPOS_PIN8_Val 0x8ul /**< \brief (ADC_INPUTCTRL) ADC AIN8 Pin */
+#define ADC_INPUTCTRL_MUXPOS_PIN9_Val 0x9ul /**< \brief (ADC_INPUTCTRL) ADC AIN9 Pin */
+#define ADC_INPUTCTRL_MUXPOS_PIN10_Val 0xAul /**< \brief (ADC_INPUTCTRL) ADC AIN10 Pin */
+#define ADC_INPUTCTRL_MUXPOS_PIN11_Val 0xBul /**< \brief (ADC_INPUTCTRL) ADC AIN11 Pin */
+#define ADC_INPUTCTRL_MUXPOS_PIN12_Val 0xCul /**< \brief (ADC_INPUTCTRL) ADC AIN12 Pin */
+#define ADC_INPUTCTRL_MUXPOS_PIN13_Val 0xDul /**< \brief (ADC_INPUTCTRL) ADC AIN13 Pin */
+#define ADC_INPUTCTRL_MUXPOS_PIN14_Val 0xEul /**< \brief (ADC_INPUTCTRL) ADC AIN14 Pin */
+#define ADC_INPUTCTRL_MUXPOS_PIN15_Val 0xFul /**< \brief (ADC_INPUTCTRL) ADC AIN15 Pin */
+#define ADC_INPUTCTRL_MUXPOS_PIN16_Val 0x10ul /**< \brief (ADC_INPUTCTRL) ADC AIN16 Pin */
+#define ADC_INPUTCTRL_MUXPOS_PIN17_Val 0x11ul /**< \brief (ADC_INPUTCTRL) ADC AIN17 Pin */
+#define ADC_INPUTCTRL_MUXPOS_PIN18_Val 0x12ul /**< \brief (ADC_INPUTCTRL) ADC AIN18 Pin */
+#define ADC_INPUTCTRL_MUXPOS_PIN19_Val 0x13ul /**< \brief (ADC_INPUTCTRL) ADC AIN19 Pin */
+#define ADC_INPUTCTRL_MUXPOS_TEMP_Val 0x18ul /**< \brief (ADC_INPUTCTRL) Temperature Reference */
+#define ADC_INPUTCTRL_MUXPOS_BANDGAP_Val 0x19ul /**< \brief (ADC_INPUTCTRL) Bandgap Voltage */
+#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val 0x1Aul /**< \brief (ADC_INPUTCTRL) 1/4 Scaled Core Supply */
+#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val 0x1Bul /**< \brief (ADC_INPUTCTRL) 1/4 Scaled I/O Supply */
+#define ADC_INPUTCTRL_MUXPOS_DAC_Val 0x1Cul /**< \brief (ADC_INPUTCTRL) DAC Output */
+#define ADC_INPUTCTRL_MUXPOS_PIN0 (ADC_INPUTCTRL_MUXPOS_PIN0_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN1 (ADC_INPUTCTRL_MUXPOS_PIN1_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN2 (ADC_INPUTCTRL_MUXPOS_PIN2_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN3 (ADC_INPUTCTRL_MUXPOS_PIN3_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN4 (ADC_INPUTCTRL_MUXPOS_PIN4_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN5 (ADC_INPUTCTRL_MUXPOS_PIN5_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN6 (ADC_INPUTCTRL_MUXPOS_PIN6_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN7 (ADC_INPUTCTRL_MUXPOS_PIN7_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN8 (ADC_INPUTCTRL_MUXPOS_PIN8_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN9 (ADC_INPUTCTRL_MUXPOS_PIN9_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN10 (ADC_INPUTCTRL_MUXPOS_PIN10_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN11 (ADC_INPUTCTRL_MUXPOS_PIN11_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN12 (ADC_INPUTCTRL_MUXPOS_PIN12_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN13 (ADC_INPUTCTRL_MUXPOS_PIN13_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN14 (ADC_INPUTCTRL_MUXPOS_PIN14_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN15 (ADC_INPUTCTRL_MUXPOS_PIN15_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN16 (ADC_INPUTCTRL_MUXPOS_PIN16_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN17 (ADC_INPUTCTRL_MUXPOS_PIN17_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN18 (ADC_INPUTCTRL_MUXPOS_PIN18_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_PIN19 (ADC_INPUTCTRL_MUXPOS_PIN19_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_TEMP (ADC_INPUTCTRL_MUXPOS_TEMP_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_BANDGAP (ADC_INPUTCTRL_MUXPOS_BANDGAP_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC (ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC (ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXPOS_DAC (ADC_INPUTCTRL_MUXPOS_DAC_Val << ADC_INPUTCTRL_MUXPOS_Pos)
+#define ADC_INPUTCTRL_MUXNEG_Pos 8 /**< \brief (ADC_INPUTCTRL) Negative Mux Input Selection */
+#define ADC_INPUTCTRL_MUXNEG_Msk (0x1Ful << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG(value) (ADC_INPUTCTRL_MUXNEG_Msk & ((value) << ADC_INPUTCTRL_MUXNEG_Pos))
+#define ADC_INPUTCTRL_MUXNEG_PIN0_Val 0x0ul /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */
+#define ADC_INPUTCTRL_MUXNEG_PIN1_Val 0x1ul /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */
+#define ADC_INPUTCTRL_MUXNEG_PIN2_Val 0x2ul /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */
+#define ADC_INPUTCTRL_MUXNEG_PIN3_Val 0x3ul /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */
+#define ADC_INPUTCTRL_MUXNEG_PIN4_Val 0x4ul /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */
+#define ADC_INPUTCTRL_MUXNEG_PIN5_Val 0x5ul /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */
+#define ADC_INPUTCTRL_MUXNEG_PIN6_Val 0x6ul /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */
+#define ADC_INPUTCTRL_MUXNEG_PIN7_Val 0x7ul /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */
+#define ADC_INPUTCTRL_MUXNEG_GND_Val 0x18ul /**< \brief (ADC_INPUTCTRL) Internal Ground */
+#define ADC_INPUTCTRL_MUXNEG_IOGND_Val 0x19ul /**< \brief (ADC_INPUTCTRL) I/O Ground */
+#define ADC_INPUTCTRL_MUXNEG_PIN0 (ADC_INPUTCTRL_MUXNEG_PIN0_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_PIN1 (ADC_INPUTCTRL_MUXNEG_PIN1_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_PIN2 (ADC_INPUTCTRL_MUXNEG_PIN2_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_PIN3 (ADC_INPUTCTRL_MUXNEG_PIN3_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_PIN4 (ADC_INPUTCTRL_MUXNEG_PIN4_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_PIN5 (ADC_INPUTCTRL_MUXNEG_PIN5_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_PIN6 (ADC_INPUTCTRL_MUXNEG_PIN6_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_PIN7 (ADC_INPUTCTRL_MUXNEG_PIN7_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_GND (ADC_INPUTCTRL_MUXNEG_GND_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_MUXNEG_IOGND (ADC_INPUTCTRL_MUXNEG_IOGND_Val << ADC_INPUTCTRL_MUXNEG_Pos)
+#define ADC_INPUTCTRL_INPUTSCAN_Pos 16 /**< \brief (ADC_INPUTCTRL) Number of Input Channels Included in Scan */
+#define ADC_INPUTCTRL_INPUTSCAN_Msk (0xFul << ADC_INPUTCTRL_INPUTSCAN_Pos)
+#define ADC_INPUTCTRL_INPUTSCAN(value) (ADC_INPUTCTRL_INPUTSCAN_Msk & ((value) << ADC_INPUTCTRL_INPUTSCAN_Pos))
+#define ADC_INPUTCTRL_INPUTOFFSET_Pos 20 /**< \brief (ADC_INPUTCTRL) Positive Mux Setting Offset */
+#define ADC_INPUTCTRL_INPUTOFFSET_Msk (0xFul << ADC_INPUTCTRL_INPUTOFFSET_Pos)
+#define ADC_INPUTCTRL_INPUTOFFSET(value) (ADC_INPUTCTRL_INPUTOFFSET_Msk & ((value) << ADC_INPUTCTRL_INPUTOFFSET_Pos))
+#define ADC_INPUTCTRL_GAIN_Pos 24 /**< \brief (ADC_INPUTCTRL) Gain Factor Selection */
+#define ADC_INPUTCTRL_GAIN_Msk (0xFul << ADC_INPUTCTRL_GAIN_Pos)
+#define ADC_INPUTCTRL_GAIN(value) (ADC_INPUTCTRL_GAIN_Msk & ((value) << ADC_INPUTCTRL_GAIN_Pos))
+#define ADC_INPUTCTRL_GAIN_1X_Val 0x0ul /**< \brief (ADC_INPUTCTRL) 1x */
+#define ADC_INPUTCTRL_GAIN_2X_Val 0x1ul /**< \brief (ADC_INPUTCTRL) 2x */
+#define ADC_INPUTCTRL_GAIN_4X_Val 0x2ul /**< \brief (ADC_INPUTCTRL) 4x */
+#define ADC_INPUTCTRL_GAIN_8X_Val 0x3ul /**< \brief (ADC_INPUTCTRL) 8x */
+#define ADC_INPUTCTRL_GAIN_16X_Val 0x4ul /**< \brief (ADC_INPUTCTRL) 16x */
+#define ADC_INPUTCTRL_GAIN_DIV2_Val 0xFul /**< \brief (ADC_INPUTCTRL) 1/2x */
+#define ADC_INPUTCTRL_GAIN_1X (ADC_INPUTCTRL_GAIN_1X_Val << ADC_INPUTCTRL_GAIN_Pos)
+#define ADC_INPUTCTRL_GAIN_2X (ADC_INPUTCTRL_GAIN_2X_Val << ADC_INPUTCTRL_GAIN_Pos)
+#define ADC_INPUTCTRL_GAIN_4X (ADC_INPUTCTRL_GAIN_4X_Val << ADC_INPUTCTRL_GAIN_Pos)
+#define ADC_INPUTCTRL_GAIN_8X (ADC_INPUTCTRL_GAIN_8X_Val << ADC_INPUTCTRL_GAIN_Pos)
+#define ADC_INPUTCTRL_GAIN_16X (ADC_INPUTCTRL_GAIN_16X_Val << ADC_INPUTCTRL_GAIN_Pos)
+#define ADC_INPUTCTRL_GAIN_DIV2 (ADC_INPUTCTRL_GAIN_DIV2_Val << ADC_INPUTCTRL_GAIN_Pos)
+#define ADC_INPUTCTRL_MASK 0x0FFF1F1Ful /**< \brief (ADC_INPUTCTRL) MASK Register */
+
+/* -------- ADC_EVCTRL : (ADC Offset: 0x14) (R/W 8) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event In */
+ uint8_t SYNCEI:1; /*!< bit: 1 Synchronization Event In */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t RESRDYEO:1; /*!< bit: 4 Result Ready Event Out */
+ uint8_t WINMONEO:1; /*!< bit: 5 Window Monitor Event Out */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} ADC_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_EVCTRL_OFFSET 0x14 /**< \brief (ADC_EVCTRL offset) Event Control */
+#define ADC_EVCTRL_RESETVALUE 0x00ul /**< \brief (ADC_EVCTRL reset_value) Event Control */
+
+#define ADC_EVCTRL_STARTEI_Pos 0 /**< \brief (ADC_EVCTRL) Start Conversion Event In */
+#define ADC_EVCTRL_STARTEI (0x1ul << ADC_EVCTRL_STARTEI_Pos)
+#define ADC_EVCTRL_SYNCEI_Pos 1 /**< \brief (ADC_EVCTRL) Synchronization Event In */
+#define ADC_EVCTRL_SYNCEI (0x1ul << ADC_EVCTRL_SYNCEI_Pos)
+#define ADC_EVCTRL_RESRDYEO_Pos 4 /**< \brief (ADC_EVCTRL) Result Ready Event Out */
+#define ADC_EVCTRL_RESRDYEO (0x1ul << ADC_EVCTRL_RESRDYEO_Pos)
+#define ADC_EVCTRL_WINMONEO_Pos 5 /**< \brief (ADC_EVCTRL) Window Monitor Event Out */
+#define ADC_EVCTRL_WINMONEO (0x1ul << ADC_EVCTRL_WINMONEO_Pos)
+#define ADC_EVCTRL_MASK 0x33ul /**< \brief (ADC_EVCTRL) MASK Register */
+
+/* -------- ADC_INTENCLR : (ADC Offset: 0x16) (R/W 8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */
+ uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */
+ uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */
+ uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} ADC_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_INTENCLR_OFFSET 0x16 /**< \brief (ADC_INTENCLR offset) Interrupt Enable Clear */
+#define ADC_INTENCLR_RESETVALUE 0x00ul /**< \brief (ADC_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define ADC_INTENCLR_RESRDY_Pos 0 /**< \brief (ADC_INTENCLR) Result Ready Interrupt Enable */
+#define ADC_INTENCLR_RESRDY (0x1ul << ADC_INTENCLR_RESRDY_Pos)
+#define ADC_INTENCLR_OVERRUN_Pos 1 /**< \brief (ADC_INTENCLR) Overrun Interrupt Enable */
+#define ADC_INTENCLR_OVERRUN (0x1ul << ADC_INTENCLR_OVERRUN_Pos)
+#define ADC_INTENCLR_WINMON_Pos 2 /**< \brief (ADC_INTENCLR) Window Monitor Interrupt Enable */
+#define ADC_INTENCLR_WINMON (0x1ul << ADC_INTENCLR_WINMON_Pos)
+#define ADC_INTENCLR_SYNCRDY_Pos 3 /**< \brief (ADC_INTENCLR) Synchronization Ready Interrupt Enable */
+#define ADC_INTENCLR_SYNCRDY (0x1ul << ADC_INTENCLR_SYNCRDY_Pos)
+#define ADC_INTENCLR_MASK 0x0Ful /**< \brief (ADC_INTENCLR) MASK Register */
+
+/* -------- ADC_INTENSET : (ADC Offset: 0x17) (R/W 8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */
+ uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */
+ uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */
+ uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} ADC_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_INTENSET_OFFSET 0x17 /**< \brief (ADC_INTENSET offset) Interrupt Enable Set */
+#define ADC_INTENSET_RESETVALUE 0x00ul /**< \brief (ADC_INTENSET reset_value) Interrupt Enable Set */
+
+#define ADC_INTENSET_RESRDY_Pos 0 /**< \brief (ADC_INTENSET) Result Ready Interrupt Enable */
+#define ADC_INTENSET_RESRDY (0x1ul << ADC_INTENSET_RESRDY_Pos)
+#define ADC_INTENSET_OVERRUN_Pos 1 /**< \brief (ADC_INTENSET) Overrun Interrupt Enable */
+#define ADC_INTENSET_OVERRUN (0x1ul << ADC_INTENSET_OVERRUN_Pos)
+#define ADC_INTENSET_WINMON_Pos 2 /**< \brief (ADC_INTENSET) Window Monitor Interrupt Enable */
+#define ADC_INTENSET_WINMON (0x1ul << ADC_INTENSET_WINMON_Pos)
+#define ADC_INTENSET_SYNCRDY_Pos 3 /**< \brief (ADC_INTENSET) Synchronization Ready Interrupt Enable */
+#define ADC_INTENSET_SYNCRDY (0x1ul << ADC_INTENSET_SYNCRDY_Pos)
+#define ADC_INTENSET_MASK 0x0Ful /**< \brief (ADC_INTENSET) MASK Register */
+
+/* -------- ADC_INTFLAG : (ADC Offset: 0x18) (R/W 8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint8_t RESRDY:1; /*!< bit: 0 Result Ready */
+ __I uint8_t OVERRUN:1; /*!< bit: 1 Overrun */
+ __I uint8_t WINMON:1; /*!< bit: 2 Window Monitor */
+ __I uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */
+ __I uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} ADC_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_INTFLAG_OFFSET 0x18 /**< \brief (ADC_INTFLAG offset) Interrupt Flag Status and Clear */
+#define ADC_INTFLAG_RESETVALUE 0x00ul /**< \brief (ADC_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define ADC_INTFLAG_RESRDY_Pos 0 /**< \brief (ADC_INTFLAG) Result Ready */
+#define ADC_INTFLAG_RESRDY (0x1ul << ADC_INTFLAG_RESRDY_Pos)
+#define ADC_INTFLAG_OVERRUN_Pos 1 /**< \brief (ADC_INTFLAG) Overrun */
+#define ADC_INTFLAG_OVERRUN (0x1ul << ADC_INTFLAG_OVERRUN_Pos)
+#define ADC_INTFLAG_WINMON_Pos 2 /**< \brief (ADC_INTFLAG) Window Monitor */
+#define ADC_INTFLAG_WINMON (0x1ul << ADC_INTFLAG_WINMON_Pos)
+#define ADC_INTFLAG_SYNCRDY_Pos 3 /**< \brief (ADC_INTFLAG) Synchronization Ready */
+#define ADC_INTFLAG_SYNCRDY (0x1ul << ADC_INTFLAG_SYNCRDY_Pos)
+#define ADC_INTFLAG_MASK 0x0Ful /**< \brief (ADC_INTFLAG) MASK Register */
+
+/* -------- ADC_STATUS : (ADC Offset: 0x19) (R/ 8) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t :7; /*!< bit: 0.. 6 Reserved */
+ uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} ADC_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_STATUS_OFFSET 0x19 /**< \brief (ADC_STATUS offset) Status */
+#define ADC_STATUS_RESETVALUE 0x00ul /**< \brief (ADC_STATUS reset_value) Status */
+
+#define ADC_STATUS_SYNCBUSY_Pos 7 /**< \brief (ADC_STATUS) Synchronization Busy */
+#define ADC_STATUS_SYNCBUSY (0x1ul << ADC_STATUS_SYNCBUSY_Pos)
+#define ADC_STATUS_MASK 0x80ul /**< \brief (ADC_STATUS) MASK Register */
+
+/* -------- ADC_RESULT : (ADC Offset: 0x1A) (R/ 16) Result -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t RESULT:16; /*!< bit: 0..15 Result Conversion Value */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} ADC_RESULT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_RESULT_OFFSET 0x1A /**< \brief (ADC_RESULT offset) Result */
+#define ADC_RESULT_RESETVALUE 0x0000ul /**< \brief (ADC_RESULT reset_value) Result */
+
+#define ADC_RESULT_RESULT_Pos 0 /**< \brief (ADC_RESULT) Result Conversion Value */
+#define ADC_RESULT_RESULT_Msk (0xFFFFul << ADC_RESULT_RESULT_Pos)
+#define ADC_RESULT_RESULT(value) (ADC_RESULT_RESULT_Msk & ((value) << ADC_RESULT_RESULT_Pos))
+#define ADC_RESULT_MASK 0xFFFFul /**< \brief (ADC_RESULT) MASK Register */
+
+/* -------- ADC_WINLT : (ADC Offset: 0x1C) (R/W 16) Window Monitor Lower Threshold -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t WINLT:16; /*!< bit: 0..15 Window Lower Threshold */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} ADC_WINLT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_WINLT_OFFSET 0x1C /**< \brief (ADC_WINLT offset) Window Monitor Lower Threshold */
+#define ADC_WINLT_RESETVALUE 0x0000ul /**< \brief (ADC_WINLT reset_value) Window Monitor Lower Threshold */
+
+#define ADC_WINLT_WINLT_Pos 0 /**< \brief (ADC_WINLT) Window Lower Threshold */
+#define ADC_WINLT_WINLT_Msk (0xFFFFul << ADC_WINLT_WINLT_Pos)
+#define ADC_WINLT_WINLT(value) (ADC_WINLT_WINLT_Msk & ((value) << ADC_WINLT_WINLT_Pos))
+#define ADC_WINLT_MASK 0xFFFFul /**< \brief (ADC_WINLT) MASK Register */
+
+/* -------- ADC_WINUT : (ADC Offset: 0x20) (R/W 16) Window Monitor Upper Threshold -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t WINUT:16; /*!< bit: 0..15 Window Upper Threshold */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} ADC_WINUT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_WINUT_OFFSET 0x20 /**< \brief (ADC_WINUT offset) Window Monitor Upper Threshold */
+#define ADC_WINUT_RESETVALUE 0x0000ul /**< \brief (ADC_WINUT reset_value) Window Monitor Upper Threshold */
+
+#define ADC_WINUT_WINUT_Pos 0 /**< \brief (ADC_WINUT) Window Upper Threshold */
+#define ADC_WINUT_WINUT_Msk (0xFFFFul << ADC_WINUT_WINUT_Pos)
+#define ADC_WINUT_WINUT(value) (ADC_WINUT_WINUT_Msk & ((value) << ADC_WINUT_WINUT_Pos))
+#define ADC_WINUT_MASK 0xFFFFul /**< \brief (ADC_WINUT) MASK Register */
+
+/* -------- ADC_GAINCORR : (ADC Offset: 0x24) (R/W 16) Gain Correction -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t GAINCORR:12; /*!< bit: 0..11 Gain Correction Value */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} ADC_GAINCORR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_GAINCORR_OFFSET 0x24 /**< \brief (ADC_GAINCORR offset) Gain Correction */
+#define ADC_GAINCORR_RESETVALUE 0x0000ul /**< \brief (ADC_GAINCORR reset_value) Gain Correction */
+
+#define ADC_GAINCORR_GAINCORR_Pos 0 /**< \brief (ADC_GAINCORR) Gain Correction Value */
+#define ADC_GAINCORR_GAINCORR_Msk (0xFFFul << ADC_GAINCORR_GAINCORR_Pos)
+#define ADC_GAINCORR_GAINCORR(value) (ADC_GAINCORR_GAINCORR_Msk & ((value) << ADC_GAINCORR_GAINCORR_Pos))
+#define ADC_GAINCORR_MASK 0x0FFFul /**< \brief (ADC_GAINCORR) MASK Register */
+
+/* -------- ADC_OFFSETCORR : (ADC Offset: 0x26) (R/W 16) Offset Correction -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t OFFSETCORR:12; /*!< bit: 0..11 Offset Correction Value */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} ADC_OFFSETCORR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_OFFSETCORR_OFFSET 0x26 /**< \brief (ADC_OFFSETCORR offset) Offset Correction */
+#define ADC_OFFSETCORR_RESETVALUE 0x0000ul /**< \brief (ADC_OFFSETCORR reset_value) Offset Correction */
+
+#define ADC_OFFSETCORR_OFFSETCORR_Pos 0 /**< \brief (ADC_OFFSETCORR) Offset Correction Value */
+#define ADC_OFFSETCORR_OFFSETCORR_Msk (0xFFFul << ADC_OFFSETCORR_OFFSETCORR_Pos)
+#define ADC_OFFSETCORR_OFFSETCORR(value) (ADC_OFFSETCORR_OFFSETCORR_Msk & ((value) << ADC_OFFSETCORR_OFFSETCORR_Pos))
+#define ADC_OFFSETCORR_MASK 0x0FFFul /**< \brief (ADC_OFFSETCORR) MASK Register */
+
+/* -------- ADC_CALIB : (ADC Offset: 0x28) (R/W 16) Calibration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t LINEARITY_CAL:8; /*!< bit: 0.. 7 Linearity Calibration Value */
+ uint16_t BIAS_CAL:3; /*!< bit: 8..10 Bias Calibration Value */
+ uint16_t :5; /*!< bit: 11..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} ADC_CALIB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_CALIB_OFFSET 0x28 /**< \brief (ADC_CALIB offset) Calibration */
+#define ADC_CALIB_RESETVALUE 0x0000ul /**< \brief (ADC_CALIB reset_value) Calibration */
+
+#define ADC_CALIB_LINEARITY_CAL_Pos 0 /**< \brief (ADC_CALIB) Linearity Calibration Value */
+#define ADC_CALIB_LINEARITY_CAL_Msk (0xFFul << ADC_CALIB_LINEARITY_CAL_Pos)
+#define ADC_CALIB_LINEARITY_CAL(value) (ADC_CALIB_LINEARITY_CAL_Msk & ((value) << ADC_CALIB_LINEARITY_CAL_Pos))
+#define ADC_CALIB_BIAS_CAL_Pos 8 /**< \brief (ADC_CALIB) Bias Calibration Value */
+#define ADC_CALIB_BIAS_CAL_Msk (0x7ul << ADC_CALIB_BIAS_CAL_Pos)
+#define ADC_CALIB_BIAS_CAL(value) (ADC_CALIB_BIAS_CAL_Msk & ((value) << ADC_CALIB_BIAS_CAL_Pos))
+#define ADC_CALIB_MASK 0x07FFul /**< \brief (ADC_CALIB) MASK Register */
+
+/* -------- ADC_DBGCTRL : (ADC Offset: 0x2A) (R/W 8) Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} ADC_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define ADC_DBGCTRL_OFFSET 0x2A /**< \brief (ADC_DBGCTRL offset) Debug Control */
+#define ADC_DBGCTRL_RESETVALUE 0x00ul /**< \brief (ADC_DBGCTRL reset_value) Debug Control */
+
+#define ADC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (ADC_DBGCTRL) Debug Run */
+#define ADC_DBGCTRL_DBGRUN (0x1ul << ADC_DBGCTRL_DBGRUN_Pos)
+#define ADC_DBGCTRL_MASK 0x01ul /**< \brief (ADC_DBGCTRL) MASK Register */
+
+/** \brief ADC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO ADC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
+ __IO ADC_REFCTRL_Type REFCTRL; /**< \brief Offset: 0x01 (R/W 8) Reference Control */
+ __IO ADC_AVGCTRL_Type AVGCTRL; /**< \brief Offset: 0x02 (R/W 8) Average Control */
+ __IO ADC_SAMPCTRL_Type SAMPCTRL; /**< \brief Offset: 0x03 (R/W 8) Sampling Time Control */
+ __IO ADC_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 16) Control B */
+ RoReg8 Reserved1[0x2];
+ __IO ADC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x08 (R/W 8) Window Monitor Control */
+ RoReg8 Reserved2[0x3];
+ __IO ADC_SWTRIG_Type SWTRIG; /**< \brief Offset: 0x0C (R/W 8) Software Trigger */
+ RoReg8 Reserved3[0x3];
+ __IO ADC_INPUTCTRL_Type INPUTCTRL; /**< \brief Offset: 0x10 (R/W 32) Input Control */
+ __IO ADC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x14 (R/W 8) Event Control */
+ RoReg8 Reserved4[0x1];
+ __IO ADC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x16 (R/W 8) Interrupt Enable Clear */
+ __IO ADC_INTENSET_Type INTENSET; /**< \brief Offset: 0x17 (R/W 8) Interrupt Enable Set */
+ __IO ADC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) Interrupt Flag Status and Clear */
+ __I ADC_STATUS_Type STATUS; /**< \brief Offset: 0x19 (R/ 8) Status */
+ __I ADC_RESULT_Type RESULT; /**< \brief Offset: 0x1A (R/ 16) Result */
+ __IO ADC_WINLT_Type WINLT; /**< \brief Offset: 0x1C (R/W 16) Window Monitor Lower Threshold */
+ RoReg8 Reserved5[0x2];
+ __IO ADC_WINUT_Type WINUT; /**< \brief Offset: 0x20 (R/W 16) Window Monitor Upper Threshold */
+ RoReg8 Reserved6[0x2];
+ __IO ADC_GAINCORR_Type GAINCORR; /**< \brief Offset: 0x24 (R/W 16) Gain Correction */
+ __IO ADC_OFFSETCORR_Type OFFSETCORR; /**< \brief Offset: 0x26 (R/W 16) Offset Correction */
+ __IO ADC_CALIB_Type CALIB; /**< \brief Offset: 0x28 (R/W 16) Calibration */
+ __IO ADC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x2A (R/W 8) Debug Control */
+} Adc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_ADC_COMPONENT_ */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/component/dac.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/component/dac.h
new file mode 100644
index 0000000000000000000000000000000000000000..ec6b4c56986129cc95445aad90ce6c0320fde6bc
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/component/dac.h
@@ -0,0 +1,286 @@
+/**
+ * \file
+ *
+ * \brief Component description for DAC
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_DAC_COMPONENT_
+#define _SAMD21_DAC_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR DAC */
+/* ========================================================================== */
+/** \addtogroup SAMD21_DAC Digital Analog Converter */
+/*@{*/
+
+#define DAC_U2214
+#define REV_DAC 0x110
+
+/* -------- DAC_CTRLA : (DAC Offset: 0x0) (R/W 8) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t ENABLE:1; /*!< bit: 1 Enable */
+ uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DAC_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_CTRLA_OFFSET 0x0 /**< \brief (DAC_CTRLA offset) Control A */
+#define DAC_CTRLA_RESETVALUE 0x00ul /**< \brief (DAC_CTRLA reset_value) Control A */
+
+#define DAC_CTRLA_SWRST_Pos 0 /**< \brief (DAC_CTRLA) Software Reset */
+#define DAC_CTRLA_SWRST (0x1ul << DAC_CTRLA_SWRST_Pos)
+#define DAC_CTRLA_ENABLE_Pos 1 /**< \brief (DAC_CTRLA) Enable */
+#define DAC_CTRLA_ENABLE (0x1ul << DAC_CTRLA_ENABLE_Pos)
+#define DAC_CTRLA_RUNSTDBY_Pos 2 /**< \brief (DAC_CTRLA) Run in Standby */
+#define DAC_CTRLA_RUNSTDBY (0x1ul << DAC_CTRLA_RUNSTDBY_Pos)
+#define DAC_CTRLA_MASK 0x07ul /**< \brief (DAC_CTRLA) MASK Register */
+
+/* -------- DAC_CTRLB : (DAC Offset: 0x1) (R/W 8) Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t EOEN:1; /*!< bit: 0 External Output Enable */
+ uint8_t IOEN:1; /*!< bit: 1 Internal Output Enable */
+ uint8_t LEFTADJ:1; /*!< bit: 2 Left Adjusted Data */
+ uint8_t VPD:1; /*!< bit: 3 Voltage Pump Disable */
+ uint8_t BDWP:1; /*!< bit: 4 Bypass DATABUF Write Protection */
+ uint8_t :1; /*!< bit: 5 Reserved */
+ uint8_t REFSEL:2; /*!< bit: 6.. 7 Reference Selection */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DAC_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_CTRLB_OFFSET 0x1 /**< \brief (DAC_CTRLB offset) Control B */
+#define DAC_CTRLB_RESETVALUE 0x00ul /**< \brief (DAC_CTRLB reset_value) Control B */
+
+#define DAC_CTRLB_EOEN_Pos 0 /**< \brief (DAC_CTRLB) External Output Enable */
+#define DAC_CTRLB_EOEN (0x1ul << DAC_CTRLB_EOEN_Pos)
+#define DAC_CTRLB_IOEN_Pos 1 /**< \brief (DAC_CTRLB) Internal Output Enable */
+#define DAC_CTRLB_IOEN (0x1ul << DAC_CTRLB_IOEN_Pos)
+#define DAC_CTRLB_LEFTADJ_Pos 2 /**< \brief (DAC_CTRLB) Left Adjusted Data */
+#define DAC_CTRLB_LEFTADJ (0x1ul << DAC_CTRLB_LEFTADJ_Pos)
+#define DAC_CTRLB_VPD_Pos 3 /**< \brief (DAC_CTRLB) Voltage Pump Disable */
+#define DAC_CTRLB_VPD (0x1ul << DAC_CTRLB_VPD_Pos)
+#define DAC_CTRLB_BDWP_Pos 4 /**< \brief (DAC_CTRLB) Bypass DATABUF Write Protection */
+#define DAC_CTRLB_BDWP (0x1ul << DAC_CTRLB_BDWP_Pos)
+#define DAC_CTRLB_REFSEL_Pos 6 /**< \brief (DAC_CTRLB) Reference Selection */
+#define DAC_CTRLB_REFSEL_Msk (0x3ul << DAC_CTRLB_REFSEL_Pos)
+#define DAC_CTRLB_REFSEL(value) (DAC_CTRLB_REFSEL_Msk & ((value) << DAC_CTRLB_REFSEL_Pos))
+#define DAC_CTRLB_REFSEL_INT1V_Val 0x0ul /**< \brief (DAC_CTRLB) Internal 1.0V reference */
+#define DAC_CTRLB_REFSEL_AVCC_Val 0x1ul /**< \brief (DAC_CTRLB) AVCC */
+#define DAC_CTRLB_REFSEL_VREFP_Val 0x2ul /**< \brief (DAC_CTRLB) External reference */
+#define DAC_CTRLB_REFSEL_INT1V (DAC_CTRLB_REFSEL_INT1V_Val << DAC_CTRLB_REFSEL_Pos)
+#define DAC_CTRLB_REFSEL_AVCC (DAC_CTRLB_REFSEL_AVCC_Val << DAC_CTRLB_REFSEL_Pos)
+#define DAC_CTRLB_REFSEL_VREFP (DAC_CTRLB_REFSEL_VREFP_Val << DAC_CTRLB_REFSEL_Pos)
+#define DAC_CTRLB_MASK 0xDFul /**< \brief (DAC_CTRLB) MASK Register */
+
+/* -------- DAC_EVCTRL : (DAC Offset: 0x2) (R/W 8) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event Input */
+ uint8_t EMPTYEO:1; /*!< bit: 1 Data Buffer Empty Event Output */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DAC_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_EVCTRL_OFFSET 0x2 /**< \brief (DAC_EVCTRL offset) Event Control */
+#define DAC_EVCTRL_RESETVALUE 0x00ul /**< \brief (DAC_EVCTRL reset_value) Event Control */
+
+#define DAC_EVCTRL_STARTEI_Pos 0 /**< \brief (DAC_EVCTRL) Start Conversion Event Input */
+#define DAC_EVCTRL_STARTEI (0x1ul << DAC_EVCTRL_STARTEI_Pos)
+#define DAC_EVCTRL_EMPTYEO_Pos 1 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output */
+#define DAC_EVCTRL_EMPTYEO (0x1ul << DAC_EVCTRL_EMPTYEO_Pos)
+#define DAC_EVCTRL_MASK 0x03ul /**< \brief (DAC_EVCTRL) MASK Register */
+
+/* -------- DAC_INTENCLR : (DAC Offset: 0x4) (R/W 8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t UNDERRUN:1; /*!< bit: 0 Underrun Interrupt Enable */
+ uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty Interrupt Enable */
+ uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready Interrupt Enable */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DAC_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_INTENCLR_OFFSET 0x4 /**< \brief (DAC_INTENCLR offset) Interrupt Enable Clear */
+#define DAC_INTENCLR_RESETVALUE 0x00ul /**< \brief (DAC_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define DAC_INTENCLR_UNDERRUN_Pos 0 /**< \brief (DAC_INTENCLR) Underrun Interrupt Enable */
+#define DAC_INTENCLR_UNDERRUN (0x1ul << DAC_INTENCLR_UNDERRUN_Pos)
+#define DAC_INTENCLR_EMPTY_Pos 1 /**< \brief (DAC_INTENCLR) Data Buffer Empty Interrupt Enable */
+#define DAC_INTENCLR_EMPTY (0x1ul << DAC_INTENCLR_EMPTY_Pos)
+#define DAC_INTENCLR_SYNCRDY_Pos 2 /**< \brief (DAC_INTENCLR) Synchronization Ready Interrupt Enable */
+#define DAC_INTENCLR_SYNCRDY (0x1ul << DAC_INTENCLR_SYNCRDY_Pos)
+#define DAC_INTENCLR_MASK 0x07ul /**< \brief (DAC_INTENCLR) MASK Register */
+
+/* -------- DAC_INTENSET : (DAC Offset: 0x5) (R/W 8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t UNDERRUN:1; /*!< bit: 0 Underrun Interrupt Enable */
+ uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty Interrupt Enable */
+ uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready Interrupt Enable */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DAC_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_INTENSET_OFFSET 0x5 /**< \brief (DAC_INTENSET offset) Interrupt Enable Set */
+#define DAC_INTENSET_RESETVALUE 0x00ul /**< \brief (DAC_INTENSET reset_value) Interrupt Enable Set */
+
+#define DAC_INTENSET_UNDERRUN_Pos 0 /**< \brief (DAC_INTENSET) Underrun Interrupt Enable */
+#define DAC_INTENSET_UNDERRUN (0x1ul << DAC_INTENSET_UNDERRUN_Pos)
+#define DAC_INTENSET_EMPTY_Pos 1 /**< \brief (DAC_INTENSET) Data Buffer Empty Interrupt Enable */
+#define DAC_INTENSET_EMPTY (0x1ul << DAC_INTENSET_EMPTY_Pos)
+#define DAC_INTENSET_SYNCRDY_Pos 2 /**< \brief (DAC_INTENSET) Synchronization Ready Interrupt Enable */
+#define DAC_INTENSET_SYNCRDY (0x1ul << DAC_INTENSET_SYNCRDY_Pos)
+#define DAC_INTENSET_MASK 0x07ul /**< \brief (DAC_INTENSET) MASK Register */
+
+/* -------- DAC_INTFLAG : (DAC Offset: 0x6) (R/W 8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint8_t UNDERRUN:1; /*!< bit: 0 Underrun */
+ __I uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty */
+ __I uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready */
+ __I uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DAC_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_INTFLAG_OFFSET 0x6 /**< \brief (DAC_INTFLAG offset) Interrupt Flag Status and Clear */
+#define DAC_INTFLAG_RESETVALUE 0x00ul /**< \brief (DAC_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define DAC_INTFLAG_UNDERRUN_Pos 0 /**< \brief (DAC_INTFLAG) Underrun */
+#define DAC_INTFLAG_UNDERRUN (0x1ul << DAC_INTFLAG_UNDERRUN_Pos)
+#define DAC_INTFLAG_EMPTY_Pos 1 /**< \brief (DAC_INTFLAG) Data Buffer Empty */
+#define DAC_INTFLAG_EMPTY (0x1ul << DAC_INTFLAG_EMPTY_Pos)
+#define DAC_INTFLAG_SYNCRDY_Pos 2 /**< \brief (DAC_INTFLAG) Synchronization Ready */
+#define DAC_INTFLAG_SYNCRDY (0x1ul << DAC_INTFLAG_SYNCRDY_Pos)
+#define DAC_INTFLAG_MASK 0x07ul /**< \brief (DAC_INTFLAG) MASK Register */
+
+/* -------- DAC_STATUS : (DAC Offset: 0x7) (R/ 8) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t :7; /*!< bit: 0.. 6 Reserved */
+ uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy Status */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DAC_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_STATUS_OFFSET 0x7 /**< \brief (DAC_STATUS offset) Status */
+#define DAC_STATUS_RESETVALUE 0x00ul /**< \brief (DAC_STATUS reset_value) Status */
+
+#define DAC_STATUS_SYNCBUSY_Pos 7 /**< \brief (DAC_STATUS) Synchronization Busy Status */
+#define DAC_STATUS_SYNCBUSY (0x1ul << DAC_STATUS_SYNCBUSY_Pos)
+#define DAC_STATUS_MASK 0x80ul /**< \brief (DAC_STATUS) MASK Register */
+
+/* -------- DAC_DATA : (DAC Offset: 0x8) (R/W 16) Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t DATA:16; /*!< bit: 0..15 Data value to be converted */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} DAC_DATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_DATA_OFFSET 0x8 /**< \brief (DAC_DATA offset) Data */
+#define DAC_DATA_RESETVALUE 0x0000ul /**< \brief (DAC_DATA reset_value) Data */
+
+#define DAC_DATA_DATA_Pos 0 /**< \brief (DAC_DATA) Data value to be converted */
+#define DAC_DATA_DATA_Msk (0xFFFFul << DAC_DATA_DATA_Pos)
+#define DAC_DATA_DATA(value) (DAC_DATA_DATA_Msk & ((value) << DAC_DATA_DATA_Pos))
+#define DAC_DATA_MASK 0xFFFFul /**< \brief (DAC_DATA) MASK Register */
+
+/* -------- DAC_DATABUF : (DAC Offset: 0xC) (R/W 16) Data Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t DATABUF:16; /*!< bit: 0..15 Data Buffer */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} DAC_DATABUF_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DAC_DATABUF_OFFSET 0xC /**< \brief (DAC_DATABUF offset) Data Buffer */
+#define DAC_DATABUF_RESETVALUE 0x0000ul /**< \brief (DAC_DATABUF reset_value) Data Buffer */
+
+#define DAC_DATABUF_DATABUF_Pos 0 /**< \brief (DAC_DATABUF) Data Buffer */
+#define DAC_DATABUF_DATABUF_Msk (0xFFFFul << DAC_DATABUF_DATABUF_Pos)
+#define DAC_DATABUF_DATABUF(value) (DAC_DATABUF_DATABUF_Msk & ((value) << DAC_DATABUF_DATABUF_Pos))
+#define DAC_DATABUF_MASK 0xFFFFul /**< \brief (DAC_DATABUF) MASK Register */
+
+/** \brief DAC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO DAC_CTRLA_Type CTRLA; /**< \brief Offset: 0x0 (R/W 8) Control A */
+ __IO DAC_CTRLB_Type CTRLB; /**< \brief Offset: 0x1 (R/W 8) Control B */
+ __IO DAC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x2 (R/W 8) Event Control */
+ RoReg8 Reserved1[0x1];
+ __IO DAC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x4 (R/W 8) Interrupt Enable Clear */
+ __IO DAC_INTENSET_Type INTENSET; /**< \brief Offset: 0x5 (R/W 8) Interrupt Enable Set */
+ __IO DAC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x6 (R/W 8) Interrupt Flag Status and Clear */
+ __I DAC_STATUS_Type STATUS; /**< \brief Offset: 0x7 (R/ 8) Status */
+ __IO DAC_DATA_Type DATA; /**< \brief Offset: 0x8 (R/W 16) Data */
+ RoReg8 Reserved2[0x2];
+ __IO DAC_DATABUF_Type DATABUF; /**< \brief Offset: 0xC (R/W 16) Data Buffer */
+} Dac;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_DAC_COMPONENT_ */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/component/dmac.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/component/dmac.h
new file mode 100644
index 0000000000000000000000000000000000000000..f26f1be29a8b4b7caf754437f69e8b7be8f5ffda
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/component/dmac.h
@@ -0,0 +1,1087 @@
+/**
+ * \file
+ *
+ * \brief Component description for DMAC
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_DMAC_COMPONENT_
+#define _SAMD21_DMAC_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR DMAC */
+/* ========================================================================== */
+/** \addtogroup SAMD21_DMAC Direct Memory Access Controller */
+/*@{*/
+
+#define DMAC_U2223
+#define REV_DMAC 0x100
+
+/* -------- DMAC_CTRL : (DMAC Offset: 0x00) (R/W 16) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint16_t DMAENABLE:1; /*!< bit: 1 DMA Enable */
+ uint16_t CRCENABLE:1; /*!< bit: 2 CRC Enable */
+ uint16_t :5; /*!< bit: 3.. 7 Reserved */
+ uint16_t LVLEN0:1; /*!< bit: 8 Priority Level 0 Enable */
+ uint16_t LVLEN1:1; /*!< bit: 9 Priority Level 1 Enable */
+ uint16_t LVLEN2:1; /*!< bit: 10 Priority Level 2 Enable */
+ uint16_t LVLEN3:1; /*!< bit: 11 Priority Level 3 Enable */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t :8; /*!< bit: 0.. 7 Reserved */
+ uint16_t LVLEN:4; /*!< bit: 8..11 Priority Level x Enable */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} DMAC_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CTRL_OFFSET 0x00 /**< \brief (DMAC_CTRL offset) Control */
+#define DMAC_CTRL_RESETVALUE 0x0000ul /**< \brief (DMAC_CTRL reset_value) Control */
+
+#define DMAC_CTRL_SWRST_Pos 0 /**< \brief (DMAC_CTRL) Software Reset */
+#define DMAC_CTRL_SWRST (0x1ul << DMAC_CTRL_SWRST_Pos)
+#define DMAC_CTRL_DMAENABLE_Pos 1 /**< \brief (DMAC_CTRL) DMA Enable */
+#define DMAC_CTRL_DMAENABLE (0x1ul << DMAC_CTRL_DMAENABLE_Pos)
+#define DMAC_CTRL_CRCENABLE_Pos 2 /**< \brief (DMAC_CTRL) CRC Enable */
+#define DMAC_CTRL_CRCENABLE (0x1ul << DMAC_CTRL_CRCENABLE_Pos)
+#define DMAC_CTRL_LVLEN0_Pos 8 /**< \brief (DMAC_CTRL) Priority Level 0 Enable */
+#define DMAC_CTRL_LVLEN0 (1 << DMAC_CTRL_LVLEN0_Pos)
+#define DMAC_CTRL_LVLEN1_Pos 9 /**< \brief (DMAC_CTRL) Priority Level 1 Enable */
+#define DMAC_CTRL_LVLEN1 (1 << DMAC_CTRL_LVLEN1_Pos)
+#define DMAC_CTRL_LVLEN2_Pos 10 /**< \brief (DMAC_CTRL) Priority Level 2 Enable */
+#define DMAC_CTRL_LVLEN2 (1 << DMAC_CTRL_LVLEN2_Pos)
+#define DMAC_CTRL_LVLEN3_Pos 11 /**< \brief (DMAC_CTRL) Priority Level 3 Enable */
+#define DMAC_CTRL_LVLEN3 (1 << DMAC_CTRL_LVLEN3_Pos)
+#define DMAC_CTRL_LVLEN_Pos 8 /**< \brief (DMAC_CTRL) Priority Level x Enable */
+#define DMAC_CTRL_LVLEN_Msk (0xFul << DMAC_CTRL_LVLEN_Pos)
+#define DMAC_CTRL_LVLEN(value) (DMAC_CTRL_LVLEN_Msk & ((value) << DMAC_CTRL_LVLEN_Pos))
+#define DMAC_CTRL_MASK 0x0F07ul /**< \brief (DMAC_CTRL) MASK Register */
+
+/* -------- DMAC_CRCCTRL : (DMAC Offset: 0x02) (R/W 16) CRC Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t CRCBEATSIZE:2; /*!< bit: 0.. 1 CRC Beat Size */
+ uint16_t CRCPOLY:2; /*!< bit: 2.. 3 CRC Polynomial Type */
+ uint16_t :4; /*!< bit: 4.. 7 Reserved */
+ uint16_t CRCSRC:6; /*!< bit: 8..13 CRC Input Source */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} DMAC_CRCCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CRCCTRL_OFFSET 0x02 /**< \brief (DMAC_CRCCTRL offset) CRC Control */
+#define DMAC_CRCCTRL_RESETVALUE 0x0000ul /**< \brief (DMAC_CRCCTRL reset_value) CRC Control */
+
+#define DMAC_CRCCTRL_CRCBEATSIZE_Pos 0 /**< \brief (DMAC_CRCCTRL) CRC Beat Size */
+#define DMAC_CRCCTRL_CRCBEATSIZE_Msk (0x3ul << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
+#define DMAC_CRCCTRL_CRCBEATSIZE(value) (DMAC_CRCCTRL_CRCBEATSIZE_Msk & ((value) << DMAC_CRCCTRL_CRCBEATSIZE_Pos))
+#define DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val 0x0ul /**< \brief (DMAC_CRCCTRL) 8-bit bus transfer */
+#define DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val 0x1ul /**< \brief (DMAC_CRCCTRL) 16-bit bus transfer */
+#define DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val 0x2ul /**< \brief (DMAC_CRCCTRL) 32-bit bus transfer */
+#define DMAC_CRCCTRL_CRCBEATSIZE_BYTE (DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
+#define DMAC_CRCCTRL_CRCBEATSIZE_HWORD (DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
+#define DMAC_CRCCTRL_CRCBEATSIZE_WORD (DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
+#define DMAC_CRCCTRL_CRCPOLY_Pos 2 /**< \brief (DMAC_CRCCTRL) CRC Polynomial Type */
+#define DMAC_CRCCTRL_CRCPOLY_Msk (0x3ul << DMAC_CRCCTRL_CRCPOLY_Pos)
+#define DMAC_CRCCTRL_CRCPOLY(value) (DMAC_CRCCTRL_CRCPOLY_Msk & ((value) << DMAC_CRCCTRL_CRCPOLY_Pos))
+#define DMAC_CRCCTRL_CRCPOLY_CRC16_Val 0x0ul /**< \brief (DMAC_CRCCTRL) CRC-16 (CRC-CCITT) */
+#define DMAC_CRCCTRL_CRCPOLY_CRC32_Val 0x1ul /**< \brief (DMAC_CRCCTRL) CRC32 (IEEE 802.3) */
+#define DMAC_CRCCTRL_CRCPOLY_CRC16 (DMAC_CRCCTRL_CRCPOLY_CRC16_Val << DMAC_CRCCTRL_CRCPOLY_Pos)
+#define DMAC_CRCCTRL_CRCPOLY_CRC32 (DMAC_CRCCTRL_CRCPOLY_CRC32_Val << DMAC_CRCCTRL_CRCPOLY_Pos)
+#define DMAC_CRCCTRL_CRCSRC_Pos 8 /**< \brief (DMAC_CRCCTRL) CRC Input Source */
+#define DMAC_CRCCTRL_CRCSRC_Msk (0x3Ful << DMAC_CRCCTRL_CRCSRC_Pos)
+#define DMAC_CRCCTRL_CRCSRC(value) (DMAC_CRCCTRL_CRCSRC_Msk & ((value) << DMAC_CRCCTRL_CRCSRC_Pos))
+#define DMAC_CRCCTRL_CRCSRC_NOACT_Val 0x0ul /**< \brief (DMAC_CRCCTRL) No action */
+#define DMAC_CRCCTRL_CRCSRC_IO_Val 0x1ul /**< \brief (DMAC_CRCCTRL) I/O interface */
+#define DMAC_CRCCTRL_CRCSRC_NOACT (DMAC_CRCCTRL_CRCSRC_NOACT_Val << DMAC_CRCCTRL_CRCSRC_Pos)
+#define DMAC_CRCCTRL_CRCSRC_IO (DMAC_CRCCTRL_CRCSRC_IO_Val << DMAC_CRCCTRL_CRCSRC_Pos)
+#define DMAC_CRCCTRL_MASK 0x3F0Ful /**< \brief (DMAC_CRCCTRL) MASK Register */
+
+/* -------- DMAC_CRCDATAIN : (DMAC Offset: 0x04) (R/W 32) CRC Data Input -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CRCDATAIN:32; /*!< bit: 0..31 CRC Data Input */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DMAC_CRCDATAIN_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CRCDATAIN_OFFSET 0x04 /**< \brief (DMAC_CRCDATAIN offset) CRC Data Input */
+#define DMAC_CRCDATAIN_RESETVALUE 0x00000000ul /**< \brief (DMAC_CRCDATAIN reset_value) CRC Data Input */
+
+#define DMAC_CRCDATAIN_CRCDATAIN_Pos 0 /**< \brief (DMAC_CRCDATAIN) CRC Data Input */
+#define DMAC_CRCDATAIN_CRCDATAIN_Msk (0xFFFFFFFFul << DMAC_CRCDATAIN_CRCDATAIN_Pos)
+#define DMAC_CRCDATAIN_CRCDATAIN(value) (DMAC_CRCDATAIN_CRCDATAIN_Msk & ((value) << DMAC_CRCDATAIN_CRCDATAIN_Pos))
+#define DMAC_CRCDATAIN_MASK 0xFFFFFFFFul /**< \brief (DMAC_CRCDATAIN) MASK Register */
+
+/* -------- DMAC_CRCCHKSUM : (DMAC Offset: 0x08) (R/W 32) CRC Checksum -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CRCCHKSUM:32; /*!< bit: 0..31 CRC Checksum */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DMAC_CRCCHKSUM_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CRCCHKSUM_OFFSET 0x08 /**< \brief (DMAC_CRCCHKSUM offset) CRC Checksum */
+#define DMAC_CRCCHKSUM_RESETVALUE 0x00000000ul /**< \brief (DMAC_CRCCHKSUM reset_value) CRC Checksum */
+
+#define DMAC_CRCCHKSUM_CRCCHKSUM_Pos 0 /**< \brief (DMAC_CRCCHKSUM) CRC Checksum */
+#define DMAC_CRCCHKSUM_CRCCHKSUM_Msk (0xFFFFFFFFul << DMAC_CRCCHKSUM_CRCCHKSUM_Pos)
+#define DMAC_CRCCHKSUM_CRCCHKSUM(value) (DMAC_CRCCHKSUM_CRCCHKSUM_Msk & ((value) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos))
+#define DMAC_CRCCHKSUM_MASK 0xFFFFFFFFul /**< \brief (DMAC_CRCCHKSUM) MASK Register */
+
+/* -------- DMAC_CRCSTATUS : (DMAC Offset: 0x0C) (R/W 8) CRC Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t CRCBUSY:1; /*!< bit: 0 CRC Module Busy */
+ uint8_t CRCZERO:1; /*!< bit: 1 CRC Zero */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DMAC_CRCSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CRCSTATUS_OFFSET 0x0C /**< \brief (DMAC_CRCSTATUS offset) CRC Status */
+#define DMAC_CRCSTATUS_RESETVALUE 0x00ul /**< \brief (DMAC_CRCSTATUS reset_value) CRC Status */
+
+#define DMAC_CRCSTATUS_CRCBUSY_Pos 0 /**< \brief (DMAC_CRCSTATUS) CRC Module Busy */
+#define DMAC_CRCSTATUS_CRCBUSY (0x1ul << DMAC_CRCSTATUS_CRCBUSY_Pos)
+#define DMAC_CRCSTATUS_CRCZERO_Pos 1 /**< \brief (DMAC_CRCSTATUS) CRC Zero */
+#define DMAC_CRCSTATUS_CRCZERO (0x1ul << DMAC_CRCSTATUS_CRCZERO_Pos)
+#define DMAC_CRCSTATUS_MASK 0x03ul /**< \brief (DMAC_CRCSTATUS) MASK Register */
+
+/* -------- DMAC_DBGCTRL : (DMAC Offset: 0x0D) (R/W 8) Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DMAC_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_DBGCTRL_OFFSET 0x0D /**< \brief (DMAC_DBGCTRL offset) Debug Control */
+#define DMAC_DBGCTRL_RESETVALUE 0x00ul /**< \brief (DMAC_DBGCTRL reset_value) Debug Control */
+
+#define DMAC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (DMAC_DBGCTRL) Debug Run */
+#define DMAC_DBGCTRL_DBGRUN (0x1ul << DMAC_DBGCTRL_DBGRUN_Pos)
+#define DMAC_DBGCTRL_MASK 0x01ul /**< \brief (DMAC_DBGCTRL) MASK Register */
+
+/* -------- DMAC_QOSCTRL : (DMAC Offset: 0x0E) (R/W 8) QOS Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t WRBQOS:2; /*!< bit: 0.. 1 Write-Back Quality of Service */
+ uint8_t FQOS:2; /*!< bit: 2.. 3 Fetch Quality of Service */
+ uint8_t DQOS:2; /*!< bit: 4.. 5 Data Transfer Quality of Service */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DMAC_QOSCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_QOSCTRL_OFFSET 0x0E /**< \brief (DMAC_QOSCTRL offset) QOS Control */
+#define DMAC_QOSCTRL_RESETVALUE 0x15ul /**< \brief (DMAC_QOSCTRL reset_value) QOS Control */
+
+#define DMAC_QOSCTRL_WRBQOS_Pos 0 /**< \brief (DMAC_QOSCTRL) Write-Back Quality of Service */
+#define DMAC_QOSCTRL_WRBQOS_Msk (0x3ul << DMAC_QOSCTRL_WRBQOS_Pos)
+#define DMAC_QOSCTRL_WRBQOS(value) (DMAC_QOSCTRL_WRBQOS_Msk & ((value) << DMAC_QOSCTRL_WRBQOS_Pos))
+#define DMAC_QOSCTRL_WRBQOS_DISABLE_Val 0x0ul /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */
+#define DMAC_QOSCTRL_WRBQOS_LOW_Val 0x1ul /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */
+#define DMAC_QOSCTRL_WRBQOS_MEDIUM_Val 0x2ul /**< \brief (DMAC_QOSCTRL) Sensitive Latency */
+#define DMAC_QOSCTRL_WRBQOS_HIGH_Val 0x3ul /**< \brief (DMAC_QOSCTRL) Critical Latency */
+#define DMAC_QOSCTRL_WRBQOS_DISABLE (DMAC_QOSCTRL_WRBQOS_DISABLE_Val << DMAC_QOSCTRL_WRBQOS_Pos)
+#define DMAC_QOSCTRL_WRBQOS_LOW (DMAC_QOSCTRL_WRBQOS_LOW_Val << DMAC_QOSCTRL_WRBQOS_Pos)
+#define DMAC_QOSCTRL_WRBQOS_MEDIUM (DMAC_QOSCTRL_WRBQOS_MEDIUM_Val << DMAC_QOSCTRL_WRBQOS_Pos)
+#define DMAC_QOSCTRL_WRBQOS_HIGH (DMAC_QOSCTRL_WRBQOS_HIGH_Val << DMAC_QOSCTRL_WRBQOS_Pos)
+#define DMAC_QOSCTRL_FQOS_Pos 2 /**< \brief (DMAC_QOSCTRL) Fetch Quality of Service */
+#define DMAC_QOSCTRL_FQOS_Msk (0x3ul << DMAC_QOSCTRL_FQOS_Pos)
+#define DMAC_QOSCTRL_FQOS(value) (DMAC_QOSCTRL_FQOS_Msk & ((value) << DMAC_QOSCTRL_FQOS_Pos))
+#define DMAC_QOSCTRL_FQOS_DISABLE_Val 0x0ul /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */
+#define DMAC_QOSCTRL_FQOS_LOW_Val 0x1ul /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */
+#define DMAC_QOSCTRL_FQOS_MEDIUM_Val 0x2ul /**< \brief (DMAC_QOSCTRL) Sensitive Latency */
+#define DMAC_QOSCTRL_FQOS_HIGH_Val 0x3ul /**< \brief (DMAC_QOSCTRL) Critical Latency */
+#define DMAC_QOSCTRL_FQOS_DISABLE (DMAC_QOSCTRL_FQOS_DISABLE_Val << DMAC_QOSCTRL_FQOS_Pos)
+#define DMAC_QOSCTRL_FQOS_LOW (DMAC_QOSCTRL_FQOS_LOW_Val << DMAC_QOSCTRL_FQOS_Pos)
+#define DMAC_QOSCTRL_FQOS_MEDIUM (DMAC_QOSCTRL_FQOS_MEDIUM_Val << DMAC_QOSCTRL_FQOS_Pos)
+#define DMAC_QOSCTRL_FQOS_HIGH (DMAC_QOSCTRL_FQOS_HIGH_Val << DMAC_QOSCTRL_FQOS_Pos)
+#define DMAC_QOSCTRL_DQOS_Pos 4 /**< \brief (DMAC_QOSCTRL) Data Transfer Quality of Service */
+#define DMAC_QOSCTRL_DQOS_Msk (0x3ul << DMAC_QOSCTRL_DQOS_Pos)
+#define DMAC_QOSCTRL_DQOS(value) (DMAC_QOSCTRL_DQOS_Msk & ((value) << DMAC_QOSCTRL_DQOS_Pos))
+#define DMAC_QOSCTRL_DQOS_DISABLE_Val 0x0ul /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */
+#define DMAC_QOSCTRL_DQOS_LOW_Val 0x1ul /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */
+#define DMAC_QOSCTRL_DQOS_MEDIUM_Val 0x2ul /**< \brief (DMAC_QOSCTRL) Sensitive Latency */
+#define DMAC_QOSCTRL_DQOS_HIGH_Val 0x3ul /**< \brief (DMAC_QOSCTRL) Critical Latency */
+#define DMAC_QOSCTRL_DQOS_DISABLE (DMAC_QOSCTRL_DQOS_DISABLE_Val << DMAC_QOSCTRL_DQOS_Pos)
+#define DMAC_QOSCTRL_DQOS_LOW (DMAC_QOSCTRL_DQOS_LOW_Val << DMAC_QOSCTRL_DQOS_Pos)
+#define DMAC_QOSCTRL_DQOS_MEDIUM (DMAC_QOSCTRL_DQOS_MEDIUM_Val << DMAC_QOSCTRL_DQOS_Pos)
+#define DMAC_QOSCTRL_DQOS_HIGH (DMAC_QOSCTRL_DQOS_HIGH_Val << DMAC_QOSCTRL_DQOS_Pos)
+#define DMAC_QOSCTRL_MASK 0x3Ful /**< \brief (DMAC_QOSCTRL) MASK Register */
+
+/* -------- DMAC_SWTRIGCTRL : (DMAC Offset: 0x10) (R/W 32) Software Trigger Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWTRIG0:1; /*!< bit: 0 Channel 0 Software Trigger */
+ uint32_t SWTRIG1:1; /*!< bit: 1 Channel 1 Software Trigger */
+ uint32_t SWTRIG2:1; /*!< bit: 2 Channel 2 Software Trigger */
+ uint32_t SWTRIG3:1; /*!< bit: 3 Channel 3 Software Trigger */
+ uint32_t SWTRIG4:1; /*!< bit: 4 Channel 4 Software Trigger */
+ uint32_t SWTRIG5:1; /*!< bit: 5 Channel 5 Software Trigger */
+ uint32_t SWTRIG6:1; /*!< bit: 6 Channel 6 Software Trigger */
+ uint32_t SWTRIG7:1; /*!< bit: 7 Channel 7 Software Trigger */
+ uint32_t SWTRIG8:1; /*!< bit: 8 Channel 8 Software Trigger */
+ uint32_t SWTRIG9:1; /*!< bit: 9 Channel 9 Software Trigger */
+ uint32_t SWTRIG10:1; /*!< bit: 10 Channel 10 Software Trigger */
+ uint32_t SWTRIG11:1; /*!< bit: 11 Channel 11 Software Trigger */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t SWTRIG:12; /*!< bit: 0..11 Channel x Software Trigger */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} DMAC_SWTRIGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_SWTRIGCTRL_OFFSET 0x10 /**< \brief (DMAC_SWTRIGCTRL offset) Software Trigger Control */
+#define DMAC_SWTRIGCTRL_RESETVALUE 0x00000000ul /**< \brief (DMAC_SWTRIGCTRL reset_value) Software Trigger Control */
+
+#define DMAC_SWTRIGCTRL_SWTRIG0_Pos 0 /**< \brief (DMAC_SWTRIGCTRL) Channel 0 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG0 (1 << DMAC_SWTRIGCTRL_SWTRIG0_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG1_Pos 1 /**< \brief (DMAC_SWTRIGCTRL) Channel 1 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG1 (1 << DMAC_SWTRIGCTRL_SWTRIG1_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG2_Pos 2 /**< \brief (DMAC_SWTRIGCTRL) Channel 2 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG2 (1 << DMAC_SWTRIGCTRL_SWTRIG2_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG3_Pos 3 /**< \brief (DMAC_SWTRIGCTRL) Channel 3 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG3 (1 << DMAC_SWTRIGCTRL_SWTRIG3_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG4_Pos 4 /**< \brief (DMAC_SWTRIGCTRL) Channel 4 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG4 (1 << DMAC_SWTRIGCTRL_SWTRIG4_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG5_Pos 5 /**< \brief (DMAC_SWTRIGCTRL) Channel 5 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG5 (1 << DMAC_SWTRIGCTRL_SWTRIG5_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG6_Pos 6 /**< \brief (DMAC_SWTRIGCTRL) Channel 6 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG6 (1 << DMAC_SWTRIGCTRL_SWTRIG6_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG7_Pos 7 /**< \brief (DMAC_SWTRIGCTRL) Channel 7 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG7 (1 << DMAC_SWTRIGCTRL_SWTRIG7_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG8_Pos 8 /**< \brief (DMAC_SWTRIGCTRL) Channel 8 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG8 (1 << DMAC_SWTRIGCTRL_SWTRIG8_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG9_Pos 9 /**< \brief (DMAC_SWTRIGCTRL) Channel 9 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG9 (1 << DMAC_SWTRIGCTRL_SWTRIG9_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG10_Pos 10 /**< \brief (DMAC_SWTRIGCTRL) Channel 10 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG10 (1 << DMAC_SWTRIGCTRL_SWTRIG10_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG11_Pos 11 /**< \brief (DMAC_SWTRIGCTRL) Channel 11 Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG11 (1 << DMAC_SWTRIGCTRL_SWTRIG11_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG_Pos 0 /**< \brief (DMAC_SWTRIGCTRL) Channel x Software Trigger */
+#define DMAC_SWTRIGCTRL_SWTRIG_Msk (0xFFFul << DMAC_SWTRIGCTRL_SWTRIG_Pos)
+#define DMAC_SWTRIGCTRL_SWTRIG(value) (DMAC_SWTRIGCTRL_SWTRIG_Msk & ((value) << DMAC_SWTRIGCTRL_SWTRIG_Pos))
+#define DMAC_SWTRIGCTRL_MASK 0x00000FFFul /**< \brief (DMAC_SWTRIGCTRL) MASK Register */
+
+/* -------- DMAC_PRICTRL0 : (DMAC Offset: 0x14) (R/W 32) Priority Control 0 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t LVLPRI0:4; /*!< bit: 0.. 3 Level 0 Channel Priority Number */
+ uint32_t :3; /*!< bit: 4.. 6 Reserved */
+ uint32_t RRLVLEN0:1; /*!< bit: 7 Level 0 Round-Robin Scheduling Enable */
+ uint32_t LVLPRI1:4; /*!< bit: 8..11 Level 1 Channel Priority Number */
+ uint32_t :3; /*!< bit: 12..14 Reserved */
+ uint32_t RRLVLEN1:1; /*!< bit: 15 Level 1 Round-Robin Scheduling Enable */
+ uint32_t LVLPRI2:4; /*!< bit: 16..19 Level 2 Channel Priority Number */
+ uint32_t :3; /*!< bit: 20..22 Reserved */
+ uint32_t RRLVLEN2:1; /*!< bit: 23 Level 2 Round-Robin Scheduling Enable */
+ uint32_t LVLPRI3:4; /*!< bit: 24..27 Level 3 Channel Priority Number */
+ uint32_t :3; /*!< bit: 28..30 Reserved */
+ uint32_t RRLVLEN3:1; /*!< bit: 31 Level 3 Round-Robin Scheduling Enable */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DMAC_PRICTRL0_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_PRICTRL0_OFFSET 0x14 /**< \brief (DMAC_PRICTRL0 offset) Priority Control 0 */
+#define DMAC_PRICTRL0_RESETVALUE 0x00000000ul /**< \brief (DMAC_PRICTRL0 reset_value) Priority Control 0 */
+
+#define DMAC_PRICTRL0_LVLPRI0_Pos 0 /**< \brief (DMAC_PRICTRL0) Level 0 Channel Priority Number */
+#define DMAC_PRICTRL0_LVLPRI0_Msk (0xFul << DMAC_PRICTRL0_LVLPRI0_Pos)
+#define DMAC_PRICTRL0_LVLPRI0(value) (DMAC_PRICTRL0_LVLPRI0_Msk & ((value) << DMAC_PRICTRL0_LVLPRI0_Pos))
+#define DMAC_PRICTRL0_RRLVLEN0_Pos 7 /**< \brief (DMAC_PRICTRL0) Level 0 Round-Robin Scheduling Enable */
+#define DMAC_PRICTRL0_RRLVLEN0 (0x1ul << DMAC_PRICTRL0_RRLVLEN0_Pos)
+#define DMAC_PRICTRL0_LVLPRI1_Pos 8 /**< \brief (DMAC_PRICTRL0) Level 1 Channel Priority Number */
+#define DMAC_PRICTRL0_LVLPRI1_Msk (0xFul << DMAC_PRICTRL0_LVLPRI1_Pos)
+#define DMAC_PRICTRL0_LVLPRI1(value) (DMAC_PRICTRL0_LVLPRI1_Msk & ((value) << DMAC_PRICTRL0_LVLPRI1_Pos))
+#define DMAC_PRICTRL0_RRLVLEN1_Pos 15 /**< \brief (DMAC_PRICTRL0) Level 1 Round-Robin Scheduling Enable */
+#define DMAC_PRICTRL0_RRLVLEN1 (0x1ul << DMAC_PRICTRL0_RRLVLEN1_Pos)
+#define DMAC_PRICTRL0_LVLPRI2_Pos 16 /**< \brief (DMAC_PRICTRL0) Level 2 Channel Priority Number */
+#define DMAC_PRICTRL0_LVLPRI2_Msk (0xFul << DMAC_PRICTRL0_LVLPRI2_Pos)
+#define DMAC_PRICTRL0_LVLPRI2(value) (DMAC_PRICTRL0_LVLPRI2_Msk & ((value) << DMAC_PRICTRL0_LVLPRI2_Pos))
+#define DMAC_PRICTRL0_RRLVLEN2_Pos 23 /**< \brief (DMAC_PRICTRL0) Level 2 Round-Robin Scheduling Enable */
+#define DMAC_PRICTRL0_RRLVLEN2 (0x1ul << DMAC_PRICTRL0_RRLVLEN2_Pos)
+#define DMAC_PRICTRL0_LVLPRI3_Pos 24 /**< \brief (DMAC_PRICTRL0) Level 3 Channel Priority Number */
+#define DMAC_PRICTRL0_LVLPRI3_Msk (0xFul << DMAC_PRICTRL0_LVLPRI3_Pos)
+#define DMAC_PRICTRL0_LVLPRI3(value) (DMAC_PRICTRL0_LVLPRI3_Msk & ((value) << DMAC_PRICTRL0_LVLPRI3_Pos))
+#define DMAC_PRICTRL0_RRLVLEN3_Pos 31 /**< \brief (DMAC_PRICTRL0) Level 3 Round-Robin Scheduling Enable */
+#define DMAC_PRICTRL0_RRLVLEN3 (0x1ul << DMAC_PRICTRL0_RRLVLEN3_Pos)
+#define DMAC_PRICTRL0_MASK 0x8F8F8F8Ful /**< \brief (DMAC_PRICTRL0) MASK Register */
+
+/* -------- DMAC_INTPEND : (DMAC Offset: 0x20) (R/W 16) Interrupt Pending -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t ID:4; /*!< bit: 0.. 3 Channel ID */
+ uint16_t :4; /*!< bit: 4.. 7 Reserved */
+ uint16_t TERR:1; /*!< bit: 8 Transfer Error */
+ uint16_t TCMPL:1; /*!< bit: 9 Transfer Complete */
+ uint16_t SUSP:1; /*!< bit: 10 Channel Suspend */
+ uint16_t :2; /*!< bit: 11..12 Reserved */
+ uint16_t FERR:1; /*!< bit: 13 Fetch Error */
+ uint16_t BUSY:1; /*!< bit: 14 Busy */
+ uint16_t PEND:1; /*!< bit: 15 Pending */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} DMAC_INTPEND_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_INTPEND_OFFSET 0x20 /**< \brief (DMAC_INTPEND offset) Interrupt Pending */
+#define DMAC_INTPEND_RESETVALUE 0x0000ul /**< \brief (DMAC_INTPEND reset_value) Interrupt Pending */
+
+#define DMAC_INTPEND_ID_Pos 0 /**< \brief (DMAC_INTPEND) Channel ID */
+#define DMAC_INTPEND_ID_Msk (0xFul << DMAC_INTPEND_ID_Pos)
+#define DMAC_INTPEND_ID(value) (DMAC_INTPEND_ID_Msk & ((value) << DMAC_INTPEND_ID_Pos))
+#define DMAC_INTPEND_TERR_Pos 8 /**< \brief (DMAC_INTPEND) Transfer Error */
+#define DMAC_INTPEND_TERR (0x1ul << DMAC_INTPEND_TERR_Pos)
+#define DMAC_INTPEND_TCMPL_Pos 9 /**< \brief (DMAC_INTPEND) Transfer Complete */
+#define DMAC_INTPEND_TCMPL (0x1ul << DMAC_INTPEND_TCMPL_Pos)
+#define DMAC_INTPEND_SUSP_Pos 10 /**< \brief (DMAC_INTPEND) Channel Suspend */
+#define DMAC_INTPEND_SUSP (0x1ul << DMAC_INTPEND_SUSP_Pos)
+#define DMAC_INTPEND_FERR_Pos 13 /**< \brief (DMAC_INTPEND) Fetch Error */
+#define DMAC_INTPEND_FERR (0x1ul << DMAC_INTPEND_FERR_Pos)
+#define DMAC_INTPEND_BUSY_Pos 14 /**< \brief (DMAC_INTPEND) Busy */
+#define DMAC_INTPEND_BUSY (0x1ul << DMAC_INTPEND_BUSY_Pos)
+#define DMAC_INTPEND_PEND_Pos 15 /**< \brief (DMAC_INTPEND) Pending */
+#define DMAC_INTPEND_PEND (0x1ul << DMAC_INTPEND_PEND_Pos)
+#define DMAC_INTPEND_MASK 0xE70Ful /**< \brief (DMAC_INTPEND) MASK Register */
+
+/* -------- DMAC_INTSTATUS : (DMAC Offset: 0x24) (R/ 32) Interrupt Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CHINT0:1; /*!< bit: 0 Channel 0 Pending Interrupt */
+ uint32_t CHINT1:1; /*!< bit: 1 Channel 1 Pending Interrupt */
+ uint32_t CHINT2:1; /*!< bit: 2 Channel 2 Pending Interrupt */
+ uint32_t CHINT3:1; /*!< bit: 3 Channel 3 Pending Interrupt */
+ uint32_t CHINT4:1; /*!< bit: 4 Channel 4 Pending Interrupt */
+ uint32_t CHINT5:1; /*!< bit: 5 Channel 5 Pending Interrupt */
+ uint32_t CHINT6:1; /*!< bit: 6 Channel 6 Pending Interrupt */
+ uint32_t CHINT7:1; /*!< bit: 7 Channel 7 Pending Interrupt */
+ uint32_t CHINT8:1; /*!< bit: 8 Channel 8 Pending Interrupt */
+ uint32_t CHINT9:1; /*!< bit: 9 Channel 9 Pending Interrupt */
+ uint32_t CHINT10:1; /*!< bit: 10 Channel 10 Pending Interrupt */
+ uint32_t CHINT11:1; /*!< bit: 11 Channel 11 Pending Interrupt */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t CHINT:12; /*!< bit: 0..11 Channel x Pending Interrupt */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} DMAC_INTSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_INTSTATUS_OFFSET 0x24 /**< \brief (DMAC_INTSTATUS offset) Interrupt Status */
+#define DMAC_INTSTATUS_RESETVALUE 0x00000000ul /**< \brief (DMAC_INTSTATUS reset_value) Interrupt Status */
+
+#define DMAC_INTSTATUS_CHINT0_Pos 0 /**< \brief (DMAC_INTSTATUS) Channel 0 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT0 (1 << DMAC_INTSTATUS_CHINT0_Pos)
+#define DMAC_INTSTATUS_CHINT1_Pos 1 /**< \brief (DMAC_INTSTATUS) Channel 1 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT1 (1 << DMAC_INTSTATUS_CHINT1_Pos)
+#define DMAC_INTSTATUS_CHINT2_Pos 2 /**< \brief (DMAC_INTSTATUS) Channel 2 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT2 (1 << DMAC_INTSTATUS_CHINT2_Pos)
+#define DMAC_INTSTATUS_CHINT3_Pos 3 /**< \brief (DMAC_INTSTATUS) Channel 3 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT3 (1 << DMAC_INTSTATUS_CHINT3_Pos)
+#define DMAC_INTSTATUS_CHINT4_Pos 4 /**< \brief (DMAC_INTSTATUS) Channel 4 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT4 (1 << DMAC_INTSTATUS_CHINT4_Pos)
+#define DMAC_INTSTATUS_CHINT5_Pos 5 /**< \brief (DMAC_INTSTATUS) Channel 5 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT5 (1 << DMAC_INTSTATUS_CHINT5_Pos)
+#define DMAC_INTSTATUS_CHINT6_Pos 6 /**< \brief (DMAC_INTSTATUS) Channel 6 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT6 (1 << DMAC_INTSTATUS_CHINT6_Pos)
+#define DMAC_INTSTATUS_CHINT7_Pos 7 /**< \brief (DMAC_INTSTATUS) Channel 7 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT7 (1 << DMAC_INTSTATUS_CHINT7_Pos)
+#define DMAC_INTSTATUS_CHINT8_Pos 8 /**< \brief (DMAC_INTSTATUS) Channel 8 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT8 (1 << DMAC_INTSTATUS_CHINT8_Pos)
+#define DMAC_INTSTATUS_CHINT9_Pos 9 /**< \brief (DMAC_INTSTATUS) Channel 9 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT9 (1 << DMAC_INTSTATUS_CHINT9_Pos)
+#define DMAC_INTSTATUS_CHINT10_Pos 10 /**< \brief (DMAC_INTSTATUS) Channel 10 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT10 (1 << DMAC_INTSTATUS_CHINT10_Pos)
+#define DMAC_INTSTATUS_CHINT11_Pos 11 /**< \brief (DMAC_INTSTATUS) Channel 11 Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT11 (1 << DMAC_INTSTATUS_CHINT11_Pos)
+#define DMAC_INTSTATUS_CHINT_Pos 0 /**< \brief (DMAC_INTSTATUS) Channel x Pending Interrupt */
+#define DMAC_INTSTATUS_CHINT_Msk (0xFFFul << DMAC_INTSTATUS_CHINT_Pos)
+#define DMAC_INTSTATUS_CHINT(value) (DMAC_INTSTATUS_CHINT_Msk & ((value) << DMAC_INTSTATUS_CHINT_Pos))
+#define DMAC_INTSTATUS_MASK 0x00000FFFul /**< \brief (DMAC_INTSTATUS) MASK Register */
+
+/* -------- DMAC_BUSYCH : (DMAC Offset: 0x28) (R/ 32) Busy Channels -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t BUSYCH0:1; /*!< bit: 0 Busy Channel 0 */
+ uint32_t BUSYCH1:1; /*!< bit: 1 Busy Channel 1 */
+ uint32_t BUSYCH2:1; /*!< bit: 2 Busy Channel 2 */
+ uint32_t BUSYCH3:1; /*!< bit: 3 Busy Channel 3 */
+ uint32_t BUSYCH4:1; /*!< bit: 4 Busy Channel 4 */
+ uint32_t BUSYCH5:1; /*!< bit: 5 Busy Channel 5 */
+ uint32_t BUSYCH6:1; /*!< bit: 6 Busy Channel 6 */
+ uint32_t BUSYCH7:1; /*!< bit: 7 Busy Channel 7 */
+ uint32_t BUSYCH8:1; /*!< bit: 8 Busy Channel 8 */
+ uint32_t BUSYCH9:1; /*!< bit: 9 Busy Channel 9 */
+ uint32_t BUSYCH10:1; /*!< bit: 10 Busy Channel 10 */
+ uint32_t BUSYCH11:1; /*!< bit: 11 Busy Channel 11 */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t BUSYCH:12; /*!< bit: 0..11 Busy Channel x */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} DMAC_BUSYCH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_BUSYCH_OFFSET 0x28 /**< \brief (DMAC_BUSYCH offset) Busy Channels */
+#define DMAC_BUSYCH_RESETVALUE 0x00000000ul /**< \brief (DMAC_BUSYCH reset_value) Busy Channels */
+
+#define DMAC_BUSYCH_BUSYCH0_Pos 0 /**< \brief (DMAC_BUSYCH) Busy Channel 0 */
+#define DMAC_BUSYCH_BUSYCH0 (1 << DMAC_BUSYCH_BUSYCH0_Pos)
+#define DMAC_BUSYCH_BUSYCH1_Pos 1 /**< \brief (DMAC_BUSYCH) Busy Channel 1 */
+#define DMAC_BUSYCH_BUSYCH1 (1 << DMAC_BUSYCH_BUSYCH1_Pos)
+#define DMAC_BUSYCH_BUSYCH2_Pos 2 /**< \brief (DMAC_BUSYCH) Busy Channel 2 */
+#define DMAC_BUSYCH_BUSYCH2 (1 << DMAC_BUSYCH_BUSYCH2_Pos)
+#define DMAC_BUSYCH_BUSYCH3_Pos 3 /**< \brief (DMAC_BUSYCH) Busy Channel 3 */
+#define DMAC_BUSYCH_BUSYCH3 (1 << DMAC_BUSYCH_BUSYCH3_Pos)
+#define DMAC_BUSYCH_BUSYCH4_Pos 4 /**< \brief (DMAC_BUSYCH) Busy Channel 4 */
+#define DMAC_BUSYCH_BUSYCH4 (1 << DMAC_BUSYCH_BUSYCH4_Pos)
+#define DMAC_BUSYCH_BUSYCH5_Pos 5 /**< \brief (DMAC_BUSYCH) Busy Channel 5 */
+#define DMAC_BUSYCH_BUSYCH5 (1 << DMAC_BUSYCH_BUSYCH5_Pos)
+#define DMAC_BUSYCH_BUSYCH6_Pos 6 /**< \brief (DMAC_BUSYCH) Busy Channel 6 */
+#define DMAC_BUSYCH_BUSYCH6 (1 << DMAC_BUSYCH_BUSYCH6_Pos)
+#define DMAC_BUSYCH_BUSYCH7_Pos 7 /**< \brief (DMAC_BUSYCH) Busy Channel 7 */
+#define DMAC_BUSYCH_BUSYCH7 (1 << DMAC_BUSYCH_BUSYCH7_Pos)
+#define DMAC_BUSYCH_BUSYCH8_Pos 8 /**< \brief (DMAC_BUSYCH) Busy Channel 8 */
+#define DMAC_BUSYCH_BUSYCH8 (1 << DMAC_BUSYCH_BUSYCH8_Pos)
+#define DMAC_BUSYCH_BUSYCH9_Pos 9 /**< \brief (DMAC_BUSYCH) Busy Channel 9 */
+#define DMAC_BUSYCH_BUSYCH9 (1 << DMAC_BUSYCH_BUSYCH9_Pos)
+#define DMAC_BUSYCH_BUSYCH10_Pos 10 /**< \brief (DMAC_BUSYCH) Busy Channel 10 */
+#define DMAC_BUSYCH_BUSYCH10 (1 << DMAC_BUSYCH_BUSYCH10_Pos)
+#define DMAC_BUSYCH_BUSYCH11_Pos 11 /**< \brief (DMAC_BUSYCH) Busy Channel 11 */
+#define DMAC_BUSYCH_BUSYCH11 (1 << DMAC_BUSYCH_BUSYCH11_Pos)
+#define DMAC_BUSYCH_BUSYCH_Pos 0 /**< \brief (DMAC_BUSYCH) Busy Channel x */
+#define DMAC_BUSYCH_BUSYCH_Msk (0xFFFul << DMAC_BUSYCH_BUSYCH_Pos)
+#define DMAC_BUSYCH_BUSYCH(value) (DMAC_BUSYCH_BUSYCH_Msk & ((value) << DMAC_BUSYCH_BUSYCH_Pos))
+#define DMAC_BUSYCH_MASK 0x00000FFFul /**< \brief (DMAC_BUSYCH) MASK Register */
+
+/* -------- DMAC_PENDCH : (DMAC Offset: 0x2C) (R/ 32) Pending Channels -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t PENDCH0:1; /*!< bit: 0 Pending Channel 0 */
+ uint32_t PENDCH1:1; /*!< bit: 1 Pending Channel 1 */
+ uint32_t PENDCH2:1; /*!< bit: 2 Pending Channel 2 */
+ uint32_t PENDCH3:1; /*!< bit: 3 Pending Channel 3 */
+ uint32_t PENDCH4:1; /*!< bit: 4 Pending Channel 4 */
+ uint32_t PENDCH5:1; /*!< bit: 5 Pending Channel 5 */
+ uint32_t PENDCH6:1; /*!< bit: 6 Pending Channel 6 */
+ uint32_t PENDCH7:1; /*!< bit: 7 Pending Channel 7 */
+ uint32_t PENDCH8:1; /*!< bit: 8 Pending Channel 8 */
+ uint32_t PENDCH9:1; /*!< bit: 9 Pending Channel 9 */
+ uint32_t PENDCH10:1; /*!< bit: 10 Pending Channel 10 */
+ uint32_t PENDCH11:1; /*!< bit: 11 Pending Channel 11 */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t PENDCH:12; /*!< bit: 0..11 Pending Channel x */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} DMAC_PENDCH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_PENDCH_OFFSET 0x2C /**< \brief (DMAC_PENDCH offset) Pending Channels */
+#define DMAC_PENDCH_RESETVALUE 0x00000000ul /**< \brief (DMAC_PENDCH reset_value) Pending Channels */
+
+#define DMAC_PENDCH_PENDCH0_Pos 0 /**< \brief (DMAC_PENDCH) Pending Channel 0 */
+#define DMAC_PENDCH_PENDCH0 (1 << DMAC_PENDCH_PENDCH0_Pos)
+#define DMAC_PENDCH_PENDCH1_Pos 1 /**< \brief (DMAC_PENDCH) Pending Channel 1 */
+#define DMAC_PENDCH_PENDCH1 (1 << DMAC_PENDCH_PENDCH1_Pos)
+#define DMAC_PENDCH_PENDCH2_Pos 2 /**< \brief (DMAC_PENDCH) Pending Channel 2 */
+#define DMAC_PENDCH_PENDCH2 (1 << DMAC_PENDCH_PENDCH2_Pos)
+#define DMAC_PENDCH_PENDCH3_Pos 3 /**< \brief (DMAC_PENDCH) Pending Channel 3 */
+#define DMAC_PENDCH_PENDCH3 (1 << DMAC_PENDCH_PENDCH3_Pos)
+#define DMAC_PENDCH_PENDCH4_Pos 4 /**< \brief (DMAC_PENDCH) Pending Channel 4 */
+#define DMAC_PENDCH_PENDCH4 (1 << DMAC_PENDCH_PENDCH4_Pos)
+#define DMAC_PENDCH_PENDCH5_Pos 5 /**< \brief (DMAC_PENDCH) Pending Channel 5 */
+#define DMAC_PENDCH_PENDCH5 (1 << DMAC_PENDCH_PENDCH5_Pos)
+#define DMAC_PENDCH_PENDCH6_Pos 6 /**< \brief (DMAC_PENDCH) Pending Channel 6 */
+#define DMAC_PENDCH_PENDCH6 (1 << DMAC_PENDCH_PENDCH6_Pos)
+#define DMAC_PENDCH_PENDCH7_Pos 7 /**< \brief (DMAC_PENDCH) Pending Channel 7 */
+#define DMAC_PENDCH_PENDCH7 (1 << DMAC_PENDCH_PENDCH7_Pos)
+#define DMAC_PENDCH_PENDCH8_Pos 8 /**< \brief (DMAC_PENDCH) Pending Channel 8 */
+#define DMAC_PENDCH_PENDCH8 (1 << DMAC_PENDCH_PENDCH8_Pos)
+#define DMAC_PENDCH_PENDCH9_Pos 9 /**< \brief (DMAC_PENDCH) Pending Channel 9 */
+#define DMAC_PENDCH_PENDCH9 (1 << DMAC_PENDCH_PENDCH9_Pos)
+#define DMAC_PENDCH_PENDCH10_Pos 10 /**< \brief (DMAC_PENDCH) Pending Channel 10 */
+#define DMAC_PENDCH_PENDCH10 (1 << DMAC_PENDCH_PENDCH10_Pos)
+#define DMAC_PENDCH_PENDCH11_Pos 11 /**< \brief (DMAC_PENDCH) Pending Channel 11 */
+#define DMAC_PENDCH_PENDCH11 (1 << DMAC_PENDCH_PENDCH11_Pos)
+#define DMAC_PENDCH_PENDCH_Pos 0 /**< \brief (DMAC_PENDCH) Pending Channel x */
+#define DMAC_PENDCH_PENDCH_Msk (0xFFFul << DMAC_PENDCH_PENDCH_Pos)
+#define DMAC_PENDCH_PENDCH(value) (DMAC_PENDCH_PENDCH_Msk & ((value) << DMAC_PENDCH_PENDCH_Pos))
+#define DMAC_PENDCH_MASK 0x00000FFFul /**< \brief (DMAC_PENDCH) MASK Register */
+
+/* -------- DMAC_ACTIVE : (DMAC Offset: 0x30) (R/ 32) Active Channel and Levels -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t LVLEX0:1; /*!< bit: 0 Level 0 Channel Trigger Request Executing */
+ uint32_t LVLEX1:1; /*!< bit: 1 Level 1 Channel Trigger Request Executing */
+ uint32_t LVLEX2:1; /*!< bit: 2 Level 2 Channel Trigger Request Executing */
+ uint32_t LVLEX3:1; /*!< bit: 3 Level 3 Channel Trigger Request Executing */
+ uint32_t :4; /*!< bit: 4.. 7 Reserved */
+ uint32_t ID:5; /*!< bit: 8..12 Active Channel ID */
+ uint32_t :2; /*!< bit: 13..14 Reserved */
+ uint32_t ABUSY:1; /*!< bit: 15 Active Channel Busy */
+ uint32_t BTCNT:16; /*!< bit: 16..31 Active Channel Block Transfer Count */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t LVLEX:4; /*!< bit: 0.. 3 Level x Channel Trigger Request Executing */
+ uint32_t :28; /*!< bit: 4..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} DMAC_ACTIVE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_ACTIVE_OFFSET 0x30 /**< \brief (DMAC_ACTIVE offset) Active Channel and Levels */
+#define DMAC_ACTIVE_RESETVALUE 0x00000000ul /**< \brief (DMAC_ACTIVE reset_value) Active Channel and Levels */
+
+#define DMAC_ACTIVE_LVLEX0_Pos 0 /**< \brief (DMAC_ACTIVE) Level 0 Channel Trigger Request Executing */
+#define DMAC_ACTIVE_LVLEX0 (1 << DMAC_ACTIVE_LVLEX0_Pos)
+#define DMAC_ACTIVE_LVLEX1_Pos 1 /**< \brief (DMAC_ACTIVE) Level 1 Channel Trigger Request Executing */
+#define DMAC_ACTIVE_LVLEX1 (1 << DMAC_ACTIVE_LVLEX1_Pos)
+#define DMAC_ACTIVE_LVLEX2_Pos 2 /**< \brief (DMAC_ACTIVE) Level 2 Channel Trigger Request Executing */
+#define DMAC_ACTIVE_LVLEX2 (1 << DMAC_ACTIVE_LVLEX2_Pos)
+#define DMAC_ACTIVE_LVLEX3_Pos 3 /**< \brief (DMAC_ACTIVE) Level 3 Channel Trigger Request Executing */
+#define DMAC_ACTIVE_LVLEX3 (1 << DMAC_ACTIVE_LVLEX3_Pos)
+#define DMAC_ACTIVE_LVLEX_Pos 0 /**< \brief (DMAC_ACTIVE) Level x Channel Trigger Request Executing */
+#define DMAC_ACTIVE_LVLEX_Msk (0xFul << DMAC_ACTIVE_LVLEX_Pos)
+#define DMAC_ACTIVE_LVLEX(value) (DMAC_ACTIVE_LVLEX_Msk & ((value) << DMAC_ACTIVE_LVLEX_Pos))
+#define DMAC_ACTIVE_ID_Pos 8 /**< \brief (DMAC_ACTIVE) Active Channel ID */
+#define DMAC_ACTIVE_ID_Msk (0x1Ful << DMAC_ACTIVE_ID_Pos)
+#define DMAC_ACTIVE_ID(value) (DMAC_ACTIVE_ID_Msk & ((value) << DMAC_ACTIVE_ID_Pos))
+#define DMAC_ACTIVE_ABUSY_Pos 15 /**< \brief (DMAC_ACTIVE) Active Channel Busy */
+#define DMAC_ACTIVE_ABUSY (0x1ul << DMAC_ACTIVE_ABUSY_Pos)
+#define DMAC_ACTIVE_BTCNT_Pos 16 /**< \brief (DMAC_ACTIVE) Active Channel Block Transfer Count */
+#define DMAC_ACTIVE_BTCNT_Msk (0xFFFFul << DMAC_ACTIVE_BTCNT_Pos)
+#define DMAC_ACTIVE_BTCNT(value) (DMAC_ACTIVE_BTCNT_Msk & ((value) << DMAC_ACTIVE_BTCNT_Pos))
+#define DMAC_ACTIVE_MASK 0xFFFF9F0Ful /**< \brief (DMAC_ACTIVE) MASK Register */
+
+/* -------- DMAC_BASEADDR : (DMAC Offset: 0x34) (R/W 32) Descriptor Memory Section Base Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t BASEADDR:32; /*!< bit: 0..31 Descriptor Memory Base Address */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DMAC_BASEADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_BASEADDR_OFFSET 0x34 /**< \brief (DMAC_BASEADDR offset) Descriptor Memory Section Base Address */
+#define DMAC_BASEADDR_RESETVALUE 0x00000000ul /**< \brief (DMAC_BASEADDR reset_value) Descriptor Memory Section Base Address */
+
+#define DMAC_BASEADDR_BASEADDR_Pos 0 /**< \brief (DMAC_BASEADDR) Descriptor Memory Base Address */
+#define DMAC_BASEADDR_BASEADDR_Msk (0xFFFFFFFFul << DMAC_BASEADDR_BASEADDR_Pos)
+#define DMAC_BASEADDR_BASEADDR(value) (DMAC_BASEADDR_BASEADDR_Msk & ((value) << DMAC_BASEADDR_BASEADDR_Pos))
+#define DMAC_BASEADDR_MASK 0xFFFFFFFFul /**< \brief (DMAC_BASEADDR) MASK Register */
+
+/* -------- DMAC_WRBADDR : (DMAC Offset: 0x38) (R/W 32) Write-Back Memory Section Base Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t WRBADDR:32; /*!< bit: 0..31 Write-Back Memory Base Address */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DMAC_WRBADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_WRBADDR_OFFSET 0x38 /**< \brief (DMAC_WRBADDR offset) Write-Back Memory Section Base Address */
+#define DMAC_WRBADDR_RESETVALUE 0x00000000ul /**< \brief (DMAC_WRBADDR reset_value) Write-Back Memory Section Base Address */
+
+#define DMAC_WRBADDR_WRBADDR_Pos 0 /**< \brief (DMAC_WRBADDR) Write-Back Memory Base Address */
+#define DMAC_WRBADDR_WRBADDR_Msk (0xFFFFFFFFul << DMAC_WRBADDR_WRBADDR_Pos)
+#define DMAC_WRBADDR_WRBADDR(value) (DMAC_WRBADDR_WRBADDR_Msk & ((value) << DMAC_WRBADDR_WRBADDR_Pos))
+#define DMAC_WRBADDR_MASK 0xFFFFFFFFul /**< \brief (DMAC_WRBADDR) MASK Register */
+
+/* -------- DMAC_CHID : (DMAC Offset: 0x3F) (R/W 8) Channel ID -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t ID:4; /*!< bit: 0.. 3 Channel ID */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DMAC_CHID_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CHID_OFFSET 0x3F /**< \brief (DMAC_CHID offset) Channel ID */
+#define DMAC_CHID_RESETVALUE 0x00ul /**< \brief (DMAC_CHID reset_value) Channel ID */
+
+#define DMAC_CHID_ID_Pos 0 /**< \brief (DMAC_CHID) Channel ID */
+#define DMAC_CHID_ID_Msk (0xFul << DMAC_CHID_ID_Pos)
+#define DMAC_CHID_ID(value) (DMAC_CHID_ID_Msk & ((value) << DMAC_CHID_ID_Pos))
+#define DMAC_CHID_MASK 0x0Ful /**< \brief (DMAC_CHID) MASK Register */
+
+/* -------- DMAC_CHCTRLA : (DMAC Offset: 0x40) (R/W 8) Channel Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Channel Software Reset */
+ uint8_t ENABLE:1; /*!< bit: 1 Channel Enable */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DMAC_CHCTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CHCTRLA_OFFSET 0x40 /**< \brief (DMAC_CHCTRLA offset) Channel Control A */
+#define DMAC_CHCTRLA_RESETVALUE 0x00ul /**< \brief (DMAC_CHCTRLA reset_value) Channel Control A */
+
+#define DMAC_CHCTRLA_SWRST_Pos 0 /**< \brief (DMAC_CHCTRLA) Channel Software Reset */
+#define DMAC_CHCTRLA_SWRST (0x1ul << DMAC_CHCTRLA_SWRST_Pos)
+#define DMAC_CHCTRLA_ENABLE_Pos 1 /**< \brief (DMAC_CHCTRLA) Channel Enable */
+#define DMAC_CHCTRLA_ENABLE (0x1ul << DMAC_CHCTRLA_ENABLE_Pos)
+#define DMAC_CHCTRLA_MASK 0x03ul /**< \brief (DMAC_CHCTRLA) MASK Register */
+
+/* -------- DMAC_CHCTRLB : (DMAC Offset: 0x44) (R/W 32) Channel Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t EVACT:3; /*!< bit: 0.. 2 Event Input Action */
+ uint32_t EVIE:1; /*!< bit: 3 Channel Event Input Enable */
+ uint32_t EVOE:1; /*!< bit: 4 Channel Event Output Enable */
+ uint32_t LVL:2; /*!< bit: 5.. 6 Channel Arbitration Level */
+ uint32_t :1; /*!< bit: 7 Reserved */
+ uint32_t TRIGSRC:6; /*!< bit: 8..13 Trigger Source */
+ uint32_t :8; /*!< bit: 14..21 Reserved */
+ uint32_t TRIGACT:2; /*!< bit: 22..23 Trigger Action */
+ uint32_t CMD:2; /*!< bit: 24..25 Software Command */
+ uint32_t :6; /*!< bit: 26..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DMAC_CHCTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CHCTRLB_OFFSET 0x44 /**< \brief (DMAC_CHCTRLB offset) Channel Control B */
+#define DMAC_CHCTRLB_RESETVALUE 0x00000000ul /**< \brief (DMAC_CHCTRLB reset_value) Channel Control B */
+
+#define DMAC_CHCTRLB_EVACT_Pos 0 /**< \brief (DMAC_CHCTRLB) Event Input Action */
+#define DMAC_CHCTRLB_EVACT_Msk (0x7ul << DMAC_CHCTRLB_EVACT_Pos)
+#define DMAC_CHCTRLB_EVACT(value) (DMAC_CHCTRLB_EVACT_Msk & ((value) << DMAC_CHCTRLB_EVACT_Pos))
+#define DMAC_CHCTRLB_EVACT_NOACT_Val 0x0ul /**< \brief (DMAC_CHCTRLB) No action */
+#define DMAC_CHCTRLB_EVACT_TRIG_Val 0x1ul /**< \brief (DMAC_CHCTRLB) Transfer and periodic transfer trigger */
+#define DMAC_CHCTRLB_EVACT_CTRIG_Val 0x2ul /**< \brief (DMAC_CHCTRLB) Conditional transfer trigger */
+#define DMAC_CHCTRLB_EVACT_CBLOCK_Val 0x3ul /**< \brief (DMAC_CHCTRLB) Conditional block transfer */
+#define DMAC_CHCTRLB_EVACT_SUSPEND_Val 0x4ul /**< \brief (DMAC_CHCTRLB) Channel suspend operation */
+#define DMAC_CHCTRLB_EVACT_RESUME_Val 0x5ul /**< \brief (DMAC_CHCTRLB) Channel resume operation */
+#define DMAC_CHCTRLB_EVACT_SSKIP_Val 0x6ul /**< \brief (DMAC_CHCTRLB) Skip next block suspend action */
+#define DMAC_CHCTRLB_EVACT_NOACT (DMAC_CHCTRLB_EVACT_NOACT_Val << DMAC_CHCTRLB_EVACT_Pos)
+#define DMAC_CHCTRLB_EVACT_TRIG (DMAC_CHCTRLB_EVACT_TRIG_Val << DMAC_CHCTRLB_EVACT_Pos)
+#define DMAC_CHCTRLB_EVACT_CTRIG (DMAC_CHCTRLB_EVACT_CTRIG_Val << DMAC_CHCTRLB_EVACT_Pos)
+#define DMAC_CHCTRLB_EVACT_CBLOCK (DMAC_CHCTRLB_EVACT_CBLOCK_Val << DMAC_CHCTRLB_EVACT_Pos)
+#define DMAC_CHCTRLB_EVACT_SUSPEND (DMAC_CHCTRLB_EVACT_SUSPEND_Val << DMAC_CHCTRLB_EVACT_Pos)
+#define DMAC_CHCTRLB_EVACT_RESUME (DMAC_CHCTRLB_EVACT_RESUME_Val << DMAC_CHCTRLB_EVACT_Pos)
+#define DMAC_CHCTRLB_EVACT_SSKIP (DMAC_CHCTRLB_EVACT_SSKIP_Val << DMAC_CHCTRLB_EVACT_Pos)
+#define DMAC_CHCTRLB_EVIE_Pos 3 /**< \brief (DMAC_CHCTRLB) Channel Event Input Enable */
+#define DMAC_CHCTRLB_EVIE (0x1ul << DMAC_CHCTRLB_EVIE_Pos)
+#define DMAC_CHCTRLB_EVOE_Pos 4 /**< \brief (DMAC_CHCTRLB) Channel Event Output Enable */
+#define DMAC_CHCTRLB_EVOE (0x1ul << DMAC_CHCTRLB_EVOE_Pos)
+#define DMAC_CHCTRLB_LVL_Pos 5 /**< \brief (DMAC_CHCTRLB) Channel Arbitration Level */
+#define DMAC_CHCTRLB_LVL_Msk (0x3ul << DMAC_CHCTRLB_LVL_Pos)
+#define DMAC_CHCTRLB_LVL(value) (DMAC_CHCTRLB_LVL_Msk & ((value) << DMAC_CHCTRLB_LVL_Pos))
+#define DMAC_CHCTRLB_LVL_LVL0_Val 0x0ul /**< \brief (DMAC_CHCTRLB) Channel Priority Level 0 */
+#define DMAC_CHCTRLB_LVL_LVL1_Val 0x1ul /**< \brief (DMAC_CHCTRLB) Channel Priority Level 1 */
+#define DMAC_CHCTRLB_LVL_LVL2_Val 0x2ul /**< \brief (DMAC_CHCTRLB) Channel Priority Level 2 */
+#define DMAC_CHCTRLB_LVL_LVL3_Val 0x3ul /**< \brief (DMAC_CHCTRLB) Channel Priority Level 3 */
+#define DMAC_CHCTRLB_LVL_LVL0 (DMAC_CHCTRLB_LVL_LVL0_Val << DMAC_CHCTRLB_LVL_Pos)
+#define DMAC_CHCTRLB_LVL_LVL1 (DMAC_CHCTRLB_LVL_LVL1_Val << DMAC_CHCTRLB_LVL_Pos)
+#define DMAC_CHCTRLB_LVL_LVL2 (DMAC_CHCTRLB_LVL_LVL2_Val << DMAC_CHCTRLB_LVL_Pos)
+#define DMAC_CHCTRLB_LVL_LVL3 (DMAC_CHCTRLB_LVL_LVL3_Val << DMAC_CHCTRLB_LVL_Pos)
+#define DMAC_CHCTRLB_TRIGSRC_Pos 8 /**< \brief (DMAC_CHCTRLB) Trigger Source */
+#define DMAC_CHCTRLB_TRIGSRC_Msk (0x3Ful << DMAC_CHCTRLB_TRIGSRC_Pos)
+#define DMAC_CHCTRLB_TRIGSRC(value) (DMAC_CHCTRLB_TRIGSRC_Msk & ((value) << DMAC_CHCTRLB_TRIGSRC_Pos))
+#define DMAC_CHCTRLB_TRIGSRC_DISABLE_Val 0x0ul /**< \brief (DMAC_CHCTRLB) Only software/event triggers */
+#define DMAC_CHCTRLB_TRIGSRC_DISABLE (DMAC_CHCTRLB_TRIGSRC_DISABLE_Val << DMAC_CHCTRLB_TRIGSRC_Pos)
+#define DMAC_CHCTRLB_TRIGACT_Pos 22 /**< \brief (DMAC_CHCTRLB) Trigger Action */
+#define DMAC_CHCTRLB_TRIGACT_Msk (0x3ul << DMAC_CHCTRLB_TRIGACT_Pos)
+#define DMAC_CHCTRLB_TRIGACT(value) (DMAC_CHCTRLB_TRIGACT_Msk & ((value) << DMAC_CHCTRLB_TRIGACT_Pos))
+#define DMAC_CHCTRLB_TRIGACT_BLOCK_Val 0x0ul /**< \brief (DMAC_CHCTRLB) One trigger required for each block transfer */
+#define DMAC_CHCTRLB_TRIGACT_BEAT_Val 0x2ul /**< \brief (DMAC_CHCTRLB) One trigger required for each beat transfer */
+#define DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val 0x3ul /**< \brief (DMAC_CHCTRLB) One trigger required for each transaction */
+#define DMAC_CHCTRLB_TRIGACT_BLOCK (DMAC_CHCTRLB_TRIGACT_BLOCK_Val << DMAC_CHCTRLB_TRIGACT_Pos)
+#define DMAC_CHCTRLB_TRIGACT_BEAT (DMAC_CHCTRLB_TRIGACT_BEAT_Val << DMAC_CHCTRLB_TRIGACT_Pos)
+#define DMAC_CHCTRLB_TRIGACT_TRANSACTION (DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val << DMAC_CHCTRLB_TRIGACT_Pos)
+#define DMAC_CHCTRLB_CMD_Pos 24 /**< \brief (DMAC_CHCTRLB) Software Command */
+#define DMAC_CHCTRLB_CMD_Msk (0x3ul << DMAC_CHCTRLB_CMD_Pos)
+#define DMAC_CHCTRLB_CMD(value) (DMAC_CHCTRLB_CMD_Msk & ((value) << DMAC_CHCTRLB_CMD_Pos))
+#define DMAC_CHCTRLB_CMD_NOACT_Val 0x0ul /**< \brief (DMAC_CHCTRLB) No action */
+#define DMAC_CHCTRLB_CMD_SUSPEND_Val 0x1ul /**< \brief (DMAC_CHCTRLB) Channel suspend operation */
+#define DMAC_CHCTRLB_CMD_RESUME_Val 0x2ul /**< \brief (DMAC_CHCTRLB) Channel resume operation */
+#define DMAC_CHCTRLB_CMD_NOACT (DMAC_CHCTRLB_CMD_NOACT_Val << DMAC_CHCTRLB_CMD_Pos)
+#define DMAC_CHCTRLB_CMD_SUSPEND (DMAC_CHCTRLB_CMD_SUSPEND_Val << DMAC_CHCTRLB_CMD_Pos)
+#define DMAC_CHCTRLB_CMD_RESUME (DMAC_CHCTRLB_CMD_RESUME_Val << DMAC_CHCTRLB_CMD_Pos)
+#define DMAC_CHCTRLB_MASK 0x03C03F7Ful /**< \brief (DMAC_CHCTRLB) MASK Register */
+
+/* -------- DMAC_CHINTENCLR : (DMAC Offset: 0x4C) (R/W 8) Channel Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */
+ uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */
+ uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DMAC_CHINTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CHINTENCLR_OFFSET 0x4C /**< \brief (DMAC_CHINTENCLR offset) Channel Interrupt Enable Clear */
+#define DMAC_CHINTENCLR_RESETVALUE 0x00ul /**< \brief (DMAC_CHINTENCLR reset_value) Channel Interrupt Enable Clear */
+
+#define DMAC_CHINTENCLR_TERR_Pos 0 /**< \brief (DMAC_CHINTENCLR) Channel Transfer Error Interrupt Enable */
+#define DMAC_CHINTENCLR_TERR (0x1ul << DMAC_CHINTENCLR_TERR_Pos)
+#define DMAC_CHINTENCLR_TCMPL_Pos 1 /**< \brief (DMAC_CHINTENCLR) Channel Transfer Complete Interrupt Enable */
+#define DMAC_CHINTENCLR_TCMPL (0x1ul << DMAC_CHINTENCLR_TCMPL_Pos)
+#define DMAC_CHINTENCLR_SUSP_Pos 2 /**< \brief (DMAC_CHINTENCLR) Channel Suspend Interrupt Enable */
+#define DMAC_CHINTENCLR_SUSP (0x1ul << DMAC_CHINTENCLR_SUSP_Pos)
+#define DMAC_CHINTENCLR_MASK 0x07ul /**< \brief (DMAC_CHINTENCLR) MASK Register */
+
+/* -------- DMAC_CHINTENSET : (DMAC Offset: 0x4D) (R/W 8) Channel Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */
+ uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */
+ uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DMAC_CHINTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CHINTENSET_OFFSET 0x4D /**< \brief (DMAC_CHINTENSET offset) Channel Interrupt Enable Set */
+#define DMAC_CHINTENSET_RESETVALUE 0x00ul /**< \brief (DMAC_CHINTENSET reset_value) Channel Interrupt Enable Set */
+
+#define DMAC_CHINTENSET_TERR_Pos 0 /**< \brief (DMAC_CHINTENSET) Channel Transfer Error Interrupt Enable */
+#define DMAC_CHINTENSET_TERR (0x1ul << DMAC_CHINTENSET_TERR_Pos)
+#define DMAC_CHINTENSET_TCMPL_Pos 1 /**< \brief (DMAC_CHINTENSET) Channel Transfer Complete Interrupt Enable */
+#define DMAC_CHINTENSET_TCMPL (0x1ul << DMAC_CHINTENSET_TCMPL_Pos)
+#define DMAC_CHINTENSET_SUSP_Pos 2 /**< \brief (DMAC_CHINTENSET) Channel Suspend Interrupt Enable */
+#define DMAC_CHINTENSET_SUSP (0x1ul << DMAC_CHINTENSET_SUSP_Pos)
+#define DMAC_CHINTENSET_MASK 0x07ul /**< \brief (DMAC_CHINTENSET) MASK Register */
+
+/* -------- DMAC_CHINTFLAG : (DMAC Offset: 0x4E) (R/W 8) Channel Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error */
+ __I uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete */
+ __I uint8_t SUSP:1; /*!< bit: 2 Channel Suspend */
+ __I uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DMAC_CHINTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CHINTFLAG_OFFSET 0x4E /**< \brief (DMAC_CHINTFLAG offset) Channel Interrupt Flag Status and Clear */
+#define DMAC_CHINTFLAG_RESETVALUE 0x00ul /**< \brief (DMAC_CHINTFLAG reset_value) Channel Interrupt Flag Status and Clear */
+
+#define DMAC_CHINTFLAG_TERR_Pos 0 /**< \brief (DMAC_CHINTFLAG) Channel Transfer Error */
+#define DMAC_CHINTFLAG_TERR (0x1ul << DMAC_CHINTFLAG_TERR_Pos)
+#define DMAC_CHINTFLAG_TCMPL_Pos 1 /**< \brief (DMAC_CHINTFLAG) Channel Transfer Complete */
+#define DMAC_CHINTFLAG_TCMPL (0x1ul << DMAC_CHINTFLAG_TCMPL_Pos)
+#define DMAC_CHINTFLAG_SUSP_Pos 2 /**< \brief (DMAC_CHINTFLAG) Channel Suspend */
+#define DMAC_CHINTFLAG_SUSP (0x1ul << DMAC_CHINTFLAG_SUSP_Pos)
+#define DMAC_CHINTFLAG_MASK 0x07ul /**< \brief (DMAC_CHINTFLAG) MASK Register */
+
+/* -------- DMAC_CHSTATUS : (DMAC Offset: 0x4F) (R/ 8) Channel Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t PEND:1; /*!< bit: 0 Channel Pending */
+ uint8_t BUSY:1; /*!< bit: 1 Channel Busy */
+ uint8_t FERR:1; /*!< bit: 2 Channel Fetch Error */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DMAC_CHSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_CHSTATUS_OFFSET 0x4F /**< \brief (DMAC_CHSTATUS offset) Channel Status */
+#define DMAC_CHSTATUS_RESETVALUE 0x00ul /**< \brief (DMAC_CHSTATUS reset_value) Channel Status */
+
+#define DMAC_CHSTATUS_PEND_Pos 0 /**< \brief (DMAC_CHSTATUS) Channel Pending */
+#define DMAC_CHSTATUS_PEND (0x1ul << DMAC_CHSTATUS_PEND_Pos)
+#define DMAC_CHSTATUS_BUSY_Pos 1 /**< \brief (DMAC_CHSTATUS) Channel Busy */
+#define DMAC_CHSTATUS_BUSY (0x1ul << DMAC_CHSTATUS_BUSY_Pos)
+#define DMAC_CHSTATUS_FERR_Pos 2 /**< \brief (DMAC_CHSTATUS) Channel Fetch Error */
+#define DMAC_CHSTATUS_FERR (0x1ul << DMAC_CHSTATUS_FERR_Pos)
+#define DMAC_CHSTATUS_MASK 0x07ul /**< \brief (DMAC_CHSTATUS) MASK Register */
+
+/* -------- DMAC_BTCTRL : (DMAC Offset: 0x00) (R/W 16) Block Transfer Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t VALID:1; /*!< bit: 0 Descriptor Valid */
+ uint16_t EVOSEL:2; /*!< bit: 1.. 2 Event Output Selection */
+ uint16_t BLOCKACT:2; /*!< bit: 3.. 4 Block Action */
+ uint16_t :3; /*!< bit: 5.. 7 Reserved */
+ uint16_t BEATSIZE:2; /*!< bit: 8.. 9 Beat Size */
+ uint16_t SRCINC:1; /*!< bit: 10 Source Address Increment Enable */
+ uint16_t DSTINC:1; /*!< bit: 11 Destination Address Increment Enable */
+ uint16_t STEPSEL:1; /*!< bit: 12 Step Selection */
+ uint16_t STEPSIZE:3; /*!< bit: 13..15 Address Increment Step Size */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} DMAC_BTCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_BTCTRL_OFFSET 0x00 /**< \brief (DMAC_BTCTRL offset) Block Transfer Control */
+#define DMAC_BTCTRL_RESETVALUE 0x0000ul /**< \brief (DMAC_BTCTRL reset_value) Block Transfer Control */
+
+#define DMAC_BTCTRL_VALID_Pos 0 /**< \brief (DMAC_BTCTRL) Descriptor Valid */
+#define DMAC_BTCTRL_VALID (0x1ul << DMAC_BTCTRL_VALID_Pos)
+#define DMAC_BTCTRL_EVOSEL_Pos 1 /**< \brief (DMAC_BTCTRL) Event Output Selection */
+#define DMAC_BTCTRL_EVOSEL_Msk (0x3ul << DMAC_BTCTRL_EVOSEL_Pos)
+#define DMAC_BTCTRL_EVOSEL(value) (DMAC_BTCTRL_EVOSEL_Msk & ((value) << DMAC_BTCTRL_EVOSEL_Pos))
+#define DMAC_BTCTRL_EVOSEL_DISABLE_Val 0x0ul /**< \brief (DMAC_BTCTRL) Event generation disabled */
+#define DMAC_BTCTRL_EVOSEL_BLOCK_Val 0x1ul /**< \brief (DMAC_BTCTRL) Event strobe when block transfer complete */
+#define DMAC_BTCTRL_EVOSEL_BEAT_Val 0x3ul /**< \brief (DMAC_BTCTRL) Event strobe when beat transfer complete */
+#define DMAC_BTCTRL_EVOSEL_DISABLE (DMAC_BTCTRL_EVOSEL_DISABLE_Val << DMAC_BTCTRL_EVOSEL_Pos)
+#define DMAC_BTCTRL_EVOSEL_BLOCK (DMAC_BTCTRL_EVOSEL_BLOCK_Val << DMAC_BTCTRL_EVOSEL_Pos)
+#define DMAC_BTCTRL_EVOSEL_BEAT (DMAC_BTCTRL_EVOSEL_BEAT_Val << DMAC_BTCTRL_EVOSEL_Pos)
+#define DMAC_BTCTRL_BLOCKACT_Pos 3 /**< \brief (DMAC_BTCTRL) Block Action */
+#define DMAC_BTCTRL_BLOCKACT_Msk (0x3ul << DMAC_BTCTRL_BLOCKACT_Pos)
+#define DMAC_BTCTRL_BLOCKACT(value) (DMAC_BTCTRL_BLOCKACT_Msk & ((value) << DMAC_BTCTRL_BLOCKACT_Pos))
+#define DMAC_BTCTRL_BLOCKACT_NOACT_Val 0x0ul /**< \brief (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction */
+#define DMAC_BTCTRL_BLOCKACT_INT_Val 0x1ul /**< \brief (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction and block interrupt */
+#define DMAC_BTCTRL_BLOCKACT_SUSPEND_Val 0x2ul /**< \brief (DMAC_BTCTRL) Channel suspend operation is completed */
+#define DMAC_BTCTRL_BLOCKACT_BOTH_Val 0x3ul /**< \brief (DMAC_BTCTRL) Both channel suspend operation and block interrupt */
+#define DMAC_BTCTRL_BLOCKACT_NOACT (DMAC_BTCTRL_BLOCKACT_NOACT_Val << DMAC_BTCTRL_BLOCKACT_Pos)
+#define DMAC_BTCTRL_BLOCKACT_INT (DMAC_BTCTRL_BLOCKACT_INT_Val << DMAC_BTCTRL_BLOCKACT_Pos)
+#define DMAC_BTCTRL_BLOCKACT_SUSPEND (DMAC_BTCTRL_BLOCKACT_SUSPEND_Val << DMAC_BTCTRL_BLOCKACT_Pos)
+#define DMAC_BTCTRL_BLOCKACT_BOTH (DMAC_BTCTRL_BLOCKACT_BOTH_Val << DMAC_BTCTRL_BLOCKACT_Pos)
+#define DMAC_BTCTRL_BEATSIZE_Pos 8 /**< \brief (DMAC_BTCTRL) Beat Size */
+#define DMAC_BTCTRL_BEATSIZE_Msk (0x3ul << DMAC_BTCTRL_BEATSIZE_Pos)
+#define DMAC_BTCTRL_BEATSIZE(value) (DMAC_BTCTRL_BEATSIZE_Msk & ((value) << DMAC_BTCTRL_BEATSIZE_Pos))
+#define DMAC_BTCTRL_BEATSIZE_BYTE_Val 0x0ul /**< \brief (DMAC_BTCTRL) 8-bit bus transfer */
+#define DMAC_BTCTRL_BEATSIZE_HWORD_Val 0x1ul /**< \brief (DMAC_BTCTRL) 16-bit bus transfer */
+#define DMAC_BTCTRL_BEATSIZE_WORD_Val 0x2ul /**< \brief (DMAC_BTCTRL) 32-bit bus transfer */
+#define DMAC_BTCTRL_BEATSIZE_BYTE (DMAC_BTCTRL_BEATSIZE_BYTE_Val << DMAC_BTCTRL_BEATSIZE_Pos)
+#define DMAC_BTCTRL_BEATSIZE_HWORD (DMAC_BTCTRL_BEATSIZE_HWORD_Val << DMAC_BTCTRL_BEATSIZE_Pos)
+#define DMAC_BTCTRL_BEATSIZE_WORD (DMAC_BTCTRL_BEATSIZE_WORD_Val << DMAC_BTCTRL_BEATSIZE_Pos)
+#define DMAC_BTCTRL_SRCINC_Pos 10 /**< \brief (DMAC_BTCTRL) Source Address Increment Enable */
+#define DMAC_BTCTRL_SRCINC (0x1ul << DMAC_BTCTRL_SRCINC_Pos)
+#define DMAC_BTCTRL_DSTINC_Pos 11 /**< \brief (DMAC_BTCTRL) Destination Address Increment Enable */
+#define DMAC_BTCTRL_DSTINC (0x1ul << DMAC_BTCTRL_DSTINC_Pos)
+#define DMAC_BTCTRL_STEPSEL_Pos 12 /**< \brief (DMAC_BTCTRL) Step Selection */
+#define DMAC_BTCTRL_STEPSEL (0x1ul << DMAC_BTCTRL_STEPSEL_Pos)
+#define DMAC_BTCTRL_STEPSEL_DST_Val 0x0ul /**< \brief (DMAC_BTCTRL) Step size settings apply to the destination address */
+#define DMAC_BTCTRL_STEPSEL_SRC_Val 0x1ul /**< \brief (DMAC_BTCTRL) Step size settings apply to the source address */
+#define DMAC_BTCTRL_STEPSEL_DST (DMAC_BTCTRL_STEPSEL_DST_Val << DMAC_BTCTRL_STEPSEL_Pos)
+#define DMAC_BTCTRL_STEPSEL_SRC (DMAC_BTCTRL_STEPSEL_SRC_Val << DMAC_BTCTRL_STEPSEL_Pos)
+#define DMAC_BTCTRL_STEPSIZE_Pos 13 /**< \brief (DMAC_BTCTRL) Address Increment Step Size */
+#define DMAC_BTCTRL_STEPSIZE_Msk (0x7ul << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_STEPSIZE(value) (DMAC_BTCTRL_STEPSIZE_Msk & ((value) << DMAC_BTCTRL_STEPSIZE_Pos))
+#define DMAC_BTCTRL_STEPSIZE_X1_Val 0x0ul /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1<<BEATSIZE) * 1 */
+#define DMAC_BTCTRL_STEPSIZE_X2_Val 0x1ul /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1<<BEATSIZE) * 2 */
+#define DMAC_BTCTRL_STEPSIZE_X4_Val 0x2ul /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1<<BEATSIZE) * 4 */
+#define DMAC_BTCTRL_STEPSIZE_X8_Val 0x3ul /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1<<BEATSIZE) * 8 */
+#define DMAC_BTCTRL_STEPSIZE_X16_Val 0x4ul /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1<<BEATSIZE) * 16 */
+#define DMAC_BTCTRL_STEPSIZE_X32_Val 0x5ul /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1<<BEATSIZE) * 32 */
+#define DMAC_BTCTRL_STEPSIZE_X64_Val 0x6ul /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1<<BEATSIZE) * 64 */
+#define DMAC_BTCTRL_STEPSIZE_X128_Val 0x7ul /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1<<BEATSIZE) * 128 */
+#define DMAC_BTCTRL_STEPSIZE_X1 (DMAC_BTCTRL_STEPSIZE_X1_Val << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_STEPSIZE_X2 (DMAC_BTCTRL_STEPSIZE_X2_Val << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_STEPSIZE_X4 (DMAC_BTCTRL_STEPSIZE_X4_Val << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_STEPSIZE_X8 (DMAC_BTCTRL_STEPSIZE_X8_Val << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_STEPSIZE_X16 (DMAC_BTCTRL_STEPSIZE_X16_Val << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_STEPSIZE_X32 (DMAC_BTCTRL_STEPSIZE_X32_Val << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_STEPSIZE_X64 (DMAC_BTCTRL_STEPSIZE_X64_Val << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_STEPSIZE_X128 (DMAC_BTCTRL_STEPSIZE_X128_Val << DMAC_BTCTRL_STEPSIZE_Pos)
+#define DMAC_BTCTRL_MASK 0xFF1Ful /**< \brief (DMAC_BTCTRL) MASK Register */
+
+/* -------- DMAC_BTCNT : (DMAC Offset: 0x02) (R/W 16) Block Transfer Count -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t BTCNT:16; /*!< bit: 0..15 Block Transfer Count */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} DMAC_BTCNT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_BTCNT_OFFSET 0x02 /**< \brief (DMAC_BTCNT offset) Block Transfer Count */
+
+#define DMAC_BTCNT_BTCNT_Pos 0 /**< \brief (DMAC_BTCNT) Block Transfer Count */
+#define DMAC_BTCNT_BTCNT_Msk (0xFFFFul << DMAC_BTCNT_BTCNT_Pos)
+#define DMAC_BTCNT_BTCNT(value) (DMAC_BTCNT_BTCNT_Msk & ((value) << DMAC_BTCNT_BTCNT_Pos))
+#define DMAC_BTCNT_MASK 0xFFFFul /**< \brief (DMAC_BTCNT) MASK Register */
+
+/* -------- DMAC_SRCADDR : (DMAC Offset: 0x04) (R/W 32) Block Transfer Source Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SRCADDR:32; /*!< bit: 0..31 Transfer Source Address */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DMAC_SRCADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_SRCADDR_OFFSET 0x04 /**< \brief (DMAC_SRCADDR offset) Block Transfer Source Address */
+
+#define DMAC_SRCADDR_SRCADDR_Pos 0 /**< \brief (DMAC_SRCADDR) Transfer Source Address */
+#define DMAC_SRCADDR_SRCADDR_Msk (0xFFFFFFFFul << DMAC_SRCADDR_SRCADDR_Pos)
+#define DMAC_SRCADDR_SRCADDR(value) (DMAC_SRCADDR_SRCADDR_Msk & ((value) << DMAC_SRCADDR_SRCADDR_Pos))
+#define DMAC_SRCADDR_MASK 0xFFFFFFFFul /**< \brief (DMAC_SRCADDR) MASK Register */
+
+/* -------- DMAC_DSTADDR : (DMAC Offset: 0x08) (R/W 32) Block Transfer Destination Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DSTADDR:32; /*!< bit: 0..31 Transfer Destination Address */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DMAC_DSTADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_DSTADDR_OFFSET 0x08 /**< \brief (DMAC_DSTADDR offset) Block Transfer Destination Address */
+
+#define DMAC_DSTADDR_DSTADDR_Pos 0 /**< \brief (DMAC_DSTADDR) Transfer Destination Address */
+#define DMAC_DSTADDR_DSTADDR_Msk (0xFFFFFFFFul << DMAC_DSTADDR_DSTADDR_Pos)
+#define DMAC_DSTADDR_DSTADDR(value) (DMAC_DSTADDR_DSTADDR_Msk & ((value) << DMAC_DSTADDR_DSTADDR_Pos))
+#define DMAC_DSTADDR_MASK 0xFFFFFFFFul /**< \brief (DMAC_DSTADDR) MASK Register */
+
+/* -------- DMAC_DESCADDR : (DMAC Offset: 0x0C) (R/W 32) Next Descriptor Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DESCADDR:32; /*!< bit: 0..31 Next Descriptor Address */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DMAC_DESCADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DMAC_DESCADDR_OFFSET 0x0C /**< \brief (DMAC_DESCADDR offset) Next Descriptor Address */
+
+#define DMAC_DESCADDR_DESCADDR_Pos 0 /**< \brief (DMAC_DESCADDR) Next Descriptor Address */
+#define DMAC_DESCADDR_DESCADDR_Msk (0xFFFFFFFFul << DMAC_DESCADDR_DESCADDR_Pos)
+#define DMAC_DESCADDR_DESCADDR(value) (DMAC_DESCADDR_DESCADDR_Msk & ((value) << DMAC_DESCADDR_DESCADDR_Pos))
+#define DMAC_DESCADDR_MASK 0xFFFFFFFFul /**< \brief (DMAC_DESCADDR) MASK Register */
+
+/** \brief DMAC APB hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO DMAC_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) Control */
+ __IO DMAC_CRCCTRL_Type CRCCTRL; /**< \brief Offset: 0x02 (R/W 16) CRC Control */
+ __IO DMAC_CRCDATAIN_Type CRCDATAIN; /**< \brief Offset: 0x04 (R/W 32) CRC Data Input */
+ __IO DMAC_CRCCHKSUM_Type CRCCHKSUM; /**< \brief Offset: 0x08 (R/W 32) CRC Checksum */
+ __IO DMAC_CRCSTATUS_Type CRCSTATUS; /**< \brief Offset: 0x0C (R/W 8) CRC Status */
+ __IO DMAC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0D (R/W 8) Debug Control */
+ __IO DMAC_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x0E (R/W 8) QOS Control */
+ RoReg8 Reserved1[0x1];
+ __IO DMAC_SWTRIGCTRL_Type SWTRIGCTRL; /**< \brief Offset: 0x10 (R/W 32) Software Trigger Control */
+ __IO DMAC_PRICTRL0_Type PRICTRL0; /**< \brief Offset: 0x14 (R/W 32) Priority Control 0 */
+ RoReg8 Reserved2[0x8];
+ __IO DMAC_INTPEND_Type INTPEND; /**< \brief Offset: 0x20 (R/W 16) Interrupt Pending */
+ RoReg8 Reserved3[0x2];
+ __I DMAC_INTSTATUS_Type INTSTATUS; /**< \brief Offset: 0x24 (R/ 32) Interrupt Status */
+ __I DMAC_BUSYCH_Type BUSYCH; /**< \brief Offset: 0x28 (R/ 32) Busy Channels */
+ __I DMAC_PENDCH_Type PENDCH; /**< \brief Offset: 0x2C (R/ 32) Pending Channels */
+ __I DMAC_ACTIVE_Type ACTIVE; /**< \brief Offset: 0x30 (R/ 32) Active Channel and Levels */
+ __IO DMAC_BASEADDR_Type BASEADDR; /**< \brief Offset: 0x34 (R/W 32) Descriptor Memory Section Base Address */
+ __IO DMAC_WRBADDR_Type WRBADDR; /**< \brief Offset: 0x38 (R/W 32) Write-Back Memory Section Base Address */
+ RoReg8 Reserved4[0x3];
+ __IO DMAC_CHID_Type CHID; /**< \brief Offset: 0x3F (R/W 8) Channel ID */
+ __IO DMAC_CHCTRLA_Type CHCTRLA; /**< \brief Offset: 0x40 (R/W 8) Channel Control A */
+ RoReg8 Reserved5[0x3];
+ __IO DMAC_CHCTRLB_Type CHCTRLB; /**< \brief Offset: 0x44 (R/W 32) Channel Control B */
+ RoReg8 Reserved6[0x4];
+ __IO DMAC_CHINTENCLR_Type CHINTENCLR; /**< \brief Offset: 0x4C (R/W 8) Channel Interrupt Enable Clear */
+ __IO DMAC_CHINTENSET_Type CHINTENSET; /**< \brief Offset: 0x4D (R/W 8) Channel Interrupt Enable Set */
+ __IO DMAC_CHINTFLAG_Type CHINTFLAG; /**< \brief Offset: 0x4E (R/W 8) Channel Interrupt Flag Status and Clear */
+ __I DMAC_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x4F (R/ 8) Channel Status */
+} Dmac;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief DMAC Descriptor SRAM registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO DMAC_BTCTRL_Type BTCTRL; /**< \brief Offset: 0x00 (R/W 16) Block Transfer Control */
+ __IO DMAC_BTCNT_Type BTCNT; /**< \brief Offset: 0x02 (R/W 16) Block Transfer Count */
+ __IO DMAC_SRCADDR_Type SRCADDR; /**< \brief Offset: 0x04 (R/W 32) Block Transfer Source Address */
+ __IO DMAC_DSTADDR_Type DSTADDR; /**< \brief Offset: 0x08 (R/W 32) Block Transfer Destination Address */
+ __IO DMAC_DESCADDR_Type DESCADDR; /**< \brief Offset: 0x0C (R/W 32) Next Descriptor Address */
+} DmacDescriptor
+#ifdef __GNUC__
+ __attribute__ ((aligned (8)))
+#endif
+;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SECTION_DMAC_DESCRIPTOR
+
+/*@}*/
+
+#endif /* _SAMD21_DMAC_COMPONENT_ */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/component/dsu.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/component/dsu.h
new file mode 100644
index 0000000000000000000000000000000000000000..b248d6ec11a6b80b0ad640cd897afe6ce2bc9b83
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/component/dsu.h
@@ -0,0 +1,551 @@
+/**
+ * \file
+ *
+ * \brief Component description for DSU
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_DSU_COMPONENT_
+#define _SAMD21_DSU_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR DSU */
+/* ========================================================================== */
+/** \addtogroup SAMD21_DSU Device Service Unit */
+/*@{*/
+
+#define DSU_U2209
+#define REV_DSU 0x200
+
+/* -------- DSU_CTRL : (DSU Offset: 0x0000) ( /W 8) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t :1; /*!< bit: 1 Reserved */
+ uint8_t CRC:1; /*!< bit: 2 32-bit Cyclic Redundancy Check */
+ uint8_t MBIST:1; /*!< bit: 3 Memory Built-In Self-Test */
+ uint8_t CE:1; /*!< bit: 4 Chip Erase */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DSU_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_CTRL_OFFSET 0x0000 /**< \brief (DSU_CTRL offset) Control */
+#define DSU_CTRL_RESETVALUE 0x00ul /**< \brief (DSU_CTRL reset_value) Control */
+
+#define DSU_CTRL_SWRST_Pos 0 /**< \brief (DSU_CTRL) Software Reset */
+#define DSU_CTRL_SWRST (0x1ul << DSU_CTRL_SWRST_Pos)
+#define DSU_CTRL_CRC_Pos 2 /**< \brief (DSU_CTRL) 32-bit Cyclic Redundancy Check */
+#define DSU_CTRL_CRC (0x1ul << DSU_CTRL_CRC_Pos)
+#define DSU_CTRL_MBIST_Pos 3 /**< \brief (DSU_CTRL) Memory Built-In Self-Test */
+#define DSU_CTRL_MBIST (0x1ul << DSU_CTRL_MBIST_Pos)
+#define DSU_CTRL_CE_Pos 4 /**< \brief (DSU_CTRL) Chip Erase */
+#define DSU_CTRL_CE (0x1ul << DSU_CTRL_CE_Pos)
+#define DSU_CTRL_MASK 0x1Dul /**< \brief (DSU_CTRL) MASK Register */
+
+/* -------- DSU_STATUSA : (DSU Offset: 0x0001) (R/W 8) Status A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DONE:1; /*!< bit: 0 Done */
+ uint8_t CRSTEXT:1; /*!< bit: 1 CPU Reset Phase Extension */
+ uint8_t BERR:1; /*!< bit: 2 Bus Error */
+ uint8_t FAIL:1; /*!< bit: 3 Failure */
+ uint8_t PERR:1; /*!< bit: 4 Protection Error */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} DSU_STATUSA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_STATUSA_OFFSET 0x0001 /**< \brief (DSU_STATUSA offset) Status A */
+#define DSU_STATUSA_RESETVALUE 0x00ul /**< \brief (DSU_STATUSA reset_value) Status A */
+
+#define DSU_STATUSA_DONE_Pos 0 /**< \brief (DSU_STATUSA) Done */
+#define DSU_STATUSA_DONE (0x1ul << DSU_STATUSA_DONE_Pos)
+#define DSU_STATUSA_CRSTEXT_Pos 1 /**< \brief (DSU_STATUSA) CPU Reset Phase Extension */
+#define DSU_STATUSA_CRSTEXT (0x1ul << DSU_STATUSA_CRSTEXT_Pos)
+#define DSU_STATUSA_BERR_Pos 2 /**< \brief (DSU_STATUSA) Bus Error */
+#define DSU_STATUSA_BERR (0x1ul << DSU_STATUSA_BERR_Pos)
+#define DSU_STATUSA_FAIL_Pos 3 /**< \brief (DSU_STATUSA) Failure */
+#define DSU_STATUSA_FAIL (0x1ul << DSU_STATUSA_FAIL_Pos)
+#define DSU_STATUSA_PERR_Pos 4 /**< \brief (DSU_STATUSA) Protection Error */
+#define DSU_STATUSA_PERR (0x1ul << DSU_STATUSA_PERR_Pos)
+#define DSU_STATUSA_MASK 0x1Ful /**< \brief (DSU_STATUSA) MASK Register */
+
+/* -------- DSU_STATUSB : (DSU Offset: 0x0002) (R/ 8) Status B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t PROT:1; /*!< bit: 0 Protected */
+ uint8_t DBGPRES:1; /*!< bit: 1 Debugger Present */
+ uint8_t DCCD0:1; /*!< bit: 2 Debug Communication Channel 0 Dirty */
+ uint8_t DCCD1:1; /*!< bit: 3 Debug Communication Channel 1 Dirty */
+ uint8_t HPE:1; /*!< bit: 4 Hot-Plugging Enable */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t :2; /*!< bit: 0.. 1 Reserved */
+ uint8_t DCCD:2; /*!< bit: 2.. 3 Debug Communication Channel x Dirty */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} DSU_STATUSB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_STATUSB_OFFSET 0x0002 /**< \brief (DSU_STATUSB offset) Status B */
+#define DSU_STATUSB_RESETVALUE 0x10ul /**< \brief (DSU_STATUSB reset_value) Status B */
+
+#define DSU_STATUSB_PROT_Pos 0 /**< \brief (DSU_STATUSB) Protected */
+#define DSU_STATUSB_PROT (0x1ul << DSU_STATUSB_PROT_Pos)
+#define DSU_STATUSB_DBGPRES_Pos 1 /**< \brief (DSU_STATUSB) Debugger Present */
+#define DSU_STATUSB_DBGPRES (0x1ul << DSU_STATUSB_DBGPRES_Pos)
+#define DSU_STATUSB_DCCD0_Pos 2 /**< \brief (DSU_STATUSB) Debug Communication Channel 0 Dirty */
+#define DSU_STATUSB_DCCD0 (1 << DSU_STATUSB_DCCD0_Pos)
+#define DSU_STATUSB_DCCD1_Pos 3 /**< \brief (DSU_STATUSB) Debug Communication Channel 1 Dirty */
+#define DSU_STATUSB_DCCD1 (1 << DSU_STATUSB_DCCD1_Pos)
+#define DSU_STATUSB_DCCD_Pos 2 /**< \brief (DSU_STATUSB) Debug Communication Channel x Dirty */
+#define DSU_STATUSB_DCCD_Msk (0x3ul << DSU_STATUSB_DCCD_Pos)
+#define DSU_STATUSB_DCCD(value) (DSU_STATUSB_DCCD_Msk & ((value) << DSU_STATUSB_DCCD_Pos))
+#define DSU_STATUSB_HPE_Pos 4 /**< \brief (DSU_STATUSB) Hot-Plugging Enable */
+#define DSU_STATUSB_HPE (0x1ul << DSU_STATUSB_HPE_Pos)
+#define DSU_STATUSB_MASK 0x1Ful /**< \brief (DSU_STATUSB) MASK Register */
+
+/* -------- DSU_ADDR : (DSU Offset: 0x0004) (R/W 32) Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :2; /*!< bit: 0.. 1 Reserved */
+ uint32_t ADDR:30; /*!< bit: 2..31 Address */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DSU_ADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_ADDR_OFFSET 0x0004 /**< \brief (DSU_ADDR offset) Address */
+#define DSU_ADDR_RESETVALUE 0x00000000ul /**< \brief (DSU_ADDR reset_value) Address */
+
+#define DSU_ADDR_ADDR_Pos 2 /**< \brief (DSU_ADDR) Address */
+#define DSU_ADDR_ADDR_Msk (0x3FFFFFFFul << DSU_ADDR_ADDR_Pos)
+#define DSU_ADDR_ADDR(value) (DSU_ADDR_ADDR_Msk & ((value) << DSU_ADDR_ADDR_Pos))
+#define DSU_ADDR_MASK 0xFFFFFFFCul /**< \brief (DSU_ADDR) MASK Register */
+
+/* -------- DSU_LENGTH : (DSU Offset: 0x0008) (R/W 32) Length -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :2; /*!< bit: 0.. 1 Reserved */
+ uint32_t LENGTH:30; /*!< bit: 2..31 Length */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DSU_LENGTH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_LENGTH_OFFSET 0x0008 /**< \brief (DSU_LENGTH offset) Length */
+#define DSU_LENGTH_RESETVALUE 0x00000000ul /**< \brief (DSU_LENGTH reset_value) Length */
+
+#define DSU_LENGTH_LENGTH_Pos 2 /**< \brief (DSU_LENGTH) Length */
+#define DSU_LENGTH_LENGTH_Msk (0x3FFFFFFFul << DSU_LENGTH_LENGTH_Pos)
+#define DSU_LENGTH_LENGTH(value) (DSU_LENGTH_LENGTH_Msk & ((value) << DSU_LENGTH_LENGTH_Pos))
+#define DSU_LENGTH_MASK 0xFFFFFFFCul /**< \brief (DSU_LENGTH) MASK Register */
+
+/* -------- DSU_DATA : (DSU Offset: 0x000C) (R/W 32) Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DATA:32; /*!< bit: 0..31 Data */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DSU_DATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_DATA_OFFSET 0x000C /**< \brief (DSU_DATA offset) Data */
+#define DSU_DATA_RESETVALUE 0x00000000ul /**< \brief (DSU_DATA reset_value) Data */
+
+#define DSU_DATA_DATA_Pos 0 /**< \brief (DSU_DATA) Data */
+#define DSU_DATA_DATA_Msk (0xFFFFFFFFul << DSU_DATA_DATA_Pos)
+#define DSU_DATA_DATA(value) (DSU_DATA_DATA_Msk & ((value) << DSU_DATA_DATA_Pos))
+#define DSU_DATA_MASK 0xFFFFFFFFul /**< \brief (DSU_DATA) MASK Register */
+
+/* -------- DSU_DCC : (DSU Offset: 0x0010) (R/W 32) Debug Communication Channel n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DATA:32; /*!< bit: 0..31 Data */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DSU_DCC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_DCC_OFFSET 0x0010 /**< \brief (DSU_DCC offset) Debug Communication Channel n */
+#define DSU_DCC_RESETVALUE 0x00000000ul /**< \brief (DSU_DCC reset_value) Debug Communication Channel n */
+
+#define DSU_DCC_DATA_Pos 0 /**< \brief (DSU_DCC) Data */
+#define DSU_DCC_DATA_Msk (0xFFFFFFFFul << DSU_DCC_DATA_Pos)
+#define DSU_DCC_DATA(value) (DSU_DCC_DATA_Msk & ((value) << DSU_DCC_DATA_Pos))
+#define DSU_DCC_MASK 0xFFFFFFFFul /**< \brief (DSU_DCC) MASK Register */
+
+/* -------- DSU_DID : (DSU Offset: 0x0018) (R/ 32) Device Identification -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DEVSEL:8; /*!< bit: 0.. 7 Device Select */
+ uint32_t REVISION:4; /*!< bit: 8..11 Revision */
+ uint32_t DIE:4; /*!< bit: 12..15 Die Identification */
+ uint32_t SERIES:6; /*!< bit: 16..21 Product Series */
+ uint32_t :1; /*!< bit: 22 Reserved */
+ uint32_t FAMILY:5; /*!< bit: 23..27 Product Family */
+ uint32_t PROCESSOR:4; /*!< bit: 28..31 Processor */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DSU_DID_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_DID_OFFSET 0x0018 /**< \brief (DSU_DID offset) Device Identification */
+
+#define DSU_DID_DEVSEL_Pos 0 /**< \brief (DSU_DID) Device Select */
+#define DSU_DID_DEVSEL_Msk (0xFFul << DSU_DID_DEVSEL_Pos)
+#define DSU_DID_DEVSEL(value) (DSU_DID_DEVSEL_Msk & ((value) << DSU_DID_DEVSEL_Pos))
+#define DSU_DID_REVISION_Pos 8 /**< \brief (DSU_DID) Revision */
+#define DSU_DID_REVISION_Msk (0xFul << DSU_DID_REVISION_Pos)
+#define DSU_DID_REVISION(value) (DSU_DID_REVISION_Msk & ((value) << DSU_DID_REVISION_Pos))
+#define DSU_DID_DIE_Pos 12 /**< \brief (DSU_DID) Die Identification */
+#define DSU_DID_DIE_Msk (0xFul << DSU_DID_DIE_Pos)
+#define DSU_DID_DIE(value) (DSU_DID_DIE_Msk & ((value) << DSU_DID_DIE_Pos))
+#define DSU_DID_SERIES_Pos 16 /**< \brief (DSU_DID) Product Series */
+#define DSU_DID_SERIES_Msk (0x3Ful << DSU_DID_SERIES_Pos)
+#define DSU_DID_SERIES(value) (DSU_DID_SERIES_Msk & ((value) << DSU_DID_SERIES_Pos))
+#define DSU_DID_FAMILY_Pos 23 /**< \brief (DSU_DID) Product Family */
+#define DSU_DID_FAMILY_Msk (0x1Ful << DSU_DID_FAMILY_Pos)
+#define DSU_DID_FAMILY(value) (DSU_DID_FAMILY_Msk & ((value) << DSU_DID_FAMILY_Pos))
+#define DSU_DID_PROCESSOR_Pos 28 /**< \brief (DSU_DID) Processor */
+#define DSU_DID_PROCESSOR_Msk (0xFul << DSU_DID_PROCESSOR_Pos)
+#define DSU_DID_PROCESSOR(value) (DSU_DID_PROCESSOR_Msk & ((value) << DSU_DID_PROCESSOR_Pos))
+#define DSU_DID_MASK 0xFFBFFFFFul /**< \brief (DSU_DID) MASK Register */
+
+/* -------- DSU_ENTRY : (DSU Offset: 0x1000) (R/ 32) Coresight ROM Table Entry n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t EPRES:1; /*!< bit: 0 Entry Present */
+ uint32_t FMT:1; /*!< bit: 1 Format */
+ uint32_t :10; /*!< bit: 2..11 Reserved */
+ uint32_t ADDOFF:20; /*!< bit: 12..31 Address Offset */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DSU_ENTRY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_ENTRY_OFFSET 0x1000 /**< \brief (DSU_ENTRY offset) Coresight ROM Table Entry n */
+#define DSU_ENTRY_RESETVALUE 0x00000002ul /**< \brief (DSU_ENTRY reset_value) Coresight ROM Table Entry n */
+
+#define DSU_ENTRY_EPRES_Pos 0 /**< \brief (DSU_ENTRY) Entry Present */
+#define DSU_ENTRY_EPRES (0x1ul << DSU_ENTRY_EPRES_Pos)
+#define DSU_ENTRY_FMT_Pos 1 /**< \brief (DSU_ENTRY) Format */
+#define DSU_ENTRY_FMT (0x1ul << DSU_ENTRY_FMT_Pos)
+#define DSU_ENTRY_ADDOFF_Pos 12 /**< \brief (DSU_ENTRY) Address Offset */
+#define DSU_ENTRY_ADDOFF_Msk (0xFFFFFul << DSU_ENTRY_ADDOFF_Pos)
+#define DSU_ENTRY_ADDOFF(value) (DSU_ENTRY_ADDOFF_Msk & ((value) << DSU_ENTRY_ADDOFF_Pos))
+#define DSU_ENTRY_MASK 0xFFFFF003ul /**< \brief (DSU_ENTRY) MASK Register */
+
+/* -------- DSU_END : (DSU Offset: 0x1008) (R/ 32) Coresight ROM Table End -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t END:32; /*!< bit: 0..31 End Marker */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DSU_END_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_END_OFFSET 0x1008 /**< \brief (DSU_END offset) Coresight ROM Table End */
+#define DSU_END_RESETVALUE 0x00000000ul /**< \brief (DSU_END reset_value) Coresight ROM Table End */
+
+#define DSU_END_END_Pos 0 /**< \brief (DSU_END) End Marker */
+#define DSU_END_END_Msk (0xFFFFFFFFul << DSU_END_END_Pos)
+#define DSU_END_END(value) (DSU_END_END_Msk & ((value) << DSU_END_END_Pos))
+#define DSU_END_MASK 0xFFFFFFFFul /**< \brief (DSU_END) MASK Register */
+
+/* -------- DSU_MEMTYPE : (DSU Offset: 0x1FCC) (R/ 32) Coresight ROM Table Memory Type -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SMEMP:1; /*!< bit: 0 System Memory Present */
+ uint32_t :31; /*!< bit: 1..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DSU_MEMTYPE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_MEMTYPE_OFFSET 0x1FCC /**< \brief (DSU_MEMTYPE offset) Coresight ROM Table Memory Type */
+#define DSU_MEMTYPE_RESETVALUE 0x00000000ul /**< \brief (DSU_MEMTYPE reset_value) Coresight ROM Table Memory Type */
+
+#define DSU_MEMTYPE_SMEMP_Pos 0 /**< \brief (DSU_MEMTYPE) System Memory Present */
+#define DSU_MEMTYPE_SMEMP (0x1ul << DSU_MEMTYPE_SMEMP_Pos)
+#define DSU_MEMTYPE_MASK 0x00000001ul /**< \brief (DSU_MEMTYPE) MASK Register */
+
+/* -------- DSU_PID4 : (DSU Offset: 0x1FD0) (R/ 32) Peripheral Identification 4 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t JEPCC:4; /*!< bit: 0.. 3 JEP-106 Continuation Code */
+ uint32_t FKBC:4; /*!< bit: 4.. 7 4KB Count */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DSU_PID4_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_PID4_OFFSET 0x1FD0 /**< \brief (DSU_PID4 offset) Peripheral Identification 4 */
+#define DSU_PID4_RESETVALUE 0x00000000ul /**< \brief (DSU_PID4 reset_value) Peripheral Identification 4 */
+
+#define DSU_PID4_JEPCC_Pos 0 /**< \brief (DSU_PID4) JEP-106 Continuation Code */
+#define DSU_PID4_JEPCC_Msk (0xFul << DSU_PID4_JEPCC_Pos)
+#define DSU_PID4_JEPCC(value) (DSU_PID4_JEPCC_Msk & ((value) << DSU_PID4_JEPCC_Pos))
+#define DSU_PID4_FKBC_Pos 4 /**< \brief (DSU_PID4) 4KB Count */
+#define DSU_PID4_FKBC_Msk (0xFul << DSU_PID4_FKBC_Pos)
+#define DSU_PID4_FKBC(value) (DSU_PID4_FKBC_Msk & ((value) << DSU_PID4_FKBC_Pos))
+#define DSU_PID4_MASK 0x000000FFul /**< \brief (DSU_PID4) MASK Register */
+
+/* -------- DSU_PID0 : (DSU Offset: 0x1FE0) (R/ 32) Peripheral Identification 0 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t PARTNBL:8; /*!< bit: 0.. 7 Part Number Low */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DSU_PID0_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_PID0_OFFSET 0x1FE0 /**< \brief (DSU_PID0 offset) Peripheral Identification 0 */
+#define DSU_PID0_RESETVALUE 0x000000D0ul /**< \brief (DSU_PID0 reset_value) Peripheral Identification 0 */
+
+#define DSU_PID0_PARTNBL_Pos 0 /**< \brief (DSU_PID0) Part Number Low */
+#define DSU_PID0_PARTNBL_Msk (0xFFul << DSU_PID0_PARTNBL_Pos)
+#define DSU_PID0_PARTNBL(value) (DSU_PID0_PARTNBL_Msk & ((value) << DSU_PID0_PARTNBL_Pos))
+#define DSU_PID0_MASK 0x000000FFul /**< \brief (DSU_PID0) MASK Register */
+
+/* -------- DSU_PID1 : (DSU Offset: 0x1FE4) (R/ 32) Peripheral Identification 1 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t PARTNBH:4; /*!< bit: 0.. 3 Part Number High */
+ uint32_t JEPIDCL:4; /*!< bit: 4.. 7 Low part of the JEP-106 Identity Code */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DSU_PID1_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_PID1_OFFSET 0x1FE4 /**< \brief (DSU_PID1 offset) Peripheral Identification 1 */
+#define DSU_PID1_RESETVALUE 0x000000FCul /**< \brief (DSU_PID1 reset_value) Peripheral Identification 1 */
+
+#define DSU_PID1_PARTNBH_Pos 0 /**< \brief (DSU_PID1) Part Number High */
+#define DSU_PID1_PARTNBH_Msk (0xFul << DSU_PID1_PARTNBH_Pos)
+#define DSU_PID1_PARTNBH(value) (DSU_PID1_PARTNBH_Msk & ((value) << DSU_PID1_PARTNBH_Pos))
+#define DSU_PID1_JEPIDCL_Pos 4 /**< \brief (DSU_PID1) Low part of the JEP-106 Identity Code */
+#define DSU_PID1_JEPIDCL_Msk (0xFul << DSU_PID1_JEPIDCL_Pos)
+#define DSU_PID1_JEPIDCL(value) (DSU_PID1_JEPIDCL_Msk & ((value) << DSU_PID1_JEPIDCL_Pos))
+#define DSU_PID1_MASK 0x000000FFul /**< \brief (DSU_PID1) MASK Register */
+
+/* -------- DSU_PID2 : (DSU Offset: 0x1FE8) (R/ 32) Peripheral Identification 2 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t JEPIDCH:3; /*!< bit: 0.. 2 JEP-106 Identity Code High */
+ uint32_t JEPU:1; /*!< bit: 3 JEP-106 Identity Code is used */
+ uint32_t REVISION:4; /*!< bit: 4.. 7 Revision Number */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DSU_PID2_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_PID2_OFFSET 0x1FE8 /**< \brief (DSU_PID2 offset) Peripheral Identification 2 */
+#define DSU_PID2_RESETVALUE 0x00000009ul /**< \brief (DSU_PID2 reset_value) Peripheral Identification 2 */
+
+#define DSU_PID2_JEPIDCH_Pos 0 /**< \brief (DSU_PID2) JEP-106 Identity Code High */
+#define DSU_PID2_JEPIDCH_Msk (0x7ul << DSU_PID2_JEPIDCH_Pos)
+#define DSU_PID2_JEPIDCH(value) (DSU_PID2_JEPIDCH_Msk & ((value) << DSU_PID2_JEPIDCH_Pos))
+#define DSU_PID2_JEPU_Pos 3 /**< \brief (DSU_PID2) JEP-106 Identity Code is used */
+#define DSU_PID2_JEPU (0x1ul << DSU_PID2_JEPU_Pos)
+#define DSU_PID2_REVISION_Pos 4 /**< \brief (DSU_PID2) Revision Number */
+#define DSU_PID2_REVISION_Msk (0xFul << DSU_PID2_REVISION_Pos)
+#define DSU_PID2_REVISION(value) (DSU_PID2_REVISION_Msk & ((value) << DSU_PID2_REVISION_Pos))
+#define DSU_PID2_MASK 0x000000FFul /**< \brief (DSU_PID2) MASK Register */
+
+/* -------- DSU_PID3 : (DSU Offset: 0x1FEC) (R/ 32) Peripheral Identification 3 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CUSMOD:4; /*!< bit: 0.. 3 ARM CUSMOD */
+ uint32_t REVAND:4; /*!< bit: 4.. 7 Revision Number */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DSU_PID3_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_PID3_OFFSET 0x1FEC /**< \brief (DSU_PID3 offset) Peripheral Identification 3 */
+#define DSU_PID3_RESETVALUE 0x00000000ul /**< \brief (DSU_PID3 reset_value) Peripheral Identification 3 */
+
+#define DSU_PID3_CUSMOD_Pos 0 /**< \brief (DSU_PID3) ARM CUSMOD */
+#define DSU_PID3_CUSMOD_Msk (0xFul << DSU_PID3_CUSMOD_Pos)
+#define DSU_PID3_CUSMOD(value) (DSU_PID3_CUSMOD_Msk & ((value) << DSU_PID3_CUSMOD_Pos))
+#define DSU_PID3_REVAND_Pos 4 /**< \brief (DSU_PID3) Revision Number */
+#define DSU_PID3_REVAND_Msk (0xFul << DSU_PID3_REVAND_Pos)
+#define DSU_PID3_REVAND(value) (DSU_PID3_REVAND_Msk & ((value) << DSU_PID3_REVAND_Pos))
+#define DSU_PID3_MASK 0x000000FFul /**< \brief (DSU_PID3) MASK Register */
+
+/* -------- DSU_CID0 : (DSU Offset: 0x1FF0) (R/ 32) Component Identification 0 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t PREAMBLEB0:8; /*!< bit: 0.. 7 Preamble Byte 0 */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DSU_CID0_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_CID0_OFFSET 0x1FF0 /**< \brief (DSU_CID0 offset) Component Identification 0 */
+#define DSU_CID0_RESETVALUE 0x0000000Dul /**< \brief (DSU_CID0 reset_value) Component Identification 0 */
+
+#define DSU_CID0_PREAMBLEB0_Pos 0 /**< \brief (DSU_CID0) Preamble Byte 0 */
+#define DSU_CID0_PREAMBLEB0_Msk (0xFFul << DSU_CID0_PREAMBLEB0_Pos)
+#define DSU_CID0_PREAMBLEB0(value) (DSU_CID0_PREAMBLEB0_Msk & ((value) << DSU_CID0_PREAMBLEB0_Pos))
+#define DSU_CID0_MASK 0x000000FFul /**< \brief (DSU_CID0) MASK Register */
+
+/* -------- DSU_CID1 : (DSU Offset: 0x1FF4) (R/ 32) Component Identification 1 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t PREAMBLE:4; /*!< bit: 0.. 3 Preamble */
+ uint32_t CCLASS:4; /*!< bit: 4.. 7 Component Class */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DSU_CID1_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_CID1_OFFSET 0x1FF4 /**< \brief (DSU_CID1 offset) Component Identification 1 */
+#define DSU_CID1_RESETVALUE 0x00000010ul /**< \brief (DSU_CID1 reset_value) Component Identification 1 */
+
+#define DSU_CID1_PREAMBLE_Pos 0 /**< \brief (DSU_CID1) Preamble */
+#define DSU_CID1_PREAMBLE_Msk (0xFul << DSU_CID1_PREAMBLE_Pos)
+#define DSU_CID1_PREAMBLE(value) (DSU_CID1_PREAMBLE_Msk & ((value) << DSU_CID1_PREAMBLE_Pos))
+#define DSU_CID1_CCLASS_Pos 4 /**< \brief (DSU_CID1) Component Class */
+#define DSU_CID1_CCLASS_Msk (0xFul << DSU_CID1_CCLASS_Pos)
+#define DSU_CID1_CCLASS(value) (DSU_CID1_CCLASS_Msk & ((value) << DSU_CID1_CCLASS_Pos))
+#define DSU_CID1_MASK 0x000000FFul /**< \brief (DSU_CID1) MASK Register */
+
+/* -------- DSU_CID2 : (DSU Offset: 0x1FF8) (R/ 32) Component Identification 2 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t PREAMBLEB2:8; /*!< bit: 0.. 7 Preamble Byte 2 */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DSU_CID2_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_CID2_OFFSET 0x1FF8 /**< \brief (DSU_CID2 offset) Component Identification 2 */
+#define DSU_CID2_RESETVALUE 0x00000005ul /**< \brief (DSU_CID2 reset_value) Component Identification 2 */
+
+#define DSU_CID2_PREAMBLEB2_Pos 0 /**< \brief (DSU_CID2) Preamble Byte 2 */
+#define DSU_CID2_PREAMBLEB2_Msk (0xFFul << DSU_CID2_PREAMBLEB2_Pos)
+#define DSU_CID2_PREAMBLEB2(value) (DSU_CID2_PREAMBLEB2_Msk & ((value) << DSU_CID2_PREAMBLEB2_Pos))
+#define DSU_CID2_MASK 0x000000FFul /**< \brief (DSU_CID2) MASK Register */
+
+/* -------- DSU_CID3 : (DSU Offset: 0x1FFC) (R/ 32) Component Identification 3 -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t PREAMBLEB3:8; /*!< bit: 0.. 7 Preamble Byte 3 */
+ uint32_t :24; /*!< bit: 8..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} DSU_CID3_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define DSU_CID3_OFFSET 0x1FFC /**< \brief (DSU_CID3 offset) Component Identification 3 */
+#define DSU_CID3_RESETVALUE 0x000000B1ul /**< \brief (DSU_CID3 reset_value) Component Identification 3 */
+
+#define DSU_CID3_PREAMBLEB3_Pos 0 /**< \brief (DSU_CID3) Preamble Byte 3 */
+#define DSU_CID3_PREAMBLEB3_Msk (0xFFul << DSU_CID3_PREAMBLEB3_Pos)
+#define DSU_CID3_PREAMBLEB3(value) (DSU_CID3_PREAMBLEB3_Msk & ((value) << DSU_CID3_PREAMBLEB3_Pos))
+#define DSU_CID3_MASK 0x000000FFul /**< \brief (DSU_CID3) MASK Register */
+
+/** \brief DSU hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __O DSU_CTRL_Type CTRL; /**< \brief Offset: 0x0000 ( /W 8) Control */
+ __IO DSU_STATUSA_Type STATUSA; /**< \brief Offset: 0x0001 (R/W 8) Status A */
+ __I DSU_STATUSB_Type STATUSB; /**< \brief Offset: 0x0002 (R/ 8) Status B */
+ RoReg8 Reserved1[0x1];
+ __IO DSU_ADDR_Type ADDR; /**< \brief Offset: 0x0004 (R/W 32) Address */
+ __IO DSU_LENGTH_Type LENGTH; /**< \brief Offset: 0x0008 (R/W 32) Length */
+ __IO DSU_DATA_Type DATA; /**< \brief Offset: 0x000C (R/W 32) Data */
+ __IO DSU_DCC_Type DCC[2]; /**< \brief Offset: 0x0010 (R/W 32) Debug Communication Channel n */
+ __I DSU_DID_Type DID; /**< \brief Offset: 0x0018 (R/ 32) Device Identification */
+ RoReg8 Reserved2[0xFE4];
+ __I DSU_ENTRY_Type ENTRY[2]; /**< \brief Offset: 0x1000 (R/ 32) Coresight ROM Table Entry n */
+ __I DSU_END_Type END; /**< \brief Offset: 0x1008 (R/ 32) Coresight ROM Table End */
+ RoReg8 Reserved3[0xFC0];
+ __I DSU_MEMTYPE_Type MEMTYPE; /**< \brief Offset: 0x1FCC (R/ 32) Coresight ROM Table Memory Type */
+ __I DSU_PID4_Type PID4; /**< \brief Offset: 0x1FD0 (R/ 32) Peripheral Identification 4 */
+ RoReg8 Reserved4[0xC];
+ __I DSU_PID0_Type PID0; /**< \brief Offset: 0x1FE0 (R/ 32) Peripheral Identification 0 */
+ __I DSU_PID1_Type PID1; /**< \brief Offset: 0x1FE4 (R/ 32) Peripheral Identification 1 */
+ __I DSU_PID2_Type PID2; /**< \brief Offset: 0x1FE8 (R/ 32) Peripheral Identification 2 */
+ __I DSU_PID3_Type PID3; /**< \brief Offset: 0x1FEC (R/ 32) Peripheral Identification 3 */
+ __I DSU_CID0_Type CID0; /**< \brief Offset: 0x1FF0 (R/ 32) Component Identification 0 */
+ __I DSU_CID1_Type CID1; /**< \brief Offset: 0x1FF4 (R/ 32) Component Identification 1 */
+ __I DSU_CID2_Type CID2; /**< \brief Offset: 0x1FF8 (R/ 32) Component Identification 2 */
+ __I DSU_CID3_Type CID3; /**< \brief Offset: 0x1FFC (R/ 32) Component Identification 3 */
+} Dsu;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_DSU_COMPONENT_ */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/component/eic.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/component/eic.h
new file mode 100644
index 0000000000000000000000000000000000000000..e81a25ffec6cfdf0d6d57e74b3c867ceaffcf2ef
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/component/eic.h
@@ -0,0 +1,681 @@
+/**
+ * \file
+ *
+ * \brief Component description for EIC
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_EIC_COMPONENT_
+#define _SAMD21_EIC_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR EIC */
+/* ========================================================================== */
+/** \addtogroup SAMD21_EIC External Interrupt Controller */
+/*@{*/
+
+#define EIC_U2217
+#define REV_EIC 0x101
+
+/* -------- EIC_CTRL : (EIC Offset: 0x00) (R/W 8) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t ENABLE:1; /*!< bit: 1 Enable */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} EIC_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_CTRL_OFFSET 0x00 /**< \brief (EIC_CTRL offset) Control */
+#define EIC_CTRL_RESETVALUE 0x00ul /**< \brief (EIC_CTRL reset_value) Control */
+
+#define EIC_CTRL_SWRST_Pos 0 /**< \brief (EIC_CTRL) Software Reset */
+#define EIC_CTRL_SWRST (0x1ul << EIC_CTRL_SWRST_Pos)
+#define EIC_CTRL_ENABLE_Pos 1 /**< \brief (EIC_CTRL) Enable */
+#define EIC_CTRL_ENABLE (0x1ul << EIC_CTRL_ENABLE_Pos)
+#define EIC_CTRL_MASK 0x03ul /**< \brief (EIC_CTRL) MASK Register */
+
+/* -------- EIC_STATUS : (EIC Offset: 0x01) (R/ 8) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t :7; /*!< bit: 0.. 6 Reserved */
+ uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} EIC_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_STATUS_OFFSET 0x01 /**< \brief (EIC_STATUS offset) Status */
+#define EIC_STATUS_RESETVALUE 0x00ul /**< \brief (EIC_STATUS reset_value) Status */
+
+#define EIC_STATUS_SYNCBUSY_Pos 7 /**< \brief (EIC_STATUS) Synchronization Busy */
+#define EIC_STATUS_SYNCBUSY (0x1ul << EIC_STATUS_SYNCBUSY_Pos)
+#define EIC_STATUS_MASK 0x80ul /**< \brief (EIC_STATUS) MASK Register */
+
+/* -------- EIC_NMICTRL : (EIC Offset: 0x02) (R/W 8) Non-Maskable Interrupt Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t NMISENSE:3; /*!< bit: 0.. 2 Non-Maskable Interrupt Sense */
+ uint8_t NMIFILTEN:1; /*!< bit: 3 Non-Maskable Interrupt Filter Enable */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} EIC_NMICTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_NMICTRL_OFFSET 0x02 /**< \brief (EIC_NMICTRL offset) Non-Maskable Interrupt Control */
+#define EIC_NMICTRL_RESETVALUE 0x00ul /**< \brief (EIC_NMICTRL reset_value) Non-Maskable Interrupt Control */
+
+#define EIC_NMICTRL_NMISENSE_Pos 0 /**< \brief (EIC_NMICTRL) Non-Maskable Interrupt Sense */
+#define EIC_NMICTRL_NMISENSE_Msk (0x7ul << EIC_NMICTRL_NMISENSE_Pos)
+#define EIC_NMICTRL_NMISENSE(value) (EIC_NMICTRL_NMISENSE_Msk & ((value) << EIC_NMICTRL_NMISENSE_Pos))
+#define EIC_NMICTRL_NMISENSE_NONE_Val 0x0ul /**< \brief (EIC_NMICTRL) No detection */
+#define EIC_NMICTRL_NMISENSE_RISE_Val 0x1ul /**< \brief (EIC_NMICTRL) Rising-edge detection */
+#define EIC_NMICTRL_NMISENSE_FALL_Val 0x2ul /**< \brief (EIC_NMICTRL) Falling-edge detection */
+#define EIC_NMICTRL_NMISENSE_BOTH_Val 0x3ul /**< \brief (EIC_NMICTRL) Both-edges detection */
+#define EIC_NMICTRL_NMISENSE_HIGH_Val 0x4ul /**< \brief (EIC_NMICTRL) High-level detection */
+#define EIC_NMICTRL_NMISENSE_LOW_Val 0x5ul /**< \brief (EIC_NMICTRL) Low-level detection */
+#define EIC_NMICTRL_NMISENSE_NONE (EIC_NMICTRL_NMISENSE_NONE_Val << EIC_NMICTRL_NMISENSE_Pos)
+#define EIC_NMICTRL_NMISENSE_RISE (EIC_NMICTRL_NMISENSE_RISE_Val << EIC_NMICTRL_NMISENSE_Pos)
+#define EIC_NMICTRL_NMISENSE_FALL (EIC_NMICTRL_NMISENSE_FALL_Val << EIC_NMICTRL_NMISENSE_Pos)
+#define EIC_NMICTRL_NMISENSE_BOTH (EIC_NMICTRL_NMISENSE_BOTH_Val << EIC_NMICTRL_NMISENSE_Pos)
+#define EIC_NMICTRL_NMISENSE_HIGH (EIC_NMICTRL_NMISENSE_HIGH_Val << EIC_NMICTRL_NMISENSE_Pos)
+#define EIC_NMICTRL_NMISENSE_LOW (EIC_NMICTRL_NMISENSE_LOW_Val << EIC_NMICTRL_NMISENSE_Pos)
+#define EIC_NMICTRL_NMIFILTEN_Pos 3 /**< \brief (EIC_NMICTRL) Non-Maskable Interrupt Filter Enable */
+#define EIC_NMICTRL_NMIFILTEN (0x1ul << EIC_NMICTRL_NMIFILTEN_Pos)
+#define EIC_NMICTRL_MASK 0x0Ful /**< \brief (EIC_NMICTRL) MASK Register */
+
+/* -------- EIC_NMIFLAG : (EIC Offset: 0x03) (R/W 8) Non-Maskable Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t NMI:1; /*!< bit: 0 Non-Maskable Interrupt */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} EIC_NMIFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_NMIFLAG_OFFSET 0x03 /**< \brief (EIC_NMIFLAG offset) Non-Maskable Interrupt Flag Status and Clear */
+#define EIC_NMIFLAG_RESETVALUE 0x00ul /**< \brief (EIC_NMIFLAG reset_value) Non-Maskable Interrupt Flag Status and Clear */
+
+#define EIC_NMIFLAG_NMI_Pos 0 /**< \brief (EIC_NMIFLAG) Non-Maskable Interrupt */
+#define EIC_NMIFLAG_NMI (0x1ul << EIC_NMIFLAG_NMI_Pos)
+#define EIC_NMIFLAG_MASK 0x01ul /**< \brief (EIC_NMIFLAG) MASK Register */
+
+/* -------- EIC_EVCTRL : (EIC Offset: 0x04) (R/W 32) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t EXTINTEO0:1; /*!< bit: 0 External Interrupt 0 Event Output Enable */
+ uint32_t EXTINTEO1:1; /*!< bit: 1 External Interrupt 1 Event Output Enable */
+ uint32_t EXTINTEO2:1; /*!< bit: 2 External Interrupt 2 Event Output Enable */
+ uint32_t EXTINTEO3:1; /*!< bit: 3 External Interrupt 3 Event Output Enable */
+ uint32_t EXTINTEO4:1; /*!< bit: 4 External Interrupt 4 Event Output Enable */
+ uint32_t EXTINTEO5:1; /*!< bit: 5 External Interrupt 5 Event Output Enable */
+ uint32_t EXTINTEO6:1; /*!< bit: 6 External Interrupt 6 Event Output Enable */
+ uint32_t EXTINTEO7:1; /*!< bit: 7 External Interrupt 7 Event Output Enable */
+ uint32_t EXTINTEO8:1; /*!< bit: 8 External Interrupt 8 Event Output Enable */
+ uint32_t EXTINTEO9:1; /*!< bit: 9 External Interrupt 9 Event Output Enable */
+ uint32_t EXTINTEO10:1; /*!< bit: 10 External Interrupt 10 Event Output Enable */
+ uint32_t EXTINTEO11:1; /*!< bit: 11 External Interrupt 11 Event Output Enable */
+ uint32_t EXTINTEO12:1; /*!< bit: 12 External Interrupt 12 Event Output Enable */
+ uint32_t EXTINTEO13:1; /*!< bit: 13 External Interrupt 13 Event Output Enable */
+ uint32_t EXTINTEO14:1; /*!< bit: 14 External Interrupt 14 Event Output Enable */
+ uint32_t EXTINTEO15:1; /*!< bit: 15 External Interrupt 15 Event Output Enable */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t EXTINTEO:16; /*!< bit: 0..15 External Interrupt x Event Output Enable */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} EIC_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_EVCTRL_OFFSET 0x04 /**< \brief (EIC_EVCTRL offset) Event Control */
+#define EIC_EVCTRL_RESETVALUE 0x00000000ul /**< \brief (EIC_EVCTRL reset_value) Event Control */
+
+#define EIC_EVCTRL_EXTINTEO0_Pos 0 /**< \brief (EIC_EVCTRL) External Interrupt 0 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO0 (1 << EIC_EVCTRL_EXTINTEO0_Pos)
+#define EIC_EVCTRL_EXTINTEO1_Pos 1 /**< \brief (EIC_EVCTRL) External Interrupt 1 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO1 (1 << EIC_EVCTRL_EXTINTEO1_Pos)
+#define EIC_EVCTRL_EXTINTEO2_Pos 2 /**< \brief (EIC_EVCTRL) External Interrupt 2 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO2 (1 << EIC_EVCTRL_EXTINTEO2_Pos)
+#define EIC_EVCTRL_EXTINTEO3_Pos 3 /**< \brief (EIC_EVCTRL) External Interrupt 3 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO3 (1 << EIC_EVCTRL_EXTINTEO3_Pos)
+#define EIC_EVCTRL_EXTINTEO4_Pos 4 /**< \brief (EIC_EVCTRL) External Interrupt 4 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO4 (1 << EIC_EVCTRL_EXTINTEO4_Pos)
+#define EIC_EVCTRL_EXTINTEO5_Pos 5 /**< \brief (EIC_EVCTRL) External Interrupt 5 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO5 (1 << EIC_EVCTRL_EXTINTEO5_Pos)
+#define EIC_EVCTRL_EXTINTEO6_Pos 6 /**< \brief (EIC_EVCTRL) External Interrupt 6 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO6 (1 << EIC_EVCTRL_EXTINTEO6_Pos)
+#define EIC_EVCTRL_EXTINTEO7_Pos 7 /**< \brief (EIC_EVCTRL) External Interrupt 7 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO7 (1 << EIC_EVCTRL_EXTINTEO7_Pos)
+#define EIC_EVCTRL_EXTINTEO8_Pos 8 /**< \brief (EIC_EVCTRL) External Interrupt 8 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO8 (1 << EIC_EVCTRL_EXTINTEO8_Pos)
+#define EIC_EVCTRL_EXTINTEO9_Pos 9 /**< \brief (EIC_EVCTRL) External Interrupt 9 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO9 (1 << EIC_EVCTRL_EXTINTEO9_Pos)
+#define EIC_EVCTRL_EXTINTEO10_Pos 10 /**< \brief (EIC_EVCTRL) External Interrupt 10 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO10 (1 << EIC_EVCTRL_EXTINTEO10_Pos)
+#define EIC_EVCTRL_EXTINTEO11_Pos 11 /**< \brief (EIC_EVCTRL) External Interrupt 11 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO11 (1 << EIC_EVCTRL_EXTINTEO11_Pos)
+#define EIC_EVCTRL_EXTINTEO12_Pos 12 /**< \brief (EIC_EVCTRL) External Interrupt 12 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO12 (1 << EIC_EVCTRL_EXTINTEO12_Pos)
+#define EIC_EVCTRL_EXTINTEO13_Pos 13 /**< \brief (EIC_EVCTRL) External Interrupt 13 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO13 (1 << EIC_EVCTRL_EXTINTEO13_Pos)
+#define EIC_EVCTRL_EXTINTEO14_Pos 14 /**< \brief (EIC_EVCTRL) External Interrupt 14 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO14 (1 << EIC_EVCTRL_EXTINTEO14_Pos)
+#define EIC_EVCTRL_EXTINTEO15_Pos 15 /**< \brief (EIC_EVCTRL) External Interrupt 15 Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO15 (1 << EIC_EVCTRL_EXTINTEO15_Pos)
+#define EIC_EVCTRL_EXTINTEO_Pos 0 /**< \brief (EIC_EVCTRL) External Interrupt x Event Output Enable */
+#define EIC_EVCTRL_EXTINTEO_Msk (0xFFFFul << EIC_EVCTRL_EXTINTEO_Pos)
+#define EIC_EVCTRL_EXTINTEO(value) (EIC_EVCTRL_EXTINTEO_Msk & ((value) << EIC_EVCTRL_EXTINTEO_Pos))
+#define EIC_EVCTRL_MASK 0x0000FFFFul /**< \brief (EIC_EVCTRL) MASK Register */
+
+/* -------- EIC_INTENCLR : (EIC Offset: 0x08) (R/W 32) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 Enable */
+ uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 Enable */
+ uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 Enable */
+ uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 Enable */
+ uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 Enable */
+ uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 Enable */
+ uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 Enable */
+ uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 Enable */
+ uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 Enable */
+ uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 Enable */
+ uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 Enable */
+ uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 Enable */
+ uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 Enable */
+ uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 Enable */
+ uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 Enable */
+ uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 Enable */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x Enable */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} EIC_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_INTENCLR_OFFSET 0x08 /**< \brief (EIC_INTENCLR offset) Interrupt Enable Clear */
+#define EIC_INTENCLR_RESETVALUE 0x00000000ul /**< \brief (EIC_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define EIC_INTENCLR_EXTINT0_Pos 0 /**< \brief (EIC_INTENCLR) External Interrupt 0 Enable */
+#define EIC_INTENCLR_EXTINT0 (1 << EIC_INTENCLR_EXTINT0_Pos)
+#define EIC_INTENCLR_EXTINT1_Pos 1 /**< \brief (EIC_INTENCLR) External Interrupt 1 Enable */
+#define EIC_INTENCLR_EXTINT1 (1 << EIC_INTENCLR_EXTINT1_Pos)
+#define EIC_INTENCLR_EXTINT2_Pos 2 /**< \brief (EIC_INTENCLR) External Interrupt 2 Enable */
+#define EIC_INTENCLR_EXTINT2 (1 << EIC_INTENCLR_EXTINT2_Pos)
+#define EIC_INTENCLR_EXTINT3_Pos 3 /**< \brief (EIC_INTENCLR) External Interrupt 3 Enable */
+#define EIC_INTENCLR_EXTINT3 (1 << EIC_INTENCLR_EXTINT3_Pos)
+#define EIC_INTENCLR_EXTINT4_Pos 4 /**< \brief (EIC_INTENCLR) External Interrupt 4 Enable */
+#define EIC_INTENCLR_EXTINT4 (1 << EIC_INTENCLR_EXTINT4_Pos)
+#define EIC_INTENCLR_EXTINT5_Pos 5 /**< \brief (EIC_INTENCLR) External Interrupt 5 Enable */
+#define EIC_INTENCLR_EXTINT5 (1 << EIC_INTENCLR_EXTINT5_Pos)
+#define EIC_INTENCLR_EXTINT6_Pos 6 /**< \brief (EIC_INTENCLR) External Interrupt 6 Enable */
+#define EIC_INTENCLR_EXTINT6 (1 << EIC_INTENCLR_EXTINT6_Pos)
+#define EIC_INTENCLR_EXTINT7_Pos 7 /**< \brief (EIC_INTENCLR) External Interrupt 7 Enable */
+#define EIC_INTENCLR_EXTINT7 (1 << EIC_INTENCLR_EXTINT7_Pos)
+#define EIC_INTENCLR_EXTINT8_Pos 8 /**< \brief (EIC_INTENCLR) External Interrupt 8 Enable */
+#define EIC_INTENCLR_EXTINT8 (1 << EIC_INTENCLR_EXTINT8_Pos)
+#define EIC_INTENCLR_EXTINT9_Pos 9 /**< \brief (EIC_INTENCLR) External Interrupt 9 Enable */
+#define EIC_INTENCLR_EXTINT9 (1 << EIC_INTENCLR_EXTINT9_Pos)
+#define EIC_INTENCLR_EXTINT10_Pos 10 /**< \brief (EIC_INTENCLR) External Interrupt 10 Enable */
+#define EIC_INTENCLR_EXTINT10 (1 << EIC_INTENCLR_EXTINT10_Pos)
+#define EIC_INTENCLR_EXTINT11_Pos 11 /**< \brief (EIC_INTENCLR) External Interrupt 11 Enable */
+#define EIC_INTENCLR_EXTINT11 (1 << EIC_INTENCLR_EXTINT11_Pos)
+#define EIC_INTENCLR_EXTINT12_Pos 12 /**< \brief (EIC_INTENCLR) External Interrupt 12 Enable */
+#define EIC_INTENCLR_EXTINT12 (1 << EIC_INTENCLR_EXTINT12_Pos)
+#define EIC_INTENCLR_EXTINT13_Pos 13 /**< \brief (EIC_INTENCLR) External Interrupt 13 Enable */
+#define EIC_INTENCLR_EXTINT13 (1 << EIC_INTENCLR_EXTINT13_Pos)
+#define EIC_INTENCLR_EXTINT14_Pos 14 /**< \brief (EIC_INTENCLR) External Interrupt 14 Enable */
+#define EIC_INTENCLR_EXTINT14 (1 << EIC_INTENCLR_EXTINT14_Pos)
+#define EIC_INTENCLR_EXTINT15_Pos 15 /**< \brief (EIC_INTENCLR) External Interrupt 15 Enable */
+#define EIC_INTENCLR_EXTINT15 (1 << EIC_INTENCLR_EXTINT15_Pos)
+#define EIC_INTENCLR_EXTINT_Pos 0 /**< \brief (EIC_INTENCLR) External Interrupt x Enable */
+#define EIC_INTENCLR_EXTINT_Msk (0xFFFFul << EIC_INTENCLR_EXTINT_Pos)
+#define EIC_INTENCLR_EXTINT(value) (EIC_INTENCLR_EXTINT_Msk & ((value) << EIC_INTENCLR_EXTINT_Pos))
+#define EIC_INTENCLR_MASK 0x0000FFFFul /**< \brief (EIC_INTENCLR) MASK Register */
+
+/* -------- EIC_INTENSET : (EIC Offset: 0x0C) (R/W 32) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 Enable */
+ uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 Enable */
+ uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 Enable */
+ uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 Enable */
+ uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 Enable */
+ uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 Enable */
+ uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 Enable */
+ uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 Enable */
+ uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 Enable */
+ uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 Enable */
+ uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 Enable */
+ uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 Enable */
+ uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 Enable */
+ uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 Enable */
+ uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 Enable */
+ uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 Enable */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x Enable */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} EIC_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_INTENSET_OFFSET 0x0C /**< \brief (EIC_INTENSET offset) Interrupt Enable Set */
+#define EIC_INTENSET_RESETVALUE 0x00000000ul /**< \brief (EIC_INTENSET reset_value) Interrupt Enable Set */
+
+#define EIC_INTENSET_EXTINT0_Pos 0 /**< \brief (EIC_INTENSET) External Interrupt 0 Enable */
+#define EIC_INTENSET_EXTINT0 (1 << EIC_INTENSET_EXTINT0_Pos)
+#define EIC_INTENSET_EXTINT1_Pos 1 /**< \brief (EIC_INTENSET) External Interrupt 1 Enable */
+#define EIC_INTENSET_EXTINT1 (1 << EIC_INTENSET_EXTINT1_Pos)
+#define EIC_INTENSET_EXTINT2_Pos 2 /**< \brief (EIC_INTENSET) External Interrupt 2 Enable */
+#define EIC_INTENSET_EXTINT2 (1 << EIC_INTENSET_EXTINT2_Pos)
+#define EIC_INTENSET_EXTINT3_Pos 3 /**< \brief (EIC_INTENSET) External Interrupt 3 Enable */
+#define EIC_INTENSET_EXTINT3 (1 << EIC_INTENSET_EXTINT3_Pos)
+#define EIC_INTENSET_EXTINT4_Pos 4 /**< \brief (EIC_INTENSET) External Interrupt 4 Enable */
+#define EIC_INTENSET_EXTINT4 (1 << EIC_INTENSET_EXTINT4_Pos)
+#define EIC_INTENSET_EXTINT5_Pos 5 /**< \brief (EIC_INTENSET) External Interrupt 5 Enable */
+#define EIC_INTENSET_EXTINT5 (1 << EIC_INTENSET_EXTINT5_Pos)
+#define EIC_INTENSET_EXTINT6_Pos 6 /**< \brief (EIC_INTENSET) External Interrupt 6 Enable */
+#define EIC_INTENSET_EXTINT6 (1 << EIC_INTENSET_EXTINT6_Pos)
+#define EIC_INTENSET_EXTINT7_Pos 7 /**< \brief (EIC_INTENSET) External Interrupt 7 Enable */
+#define EIC_INTENSET_EXTINT7 (1 << EIC_INTENSET_EXTINT7_Pos)
+#define EIC_INTENSET_EXTINT8_Pos 8 /**< \brief (EIC_INTENSET) External Interrupt 8 Enable */
+#define EIC_INTENSET_EXTINT8 (1 << EIC_INTENSET_EXTINT8_Pos)
+#define EIC_INTENSET_EXTINT9_Pos 9 /**< \brief (EIC_INTENSET) External Interrupt 9 Enable */
+#define EIC_INTENSET_EXTINT9 (1 << EIC_INTENSET_EXTINT9_Pos)
+#define EIC_INTENSET_EXTINT10_Pos 10 /**< \brief (EIC_INTENSET) External Interrupt 10 Enable */
+#define EIC_INTENSET_EXTINT10 (1 << EIC_INTENSET_EXTINT10_Pos)
+#define EIC_INTENSET_EXTINT11_Pos 11 /**< \brief (EIC_INTENSET) External Interrupt 11 Enable */
+#define EIC_INTENSET_EXTINT11 (1 << EIC_INTENSET_EXTINT11_Pos)
+#define EIC_INTENSET_EXTINT12_Pos 12 /**< \brief (EIC_INTENSET) External Interrupt 12 Enable */
+#define EIC_INTENSET_EXTINT12 (1 << EIC_INTENSET_EXTINT12_Pos)
+#define EIC_INTENSET_EXTINT13_Pos 13 /**< \brief (EIC_INTENSET) External Interrupt 13 Enable */
+#define EIC_INTENSET_EXTINT13 (1 << EIC_INTENSET_EXTINT13_Pos)
+#define EIC_INTENSET_EXTINT14_Pos 14 /**< \brief (EIC_INTENSET) External Interrupt 14 Enable */
+#define EIC_INTENSET_EXTINT14 (1 << EIC_INTENSET_EXTINT14_Pos)
+#define EIC_INTENSET_EXTINT15_Pos 15 /**< \brief (EIC_INTENSET) External Interrupt 15 Enable */
+#define EIC_INTENSET_EXTINT15 (1 << EIC_INTENSET_EXTINT15_Pos)
+#define EIC_INTENSET_EXTINT_Pos 0 /**< \brief (EIC_INTENSET) External Interrupt x Enable */
+#define EIC_INTENSET_EXTINT_Msk (0xFFFFul << EIC_INTENSET_EXTINT_Pos)
+#define EIC_INTENSET_EXTINT(value) (EIC_INTENSET_EXTINT_Msk & ((value) << EIC_INTENSET_EXTINT_Pos))
+#define EIC_INTENSET_MASK 0x0000FFFFul /**< \brief (EIC_INTENSET) MASK Register */
+
+/* -------- EIC_INTFLAG : (EIC Offset: 0x10) (R/W 32) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 */
+ __I uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 */
+ __I uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 */
+ __I uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 */
+ __I uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 */
+ __I uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 */
+ __I uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 */
+ __I uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 */
+ __I uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 */
+ __I uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 */
+ __I uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 */
+ __I uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 */
+ __I uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 */
+ __I uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 */
+ __I uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 */
+ __I uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 */
+ __I uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ __I uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x */
+ __I uint32_t :16; /*!< bit: 16..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} EIC_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_INTFLAG_OFFSET 0x10 /**< \brief (EIC_INTFLAG offset) Interrupt Flag Status and Clear */
+#define EIC_INTFLAG_RESETVALUE 0x00000000ul /**< \brief (EIC_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define EIC_INTFLAG_EXTINT0_Pos 0 /**< \brief (EIC_INTFLAG) External Interrupt 0 */
+#define EIC_INTFLAG_EXTINT0 (1 << EIC_INTFLAG_EXTINT0_Pos)
+#define EIC_INTFLAG_EXTINT1_Pos 1 /**< \brief (EIC_INTFLAG) External Interrupt 1 */
+#define EIC_INTFLAG_EXTINT1 (1 << EIC_INTFLAG_EXTINT1_Pos)
+#define EIC_INTFLAG_EXTINT2_Pos 2 /**< \brief (EIC_INTFLAG) External Interrupt 2 */
+#define EIC_INTFLAG_EXTINT2 (1 << EIC_INTFLAG_EXTINT2_Pos)
+#define EIC_INTFLAG_EXTINT3_Pos 3 /**< \brief (EIC_INTFLAG) External Interrupt 3 */
+#define EIC_INTFLAG_EXTINT3 (1 << EIC_INTFLAG_EXTINT3_Pos)
+#define EIC_INTFLAG_EXTINT4_Pos 4 /**< \brief (EIC_INTFLAG) External Interrupt 4 */
+#define EIC_INTFLAG_EXTINT4 (1 << EIC_INTFLAG_EXTINT4_Pos)
+#define EIC_INTFLAG_EXTINT5_Pos 5 /**< \brief (EIC_INTFLAG) External Interrupt 5 */
+#define EIC_INTFLAG_EXTINT5 (1 << EIC_INTFLAG_EXTINT5_Pos)
+#define EIC_INTFLAG_EXTINT6_Pos 6 /**< \brief (EIC_INTFLAG) External Interrupt 6 */
+#define EIC_INTFLAG_EXTINT6 (1 << EIC_INTFLAG_EXTINT6_Pos)
+#define EIC_INTFLAG_EXTINT7_Pos 7 /**< \brief (EIC_INTFLAG) External Interrupt 7 */
+#define EIC_INTFLAG_EXTINT7 (1 << EIC_INTFLAG_EXTINT7_Pos)
+#define EIC_INTFLAG_EXTINT8_Pos 8 /**< \brief (EIC_INTFLAG) External Interrupt 8 */
+#define EIC_INTFLAG_EXTINT8 (1 << EIC_INTFLAG_EXTINT8_Pos)
+#define EIC_INTFLAG_EXTINT9_Pos 9 /**< \brief (EIC_INTFLAG) External Interrupt 9 */
+#define EIC_INTFLAG_EXTINT9 (1 << EIC_INTFLAG_EXTINT9_Pos)
+#define EIC_INTFLAG_EXTINT10_Pos 10 /**< \brief (EIC_INTFLAG) External Interrupt 10 */
+#define EIC_INTFLAG_EXTINT10 (1 << EIC_INTFLAG_EXTINT10_Pos)
+#define EIC_INTFLAG_EXTINT11_Pos 11 /**< \brief (EIC_INTFLAG) External Interrupt 11 */
+#define EIC_INTFLAG_EXTINT11 (1 << EIC_INTFLAG_EXTINT11_Pos)
+#define EIC_INTFLAG_EXTINT12_Pos 12 /**< \brief (EIC_INTFLAG) External Interrupt 12 */
+#define EIC_INTFLAG_EXTINT12 (1 << EIC_INTFLAG_EXTINT12_Pos)
+#define EIC_INTFLAG_EXTINT13_Pos 13 /**< \brief (EIC_INTFLAG) External Interrupt 13 */
+#define EIC_INTFLAG_EXTINT13 (1 << EIC_INTFLAG_EXTINT13_Pos)
+#define EIC_INTFLAG_EXTINT14_Pos 14 /**< \brief (EIC_INTFLAG) External Interrupt 14 */
+#define EIC_INTFLAG_EXTINT14 (1 << EIC_INTFLAG_EXTINT14_Pos)
+#define EIC_INTFLAG_EXTINT15_Pos 15 /**< \brief (EIC_INTFLAG) External Interrupt 15 */
+#define EIC_INTFLAG_EXTINT15 (1 << EIC_INTFLAG_EXTINT15_Pos)
+#define EIC_INTFLAG_EXTINT_Pos 0 /**< \brief (EIC_INTFLAG) External Interrupt x */
+#define EIC_INTFLAG_EXTINT_Msk (0xFFFFul << EIC_INTFLAG_EXTINT_Pos)
+#define EIC_INTFLAG_EXTINT(value) (EIC_INTFLAG_EXTINT_Msk & ((value) << EIC_INTFLAG_EXTINT_Pos))
+#define EIC_INTFLAG_MASK 0x0000FFFFul /**< \brief (EIC_INTFLAG) MASK Register */
+
+/* -------- EIC_WAKEUP : (EIC Offset: 0x14) (R/W 32) Wake-Up Enable -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t WAKEUPEN0:1; /*!< bit: 0 External Interrupt 0 Wake-up Enable */
+ uint32_t WAKEUPEN1:1; /*!< bit: 1 External Interrupt 1 Wake-up Enable */
+ uint32_t WAKEUPEN2:1; /*!< bit: 2 External Interrupt 2 Wake-up Enable */
+ uint32_t WAKEUPEN3:1; /*!< bit: 3 External Interrupt 3 Wake-up Enable */
+ uint32_t WAKEUPEN4:1; /*!< bit: 4 External Interrupt 4 Wake-up Enable */
+ uint32_t WAKEUPEN5:1; /*!< bit: 5 External Interrupt 5 Wake-up Enable */
+ uint32_t WAKEUPEN6:1; /*!< bit: 6 External Interrupt 6 Wake-up Enable */
+ uint32_t WAKEUPEN7:1; /*!< bit: 7 External Interrupt 7 Wake-up Enable */
+ uint32_t WAKEUPEN8:1; /*!< bit: 8 External Interrupt 8 Wake-up Enable */
+ uint32_t WAKEUPEN9:1; /*!< bit: 9 External Interrupt 9 Wake-up Enable */
+ uint32_t WAKEUPEN10:1; /*!< bit: 10 External Interrupt 10 Wake-up Enable */
+ uint32_t WAKEUPEN11:1; /*!< bit: 11 External Interrupt 11 Wake-up Enable */
+ uint32_t WAKEUPEN12:1; /*!< bit: 12 External Interrupt 12 Wake-up Enable */
+ uint32_t WAKEUPEN13:1; /*!< bit: 13 External Interrupt 13 Wake-up Enable */
+ uint32_t WAKEUPEN14:1; /*!< bit: 14 External Interrupt 14 Wake-up Enable */
+ uint32_t WAKEUPEN15:1; /*!< bit: 15 External Interrupt 15 Wake-up Enable */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t WAKEUPEN:16; /*!< bit: 0..15 External Interrupt x Wake-up Enable */
+ uint32_t :16; /*!< bit: 16..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} EIC_WAKEUP_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_WAKEUP_OFFSET 0x14 /**< \brief (EIC_WAKEUP offset) Wake-Up Enable */
+#define EIC_WAKEUP_RESETVALUE 0x00000000ul /**< \brief (EIC_WAKEUP reset_value) Wake-Up Enable */
+
+#define EIC_WAKEUP_WAKEUPEN0_Pos 0 /**< \brief (EIC_WAKEUP) External Interrupt 0 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN0 (1 << EIC_WAKEUP_WAKEUPEN0_Pos)
+#define EIC_WAKEUP_WAKEUPEN1_Pos 1 /**< \brief (EIC_WAKEUP) External Interrupt 1 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN1 (1 << EIC_WAKEUP_WAKEUPEN1_Pos)
+#define EIC_WAKEUP_WAKEUPEN2_Pos 2 /**< \brief (EIC_WAKEUP) External Interrupt 2 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN2 (1 << EIC_WAKEUP_WAKEUPEN2_Pos)
+#define EIC_WAKEUP_WAKEUPEN3_Pos 3 /**< \brief (EIC_WAKEUP) External Interrupt 3 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN3 (1 << EIC_WAKEUP_WAKEUPEN3_Pos)
+#define EIC_WAKEUP_WAKEUPEN4_Pos 4 /**< \brief (EIC_WAKEUP) External Interrupt 4 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN4 (1 << EIC_WAKEUP_WAKEUPEN4_Pos)
+#define EIC_WAKEUP_WAKEUPEN5_Pos 5 /**< \brief (EIC_WAKEUP) External Interrupt 5 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN5 (1 << EIC_WAKEUP_WAKEUPEN5_Pos)
+#define EIC_WAKEUP_WAKEUPEN6_Pos 6 /**< \brief (EIC_WAKEUP) External Interrupt 6 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN6 (1 << EIC_WAKEUP_WAKEUPEN6_Pos)
+#define EIC_WAKEUP_WAKEUPEN7_Pos 7 /**< \brief (EIC_WAKEUP) External Interrupt 7 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN7 (1 << EIC_WAKEUP_WAKEUPEN7_Pos)
+#define EIC_WAKEUP_WAKEUPEN8_Pos 8 /**< \brief (EIC_WAKEUP) External Interrupt 8 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN8 (1 << EIC_WAKEUP_WAKEUPEN8_Pos)
+#define EIC_WAKEUP_WAKEUPEN9_Pos 9 /**< \brief (EIC_WAKEUP) External Interrupt 9 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN9 (1 << EIC_WAKEUP_WAKEUPEN9_Pos)
+#define EIC_WAKEUP_WAKEUPEN10_Pos 10 /**< \brief (EIC_WAKEUP) External Interrupt 10 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN10 (1 << EIC_WAKEUP_WAKEUPEN10_Pos)
+#define EIC_WAKEUP_WAKEUPEN11_Pos 11 /**< \brief (EIC_WAKEUP) External Interrupt 11 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN11 (1 << EIC_WAKEUP_WAKEUPEN11_Pos)
+#define EIC_WAKEUP_WAKEUPEN12_Pos 12 /**< \brief (EIC_WAKEUP) External Interrupt 12 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN12 (1 << EIC_WAKEUP_WAKEUPEN12_Pos)
+#define EIC_WAKEUP_WAKEUPEN13_Pos 13 /**< \brief (EIC_WAKEUP) External Interrupt 13 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN13 (1 << EIC_WAKEUP_WAKEUPEN13_Pos)
+#define EIC_WAKEUP_WAKEUPEN14_Pos 14 /**< \brief (EIC_WAKEUP) External Interrupt 14 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN14 (1 << EIC_WAKEUP_WAKEUPEN14_Pos)
+#define EIC_WAKEUP_WAKEUPEN15_Pos 15 /**< \brief (EIC_WAKEUP) External Interrupt 15 Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN15 (1 << EIC_WAKEUP_WAKEUPEN15_Pos)
+#define EIC_WAKEUP_WAKEUPEN_Pos 0 /**< \brief (EIC_WAKEUP) External Interrupt x Wake-up Enable */
+#define EIC_WAKEUP_WAKEUPEN_Msk (0xFFFFul << EIC_WAKEUP_WAKEUPEN_Pos)
+#define EIC_WAKEUP_WAKEUPEN(value) (EIC_WAKEUP_WAKEUPEN_Msk & ((value) << EIC_WAKEUP_WAKEUPEN_Pos))
+#define EIC_WAKEUP_MASK 0x0000FFFFul /**< \brief (EIC_WAKEUP) MASK Register */
+
+/* -------- EIC_CONFIG : (EIC Offset: 0x18) (R/W 32) Configuration n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SENSE0:3; /*!< bit: 0.. 2 Input Sense 0 Configuration */
+ uint32_t FILTEN0:1; /*!< bit: 3 Filter 0 Enable */
+ uint32_t SENSE1:3; /*!< bit: 4.. 6 Input Sense 1 Configuration */
+ uint32_t FILTEN1:1; /*!< bit: 7 Filter 1 Enable */
+ uint32_t SENSE2:3; /*!< bit: 8..10 Input Sense 2 Configuration */
+ uint32_t FILTEN2:1; /*!< bit: 11 Filter 2 Enable */
+ uint32_t SENSE3:3; /*!< bit: 12..14 Input Sense 3 Configuration */
+ uint32_t FILTEN3:1; /*!< bit: 15 Filter 3 Enable */
+ uint32_t SENSE4:3; /*!< bit: 16..18 Input Sense 4 Configuration */
+ uint32_t FILTEN4:1; /*!< bit: 19 Filter 4 Enable */
+ uint32_t SENSE5:3; /*!< bit: 20..22 Input Sense 5 Configuration */
+ uint32_t FILTEN5:1; /*!< bit: 23 Filter 5 Enable */
+ uint32_t SENSE6:3; /*!< bit: 24..26 Input Sense 6 Configuration */
+ uint32_t FILTEN6:1; /*!< bit: 27 Filter 6 Enable */
+ uint32_t SENSE7:3; /*!< bit: 28..30 Input Sense 7 Configuration */
+ uint32_t FILTEN7:1; /*!< bit: 31 Filter 7 Enable */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} EIC_CONFIG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EIC_CONFIG_OFFSET 0x18 /**< \brief (EIC_CONFIG offset) Configuration n */
+#define EIC_CONFIG_RESETVALUE 0x00000000ul /**< \brief (EIC_CONFIG reset_value) Configuration n */
+
+#define EIC_CONFIG_SENSE0_Pos 0 /**< \brief (EIC_CONFIG) Input Sense 0 Configuration */
+#define EIC_CONFIG_SENSE0_Msk (0x7ul << EIC_CONFIG_SENSE0_Pos)
+#define EIC_CONFIG_SENSE0(value) (EIC_CONFIG_SENSE0_Msk & ((value) << EIC_CONFIG_SENSE0_Pos))
+#define EIC_CONFIG_SENSE0_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */
+#define EIC_CONFIG_SENSE0_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising-edge detection */
+#define EIC_CONFIG_SENSE0_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling-edge detection */
+#define EIC_CONFIG_SENSE0_BOTH_Val 0x3ul /**< \brief (EIC_CONFIG) Both-edges detection */
+#define EIC_CONFIG_SENSE0_HIGH_Val 0x4ul /**< \brief (EIC_CONFIG) High-level detection */
+#define EIC_CONFIG_SENSE0_LOW_Val 0x5ul /**< \brief (EIC_CONFIG) Low-level detection */
+#define EIC_CONFIG_SENSE0_NONE (EIC_CONFIG_SENSE0_NONE_Val << EIC_CONFIG_SENSE0_Pos)
+#define EIC_CONFIG_SENSE0_RISE (EIC_CONFIG_SENSE0_RISE_Val << EIC_CONFIG_SENSE0_Pos)
+#define EIC_CONFIG_SENSE0_FALL (EIC_CONFIG_SENSE0_FALL_Val << EIC_CONFIG_SENSE0_Pos)
+#define EIC_CONFIG_SENSE0_BOTH (EIC_CONFIG_SENSE0_BOTH_Val << EIC_CONFIG_SENSE0_Pos)
+#define EIC_CONFIG_SENSE0_HIGH (EIC_CONFIG_SENSE0_HIGH_Val << EIC_CONFIG_SENSE0_Pos)
+#define EIC_CONFIG_SENSE0_LOW (EIC_CONFIG_SENSE0_LOW_Val << EIC_CONFIG_SENSE0_Pos)
+#define EIC_CONFIG_FILTEN0_Pos 3 /**< \brief (EIC_CONFIG) Filter 0 Enable */
+#define EIC_CONFIG_FILTEN0 (0x1ul << EIC_CONFIG_FILTEN0_Pos)
+#define EIC_CONFIG_SENSE1_Pos 4 /**< \brief (EIC_CONFIG) Input Sense 1 Configuration */
+#define EIC_CONFIG_SENSE1_Msk (0x7ul << EIC_CONFIG_SENSE1_Pos)
+#define EIC_CONFIG_SENSE1(value) (EIC_CONFIG_SENSE1_Msk & ((value) << EIC_CONFIG_SENSE1_Pos))
+#define EIC_CONFIG_SENSE1_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */
+#define EIC_CONFIG_SENSE1_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */
+#define EIC_CONFIG_SENSE1_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */
+#define EIC_CONFIG_SENSE1_BOTH_Val 0x3ul /**< \brief (EIC_CONFIG) Both edges detection */
+#define EIC_CONFIG_SENSE1_HIGH_Val 0x4ul /**< \brief (EIC_CONFIG) High level detection */
+#define EIC_CONFIG_SENSE1_LOW_Val 0x5ul /**< \brief (EIC_CONFIG) Low level detection */
+#define EIC_CONFIG_SENSE1_NONE (EIC_CONFIG_SENSE1_NONE_Val << EIC_CONFIG_SENSE1_Pos)
+#define EIC_CONFIG_SENSE1_RISE (EIC_CONFIG_SENSE1_RISE_Val << EIC_CONFIG_SENSE1_Pos)
+#define EIC_CONFIG_SENSE1_FALL (EIC_CONFIG_SENSE1_FALL_Val << EIC_CONFIG_SENSE1_Pos)
+#define EIC_CONFIG_SENSE1_BOTH (EIC_CONFIG_SENSE1_BOTH_Val << EIC_CONFIG_SENSE1_Pos)
+#define EIC_CONFIG_SENSE1_HIGH (EIC_CONFIG_SENSE1_HIGH_Val << EIC_CONFIG_SENSE1_Pos)
+#define EIC_CONFIG_SENSE1_LOW (EIC_CONFIG_SENSE1_LOW_Val << EIC_CONFIG_SENSE1_Pos)
+#define EIC_CONFIG_FILTEN1_Pos 7 /**< \brief (EIC_CONFIG) Filter 1 Enable */
+#define EIC_CONFIG_FILTEN1 (0x1ul << EIC_CONFIG_FILTEN1_Pos)
+#define EIC_CONFIG_SENSE2_Pos 8 /**< \brief (EIC_CONFIG) Input Sense 2 Configuration */
+#define EIC_CONFIG_SENSE2_Msk (0x7ul << EIC_CONFIG_SENSE2_Pos)
+#define EIC_CONFIG_SENSE2(value) (EIC_CONFIG_SENSE2_Msk & ((value) << EIC_CONFIG_SENSE2_Pos))
+#define EIC_CONFIG_SENSE2_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */
+#define EIC_CONFIG_SENSE2_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */
+#define EIC_CONFIG_SENSE2_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */
+#define EIC_CONFIG_SENSE2_BOTH_Val 0x3ul /**< \brief (EIC_CONFIG) Both edges detection */
+#define EIC_CONFIG_SENSE2_HIGH_Val 0x4ul /**< \brief (EIC_CONFIG) High level detection */
+#define EIC_CONFIG_SENSE2_LOW_Val 0x5ul /**< \brief (EIC_CONFIG) Low level detection */
+#define EIC_CONFIG_SENSE2_NONE (EIC_CONFIG_SENSE2_NONE_Val << EIC_CONFIG_SENSE2_Pos)
+#define EIC_CONFIG_SENSE2_RISE (EIC_CONFIG_SENSE2_RISE_Val << EIC_CONFIG_SENSE2_Pos)
+#define EIC_CONFIG_SENSE2_FALL (EIC_CONFIG_SENSE2_FALL_Val << EIC_CONFIG_SENSE2_Pos)
+#define EIC_CONFIG_SENSE2_BOTH (EIC_CONFIG_SENSE2_BOTH_Val << EIC_CONFIG_SENSE2_Pos)
+#define EIC_CONFIG_SENSE2_HIGH (EIC_CONFIG_SENSE2_HIGH_Val << EIC_CONFIG_SENSE2_Pos)
+#define EIC_CONFIG_SENSE2_LOW (EIC_CONFIG_SENSE2_LOW_Val << EIC_CONFIG_SENSE2_Pos)
+#define EIC_CONFIG_FILTEN2_Pos 11 /**< \brief (EIC_CONFIG) Filter 2 Enable */
+#define EIC_CONFIG_FILTEN2 (0x1ul << EIC_CONFIG_FILTEN2_Pos)
+#define EIC_CONFIG_SENSE3_Pos 12 /**< \brief (EIC_CONFIG) Input Sense 3 Configuration */
+#define EIC_CONFIG_SENSE3_Msk (0x7ul << EIC_CONFIG_SENSE3_Pos)
+#define EIC_CONFIG_SENSE3(value) (EIC_CONFIG_SENSE3_Msk & ((value) << EIC_CONFIG_SENSE3_Pos))
+#define EIC_CONFIG_SENSE3_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */
+#define EIC_CONFIG_SENSE3_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */
+#define EIC_CONFIG_SENSE3_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */
+#define EIC_CONFIG_SENSE3_BOTH_Val 0x3ul /**< \brief (EIC_CONFIG) Both edges detection */
+#define EIC_CONFIG_SENSE3_HIGH_Val 0x4ul /**< \brief (EIC_CONFIG) High level detection */
+#define EIC_CONFIG_SENSE3_LOW_Val 0x5ul /**< \brief (EIC_CONFIG) Low level detection */
+#define EIC_CONFIG_SENSE3_NONE (EIC_CONFIG_SENSE3_NONE_Val << EIC_CONFIG_SENSE3_Pos)
+#define EIC_CONFIG_SENSE3_RISE (EIC_CONFIG_SENSE3_RISE_Val << EIC_CONFIG_SENSE3_Pos)
+#define EIC_CONFIG_SENSE3_FALL (EIC_CONFIG_SENSE3_FALL_Val << EIC_CONFIG_SENSE3_Pos)
+#define EIC_CONFIG_SENSE3_BOTH (EIC_CONFIG_SENSE3_BOTH_Val << EIC_CONFIG_SENSE3_Pos)
+#define EIC_CONFIG_SENSE3_HIGH (EIC_CONFIG_SENSE3_HIGH_Val << EIC_CONFIG_SENSE3_Pos)
+#define EIC_CONFIG_SENSE3_LOW (EIC_CONFIG_SENSE3_LOW_Val << EIC_CONFIG_SENSE3_Pos)
+#define EIC_CONFIG_FILTEN3_Pos 15 /**< \brief (EIC_CONFIG) Filter 3 Enable */
+#define EIC_CONFIG_FILTEN3 (0x1ul << EIC_CONFIG_FILTEN3_Pos)
+#define EIC_CONFIG_SENSE4_Pos 16 /**< \brief (EIC_CONFIG) Input Sense 4 Configuration */
+#define EIC_CONFIG_SENSE4_Msk (0x7ul << EIC_CONFIG_SENSE4_Pos)
+#define EIC_CONFIG_SENSE4(value) (EIC_CONFIG_SENSE4_Msk & ((value) << EIC_CONFIG_SENSE4_Pos))
+#define EIC_CONFIG_SENSE4_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */
+#define EIC_CONFIG_SENSE4_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */
+#define EIC_CONFIG_SENSE4_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */
+#define EIC_CONFIG_SENSE4_BOTH_Val 0x3ul /**< \brief (EIC_CONFIG) Both edges detection */
+#define EIC_CONFIG_SENSE4_HIGH_Val 0x4ul /**< \brief (EIC_CONFIG) High level detection */
+#define EIC_CONFIG_SENSE4_LOW_Val 0x5ul /**< \brief (EIC_CONFIG) Low level detection */
+#define EIC_CONFIG_SENSE4_NONE (EIC_CONFIG_SENSE4_NONE_Val << EIC_CONFIG_SENSE4_Pos)
+#define EIC_CONFIG_SENSE4_RISE (EIC_CONFIG_SENSE4_RISE_Val << EIC_CONFIG_SENSE4_Pos)
+#define EIC_CONFIG_SENSE4_FALL (EIC_CONFIG_SENSE4_FALL_Val << EIC_CONFIG_SENSE4_Pos)
+#define EIC_CONFIG_SENSE4_BOTH (EIC_CONFIG_SENSE4_BOTH_Val << EIC_CONFIG_SENSE4_Pos)
+#define EIC_CONFIG_SENSE4_HIGH (EIC_CONFIG_SENSE4_HIGH_Val << EIC_CONFIG_SENSE4_Pos)
+#define EIC_CONFIG_SENSE4_LOW (EIC_CONFIG_SENSE4_LOW_Val << EIC_CONFIG_SENSE4_Pos)
+#define EIC_CONFIG_FILTEN4_Pos 19 /**< \brief (EIC_CONFIG) Filter 4 Enable */
+#define EIC_CONFIG_FILTEN4 (0x1ul << EIC_CONFIG_FILTEN4_Pos)
+#define EIC_CONFIG_SENSE5_Pos 20 /**< \brief (EIC_CONFIG) Input Sense 5 Configuration */
+#define EIC_CONFIG_SENSE5_Msk (0x7ul << EIC_CONFIG_SENSE5_Pos)
+#define EIC_CONFIG_SENSE5(value) (EIC_CONFIG_SENSE5_Msk & ((value) << EIC_CONFIG_SENSE5_Pos))
+#define EIC_CONFIG_SENSE5_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */
+#define EIC_CONFIG_SENSE5_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */
+#define EIC_CONFIG_SENSE5_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */
+#define EIC_CONFIG_SENSE5_BOTH_Val 0x3ul /**< \brief (EIC_CONFIG) Both edges detection */
+#define EIC_CONFIG_SENSE5_HIGH_Val 0x4ul /**< \brief (EIC_CONFIG) High level detection */
+#define EIC_CONFIG_SENSE5_LOW_Val 0x5ul /**< \brief (EIC_CONFIG) Low level detection */
+#define EIC_CONFIG_SENSE5_NONE (EIC_CONFIG_SENSE5_NONE_Val << EIC_CONFIG_SENSE5_Pos)
+#define EIC_CONFIG_SENSE5_RISE (EIC_CONFIG_SENSE5_RISE_Val << EIC_CONFIG_SENSE5_Pos)
+#define EIC_CONFIG_SENSE5_FALL (EIC_CONFIG_SENSE5_FALL_Val << EIC_CONFIG_SENSE5_Pos)
+#define EIC_CONFIG_SENSE5_BOTH (EIC_CONFIG_SENSE5_BOTH_Val << EIC_CONFIG_SENSE5_Pos)
+#define EIC_CONFIG_SENSE5_HIGH (EIC_CONFIG_SENSE5_HIGH_Val << EIC_CONFIG_SENSE5_Pos)
+#define EIC_CONFIG_SENSE5_LOW (EIC_CONFIG_SENSE5_LOW_Val << EIC_CONFIG_SENSE5_Pos)
+#define EIC_CONFIG_FILTEN5_Pos 23 /**< \brief (EIC_CONFIG) Filter 5 Enable */
+#define EIC_CONFIG_FILTEN5 (0x1ul << EIC_CONFIG_FILTEN5_Pos)
+#define EIC_CONFIG_SENSE6_Pos 24 /**< \brief (EIC_CONFIG) Input Sense 6 Configuration */
+#define EIC_CONFIG_SENSE6_Msk (0x7ul << EIC_CONFIG_SENSE6_Pos)
+#define EIC_CONFIG_SENSE6(value) (EIC_CONFIG_SENSE6_Msk & ((value) << EIC_CONFIG_SENSE6_Pos))
+#define EIC_CONFIG_SENSE6_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */
+#define EIC_CONFIG_SENSE6_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */
+#define EIC_CONFIG_SENSE6_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */
+#define EIC_CONFIG_SENSE6_BOTH_Val 0x3ul /**< \brief (EIC_CONFIG) Both edges detection */
+#define EIC_CONFIG_SENSE6_HIGH_Val 0x4ul /**< \brief (EIC_CONFIG) High level detection */
+#define EIC_CONFIG_SENSE6_LOW_Val 0x5ul /**< \brief (EIC_CONFIG) Low level detection */
+#define EIC_CONFIG_SENSE6_NONE (EIC_CONFIG_SENSE6_NONE_Val << EIC_CONFIG_SENSE6_Pos)
+#define EIC_CONFIG_SENSE6_RISE (EIC_CONFIG_SENSE6_RISE_Val << EIC_CONFIG_SENSE6_Pos)
+#define EIC_CONFIG_SENSE6_FALL (EIC_CONFIG_SENSE6_FALL_Val << EIC_CONFIG_SENSE6_Pos)
+#define EIC_CONFIG_SENSE6_BOTH (EIC_CONFIG_SENSE6_BOTH_Val << EIC_CONFIG_SENSE6_Pos)
+#define EIC_CONFIG_SENSE6_HIGH (EIC_CONFIG_SENSE6_HIGH_Val << EIC_CONFIG_SENSE6_Pos)
+#define EIC_CONFIG_SENSE6_LOW (EIC_CONFIG_SENSE6_LOW_Val << EIC_CONFIG_SENSE6_Pos)
+#define EIC_CONFIG_FILTEN6_Pos 27 /**< \brief (EIC_CONFIG) Filter 6 Enable */
+#define EIC_CONFIG_FILTEN6 (0x1ul << EIC_CONFIG_FILTEN6_Pos)
+#define EIC_CONFIG_SENSE7_Pos 28 /**< \brief (EIC_CONFIG) Input Sense 7 Configuration */
+#define EIC_CONFIG_SENSE7_Msk (0x7ul << EIC_CONFIG_SENSE7_Pos)
+#define EIC_CONFIG_SENSE7(value) (EIC_CONFIG_SENSE7_Msk & ((value) << EIC_CONFIG_SENSE7_Pos))
+#define EIC_CONFIG_SENSE7_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */
+#define EIC_CONFIG_SENSE7_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */
+#define EIC_CONFIG_SENSE7_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */
+#define EIC_CONFIG_SENSE7_BOTH_Val 0x3ul /**< \brief (EIC_CONFIG) Both edges detection */
+#define EIC_CONFIG_SENSE7_HIGH_Val 0x4ul /**< \brief (EIC_CONFIG) High level detection */
+#define EIC_CONFIG_SENSE7_LOW_Val 0x5ul /**< \brief (EIC_CONFIG) Low level detection */
+#define EIC_CONFIG_SENSE7_NONE (EIC_CONFIG_SENSE7_NONE_Val << EIC_CONFIG_SENSE7_Pos)
+#define EIC_CONFIG_SENSE7_RISE (EIC_CONFIG_SENSE7_RISE_Val << EIC_CONFIG_SENSE7_Pos)
+#define EIC_CONFIG_SENSE7_FALL (EIC_CONFIG_SENSE7_FALL_Val << EIC_CONFIG_SENSE7_Pos)
+#define EIC_CONFIG_SENSE7_BOTH (EIC_CONFIG_SENSE7_BOTH_Val << EIC_CONFIG_SENSE7_Pos)
+#define EIC_CONFIG_SENSE7_HIGH (EIC_CONFIG_SENSE7_HIGH_Val << EIC_CONFIG_SENSE7_Pos)
+#define EIC_CONFIG_SENSE7_LOW (EIC_CONFIG_SENSE7_LOW_Val << EIC_CONFIG_SENSE7_Pos)
+#define EIC_CONFIG_FILTEN7_Pos 31 /**< \brief (EIC_CONFIG) Filter 7 Enable */
+#define EIC_CONFIG_FILTEN7 (0x1ul << EIC_CONFIG_FILTEN7_Pos)
+#define EIC_CONFIG_MASK 0xFFFFFFFFul /**< \brief (EIC_CONFIG) MASK Register */
+
+/** \brief EIC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO EIC_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 8) Control */
+ __I EIC_STATUS_Type STATUS; /**< \brief Offset: 0x01 (R/ 8) Status */
+ __IO EIC_NMICTRL_Type NMICTRL; /**< \brief Offset: 0x02 (R/W 8) Non-Maskable Interrupt Control */
+ __IO EIC_NMIFLAG_Type NMIFLAG; /**< \brief Offset: 0x03 (R/W 8) Non-Maskable Interrupt Flag Status and Clear */
+ __IO EIC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 32) Event Control */
+ __IO EIC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 32) Interrupt Enable Clear */
+ __IO EIC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0C (R/W 32) Interrupt Enable Set */
+ __IO EIC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x10 (R/W 32) Interrupt Flag Status and Clear */
+ __IO EIC_WAKEUP_Type WAKEUP; /**< \brief Offset: 0x14 (R/W 32) Wake-Up Enable */
+ __IO EIC_CONFIG_Type CONFIG[2]; /**< \brief Offset: 0x18 (R/W 32) Configuration n */
+} Eic;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_EIC_COMPONENT_ */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/component/evsys.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/component/evsys.h
new file mode 100644
index 0000000000000000000000000000000000000000..4f2ada1d3faed54afdac4a772c15e505e8683a32
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/component/evsys.h
@@ -0,0 +1,604 @@
+/**
+ * \file
+ *
+ * \brief Component description for EVSYS
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_EVSYS_COMPONENT_
+#define _SAMD21_EVSYS_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR EVSYS */
+/* ========================================================================== */
+/** \addtogroup SAMD21_EVSYS Event System Interface */
+/*@{*/
+
+#define EVSYS_U2208
+#define REV_EVSYS 0x101
+
+/* -------- EVSYS_CTRL : (EVSYS Offset: 0x00) ( /W 8) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t :3; /*!< bit: 1.. 3 Reserved */
+ uint8_t GCLKREQ:1; /*!< bit: 4 Generic Clock Requests */
+ uint8_t :3; /*!< bit: 5.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} EVSYS_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_CTRL_OFFSET 0x00 /**< \brief (EVSYS_CTRL offset) Control */
+#define EVSYS_CTRL_RESETVALUE 0x00ul /**< \brief (EVSYS_CTRL reset_value) Control */
+
+#define EVSYS_CTRL_SWRST_Pos 0 /**< \brief (EVSYS_CTRL) Software Reset */
+#define EVSYS_CTRL_SWRST (0x1ul << EVSYS_CTRL_SWRST_Pos)
+#define EVSYS_CTRL_GCLKREQ_Pos 4 /**< \brief (EVSYS_CTRL) Generic Clock Requests */
+#define EVSYS_CTRL_GCLKREQ (0x1ul << EVSYS_CTRL_GCLKREQ_Pos)
+#define EVSYS_CTRL_MASK 0x11ul /**< \brief (EVSYS_CTRL) MASK Register */
+
+/* -------- EVSYS_CHANNEL : (EVSYS Offset: 0x04) (R/W 32) Channel -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CHANNEL:4; /*!< bit: 0.. 3 Channel Selection */
+ uint32_t :4; /*!< bit: 4.. 7 Reserved */
+ uint32_t SWEVT:1; /*!< bit: 8 Software Event */
+ uint32_t :7; /*!< bit: 9..15 Reserved */
+ uint32_t EVGEN:7; /*!< bit: 16..22 Event Generator Selection */
+ uint32_t :1; /*!< bit: 23 Reserved */
+ uint32_t PATH:2; /*!< bit: 24..25 Path Selection */
+ uint32_t EDGSEL:2; /*!< bit: 26..27 Edge Detection Selection */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} EVSYS_CHANNEL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_CHANNEL_OFFSET 0x04 /**< \brief (EVSYS_CHANNEL offset) Channel */
+#define EVSYS_CHANNEL_RESETVALUE 0x00000000ul /**< \brief (EVSYS_CHANNEL reset_value) Channel */
+
+#define EVSYS_CHANNEL_CHANNEL_Pos 0 /**< \brief (EVSYS_CHANNEL) Channel Selection */
+#define EVSYS_CHANNEL_CHANNEL_Msk (0xFul << EVSYS_CHANNEL_CHANNEL_Pos)
+#define EVSYS_CHANNEL_CHANNEL(value) (EVSYS_CHANNEL_CHANNEL_Msk & ((value) << EVSYS_CHANNEL_CHANNEL_Pos))
+#define EVSYS_CHANNEL_SWEVT_Pos 8 /**< \brief (EVSYS_CHANNEL) Software Event */
+#define EVSYS_CHANNEL_SWEVT (0x1ul << EVSYS_CHANNEL_SWEVT_Pos)
+#define EVSYS_CHANNEL_EVGEN_Pos 16 /**< \brief (EVSYS_CHANNEL) Event Generator Selection */
+#define EVSYS_CHANNEL_EVGEN_Msk (0x7Ful << EVSYS_CHANNEL_EVGEN_Pos)
+#define EVSYS_CHANNEL_EVGEN(value) (EVSYS_CHANNEL_EVGEN_Msk & ((value) << EVSYS_CHANNEL_EVGEN_Pos))
+#define EVSYS_CHANNEL_PATH_Pos 24 /**< \brief (EVSYS_CHANNEL) Path Selection */
+#define EVSYS_CHANNEL_PATH_Msk (0x3ul << EVSYS_CHANNEL_PATH_Pos)
+#define EVSYS_CHANNEL_PATH(value) (EVSYS_CHANNEL_PATH_Msk & ((value) << EVSYS_CHANNEL_PATH_Pos))
+#define EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val 0x0ul /**< \brief (EVSYS_CHANNEL) Synchronous path */
+#define EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val 0x1ul /**< \brief (EVSYS_CHANNEL) Resynchronized path */
+#define EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val 0x2ul /**< \brief (EVSYS_CHANNEL) Asynchronous path */
+#define EVSYS_CHANNEL_PATH_SYNCHRONOUS (EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos)
+#define EVSYS_CHANNEL_PATH_RESYNCHRONIZED (EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val << EVSYS_CHANNEL_PATH_Pos)
+#define EVSYS_CHANNEL_PATH_ASYNCHRONOUS (EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos)
+#define EVSYS_CHANNEL_EDGSEL_Pos 26 /**< \brief (EVSYS_CHANNEL) Edge Detection Selection */
+#define EVSYS_CHANNEL_EDGSEL_Msk (0x3ul << EVSYS_CHANNEL_EDGSEL_Pos)
+#define EVSYS_CHANNEL_EDGSEL(value) (EVSYS_CHANNEL_EDGSEL_Msk & ((value) << EVSYS_CHANNEL_EDGSEL_Pos))
+#define EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val 0x0ul /**< \brief (EVSYS_CHANNEL) No event output when using the resynchronized or synchronous path */
+#define EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val 0x1ul /**< \brief (EVSYS_CHANNEL) Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path */
+#define EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val 0x2ul /**< \brief (EVSYS_CHANNEL) Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path */
+#define EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val 0x3ul /**< \brief (EVSYS_CHANNEL) Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path */
+#define EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT (EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val << EVSYS_CHANNEL_EDGSEL_Pos)
+#define EVSYS_CHANNEL_EDGSEL_RISING_EDGE (EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos)
+#define EVSYS_CHANNEL_EDGSEL_FALLING_EDGE (EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos)
+#define EVSYS_CHANNEL_EDGSEL_BOTH_EDGES (EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val << EVSYS_CHANNEL_EDGSEL_Pos)
+#define EVSYS_CHANNEL_MASK 0x0F7F010Ful /**< \brief (EVSYS_CHANNEL) MASK Register */
+
+/* -------- EVSYS_USER : (EVSYS Offset: 0x08) (R/W 16) User Multiplexer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t USER:5; /*!< bit: 0.. 4 User Multiplexer Selection */
+ uint16_t :3; /*!< bit: 5.. 7 Reserved */
+ uint16_t CHANNEL:5; /*!< bit: 8..12 Channel Event Selection */
+ uint16_t :3; /*!< bit: 13..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} EVSYS_USER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_USER_OFFSET 0x08 /**< \brief (EVSYS_USER offset) User Multiplexer */
+#define EVSYS_USER_RESETVALUE 0x0000ul /**< \brief (EVSYS_USER reset_value) User Multiplexer */
+
+#define EVSYS_USER_USER_Pos 0 /**< \brief (EVSYS_USER) User Multiplexer Selection */
+#define EVSYS_USER_USER_Msk (0x1Ful << EVSYS_USER_USER_Pos)
+#define EVSYS_USER_USER(value) (EVSYS_USER_USER_Msk & ((value) << EVSYS_USER_USER_Pos))
+#define EVSYS_USER_CHANNEL_Pos 8 /**< \brief (EVSYS_USER) Channel Event Selection */
+#define EVSYS_USER_CHANNEL_Msk (0x1Ful << EVSYS_USER_CHANNEL_Pos)
+#define EVSYS_USER_CHANNEL(value) (EVSYS_USER_CHANNEL_Msk & ((value) << EVSYS_USER_CHANNEL_Pos))
+#define EVSYS_USER_CHANNEL_0_Val 0x0ul /**< \brief (EVSYS_USER) No Channel Output Selected */
+#define EVSYS_USER_CHANNEL_0 (EVSYS_USER_CHANNEL_0_Val << EVSYS_USER_CHANNEL_Pos)
+#define EVSYS_USER_MASK 0x1F1Ful /**< \brief (EVSYS_USER) MASK Register */
+
+/* -------- EVSYS_CHSTATUS : (EVSYS Offset: 0x0C) (R/ 32) Channel Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t USRRDY0:1; /*!< bit: 0 Channel 0 User Ready */
+ uint32_t USRRDY1:1; /*!< bit: 1 Channel 1 User Ready */
+ uint32_t USRRDY2:1; /*!< bit: 2 Channel 2 User Ready */
+ uint32_t USRRDY3:1; /*!< bit: 3 Channel 3 User Ready */
+ uint32_t USRRDY4:1; /*!< bit: 4 Channel 4 User Ready */
+ uint32_t USRRDY5:1; /*!< bit: 5 Channel 5 User Ready */
+ uint32_t USRRDY6:1; /*!< bit: 6 Channel 6 User Ready */
+ uint32_t USRRDY7:1; /*!< bit: 7 Channel 7 User Ready */
+ uint32_t CHBUSY0:1; /*!< bit: 8 Channel 0 Busy */
+ uint32_t CHBUSY1:1; /*!< bit: 9 Channel 1 Busy */
+ uint32_t CHBUSY2:1; /*!< bit: 10 Channel 2 Busy */
+ uint32_t CHBUSY3:1; /*!< bit: 11 Channel 3 Busy */
+ uint32_t CHBUSY4:1; /*!< bit: 12 Channel 4 Busy */
+ uint32_t CHBUSY5:1; /*!< bit: 13 Channel 5 Busy */
+ uint32_t CHBUSY6:1; /*!< bit: 14 Channel 6 Busy */
+ uint32_t CHBUSY7:1; /*!< bit: 15 Channel 7 Busy */
+ uint32_t USRRDY8:1; /*!< bit: 16 Channel 8 User Ready */
+ uint32_t USRRDY9:1; /*!< bit: 17 Channel 9 User Ready */
+ uint32_t USRRDY10:1; /*!< bit: 18 Channel 10 User Ready */
+ uint32_t USRRDY11:1; /*!< bit: 19 Channel 11 User Ready */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t CHBUSY8:1; /*!< bit: 24 Channel 8 Busy */
+ uint32_t CHBUSY9:1; /*!< bit: 25 Channel 9 Busy */
+ uint32_t CHBUSY10:1; /*!< bit: 26 Channel 10 Busy */
+ uint32_t CHBUSY11:1; /*!< bit: 27 Channel 11 Busy */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t USRRDY:8; /*!< bit: 0.. 7 Channel x User Ready */
+ uint32_t CHBUSY:8; /*!< bit: 8..15 Channel x Busy */
+ uint32_t USRRDYp8:4; /*!< bit: 16..19 Channel x+8 User Ready */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t CHBUSYp8:4; /*!< bit: 24..27 Channel x+8 Busy */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} EVSYS_CHSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_CHSTATUS_OFFSET 0x0C /**< \brief (EVSYS_CHSTATUS offset) Channel Status */
+#define EVSYS_CHSTATUS_RESETVALUE 0x000F00FFul /**< \brief (EVSYS_CHSTATUS reset_value) Channel Status */
+
+#define EVSYS_CHSTATUS_USRRDY0_Pos 0 /**< \brief (EVSYS_CHSTATUS) Channel 0 User Ready */
+#define EVSYS_CHSTATUS_USRRDY0 (1 << EVSYS_CHSTATUS_USRRDY0_Pos)
+#define EVSYS_CHSTATUS_USRRDY1_Pos 1 /**< \brief (EVSYS_CHSTATUS) Channel 1 User Ready */
+#define EVSYS_CHSTATUS_USRRDY1 (1 << EVSYS_CHSTATUS_USRRDY1_Pos)
+#define EVSYS_CHSTATUS_USRRDY2_Pos 2 /**< \brief (EVSYS_CHSTATUS) Channel 2 User Ready */
+#define EVSYS_CHSTATUS_USRRDY2 (1 << EVSYS_CHSTATUS_USRRDY2_Pos)
+#define EVSYS_CHSTATUS_USRRDY3_Pos 3 /**< \brief (EVSYS_CHSTATUS) Channel 3 User Ready */
+#define EVSYS_CHSTATUS_USRRDY3 (1 << EVSYS_CHSTATUS_USRRDY3_Pos)
+#define EVSYS_CHSTATUS_USRRDY4_Pos 4 /**< \brief (EVSYS_CHSTATUS) Channel 4 User Ready */
+#define EVSYS_CHSTATUS_USRRDY4 (1 << EVSYS_CHSTATUS_USRRDY4_Pos)
+#define EVSYS_CHSTATUS_USRRDY5_Pos 5 /**< \brief (EVSYS_CHSTATUS) Channel 5 User Ready */
+#define EVSYS_CHSTATUS_USRRDY5 (1 << EVSYS_CHSTATUS_USRRDY5_Pos)
+#define EVSYS_CHSTATUS_USRRDY6_Pos 6 /**< \brief (EVSYS_CHSTATUS) Channel 6 User Ready */
+#define EVSYS_CHSTATUS_USRRDY6 (1 << EVSYS_CHSTATUS_USRRDY6_Pos)
+#define EVSYS_CHSTATUS_USRRDY7_Pos 7 /**< \brief (EVSYS_CHSTATUS) Channel 7 User Ready */
+#define EVSYS_CHSTATUS_USRRDY7 (1 << EVSYS_CHSTATUS_USRRDY7_Pos)
+#define EVSYS_CHSTATUS_USRRDY_Pos 0 /**< \brief (EVSYS_CHSTATUS) Channel x User Ready */
+#define EVSYS_CHSTATUS_USRRDY_Msk (0xFFul << EVSYS_CHSTATUS_USRRDY_Pos)
+#define EVSYS_CHSTATUS_USRRDY(value) (EVSYS_CHSTATUS_USRRDY_Msk & ((value) << EVSYS_CHSTATUS_USRRDY_Pos))
+#define EVSYS_CHSTATUS_CHBUSY0_Pos 8 /**< \brief (EVSYS_CHSTATUS) Channel 0 Busy */
+#define EVSYS_CHSTATUS_CHBUSY0 (1 << EVSYS_CHSTATUS_CHBUSY0_Pos)
+#define EVSYS_CHSTATUS_CHBUSY1_Pos 9 /**< \brief (EVSYS_CHSTATUS) Channel 1 Busy */
+#define EVSYS_CHSTATUS_CHBUSY1 (1 << EVSYS_CHSTATUS_CHBUSY1_Pos)
+#define EVSYS_CHSTATUS_CHBUSY2_Pos 10 /**< \brief (EVSYS_CHSTATUS) Channel 2 Busy */
+#define EVSYS_CHSTATUS_CHBUSY2 (1 << EVSYS_CHSTATUS_CHBUSY2_Pos)
+#define EVSYS_CHSTATUS_CHBUSY3_Pos 11 /**< \brief (EVSYS_CHSTATUS) Channel 3 Busy */
+#define EVSYS_CHSTATUS_CHBUSY3 (1 << EVSYS_CHSTATUS_CHBUSY3_Pos)
+#define EVSYS_CHSTATUS_CHBUSY4_Pos 12 /**< \brief (EVSYS_CHSTATUS) Channel 4 Busy */
+#define EVSYS_CHSTATUS_CHBUSY4 (1 << EVSYS_CHSTATUS_CHBUSY4_Pos)
+#define EVSYS_CHSTATUS_CHBUSY5_Pos 13 /**< \brief (EVSYS_CHSTATUS) Channel 5 Busy */
+#define EVSYS_CHSTATUS_CHBUSY5 (1 << EVSYS_CHSTATUS_CHBUSY5_Pos)
+#define EVSYS_CHSTATUS_CHBUSY6_Pos 14 /**< \brief (EVSYS_CHSTATUS) Channel 6 Busy */
+#define EVSYS_CHSTATUS_CHBUSY6 (1 << EVSYS_CHSTATUS_CHBUSY6_Pos)
+#define EVSYS_CHSTATUS_CHBUSY7_Pos 15 /**< \brief (EVSYS_CHSTATUS) Channel 7 Busy */
+#define EVSYS_CHSTATUS_CHBUSY7 (1 << EVSYS_CHSTATUS_CHBUSY7_Pos)
+#define EVSYS_CHSTATUS_CHBUSY_Pos 8 /**< \brief (EVSYS_CHSTATUS) Channel x Busy */
+#define EVSYS_CHSTATUS_CHBUSY_Msk (0xFFul << EVSYS_CHSTATUS_CHBUSY_Pos)
+#define EVSYS_CHSTATUS_CHBUSY(value) (EVSYS_CHSTATUS_CHBUSY_Msk & ((value) << EVSYS_CHSTATUS_CHBUSY_Pos))
+#define EVSYS_CHSTATUS_USRRDY8_Pos 16 /**< \brief (EVSYS_CHSTATUS) Channel 8 User Ready */
+#define EVSYS_CHSTATUS_USRRDY8 (1 << EVSYS_CHSTATUS_USRRDY8_Pos)
+#define EVSYS_CHSTATUS_USRRDY9_Pos 17 /**< \brief (EVSYS_CHSTATUS) Channel 9 User Ready */
+#define EVSYS_CHSTATUS_USRRDY9 (1 << EVSYS_CHSTATUS_USRRDY9_Pos)
+#define EVSYS_CHSTATUS_USRRDY10_Pos 18 /**< \brief (EVSYS_CHSTATUS) Channel 10 User Ready */
+#define EVSYS_CHSTATUS_USRRDY10 (1 << EVSYS_CHSTATUS_USRRDY10_Pos)
+#define EVSYS_CHSTATUS_USRRDY11_Pos 19 /**< \brief (EVSYS_CHSTATUS) Channel 11 User Ready */
+#define EVSYS_CHSTATUS_USRRDY11 (1 << EVSYS_CHSTATUS_USRRDY11_Pos)
+#define EVSYS_CHSTATUS_USRRDYp8_Pos 16 /**< \brief (EVSYS_CHSTATUS) Channel x+8 User Ready */
+#define EVSYS_CHSTATUS_USRRDYp8_Msk (0xFul << EVSYS_CHSTATUS_USRRDYp8_Pos)
+#define EVSYS_CHSTATUS_USRRDYp8(value) (EVSYS_CHSTATUS_USRRDYp8_Msk & ((value) << EVSYS_CHSTATUS_USRRDYp8_Pos))
+#define EVSYS_CHSTATUS_CHBUSY8_Pos 24 /**< \brief (EVSYS_CHSTATUS) Channel 8 Busy */
+#define EVSYS_CHSTATUS_CHBUSY8 (1 << EVSYS_CHSTATUS_CHBUSY8_Pos)
+#define EVSYS_CHSTATUS_CHBUSY9_Pos 25 /**< \brief (EVSYS_CHSTATUS) Channel 9 Busy */
+#define EVSYS_CHSTATUS_CHBUSY9 (1 << EVSYS_CHSTATUS_CHBUSY9_Pos)
+#define EVSYS_CHSTATUS_CHBUSY10_Pos 26 /**< \brief (EVSYS_CHSTATUS) Channel 10 Busy */
+#define EVSYS_CHSTATUS_CHBUSY10 (1 << EVSYS_CHSTATUS_CHBUSY10_Pos)
+#define EVSYS_CHSTATUS_CHBUSY11_Pos 27 /**< \brief (EVSYS_CHSTATUS) Channel 11 Busy */
+#define EVSYS_CHSTATUS_CHBUSY11 (1 << EVSYS_CHSTATUS_CHBUSY11_Pos)
+#define EVSYS_CHSTATUS_CHBUSYp8_Pos 24 /**< \brief (EVSYS_CHSTATUS) Channel x+8 Busy */
+#define EVSYS_CHSTATUS_CHBUSYp8_Msk (0xFul << EVSYS_CHSTATUS_CHBUSYp8_Pos)
+#define EVSYS_CHSTATUS_CHBUSYp8(value) (EVSYS_CHSTATUS_CHBUSYp8_Msk & ((value) << EVSYS_CHSTATUS_CHBUSYp8_Pos))
+#define EVSYS_CHSTATUS_MASK 0x0F0FFFFFul /**< \brief (EVSYS_CHSTATUS) MASK Register */
+
+/* -------- EVSYS_INTENCLR : (EVSYS Offset: 0x10) (R/W 32) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun Interrupt Enable */
+ uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun Interrupt Enable */
+ uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun Interrupt Enable */
+ uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun Interrupt Enable */
+ uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun Interrupt Enable */
+ uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun Interrupt Enable */
+ uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun Interrupt Enable */
+ uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun Interrupt Enable */
+ uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection Interrupt Enable */
+ uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection Interrupt Enable */
+ uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection Interrupt Enable */
+ uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection Interrupt Enable */
+ uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection Interrupt Enable */
+ uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection Interrupt Enable */
+ uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection Interrupt Enable */
+ uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection Interrupt Enable */
+ uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun Interrupt Enable */
+ uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun Interrupt Enable */
+ uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun Interrupt Enable */
+ uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun Interrupt Enable */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection Interrupt Enable */
+ uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection Interrupt Enable */
+ uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection Interrupt Enable */
+ uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection Interrupt Enable */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun Interrupt Enable */
+ uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection Interrupt Enable */
+ uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun Interrupt Enable */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection Interrupt Enable */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} EVSYS_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_INTENCLR_OFFSET 0x10 /**< \brief (EVSYS_INTENCLR offset) Interrupt Enable Clear */
+#define EVSYS_INTENCLR_RESETVALUE 0x00000000ul /**< \brief (EVSYS_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define EVSYS_INTENCLR_OVR0_Pos 0 /**< \brief (EVSYS_INTENCLR) Channel 0 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR0 (1 << EVSYS_INTENCLR_OVR0_Pos)
+#define EVSYS_INTENCLR_OVR1_Pos 1 /**< \brief (EVSYS_INTENCLR) Channel 1 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR1 (1 << EVSYS_INTENCLR_OVR1_Pos)
+#define EVSYS_INTENCLR_OVR2_Pos 2 /**< \brief (EVSYS_INTENCLR) Channel 2 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR2 (1 << EVSYS_INTENCLR_OVR2_Pos)
+#define EVSYS_INTENCLR_OVR3_Pos 3 /**< \brief (EVSYS_INTENCLR) Channel 3 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR3 (1 << EVSYS_INTENCLR_OVR3_Pos)
+#define EVSYS_INTENCLR_OVR4_Pos 4 /**< \brief (EVSYS_INTENCLR) Channel 4 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR4 (1 << EVSYS_INTENCLR_OVR4_Pos)
+#define EVSYS_INTENCLR_OVR5_Pos 5 /**< \brief (EVSYS_INTENCLR) Channel 5 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR5 (1 << EVSYS_INTENCLR_OVR5_Pos)
+#define EVSYS_INTENCLR_OVR6_Pos 6 /**< \brief (EVSYS_INTENCLR) Channel 6 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR6 (1 << EVSYS_INTENCLR_OVR6_Pos)
+#define EVSYS_INTENCLR_OVR7_Pos 7 /**< \brief (EVSYS_INTENCLR) Channel 7 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR7 (1 << EVSYS_INTENCLR_OVR7_Pos)
+#define EVSYS_INTENCLR_OVR_Pos 0 /**< \brief (EVSYS_INTENCLR) Channel x Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR_Msk (0xFFul << EVSYS_INTENCLR_OVR_Pos)
+#define EVSYS_INTENCLR_OVR(value) (EVSYS_INTENCLR_OVR_Msk & ((value) << EVSYS_INTENCLR_OVR_Pos))
+#define EVSYS_INTENCLR_EVD0_Pos 8 /**< \brief (EVSYS_INTENCLR) Channel 0 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD0 (1 << EVSYS_INTENCLR_EVD0_Pos)
+#define EVSYS_INTENCLR_EVD1_Pos 9 /**< \brief (EVSYS_INTENCLR) Channel 1 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD1 (1 << EVSYS_INTENCLR_EVD1_Pos)
+#define EVSYS_INTENCLR_EVD2_Pos 10 /**< \brief (EVSYS_INTENCLR) Channel 2 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD2 (1 << EVSYS_INTENCLR_EVD2_Pos)
+#define EVSYS_INTENCLR_EVD3_Pos 11 /**< \brief (EVSYS_INTENCLR) Channel 3 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD3 (1 << EVSYS_INTENCLR_EVD3_Pos)
+#define EVSYS_INTENCLR_EVD4_Pos 12 /**< \brief (EVSYS_INTENCLR) Channel 4 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD4 (1 << EVSYS_INTENCLR_EVD4_Pos)
+#define EVSYS_INTENCLR_EVD5_Pos 13 /**< \brief (EVSYS_INTENCLR) Channel 5 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD5 (1 << EVSYS_INTENCLR_EVD5_Pos)
+#define EVSYS_INTENCLR_EVD6_Pos 14 /**< \brief (EVSYS_INTENCLR) Channel 6 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD6 (1 << EVSYS_INTENCLR_EVD6_Pos)
+#define EVSYS_INTENCLR_EVD7_Pos 15 /**< \brief (EVSYS_INTENCLR) Channel 7 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD7 (1 << EVSYS_INTENCLR_EVD7_Pos)
+#define EVSYS_INTENCLR_EVD_Pos 8 /**< \brief (EVSYS_INTENCLR) Channel x Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD_Msk (0xFFul << EVSYS_INTENCLR_EVD_Pos)
+#define EVSYS_INTENCLR_EVD(value) (EVSYS_INTENCLR_EVD_Msk & ((value) << EVSYS_INTENCLR_EVD_Pos))
+#define EVSYS_INTENCLR_OVR8_Pos 16 /**< \brief (EVSYS_INTENCLR) Channel 8 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR8 (1 << EVSYS_INTENCLR_OVR8_Pos)
+#define EVSYS_INTENCLR_OVR9_Pos 17 /**< \brief (EVSYS_INTENCLR) Channel 9 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR9 (1 << EVSYS_INTENCLR_OVR9_Pos)
+#define EVSYS_INTENCLR_OVR10_Pos 18 /**< \brief (EVSYS_INTENCLR) Channel 10 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR10 (1 << EVSYS_INTENCLR_OVR10_Pos)
+#define EVSYS_INTENCLR_OVR11_Pos 19 /**< \brief (EVSYS_INTENCLR) Channel 11 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVR11 (1 << EVSYS_INTENCLR_OVR11_Pos)
+#define EVSYS_INTENCLR_OVRp8_Pos 16 /**< \brief (EVSYS_INTENCLR) Channel x+8 Overrun Interrupt Enable */
+#define EVSYS_INTENCLR_OVRp8_Msk (0xFul << EVSYS_INTENCLR_OVRp8_Pos)
+#define EVSYS_INTENCLR_OVRp8(value) (EVSYS_INTENCLR_OVRp8_Msk & ((value) << EVSYS_INTENCLR_OVRp8_Pos))
+#define EVSYS_INTENCLR_EVD8_Pos 24 /**< \brief (EVSYS_INTENCLR) Channel 8 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD8 (1 << EVSYS_INTENCLR_EVD8_Pos)
+#define EVSYS_INTENCLR_EVD9_Pos 25 /**< \brief (EVSYS_INTENCLR) Channel 9 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD9 (1 << EVSYS_INTENCLR_EVD9_Pos)
+#define EVSYS_INTENCLR_EVD10_Pos 26 /**< \brief (EVSYS_INTENCLR) Channel 10 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD10 (1 << EVSYS_INTENCLR_EVD10_Pos)
+#define EVSYS_INTENCLR_EVD11_Pos 27 /**< \brief (EVSYS_INTENCLR) Channel 11 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVD11 (1 << EVSYS_INTENCLR_EVD11_Pos)
+#define EVSYS_INTENCLR_EVDp8_Pos 24 /**< \brief (EVSYS_INTENCLR) Channel x+8 Event Detection Interrupt Enable */
+#define EVSYS_INTENCLR_EVDp8_Msk (0xFul << EVSYS_INTENCLR_EVDp8_Pos)
+#define EVSYS_INTENCLR_EVDp8(value) (EVSYS_INTENCLR_EVDp8_Msk & ((value) << EVSYS_INTENCLR_EVDp8_Pos))
+#define EVSYS_INTENCLR_MASK 0x0F0FFFFFul /**< \brief (EVSYS_INTENCLR) MASK Register */
+
+/* -------- EVSYS_INTENSET : (EVSYS Offset: 0x14) (R/W 32) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun Interrupt Enable */
+ uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun Interrupt Enable */
+ uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun Interrupt Enable */
+ uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun Interrupt Enable */
+ uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun Interrupt Enable */
+ uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun Interrupt Enable */
+ uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun Interrupt Enable */
+ uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun Interrupt Enable */
+ uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection Interrupt Enable */
+ uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection Interrupt Enable */
+ uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection Interrupt Enable */
+ uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection Interrupt Enable */
+ uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection Interrupt Enable */
+ uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection Interrupt Enable */
+ uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection Interrupt Enable */
+ uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection Interrupt Enable */
+ uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun Interrupt Enable */
+ uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun Interrupt Enable */
+ uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun Interrupt Enable */
+ uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun Interrupt Enable */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection Interrupt Enable */
+ uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection Interrupt Enable */
+ uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection Interrupt Enable */
+ uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection Interrupt Enable */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun Interrupt Enable */
+ uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection Interrupt Enable */
+ uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun Interrupt Enable */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection Interrupt Enable */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} EVSYS_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_INTENSET_OFFSET 0x14 /**< \brief (EVSYS_INTENSET offset) Interrupt Enable Set */
+#define EVSYS_INTENSET_RESETVALUE 0x00000000ul /**< \brief (EVSYS_INTENSET reset_value) Interrupt Enable Set */
+
+#define EVSYS_INTENSET_OVR0_Pos 0 /**< \brief (EVSYS_INTENSET) Channel 0 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR0 (1 << EVSYS_INTENSET_OVR0_Pos)
+#define EVSYS_INTENSET_OVR1_Pos 1 /**< \brief (EVSYS_INTENSET) Channel 1 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR1 (1 << EVSYS_INTENSET_OVR1_Pos)
+#define EVSYS_INTENSET_OVR2_Pos 2 /**< \brief (EVSYS_INTENSET) Channel 2 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR2 (1 << EVSYS_INTENSET_OVR2_Pos)
+#define EVSYS_INTENSET_OVR3_Pos 3 /**< \brief (EVSYS_INTENSET) Channel 3 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR3 (1 << EVSYS_INTENSET_OVR3_Pos)
+#define EVSYS_INTENSET_OVR4_Pos 4 /**< \brief (EVSYS_INTENSET) Channel 4 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR4 (1 << EVSYS_INTENSET_OVR4_Pos)
+#define EVSYS_INTENSET_OVR5_Pos 5 /**< \brief (EVSYS_INTENSET) Channel 5 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR5 (1 << EVSYS_INTENSET_OVR5_Pos)
+#define EVSYS_INTENSET_OVR6_Pos 6 /**< \brief (EVSYS_INTENSET) Channel 6 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR6 (1 << EVSYS_INTENSET_OVR6_Pos)
+#define EVSYS_INTENSET_OVR7_Pos 7 /**< \brief (EVSYS_INTENSET) Channel 7 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR7 (1 << EVSYS_INTENSET_OVR7_Pos)
+#define EVSYS_INTENSET_OVR_Pos 0 /**< \brief (EVSYS_INTENSET) Channel x Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR_Msk (0xFFul << EVSYS_INTENSET_OVR_Pos)
+#define EVSYS_INTENSET_OVR(value) (EVSYS_INTENSET_OVR_Msk & ((value) << EVSYS_INTENSET_OVR_Pos))
+#define EVSYS_INTENSET_EVD0_Pos 8 /**< \brief (EVSYS_INTENSET) Channel 0 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD0 (1 << EVSYS_INTENSET_EVD0_Pos)
+#define EVSYS_INTENSET_EVD1_Pos 9 /**< \brief (EVSYS_INTENSET) Channel 1 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD1 (1 << EVSYS_INTENSET_EVD1_Pos)
+#define EVSYS_INTENSET_EVD2_Pos 10 /**< \brief (EVSYS_INTENSET) Channel 2 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD2 (1 << EVSYS_INTENSET_EVD2_Pos)
+#define EVSYS_INTENSET_EVD3_Pos 11 /**< \brief (EVSYS_INTENSET) Channel 3 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD3 (1 << EVSYS_INTENSET_EVD3_Pos)
+#define EVSYS_INTENSET_EVD4_Pos 12 /**< \brief (EVSYS_INTENSET) Channel 4 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD4 (1 << EVSYS_INTENSET_EVD4_Pos)
+#define EVSYS_INTENSET_EVD5_Pos 13 /**< \brief (EVSYS_INTENSET) Channel 5 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD5 (1 << EVSYS_INTENSET_EVD5_Pos)
+#define EVSYS_INTENSET_EVD6_Pos 14 /**< \brief (EVSYS_INTENSET) Channel 6 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD6 (1 << EVSYS_INTENSET_EVD6_Pos)
+#define EVSYS_INTENSET_EVD7_Pos 15 /**< \brief (EVSYS_INTENSET) Channel 7 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD7 (1 << EVSYS_INTENSET_EVD7_Pos)
+#define EVSYS_INTENSET_EVD_Pos 8 /**< \brief (EVSYS_INTENSET) Channel x Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD_Msk (0xFFul << EVSYS_INTENSET_EVD_Pos)
+#define EVSYS_INTENSET_EVD(value) (EVSYS_INTENSET_EVD_Msk & ((value) << EVSYS_INTENSET_EVD_Pos))
+#define EVSYS_INTENSET_OVR8_Pos 16 /**< \brief (EVSYS_INTENSET) Channel 8 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR8 (1 << EVSYS_INTENSET_OVR8_Pos)
+#define EVSYS_INTENSET_OVR9_Pos 17 /**< \brief (EVSYS_INTENSET) Channel 9 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR9 (1 << EVSYS_INTENSET_OVR9_Pos)
+#define EVSYS_INTENSET_OVR10_Pos 18 /**< \brief (EVSYS_INTENSET) Channel 10 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR10 (1 << EVSYS_INTENSET_OVR10_Pos)
+#define EVSYS_INTENSET_OVR11_Pos 19 /**< \brief (EVSYS_INTENSET) Channel 11 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVR11 (1 << EVSYS_INTENSET_OVR11_Pos)
+#define EVSYS_INTENSET_OVRp8_Pos 16 /**< \brief (EVSYS_INTENSET) Channel x+8 Overrun Interrupt Enable */
+#define EVSYS_INTENSET_OVRp8_Msk (0xFul << EVSYS_INTENSET_OVRp8_Pos)
+#define EVSYS_INTENSET_OVRp8(value) (EVSYS_INTENSET_OVRp8_Msk & ((value) << EVSYS_INTENSET_OVRp8_Pos))
+#define EVSYS_INTENSET_EVD8_Pos 24 /**< \brief (EVSYS_INTENSET) Channel 8 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD8 (1 << EVSYS_INTENSET_EVD8_Pos)
+#define EVSYS_INTENSET_EVD9_Pos 25 /**< \brief (EVSYS_INTENSET) Channel 9 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD9 (1 << EVSYS_INTENSET_EVD9_Pos)
+#define EVSYS_INTENSET_EVD10_Pos 26 /**< \brief (EVSYS_INTENSET) Channel 10 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD10 (1 << EVSYS_INTENSET_EVD10_Pos)
+#define EVSYS_INTENSET_EVD11_Pos 27 /**< \brief (EVSYS_INTENSET) Channel 11 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVD11 (1 << EVSYS_INTENSET_EVD11_Pos)
+#define EVSYS_INTENSET_EVDp8_Pos 24 /**< \brief (EVSYS_INTENSET) Channel x+8 Event Detection Interrupt Enable */
+#define EVSYS_INTENSET_EVDp8_Msk (0xFul << EVSYS_INTENSET_EVDp8_Pos)
+#define EVSYS_INTENSET_EVDp8(value) (EVSYS_INTENSET_EVDp8_Msk & ((value) << EVSYS_INTENSET_EVDp8_Pos))
+#define EVSYS_INTENSET_MASK 0x0F0FFFFFul /**< \brief (EVSYS_INTENSET) MASK Register */
+
+/* -------- EVSYS_INTFLAG : (EVSYS Offset: 0x18) (R/W 32) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun */
+ __I uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun */
+ __I uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun */
+ __I uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun */
+ __I uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun */
+ __I uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun */
+ __I uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun */
+ __I uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun */
+ __I uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection */
+ __I uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection */
+ __I uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection */
+ __I uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection */
+ __I uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection */
+ __I uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection */
+ __I uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection */
+ __I uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection */
+ __I uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun */
+ __I uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun */
+ __I uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun */
+ __I uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun */
+ __I uint32_t :4; /*!< bit: 20..23 Reserved */
+ __I uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection */
+ __I uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection */
+ __I uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection */
+ __I uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection */
+ __I uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ __I uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun */
+ __I uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection */
+ __I uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun */
+ __I uint32_t :4; /*!< bit: 20..23 Reserved */
+ __I uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection */
+ __I uint32_t :4; /*!< bit: 28..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} EVSYS_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define EVSYS_INTFLAG_OFFSET 0x18 /**< \brief (EVSYS_INTFLAG offset) Interrupt Flag Status and Clear */
+#define EVSYS_INTFLAG_RESETVALUE 0x00000000ul /**< \brief (EVSYS_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define EVSYS_INTFLAG_OVR0_Pos 0 /**< \brief (EVSYS_INTFLAG) Channel 0 Overrun */
+#define EVSYS_INTFLAG_OVR0 (1 << EVSYS_INTFLAG_OVR0_Pos)
+#define EVSYS_INTFLAG_OVR1_Pos 1 /**< \brief (EVSYS_INTFLAG) Channel 1 Overrun */
+#define EVSYS_INTFLAG_OVR1 (1 << EVSYS_INTFLAG_OVR1_Pos)
+#define EVSYS_INTFLAG_OVR2_Pos 2 /**< \brief (EVSYS_INTFLAG) Channel 2 Overrun */
+#define EVSYS_INTFLAG_OVR2 (1 << EVSYS_INTFLAG_OVR2_Pos)
+#define EVSYS_INTFLAG_OVR3_Pos 3 /**< \brief (EVSYS_INTFLAG) Channel 3 Overrun */
+#define EVSYS_INTFLAG_OVR3 (1 << EVSYS_INTFLAG_OVR3_Pos)
+#define EVSYS_INTFLAG_OVR4_Pos 4 /**< \brief (EVSYS_INTFLAG) Channel 4 Overrun */
+#define EVSYS_INTFLAG_OVR4 (1 << EVSYS_INTFLAG_OVR4_Pos)
+#define EVSYS_INTFLAG_OVR5_Pos 5 /**< \brief (EVSYS_INTFLAG) Channel 5 Overrun */
+#define EVSYS_INTFLAG_OVR5 (1 << EVSYS_INTFLAG_OVR5_Pos)
+#define EVSYS_INTFLAG_OVR6_Pos 6 /**< \brief (EVSYS_INTFLAG) Channel 6 Overrun */
+#define EVSYS_INTFLAG_OVR6 (1 << EVSYS_INTFLAG_OVR6_Pos)
+#define EVSYS_INTFLAG_OVR7_Pos 7 /**< \brief (EVSYS_INTFLAG) Channel 7 Overrun */
+#define EVSYS_INTFLAG_OVR7 (1 << EVSYS_INTFLAG_OVR7_Pos)
+#define EVSYS_INTFLAG_OVR_Pos 0 /**< \brief (EVSYS_INTFLAG) Channel x Overrun */
+#define EVSYS_INTFLAG_OVR_Msk (0xFFul << EVSYS_INTFLAG_OVR_Pos)
+#define EVSYS_INTFLAG_OVR(value) (EVSYS_INTFLAG_OVR_Msk & ((value) << EVSYS_INTFLAG_OVR_Pos))
+#define EVSYS_INTFLAG_EVD0_Pos 8 /**< \brief (EVSYS_INTFLAG) Channel 0 Event Detection */
+#define EVSYS_INTFLAG_EVD0 (1 << EVSYS_INTFLAG_EVD0_Pos)
+#define EVSYS_INTFLAG_EVD1_Pos 9 /**< \brief (EVSYS_INTFLAG) Channel 1 Event Detection */
+#define EVSYS_INTFLAG_EVD1 (1 << EVSYS_INTFLAG_EVD1_Pos)
+#define EVSYS_INTFLAG_EVD2_Pos 10 /**< \brief (EVSYS_INTFLAG) Channel 2 Event Detection */
+#define EVSYS_INTFLAG_EVD2 (1 << EVSYS_INTFLAG_EVD2_Pos)
+#define EVSYS_INTFLAG_EVD3_Pos 11 /**< \brief (EVSYS_INTFLAG) Channel 3 Event Detection */
+#define EVSYS_INTFLAG_EVD3 (1 << EVSYS_INTFLAG_EVD3_Pos)
+#define EVSYS_INTFLAG_EVD4_Pos 12 /**< \brief (EVSYS_INTFLAG) Channel 4 Event Detection */
+#define EVSYS_INTFLAG_EVD4 (1 << EVSYS_INTFLAG_EVD4_Pos)
+#define EVSYS_INTFLAG_EVD5_Pos 13 /**< \brief (EVSYS_INTFLAG) Channel 5 Event Detection */
+#define EVSYS_INTFLAG_EVD5 (1 << EVSYS_INTFLAG_EVD5_Pos)
+#define EVSYS_INTFLAG_EVD6_Pos 14 /**< \brief (EVSYS_INTFLAG) Channel 6 Event Detection */
+#define EVSYS_INTFLAG_EVD6 (1 << EVSYS_INTFLAG_EVD6_Pos)
+#define EVSYS_INTFLAG_EVD7_Pos 15 /**< \brief (EVSYS_INTFLAG) Channel 7 Event Detection */
+#define EVSYS_INTFLAG_EVD7 (1 << EVSYS_INTFLAG_EVD7_Pos)
+#define EVSYS_INTFLAG_EVD_Pos 8 /**< \brief (EVSYS_INTFLAG) Channel x Event Detection */
+#define EVSYS_INTFLAG_EVD_Msk (0xFFul << EVSYS_INTFLAG_EVD_Pos)
+#define EVSYS_INTFLAG_EVD(value) (EVSYS_INTFLAG_EVD_Msk & ((value) << EVSYS_INTFLAG_EVD_Pos))
+#define EVSYS_INTFLAG_OVR8_Pos 16 /**< \brief (EVSYS_INTFLAG) Channel 8 Overrun */
+#define EVSYS_INTFLAG_OVR8 (1 << EVSYS_INTFLAG_OVR8_Pos)
+#define EVSYS_INTFLAG_OVR9_Pos 17 /**< \brief (EVSYS_INTFLAG) Channel 9 Overrun */
+#define EVSYS_INTFLAG_OVR9 (1 << EVSYS_INTFLAG_OVR9_Pos)
+#define EVSYS_INTFLAG_OVR10_Pos 18 /**< \brief (EVSYS_INTFLAG) Channel 10 Overrun */
+#define EVSYS_INTFLAG_OVR10 (1 << EVSYS_INTFLAG_OVR10_Pos)
+#define EVSYS_INTFLAG_OVR11_Pos 19 /**< \brief (EVSYS_INTFLAG) Channel 11 Overrun */
+#define EVSYS_INTFLAG_OVR11 (1 << EVSYS_INTFLAG_OVR11_Pos)
+#define EVSYS_INTFLAG_OVRp8_Pos 16 /**< \brief (EVSYS_INTFLAG) Channel x+8 Overrun */
+#define EVSYS_INTFLAG_OVRp8_Msk (0xFul << EVSYS_INTFLAG_OVRp8_Pos)
+#define EVSYS_INTFLAG_OVRp8(value) (EVSYS_INTFLAG_OVRp8_Msk & ((value) << EVSYS_INTFLAG_OVRp8_Pos))
+#define EVSYS_INTFLAG_EVD8_Pos 24 /**< \brief (EVSYS_INTFLAG) Channel 8 Event Detection */
+#define EVSYS_INTFLAG_EVD8 (1 << EVSYS_INTFLAG_EVD8_Pos)
+#define EVSYS_INTFLAG_EVD9_Pos 25 /**< \brief (EVSYS_INTFLAG) Channel 9 Event Detection */
+#define EVSYS_INTFLAG_EVD9 (1 << EVSYS_INTFLAG_EVD9_Pos)
+#define EVSYS_INTFLAG_EVD10_Pos 26 /**< \brief (EVSYS_INTFLAG) Channel 10 Event Detection */
+#define EVSYS_INTFLAG_EVD10 (1 << EVSYS_INTFLAG_EVD10_Pos)
+#define EVSYS_INTFLAG_EVD11_Pos 27 /**< \brief (EVSYS_INTFLAG) Channel 11 Event Detection */
+#define EVSYS_INTFLAG_EVD11 (1 << EVSYS_INTFLAG_EVD11_Pos)
+#define EVSYS_INTFLAG_EVDp8_Pos 24 /**< \brief (EVSYS_INTFLAG) Channel x+8 Event Detection */
+#define EVSYS_INTFLAG_EVDp8_Msk (0xFul << EVSYS_INTFLAG_EVDp8_Pos)
+#define EVSYS_INTFLAG_EVDp8(value) (EVSYS_INTFLAG_EVDp8_Msk & ((value) << EVSYS_INTFLAG_EVDp8_Pos))
+#define EVSYS_INTFLAG_MASK 0x0F0FFFFFul /**< \brief (EVSYS_INTFLAG) MASK Register */
+
+/** \brief EVSYS hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __O EVSYS_CTRL_Type CTRL; /**< \brief Offset: 0x00 ( /W 8) Control */
+ RoReg8 Reserved1[0x3];
+ __IO EVSYS_CHANNEL_Type CHANNEL; /**< \brief Offset: 0x04 (R/W 32) Channel */
+ __IO EVSYS_USER_Type USER; /**< \brief Offset: 0x08 (R/W 16) User Multiplexer */
+ RoReg8 Reserved2[0x2];
+ __I EVSYS_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x0C (R/ 32) Channel Status */
+ __IO EVSYS_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x10 (R/W 32) Interrupt Enable Clear */
+ __IO EVSYS_INTENSET_Type INTENSET; /**< \brief Offset: 0x14 (R/W 32) Interrupt Enable Set */
+ __IO EVSYS_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 32) Interrupt Flag Status and Clear */
+} Evsys;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_EVSYS_COMPONENT_ */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/component/gclk.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/component/gclk.h
new file mode 100644
index 0000000000000000000000000000000000000000..e103f04411ab93edb630a2f8c74f6067e3eb0f30
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/component/gclk.h
@@ -0,0 +1,310 @@
+/**
+ * \file
+ *
+ * \brief Component description for GCLK
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_GCLK_COMPONENT_
+#define _SAMD21_GCLK_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR GCLK */
+/* ========================================================================== */
+/** \addtogroup SAMD21_GCLK Generic Clock Generator */
+/*@{*/
+
+#define GCLK_U2102
+#define REV_GCLK 0x210
+
+/* -------- GCLK_CTRL : (GCLK Offset: 0x0) (R/W 8) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} GCLK_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GCLK_CTRL_OFFSET 0x0 /**< \brief (GCLK_CTRL offset) Control */
+#define GCLK_CTRL_RESETVALUE 0x00ul /**< \brief (GCLK_CTRL reset_value) Control */
+
+#define GCLK_CTRL_SWRST_Pos 0 /**< \brief (GCLK_CTRL) Software Reset */
+#define GCLK_CTRL_SWRST (0x1ul << GCLK_CTRL_SWRST_Pos)
+#define GCLK_CTRL_MASK 0x01ul /**< \brief (GCLK_CTRL) MASK Register */
+
+/* -------- GCLK_STATUS : (GCLK Offset: 0x1) (R/ 8) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t :7; /*!< bit: 0.. 6 Reserved */
+ uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy Status */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} GCLK_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GCLK_STATUS_OFFSET 0x1 /**< \brief (GCLK_STATUS offset) Status */
+#define GCLK_STATUS_RESETVALUE 0x00ul /**< \brief (GCLK_STATUS reset_value) Status */
+
+#define GCLK_STATUS_SYNCBUSY_Pos 7 /**< \brief (GCLK_STATUS) Synchronization Busy Status */
+#define GCLK_STATUS_SYNCBUSY (0x1ul << GCLK_STATUS_SYNCBUSY_Pos)
+#define GCLK_STATUS_MASK 0x80ul /**< \brief (GCLK_STATUS) MASK Register */
+
+/* -------- GCLK_CLKCTRL : (GCLK Offset: 0x2) (R/W 16) Generic Clock Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t ID:6; /*!< bit: 0.. 5 Generic Clock Selection ID */
+ uint16_t :2; /*!< bit: 6.. 7 Reserved */
+ uint16_t GEN:4; /*!< bit: 8..11 Generic Clock Generator */
+ uint16_t :2; /*!< bit: 12..13 Reserved */
+ uint16_t CLKEN:1; /*!< bit: 14 Clock Enable */
+ uint16_t WRTLOCK:1; /*!< bit: 15 Write Lock */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} GCLK_CLKCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GCLK_CLKCTRL_OFFSET 0x2 /**< \brief (GCLK_CLKCTRL offset) Generic Clock Control */
+#define GCLK_CLKCTRL_RESETVALUE 0x0000ul /**< \brief (GCLK_CLKCTRL reset_value) Generic Clock Control */
+
+#define GCLK_CLKCTRL_ID_Pos 0 /**< \brief (GCLK_CLKCTRL) Generic Clock Selection ID */
+#define GCLK_CLKCTRL_ID_Msk (0x3Ful << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID(value) (GCLK_CLKCTRL_ID_Msk & ((value) << GCLK_CLKCTRL_ID_Pos))
+#define GCLK_CLKCTRL_ID_DFLL48_Val 0x0ul /**< \brief (GCLK_CLKCTRL) DFLL48 */
+#define GCLK_CLKCTRL_ID_FDPLL_Val 0x1ul /**< \brief (GCLK_CLKCTRL) FDPLL */
+#define GCLK_CLKCTRL_ID_FDPLL32K_Val 0x2ul /**< \brief (GCLK_CLKCTRL) FDPLL32K */
+#define GCLK_CLKCTRL_ID_WDT_Val 0x3ul /**< \brief (GCLK_CLKCTRL) WDT */
+#define GCLK_CLKCTRL_ID_RTC_Val 0x4ul /**< \brief (GCLK_CLKCTRL) RTC */
+#define GCLK_CLKCTRL_ID_EIC_Val 0x5ul /**< \brief (GCLK_CLKCTRL) EIC */
+#define GCLK_CLKCTRL_ID_USB_Val 0x6ul /**< \brief (GCLK_CLKCTRL) USB */
+#define GCLK_CLKCTRL_ID_EVSYS_0_Val 0x7ul /**< \brief (GCLK_CLKCTRL) EVSYS_0 */
+#define GCLK_CLKCTRL_ID_EVSYS_1_Val 0x8ul /**< \brief (GCLK_CLKCTRL) EVSYS_1 */
+#define GCLK_CLKCTRL_ID_EVSYS_2_Val 0x9ul /**< \brief (GCLK_CLKCTRL) EVSYS_2 */
+#define GCLK_CLKCTRL_ID_EVSYS_3_Val 0xAul /**< \brief (GCLK_CLKCTRL) EVSYS_3 */
+#define GCLK_CLKCTRL_ID_EVSYS_4_Val 0xBul /**< \brief (GCLK_CLKCTRL) EVSYS_4 */
+#define GCLK_CLKCTRL_ID_EVSYS_5_Val 0xCul /**< \brief (GCLK_CLKCTRL) EVSYS_5 */
+#define GCLK_CLKCTRL_ID_EVSYS_6_Val 0xDul /**< \brief (GCLK_CLKCTRL) EVSYS_6 */
+#define GCLK_CLKCTRL_ID_EVSYS_7_Val 0xEul /**< \brief (GCLK_CLKCTRL) EVSYS_7 */
+#define GCLK_CLKCTRL_ID_EVSYS_8_Val 0xFul /**< \brief (GCLK_CLKCTRL) EVSYS_8 */
+#define GCLK_CLKCTRL_ID_EVSYS_9_Val 0x10ul /**< \brief (GCLK_CLKCTRL) EVSYS_9 */
+#define GCLK_CLKCTRL_ID_EVSYS_10_Val 0x11ul /**< \brief (GCLK_CLKCTRL) EVSYS_10 */
+#define GCLK_CLKCTRL_ID_EVSYS_11_Val 0x12ul /**< \brief (GCLK_CLKCTRL) EVSYS_11 */
+#define GCLK_CLKCTRL_ID_SERCOMX_SLOW_Val 0x13ul /**< \brief (GCLK_CLKCTRL) SERCOMX_SLOW */
+#define GCLK_CLKCTRL_ID_SERCOM0_CORE_Val 0x14ul /**< \brief (GCLK_CLKCTRL) SERCOM0_CORE */
+#define GCLK_CLKCTRL_ID_SERCOM1_CORE_Val 0x15ul /**< \brief (GCLK_CLKCTRL) SERCOM1_CORE */
+#define GCLK_CLKCTRL_ID_SERCOM2_CORE_Val 0x16ul /**< \brief (GCLK_CLKCTRL) SERCOM2_CORE */
+#define GCLK_CLKCTRL_ID_SERCOM3_CORE_Val 0x17ul /**< \brief (GCLK_CLKCTRL) SERCOM3_CORE */
+#define GCLK_CLKCTRL_ID_SERCOM4_CORE_Val 0x18ul /**< \brief (GCLK_CLKCTRL) SERCOM4_CORE */
+#define GCLK_CLKCTRL_ID_SERCOM5_CORE_Val 0x19ul /**< \brief (GCLK_CLKCTRL) SERCOM5_CORE */
+#define GCLK_CLKCTRL_ID_TCC0_TCC1_Val 0x1Aul /**< \brief (GCLK_CLKCTRL) TCC0_TCC1 */
+#define GCLK_CLKCTRL_ID_TCC2_TC3_Val 0x1Bul /**< \brief (GCLK_CLKCTRL) TCC2_TC3 */
+#define GCLK_CLKCTRL_ID_TC4_TC5_Val 0x1Cul /**< \brief (GCLK_CLKCTRL) TC4_TC5 */
+#define GCLK_CLKCTRL_ID_TC6_TC7_Val 0x1Dul /**< \brief (GCLK_CLKCTRL) TC6_TC7 */
+#define GCLK_CLKCTRL_ID_ADC_Val 0x1Eul /**< \brief (GCLK_CLKCTRL) ADC */
+#define GCLK_CLKCTRL_ID_AC_DIG_Val 0x1Ful /**< \brief (GCLK_CLKCTRL) AC_DIG */
+#define GCLK_CLKCTRL_ID_AC_ANA_Val 0x20ul /**< \brief (GCLK_CLKCTRL) AC_ANA */
+#define GCLK_CLKCTRL_ID_DAC_Val 0x21ul /**< \brief (GCLK_CLKCTRL) DAC */
+#define GCLK_CLKCTRL_ID_PTC_Val 0x22ul /**< \brief (GCLK_CLKCTRL) PTC */
+#define GCLK_CLKCTRL_ID_I2S_0_Val 0x23ul /**< \brief (GCLK_CLKCTRL) I2S_0 */
+#define GCLK_CLKCTRL_ID_I2S_1_Val 0x24ul /**< \brief (GCLK_CLKCTRL) I2S_1 */
+#define GCLK_CLKCTRL_ID_DFLL48 (GCLK_CLKCTRL_ID_DFLL48_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_FDPLL (GCLK_CLKCTRL_ID_FDPLL_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_FDPLL32K (GCLK_CLKCTRL_ID_FDPLL32K_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_WDT (GCLK_CLKCTRL_ID_WDT_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_RTC (GCLK_CLKCTRL_ID_RTC_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_EIC (GCLK_CLKCTRL_ID_EIC_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_USB (GCLK_CLKCTRL_ID_USB_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_EVSYS_0 (GCLK_CLKCTRL_ID_EVSYS_0_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_EVSYS_1 (GCLK_CLKCTRL_ID_EVSYS_1_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_EVSYS_2 (GCLK_CLKCTRL_ID_EVSYS_2_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_EVSYS_3 (GCLK_CLKCTRL_ID_EVSYS_3_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_EVSYS_4 (GCLK_CLKCTRL_ID_EVSYS_4_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_EVSYS_5 (GCLK_CLKCTRL_ID_EVSYS_5_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_EVSYS_6 (GCLK_CLKCTRL_ID_EVSYS_6_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_EVSYS_7 (GCLK_CLKCTRL_ID_EVSYS_7_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_EVSYS_8 (GCLK_CLKCTRL_ID_EVSYS_8_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_EVSYS_9 (GCLK_CLKCTRL_ID_EVSYS_9_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_EVSYS_10 (GCLK_CLKCTRL_ID_EVSYS_10_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_EVSYS_11 (GCLK_CLKCTRL_ID_EVSYS_11_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_SERCOMX_SLOW (GCLK_CLKCTRL_ID_SERCOMX_SLOW_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_SERCOM0_CORE (GCLK_CLKCTRL_ID_SERCOM0_CORE_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_SERCOM1_CORE (GCLK_CLKCTRL_ID_SERCOM1_CORE_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_SERCOM2_CORE (GCLK_CLKCTRL_ID_SERCOM2_CORE_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_SERCOM3_CORE (GCLK_CLKCTRL_ID_SERCOM3_CORE_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_SERCOM4_CORE (GCLK_CLKCTRL_ID_SERCOM4_CORE_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_SERCOM5_CORE (GCLK_CLKCTRL_ID_SERCOM5_CORE_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_TCC0_TCC1 (GCLK_CLKCTRL_ID_TCC0_TCC1_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_TCC2_TC3 (GCLK_CLKCTRL_ID_TCC2_TC3_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_TC4_TC5 (GCLK_CLKCTRL_ID_TC4_TC5_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_TC6_TC7 (GCLK_CLKCTRL_ID_TC6_TC7_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_ADC (GCLK_CLKCTRL_ID_ADC_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_AC_DIG (GCLK_CLKCTRL_ID_AC_DIG_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_AC_ANA (GCLK_CLKCTRL_ID_AC_ANA_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_DAC (GCLK_CLKCTRL_ID_DAC_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_PTC (GCLK_CLKCTRL_ID_PTC_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_I2S_0 (GCLK_CLKCTRL_ID_I2S_0_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_ID_I2S_1 (GCLK_CLKCTRL_ID_I2S_1_Val << GCLK_CLKCTRL_ID_Pos)
+#define GCLK_CLKCTRL_GEN_Pos 8 /**< \brief (GCLK_CLKCTRL) Generic Clock Generator */
+#define GCLK_CLKCTRL_GEN_Msk (0xFul << GCLK_CLKCTRL_GEN_Pos)
+#define GCLK_CLKCTRL_GEN(value) (GCLK_CLKCTRL_GEN_Msk & ((value) << GCLK_CLKCTRL_GEN_Pos))
+#define GCLK_CLKCTRL_GEN_GCLK0_Val 0x0ul /**< \brief (GCLK_CLKCTRL) Generic clock generator 0 */
+#define GCLK_CLKCTRL_GEN_GCLK1_Val 0x1ul /**< \brief (GCLK_CLKCTRL) Generic clock generator 1 */
+#define GCLK_CLKCTRL_GEN_GCLK2_Val 0x2ul /**< \brief (GCLK_CLKCTRL) Generic clock generator 2 */
+#define GCLK_CLKCTRL_GEN_GCLK3_Val 0x3ul /**< \brief (GCLK_CLKCTRL) Generic clock generator 3 */
+#define GCLK_CLKCTRL_GEN_GCLK4_Val 0x4ul /**< \brief (GCLK_CLKCTRL) Generic clock generator 4 */
+#define GCLK_CLKCTRL_GEN_GCLK5_Val 0x5ul /**< \brief (GCLK_CLKCTRL) Generic clock generator 5 */
+#define GCLK_CLKCTRL_GEN_GCLK6_Val 0x6ul /**< \brief (GCLK_CLKCTRL) Generic clock generator 6 */
+#define GCLK_CLKCTRL_GEN_GCLK7_Val 0x7ul /**< \brief (GCLK_CLKCTRL) Generic clock generator 7 */
+#define GCLK_CLKCTRL_GEN_GCLK0 (GCLK_CLKCTRL_GEN_GCLK0_Val << GCLK_CLKCTRL_GEN_Pos)
+#define GCLK_CLKCTRL_GEN_GCLK1 (GCLK_CLKCTRL_GEN_GCLK1_Val << GCLK_CLKCTRL_GEN_Pos)
+#define GCLK_CLKCTRL_GEN_GCLK2 (GCLK_CLKCTRL_GEN_GCLK2_Val << GCLK_CLKCTRL_GEN_Pos)
+#define GCLK_CLKCTRL_GEN_GCLK3 (GCLK_CLKCTRL_GEN_GCLK3_Val << GCLK_CLKCTRL_GEN_Pos)
+#define GCLK_CLKCTRL_GEN_GCLK4 (GCLK_CLKCTRL_GEN_GCLK4_Val << GCLK_CLKCTRL_GEN_Pos)
+#define GCLK_CLKCTRL_GEN_GCLK5 (GCLK_CLKCTRL_GEN_GCLK5_Val << GCLK_CLKCTRL_GEN_Pos)
+#define GCLK_CLKCTRL_GEN_GCLK6 (GCLK_CLKCTRL_GEN_GCLK6_Val << GCLK_CLKCTRL_GEN_Pos)
+#define GCLK_CLKCTRL_GEN_GCLK7 (GCLK_CLKCTRL_GEN_GCLK7_Val << GCLK_CLKCTRL_GEN_Pos)
+#define GCLK_CLKCTRL_CLKEN_Pos 14 /**< \brief (GCLK_CLKCTRL) Clock Enable */
+#define GCLK_CLKCTRL_CLKEN (0x1ul << GCLK_CLKCTRL_CLKEN_Pos)
+#define GCLK_CLKCTRL_WRTLOCK_Pos 15 /**< \brief (GCLK_CLKCTRL) Write Lock */
+#define GCLK_CLKCTRL_WRTLOCK (0x1ul << GCLK_CLKCTRL_WRTLOCK_Pos)
+#define GCLK_CLKCTRL_MASK 0xCF3Ful /**< \brief (GCLK_CLKCTRL) MASK Register */
+
+/* -------- GCLK_GENCTRL : (GCLK Offset: 0x4) (R/W 32) Generic Clock Generator Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ID:4; /*!< bit: 0.. 3 Generic Clock Generator Selection */
+ uint32_t :4; /*!< bit: 4.. 7 Reserved */
+ uint32_t SRC:5; /*!< bit: 8..12 Source Select */
+ uint32_t :3; /*!< bit: 13..15 Reserved */
+ uint32_t GENEN:1; /*!< bit: 16 Generic Clock Generator Enable */
+ uint32_t IDC:1; /*!< bit: 17 Improve Duty Cycle */
+ uint32_t OOV:1; /*!< bit: 18 Output Off Value */
+ uint32_t OE:1; /*!< bit: 19 Output Enable */
+ uint32_t DIVSEL:1; /*!< bit: 20 Divide Selection */
+ uint32_t RUNSTDBY:1; /*!< bit: 21 Run in Standby */
+ uint32_t :10; /*!< bit: 22..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GCLK_GENCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GCLK_GENCTRL_OFFSET 0x4 /**< \brief (GCLK_GENCTRL offset) Generic Clock Generator Control */
+#define GCLK_GENCTRL_RESETVALUE 0x00000000ul /**< \brief (GCLK_GENCTRL reset_value) Generic Clock Generator Control */
+
+#define GCLK_GENCTRL_ID_Pos 0 /**< \brief (GCLK_GENCTRL) Generic Clock Generator Selection */
+#define GCLK_GENCTRL_ID_Msk (0xFul << GCLK_GENCTRL_ID_Pos)
+#define GCLK_GENCTRL_ID(value) (GCLK_GENCTRL_ID_Msk & ((value) << GCLK_GENCTRL_ID_Pos))
+#define GCLK_GENCTRL_SRC_Pos 8 /**< \brief (GCLK_GENCTRL) Source Select */
+#define GCLK_GENCTRL_SRC_Msk (0x1Ful << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC(value) (GCLK_GENCTRL_SRC_Msk & ((value) << GCLK_GENCTRL_SRC_Pos))
+#define GCLK_GENCTRL_SRC_XOSC_Val 0x0ul /**< \brief (GCLK_GENCTRL) XOSC oscillator output */
+#define GCLK_GENCTRL_SRC_GCLKIN_Val 0x1ul /**< \brief (GCLK_GENCTRL) Generator input pad */
+#define GCLK_GENCTRL_SRC_GCLKGEN1_Val 0x2ul /**< \brief (GCLK_GENCTRL) Generic clock generator 1 output */
+#define GCLK_GENCTRL_SRC_OSCULP32K_Val 0x3ul /**< \brief (GCLK_GENCTRL) OSCULP32K oscillator output */
+#define GCLK_GENCTRL_SRC_OSC32K_Val 0x4ul /**< \brief (GCLK_GENCTRL) OSC32K oscillator output */
+#define GCLK_GENCTRL_SRC_XOSC32K_Val 0x5ul /**< \brief (GCLK_GENCTRL) XOSC32K oscillator output */
+#define GCLK_GENCTRL_SRC_OSC8M_Val 0x6ul /**< \brief (GCLK_GENCTRL) OSC8M oscillator output */
+#define GCLK_GENCTRL_SRC_DFLL48M_Val 0x7ul /**< \brief (GCLK_GENCTRL) DFLL48M output */
+#define GCLK_GENCTRL_SRC_FDPLL_Val 0x8ul /**< \brief (GCLK_GENCTRL) FDPLL output */
+#define GCLK_GENCTRL_SRC_XOSC (GCLK_GENCTRL_SRC_XOSC_Val << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_GCLKIN (GCLK_GENCTRL_SRC_GCLKIN_Val << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_GCLKGEN1 (GCLK_GENCTRL_SRC_GCLKGEN1_Val << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_OSCULP32K (GCLK_GENCTRL_SRC_OSCULP32K_Val << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_OSC32K (GCLK_GENCTRL_SRC_OSC32K_Val << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_XOSC32K (GCLK_GENCTRL_SRC_XOSC32K_Val << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_OSC8M (GCLK_GENCTRL_SRC_OSC8M_Val << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_DFLL48M (GCLK_GENCTRL_SRC_DFLL48M_Val << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_SRC_FDPLL (GCLK_GENCTRL_SRC_FDPLL_Val << GCLK_GENCTRL_SRC_Pos)
+#define GCLK_GENCTRL_GENEN_Pos 16 /**< \brief (GCLK_GENCTRL) Generic Clock Generator Enable */
+#define GCLK_GENCTRL_GENEN (0x1ul << GCLK_GENCTRL_GENEN_Pos)
+#define GCLK_GENCTRL_IDC_Pos 17 /**< \brief (GCLK_GENCTRL) Improve Duty Cycle */
+#define GCLK_GENCTRL_IDC (0x1ul << GCLK_GENCTRL_IDC_Pos)
+#define GCLK_GENCTRL_OOV_Pos 18 /**< \brief (GCLK_GENCTRL) Output Off Value */
+#define GCLK_GENCTRL_OOV (0x1ul << GCLK_GENCTRL_OOV_Pos)
+#define GCLK_GENCTRL_OE_Pos 19 /**< \brief (GCLK_GENCTRL) Output Enable */
+#define GCLK_GENCTRL_OE (0x1ul << GCLK_GENCTRL_OE_Pos)
+#define GCLK_GENCTRL_DIVSEL_Pos 20 /**< \brief (GCLK_GENCTRL) Divide Selection */
+#define GCLK_GENCTRL_DIVSEL (0x1ul << GCLK_GENCTRL_DIVSEL_Pos)
+#define GCLK_GENCTRL_RUNSTDBY_Pos 21 /**< \brief (GCLK_GENCTRL) Run in Standby */
+#define GCLK_GENCTRL_RUNSTDBY (0x1ul << GCLK_GENCTRL_RUNSTDBY_Pos)
+#define GCLK_GENCTRL_MASK 0x003F1F0Ful /**< \brief (GCLK_GENCTRL) MASK Register */
+
+/* -------- GCLK_GENDIV : (GCLK Offset: 0x8) (R/W 32) Generic Clock Generator Division -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ID:4; /*!< bit: 0.. 3 Generic Clock Generator Selection */
+ uint32_t :4; /*!< bit: 4.. 7 Reserved */
+ uint32_t DIV:16; /*!< bit: 8..23 Division Factor */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} GCLK_GENDIV_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define GCLK_GENDIV_OFFSET 0x8 /**< \brief (GCLK_GENDIV offset) Generic Clock Generator Division */
+#define GCLK_GENDIV_RESETVALUE 0x00000000ul /**< \brief (GCLK_GENDIV reset_value) Generic Clock Generator Division */
+
+#define GCLK_GENDIV_ID_Pos 0 /**< \brief (GCLK_GENDIV) Generic Clock Generator Selection */
+#define GCLK_GENDIV_ID_Msk (0xFul << GCLK_GENDIV_ID_Pos)
+#define GCLK_GENDIV_ID(value) (GCLK_GENDIV_ID_Msk & ((value) << GCLK_GENDIV_ID_Pos))
+#define GCLK_GENDIV_DIV_Pos 8 /**< \brief (GCLK_GENDIV) Division Factor */
+#define GCLK_GENDIV_DIV_Msk (0xFFFFul << GCLK_GENDIV_DIV_Pos)
+#define GCLK_GENDIV_DIV(value) (GCLK_GENDIV_DIV_Msk & ((value) << GCLK_GENDIV_DIV_Pos))
+#define GCLK_GENDIV_MASK 0x00FFFF0Ful /**< \brief (GCLK_GENDIV) MASK Register */
+
+/** \brief GCLK hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO GCLK_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */
+ __I GCLK_STATUS_Type STATUS; /**< \brief Offset: 0x1 (R/ 8) Status */
+ __IO GCLK_CLKCTRL_Type CLKCTRL; /**< \brief Offset: 0x2 (R/W 16) Generic Clock Control */
+ __IO GCLK_GENCTRL_Type GENCTRL; /**< \brief Offset: 0x4 (R/W 32) Generic Clock Generator Control */
+ __IO GCLK_GENDIV_Type GENDIV; /**< \brief Offset: 0x8 (R/W 32) Generic Clock Generator Division */
+} Gclk;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_GCLK_COMPONENT_ */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/component/hmatrixb.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/component/hmatrixb.h
new file mode 100644
index 0000000000000000000000000000000000000000..934c508ada60fc4d0ae1daa5ad65391d500efc26
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/component/hmatrixb.h
@@ -0,0 +1,118 @@
+/**
+ * \file
+ *
+ * \brief Component description for HMATRIXB
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_HMATRIXB_COMPONENT_
+#define _SAMD21_HMATRIXB_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR HMATRIXB */
+/* ========================================================================== */
+/** \addtogroup SAMD21_HMATRIXB HSB Matrix */
+/*@{*/
+
+#define HMATRIXB_I7638
+#define REV_HMATRIXB 0x212
+
+/* -------- HMATRIXB_PRAS : (HMATRIXB Offset: 0x080) (R/W 32) PRS Priority A for Slave -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} HMATRIXB_PRAS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define HMATRIXB_PRAS_OFFSET 0x080 /**< \brief (HMATRIXB_PRAS offset) Priority A for Slave */
+#define HMATRIXB_PRAS_RESETVALUE 0x00000000ul /**< \brief (HMATRIXB_PRAS reset_value) Priority A for Slave */
+
+#define HMATRIXB_PRAS_MASK 0x00000000ul /**< \brief (HMATRIXB_PRAS) MASK Register */
+
+/* -------- HMATRIXB_PRBS : (HMATRIXB Offset: 0x084) (R/W 32) PRS Priority B for Slave -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} HMATRIXB_PRBS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define HMATRIXB_PRBS_OFFSET 0x084 /**< \brief (HMATRIXB_PRBS offset) Priority B for Slave */
+#define HMATRIXB_PRBS_RESETVALUE 0x00000000ul /**< \brief (HMATRIXB_PRBS reset_value) Priority B for Slave */
+
+#define HMATRIXB_PRBS_MASK 0x00000000ul /**< \brief (HMATRIXB_PRBS) MASK Register */
+
+/* -------- HMATRIXB_SFR : (HMATRIXB Offset: 0x110) (R/W 32) Special Function -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SFR:32; /*!< bit: 0..31 Special Function Register */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} HMATRIXB_SFR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define HMATRIXB_SFR_OFFSET 0x110 /**< \brief (HMATRIXB_SFR offset) Special Function */
+#define HMATRIXB_SFR_RESETVALUE 0x00000000ul /**< \brief (HMATRIXB_SFR reset_value) Special Function */
+
+#define HMATRIXB_SFR_SFR_Pos 0 /**< \brief (HMATRIXB_SFR) Special Function Register */
+#define HMATRIXB_SFR_SFR_Msk (0xFFFFFFFFul << HMATRIXB_SFR_SFR_Pos)
+#define HMATRIXB_SFR_SFR(value) (HMATRIXB_SFR_SFR_Msk & ((value) << HMATRIXB_SFR_SFR_Pos))
+#define HMATRIXB_SFR_MASK 0xFFFFFFFFul /**< \brief (HMATRIXB_SFR) MASK Register */
+
+/** \brief HmatrixbPrs hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO HMATRIXB_PRAS_Type PRAS; /**< \brief Offset: 0x000 (R/W 32) Priority A for Slave */
+ __IO HMATRIXB_PRBS_Type PRBS; /**< \brief Offset: 0x004 (R/W 32) Priority B for Slave */
+} HmatrixbPrs;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief HMATRIXB hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ RoReg8 Reserved1[0x80];
+ HmatrixbPrs Prs[16]; /**< \brief Offset: 0x080 HmatrixbPrs groups */
+ RoReg8 Reserved2[0x10];
+ __IO HMATRIXB_SFR_Type SFR[16]; /**< \brief Offset: 0x110 (R/W 32) Special Function */
+} Hmatrixb;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_HMATRIXB_COMPONENT_ */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/component/i2s.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/component/i2s.h
new file mode 100644
index 0000000000000000000000000000000000000000..e6d75656836c8858c184b9a69b8ee72df8fa208a
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/component/i2s.h
@@ -0,0 +1,639 @@
+/**
+ * \file
+ *
+ * \brief Component description for I2S
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_I2S_COMPONENT_
+#define _SAMD21_I2S_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR I2S */
+/* ========================================================================== */
+/** \addtogroup SAMD21_I2S Inter-IC Sound Interface */
+/*@{*/
+
+#define I2S_U2224
+#define REV_I2S 0x102
+
+/* -------- I2S_CTRLA : (I2S Offset: 0x00) (R/W 8) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t ENABLE:1; /*!< bit: 1 Enable */
+ uint8_t CKEN0:1; /*!< bit: 2 Clock Unit 0 Enable */
+ uint8_t CKEN1:1; /*!< bit: 3 Clock Unit 1 Enable */
+ uint8_t SEREN0:1; /*!< bit: 4 Serializer 0 Enable */
+ uint8_t SEREN1:1; /*!< bit: 5 Serializer 1 Enable */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t :2; /*!< bit: 0.. 1 Reserved */
+ uint8_t CKEN:2; /*!< bit: 2.. 3 Clock Unit x Enable */
+ uint8_t SEREN:2; /*!< bit: 4.. 5 Serializer x Enable */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} I2S_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define I2S_CTRLA_OFFSET 0x00 /**< \brief (I2S_CTRLA offset) Control A */
+#define I2S_CTRLA_RESETVALUE 0x00ul /**< \brief (I2S_CTRLA reset_value) Control A */
+
+#define I2S_CTRLA_SWRST_Pos 0 /**< \brief (I2S_CTRLA) Software Reset */
+#define I2S_CTRLA_SWRST (0x1ul << I2S_CTRLA_SWRST_Pos)
+#define I2S_CTRLA_ENABLE_Pos 1 /**< \brief (I2S_CTRLA) Enable */
+#define I2S_CTRLA_ENABLE (0x1ul << I2S_CTRLA_ENABLE_Pos)
+#define I2S_CTRLA_CKEN0_Pos 2 /**< \brief (I2S_CTRLA) Clock Unit 0 Enable */
+#define I2S_CTRLA_CKEN0 (1 << I2S_CTRLA_CKEN0_Pos)
+#define I2S_CTRLA_CKEN1_Pos 3 /**< \brief (I2S_CTRLA) Clock Unit 1 Enable */
+#define I2S_CTRLA_CKEN1 (1 << I2S_CTRLA_CKEN1_Pos)
+#define I2S_CTRLA_CKEN_Pos 2 /**< \brief (I2S_CTRLA) Clock Unit x Enable */
+#define I2S_CTRLA_CKEN_Msk (0x3ul << I2S_CTRLA_CKEN_Pos)
+#define I2S_CTRLA_CKEN(value) (I2S_CTRLA_CKEN_Msk & ((value) << I2S_CTRLA_CKEN_Pos))
+#define I2S_CTRLA_SEREN0_Pos 4 /**< \brief (I2S_CTRLA) Serializer 0 Enable */
+#define I2S_CTRLA_SEREN0 (1 << I2S_CTRLA_SEREN0_Pos)
+#define I2S_CTRLA_SEREN1_Pos 5 /**< \brief (I2S_CTRLA) Serializer 1 Enable */
+#define I2S_CTRLA_SEREN1 (1 << I2S_CTRLA_SEREN1_Pos)
+#define I2S_CTRLA_SEREN_Pos 4 /**< \brief (I2S_CTRLA) Serializer x Enable */
+#define I2S_CTRLA_SEREN_Msk (0x3ul << I2S_CTRLA_SEREN_Pos)
+#define I2S_CTRLA_SEREN(value) (I2S_CTRLA_SEREN_Msk & ((value) << I2S_CTRLA_SEREN_Pos))
+#define I2S_CTRLA_MASK 0x3Ful /**< \brief (I2S_CTRLA) MASK Register */
+
+/* -------- I2S_CLKCTRL : (I2S Offset: 0x04) (R/W 32) Clock Unit n Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SLOTSIZE:2; /*!< bit: 0.. 1 Slot Size */
+ uint32_t NBSLOTS:3; /*!< bit: 2.. 4 Number of Slots in Frame */
+ uint32_t FSWIDTH:2; /*!< bit: 5.. 6 Frame Sync Width */
+ uint32_t BITDELAY:1; /*!< bit: 7 Data Delay from Frame Sync */
+ uint32_t FSSEL:1; /*!< bit: 8 Frame Sync Select */
+ uint32_t :2; /*!< bit: 9..10 Reserved */
+ uint32_t FSINV:1; /*!< bit: 11 Frame Sync Invert */
+ uint32_t SCKSEL:1; /*!< bit: 12 Serial Clock Select */
+ uint32_t :3; /*!< bit: 13..15 Reserved */
+ uint32_t MCKSEL:1; /*!< bit: 16 Master Clock Select */
+ uint32_t :1; /*!< bit: 17 Reserved */
+ uint32_t MCKEN:1; /*!< bit: 18 Master Clock Enable */
+ uint32_t MCKDIV:5; /*!< bit: 19..23 Master Clock Division Factor */
+ uint32_t MCKOUTDIV:5; /*!< bit: 24..28 Master Clock Output Division Factor */
+ uint32_t FSOUTINV:1; /*!< bit: 29 Frame Sync Output Invert */
+ uint32_t SCKOUTINV:1; /*!< bit: 30 Serial Clock Output Invert */
+ uint32_t MCKOUTINV:1; /*!< bit: 31 Master Clock Output Invert */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} I2S_CLKCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define I2S_CLKCTRL_OFFSET 0x04 /**< \brief (I2S_CLKCTRL offset) Clock Unit n Control */
+#define I2S_CLKCTRL_RESETVALUE 0x00000000ul /**< \brief (I2S_CLKCTRL reset_value) Clock Unit n Control */
+
+#define I2S_CLKCTRL_SLOTSIZE_Pos 0 /**< \brief (I2S_CLKCTRL) Slot Size */
+#define I2S_CLKCTRL_SLOTSIZE_Msk (0x3ul << I2S_CLKCTRL_SLOTSIZE_Pos)
+#define I2S_CLKCTRL_SLOTSIZE(value) (I2S_CLKCTRL_SLOTSIZE_Msk & ((value) << I2S_CLKCTRL_SLOTSIZE_Pos))
+#define I2S_CLKCTRL_SLOTSIZE_8_Val 0x0ul /**< \brief (I2S_CLKCTRL) 8-bit Slot for Clock Unit n */
+#define I2S_CLKCTRL_SLOTSIZE_16_Val 0x1ul /**< \brief (I2S_CLKCTRL) 16-bit Slot for Clock Unit n */
+#define I2S_CLKCTRL_SLOTSIZE_24_Val 0x2ul /**< \brief (I2S_CLKCTRL) 24-bit Slot for Clock Unit n */
+#define I2S_CLKCTRL_SLOTSIZE_32_Val 0x3ul /**< \brief (I2S_CLKCTRL) 32-bit Slot for Clock Unit n */
+#define I2S_CLKCTRL_SLOTSIZE_8 (I2S_CLKCTRL_SLOTSIZE_8_Val << I2S_CLKCTRL_SLOTSIZE_Pos)
+#define I2S_CLKCTRL_SLOTSIZE_16 (I2S_CLKCTRL_SLOTSIZE_16_Val << I2S_CLKCTRL_SLOTSIZE_Pos)
+#define I2S_CLKCTRL_SLOTSIZE_24 (I2S_CLKCTRL_SLOTSIZE_24_Val << I2S_CLKCTRL_SLOTSIZE_Pos)
+#define I2S_CLKCTRL_SLOTSIZE_32 (I2S_CLKCTRL_SLOTSIZE_32_Val << I2S_CLKCTRL_SLOTSIZE_Pos)
+#define I2S_CLKCTRL_NBSLOTS_Pos 2 /**< \brief (I2S_CLKCTRL) Number of Slots in Frame */
+#define I2S_CLKCTRL_NBSLOTS_Msk (0x7ul << I2S_CLKCTRL_NBSLOTS_Pos)
+#define I2S_CLKCTRL_NBSLOTS(value) (I2S_CLKCTRL_NBSLOTS_Msk & ((value) << I2S_CLKCTRL_NBSLOTS_Pos))
+#define I2S_CLKCTRL_FSWIDTH_Pos 5 /**< \brief (I2S_CLKCTRL) Frame Sync Width */
+#define I2S_CLKCTRL_FSWIDTH_Msk (0x3ul << I2S_CLKCTRL_FSWIDTH_Pos)
+#define I2S_CLKCTRL_FSWIDTH(value) (I2S_CLKCTRL_FSWIDTH_Msk & ((value) << I2S_CLKCTRL_FSWIDTH_Pos))
+#define I2S_CLKCTRL_FSWIDTH_SLOT_Val 0x0ul /**< \brief (I2S_CLKCTRL) Frame Sync Pulse is 1 Slot wide (default for I2S protocol) */
+#define I2S_CLKCTRL_FSWIDTH_HALF_Val 0x1ul /**< \brief (I2S_CLKCTRL) Frame Sync Pulse is half a Frame wide */
+#define I2S_CLKCTRL_FSWIDTH_BIT_Val 0x2ul /**< \brief (I2S_CLKCTRL) Frame Sync Pulse is 1 Bit wide */
+#define I2S_CLKCTRL_FSWIDTH_BURST_Val 0x3ul /**< \brief (I2S_CLKCTRL) Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested */
+#define I2S_CLKCTRL_FSWIDTH_SLOT (I2S_CLKCTRL_FSWIDTH_SLOT_Val << I2S_CLKCTRL_FSWIDTH_Pos)
+#define I2S_CLKCTRL_FSWIDTH_HALF (I2S_CLKCTRL_FSWIDTH_HALF_Val << I2S_CLKCTRL_FSWIDTH_Pos)
+#define I2S_CLKCTRL_FSWIDTH_BIT (I2S_CLKCTRL_FSWIDTH_BIT_Val << I2S_CLKCTRL_FSWIDTH_Pos)
+#define I2S_CLKCTRL_FSWIDTH_BURST (I2S_CLKCTRL_FSWIDTH_BURST_Val << I2S_CLKCTRL_FSWIDTH_Pos)
+#define I2S_CLKCTRL_BITDELAY_Pos 7 /**< \brief (I2S_CLKCTRL) Data Delay from Frame Sync */
+#define I2S_CLKCTRL_BITDELAY (0x1ul << I2S_CLKCTRL_BITDELAY_Pos)
+#define I2S_CLKCTRL_BITDELAY_LJ_Val 0x0ul /**< \brief (I2S_CLKCTRL) Left Justified (0 Bit Delay) */
+#define I2S_CLKCTRL_BITDELAY_I2S_Val 0x1ul /**< \brief (I2S_CLKCTRL) I2S (1 Bit Delay) */
+#define I2S_CLKCTRL_BITDELAY_LJ (I2S_CLKCTRL_BITDELAY_LJ_Val << I2S_CLKCTRL_BITDELAY_Pos)
+#define I2S_CLKCTRL_BITDELAY_I2S (I2S_CLKCTRL_BITDELAY_I2S_Val << I2S_CLKCTRL_BITDELAY_Pos)
+#define I2S_CLKCTRL_FSSEL_Pos 8 /**< \brief (I2S_CLKCTRL) Frame Sync Select */
+#define I2S_CLKCTRL_FSSEL (0x1ul << I2S_CLKCTRL_FSSEL_Pos)
+#define I2S_CLKCTRL_FSSEL_SCKDIV_Val 0x0ul /**< \brief (I2S_CLKCTRL) Divided Serial Clock n is used as Frame Sync n source */
+#define I2S_CLKCTRL_FSSEL_FSPIN_Val 0x1ul /**< \brief (I2S_CLKCTRL) FSn input pin is used as Frame Sync n source */
+#define I2S_CLKCTRL_FSSEL_SCKDIV (I2S_CLKCTRL_FSSEL_SCKDIV_Val << I2S_CLKCTRL_FSSEL_Pos)
+#define I2S_CLKCTRL_FSSEL_FSPIN (I2S_CLKCTRL_FSSEL_FSPIN_Val << I2S_CLKCTRL_FSSEL_Pos)
+#define I2S_CLKCTRL_FSINV_Pos 11 /**< \brief (I2S_CLKCTRL) Frame Sync Invert */
+#define I2S_CLKCTRL_FSINV (0x1ul << I2S_CLKCTRL_FSINV_Pos)
+#define I2S_CLKCTRL_SCKSEL_Pos 12 /**< \brief (I2S_CLKCTRL) Serial Clock Select */
+#define I2S_CLKCTRL_SCKSEL (0x1ul << I2S_CLKCTRL_SCKSEL_Pos)
+#define I2S_CLKCTRL_SCKSEL_MCKDIV_Val 0x0ul /**< \brief (I2S_CLKCTRL) Divided Master Clock n is used as Serial Clock n source */
+#define I2S_CLKCTRL_SCKSEL_SCKPIN_Val 0x1ul /**< \brief (I2S_CLKCTRL) SCKn input pin is used as Serial Clock n source */
+#define I2S_CLKCTRL_SCKSEL_MCKDIV (I2S_CLKCTRL_SCKSEL_MCKDIV_Val << I2S_CLKCTRL_SCKSEL_Pos)
+#define I2S_CLKCTRL_SCKSEL_SCKPIN (I2S_CLKCTRL_SCKSEL_SCKPIN_Val << I2S_CLKCTRL_SCKSEL_Pos)
+#define I2S_CLKCTRL_MCKSEL_Pos 16 /**< \brief (I2S_CLKCTRL) Master Clock Select */
+#define I2S_CLKCTRL_MCKSEL (0x1ul << I2S_CLKCTRL_MCKSEL_Pos)
+#define I2S_CLKCTRL_MCKSEL_GCLK_Val 0x0ul /**< \brief (I2S_CLKCTRL) GCLK_I2S_n is used as Master Clock n source */
+#define I2S_CLKCTRL_MCKSEL_MCKPIN_Val 0x1ul /**< \brief (I2S_CLKCTRL) MCKn input pin is used as Master Clock n source */
+#define I2S_CLKCTRL_MCKSEL_GCLK (I2S_CLKCTRL_MCKSEL_GCLK_Val << I2S_CLKCTRL_MCKSEL_Pos)
+#define I2S_CLKCTRL_MCKSEL_MCKPIN (I2S_CLKCTRL_MCKSEL_MCKPIN_Val << I2S_CLKCTRL_MCKSEL_Pos)
+#define I2S_CLKCTRL_MCKEN_Pos 18 /**< \brief (I2S_CLKCTRL) Master Clock Enable */
+#define I2S_CLKCTRL_MCKEN (0x1ul << I2S_CLKCTRL_MCKEN_Pos)
+#define I2S_CLKCTRL_MCKDIV_Pos 19 /**< \brief (I2S_CLKCTRL) Master Clock Division Factor */
+#define I2S_CLKCTRL_MCKDIV_Msk (0x1Ful << I2S_CLKCTRL_MCKDIV_Pos)
+#define I2S_CLKCTRL_MCKDIV(value) (I2S_CLKCTRL_MCKDIV_Msk & ((value) << I2S_CLKCTRL_MCKDIV_Pos))
+#define I2S_CLKCTRL_MCKOUTDIV_Pos 24 /**< \brief (I2S_CLKCTRL) Master Clock Output Division Factor */
+#define I2S_CLKCTRL_MCKOUTDIV_Msk (0x1Ful << I2S_CLKCTRL_MCKOUTDIV_Pos)
+#define I2S_CLKCTRL_MCKOUTDIV(value) (I2S_CLKCTRL_MCKOUTDIV_Msk & ((value) << I2S_CLKCTRL_MCKOUTDIV_Pos))
+#define I2S_CLKCTRL_FSOUTINV_Pos 29 /**< \brief (I2S_CLKCTRL) Frame Sync Output Invert */
+#define I2S_CLKCTRL_FSOUTINV (0x1ul << I2S_CLKCTRL_FSOUTINV_Pos)
+#define I2S_CLKCTRL_SCKOUTINV_Pos 30 /**< \brief (I2S_CLKCTRL) Serial Clock Output Invert */
+#define I2S_CLKCTRL_SCKOUTINV (0x1ul << I2S_CLKCTRL_SCKOUTINV_Pos)
+#define I2S_CLKCTRL_MCKOUTINV_Pos 31 /**< \brief (I2S_CLKCTRL) Master Clock Output Invert */
+#define I2S_CLKCTRL_MCKOUTINV (0x1ul << I2S_CLKCTRL_MCKOUTINV_Pos)
+#define I2S_CLKCTRL_MASK 0xFFFD19FFul /**< \brief (I2S_CLKCTRL) MASK Register */
+
+/* -------- I2S_INTENCLR : (I2S Offset: 0x0C) (R/W 16) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 Interrupt Enable */
+ uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 Interrupt Enable */
+ uint16_t :2; /*!< bit: 2.. 3 Reserved */
+ uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 Interrupt Enable */
+ uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 Interrupt Enable */
+ uint16_t :2; /*!< bit: 6.. 7 Reserved */
+ uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 Interrupt Enable */
+ uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 Interrupt Enable */
+ uint16_t :2; /*!< bit: 10..11 Reserved */
+ uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 Interrupt Enable */
+ uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 Interrupt Enable */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x Interrupt Enable */
+ uint16_t :2; /*!< bit: 2.. 3 Reserved */
+ uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x Interrupt Enable */
+ uint16_t :2; /*!< bit: 6.. 7 Reserved */
+ uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x Interrupt Enable */
+ uint16_t :2; /*!< bit: 10..11 Reserved */
+ uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x Interrupt Enable */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} I2S_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define I2S_INTENCLR_OFFSET 0x0C /**< \brief (I2S_INTENCLR offset) Interrupt Enable Clear */
+#define I2S_INTENCLR_RESETVALUE 0x0000ul /**< \brief (I2S_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define I2S_INTENCLR_RXRDY0_Pos 0 /**< \brief (I2S_INTENCLR) Receive Ready 0 Interrupt Enable */
+#define I2S_INTENCLR_RXRDY0 (1 << I2S_INTENCLR_RXRDY0_Pos)
+#define I2S_INTENCLR_RXRDY1_Pos 1 /**< \brief (I2S_INTENCLR) Receive Ready 1 Interrupt Enable */
+#define I2S_INTENCLR_RXRDY1 (1 << I2S_INTENCLR_RXRDY1_Pos)
+#define I2S_INTENCLR_RXRDY_Pos 0 /**< \brief (I2S_INTENCLR) Receive Ready x Interrupt Enable */
+#define I2S_INTENCLR_RXRDY_Msk (0x3ul << I2S_INTENCLR_RXRDY_Pos)
+#define I2S_INTENCLR_RXRDY(value) (I2S_INTENCLR_RXRDY_Msk & ((value) << I2S_INTENCLR_RXRDY_Pos))
+#define I2S_INTENCLR_RXOR0_Pos 4 /**< \brief (I2S_INTENCLR) Receive Overrun 0 Interrupt Enable */
+#define I2S_INTENCLR_RXOR0 (1 << I2S_INTENCLR_RXOR0_Pos)
+#define I2S_INTENCLR_RXOR1_Pos 5 /**< \brief (I2S_INTENCLR) Receive Overrun 1 Interrupt Enable */
+#define I2S_INTENCLR_RXOR1 (1 << I2S_INTENCLR_RXOR1_Pos)
+#define I2S_INTENCLR_RXOR_Pos 4 /**< \brief (I2S_INTENCLR) Receive Overrun x Interrupt Enable */
+#define I2S_INTENCLR_RXOR_Msk (0x3ul << I2S_INTENCLR_RXOR_Pos)
+#define I2S_INTENCLR_RXOR(value) (I2S_INTENCLR_RXOR_Msk & ((value) << I2S_INTENCLR_RXOR_Pos))
+#define I2S_INTENCLR_TXRDY0_Pos 8 /**< \brief (I2S_INTENCLR) Transmit Ready 0 Interrupt Enable */
+#define I2S_INTENCLR_TXRDY0 (1 << I2S_INTENCLR_TXRDY0_Pos)
+#define I2S_INTENCLR_TXRDY1_Pos 9 /**< \brief (I2S_INTENCLR) Transmit Ready 1 Interrupt Enable */
+#define I2S_INTENCLR_TXRDY1 (1 << I2S_INTENCLR_TXRDY1_Pos)
+#define I2S_INTENCLR_TXRDY_Pos 8 /**< \brief (I2S_INTENCLR) Transmit Ready x Interrupt Enable */
+#define I2S_INTENCLR_TXRDY_Msk (0x3ul << I2S_INTENCLR_TXRDY_Pos)
+#define I2S_INTENCLR_TXRDY(value) (I2S_INTENCLR_TXRDY_Msk & ((value) << I2S_INTENCLR_TXRDY_Pos))
+#define I2S_INTENCLR_TXUR0_Pos 12 /**< \brief (I2S_INTENCLR) Transmit Underrun 0 Interrupt Enable */
+#define I2S_INTENCLR_TXUR0 (1 << I2S_INTENCLR_TXUR0_Pos)
+#define I2S_INTENCLR_TXUR1_Pos 13 /**< \brief (I2S_INTENCLR) Transmit Underrun 1 Interrupt Enable */
+#define I2S_INTENCLR_TXUR1 (1 << I2S_INTENCLR_TXUR1_Pos)
+#define I2S_INTENCLR_TXUR_Pos 12 /**< \brief (I2S_INTENCLR) Transmit Underrun x Interrupt Enable */
+#define I2S_INTENCLR_TXUR_Msk (0x3ul << I2S_INTENCLR_TXUR_Pos)
+#define I2S_INTENCLR_TXUR(value) (I2S_INTENCLR_TXUR_Msk & ((value) << I2S_INTENCLR_TXUR_Pos))
+#define I2S_INTENCLR_MASK 0x3333ul /**< \brief (I2S_INTENCLR) MASK Register */
+
+/* -------- I2S_INTENSET : (I2S Offset: 0x10) (R/W 16) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 Interrupt Enable */
+ uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 Interrupt Enable */
+ uint16_t :2; /*!< bit: 2.. 3 Reserved */
+ uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 Interrupt Enable */
+ uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 Interrupt Enable */
+ uint16_t :2; /*!< bit: 6.. 7 Reserved */
+ uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 Interrupt Enable */
+ uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 Interrupt Enable */
+ uint16_t :2; /*!< bit: 10..11 Reserved */
+ uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 Interrupt Enable */
+ uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 Interrupt Enable */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x Interrupt Enable */
+ uint16_t :2; /*!< bit: 2.. 3 Reserved */
+ uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x Interrupt Enable */
+ uint16_t :2; /*!< bit: 6.. 7 Reserved */
+ uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x Interrupt Enable */
+ uint16_t :2; /*!< bit: 10..11 Reserved */
+ uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x Interrupt Enable */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} I2S_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define I2S_INTENSET_OFFSET 0x10 /**< \brief (I2S_INTENSET offset) Interrupt Enable Set */
+#define I2S_INTENSET_RESETVALUE 0x0000ul /**< \brief (I2S_INTENSET reset_value) Interrupt Enable Set */
+
+#define I2S_INTENSET_RXRDY0_Pos 0 /**< \brief (I2S_INTENSET) Receive Ready 0 Interrupt Enable */
+#define I2S_INTENSET_RXRDY0 (1 << I2S_INTENSET_RXRDY0_Pos)
+#define I2S_INTENSET_RXRDY1_Pos 1 /**< \brief (I2S_INTENSET) Receive Ready 1 Interrupt Enable */
+#define I2S_INTENSET_RXRDY1 (1 << I2S_INTENSET_RXRDY1_Pos)
+#define I2S_INTENSET_RXRDY_Pos 0 /**< \brief (I2S_INTENSET) Receive Ready x Interrupt Enable */
+#define I2S_INTENSET_RXRDY_Msk (0x3ul << I2S_INTENSET_RXRDY_Pos)
+#define I2S_INTENSET_RXRDY(value) (I2S_INTENSET_RXRDY_Msk & ((value) << I2S_INTENSET_RXRDY_Pos))
+#define I2S_INTENSET_RXOR0_Pos 4 /**< \brief (I2S_INTENSET) Receive Overrun 0 Interrupt Enable */
+#define I2S_INTENSET_RXOR0 (1 << I2S_INTENSET_RXOR0_Pos)
+#define I2S_INTENSET_RXOR1_Pos 5 /**< \brief (I2S_INTENSET) Receive Overrun 1 Interrupt Enable */
+#define I2S_INTENSET_RXOR1 (1 << I2S_INTENSET_RXOR1_Pos)
+#define I2S_INTENSET_RXOR_Pos 4 /**< \brief (I2S_INTENSET) Receive Overrun x Interrupt Enable */
+#define I2S_INTENSET_RXOR_Msk (0x3ul << I2S_INTENSET_RXOR_Pos)
+#define I2S_INTENSET_RXOR(value) (I2S_INTENSET_RXOR_Msk & ((value) << I2S_INTENSET_RXOR_Pos))
+#define I2S_INTENSET_TXRDY0_Pos 8 /**< \brief (I2S_INTENSET) Transmit Ready 0 Interrupt Enable */
+#define I2S_INTENSET_TXRDY0 (1 << I2S_INTENSET_TXRDY0_Pos)
+#define I2S_INTENSET_TXRDY1_Pos 9 /**< \brief (I2S_INTENSET) Transmit Ready 1 Interrupt Enable */
+#define I2S_INTENSET_TXRDY1 (1 << I2S_INTENSET_TXRDY1_Pos)
+#define I2S_INTENSET_TXRDY_Pos 8 /**< \brief (I2S_INTENSET) Transmit Ready x Interrupt Enable */
+#define I2S_INTENSET_TXRDY_Msk (0x3ul << I2S_INTENSET_TXRDY_Pos)
+#define I2S_INTENSET_TXRDY(value) (I2S_INTENSET_TXRDY_Msk & ((value) << I2S_INTENSET_TXRDY_Pos))
+#define I2S_INTENSET_TXUR0_Pos 12 /**< \brief (I2S_INTENSET) Transmit Underrun 0 Interrupt Enable */
+#define I2S_INTENSET_TXUR0 (1 << I2S_INTENSET_TXUR0_Pos)
+#define I2S_INTENSET_TXUR1_Pos 13 /**< \brief (I2S_INTENSET) Transmit Underrun 1 Interrupt Enable */
+#define I2S_INTENSET_TXUR1 (1 << I2S_INTENSET_TXUR1_Pos)
+#define I2S_INTENSET_TXUR_Pos 12 /**< \brief (I2S_INTENSET) Transmit Underrun x Interrupt Enable */
+#define I2S_INTENSET_TXUR_Msk (0x3ul << I2S_INTENSET_TXUR_Pos)
+#define I2S_INTENSET_TXUR(value) (I2S_INTENSET_TXUR_Msk & ((value) << I2S_INTENSET_TXUR_Pos))
+#define I2S_INTENSET_MASK 0x3333ul /**< \brief (I2S_INTENSET) MASK Register */
+
+/* -------- I2S_INTFLAG : (I2S Offset: 0x14) (R/W 16) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 */
+ __I uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 */
+ __I uint16_t :2; /*!< bit: 2.. 3 Reserved */
+ __I uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 */
+ __I uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 */
+ __I uint16_t :2; /*!< bit: 6.. 7 Reserved */
+ __I uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 */
+ __I uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 */
+ __I uint16_t :2; /*!< bit: 10..11 Reserved */
+ __I uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 */
+ __I uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 */
+ __I uint16_t :2; /*!< bit: 14..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ __I uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x */
+ __I uint16_t :2; /*!< bit: 2.. 3 Reserved */
+ __I uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x */
+ __I uint16_t :2; /*!< bit: 6.. 7 Reserved */
+ __I uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x */
+ __I uint16_t :2; /*!< bit: 10..11 Reserved */
+ __I uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x */
+ __I uint16_t :2; /*!< bit: 14..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} I2S_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define I2S_INTFLAG_OFFSET 0x14 /**< \brief (I2S_INTFLAG offset) Interrupt Flag Status and Clear */
+#define I2S_INTFLAG_RESETVALUE 0x0000ul /**< \brief (I2S_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define I2S_INTFLAG_RXRDY0_Pos 0 /**< \brief (I2S_INTFLAG) Receive Ready 0 */
+#define I2S_INTFLAG_RXRDY0 (1 << I2S_INTFLAG_RXRDY0_Pos)
+#define I2S_INTFLAG_RXRDY1_Pos 1 /**< \brief (I2S_INTFLAG) Receive Ready 1 */
+#define I2S_INTFLAG_RXRDY1 (1 << I2S_INTFLAG_RXRDY1_Pos)
+#define I2S_INTFLAG_RXRDY_Pos 0 /**< \brief (I2S_INTFLAG) Receive Ready x */
+#define I2S_INTFLAG_RXRDY_Msk (0x3ul << I2S_INTFLAG_RXRDY_Pos)
+#define I2S_INTFLAG_RXRDY(value) (I2S_INTFLAG_RXRDY_Msk & ((value) << I2S_INTFLAG_RXRDY_Pos))
+#define I2S_INTFLAG_RXOR0_Pos 4 /**< \brief (I2S_INTFLAG) Receive Overrun 0 */
+#define I2S_INTFLAG_RXOR0 (1 << I2S_INTFLAG_RXOR0_Pos)
+#define I2S_INTFLAG_RXOR1_Pos 5 /**< \brief (I2S_INTFLAG) Receive Overrun 1 */
+#define I2S_INTFLAG_RXOR1 (1 << I2S_INTFLAG_RXOR1_Pos)
+#define I2S_INTFLAG_RXOR_Pos 4 /**< \brief (I2S_INTFLAG) Receive Overrun x */
+#define I2S_INTFLAG_RXOR_Msk (0x3ul << I2S_INTFLAG_RXOR_Pos)
+#define I2S_INTFLAG_RXOR(value) (I2S_INTFLAG_RXOR_Msk & ((value) << I2S_INTFLAG_RXOR_Pos))
+#define I2S_INTFLAG_TXRDY0_Pos 8 /**< \brief (I2S_INTFLAG) Transmit Ready 0 */
+#define I2S_INTFLAG_TXRDY0 (1 << I2S_INTFLAG_TXRDY0_Pos)
+#define I2S_INTFLAG_TXRDY1_Pos 9 /**< \brief (I2S_INTFLAG) Transmit Ready 1 */
+#define I2S_INTFLAG_TXRDY1 (1 << I2S_INTFLAG_TXRDY1_Pos)
+#define I2S_INTFLAG_TXRDY_Pos 8 /**< \brief (I2S_INTFLAG) Transmit Ready x */
+#define I2S_INTFLAG_TXRDY_Msk (0x3ul << I2S_INTFLAG_TXRDY_Pos)
+#define I2S_INTFLAG_TXRDY(value) (I2S_INTFLAG_TXRDY_Msk & ((value) << I2S_INTFLAG_TXRDY_Pos))
+#define I2S_INTFLAG_TXUR0_Pos 12 /**< \brief (I2S_INTFLAG) Transmit Underrun 0 */
+#define I2S_INTFLAG_TXUR0 (1 << I2S_INTFLAG_TXUR0_Pos)
+#define I2S_INTFLAG_TXUR1_Pos 13 /**< \brief (I2S_INTFLAG) Transmit Underrun 1 */
+#define I2S_INTFLAG_TXUR1 (1 << I2S_INTFLAG_TXUR1_Pos)
+#define I2S_INTFLAG_TXUR_Pos 12 /**< \brief (I2S_INTFLAG) Transmit Underrun x */
+#define I2S_INTFLAG_TXUR_Msk (0x3ul << I2S_INTFLAG_TXUR_Pos)
+#define I2S_INTFLAG_TXUR(value) (I2S_INTFLAG_TXUR_Msk & ((value) << I2S_INTFLAG_TXUR_Pos))
+#define I2S_INTFLAG_MASK 0x3333ul /**< \brief (I2S_INTFLAG) MASK Register */
+
+/* -------- I2S_SYNCBUSY : (I2S Offset: 0x18) (R/ 16) Synchronization Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Status */
+ uint16_t ENABLE:1; /*!< bit: 1 Enable Synchronization Status */
+ uint16_t CKEN0:1; /*!< bit: 2 Clock Unit 0 Enable Synchronization Status */
+ uint16_t CKEN1:1; /*!< bit: 3 Clock Unit 1 Enable Synchronization Status */
+ uint16_t SEREN0:1; /*!< bit: 4 Serializer 0 Enable Synchronization Status */
+ uint16_t SEREN1:1; /*!< bit: 5 Serializer 1 Enable Synchronization Status */
+ uint16_t :2; /*!< bit: 6.. 7 Reserved */
+ uint16_t DATA0:1; /*!< bit: 8 Data 0 Synchronization Status */
+ uint16_t DATA1:1; /*!< bit: 9 Data 1 Synchronization Status */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t :2; /*!< bit: 0.. 1 Reserved */
+ uint16_t CKEN:2; /*!< bit: 2.. 3 Clock Unit x Enable Synchronization Status */
+ uint16_t SEREN:2; /*!< bit: 4.. 5 Serializer x Enable Synchronization Status */
+ uint16_t :2; /*!< bit: 6.. 7 Reserved */
+ uint16_t DATA:2; /*!< bit: 8.. 9 Data x Synchronization Status */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} I2S_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define I2S_SYNCBUSY_OFFSET 0x18 /**< \brief (I2S_SYNCBUSY offset) Synchronization Status */
+#define I2S_SYNCBUSY_RESETVALUE 0x0000ul /**< \brief (I2S_SYNCBUSY reset_value) Synchronization Status */
+
+#define I2S_SYNCBUSY_SWRST_Pos 0 /**< \brief (I2S_SYNCBUSY) Software Reset Synchronization Status */
+#define I2S_SYNCBUSY_SWRST (0x1ul << I2S_SYNCBUSY_SWRST_Pos)
+#define I2S_SYNCBUSY_ENABLE_Pos 1 /**< \brief (I2S_SYNCBUSY) Enable Synchronization Status */
+#define I2S_SYNCBUSY_ENABLE (0x1ul << I2S_SYNCBUSY_ENABLE_Pos)
+#define I2S_SYNCBUSY_CKEN0_Pos 2 /**< \brief (I2S_SYNCBUSY) Clock Unit 0 Enable Synchronization Status */
+#define I2S_SYNCBUSY_CKEN0 (1 << I2S_SYNCBUSY_CKEN0_Pos)
+#define I2S_SYNCBUSY_CKEN1_Pos 3 /**< \brief (I2S_SYNCBUSY) Clock Unit 1 Enable Synchronization Status */
+#define I2S_SYNCBUSY_CKEN1 (1 << I2S_SYNCBUSY_CKEN1_Pos)
+#define I2S_SYNCBUSY_CKEN_Pos 2 /**< \brief (I2S_SYNCBUSY) Clock Unit x Enable Synchronization Status */
+#define I2S_SYNCBUSY_CKEN_Msk (0x3ul << I2S_SYNCBUSY_CKEN_Pos)
+#define I2S_SYNCBUSY_CKEN(value) (I2S_SYNCBUSY_CKEN_Msk & ((value) << I2S_SYNCBUSY_CKEN_Pos))
+#define I2S_SYNCBUSY_SEREN0_Pos 4 /**< \brief (I2S_SYNCBUSY) Serializer 0 Enable Synchronization Status */
+#define I2S_SYNCBUSY_SEREN0 (1 << I2S_SYNCBUSY_SEREN0_Pos)
+#define I2S_SYNCBUSY_SEREN1_Pos 5 /**< \brief (I2S_SYNCBUSY) Serializer 1 Enable Synchronization Status */
+#define I2S_SYNCBUSY_SEREN1 (1 << I2S_SYNCBUSY_SEREN1_Pos)
+#define I2S_SYNCBUSY_SEREN_Pos 4 /**< \brief (I2S_SYNCBUSY) Serializer x Enable Synchronization Status */
+#define I2S_SYNCBUSY_SEREN_Msk (0x3ul << I2S_SYNCBUSY_SEREN_Pos)
+#define I2S_SYNCBUSY_SEREN(value) (I2S_SYNCBUSY_SEREN_Msk & ((value) << I2S_SYNCBUSY_SEREN_Pos))
+#define I2S_SYNCBUSY_DATA0_Pos 8 /**< \brief (I2S_SYNCBUSY) Data 0 Synchronization Status */
+#define I2S_SYNCBUSY_DATA0 (1 << I2S_SYNCBUSY_DATA0_Pos)
+#define I2S_SYNCBUSY_DATA1_Pos 9 /**< \brief (I2S_SYNCBUSY) Data 1 Synchronization Status */
+#define I2S_SYNCBUSY_DATA1 (1 << I2S_SYNCBUSY_DATA1_Pos)
+#define I2S_SYNCBUSY_DATA_Pos 8 /**< \brief (I2S_SYNCBUSY) Data x Synchronization Status */
+#define I2S_SYNCBUSY_DATA_Msk (0x3ul << I2S_SYNCBUSY_DATA_Pos)
+#define I2S_SYNCBUSY_DATA(value) (I2S_SYNCBUSY_DATA_Msk & ((value) << I2S_SYNCBUSY_DATA_Pos))
+#define I2S_SYNCBUSY_MASK 0x033Ful /**< \brief (I2S_SYNCBUSY) MASK Register */
+
+/* -------- I2S_SERCTRL : (I2S Offset: 0x20) (R/W 32) Serializer n Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SERMODE:2; /*!< bit: 0.. 1 Serializer Mode */
+ uint32_t TXDEFAULT:2; /*!< bit: 2.. 3 Line Default Line when Slot Disabled */
+ uint32_t TXSAME:1; /*!< bit: 4 Transmit Data when Underrun */
+ uint32_t CLKSEL:1; /*!< bit: 5 Clock Unit Selection */
+ uint32_t :1; /*!< bit: 6 Reserved */
+ uint32_t SLOTADJ:1; /*!< bit: 7 Data Slot Formatting Adjust */
+ uint32_t DATASIZE:3; /*!< bit: 8..10 Data Word Size */
+ uint32_t :1; /*!< bit: 11 Reserved */
+ uint32_t WORDADJ:1; /*!< bit: 12 Data Word Formatting Adjust */
+ uint32_t EXTEND:2; /*!< bit: 13..14 Data Formatting Bit Extension */
+ uint32_t BITREV:1; /*!< bit: 15 Data Formatting Bit Reverse */
+ uint32_t SLOTDIS0:1; /*!< bit: 16 Slot 0 Disabled for this Serializer */
+ uint32_t SLOTDIS1:1; /*!< bit: 17 Slot 1 Disabled for this Serializer */
+ uint32_t SLOTDIS2:1; /*!< bit: 18 Slot 2 Disabled for this Serializer */
+ uint32_t SLOTDIS3:1; /*!< bit: 19 Slot 3 Disabled for this Serializer */
+ uint32_t SLOTDIS4:1; /*!< bit: 20 Slot 4 Disabled for this Serializer */
+ uint32_t SLOTDIS5:1; /*!< bit: 21 Slot 5 Disabled for this Serializer */
+ uint32_t SLOTDIS6:1; /*!< bit: 22 Slot 6 Disabled for this Serializer */
+ uint32_t SLOTDIS7:1; /*!< bit: 23 Slot 7 Disabled for this Serializer */
+ uint32_t MONO:1; /*!< bit: 24 Mono Mode */
+ uint32_t DMA:1; /*!< bit: 25 Single or Multiple DMA Channels */
+ uint32_t RXLOOP:1; /*!< bit: 26 Loop-back Test Mode */
+ uint32_t :5; /*!< bit: 27..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :16; /*!< bit: 0..15 Reserved */
+ uint32_t SLOTDIS:8; /*!< bit: 16..23 Slot x Disabled for this Serializer */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} I2S_SERCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define I2S_SERCTRL_OFFSET 0x20 /**< \brief (I2S_SERCTRL offset) Serializer n Control */
+#define I2S_SERCTRL_RESETVALUE 0x00000000ul /**< \brief (I2S_SERCTRL reset_value) Serializer n Control */
+
+#define I2S_SERCTRL_SERMODE_Pos 0 /**< \brief (I2S_SERCTRL) Serializer Mode */
+#define I2S_SERCTRL_SERMODE_Msk (0x3ul << I2S_SERCTRL_SERMODE_Pos)
+#define I2S_SERCTRL_SERMODE(value) (I2S_SERCTRL_SERMODE_Msk & ((value) << I2S_SERCTRL_SERMODE_Pos))
+#define I2S_SERCTRL_SERMODE_RX_Val 0x0ul /**< \brief (I2S_SERCTRL) Receive */
+#define I2S_SERCTRL_SERMODE_TX_Val 0x1ul /**< \brief (I2S_SERCTRL) Transmit */
+#define I2S_SERCTRL_SERMODE_PDM2_Val 0x2ul /**< \brief (I2S_SERCTRL) Receive one PDM data on each serial clock edge */
+#define I2S_SERCTRL_SERMODE_RX (I2S_SERCTRL_SERMODE_RX_Val << I2S_SERCTRL_SERMODE_Pos)
+#define I2S_SERCTRL_SERMODE_TX (I2S_SERCTRL_SERMODE_TX_Val << I2S_SERCTRL_SERMODE_Pos)
+#define I2S_SERCTRL_SERMODE_PDM2 (I2S_SERCTRL_SERMODE_PDM2_Val << I2S_SERCTRL_SERMODE_Pos)
+#define I2S_SERCTRL_TXDEFAULT_Pos 2 /**< \brief (I2S_SERCTRL) Line Default Line when Slot Disabled */
+#define I2S_SERCTRL_TXDEFAULT_Msk (0x3ul << I2S_SERCTRL_TXDEFAULT_Pos)
+#define I2S_SERCTRL_TXDEFAULT(value) (I2S_SERCTRL_TXDEFAULT_Msk & ((value) << I2S_SERCTRL_TXDEFAULT_Pos))
+#define I2S_SERCTRL_TXDEFAULT_ZERO_Val 0x0ul /**< \brief (I2S_SERCTRL) Output Default Value is 0 */
+#define I2S_SERCTRL_TXDEFAULT_ONE_Val 0x1ul /**< \brief (I2S_SERCTRL) Output Default Value is 1 */
+#define I2S_SERCTRL_TXDEFAULT_HIZ_Val 0x3ul /**< \brief (I2S_SERCTRL) Output Default Value is high impedance */
+#define I2S_SERCTRL_TXDEFAULT_ZERO (I2S_SERCTRL_TXDEFAULT_ZERO_Val << I2S_SERCTRL_TXDEFAULT_Pos)
+#define I2S_SERCTRL_TXDEFAULT_ONE (I2S_SERCTRL_TXDEFAULT_ONE_Val << I2S_SERCTRL_TXDEFAULT_Pos)
+#define I2S_SERCTRL_TXDEFAULT_HIZ (I2S_SERCTRL_TXDEFAULT_HIZ_Val << I2S_SERCTRL_TXDEFAULT_Pos)
+#define I2S_SERCTRL_TXSAME_Pos 4 /**< \brief (I2S_SERCTRL) Transmit Data when Underrun */
+#define I2S_SERCTRL_TXSAME (0x1ul << I2S_SERCTRL_TXSAME_Pos)
+#define I2S_SERCTRL_TXSAME_ZERO_Val 0x0ul /**< \brief (I2S_SERCTRL) Zero data transmitted in case of underrun */
+#define I2S_SERCTRL_TXSAME_SAME_Val 0x1ul /**< \brief (I2S_SERCTRL) Last data transmitted in case of underrun */
+#define I2S_SERCTRL_TXSAME_ZERO (I2S_SERCTRL_TXSAME_ZERO_Val << I2S_SERCTRL_TXSAME_Pos)
+#define I2S_SERCTRL_TXSAME_SAME (I2S_SERCTRL_TXSAME_SAME_Val << I2S_SERCTRL_TXSAME_Pos)
+#define I2S_SERCTRL_CLKSEL_Pos 5 /**< \brief (I2S_SERCTRL) Clock Unit Selection */
+#define I2S_SERCTRL_CLKSEL (0x1ul << I2S_SERCTRL_CLKSEL_Pos)
+#define I2S_SERCTRL_CLKSEL_CLK0_Val 0x0ul /**< \brief (I2S_SERCTRL) Use Clock Unit 0 */
+#define I2S_SERCTRL_CLKSEL_CLK1_Val 0x1ul /**< \brief (I2S_SERCTRL) Use Clock Unit 1 */
+#define I2S_SERCTRL_CLKSEL_CLK0 (I2S_SERCTRL_CLKSEL_CLK0_Val << I2S_SERCTRL_CLKSEL_Pos)
+#define I2S_SERCTRL_CLKSEL_CLK1 (I2S_SERCTRL_CLKSEL_CLK1_Val << I2S_SERCTRL_CLKSEL_Pos)
+#define I2S_SERCTRL_SLOTADJ_Pos 7 /**< \brief (I2S_SERCTRL) Data Slot Formatting Adjust */
+#define I2S_SERCTRL_SLOTADJ (0x1ul << I2S_SERCTRL_SLOTADJ_Pos)
+#define I2S_SERCTRL_SLOTADJ_RIGHT_Val 0x0ul /**< \brief (I2S_SERCTRL) Data is right adjusted in slot */
+#define I2S_SERCTRL_SLOTADJ_LEFT_Val 0x1ul /**< \brief (I2S_SERCTRL) Data is left adjusted in slot */
+#define I2S_SERCTRL_SLOTADJ_RIGHT (I2S_SERCTRL_SLOTADJ_RIGHT_Val << I2S_SERCTRL_SLOTADJ_Pos)
+#define I2S_SERCTRL_SLOTADJ_LEFT (I2S_SERCTRL_SLOTADJ_LEFT_Val << I2S_SERCTRL_SLOTADJ_Pos)
+#define I2S_SERCTRL_DATASIZE_Pos 8 /**< \brief (I2S_SERCTRL) Data Word Size */
+#define I2S_SERCTRL_DATASIZE_Msk (0x7ul << I2S_SERCTRL_DATASIZE_Pos)
+#define I2S_SERCTRL_DATASIZE(value) (I2S_SERCTRL_DATASIZE_Msk & ((value) << I2S_SERCTRL_DATASIZE_Pos))
+#define I2S_SERCTRL_DATASIZE_32_Val 0x0ul /**< \brief (I2S_SERCTRL) 32 bits */
+#define I2S_SERCTRL_DATASIZE_24_Val 0x1ul /**< \brief (I2S_SERCTRL) 24 bits */
+#define I2S_SERCTRL_DATASIZE_20_Val 0x2ul /**< \brief (I2S_SERCTRL) 20 bits */
+#define I2S_SERCTRL_DATASIZE_18_Val 0x3ul /**< \brief (I2S_SERCTRL) 18 bits */
+#define I2S_SERCTRL_DATASIZE_16_Val 0x4ul /**< \brief (I2S_SERCTRL) 16 bits */
+#define I2S_SERCTRL_DATASIZE_16C_Val 0x5ul /**< \brief (I2S_SERCTRL) 16 bits compact stereo */
+#define I2S_SERCTRL_DATASIZE_8_Val 0x6ul /**< \brief (I2S_SERCTRL) 8 bits */
+#define I2S_SERCTRL_DATASIZE_8C_Val 0x7ul /**< \brief (I2S_SERCTRL) 8 bits compact stereo */
+#define I2S_SERCTRL_DATASIZE_32 (I2S_SERCTRL_DATASIZE_32_Val << I2S_SERCTRL_DATASIZE_Pos)
+#define I2S_SERCTRL_DATASIZE_24 (I2S_SERCTRL_DATASIZE_24_Val << I2S_SERCTRL_DATASIZE_Pos)
+#define I2S_SERCTRL_DATASIZE_20 (I2S_SERCTRL_DATASIZE_20_Val << I2S_SERCTRL_DATASIZE_Pos)
+#define I2S_SERCTRL_DATASIZE_18 (I2S_SERCTRL_DATASIZE_18_Val << I2S_SERCTRL_DATASIZE_Pos)
+#define I2S_SERCTRL_DATASIZE_16 (I2S_SERCTRL_DATASIZE_16_Val << I2S_SERCTRL_DATASIZE_Pos)
+#define I2S_SERCTRL_DATASIZE_16C (I2S_SERCTRL_DATASIZE_16C_Val << I2S_SERCTRL_DATASIZE_Pos)
+#define I2S_SERCTRL_DATASIZE_8 (I2S_SERCTRL_DATASIZE_8_Val << I2S_SERCTRL_DATASIZE_Pos)
+#define I2S_SERCTRL_DATASIZE_8C (I2S_SERCTRL_DATASIZE_8C_Val << I2S_SERCTRL_DATASIZE_Pos)
+#define I2S_SERCTRL_WORDADJ_Pos 12 /**< \brief (I2S_SERCTRL) Data Word Formatting Adjust */
+#define I2S_SERCTRL_WORDADJ (0x1ul << I2S_SERCTRL_WORDADJ_Pos)
+#define I2S_SERCTRL_WORDADJ_RIGHT_Val 0x0ul /**< \brief (I2S_SERCTRL) Data is right adjusted in word */
+#define I2S_SERCTRL_WORDADJ_LEFT_Val 0x1ul /**< \brief (I2S_SERCTRL) Data is left adjusted in word */
+#define I2S_SERCTRL_WORDADJ_RIGHT (I2S_SERCTRL_WORDADJ_RIGHT_Val << I2S_SERCTRL_WORDADJ_Pos)
+#define I2S_SERCTRL_WORDADJ_LEFT (I2S_SERCTRL_WORDADJ_LEFT_Val << I2S_SERCTRL_WORDADJ_Pos)
+#define I2S_SERCTRL_EXTEND_Pos 13 /**< \brief (I2S_SERCTRL) Data Formatting Bit Extension */
+#define I2S_SERCTRL_EXTEND_Msk (0x3ul << I2S_SERCTRL_EXTEND_Pos)
+#define I2S_SERCTRL_EXTEND(value) (I2S_SERCTRL_EXTEND_Msk & ((value) << I2S_SERCTRL_EXTEND_Pos))
+#define I2S_SERCTRL_EXTEND_ZERO_Val 0x0ul /**< \brief (I2S_SERCTRL) Extend with zeroes */
+#define I2S_SERCTRL_EXTEND_ONE_Val 0x1ul /**< \brief (I2S_SERCTRL) Extend with ones */
+#define I2S_SERCTRL_EXTEND_MSBIT_Val 0x2ul /**< \brief (I2S_SERCTRL) Extend with Most Significant Bit */
+#define I2S_SERCTRL_EXTEND_LSBIT_Val 0x3ul /**< \brief (I2S_SERCTRL) Extend with Least Significant Bit */
+#define I2S_SERCTRL_EXTEND_ZERO (I2S_SERCTRL_EXTEND_ZERO_Val << I2S_SERCTRL_EXTEND_Pos)
+#define I2S_SERCTRL_EXTEND_ONE (I2S_SERCTRL_EXTEND_ONE_Val << I2S_SERCTRL_EXTEND_Pos)
+#define I2S_SERCTRL_EXTEND_MSBIT (I2S_SERCTRL_EXTEND_MSBIT_Val << I2S_SERCTRL_EXTEND_Pos)
+#define I2S_SERCTRL_EXTEND_LSBIT (I2S_SERCTRL_EXTEND_LSBIT_Val << I2S_SERCTRL_EXTEND_Pos)
+#define I2S_SERCTRL_BITREV_Pos 15 /**< \brief (I2S_SERCTRL) Data Formatting Bit Reverse */
+#define I2S_SERCTRL_BITREV (0x1ul << I2S_SERCTRL_BITREV_Pos)
+#define I2S_SERCTRL_BITREV_MSBIT_Val 0x0ul /**< \brief (I2S_SERCTRL) Transfer Data Most Significant Bit (MSB) first (default for I2S protocol) */
+#define I2S_SERCTRL_BITREV_LSBIT_Val 0x1ul /**< \brief (I2S_SERCTRL) Transfer Data Least Significant Bit (LSB) first */
+#define I2S_SERCTRL_BITREV_MSBIT (I2S_SERCTRL_BITREV_MSBIT_Val << I2S_SERCTRL_BITREV_Pos)
+#define I2S_SERCTRL_BITREV_LSBIT (I2S_SERCTRL_BITREV_LSBIT_Val << I2S_SERCTRL_BITREV_Pos)
+#define I2S_SERCTRL_SLOTDIS0_Pos 16 /**< \brief (I2S_SERCTRL) Slot 0 Disabled for this Serializer */
+#define I2S_SERCTRL_SLOTDIS0 (1 << I2S_SERCTRL_SLOTDIS0_Pos)
+#define I2S_SERCTRL_SLOTDIS1_Pos 17 /**< \brief (I2S_SERCTRL) Slot 1 Disabled for this Serializer */
+#define I2S_SERCTRL_SLOTDIS1 (1 << I2S_SERCTRL_SLOTDIS1_Pos)
+#define I2S_SERCTRL_SLOTDIS2_Pos 18 /**< \brief (I2S_SERCTRL) Slot 2 Disabled for this Serializer */
+#define I2S_SERCTRL_SLOTDIS2 (1 << I2S_SERCTRL_SLOTDIS2_Pos)
+#define I2S_SERCTRL_SLOTDIS3_Pos 19 /**< \brief (I2S_SERCTRL) Slot 3 Disabled for this Serializer */
+#define I2S_SERCTRL_SLOTDIS3 (1 << I2S_SERCTRL_SLOTDIS3_Pos)
+#define I2S_SERCTRL_SLOTDIS4_Pos 20 /**< \brief (I2S_SERCTRL) Slot 4 Disabled for this Serializer */
+#define I2S_SERCTRL_SLOTDIS4 (1 << I2S_SERCTRL_SLOTDIS4_Pos)
+#define I2S_SERCTRL_SLOTDIS5_Pos 21 /**< \brief (I2S_SERCTRL) Slot 5 Disabled for this Serializer */
+#define I2S_SERCTRL_SLOTDIS5 (1 << I2S_SERCTRL_SLOTDIS5_Pos)
+#define I2S_SERCTRL_SLOTDIS6_Pos 22 /**< \brief (I2S_SERCTRL) Slot 6 Disabled for this Serializer */
+#define I2S_SERCTRL_SLOTDIS6 (1 << I2S_SERCTRL_SLOTDIS6_Pos)
+#define I2S_SERCTRL_SLOTDIS7_Pos 23 /**< \brief (I2S_SERCTRL) Slot 7 Disabled for this Serializer */
+#define I2S_SERCTRL_SLOTDIS7 (1 << I2S_SERCTRL_SLOTDIS7_Pos)
+#define I2S_SERCTRL_SLOTDIS_Pos 16 /**< \brief (I2S_SERCTRL) Slot x Disabled for this Serializer */
+#define I2S_SERCTRL_SLOTDIS_Msk (0xFFul << I2S_SERCTRL_SLOTDIS_Pos)
+#define I2S_SERCTRL_SLOTDIS(value) (I2S_SERCTRL_SLOTDIS_Msk & ((value) << I2S_SERCTRL_SLOTDIS_Pos))
+#define I2S_SERCTRL_MONO_Pos 24 /**< \brief (I2S_SERCTRL) Mono Mode */
+#define I2S_SERCTRL_MONO (0x1ul << I2S_SERCTRL_MONO_Pos)
+#define I2S_SERCTRL_MONO_STEREO_Val 0x0ul /**< \brief (I2S_SERCTRL) Normal mode */
+#define I2S_SERCTRL_MONO_MONO_Val 0x1ul /**< \brief (I2S_SERCTRL) Left channel data is duplicated to right channel */
+#define I2S_SERCTRL_MONO_STEREO (I2S_SERCTRL_MONO_STEREO_Val << I2S_SERCTRL_MONO_Pos)
+#define I2S_SERCTRL_MONO_MONO (I2S_SERCTRL_MONO_MONO_Val << I2S_SERCTRL_MONO_Pos)
+#define I2S_SERCTRL_DMA_Pos 25 /**< \brief (I2S_SERCTRL) Single or Multiple DMA Channels */
+#define I2S_SERCTRL_DMA (0x1ul << I2S_SERCTRL_DMA_Pos)
+#define I2S_SERCTRL_DMA_SINGLE_Val 0x0ul /**< \brief (I2S_SERCTRL) Single DMA channel */
+#define I2S_SERCTRL_DMA_MULTIPLE_Val 0x1ul /**< \brief (I2S_SERCTRL) One DMA channel per data channel */
+#define I2S_SERCTRL_DMA_SINGLE (I2S_SERCTRL_DMA_SINGLE_Val << I2S_SERCTRL_DMA_Pos)
+#define I2S_SERCTRL_DMA_MULTIPLE (I2S_SERCTRL_DMA_MULTIPLE_Val << I2S_SERCTRL_DMA_Pos)
+#define I2S_SERCTRL_RXLOOP_Pos 26 /**< \brief (I2S_SERCTRL) Loop-back Test Mode */
+#define I2S_SERCTRL_RXLOOP (0x1ul << I2S_SERCTRL_RXLOOP_Pos)
+#define I2S_SERCTRL_MASK 0x07FFF7BFul /**< \brief (I2S_SERCTRL) MASK Register */
+
+/* -------- I2S_DATA : (I2S Offset: 0x30) (R/W 32) Data n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DATA:32; /*!< bit: 0..31 Sample Data */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} I2S_DATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define I2S_DATA_OFFSET 0x30 /**< \brief (I2S_DATA offset) Data n */
+#define I2S_DATA_RESETVALUE 0x00000000ul /**< \brief (I2S_DATA reset_value) Data n */
+
+#define I2S_DATA_DATA_Pos 0 /**< \brief (I2S_DATA) Sample Data */
+#define I2S_DATA_DATA_Msk (0xFFFFFFFFul << I2S_DATA_DATA_Pos)
+#define I2S_DATA_DATA(value) (I2S_DATA_DATA_Msk & ((value) << I2S_DATA_DATA_Pos))
+#define I2S_DATA_MASK 0xFFFFFFFFul /**< \brief (I2S_DATA) MASK Register */
+
+/** \brief I2S hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO I2S_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
+ RoReg8 Reserved1[0x3];
+ __IO I2S_CLKCTRL_Type CLKCTRL[2]; /**< \brief Offset: 0x04 (R/W 32) Clock Unit n Control */
+ __IO I2S_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 16) Interrupt Enable Clear */
+ RoReg8 Reserved2[0x2];
+ __IO I2S_INTENSET_Type INTENSET; /**< \brief Offset: 0x10 (R/W 16) Interrupt Enable Set */
+ RoReg8 Reserved3[0x2];
+ __IO I2S_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x14 (R/W 16) Interrupt Flag Status and Clear */
+ RoReg8 Reserved4[0x2];
+ __I I2S_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x18 (R/ 16) Synchronization Status */
+ RoReg8 Reserved5[0x6];
+ __IO I2S_SERCTRL_Type SERCTRL[2]; /**< \brief Offset: 0x20 (R/W 32) Serializer n Control */
+ RoReg8 Reserved6[0x8];
+ __IO I2S_DATA_Type DATA[2]; /**< \brief Offset: 0x30 (R/W 32) Data n */
+} I2s;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_I2S_COMPONENT_ */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/component/mtb.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/component/mtb.h
new file mode 100644
index 0000000000000000000000000000000000000000..f1afb396bd1377e60c086cd2f2337ab1d387c805
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/component/mtb.h
@@ -0,0 +1,396 @@
+/**
+ * \file
+ *
+ * \brief Component description for MTB
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_MTB_COMPONENT_
+#define _SAMD21_MTB_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR MTB */
+/* ========================================================================== */
+/** \addtogroup SAMD21_MTB Cortex-M0+ Micro-Trace Buffer */
+/*@{*/
+
+#define MTB_U2002
+#define REV_MTB 0x100
+
+/* -------- MTB_POSITION : (MTB Offset: 0x000) (R/W 32) MTB Position -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :2; /*!< bit: 0.. 1 Reserved */
+ uint32_t WRAP:1; /*!< bit: 2 Pointer Value Wraps */
+ uint32_t POINTER:29; /*!< bit: 3..31 Trace Packet Location Pointer */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} MTB_POSITION_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_POSITION_OFFSET 0x000 /**< \brief (MTB_POSITION offset) MTB Position */
+
+#define MTB_POSITION_WRAP_Pos 2 /**< \brief (MTB_POSITION) Pointer Value Wraps */
+#define MTB_POSITION_WRAP (0x1ul << MTB_POSITION_WRAP_Pos)
+#define MTB_POSITION_POINTER_Pos 3 /**< \brief (MTB_POSITION) Trace Packet Location Pointer */
+#define MTB_POSITION_POINTER_Msk (0x1FFFFFFFul << MTB_POSITION_POINTER_Pos)
+#define MTB_POSITION_POINTER(value) (MTB_POSITION_POINTER_Msk & ((value) << MTB_POSITION_POINTER_Pos))
+#define MTB_POSITION_MASK 0xFFFFFFFCul /**< \brief (MTB_POSITION) MASK Register */
+
+/* -------- MTB_MASTER : (MTB Offset: 0x004) (R/W 32) MTB Master -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t MASK:5; /*!< bit: 0.. 4 Maximum Value of the Trace Buffer in SRAM */
+ uint32_t TSTARTEN:1; /*!< bit: 5 Trace Start Input Enable */
+ uint32_t TSTOPEN:1; /*!< bit: 6 Trace Stop Input Enable */
+ uint32_t SFRWPRIV:1; /*!< bit: 7 Special Function Register Write Privilege */
+ uint32_t RAMPRIV:1; /*!< bit: 8 SRAM Privilege */
+ uint32_t HALTREQ:1; /*!< bit: 9 Halt Request */
+ uint32_t :21; /*!< bit: 10..30 Reserved */
+ uint32_t EN:1; /*!< bit: 31 Main Trace Enable */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} MTB_MASTER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_MASTER_OFFSET 0x004 /**< \brief (MTB_MASTER offset) MTB Master */
+#define MTB_MASTER_RESETVALUE 0x00000000ul /**< \brief (MTB_MASTER reset_value) MTB Master */
+
+#define MTB_MASTER_MASK_Pos 0 /**< \brief (MTB_MASTER) Maximum Value of the Trace Buffer in SRAM */
+#define MTB_MASTER_MASK_Msk (0x1Ful << MTB_MASTER_MASK_Pos)
+#define MTB_MASTER_MASK(value) (MTB_MASTER_MASK_Msk & ((value) << MTB_MASTER_MASK_Pos))
+#define MTB_MASTER_TSTARTEN_Pos 5 /**< \brief (MTB_MASTER) Trace Start Input Enable */
+#define MTB_MASTER_TSTARTEN (0x1ul << MTB_MASTER_TSTARTEN_Pos)
+#define MTB_MASTER_TSTOPEN_Pos 6 /**< \brief (MTB_MASTER) Trace Stop Input Enable */
+#define MTB_MASTER_TSTOPEN (0x1ul << MTB_MASTER_TSTOPEN_Pos)
+#define MTB_MASTER_SFRWPRIV_Pos 7 /**< \brief (MTB_MASTER) Special Function Register Write Privilege */
+#define MTB_MASTER_SFRWPRIV (0x1ul << MTB_MASTER_SFRWPRIV_Pos)
+#define MTB_MASTER_RAMPRIV_Pos 8 /**< \brief (MTB_MASTER) SRAM Privilege */
+#define MTB_MASTER_RAMPRIV (0x1ul << MTB_MASTER_RAMPRIV_Pos)
+#define MTB_MASTER_HALTREQ_Pos 9 /**< \brief (MTB_MASTER) Halt Request */
+#define MTB_MASTER_HALTREQ (0x1ul << MTB_MASTER_HALTREQ_Pos)
+#define MTB_MASTER_EN_Pos 31 /**< \brief (MTB_MASTER) Main Trace Enable */
+#define MTB_MASTER_EN (0x1ul << MTB_MASTER_EN_Pos)
+#define MTB_MASTER_MASK_ 0x800003FFul /**< \brief (MTB_MASTER) MASK Register */
+
+/* -------- MTB_FLOW : (MTB Offset: 0x008) (R/W 32) MTB Flow -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t AUTOSTOP:1; /*!< bit: 0 Auto Stop Tracing */
+ uint32_t AUTOHALT:1; /*!< bit: 1 Auto Halt Request */
+ uint32_t :1; /*!< bit: 2 Reserved */
+ uint32_t WATERMARK:29; /*!< bit: 3..31 Watermark value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} MTB_FLOW_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_FLOW_OFFSET 0x008 /**< \brief (MTB_FLOW offset) MTB Flow */
+#define MTB_FLOW_RESETVALUE 0x00000000ul /**< \brief (MTB_FLOW reset_value) MTB Flow */
+
+#define MTB_FLOW_AUTOSTOP_Pos 0 /**< \brief (MTB_FLOW) Auto Stop Tracing */
+#define MTB_FLOW_AUTOSTOP (0x1ul << MTB_FLOW_AUTOSTOP_Pos)
+#define MTB_FLOW_AUTOHALT_Pos 1 /**< \brief (MTB_FLOW) Auto Halt Request */
+#define MTB_FLOW_AUTOHALT (0x1ul << MTB_FLOW_AUTOHALT_Pos)
+#define MTB_FLOW_WATERMARK_Pos 3 /**< \brief (MTB_FLOW) Watermark value */
+#define MTB_FLOW_WATERMARK_Msk (0x1FFFFFFFul << MTB_FLOW_WATERMARK_Pos)
+#define MTB_FLOW_WATERMARK(value) (MTB_FLOW_WATERMARK_Msk & ((value) << MTB_FLOW_WATERMARK_Pos))
+#define MTB_FLOW_MASK 0xFFFFFFFBul /**< \brief (MTB_FLOW) MASK Register */
+
+/* -------- MTB_BASE : (MTB Offset: 0x00C) (R/ 32) MTB Base -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} MTB_BASE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_BASE_OFFSET 0x00C /**< \brief (MTB_BASE offset) MTB Base */
+#define MTB_BASE_MASK 0xFFFFFFFFul /**< \brief (MTB_BASE) MASK Register */
+
+/* -------- MTB_ITCTRL : (MTB Offset: 0xF00) (R/W 32) MTB Integration Mode Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} MTB_ITCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_ITCTRL_OFFSET 0xF00 /**< \brief (MTB_ITCTRL offset) MTB Integration Mode Control */
+#define MTB_ITCTRL_MASK 0xFFFFFFFFul /**< \brief (MTB_ITCTRL) MASK Register */
+
+/* -------- MTB_CLAIMSET : (MTB Offset: 0xFA0) (R/W 32) MTB Claim Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} MTB_CLAIMSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_CLAIMSET_OFFSET 0xFA0 /**< \brief (MTB_CLAIMSET offset) MTB Claim Set */
+#define MTB_CLAIMSET_MASK 0xFFFFFFFFul /**< \brief (MTB_CLAIMSET) MASK Register */
+
+/* -------- MTB_CLAIMCLR : (MTB Offset: 0xFA4) (R/W 32) MTB Claim Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} MTB_CLAIMCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_CLAIMCLR_OFFSET 0xFA4 /**< \brief (MTB_CLAIMCLR offset) MTB Claim Clear */
+#define MTB_CLAIMCLR_MASK 0xFFFFFFFFul /**< \brief (MTB_CLAIMCLR) MASK Register */
+
+/* -------- MTB_LOCKACCESS : (MTB Offset: 0xFB0) (R/W 32) MTB Lock Access -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} MTB_LOCKACCESS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_LOCKACCESS_OFFSET 0xFB0 /**< \brief (MTB_LOCKACCESS offset) MTB Lock Access */
+#define MTB_LOCKACCESS_MASK 0xFFFFFFFFul /**< \brief (MTB_LOCKACCESS) MASK Register */
+
+/* -------- MTB_LOCKSTATUS : (MTB Offset: 0xFB4) (R/ 32) MTB Lock Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} MTB_LOCKSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_LOCKSTATUS_OFFSET 0xFB4 /**< \brief (MTB_LOCKSTATUS offset) MTB Lock Status */
+#define MTB_LOCKSTATUS_MASK 0xFFFFFFFFul /**< \brief (MTB_LOCKSTATUS) MASK Register */
+
+/* -------- MTB_AUTHSTATUS : (MTB Offset: 0xFB8) (R/ 32) MTB Authentication Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} MTB_AUTHSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_AUTHSTATUS_OFFSET 0xFB8 /**< \brief (MTB_AUTHSTATUS offset) MTB Authentication Status */
+#define MTB_AUTHSTATUS_MASK 0xFFFFFFFFul /**< \brief (MTB_AUTHSTATUS) MASK Register */
+
+/* -------- MTB_DEVARCH : (MTB Offset: 0xFBC) (R/ 32) MTB Device Architecture -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} MTB_DEVARCH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_DEVARCH_OFFSET 0xFBC /**< \brief (MTB_DEVARCH offset) MTB Device Architecture */
+#define MTB_DEVARCH_MASK 0xFFFFFFFFul /**< \brief (MTB_DEVARCH) MASK Register */
+
+/* -------- MTB_DEVID : (MTB Offset: 0xFC8) (R/ 32) MTB Device Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} MTB_DEVID_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_DEVID_OFFSET 0xFC8 /**< \brief (MTB_DEVID offset) MTB Device Configuration */
+#define MTB_DEVID_MASK 0xFFFFFFFFul /**< \brief (MTB_DEVID) MASK Register */
+
+/* -------- MTB_DEVTYPE : (MTB Offset: 0xFCC) (R/ 32) MTB Device Type -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} MTB_DEVTYPE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_DEVTYPE_OFFSET 0xFCC /**< \brief (MTB_DEVTYPE offset) MTB Device Type */
+#define MTB_DEVTYPE_MASK 0xFFFFFFFFul /**< \brief (MTB_DEVTYPE) MASK Register */
+
+/* -------- MTB_PID4 : (MTB Offset: 0xFD0) (R/ 32) CoreSight -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} MTB_PID4_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_PID4_OFFSET 0xFD0 /**< \brief (MTB_PID4 offset) CoreSight */
+#define MTB_PID4_MASK 0xFFFFFFFFul /**< \brief (MTB_PID4) MASK Register */
+
+/* -------- MTB_PID5 : (MTB Offset: 0xFD4) (R/ 32) CoreSight -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} MTB_PID5_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_PID5_OFFSET 0xFD4 /**< \brief (MTB_PID5 offset) CoreSight */
+#define MTB_PID5_MASK 0xFFFFFFFFul /**< \brief (MTB_PID5) MASK Register */
+
+/* -------- MTB_PID6 : (MTB Offset: 0xFD8) (R/ 32) CoreSight -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} MTB_PID6_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_PID6_OFFSET 0xFD8 /**< \brief (MTB_PID6 offset) CoreSight */
+#define MTB_PID6_MASK 0xFFFFFFFFul /**< \brief (MTB_PID6) MASK Register */
+
+/* -------- MTB_PID7 : (MTB Offset: 0xFDC) (R/ 32) CoreSight -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} MTB_PID7_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_PID7_OFFSET 0xFDC /**< \brief (MTB_PID7 offset) CoreSight */
+#define MTB_PID7_MASK 0xFFFFFFFFul /**< \brief (MTB_PID7) MASK Register */
+
+/* -------- MTB_PID0 : (MTB Offset: 0xFE0) (R/ 32) CoreSight -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} MTB_PID0_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_PID0_OFFSET 0xFE0 /**< \brief (MTB_PID0 offset) CoreSight */
+#define MTB_PID0_MASK 0xFFFFFFFFul /**< \brief (MTB_PID0) MASK Register */
+
+/* -------- MTB_PID1 : (MTB Offset: 0xFE4) (R/ 32) CoreSight -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} MTB_PID1_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_PID1_OFFSET 0xFE4 /**< \brief (MTB_PID1 offset) CoreSight */
+#define MTB_PID1_MASK 0xFFFFFFFFul /**< \brief (MTB_PID1) MASK Register */
+
+/* -------- MTB_PID2 : (MTB Offset: 0xFE8) (R/ 32) CoreSight -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} MTB_PID2_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_PID2_OFFSET 0xFE8 /**< \brief (MTB_PID2 offset) CoreSight */
+#define MTB_PID2_MASK 0xFFFFFFFFul /**< \brief (MTB_PID2) MASK Register */
+
+/* -------- MTB_PID3 : (MTB Offset: 0xFEC) (R/ 32) CoreSight -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} MTB_PID3_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_PID3_OFFSET 0xFEC /**< \brief (MTB_PID3 offset) CoreSight */
+#define MTB_PID3_MASK 0xFFFFFFFFul /**< \brief (MTB_PID3) MASK Register */
+
+/* -------- MTB_CID0 : (MTB Offset: 0xFF0) (R/ 32) CoreSight -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} MTB_CID0_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_CID0_OFFSET 0xFF0 /**< \brief (MTB_CID0 offset) CoreSight */
+#define MTB_CID0_MASK 0xFFFFFFFFul /**< \brief (MTB_CID0) MASK Register */
+
+/* -------- MTB_CID1 : (MTB Offset: 0xFF4) (R/ 32) CoreSight -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} MTB_CID1_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_CID1_OFFSET 0xFF4 /**< \brief (MTB_CID1 offset) CoreSight */
+#define MTB_CID1_MASK 0xFFFFFFFFul /**< \brief (MTB_CID1) MASK Register */
+
+/* -------- MTB_CID2 : (MTB Offset: 0xFF8) (R/ 32) CoreSight -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} MTB_CID2_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_CID2_OFFSET 0xFF8 /**< \brief (MTB_CID2 offset) CoreSight */
+#define MTB_CID2_MASK 0xFFFFFFFFul /**< \brief (MTB_CID2) MASK Register */
+
+/* -------- MTB_CID3 : (MTB Offset: 0xFFC) (R/ 32) CoreSight -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint32_t reg; /*!< Type used for register access */
+} MTB_CID3_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define MTB_CID3_OFFSET 0xFFC /**< \brief (MTB_CID3 offset) CoreSight */
+#define MTB_CID3_MASK 0xFFFFFFFFul /**< \brief (MTB_CID3) MASK Register */
+
+/** \brief MTB hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO MTB_POSITION_Type POSITION; /**< \brief Offset: 0x000 (R/W 32) MTB Position */
+ __IO MTB_MASTER_Type MASTER; /**< \brief Offset: 0x004 (R/W 32) MTB Master */
+ __IO MTB_FLOW_Type FLOW; /**< \brief Offset: 0x008 (R/W 32) MTB Flow */
+ __I MTB_BASE_Type BASE; /**< \brief Offset: 0x00C (R/ 32) MTB Base */
+ RoReg8 Reserved1[0xEF0];
+ __IO MTB_ITCTRL_Type ITCTRL; /**< \brief Offset: 0xF00 (R/W 32) MTB Integration Mode Control */
+ RoReg8 Reserved2[0x9C];
+ __IO MTB_CLAIMSET_Type CLAIMSET; /**< \brief Offset: 0xFA0 (R/W 32) MTB Claim Set */
+ __IO MTB_CLAIMCLR_Type CLAIMCLR; /**< \brief Offset: 0xFA4 (R/W 32) MTB Claim Clear */
+ RoReg8 Reserved3[0x8];
+ __IO MTB_LOCKACCESS_Type LOCKACCESS; /**< \brief Offset: 0xFB0 (R/W 32) MTB Lock Access */
+ __I MTB_LOCKSTATUS_Type LOCKSTATUS; /**< \brief Offset: 0xFB4 (R/ 32) MTB Lock Status */
+ __I MTB_AUTHSTATUS_Type AUTHSTATUS; /**< \brief Offset: 0xFB8 (R/ 32) MTB Authentication Status */
+ __I MTB_DEVARCH_Type DEVARCH; /**< \brief Offset: 0xFBC (R/ 32) MTB Device Architecture */
+ RoReg8 Reserved4[0x8];
+ __I MTB_DEVID_Type DEVID; /**< \brief Offset: 0xFC8 (R/ 32) MTB Device Configuration */
+ __I MTB_DEVTYPE_Type DEVTYPE; /**< \brief Offset: 0xFCC (R/ 32) MTB Device Type */
+ __I MTB_PID4_Type PID4; /**< \brief Offset: 0xFD0 (R/ 32) CoreSight */
+ __I MTB_PID5_Type PID5; /**< \brief Offset: 0xFD4 (R/ 32) CoreSight */
+ __I MTB_PID6_Type PID6; /**< \brief Offset: 0xFD8 (R/ 32) CoreSight */
+ __I MTB_PID7_Type PID7; /**< \brief Offset: 0xFDC (R/ 32) CoreSight */
+ __I MTB_PID0_Type PID0; /**< \brief Offset: 0xFE0 (R/ 32) CoreSight */
+ __I MTB_PID1_Type PID1; /**< \brief Offset: 0xFE4 (R/ 32) CoreSight */
+ __I MTB_PID2_Type PID2; /**< \brief Offset: 0xFE8 (R/ 32) CoreSight */
+ __I MTB_PID3_Type PID3; /**< \brief Offset: 0xFEC (R/ 32) CoreSight */
+ __I MTB_CID0_Type CID0; /**< \brief Offset: 0xFF0 (R/ 32) CoreSight */
+ __I MTB_CID1_Type CID1; /**< \brief Offset: 0xFF4 (R/ 32) CoreSight */
+ __I MTB_CID2_Type CID2; /**< \brief Offset: 0xFF8 (R/ 32) CoreSight */
+ __I MTB_CID3_Type CID3; /**< \brief Offset: 0xFFC (R/ 32) CoreSight */
+} Mtb;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_MTB_COMPONENT_ */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/component/nvmctrl.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/component/nvmctrl.h
new file mode 100644
index 0000000000000000000000000000000000000000..0d8e8fae9fdb95abc780f655061b12b6e024508a
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/component/nvmctrl.h
@@ -0,0 +1,542 @@
+/**
+ * \file
+ *
+ * \brief Component description for NVMCTRL
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_NVMCTRL_COMPONENT_
+#define _SAMD21_NVMCTRL_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR NVMCTRL */
+/* ========================================================================== */
+/** \addtogroup SAMD21_NVMCTRL Non-Volatile Memory Controller */
+/*@{*/
+
+#define NVMCTRL_U2207
+#define REV_NVMCTRL 0x106
+
+/* -------- NVMCTRL_CTRLA : (NVMCTRL Offset: 0x00) (R/W 16) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t CMD:7; /*!< bit: 0.. 6 Command */
+ uint16_t :1; /*!< bit: 7 Reserved */
+ uint16_t CMDEX:8; /*!< bit: 8..15 Command Execution */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} NVMCTRL_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_CTRLA_OFFSET 0x00 /**< \brief (NVMCTRL_CTRLA offset) Control A */
+#define NVMCTRL_CTRLA_RESETVALUE 0x0000ul /**< \brief (NVMCTRL_CTRLA reset_value) Control A */
+
+#define NVMCTRL_CTRLA_CMD_Pos 0 /**< \brief (NVMCTRL_CTRLA) Command */
+#define NVMCTRL_CTRLA_CMD_Msk (0x7Ful << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD(value) (NVMCTRL_CTRLA_CMD_Msk & ((value) << NVMCTRL_CTRLA_CMD_Pos))
+#define NVMCTRL_CTRLA_CMD_ER_Val 0x2ul /**< \brief (NVMCTRL_CTRLA) Erase Row - Erases the row addressed by the ADDR register. */
+#define NVMCTRL_CTRLA_CMD_WP_Val 0x4ul /**< \brief (NVMCTRL_CTRLA) Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. */
+#define NVMCTRL_CTRLA_CMD_EAR_Val 0x5ul /**< \brief (NVMCTRL_CTRLA) Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. */
+#define NVMCTRL_CTRLA_CMD_WAP_Val 0x6ul /**< \brief (NVMCTRL_CTRLA) Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. */
+#define NVMCTRL_CTRLA_CMD_SF_Val 0xAul /**< \brief (NVMCTRL_CTRLA) Security Flow Command */
+#define NVMCTRL_CTRLA_CMD_WL_Val 0xFul /**< \brief (NVMCTRL_CTRLA) Write lockbits */
+#define NVMCTRL_CTRLA_CMD_LR_Val 0x40ul /**< \brief (NVMCTRL_CTRLA) Lock Region - Locks the region containing the address location in the ADDR register. */
+#define NVMCTRL_CTRLA_CMD_UR_Val 0x41ul /**< \brief (NVMCTRL_CTRLA) Unlock Region - Unlocks the region containing the address location in the ADDR register. */
+#define NVMCTRL_CTRLA_CMD_SPRM_Val 0x42ul /**< \brief (NVMCTRL_CTRLA) Sets the power reduction mode. */
+#define NVMCTRL_CTRLA_CMD_CPRM_Val 0x43ul /**< \brief (NVMCTRL_CTRLA) Clears the power reduction mode. */
+#define NVMCTRL_CTRLA_CMD_PBC_Val 0x44ul /**< \brief (NVMCTRL_CTRLA) Page Buffer Clear - Clears the page buffer. */
+#define NVMCTRL_CTRLA_CMD_SSB_Val 0x45ul /**< \brief (NVMCTRL_CTRLA) Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row. */
+#define NVMCTRL_CTRLA_CMD_INVALL_Val 0x46ul /**< \brief (NVMCTRL_CTRLA) Invalidates all cache lines. */
+#define NVMCTRL_CTRLA_CMD_ER (NVMCTRL_CTRLA_CMD_ER_Val << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_WP (NVMCTRL_CTRLA_CMD_WP_Val << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_EAR (NVMCTRL_CTRLA_CMD_EAR_Val << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_WAP (NVMCTRL_CTRLA_CMD_WAP_Val << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_SF (NVMCTRL_CTRLA_CMD_SF_Val << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_WL (NVMCTRL_CTRLA_CMD_WL_Val << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_LR (NVMCTRL_CTRLA_CMD_LR_Val << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_UR (NVMCTRL_CTRLA_CMD_UR_Val << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_SPRM (NVMCTRL_CTRLA_CMD_SPRM_Val << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_CPRM (NVMCTRL_CTRLA_CMD_CPRM_Val << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_PBC (NVMCTRL_CTRLA_CMD_PBC_Val << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_SSB (NVMCTRL_CTRLA_CMD_SSB_Val << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMD_INVALL (NVMCTRL_CTRLA_CMD_INVALL_Val << NVMCTRL_CTRLA_CMD_Pos)
+#define NVMCTRL_CTRLA_CMDEX_Pos 8 /**< \brief (NVMCTRL_CTRLA) Command Execution */
+#define NVMCTRL_CTRLA_CMDEX_Msk (0xFFul << NVMCTRL_CTRLA_CMDEX_Pos)
+#define NVMCTRL_CTRLA_CMDEX(value) (NVMCTRL_CTRLA_CMDEX_Msk & ((value) << NVMCTRL_CTRLA_CMDEX_Pos))
+#define NVMCTRL_CTRLA_CMDEX_KEY_Val 0xA5ul /**< \brief (NVMCTRL_CTRLA) Execution Key */
+#define NVMCTRL_CTRLA_CMDEX_KEY (NVMCTRL_CTRLA_CMDEX_KEY_Val << NVMCTRL_CTRLA_CMDEX_Pos)
+#define NVMCTRL_CTRLA_MASK 0xFF7Ful /**< \brief (NVMCTRL_CTRLA) MASK Register */
+
+/* -------- NVMCTRL_CTRLB : (NVMCTRL Offset: 0x04) (R/W 32) Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :1; /*!< bit: 0 Reserved */
+ uint32_t RWS:4; /*!< bit: 1.. 4 NVM Read Wait States */
+ uint32_t :2; /*!< bit: 5.. 6 Reserved */
+ uint32_t MANW:1; /*!< bit: 7 Manual Write */
+ uint32_t SLEEPPRM:2; /*!< bit: 8.. 9 Power Reduction Mode during Sleep */
+ uint32_t :6; /*!< bit: 10..15 Reserved */
+ uint32_t READMODE:2; /*!< bit: 16..17 NVMCTRL Read Mode */
+ uint32_t CACHEDIS:1; /*!< bit: 18 Cache Disable */
+ uint32_t :13; /*!< bit: 19..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} NVMCTRL_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_CTRLB_OFFSET 0x04 /**< \brief (NVMCTRL_CTRLB offset) Control B */
+#define NVMCTRL_CTRLB_RESETVALUE 0x00000000ul /**< \brief (NVMCTRL_CTRLB reset_value) Control B */
+
+#define NVMCTRL_CTRLB_RWS_Pos 1 /**< \brief (NVMCTRL_CTRLB) NVM Read Wait States */
+#define NVMCTRL_CTRLB_RWS_Msk (0xFul << NVMCTRL_CTRLB_RWS_Pos)
+#define NVMCTRL_CTRLB_RWS(value) (NVMCTRL_CTRLB_RWS_Msk & ((value) << NVMCTRL_CTRLB_RWS_Pos))
+#define NVMCTRL_CTRLB_RWS_SINGLE_Val 0x0ul /**< \brief (NVMCTRL_CTRLB) Single Auto Wait State */
+#define NVMCTRL_CTRLB_RWS_HALF_Val 0x1ul /**< \brief (NVMCTRL_CTRLB) Half Auto Wait State */
+#define NVMCTRL_CTRLB_RWS_DUAL_Val 0x2ul /**< \brief (NVMCTRL_CTRLB) Dual Auto Wait State */
+#define NVMCTRL_CTRLB_RWS_SINGLE (NVMCTRL_CTRLB_RWS_SINGLE_Val << NVMCTRL_CTRLB_RWS_Pos)
+#define NVMCTRL_CTRLB_RWS_HALF (NVMCTRL_CTRLB_RWS_HALF_Val << NVMCTRL_CTRLB_RWS_Pos)
+#define NVMCTRL_CTRLB_RWS_DUAL (NVMCTRL_CTRLB_RWS_DUAL_Val << NVMCTRL_CTRLB_RWS_Pos)
+#define NVMCTRL_CTRLB_MANW_Pos 7 /**< \brief (NVMCTRL_CTRLB) Manual Write */
+#define NVMCTRL_CTRLB_MANW (0x1ul << NVMCTRL_CTRLB_MANW_Pos)
+#define NVMCTRL_CTRLB_SLEEPPRM_Pos 8 /**< \brief (NVMCTRL_CTRLB) Power Reduction Mode during Sleep */
+#define NVMCTRL_CTRLB_SLEEPPRM_Msk (0x3ul << NVMCTRL_CTRLB_SLEEPPRM_Pos)
+#define NVMCTRL_CTRLB_SLEEPPRM(value) (NVMCTRL_CTRLB_SLEEPPRM_Msk & ((value) << NVMCTRL_CTRLB_SLEEPPRM_Pos))
+#define NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS_Val 0x0ul /**< \brief (NVMCTRL_CTRLB) NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access. */
+#define NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT_Val 0x1ul /**< \brief (NVMCTRL_CTRLB) NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep. */
+#define NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val 0x3ul /**< \brief (NVMCTRL_CTRLB) Auto power reduction disabled. */
+#define NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS (NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS_Val << NVMCTRL_CTRLB_SLEEPPRM_Pos)
+#define NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT (NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT_Val << NVMCTRL_CTRLB_SLEEPPRM_Pos)
+#define NVMCTRL_CTRLB_SLEEPPRM_DISABLED (NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val << NVMCTRL_CTRLB_SLEEPPRM_Pos)
+#define NVMCTRL_CTRLB_READMODE_Pos 16 /**< \brief (NVMCTRL_CTRLB) NVMCTRL Read Mode */
+#define NVMCTRL_CTRLB_READMODE_Msk (0x3ul << NVMCTRL_CTRLB_READMODE_Pos)
+#define NVMCTRL_CTRLB_READMODE(value) (NVMCTRL_CTRLB_READMODE_Msk & ((value) << NVMCTRL_CTRLB_READMODE_Pos))
+#define NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY_Val 0x0ul /**< \brief (NVMCTRL_CTRLB) The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance. */
+#define NVMCTRL_CTRLB_READMODE_LOW_POWER_Val 0x1ul /**< \brief (NVMCTRL_CTRLB) Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time. */
+#define NVMCTRL_CTRLB_READMODE_DETERMINISTIC_Val 0x2ul /**< \brief (NVMCTRL_CTRLB) The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings. */
+#define NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY (NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY_Val << NVMCTRL_CTRLB_READMODE_Pos)
+#define NVMCTRL_CTRLB_READMODE_LOW_POWER (NVMCTRL_CTRLB_READMODE_LOW_POWER_Val << NVMCTRL_CTRLB_READMODE_Pos)
+#define NVMCTRL_CTRLB_READMODE_DETERMINISTIC (NVMCTRL_CTRLB_READMODE_DETERMINISTIC_Val << NVMCTRL_CTRLB_READMODE_Pos)
+#define NVMCTRL_CTRLB_CACHEDIS_Pos 18 /**< \brief (NVMCTRL_CTRLB) Cache Disable */
+#define NVMCTRL_CTRLB_CACHEDIS (0x1ul << NVMCTRL_CTRLB_CACHEDIS_Pos)
+#define NVMCTRL_CTRLB_MASK 0x0007039Eul /**< \brief (NVMCTRL_CTRLB) MASK Register */
+
+/* -------- NVMCTRL_PARAM : (NVMCTRL Offset: 0x08) (R/W 32) NVM Parameter -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t NVMP:16; /*!< bit: 0..15 NVM Pages */
+ uint32_t PSZ:3; /*!< bit: 16..18 Page Size */
+ uint32_t :13; /*!< bit: 19..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} NVMCTRL_PARAM_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_PARAM_OFFSET 0x08 /**< \brief (NVMCTRL_PARAM offset) NVM Parameter */
+#define NVMCTRL_PARAM_RESETVALUE 0x00000000ul /**< \brief (NVMCTRL_PARAM reset_value) NVM Parameter */
+
+#define NVMCTRL_PARAM_NVMP_Pos 0 /**< \brief (NVMCTRL_PARAM) NVM Pages */
+#define NVMCTRL_PARAM_NVMP_Msk (0xFFFFul << NVMCTRL_PARAM_NVMP_Pos)
+#define NVMCTRL_PARAM_NVMP(value) (NVMCTRL_PARAM_NVMP_Msk & ((value) << NVMCTRL_PARAM_NVMP_Pos))
+#define NVMCTRL_PARAM_PSZ_Pos 16 /**< \brief (NVMCTRL_PARAM) Page Size */
+#define NVMCTRL_PARAM_PSZ_Msk (0x7ul << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ(value) (NVMCTRL_PARAM_PSZ_Msk & ((value) << NVMCTRL_PARAM_PSZ_Pos))
+#define NVMCTRL_PARAM_PSZ_8_Val 0x0ul /**< \brief (NVMCTRL_PARAM) 8 bytes */
+#define NVMCTRL_PARAM_PSZ_16_Val 0x1ul /**< \brief (NVMCTRL_PARAM) 16 bytes */
+#define NVMCTRL_PARAM_PSZ_32_Val 0x2ul /**< \brief (NVMCTRL_PARAM) 32 bytes */
+#define NVMCTRL_PARAM_PSZ_64_Val 0x3ul /**< \brief (NVMCTRL_PARAM) 64 bytes */
+#define NVMCTRL_PARAM_PSZ_128_Val 0x4ul /**< \brief (NVMCTRL_PARAM) 128 bytes */
+#define NVMCTRL_PARAM_PSZ_256_Val 0x5ul /**< \brief (NVMCTRL_PARAM) 256 bytes */
+#define NVMCTRL_PARAM_PSZ_512_Val 0x6ul /**< \brief (NVMCTRL_PARAM) 512 bytes */
+#define NVMCTRL_PARAM_PSZ_1024_Val 0x7ul /**< \brief (NVMCTRL_PARAM) 1024 bytes */
+#define NVMCTRL_PARAM_PSZ_8 (NVMCTRL_PARAM_PSZ_8_Val << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ_16 (NVMCTRL_PARAM_PSZ_16_Val << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ_32 (NVMCTRL_PARAM_PSZ_32_Val << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ_64 (NVMCTRL_PARAM_PSZ_64_Val << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ_128 (NVMCTRL_PARAM_PSZ_128_Val << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ_256 (NVMCTRL_PARAM_PSZ_256_Val << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ_512 (NVMCTRL_PARAM_PSZ_512_Val << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_PSZ_1024 (NVMCTRL_PARAM_PSZ_1024_Val << NVMCTRL_PARAM_PSZ_Pos)
+#define NVMCTRL_PARAM_MASK 0x0007FFFFul /**< \brief (NVMCTRL_PARAM) MASK Register */
+
+/* -------- NVMCTRL_INTENCLR : (NVMCTRL Offset: 0x0C) (R/W 8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t READY:1; /*!< bit: 0 NVM Ready Interrupt Enable */
+ uint8_t ERROR:1; /*!< bit: 1 Error Interrupt Enable */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} NVMCTRL_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_INTENCLR_OFFSET 0x0C /**< \brief (NVMCTRL_INTENCLR offset) Interrupt Enable Clear */
+#define NVMCTRL_INTENCLR_RESETVALUE 0x00ul /**< \brief (NVMCTRL_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define NVMCTRL_INTENCLR_READY_Pos 0 /**< \brief (NVMCTRL_INTENCLR) NVM Ready Interrupt Enable */
+#define NVMCTRL_INTENCLR_READY (0x1ul << NVMCTRL_INTENCLR_READY_Pos)
+#define NVMCTRL_INTENCLR_ERROR_Pos 1 /**< \brief (NVMCTRL_INTENCLR) Error Interrupt Enable */
+#define NVMCTRL_INTENCLR_ERROR (0x1ul << NVMCTRL_INTENCLR_ERROR_Pos)
+#define NVMCTRL_INTENCLR_MASK 0x03ul /**< \brief (NVMCTRL_INTENCLR) MASK Register */
+
+/* -------- NVMCTRL_INTENSET : (NVMCTRL Offset: 0x10) (R/W 8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t READY:1; /*!< bit: 0 NVM Ready Interrupt Enable */
+ uint8_t ERROR:1; /*!< bit: 1 Error Interrupt Enable */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} NVMCTRL_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_INTENSET_OFFSET 0x10 /**< \brief (NVMCTRL_INTENSET offset) Interrupt Enable Set */
+#define NVMCTRL_INTENSET_RESETVALUE 0x00ul /**< \brief (NVMCTRL_INTENSET reset_value) Interrupt Enable Set */
+
+#define NVMCTRL_INTENSET_READY_Pos 0 /**< \brief (NVMCTRL_INTENSET) NVM Ready Interrupt Enable */
+#define NVMCTRL_INTENSET_READY (0x1ul << NVMCTRL_INTENSET_READY_Pos)
+#define NVMCTRL_INTENSET_ERROR_Pos 1 /**< \brief (NVMCTRL_INTENSET) Error Interrupt Enable */
+#define NVMCTRL_INTENSET_ERROR (0x1ul << NVMCTRL_INTENSET_ERROR_Pos)
+#define NVMCTRL_INTENSET_MASK 0x03ul /**< \brief (NVMCTRL_INTENSET) MASK Register */
+
+/* -------- NVMCTRL_INTFLAG : (NVMCTRL Offset: 0x14) (R/W 8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint8_t READY:1; /*!< bit: 0 NVM Ready */
+ __I uint8_t ERROR:1; /*!< bit: 1 Error */
+ __I uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} NVMCTRL_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_INTFLAG_OFFSET 0x14 /**< \brief (NVMCTRL_INTFLAG offset) Interrupt Flag Status and Clear */
+#define NVMCTRL_INTFLAG_RESETVALUE 0x00ul /**< \brief (NVMCTRL_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define NVMCTRL_INTFLAG_READY_Pos 0 /**< \brief (NVMCTRL_INTFLAG) NVM Ready */
+#define NVMCTRL_INTFLAG_READY (0x1ul << NVMCTRL_INTFLAG_READY_Pos)
+#define NVMCTRL_INTFLAG_ERROR_Pos 1 /**< \brief (NVMCTRL_INTFLAG) Error */
+#define NVMCTRL_INTFLAG_ERROR (0x1ul << NVMCTRL_INTFLAG_ERROR_Pos)
+#define NVMCTRL_INTFLAG_MASK 0x03ul /**< \brief (NVMCTRL_INTFLAG) MASK Register */
+
+/* -------- NVMCTRL_STATUS : (NVMCTRL Offset: 0x18) (R/W 16) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t PRM:1; /*!< bit: 0 Power Reduction Mode */
+ uint16_t LOAD:1; /*!< bit: 1 NVM Page Buffer Active Loading */
+ uint16_t PROGE:1; /*!< bit: 2 Programming Error Status */
+ uint16_t LOCKE:1; /*!< bit: 3 Lock Error Status */
+ uint16_t NVME:1; /*!< bit: 4 NVM Error */
+ uint16_t :3; /*!< bit: 5.. 7 Reserved */
+ uint16_t SB:1; /*!< bit: 8 Security Bit Status */
+ uint16_t :7; /*!< bit: 9..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} NVMCTRL_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_STATUS_OFFSET 0x18 /**< \brief (NVMCTRL_STATUS offset) Status */
+#define NVMCTRL_STATUS_RESETVALUE 0x0000ul /**< \brief (NVMCTRL_STATUS reset_value) Status */
+
+#define NVMCTRL_STATUS_PRM_Pos 0 /**< \brief (NVMCTRL_STATUS) Power Reduction Mode */
+#define NVMCTRL_STATUS_PRM (0x1ul << NVMCTRL_STATUS_PRM_Pos)
+#define NVMCTRL_STATUS_LOAD_Pos 1 /**< \brief (NVMCTRL_STATUS) NVM Page Buffer Active Loading */
+#define NVMCTRL_STATUS_LOAD (0x1ul << NVMCTRL_STATUS_LOAD_Pos)
+#define NVMCTRL_STATUS_PROGE_Pos 2 /**< \brief (NVMCTRL_STATUS) Programming Error Status */
+#define NVMCTRL_STATUS_PROGE (0x1ul << NVMCTRL_STATUS_PROGE_Pos)
+#define NVMCTRL_STATUS_LOCKE_Pos 3 /**< \brief (NVMCTRL_STATUS) Lock Error Status */
+#define NVMCTRL_STATUS_LOCKE (0x1ul << NVMCTRL_STATUS_LOCKE_Pos)
+#define NVMCTRL_STATUS_NVME_Pos 4 /**< \brief (NVMCTRL_STATUS) NVM Error */
+#define NVMCTRL_STATUS_NVME (0x1ul << NVMCTRL_STATUS_NVME_Pos)
+#define NVMCTRL_STATUS_SB_Pos 8 /**< \brief (NVMCTRL_STATUS) Security Bit Status */
+#define NVMCTRL_STATUS_SB (0x1ul << NVMCTRL_STATUS_SB_Pos)
+#define NVMCTRL_STATUS_MASK 0x011Ful /**< \brief (NVMCTRL_STATUS) MASK Register */
+
+/* -------- NVMCTRL_ADDR : (NVMCTRL Offset: 0x1C) (R/W 32) Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ADDR:22; /*!< bit: 0..21 NVM Address */
+ uint32_t :10; /*!< bit: 22..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} NVMCTRL_ADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_ADDR_OFFSET 0x1C /**< \brief (NVMCTRL_ADDR offset) Address */
+#define NVMCTRL_ADDR_RESETVALUE 0x00000000ul /**< \brief (NVMCTRL_ADDR reset_value) Address */
+
+#define NVMCTRL_ADDR_ADDR_Pos 0 /**< \brief (NVMCTRL_ADDR) NVM Address */
+#define NVMCTRL_ADDR_ADDR_Msk (0x3FFFFFul << NVMCTRL_ADDR_ADDR_Pos)
+#define NVMCTRL_ADDR_ADDR(value) (NVMCTRL_ADDR_ADDR_Msk & ((value) << NVMCTRL_ADDR_ADDR_Pos))
+#define NVMCTRL_ADDR_MASK 0x003FFFFFul /**< \brief (NVMCTRL_ADDR) MASK Register */
+
+/* -------- NVMCTRL_LOCK : (NVMCTRL Offset: 0x20) (R/W 16) Lock Section -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t LOCK:16; /*!< bit: 0..15 Region Lock Bits */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} NVMCTRL_LOCK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define NVMCTRL_LOCK_OFFSET 0x20 /**< \brief (NVMCTRL_LOCK offset) Lock Section */
+
+#define NVMCTRL_LOCK_LOCK_Pos 0 /**< \brief (NVMCTRL_LOCK) Region Lock Bits */
+#define NVMCTRL_LOCK_LOCK_Msk (0xFFFFul << NVMCTRL_LOCK_LOCK_Pos)
+#define NVMCTRL_LOCK_LOCK(value) (NVMCTRL_LOCK_LOCK_Msk & ((value) << NVMCTRL_LOCK_LOCK_Pos))
+#define NVMCTRL_LOCK_MASK 0xFFFFul /**< \brief (NVMCTRL_LOCK) MASK Register */
+
+/** \brief NVMCTRL APB hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO NVMCTRL_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
+ RoReg8 Reserved1[0x2];
+ __IO NVMCTRL_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) Control B */
+ __IO NVMCTRL_PARAM_Type PARAM; /**< \brief Offset: 0x08 (R/W 32) NVM Parameter */
+ __IO NVMCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
+ RoReg8 Reserved2[0x3];
+ __IO NVMCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x10 (R/W 8) Interrupt Enable Set */
+ RoReg8 Reserved3[0x3];
+ __IO NVMCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x14 (R/W 8) Interrupt Flag Status and Clear */
+ RoReg8 Reserved4[0x3];
+ __IO NVMCTRL_STATUS_Type STATUS; /**< \brief Offset: 0x18 (R/W 16) Status */
+ RoReg8 Reserved5[0x2];
+ __IO NVMCTRL_ADDR_Type ADDR; /**< \brief Offset: 0x1C (R/W 32) Address */
+ __IO NVMCTRL_LOCK_Type LOCK; /**< \brief Offset: 0x20 (R/W 16) Lock Section */
+} Nvmctrl;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SECTION_NVMCTRL_CAL
+
+#define SECTION_NVMCTRL_LOCKBIT
+
+#define SECTION_NVMCTRL_OTP1
+
+#define SECTION_NVMCTRL_OTP2
+
+#define SECTION_NVMCTRL_OTP4
+
+#define SECTION_NVMCTRL_TEMP_LOG
+
+#define SECTION_NVMCTRL_USER
+
+/*@}*/
+
+/* ************************************************************************** */
+/** SOFTWARE PERIPHERAL API DEFINITION FOR NON-VOLATILE FUSES */
+/* ************************************************************************** */
+/** \addtogroup fuses_api Peripheral Software API */
+/*@{*/
+
+
+#define ADC_FUSES_BIASCAL_ADDR (NVMCTRL_OTP4 + 4)
+#define ADC_FUSES_BIASCAL_Pos 3 /**< \brief (NVMCTRL_OTP4) ADC Bias Calibration */
+#define ADC_FUSES_BIASCAL_Msk (0x7ul << ADC_FUSES_BIASCAL_Pos)
+#define ADC_FUSES_BIASCAL(value) (ADC_FUSES_BIASCAL_Msk & ((value) << ADC_FUSES_BIASCAL_Pos))
+
+#define ADC_FUSES_LINEARITY_0_ADDR NVMCTRL_OTP4
+#define ADC_FUSES_LINEARITY_0_Pos 27 /**< \brief (NVMCTRL_OTP4) ADC Linearity bits 4:0 */
+#define ADC_FUSES_LINEARITY_0_Msk (0x1Ful << ADC_FUSES_LINEARITY_0_Pos)
+#define ADC_FUSES_LINEARITY_0(value) (ADC_FUSES_LINEARITY_0_Msk & ((value) << ADC_FUSES_LINEARITY_0_Pos))
+
+#define ADC_FUSES_LINEARITY_1_ADDR (NVMCTRL_OTP4 + 4)
+#define ADC_FUSES_LINEARITY_1_Pos 0 /**< \brief (NVMCTRL_OTP4) ADC Linearity bits 7:5 */
+#define ADC_FUSES_LINEARITY_1_Msk (0x7ul << ADC_FUSES_LINEARITY_1_Pos)
+#define ADC_FUSES_LINEARITY_1(value) (ADC_FUSES_LINEARITY_1_Msk & ((value) << ADC_FUSES_LINEARITY_1_Pos))
+
+#define FUSES_BOD33USERLEVEL_ADDR NVMCTRL_USER
+#define FUSES_BOD33USERLEVEL_Pos 8 /**< \brief (NVMCTRL_USER) BOD33 User Level */
+#define FUSES_BOD33USERLEVEL_Msk (0x3Ful << FUSES_BOD33USERLEVEL_Pos)
+#define FUSES_BOD33USERLEVEL(value) (FUSES_BOD33USERLEVEL_Msk & ((value) << FUSES_BOD33USERLEVEL_Pos))
+
+#define FUSES_BOD33_ACTION_ADDR NVMCTRL_USER
+#define FUSES_BOD33_ACTION_Pos 15 /**< \brief (NVMCTRL_USER) BOD33 Action */
+#define FUSES_BOD33_ACTION_Msk (0x3ul << FUSES_BOD33_ACTION_Pos)
+#define FUSES_BOD33_ACTION(value) (FUSES_BOD33_ACTION_Msk & ((value) << FUSES_BOD33_ACTION_Pos))
+
+#define FUSES_BOD33_EN_ADDR NVMCTRL_USER
+#define FUSES_BOD33_EN_Pos 14 /**< \brief (NVMCTRL_USER) BOD33 Enable */
+#define FUSES_BOD33_EN_Msk (0x1ul << FUSES_BOD33_EN_Pos)
+
+#define FUSES_BOD33_HYST_ADDR (NVMCTRL_USER + 4)
+#define FUSES_BOD33_HYST_Pos 8 /**< \brief (NVMCTRL_USER) BOD33 Hysteresis */
+#define FUSES_BOD33_HYST_Msk (0x1ul << FUSES_BOD33_HYST_Pos)
+
+#define FUSES_DFLL48M_COARSE_CAL_ADDR (NVMCTRL_OTP4 + 4)
+#define FUSES_DFLL48M_COARSE_CAL_Pos 26 /**< \brief (NVMCTRL_OTP4) DFLL48M Coarse Calibration */
+#define FUSES_DFLL48M_COARSE_CAL_Msk (0x3Ful << FUSES_DFLL48M_COARSE_CAL_Pos)
+#define FUSES_DFLL48M_COARSE_CAL(value) (FUSES_DFLL48M_COARSE_CAL_Msk & ((value) << FUSES_DFLL48M_COARSE_CAL_Pos))
+
+#define FUSES_DFLL48M_FINE_CAL_ADDR (NVMCTRL_OTP4 + 8)
+#define FUSES_DFLL48M_FINE_CAL_Pos 0 /**< \brief (NVMCTRL_OTP4) DFLL48M Fine Calibration */
+#define FUSES_DFLL48M_FINE_CAL_Msk (0x3FFul << FUSES_DFLL48M_FINE_CAL_Pos)
+#define FUSES_DFLL48M_FINE_CAL(value) (FUSES_DFLL48M_FINE_CAL_Msk & ((value) << FUSES_DFLL48M_FINE_CAL_Pos))
+
+#define FUSES_HOT_ADC_VAL_ADDR (NVMCTRL_TEMP_LOG + 4)
+#define FUSES_HOT_ADC_VAL_Pos 20 /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at hot temperature */
+#define FUSES_HOT_ADC_VAL_Msk (0xFFFul << FUSES_HOT_ADC_VAL_Pos)
+#define FUSES_HOT_ADC_VAL(value) (FUSES_HOT_ADC_VAL_Msk & ((value) << FUSES_HOT_ADC_VAL_Pos))
+
+#define FUSES_HOT_INT1V_VAL_ADDR (NVMCTRL_TEMP_LOG + 4)
+#define FUSES_HOT_INT1V_VAL_Pos 0 /**< \brief (NVMCTRL_TEMP_LOG) 2's complement of the internal 1V reference drift at hot temperature (versus a 1.0 centered value) */
+#define FUSES_HOT_INT1V_VAL_Msk (0xFFul << FUSES_HOT_INT1V_VAL_Pos)
+#define FUSES_HOT_INT1V_VAL(value) (FUSES_HOT_INT1V_VAL_Msk & ((value) << FUSES_HOT_INT1V_VAL_Pos))
+
+#define FUSES_HOT_TEMP_VAL_DEC_ADDR NVMCTRL_TEMP_LOG
+#define FUSES_HOT_TEMP_VAL_DEC_Pos 20 /**< \brief (NVMCTRL_TEMP_LOG) Decimal part of hot temperature */
+#define FUSES_HOT_TEMP_VAL_DEC_Msk (0xFul << FUSES_HOT_TEMP_VAL_DEC_Pos)
+#define FUSES_HOT_TEMP_VAL_DEC(value) (FUSES_HOT_TEMP_VAL_DEC_Msk & ((value) << FUSES_HOT_TEMP_VAL_DEC_Pos))
+
+#define FUSES_HOT_TEMP_VAL_INT_ADDR NVMCTRL_TEMP_LOG
+#define FUSES_HOT_TEMP_VAL_INT_Pos 12 /**< \brief (NVMCTRL_TEMP_LOG) Integer part of hot temperature in oC */
+#define FUSES_HOT_TEMP_VAL_INT_Msk (0xFFul << FUSES_HOT_TEMP_VAL_INT_Pos)
+#define FUSES_HOT_TEMP_VAL_INT(value) (FUSES_HOT_TEMP_VAL_INT_Msk & ((value) << FUSES_HOT_TEMP_VAL_INT_Pos))
+
+#define FUSES_OSC32K_CAL_ADDR (NVMCTRL_OTP4 + 4)
+#define FUSES_OSC32K_CAL_Pos 6 /**< \brief (NVMCTRL_OTP4) OSC32K Calibration */
+#define FUSES_OSC32K_CAL_Msk (0x7Ful << FUSES_OSC32K_CAL_Pos)
+#define FUSES_OSC32K_CAL(value) (FUSES_OSC32K_CAL_Msk & ((value) << FUSES_OSC32K_CAL_Pos))
+
+#define FUSES_ROOM_ADC_VAL_ADDR (NVMCTRL_TEMP_LOG + 4)
+#define FUSES_ROOM_ADC_VAL_Pos 8 /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at room temperature */
+#define FUSES_ROOM_ADC_VAL_Msk (0xFFFul << FUSES_ROOM_ADC_VAL_Pos)
+#define FUSES_ROOM_ADC_VAL(value) (FUSES_ROOM_ADC_VAL_Msk & ((value) << FUSES_ROOM_ADC_VAL_Pos))
+
+#define FUSES_ROOM_INT1V_VAL_ADDR NVMCTRL_TEMP_LOG
+#define FUSES_ROOM_INT1V_VAL_Pos 24 /**< \brief (NVMCTRL_TEMP_LOG) 2's complement of the internal 1V reference drift at room temperature (versus a 1.0 centered value) */
+#define FUSES_ROOM_INT1V_VAL_Msk (0xFFul << FUSES_ROOM_INT1V_VAL_Pos)
+#define FUSES_ROOM_INT1V_VAL(value) (FUSES_ROOM_INT1V_VAL_Msk & ((value) << FUSES_ROOM_INT1V_VAL_Pos))
+
+#define FUSES_ROOM_TEMP_VAL_DEC_ADDR NVMCTRL_TEMP_LOG
+#define FUSES_ROOM_TEMP_VAL_DEC_Pos 8 /**< \brief (NVMCTRL_TEMP_LOG) Decimal part of room temperature */
+#define FUSES_ROOM_TEMP_VAL_DEC_Msk (0xFul << FUSES_ROOM_TEMP_VAL_DEC_Pos)
+#define FUSES_ROOM_TEMP_VAL_DEC(value) (FUSES_ROOM_TEMP_VAL_DEC_Msk & ((value) << FUSES_ROOM_TEMP_VAL_DEC_Pos))
+
+#define FUSES_ROOM_TEMP_VAL_INT_ADDR NVMCTRL_TEMP_LOG
+#define FUSES_ROOM_TEMP_VAL_INT_Pos 0 /**< \brief (NVMCTRL_TEMP_LOG) Integer part of room temperature in oC */
+#define FUSES_ROOM_TEMP_VAL_INT_Msk (0xFFul << FUSES_ROOM_TEMP_VAL_INT_Pos)
+#define FUSES_ROOM_TEMP_VAL_INT(value) (FUSES_ROOM_TEMP_VAL_INT_Msk & ((value) << FUSES_ROOM_TEMP_VAL_INT_Pos))
+
+#define NVMCTRL_FUSES_BOOTPROT_ADDR NVMCTRL_USER
+#define NVMCTRL_FUSES_BOOTPROT_Pos 0 /**< \brief (NVMCTRL_USER) Bootloader Size */
+#define NVMCTRL_FUSES_BOOTPROT_Msk (0x7ul << NVMCTRL_FUSES_BOOTPROT_Pos)
+#define NVMCTRL_FUSES_BOOTPROT(value) (NVMCTRL_FUSES_BOOTPROT_Msk & ((value) << NVMCTRL_FUSES_BOOTPROT_Pos))
+
+#define NVMCTRL_FUSES_EEPROM_SIZE_ADDR NVMCTRL_USER
+#define NVMCTRL_FUSES_EEPROM_SIZE_Pos 4 /**< \brief (NVMCTRL_USER) EEPROM Size */
+#define NVMCTRL_FUSES_EEPROM_SIZE_Msk (0x7ul << NVMCTRL_FUSES_EEPROM_SIZE_Pos)
+#define NVMCTRL_FUSES_EEPROM_SIZE(value) (NVMCTRL_FUSES_EEPROM_SIZE_Msk & ((value) << NVMCTRL_FUSES_EEPROM_SIZE_Pos))
+
+#define NVMCTRL_FUSES_NVMP_ADDR NVMCTRL_OTP1
+#define NVMCTRL_FUSES_NVMP_Pos 16 /**< \brief (NVMCTRL_OTP1) Number of NVM Pages */
+#define NVMCTRL_FUSES_NVMP_Msk (0xFFFFul << NVMCTRL_FUSES_NVMP_Pos)
+#define NVMCTRL_FUSES_NVMP(value) (NVMCTRL_FUSES_NVMP_Msk & ((value) << NVMCTRL_FUSES_NVMP_Pos))
+
+#define NVMCTRL_FUSES_NVM_LOCK_ADDR NVMCTRL_OTP1
+#define NVMCTRL_FUSES_NVM_LOCK_Pos 0 /**< \brief (NVMCTRL_OTP1) NVM Lock */
+#define NVMCTRL_FUSES_NVM_LOCK_Msk (0xFFul << NVMCTRL_FUSES_NVM_LOCK_Pos)
+#define NVMCTRL_FUSES_NVM_LOCK(value) (NVMCTRL_FUSES_NVM_LOCK_Msk & ((value) << NVMCTRL_FUSES_NVM_LOCK_Pos))
+
+#define NVMCTRL_FUSES_PSZ_ADDR NVMCTRL_OTP1
+#define NVMCTRL_FUSES_PSZ_Pos 8 /**< \brief (NVMCTRL_OTP1) NVM Page Size */
+#define NVMCTRL_FUSES_PSZ_Msk (0xFul << NVMCTRL_FUSES_PSZ_Pos)
+#define NVMCTRL_FUSES_PSZ(value) (NVMCTRL_FUSES_PSZ_Msk & ((value) << NVMCTRL_FUSES_PSZ_Pos))
+
+#define NVMCTRL_FUSES_REGION_LOCKS_ADDR (NVMCTRL_USER + 4)
+#define NVMCTRL_FUSES_REGION_LOCKS_Pos 16 /**< \brief (NVMCTRL_USER) NVM Region Locks */
+#define NVMCTRL_FUSES_REGION_LOCKS_Msk (0xFFFFul << NVMCTRL_FUSES_REGION_LOCKS_Pos)
+#define NVMCTRL_FUSES_REGION_LOCKS(value) (NVMCTRL_FUSES_REGION_LOCKS_Msk & ((value) << NVMCTRL_FUSES_REGION_LOCKS_Pos))
+
+#define USB_FUSES_TRANSN_ADDR (NVMCTRL_OTP4 + 4)
+#define USB_FUSES_TRANSN_Pos 13 /**< \brief (NVMCTRL_OTP4) USB pad Transn calibration */
+#define USB_FUSES_TRANSN_Msk (0x1Ful << USB_FUSES_TRANSN_Pos)
+#define USB_FUSES_TRANSN(value) (USB_FUSES_TRANSN_Msk & ((value) << USB_FUSES_TRANSN_Pos))
+
+#define USB_FUSES_TRANSP_ADDR (NVMCTRL_OTP4 + 4)
+#define USB_FUSES_TRANSP_Pos 18 /**< \brief (NVMCTRL_OTP4) USB pad Transp calibration */
+#define USB_FUSES_TRANSP_Msk (0x1Ful << USB_FUSES_TRANSP_Pos)
+#define USB_FUSES_TRANSP(value) (USB_FUSES_TRANSP_Msk & ((value) << USB_FUSES_TRANSP_Pos))
+
+#define USB_FUSES_TRIM_ADDR (NVMCTRL_OTP4 + 4)
+#define USB_FUSES_TRIM_Pos 23 /**< \brief (NVMCTRL_OTP4) USB pad Trim calibration */
+#define USB_FUSES_TRIM_Msk (0x7ul << USB_FUSES_TRIM_Pos)
+#define USB_FUSES_TRIM(value) (USB_FUSES_TRIM_Msk & ((value) << USB_FUSES_TRIM_Pos))
+
+#define WDT_FUSES_ALWAYSON_ADDR NVMCTRL_USER
+#define WDT_FUSES_ALWAYSON_Pos 26 /**< \brief (NVMCTRL_USER) WDT Always On */
+#define WDT_FUSES_ALWAYSON_Msk (0x1ul << WDT_FUSES_ALWAYSON_Pos)
+
+#define WDT_FUSES_ENABLE_ADDR NVMCTRL_USER
+#define WDT_FUSES_ENABLE_Pos 25 /**< \brief (NVMCTRL_USER) WDT Enable */
+#define WDT_FUSES_ENABLE_Msk (0x1ul << WDT_FUSES_ENABLE_Pos)
+
+#define WDT_FUSES_EWOFFSET_ADDR (NVMCTRL_USER + 4)
+#define WDT_FUSES_EWOFFSET_Pos 3 /**< \brief (NVMCTRL_USER) WDT Early Warning Offset */
+#define WDT_FUSES_EWOFFSET_Msk (0xFul << WDT_FUSES_EWOFFSET_Pos)
+#define WDT_FUSES_EWOFFSET(value) (WDT_FUSES_EWOFFSET_Msk & ((value) << WDT_FUSES_EWOFFSET_Pos))
+
+#define WDT_FUSES_PER_ADDR NVMCTRL_USER
+#define WDT_FUSES_PER_Pos 27 /**< \brief (NVMCTRL_USER) WDT Period */
+#define WDT_FUSES_PER_Msk (0xFul << WDT_FUSES_PER_Pos)
+#define WDT_FUSES_PER(value) (WDT_FUSES_PER_Msk & ((value) << WDT_FUSES_PER_Pos))
+
+#define WDT_FUSES_WEN_ADDR (NVMCTRL_USER + 4)
+#define WDT_FUSES_WEN_Pos 7 /**< \brief (NVMCTRL_USER) WDT Window Mode Enable */
+#define WDT_FUSES_WEN_Msk (0x1ul << WDT_FUSES_WEN_Pos)
+
+#define WDT_FUSES_WINDOW_0_ADDR NVMCTRL_USER
+#define WDT_FUSES_WINDOW_0_Pos 31 /**< \brief (NVMCTRL_USER) WDT Window bit 0 */
+#define WDT_FUSES_WINDOW_0_Msk (0x1ul << WDT_FUSES_WINDOW_0_Pos)
+
+#define WDT_FUSES_WINDOW_1_ADDR (NVMCTRL_USER + 4)
+#define WDT_FUSES_WINDOW_1_Pos 0 /**< \brief (NVMCTRL_USER) WDT Window bits 3:1 */
+#define WDT_FUSES_WINDOW_1_Msk (0x7ul << WDT_FUSES_WINDOW_1_Pos)
+#define WDT_FUSES_WINDOW_1(value) (WDT_FUSES_WINDOW_1_Msk & ((value) << WDT_FUSES_WINDOW_1_Pos))
+
+/*@}*/
+
+#endif /* _SAMD21_NVMCTRL_COMPONENT_ */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/component/pac.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/component/pac.h
new file mode 100644
index 0000000000000000000000000000000000000000..0aeecde7a07736fddce73dbcd3f8c49fe4eb4dc6
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/component/pac.h
@@ -0,0 +1,104 @@
+/**
+ * \file
+ *
+ * \brief Component description for PAC
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_PAC_COMPONENT_
+#define _SAMD21_PAC_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR PAC */
+/* ========================================================================== */
+/** \addtogroup SAMD21_PAC Peripheral Access Controller */
+/*@{*/
+
+#define PAC_U2211
+#define REV_PAC 0x101
+
+/* -------- PAC_WPCLR : (PAC Offset: 0x0) (R/W 32) Write Protection Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :1; /*!< bit: 0 Reserved */
+ uint32_t WP:31; /*!< bit: 1..31 Write Protection Clear */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PAC_WPCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PAC_WPCLR_OFFSET 0x0 /**< \brief (PAC_WPCLR offset) Write Protection Clear */
+#define PAC_WPCLR_RESETVALUE 0x00000000ul /**< \brief (PAC_WPCLR reset_value) Write Protection Clear */
+
+#define PAC_WPCLR_WP_Pos 1 /**< \brief (PAC_WPCLR) Write Protection Clear */
+#define PAC_WPCLR_WP_Msk (0x7FFFFFFFul << PAC_WPCLR_WP_Pos)
+#define PAC_WPCLR_WP(value) (PAC_WPCLR_WP_Msk & ((value) << PAC_WPCLR_WP_Pos))
+#define PAC_WPCLR_MASK 0xFFFFFFFEul /**< \brief (PAC_WPCLR) MASK Register */
+
+/* -------- PAC_WPSET : (PAC Offset: 0x4) (R/W 32) Write Protection Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :1; /*!< bit: 0 Reserved */
+ uint32_t WP:31; /*!< bit: 1..31 Write Protection Set */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PAC_WPSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PAC_WPSET_OFFSET 0x4 /**< \brief (PAC_WPSET offset) Write Protection Set */
+#define PAC_WPSET_RESETVALUE 0x00000000ul /**< \brief (PAC_WPSET reset_value) Write Protection Set */
+
+#define PAC_WPSET_WP_Pos 1 /**< \brief (PAC_WPSET) Write Protection Set */
+#define PAC_WPSET_WP_Msk (0x7FFFFFFFul << PAC_WPSET_WP_Pos)
+#define PAC_WPSET_WP(value) (PAC_WPSET_WP_Msk & ((value) << PAC_WPSET_WP_Pos))
+#define PAC_WPSET_MASK 0xFFFFFFFEul /**< \brief (PAC_WPSET) MASK Register */
+
+/** \brief PAC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO PAC_WPCLR_Type WPCLR; /**< \brief Offset: 0x0 (R/W 32) Write Protection Clear */
+ __IO PAC_WPSET_Type WPSET; /**< \brief Offset: 0x4 (R/W 32) Write Protection Set */
+} Pac;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_PAC_COMPONENT_ */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/component/pm.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/component/pm.h
new file mode 100644
index 0000000000000000000000000000000000000000..9dc936a823a4a196e6718854dd209b7a50efc3c9
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/component/pm.h
@@ -0,0 +1,533 @@
+/**
+ * \file
+ *
+ * \brief Component description for PM
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_PM_COMPONENT_
+#define _SAMD21_PM_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR PM */
+/* ========================================================================== */
+/** \addtogroup SAMD21_PM Power Manager */
+/*@{*/
+
+#define PM_U2206
+#define REV_PM 0x201
+
+/* -------- PM_CTRL : (PM Offset: 0x00) (R/W 8) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ uint8_t reg; /*!< Type used for register access */
+} PM_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_CTRL_OFFSET 0x00 /**< \brief (PM_CTRL offset) Control */
+#define PM_CTRL_RESETVALUE 0x00ul /**< \brief (PM_CTRL reset_value) Control */
+
+#define PM_CTRL_MASK 0x00ul /**< \brief (PM_CTRL) MASK Register */
+
+/* -------- PM_SLEEP : (PM Offset: 0x01) (R/W 8) Sleep Mode -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t IDLE:2; /*!< bit: 0.. 1 Idle Mode Configuration */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} PM_SLEEP_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_SLEEP_OFFSET 0x01 /**< \brief (PM_SLEEP offset) Sleep Mode */
+#define PM_SLEEP_RESETVALUE 0x00ul /**< \brief (PM_SLEEP reset_value) Sleep Mode */
+
+#define PM_SLEEP_IDLE_Pos 0 /**< \brief (PM_SLEEP) Idle Mode Configuration */
+#define PM_SLEEP_IDLE_Msk (0x3ul << PM_SLEEP_IDLE_Pos)
+#define PM_SLEEP_IDLE(value) (PM_SLEEP_IDLE_Msk & ((value) << PM_SLEEP_IDLE_Pos))
+#define PM_SLEEP_IDLE_CPU_Val 0x0ul /**< \brief (PM_SLEEP) The CPU clock domain is stopped */
+#define PM_SLEEP_IDLE_AHB_Val 0x1ul /**< \brief (PM_SLEEP) The CPU and AHB clock domains are stopped */
+#define PM_SLEEP_IDLE_APB_Val 0x2ul /**< \brief (PM_SLEEP) The CPU, AHB and APB clock domains are stopped */
+#define PM_SLEEP_IDLE_CPU (PM_SLEEP_IDLE_CPU_Val << PM_SLEEP_IDLE_Pos)
+#define PM_SLEEP_IDLE_AHB (PM_SLEEP_IDLE_AHB_Val << PM_SLEEP_IDLE_Pos)
+#define PM_SLEEP_IDLE_APB (PM_SLEEP_IDLE_APB_Val << PM_SLEEP_IDLE_Pos)
+#define PM_SLEEP_MASK 0x03ul /**< \brief (PM_SLEEP) MASK Register */
+
+/* -------- PM_CPUSEL : (PM Offset: 0x08) (R/W 8) CPU Clock Select -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t CPUDIV:3; /*!< bit: 0.. 2 CPU Prescaler Selection */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} PM_CPUSEL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_CPUSEL_OFFSET 0x08 /**< \brief (PM_CPUSEL offset) CPU Clock Select */
+#define PM_CPUSEL_RESETVALUE 0x00ul /**< \brief (PM_CPUSEL reset_value) CPU Clock Select */
+
+#define PM_CPUSEL_CPUDIV_Pos 0 /**< \brief (PM_CPUSEL) CPU Prescaler Selection */
+#define PM_CPUSEL_CPUDIV_Msk (0x7ul << PM_CPUSEL_CPUDIV_Pos)
+#define PM_CPUSEL_CPUDIV(value) (PM_CPUSEL_CPUDIV_Msk & ((value) << PM_CPUSEL_CPUDIV_Pos))
+#define PM_CPUSEL_CPUDIV_DIV1_Val 0x0ul /**< \brief (PM_CPUSEL) Divide by 1 */
+#define PM_CPUSEL_CPUDIV_DIV2_Val 0x1ul /**< \brief (PM_CPUSEL) Divide by 2 */
+#define PM_CPUSEL_CPUDIV_DIV4_Val 0x2ul /**< \brief (PM_CPUSEL) Divide by 4 */
+#define PM_CPUSEL_CPUDIV_DIV8_Val 0x3ul /**< \brief (PM_CPUSEL) Divide by 8 */
+#define PM_CPUSEL_CPUDIV_DIV16_Val 0x4ul /**< \brief (PM_CPUSEL) Divide by 16 */
+#define PM_CPUSEL_CPUDIV_DIV32_Val 0x5ul /**< \brief (PM_CPUSEL) Divide by 32 */
+#define PM_CPUSEL_CPUDIV_DIV64_Val 0x6ul /**< \brief (PM_CPUSEL) Divide by 64 */
+#define PM_CPUSEL_CPUDIV_DIV128_Val 0x7ul /**< \brief (PM_CPUSEL) Divide by 128 */
+#define PM_CPUSEL_CPUDIV_DIV1 (PM_CPUSEL_CPUDIV_DIV1_Val << PM_CPUSEL_CPUDIV_Pos)
+#define PM_CPUSEL_CPUDIV_DIV2 (PM_CPUSEL_CPUDIV_DIV2_Val << PM_CPUSEL_CPUDIV_Pos)
+#define PM_CPUSEL_CPUDIV_DIV4 (PM_CPUSEL_CPUDIV_DIV4_Val << PM_CPUSEL_CPUDIV_Pos)
+#define PM_CPUSEL_CPUDIV_DIV8 (PM_CPUSEL_CPUDIV_DIV8_Val << PM_CPUSEL_CPUDIV_Pos)
+#define PM_CPUSEL_CPUDIV_DIV16 (PM_CPUSEL_CPUDIV_DIV16_Val << PM_CPUSEL_CPUDIV_Pos)
+#define PM_CPUSEL_CPUDIV_DIV32 (PM_CPUSEL_CPUDIV_DIV32_Val << PM_CPUSEL_CPUDIV_Pos)
+#define PM_CPUSEL_CPUDIV_DIV64 (PM_CPUSEL_CPUDIV_DIV64_Val << PM_CPUSEL_CPUDIV_Pos)
+#define PM_CPUSEL_CPUDIV_DIV128 (PM_CPUSEL_CPUDIV_DIV128_Val << PM_CPUSEL_CPUDIV_Pos)
+#define PM_CPUSEL_MASK 0x07ul /**< \brief (PM_CPUSEL) MASK Register */
+
+/* -------- PM_APBASEL : (PM Offset: 0x09) (R/W 8) APBA Clock Select -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t APBADIV:3; /*!< bit: 0.. 2 APBA Prescaler Selection */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} PM_APBASEL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_APBASEL_OFFSET 0x09 /**< \brief (PM_APBASEL offset) APBA Clock Select */
+#define PM_APBASEL_RESETVALUE 0x00ul /**< \brief (PM_APBASEL reset_value) APBA Clock Select */
+
+#define PM_APBASEL_APBADIV_Pos 0 /**< \brief (PM_APBASEL) APBA Prescaler Selection */
+#define PM_APBASEL_APBADIV_Msk (0x7ul << PM_APBASEL_APBADIV_Pos)
+#define PM_APBASEL_APBADIV(value) (PM_APBASEL_APBADIV_Msk & ((value) << PM_APBASEL_APBADIV_Pos))
+#define PM_APBASEL_APBADIV_DIV1_Val 0x0ul /**< \brief (PM_APBASEL) Divide by 1 */
+#define PM_APBASEL_APBADIV_DIV2_Val 0x1ul /**< \brief (PM_APBASEL) Divide by 2 */
+#define PM_APBASEL_APBADIV_DIV4_Val 0x2ul /**< \brief (PM_APBASEL) Divide by 4 */
+#define PM_APBASEL_APBADIV_DIV8_Val 0x3ul /**< \brief (PM_APBASEL) Divide by 8 */
+#define PM_APBASEL_APBADIV_DIV16_Val 0x4ul /**< \brief (PM_APBASEL) Divide by 16 */
+#define PM_APBASEL_APBADIV_DIV32_Val 0x5ul /**< \brief (PM_APBASEL) Divide by 32 */
+#define PM_APBASEL_APBADIV_DIV64_Val 0x6ul /**< \brief (PM_APBASEL) Divide by 64 */
+#define PM_APBASEL_APBADIV_DIV128_Val 0x7ul /**< \brief (PM_APBASEL) Divide by 128 */
+#define PM_APBASEL_APBADIV_DIV1 (PM_APBASEL_APBADIV_DIV1_Val << PM_APBASEL_APBADIV_Pos)
+#define PM_APBASEL_APBADIV_DIV2 (PM_APBASEL_APBADIV_DIV2_Val << PM_APBASEL_APBADIV_Pos)
+#define PM_APBASEL_APBADIV_DIV4 (PM_APBASEL_APBADIV_DIV4_Val << PM_APBASEL_APBADIV_Pos)
+#define PM_APBASEL_APBADIV_DIV8 (PM_APBASEL_APBADIV_DIV8_Val << PM_APBASEL_APBADIV_Pos)
+#define PM_APBASEL_APBADIV_DIV16 (PM_APBASEL_APBADIV_DIV16_Val << PM_APBASEL_APBADIV_Pos)
+#define PM_APBASEL_APBADIV_DIV32 (PM_APBASEL_APBADIV_DIV32_Val << PM_APBASEL_APBADIV_Pos)
+#define PM_APBASEL_APBADIV_DIV64 (PM_APBASEL_APBADIV_DIV64_Val << PM_APBASEL_APBADIV_Pos)
+#define PM_APBASEL_APBADIV_DIV128 (PM_APBASEL_APBADIV_DIV128_Val << PM_APBASEL_APBADIV_Pos)
+#define PM_APBASEL_MASK 0x07ul /**< \brief (PM_APBASEL) MASK Register */
+
+/* -------- PM_APBBSEL : (PM Offset: 0x0A) (R/W 8) APBB Clock Select -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t APBBDIV:3; /*!< bit: 0.. 2 APBB Prescaler Selection */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} PM_APBBSEL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_APBBSEL_OFFSET 0x0A /**< \brief (PM_APBBSEL offset) APBB Clock Select */
+#define PM_APBBSEL_RESETVALUE 0x00ul /**< \brief (PM_APBBSEL reset_value) APBB Clock Select */
+
+#define PM_APBBSEL_APBBDIV_Pos 0 /**< \brief (PM_APBBSEL) APBB Prescaler Selection */
+#define PM_APBBSEL_APBBDIV_Msk (0x7ul << PM_APBBSEL_APBBDIV_Pos)
+#define PM_APBBSEL_APBBDIV(value) (PM_APBBSEL_APBBDIV_Msk & ((value) << PM_APBBSEL_APBBDIV_Pos))
+#define PM_APBBSEL_APBBDIV_DIV1_Val 0x0ul /**< \brief (PM_APBBSEL) Divide by 1 */
+#define PM_APBBSEL_APBBDIV_DIV2_Val 0x1ul /**< \brief (PM_APBBSEL) Divide by 2 */
+#define PM_APBBSEL_APBBDIV_DIV4_Val 0x2ul /**< \brief (PM_APBBSEL) Divide by 4 */
+#define PM_APBBSEL_APBBDIV_DIV8_Val 0x3ul /**< \brief (PM_APBBSEL) Divide by 8 */
+#define PM_APBBSEL_APBBDIV_DIV16_Val 0x4ul /**< \brief (PM_APBBSEL) Divide by 16 */
+#define PM_APBBSEL_APBBDIV_DIV32_Val 0x5ul /**< \brief (PM_APBBSEL) Divide by 32 */
+#define PM_APBBSEL_APBBDIV_DIV64_Val 0x6ul /**< \brief (PM_APBBSEL) Divide by 64 */
+#define PM_APBBSEL_APBBDIV_DIV128_Val 0x7ul /**< \brief (PM_APBBSEL) Divide by 128 */
+#define PM_APBBSEL_APBBDIV_DIV1 (PM_APBBSEL_APBBDIV_DIV1_Val << PM_APBBSEL_APBBDIV_Pos)
+#define PM_APBBSEL_APBBDIV_DIV2 (PM_APBBSEL_APBBDIV_DIV2_Val << PM_APBBSEL_APBBDIV_Pos)
+#define PM_APBBSEL_APBBDIV_DIV4 (PM_APBBSEL_APBBDIV_DIV4_Val << PM_APBBSEL_APBBDIV_Pos)
+#define PM_APBBSEL_APBBDIV_DIV8 (PM_APBBSEL_APBBDIV_DIV8_Val << PM_APBBSEL_APBBDIV_Pos)
+#define PM_APBBSEL_APBBDIV_DIV16 (PM_APBBSEL_APBBDIV_DIV16_Val << PM_APBBSEL_APBBDIV_Pos)
+#define PM_APBBSEL_APBBDIV_DIV32 (PM_APBBSEL_APBBDIV_DIV32_Val << PM_APBBSEL_APBBDIV_Pos)
+#define PM_APBBSEL_APBBDIV_DIV64 (PM_APBBSEL_APBBDIV_DIV64_Val << PM_APBBSEL_APBBDIV_Pos)
+#define PM_APBBSEL_APBBDIV_DIV128 (PM_APBBSEL_APBBDIV_DIV128_Val << PM_APBBSEL_APBBDIV_Pos)
+#define PM_APBBSEL_MASK 0x07ul /**< \brief (PM_APBBSEL) MASK Register */
+
+/* -------- PM_APBCSEL : (PM Offset: 0x0B) (R/W 8) APBC Clock Select -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t APBCDIV:3; /*!< bit: 0.. 2 APBC Prescaler Selection */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} PM_APBCSEL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_APBCSEL_OFFSET 0x0B /**< \brief (PM_APBCSEL offset) APBC Clock Select */
+#define PM_APBCSEL_RESETVALUE 0x00ul /**< \brief (PM_APBCSEL reset_value) APBC Clock Select */
+
+#define PM_APBCSEL_APBCDIV_Pos 0 /**< \brief (PM_APBCSEL) APBC Prescaler Selection */
+#define PM_APBCSEL_APBCDIV_Msk (0x7ul << PM_APBCSEL_APBCDIV_Pos)
+#define PM_APBCSEL_APBCDIV(value) (PM_APBCSEL_APBCDIV_Msk & ((value) << PM_APBCSEL_APBCDIV_Pos))
+#define PM_APBCSEL_APBCDIV_DIV1_Val 0x0ul /**< \brief (PM_APBCSEL) Divide by 1 */
+#define PM_APBCSEL_APBCDIV_DIV2_Val 0x1ul /**< \brief (PM_APBCSEL) Divide by 2 */
+#define PM_APBCSEL_APBCDIV_DIV4_Val 0x2ul /**< \brief (PM_APBCSEL) Divide by 4 */
+#define PM_APBCSEL_APBCDIV_DIV8_Val 0x3ul /**< \brief (PM_APBCSEL) Divide by 8 */
+#define PM_APBCSEL_APBCDIV_DIV16_Val 0x4ul /**< \brief (PM_APBCSEL) Divide by 16 */
+#define PM_APBCSEL_APBCDIV_DIV32_Val 0x5ul /**< \brief (PM_APBCSEL) Divide by 32 */
+#define PM_APBCSEL_APBCDIV_DIV64_Val 0x6ul /**< \brief (PM_APBCSEL) Divide by 64 */
+#define PM_APBCSEL_APBCDIV_DIV128_Val 0x7ul /**< \brief (PM_APBCSEL) Divide by 128 */
+#define PM_APBCSEL_APBCDIV_DIV1 (PM_APBCSEL_APBCDIV_DIV1_Val << PM_APBCSEL_APBCDIV_Pos)
+#define PM_APBCSEL_APBCDIV_DIV2 (PM_APBCSEL_APBCDIV_DIV2_Val << PM_APBCSEL_APBCDIV_Pos)
+#define PM_APBCSEL_APBCDIV_DIV4 (PM_APBCSEL_APBCDIV_DIV4_Val << PM_APBCSEL_APBCDIV_Pos)
+#define PM_APBCSEL_APBCDIV_DIV8 (PM_APBCSEL_APBCDIV_DIV8_Val << PM_APBCSEL_APBCDIV_Pos)
+#define PM_APBCSEL_APBCDIV_DIV16 (PM_APBCSEL_APBCDIV_DIV16_Val << PM_APBCSEL_APBCDIV_Pos)
+#define PM_APBCSEL_APBCDIV_DIV32 (PM_APBCSEL_APBCDIV_DIV32_Val << PM_APBCSEL_APBCDIV_Pos)
+#define PM_APBCSEL_APBCDIV_DIV64 (PM_APBCSEL_APBCDIV_DIV64_Val << PM_APBCSEL_APBCDIV_Pos)
+#define PM_APBCSEL_APBCDIV_DIV128 (PM_APBCSEL_APBCDIV_DIV128_Val << PM_APBCSEL_APBCDIV_Pos)
+#define PM_APBCSEL_MASK 0x07ul /**< \brief (PM_APBCSEL) MASK Register */
+
+/* -------- PM_AHBMASK : (PM Offset: 0x14) (R/W 32) AHB Mask -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t HPB0_:1; /*!< bit: 0 HPB0 AHB Clock Mask */
+ uint32_t HPB1_:1; /*!< bit: 1 HPB1 AHB Clock Mask */
+ uint32_t HPB2_:1; /*!< bit: 2 HPB2 AHB Clock Mask */
+ uint32_t DSU_:1; /*!< bit: 3 DSU AHB Clock Mask */
+ uint32_t NVMCTRL_:1; /*!< bit: 4 NVMCTRL AHB Clock Mask */
+ uint32_t DMAC_:1; /*!< bit: 5 DMAC AHB Clock Mask */
+ uint32_t USB_:1; /*!< bit: 6 USB AHB Clock Mask */
+ uint32_t :25; /*!< bit: 7..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PM_AHBMASK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_AHBMASK_OFFSET 0x14 /**< \brief (PM_AHBMASK offset) AHB Mask */
+#define PM_AHBMASK_RESETVALUE 0x0000007Ful /**< \brief (PM_AHBMASK reset_value) AHB Mask */
+
+#define PM_AHBMASK_HPB0_Pos 0 /**< \brief (PM_AHBMASK) HPB0 AHB Clock Mask */
+#define PM_AHBMASK_HPB0 (0x1ul << PM_AHBMASK_HPB0_Pos)
+#define PM_AHBMASK_HPB1_Pos 1 /**< \brief (PM_AHBMASK) HPB1 AHB Clock Mask */
+#define PM_AHBMASK_HPB1 (0x1ul << PM_AHBMASK_HPB1_Pos)
+#define PM_AHBMASK_HPB2_Pos 2 /**< \brief (PM_AHBMASK) HPB2 AHB Clock Mask */
+#define PM_AHBMASK_HPB2 (0x1ul << PM_AHBMASK_HPB2_Pos)
+#define PM_AHBMASK_DSU_Pos 3 /**< \brief (PM_AHBMASK) DSU AHB Clock Mask */
+#define PM_AHBMASK_DSU (0x1ul << PM_AHBMASK_DSU_Pos)
+#define PM_AHBMASK_NVMCTRL_Pos 4 /**< \brief (PM_AHBMASK) NVMCTRL AHB Clock Mask */
+#define PM_AHBMASK_NVMCTRL (0x1ul << PM_AHBMASK_NVMCTRL_Pos)
+#define PM_AHBMASK_DMAC_Pos 5 /**< \brief (PM_AHBMASK) DMAC AHB Clock Mask */
+#define PM_AHBMASK_DMAC (0x1ul << PM_AHBMASK_DMAC_Pos)
+#define PM_AHBMASK_USB_Pos 6 /**< \brief (PM_AHBMASK) USB AHB Clock Mask */
+#define PM_AHBMASK_USB (0x1ul << PM_AHBMASK_USB_Pos)
+#define PM_AHBMASK_MASK 0x0000007Ful /**< \brief (PM_AHBMASK) MASK Register */
+
+/* -------- PM_APBAMASK : (PM Offset: 0x18) (R/W 32) APBA Mask -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t PAC0_:1; /*!< bit: 0 PAC0 APB Clock Enable */
+ uint32_t PM_:1; /*!< bit: 1 PM APB Clock Enable */
+ uint32_t SYSCTRL_:1; /*!< bit: 2 SYSCTRL APB Clock Enable */
+ uint32_t GCLK_:1; /*!< bit: 3 GCLK APB Clock Enable */
+ uint32_t WDT_:1; /*!< bit: 4 WDT APB Clock Enable */
+ uint32_t RTC_:1; /*!< bit: 5 RTC APB Clock Enable */
+ uint32_t EIC_:1; /*!< bit: 6 EIC APB Clock Enable */
+ uint32_t :25; /*!< bit: 7..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PM_APBAMASK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_APBAMASK_OFFSET 0x18 /**< \brief (PM_APBAMASK offset) APBA Mask */
+#define PM_APBAMASK_RESETVALUE 0x0000007Ful /**< \brief (PM_APBAMASK reset_value) APBA Mask */
+
+#define PM_APBAMASK_PAC0_Pos 0 /**< \brief (PM_APBAMASK) PAC0 APB Clock Enable */
+#define PM_APBAMASK_PAC0 (0x1ul << PM_APBAMASK_PAC0_Pos)
+#define PM_APBAMASK_PM_Pos 1 /**< \brief (PM_APBAMASK) PM APB Clock Enable */
+#define PM_APBAMASK_PM (0x1ul << PM_APBAMASK_PM_Pos)
+#define PM_APBAMASK_SYSCTRL_Pos 2 /**< \brief (PM_APBAMASK) SYSCTRL APB Clock Enable */
+#define PM_APBAMASK_SYSCTRL (0x1ul << PM_APBAMASK_SYSCTRL_Pos)
+#define PM_APBAMASK_GCLK_Pos 3 /**< \brief (PM_APBAMASK) GCLK APB Clock Enable */
+#define PM_APBAMASK_GCLK (0x1ul << PM_APBAMASK_GCLK_Pos)
+#define PM_APBAMASK_WDT_Pos 4 /**< \brief (PM_APBAMASK) WDT APB Clock Enable */
+#define PM_APBAMASK_WDT (0x1ul << PM_APBAMASK_WDT_Pos)
+#define PM_APBAMASK_RTC_Pos 5 /**< \brief (PM_APBAMASK) RTC APB Clock Enable */
+#define PM_APBAMASK_RTC (0x1ul << PM_APBAMASK_RTC_Pos)
+#define PM_APBAMASK_EIC_Pos 6 /**< \brief (PM_APBAMASK) EIC APB Clock Enable */
+#define PM_APBAMASK_EIC (0x1ul << PM_APBAMASK_EIC_Pos)
+#define PM_APBAMASK_MASK 0x0000007Ful /**< \brief (PM_APBAMASK) MASK Register */
+
+/* -------- PM_APBBMASK : (PM Offset: 0x1C) (R/W 32) APBB Mask -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t PAC1_:1; /*!< bit: 0 PAC1 APB Clock Enable */
+ uint32_t DSU_:1; /*!< bit: 1 DSU APB Clock Enable */
+ uint32_t NVMCTRL_:1; /*!< bit: 2 NVMCTRL APB Clock Enable */
+ uint32_t PORT_:1; /*!< bit: 3 PORT APB Clock Enable */
+ uint32_t DMAC_:1; /*!< bit: 4 DMAC APB Clock Enable */
+ uint32_t USB_:1; /*!< bit: 5 USB APB Clock Enable */
+ uint32_t HMATRIX_:1; /*!< bit: 6 HMATRIX APB Clock Enable */
+ uint32_t :25; /*!< bit: 7..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PM_APBBMASK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_APBBMASK_OFFSET 0x1C /**< \brief (PM_APBBMASK offset) APBB Mask */
+#define PM_APBBMASK_RESETVALUE 0x0000007Ful /**< \brief (PM_APBBMASK reset_value) APBB Mask */
+
+#define PM_APBBMASK_PAC1_Pos 0 /**< \brief (PM_APBBMASK) PAC1 APB Clock Enable */
+#define PM_APBBMASK_PAC1 (0x1ul << PM_APBBMASK_PAC1_Pos)
+#define PM_APBBMASK_DSU_Pos 1 /**< \brief (PM_APBBMASK) DSU APB Clock Enable */
+#define PM_APBBMASK_DSU (0x1ul << PM_APBBMASK_DSU_Pos)
+#define PM_APBBMASK_NVMCTRL_Pos 2 /**< \brief (PM_APBBMASK) NVMCTRL APB Clock Enable */
+#define PM_APBBMASK_NVMCTRL (0x1ul << PM_APBBMASK_NVMCTRL_Pos)
+#define PM_APBBMASK_PORT_Pos 3 /**< \brief (PM_APBBMASK) PORT APB Clock Enable */
+#define PM_APBBMASK_PORT (0x1ul << PM_APBBMASK_PORT_Pos)
+#define PM_APBBMASK_DMAC_Pos 4 /**< \brief (PM_APBBMASK) DMAC APB Clock Enable */
+#define PM_APBBMASK_DMAC (0x1ul << PM_APBBMASK_DMAC_Pos)
+#define PM_APBBMASK_USB_Pos 5 /**< \brief (PM_APBBMASK) USB APB Clock Enable */
+#define PM_APBBMASK_USB (0x1ul << PM_APBBMASK_USB_Pos)
+#define PM_APBBMASK_HMATRIX_Pos 6 /**< \brief (PM_APBBMASK) HMATRIX APB Clock Enable */
+#define PM_APBBMASK_HMATRIX (0x1ul << PM_APBBMASK_HMATRIX_Pos)
+#define PM_APBBMASK_MASK 0x0000007Ful /**< \brief (PM_APBBMASK) MASK Register */
+
+/* -------- PM_APBCMASK : (PM Offset: 0x20) (R/W 32) APBC Mask -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t PAC2_:1; /*!< bit: 0 PAC2 APB Clock Enable */
+ uint32_t EVSYS_:1; /*!< bit: 1 EVSYS APB Clock Enable */
+ uint32_t SERCOM0_:1; /*!< bit: 2 SERCOM0 APB Clock Enable */
+ uint32_t SERCOM1_:1; /*!< bit: 3 SERCOM1 APB Clock Enable */
+ uint32_t SERCOM2_:1; /*!< bit: 4 SERCOM2 APB Clock Enable */
+ uint32_t SERCOM3_:1; /*!< bit: 5 SERCOM3 APB Clock Enable */
+ uint32_t SERCOM4_:1; /*!< bit: 6 SERCOM4 APB Clock Enable */
+ uint32_t SERCOM5_:1; /*!< bit: 7 SERCOM5 APB Clock Enable */
+ uint32_t TCC0_:1; /*!< bit: 8 TCC0 APB Clock Enable */
+ uint32_t TCC1_:1; /*!< bit: 9 TCC1 APB Clock Enable */
+ uint32_t TCC2_:1; /*!< bit: 10 TCC2 APB Clock Enable */
+ uint32_t TC3_:1; /*!< bit: 11 TC3 APB Clock Enable */
+ uint32_t TC4_:1; /*!< bit: 12 TC4 APB Clock Enable */
+ uint32_t TC5_:1; /*!< bit: 13 TC5 APB Clock Enable */
+ uint32_t TC6_:1; /*!< bit: 14 TC6 APB Clock Enable */
+ uint32_t TC7_:1; /*!< bit: 15 TC7 APB Clock Enable */
+ uint32_t ADC_:1; /*!< bit: 16 ADC APB Clock Enable */
+ uint32_t AC_:1; /*!< bit: 17 AC APB Clock Enable */
+ uint32_t DAC_:1; /*!< bit: 18 DAC APB Clock Enable */
+ uint32_t PTC_:1; /*!< bit: 19 PTC APB Clock Enable */
+ uint32_t I2S_:1; /*!< bit: 20 I2S APB Clock Enable */
+ uint32_t :11; /*!< bit: 21..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PM_APBCMASK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_APBCMASK_OFFSET 0x20 /**< \brief (PM_APBCMASK offset) APBC Mask */
+#define PM_APBCMASK_RESETVALUE 0x00010000ul /**< \brief (PM_APBCMASK reset_value) APBC Mask */
+
+#define PM_APBCMASK_PAC2_Pos 0 /**< \brief (PM_APBCMASK) PAC2 APB Clock Enable */
+#define PM_APBCMASK_PAC2 (0x1ul << PM_APBCMASK_PAC2_Pos)
+#define PM_APBCMASK_EVSYS_Pos 1 /**< \brief (PM_APBCMASK) EVSYS APB Clock Enable */
+#define PM_APBCMASK_EVSYS (0x1ul << PM_APBCMASK_EVSYS_Pos)
+#define PM_APBCMASK_SERCOM0_Pos 2 /**< \brief (PM_APBCMASK) SERCOM0 APB Clock Enable */
+#define PM_APBCMASK_SERCOM0 (0x1ul << PM_APBCMASK_SERCOM0_Pos)
+#define PM_APBCMASK_SERCOM1_Pos 3 /**< \brief (PM_APBCMASK) SERCOM1 APB Clock Enable */
+#define PM_APBCMASK_SERCOM1 (0x1ul << PM_APBCMASK_SERCOM1_Pos)
+#define PM_APBCMASK_SERCOM2_Pos 4 /**< \brief (PM_APBCMASK) SERCOM2 APB Clock Enable */
+#define PM_APBCMASK_SERCOM2 (0x1ul << PM_APBCMASK_SERCOM2_Pos)
+#define PM_APBCMASK_SERCOM3_Pos 5 /**< \brief (PM_APBCMASK) SERCOM3 APB Clock Enable */
+#define PM_APBCMASK_SERCOM3 (0x1ul << PM_APBCMASK_SERCOM3_Pos)
+#define PM_APBCMASK_SERCOM4_Pos 6 /**< \brief (PM_APBCMASK) SERCOM4 APB Clock Enable */
+#define PM_APBCMASK_SERCOM4 (0x1ul << PM_APBCMASK_SERCOM4_Pos)
+#define PM_APBCMASK_SERCOM5_Pos 7 /**< \brief (PM_APBCMASK) SERCOM5 APB Clock Enable */
+#define PM_APBCMASK_SERCOM5 (0x1ul << PM_APBCMASK_SERCOM5_Pos)
+#define PM_APBCMASK_TCC0_Pos 8 /**< \brief (PM_APBCMASK) TCC0 APB Clock Enable */
+#define PM_APBCMASK_TCC0 (0x1ul << PM_APBCMASK_TCC0_Pos)
+#define PM_APBCMASK_TCC1_Pos 9 /**< \brief (PM_APBCMASK) TCC1 APB Clock Enable */
+#define PM_APBCMASK_TCC1 (0x1ul << PM_APBCMASK_TCC1_Pos)
+#define PM_APBCMASK_TCC2_Pos 10 /**< \brief (PM_APBCMASK) TCC2 APB Clock Enable */
+#define PM_APBCMASK_TCC2 (0x1ul << PM_APBCMASK_TCC2_Pos)
+#define PM_APBCMASK_TC3_Pos 11 /**< \brief (PM_APBCMASK) TC3 APB Clock Enable */
+#define PM_APBCMASK_TC3 (0x1ul << PM_APBCMASK_TC3_Pos)
+#define PM_APBCMASK_TC4_Pos 12 /**< \brief (PM_APBCMASK) TC4 APB Clock Enable */
+#define PM_APBCMASK_TC4 (0x1ul << PM_APBCMASK_TC4_Pos)
+#define PM_APBCMASK_TC5_Pos 13 /**< \brief (PM_APBCMASK) TC5 APB Clock Enable */
+#define PM_APBCMASK_TC5 (0x1ul << PM_APBCMASK_TC5_Pos)
+#define PM_APBCMASK_TC6_Pos 14 /**< \brief (PM_APBCMASK) TC6 APB Clock Enable */
+#define PM_APBCMASK_TC6 (0x1ul << PM_APBCMASK_TC6_Pos)
+#define PM_APBCMASK_TC7_Pos 15 /**< \brief (PM_APBCMASK) TC7 APB Clock Enable */
+#define PM_APBCMASK_TC7 (0x1ul << PM_APBCMASK_TC7_Pos)
+#define PM_APBCMASK_ADC_Pos 16 /**< \brief (PM_APBCMASK) ADC APB Clock Enable */
+#define PM_APBCMASK_ADC (0x1ul << PM_APBCMASK_ADC_Pos)
+#define PM_APBCMASK_AC_Pos 17 /**< \brief (PM_APBCMASK) AC APB Clock Enable */
+#define PM_APBCMASK_AC (0x1ul << PM_APBCMASK_AC_Pos)
+#define PM_APBCMASK_DAC_Pos 18 /**< \brief (PM_APBCMASK) DAC APB Clock Enable */
+#define PM_APBCMASK_DAC (0x1ul << PM_APBCMASK_DAC_Pos)
+#define PM_APBCMASK_PTC_Pos 19 /**< \brief (PM_APBCMASK) PTC APB Clock Enable */
+#define PM_APBCMASK_PTC (0x1ul << PM_APBCMASK_PTC_Pos)
+#define PM_APBCMASK_I2S_Pos 20 /**< \brief (PM_APBCMASK) I2S APB Clock Enable */
+#define PM_APBCMASK_I2S (0x1ul << PM_APBCMASK_I2S_Pos)
+#define PM_APBCMASK_MASK 0x001FFFFFul /**< \brief (PM_APBCMASK) MASK Register */
+
+/* -------- PM_INTENCLR : (PM Offset: 0x34) (R/W 8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} PM_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_INTENCLR_OFFSET 0x34 /**< \brief (PM_INTENCLR offset) Interrupt Enable Clear */
+#define PM_INTENCLR_RESETVALUE 0x00ul /**< \brief (PM_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define PM_INTENCLR_CKRDY_Pos 0 /**< \brief (PM_INTENCLR) Clock Ready Interrupt Enable */
+#define PM_INTENCLR_CKRDY (0x1ul << PM_INTENCLR_CKRDY_Pos)
+#define PM_INTENCLR_MASK 0x01ul /**< \brief (PM_INTENCLR) MASK Register */
+
+/* -------- PM_INTENSET : (PM Offset: 0x35) (R/W 8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} PM_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_INTENSET_OFFSET 0x35 /**< \brief (PM_INTENSET offset) Interrupt Enable Set */
+#define PM_INTENSET_RESETVALUE 0x00ul /**< \brief (PM_INTENSET reset_value) Interrupt Enable Set */
+
+#define PM_INTENSET_CKRDY_Pos 0 /**< \brief (PM_INTENSET) Clock Ready Interrupt Enable */
+#define PM_INTENSET_CKRDY (0x1ul << PM_INTENSET_CKRDY_Pos)
+#define PM_INTENSET_MASK 0x01ul /**< \brief (PM_INTENSET) MASK Register */
+
+/* -------- PM_INTFLAG : (PM Offset: 0x36) (R/W 8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint8_t CKRDY:1; /*!< bit: 0 Clock Ready */
+ __I uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} PM_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_INTFLAG_OFFSET 0x36 /**< \brief (PM_INTFLAG offset) Interrupt Flag Status and Clear */
+#define PM_INTFLAG_RESETVALUE 0x00ul /**< \brief (PM_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define PM_INTFLAG_CKRDY_Pos 0 /**< \brief (PM_INTFLAG) Clock Ready */
+#define PM_INTFLAG_CKRDY (0x1ul << PM_INTFLAG_CKRDY_Pos)
+#define PM_INTFLAG_MASK 0x01ul /**< \brief (PM_INTFLAG) MASK Register */
+
+/* -------- PM_RCAUSE : (PM Offset: 0x38) (R/ 8) Reset Cause -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t POR:1; /*!< bit: 0 Power On Reset */
+ uint8_t BOD12:1; /*!< bit: 1 Brown Out 12 Detector Reset */
+ uint8_t BOD33:1; /*!< bit: 2 Brown Out 33 Detector Reset */
+ uint8_t :1; /*!< bit: 3 Reserved */
+ uint8_t EXT:1; /*!< bit: 4 External Reset */
+ uint8_t WDT:1; /*!< bit: 5 Watchdog Reset */
+ uint8_t SYST:1; /*!< bit: 6 System Reset Request */
+ uint8_t :1; /*!< bit: 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} PM_RCAUSE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PM_RCAUSE_OFFSET 0x38 /**< \brief (PM_RCAUSE offset) Reset Cause */
+#define PM_RCAUSE_RESETVALUE 0x01ul /**< \brief (PM_RCAUSE reset_value) Reset Cause */
+
+#define PM_RCAUSE_POR_Pos 0 /**< \brief (PM_RCAUSE) Power On Reset */
+#define PM_RCAUSE_POR (0x1ul << PM_RCAUSE_POR_Pos)
+#define PM_RCAUSE_BOD12_Pos 1 /**< \brief (PM_RCAUSE) Brown Out 12 Detector Reset */
+#define PM_RCAUSE_BOD12 (0x1ul << PM_RCAUSE_BOD12_Pos)
+#define PM_RCAUSE_BOD33_Pos 2 /**< \brief (PM_RCAUSE) Brown Out 33 Detector Reset */
+#define PM_RCAUSE_BOD33 (0x1ul << PM_RCAUSE_BOD33_Pos)
+#define PM_RCAUSE_EXT_Pos 4 /**< \brief (PM_RCAUSE) External Reset */
+#define PM_RCAUSE_EXT (0x1ul << PM_RCAUSE_EXT_Pos)
+#define PM_RCAUSE_WDT_Pos 5 /**< \brief (PM_RCAUSE) Watchdog Reset */
+#define PM_RCAUSE_WDT (0x1ul << PM_RCAUSE_WDT_Pos)
+#define PM_RCAUSE_SYST_Pos 6 /**< \brief (PM_RCAUSE) System Reset Request */
+#define PM_RCAUSE_SYST (0x1ul << PM_RCAUSE_SYST_Pos)
+#define PM_RCAUSE_MASK 0x77ul /**< \brief (PM_RCAUSE) MASK Register */
+
+/** \brief PM hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO PM_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 8) Control */
+ __IO PM_SLEEP_Type SLEEP; /**< \brief Offset: 0x01 (R/W 8) Sleep Mode */
+ RoReg8 Reserved1[0x6];
+ __IO PM_CPUSEL_Type CPUSEL; /**< \brief Offset: 0x08 (R/W 8) CPU Clock Select */
+ __IO PM_APBASEL_Type APBASEL; /**< \brief Offset: 0x09 (R/W 8) APBA Clock Select */
+ __IO PM_APBBSEL_Type APBBSEL; /**< \brief Offset: 0x0A (R/W 8) APBB Clock Select */
+ __IO PM_APBCSEL_Type APBCSEL; /**< \brief Offset: 0x0B (R/W 8) APBC Clock Select */
+ RoReg8 Reserved2[0x8];
+ __IO PM_AHBMASK_Type AHBMASK; /**< \brief Offset: 0x14 (R/W 32) AHB Mask */
+ __IO PM_APBAMASK_Type APBAMASK; /**< \brief Offset: 0x18 (R/W 32) APBA Mask */
+ __IO PM_APBBMASK_Type APBBMASK; /**< \brief Offset: 0x1C (R/W 32) APBB Mask */
+ __IO PM_APBCMASK_Type APBCMASK; /**< \brief Offset: 0x20 (R/W 32) APBC Mask */
+ RoReg8 Reserved3[0x10];
+ __IO PM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x34 (R/W 8) Interrupt Enable Clear */
+ __IO PM_INTENSET_Type INTENSET; /**< \brief Offset: 0x35 (R/W 8) Interrupt Enable Set */
+ __IO PM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x36 (R/W 8) Interrupt Flag Status and Clear */
+ RoReg8 Reserved4[0x1];
+ __I PM_RCAUSE_Type RCAUSE; /**< \brief Offset: 0x38 (R/ 8) Reset Cause */
+} Pm;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_PM_COMPONENT_ */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/component/port.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/component/port.h
new file mode 100644
index 0000000000000000000000000000000000000000..a74e283c5b0dbba6b19880df36a943c3b3a16eea
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/component/port.h
@@ -0,0 +1,396 @@
+/**
+ * \file
+ *
+ * \brief Component description for PORT
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_PORT_COMPONENT_
+#define _SAMD21_PORT_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR PORT */
+/* ========================================================================== */
+/** \addtogroup SAMD21_PORT Port Module */
+/*@{*/
+
+#define PORT_U2210
+#define REV_PORT 0x100
+
+/* -------- PORT_DIR : (PORT Offset: 0x00) (R/W 32) GROUP Data Direction -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DIR:32; /*!< bit: 0..31 Port Data Direction */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PORT_DIR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_DIR_OFFSET 0x00 /**< \brief (PORT_DIR offset) Data Direction */
+#define PORT_DIR_RESETVALUE 0x00000000ul /**< \brief (PORT_DIR reset_value) Data Direction */
+
+#define PORT_DIR_DIR_Pos 0 /**< \brief (PORT_DIR) Port Data Direction */
+#define PORT_DIR_DIR_Msk (0xFFFFFFFFul << PORT_DIR_DIR_Pos)
+#define PORT_DIR_DIR(value) (PORT_DIR_DIR_Msk & ((value) << PORT_DIR_DIR_Pos))
+#define PORT_DIR_MASK 0xFFFFFFFFul /**< \brief (PORT_DIR) MASK Register */
+
+/* -------- PORT_DIRCLR : (PORT Offset: 0x04) (R/W 32) GROUP Data Direction Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DIRCLR:32; /*!< bit: 0..31 Port Data Direction Clear */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PORT_DIRCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_DIRCLR_OFFSET 0x04 /**< \brief (PORT_DIRCLR offset) Data Direction Clear */
+#define PORT_DIRCLR_RESETVALUE 0x00000000ul /**< \brief (PORT_DIRCLR reset_value) Data Direction Clear */
+
+#define PORT_DIRCLR_DIRCLR_Pos 0 /**< \brief (PORT_DIRCLR) Port Data Direction Clear */
+#define PORT_DIRCLR_DIRCLR_Msk (0xFFFFFFFFul << PORT_DIRCLR_DIRCLR_Pos)
+#define PORT_DIRCLR_DIRCLR(value) (PORT_DIRCLR_DIRCLR_Msk & ((value) << PORT_DIRCLR_DIRCLR_Pos))
+#define PORT_DIRCLR_MASK 0xFFFFFFFFul /**< \brief (PORT_DIRCLR) MASK Register */
+
+/* -------- PORT_DIRSET : (PORT Offset: 0x08) (R/W 32) GROUP Data Direction Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DIRSET:32; /*!< bit: 0..31 Port Data Direction Set */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PORT_DIRSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_DIRSET_OFFSET 0x08 /**< \brief (PORT_DIRSET offset) Data Direction Set */
+#define PORT_DIRSET_RESETVALUE 0x00000000ul /**< \brief (PORT_DIRSET reset_value) Data Direction Set */
+
+#define PORT_DIRSET_DIRSET_Pos 0 /**< \brief (PORT_DIRSET) Port Data Direction Set */
+#define PORT_DIRSET_DIRSET_Msk (0xFFFFFFFFul << PORT_DIRSET_DIRSET_Pos)
+#define PORT_DIRSET_DIRSET(value) (PORT_DIRSET_DIRSET_Msk & ((value) << PORT_DIRSET_DIRSET_Pos))
+#define PORT_DIRSET_MASK 0xFFFFFFFFul /**< \brief (PORT_DIRSET) MASK Register */
+
+/* -------- PORT_DIRTGL : (PORT Offset: 0x0C) (R/W 32) GROUP Data Direction Toggle -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DIRTGL:32; /*!< bit: 0..31 Port Data Direction Toggle */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PORT_DIRTGL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_DIRTGL_OFFSET 0x0C /**< \brief (PORT_DIRTGL offset) Data Direction Toggle */
+#define PORT_DIRTGL_RESETVALUE 0x00000000ul /**< \brief (PORT_DIRTGL reset_value) Data Direction Toggle */
+
+#define PORT_DIRTGL_DIRTGL_Pos 0 /**< \brief (PORT_DIRTGL) Port Data Direction Toggle */
+#define PORT_DIRTGL_DIRTGL_Msk (0xFFFFFFFFul << PORT_DIRTGL_DIRTGL_Pos)
+#define PORT_DIRTGL_DIRTGL(value) (PORT_DIRTGL_DIRTGL_Msk & ((value) << PORT_DIRTGL_DIRTGL_Pos))
+#define PORT_DIRTGL_MASK 0xFFFFFFFFul /**< \brief (PORT_DIRTGL) MASK Register */
+
+/* -------- PORT_OUT : (PORT Offset: 0x10) (R/W 32) GROUP Data Output Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t OUT:32; /*!< bit: 0..31 Port Data Output Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PORT_OUT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_OUT_OFFSET 0x10 /**< \brief (PORT_OUT offset) Data Output Value */
+#define PORT_OUT_RESETVALUE 0x00000000ul /**< \brief (PORT_OUT reset_value) Data Output Value */
+
+#define PORT_OUT_OUT_Pos 0 /**< \brief (PORT_OUT) Port Data Output Value */
+#define PORT_OUT_OUT_Msk (0xFFFFFFFFul << PORT_OUT_OUT_Pos)
+#define PORT_OUT_OUT(value) (PORT_OUT_OUT_Msk & ((value) << PORT_OUT_OUT_Pos))
+#define PORT_OUT_MASK 0xFFFFFFFFul /**< \brief (PORT_OUT) MASK Register */
+
+/* -------- PORT_OUTCLR : (PORT Offset: 0x14) (R/W 32) GROUP Data Output Value Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t OUTCLR:32; /*!< bit: 0..31 Port Data Output Value Clear */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PORT_OUTCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_OUTCLR_OFFSET 0x14 /**< \brief (PORT_OUTCLR offset) Data Output Value Clear */
+#define PORT_OUTCLR_RESETVALUE 0x00000000ul /**< \brief (PORT_OUTCLR reset_value) Data Output Value Clear */
+
+#define PORT_OUTCLR_OUTCLR_Pos 0 /**< \brief (PORT_OUTCLR) Port Data Output Value Clear */
+#define PORT_OUTCLR_OUTCLR_Msk (0xFFFFFFFFul << PORT_OUTCLR_OUTCLR_Pos)
+#define PORT_OUTCLR_OUTCLR(value) (PORT_OUTCLR_OUTCLR_Msk & ((value) << PORT_OUTCLR_OUTCLR_Pos))
+#define PORT_OUTCLR_MASK 0xFFFFFFFFul /**< \brief (PORT_OUTCLR) MASK Register */
+
+/* -------- PORT_OUTSET : (PORT Offset: 0x18) (R/W 32) GROUP Data Output Value Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t OUTSET:32; /*!< bit: 0..31 Port Data Output Value Set */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PORT_OUTSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_OUTSET_OFFSET 0x18 /**< \brief (PORT_OUTSET offset) Data Output Value Set */
+#define PORT_OUTSET_RESETVALUE 0x00000000ul /**< \brief (PORT_OUTSET reset_value) Data Output Value Set */
+
+#define PORT_OUTSET_OUTSET_Pos 0 /**< \brief (PORT_OUTSET) Port Data Output Value Set */
+#define PORT_OUTSET_OUTSET_Msk (0xFFFFFFFFul << PORT_OUTSET_OUTSET_Pos)
+#define PORT_OUTSET_OUTSET(value) (PORT_OUTSET_OUTSET_Msk & ((value) << PORT_OUTSET_OUTSET_Pos))
+#define PORT_OUTSET_MASK 0xFFFFFFFFul /**< \brief (PORT_OUTSET) MASK Register */
+
+/* -------- PORT_OUTTGL : (PORT Offset: 0x1C) (R/W 32) GROUP Data Output Value Toggle -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t OUTTGL:32; /*!< bit: 0..31 Port Data Output Value Toggle */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PORT_OUTTGL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_OUTTGL_OFFSET 0x1C /**< \brief (PORT_OUTTGL offset) Data Output Value Toggle */
+#define PORT_OUTTGL_RESETVALUE 0x00000000ul /**< \brief (PORT_OUTTGL reset_value) Data Output Value Toggle */
+
+#define PORT_OUTTGL_OUTTGL_Pos 0 /**< \brief (PORT_OUTTGL) Port Data Output Value Toggle */
+#define PORT_OUTTGL_OUTTGL_Msk (0xFFFFFFFFul << PORT_OUTTGL_OUTTGL_Pos)
+#define PORT_OUTTGL_OUTTGL(value) (PORT_OUTTGL_OUTTGL_Msk & ((value) << PORT_OUTTGL_OUTTGL_Pos))
+#define PORT_OUTTGL_MASK 0xFFFFFFFFul /**< \brief (PORT_OUTTGL) MASK Register */
+
+/* -------- PORT_IN : (PORT Offset: 0x20) (R/ 32) GROUP Data Input Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t IN:32; /*!< bit: 0..31 Port Data Input Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PORT_IN_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_IN_OFFSET 0x20 /**< \brief (PORT_IN offset) Data Input Value */
+#define PORT_IN_RESETVALUE 0x00000000ul /**< \brief (PORT_IN reset_value) Data Input Value */
+
+#define PORT_IN_IN_Pos 0 /**< \brief (PORT_IN) Port Data Input Value */
+#define PORT_IN_IN_Msk (0xFFFFFFFFul << PORT_IN_IN_Pos)
+#define PORT_IN_IN(value) (PORT_IN_IN_Msk & ((value) << PORT_IN_IN_Pos))
+#define PORT_IN_MASK 0xFFFFFFFFul /**< \brief (PORT_IN) MASK Register */
+
+/* -------- PORT_CTRL : (PORT Offset: 0x24) (R/W 32) GROUP Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SAMPLING:32; /*!< bit: 0..31 Input Sampling Mode */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PORT_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_CTRL_OFFSET 0x24 /**< \brief (PORT_CTRL offset) Control */
+#define PORT_CTRL_RESETVALUE 0x00000000ul /**< \brief (PORT_CTRL reset_value) Control */
+
+#define PORT_CTRL_SAMPLING_Pos 0 /**< \brief (PORT_CTRL) Input Sampling Mode */
+#define PORT_CTRL_SAMPLING_Msk (0xFFFFFFFFul << PORT_CTRL_SAMPLING_Pos)
+#define PORT_CTRL_SAMPLING(value) (PORT_CTRL_SAMPLING_Msk & ((value) << PORT_CTRL_SAMPLING_Pos))
+#define PORT_CTRL_MASK 0xFFFFFFFFul /**< \brief (PORT_CTRL) MASK Register */
+
+/* -------- PORT_WRCONFIG : (PORT Offset: 0x28) ( /W 32) GROUP Write Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t PINMASK:16; /*!< bit: 0..15 Pin Mask for Multiple Pin Configuration */
+ uint32_t PMUXEN:1; /*!< bit: 16 Peripheral Multiplexer Enable */
+ uint32_t INEN:1; /*!< bit: 17 Input Enable */
+ uint32_t PULLEN:1; /*!< bit: 18 Pull Enable */
+ uint32_t :3; /*!< bit: 19..21 Reserved */
+ uint32_t DRVSTR:1; /*!< bit: 22 Output Driver Strength Selection */
+ uint32_t :1; /*!< bit: 23 Reserved */
+ uint32_t PMUX:4; /*!< bit: 24..27 Peripheral Multiplexing */
+ uint32_t WRPMUX:1; /*!< bit: 28 Write PMUX */
+ uint32_t :1; /*!< bit: 29 Reserved */
+ uint32_t WRPINCFG:1; /*!< bit: 30 Write PINCFG */
+ uint32_t HWSEL:1; /*!< bit: 31 Half-Word Select */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} PORT_WRCONFIG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_WRCONFIG_OFFSET 0x28 /**< \brief (PORT_WRCONFIG offset) Write Configuration */
+#define PORT_WRCONFIG_RESETVALUE 0x00000000ul /**< \brief (PORT_WRCONFIG reset_value) Write Configuration */
+
+#define PORT_WRCONFIG_PINMASK_Pos 0 /**< \brief (PORT_WRCONFIG) Pin Mask for Multiple Pin Configuration */
+#define PORT_WRCONFIG_PINMASK_Msk (0xFFFFul << PORT_WRCONFIG_PINMASK_Pos)
+#define PORT_WRCONFIG_PINMASK(value) (PORT_WRCONFIG_PINMASK_Msk & ((value) << PORT_WRCONFIG_PINMASK_Pos))
+#define PORT_WRCONFIG_PMUXEN_Pos 16 /**< \brief (PORT_WRCONFIG) Peripheral Multiplexer Enable */
+#define PORT_WRCONFIG_PMUXEN (0x1ul << PORT_WRCONFIG_PMUXEN_Pos)
+#define PORT_WRCONFIG_INEN_Pos 17 /**< \brief (PORT_WRCONFIG) Input Enable */
+#define PORT_WRCONFIG_INEN (0x1ul << PORT_WRCONFIG_INEN_Pos)
+#define PORT_WRCONFIG_PULLEN_Pos 18 /**< \brief (PORT_WRCONFIG) Pull Enable */
+#define PORT_WRCONFIG_PULLEN (0x1ul << PORT_WRCONFIG_PULLEN_Pos)
+#define PORT_WRCONFIG_DRVSTR_Pos 22 /**< \brief (PORT_WRCONFIG) Output Driver Strength Selection */
+#define PORT_WRCONFIG_DRVSTR (0x1ul << PORT_WRCONFIG_DRVSTR_Pos)
+#define PORT_WRCONFIG_PMUX_Pos 24 /**< \brief (PORT_WRCONFIG) Peripheral Multiplexing */
+#define PORT_WRCONFIG_PMUX_Msk (0xFul << PORT_WRCONFIG_PMUX_Pos)
+#define PORT_WRCONFIG_PMUX(value) (PORT_WRCONFIG_PMUX_Msk & ((value) << PORT_WRCONFIG_PMUX_Pos))
+#define PORT_WRCONFIG_WRPMUX_Pos 28 /**< \brief (PORT_WRCONFIG) Write PMUX */
+#define PORT_WRCONFIG_WRPMUX (0x1ul << PORT_WRCONFIG_WRPMUX_Pos)
+#define PORT_WRCONFIG_WRPINCFG_Pos 30 /**< \brief (PORT_WRCONFIG) Write PINCFG */
+#define PORT_WRCONFIG_WRPINCFG (0x1ul << PORT_WRCONFIG_WRPINCFG_Pos)
+#define PORT_WRCONFIG_HWSEL_Pos 31 /**< \brief (PORT_WRCONFIG) Half-Word Select */
+#define PORT_WRCONFIG_HWSEL (0x1ul << PORT_WRCONFIG_HWSEL_Pos)
+#define PORT_WRCONFIG_MASK 0xDF47FFFFul /**< \brief (PORT_WRCONFIG) MASK Register */
+
+/* -------- PORT_PMUX : (PORT Offset: 0x30) (R/W 8) GROUP Peripheral Multiplexing n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t PMUXE:4; /*!< bit: 0.. 3 Peripheral Multiplexing Even */
+ uint8_t PMUXO:4; /*!< bit: 4.. 7 Peripheral Multiplexing Odd */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} PORT_PMUX_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_PMUX_OFFSET 0x30 /**< \brief (PORT_PMUX offset) Peripheral Multiplexing n */
+#define PORT_PMUX_RESETVALUE 0x00ul /**< \brief (PORT_PMUX reset_value) Peripheral Multiplexing n */
+
+#define PORT_PMUX_PMUXE_Pos 0 /**< \brief (PORT_PMUX) Peripheral Multiplexing Even */
+#define PORT_PMUX_PMUXE_Msk (0xFul << PORT_PMUX_PMUXE_Pos)
+#define PORT_PMUX_PMUXE(value) (PORT_PMUX_PMUXE_Msk & ((value) << PORT_PMUX_PMUXE_Pos))
+#define PORT_PMUX_PMUXE_A_Val 0x0ul /**< \brief (PORT_PMUX) Peripheral function A selected */
+#define PORT_PMUX_PMUXE_B_Val 0x1ul /**< \brief (PORT_PMUX) Peripheral function B selected */
+#define PORT_PMUX_PMUXE_C_Val 0x2ul /**< \brief (PORT_PMUX) Peripheral function C selected */
+#define PORT_PMUX_PMUXE_D_Val 0x3ul /**< \brief (PORT_PMUX) Peripheral function D selected */
+#define PORT_PMUX_PMUXE_E_Val 0x4ul /**< \brief (PORT_PMUX) Peripheral function E selected */
+#define PORT_PMUX_PMUXE_F_Val 0x5ul /**< \brief (PORT_PMUX) Peripheral function F selected */
+#define PORT_PMUX_PMUXE_G_Val 0x6ul /**< \brief (PORT_PMUX) Peripheral function G selected */
+#define PORT_PMUX_PMUXE_H_Val 0x7ul /**< \brief (PORT_PMUX) Peripheral function H selected */
+#define PORT_PMUX_PMUXE_A (PORT_PMUX_PMUXE_A_Val << PORT_PMUX_PMUXE_Pos)
+#define PORT_PMUX_PMUXE_B (PORT_PMUX_PMUXE_B_Val << PORT_PMUX_PMUXE_Pos)
+#define PORT_PMUX_PMUXE_C (PORT_PMUX_PMUXE_C_Val << PORT_PMUX_PMUXE_Pos)
+#define PORT_PMUX_PMUXE_D (PORT_PMUX_PMUXE_D_Val << PORT_PMUX_PMUXE_Pos)
+#define PORT_PMUX_PMUXE_E (PORT_PMUX_PMUXE_E_Val << PORT_PMUX_PMUXE_Pos)
+#define PORT_PMUX_PMUXE_F (PORT_PMUX_PMUXE_F_Val << PORT_PMUX_PMUXE_Pos)
+#define PORT_PMUX_PMUXE_G (PORT_PMUX_PMUXE_G_Val << PORT_PMUX_PMUXE_Pos)
+#define PORT_PMUX_PMUXE_H (PORT_PMUX_PMUXE_H_Val << PORT_PMUX_PMUXE_Pos)
+#define PORT_PMUX_PMUXO_Pos 4 /**< \brief (PORT_PMUX) Peripheral Multiplexing Odd */
+#define PORT_PMUX_PMUXO_Msk (0xFul << PORT_PMUX_PMUXO_Pos)
+#define PORT_PMUX_PMUXO(value) (PORT_PMUX_PMUXO_Msk & ((value) << PORT_PMUX_PMUXO_Pos))
+#define PORT_PMUX_PMUXO_A_Val 0x0ul /**< \brief (PORT_PMUX) Peripheral function A selected */
+#define PORT_PMUX_PMUXO_B_Val 0x1ul /**< \brief (PORT_PMUX) Peripheral function B selected */
+#define PORT_PMUX_PMUXO_C_Val 0x2ul /**< \brief (PORT_PMUX) Peripheral function C selected */
+#define PORT_PMUX_PMUXO_D_Val 0x3ul /**< \brief (PORT_PMUX) Peripheral function D selected */
+#define PORT_PMUX_PMUXO_E_Val 0x4ul /**< \brief (PORT_PMUX) Peripheral function E selected */
+#define PORT_PMUX_PMUXO_F_Val 0x5ul /**< \brief (PORT_PMUX) Peripheral function F selected */
+#define PORT_PMUX_PMUXO_G_Val 0x6ul /**< \brief (PORT_PMUX) Peripheral function G selected */
+#define PORT_PMUX_PMUXO_H_Val 0x7ul /**< \brief (PORT_PMUX) Peripheral function H selected */
+#define PORT_PMUX_PMUXO_A (PORT_PMUX_PMUXO_A_Val << PORT_PMUX_PMUXO_Pos)
+#define PORT_PMUX_PMUXO_B (PORT_PMUX_PMUXO_B_Val << PORT_PMUX_PMUXO_Pos)
+#define PORT_PMUX_PMUXO_C (PORT_PMUX_PMUXO_C_Val << PORT_PMUX_PMUXO_Pos)
+#define PORT_PMUX_PMUXO_D (PORT_PMUX_PMUXO_D_Val << PORT_PMUX_PMUXO_Pos)
+#define PORT_PMUX_PMUXO_E (PORT_PMUX_PMUXO_E_Val << PORT_PMUX_PMUXO_Pos)
+#define PORT_PMUX_PMUXO_F (PORT_PMUX_PMUXO_F_Val << PORT_PMUX_PMUXO_Pos)
+#define PORT_PMUX_PMUXO_G (PORT_PMUX_PMUXO_G_Val << PORT_PMUX_PMUXO_Pos)
+#define PORT_PMUX_PMUXO_H (PORT_PMUX_PMUXO_H_Val << PORT_PMUX_PMUXO_Pos)
+#define PORT_PMUX_MASK 0xFFul /**< \brief (PORT_PMUX) MASK Register */
+
+/* -------- PORT_PINCFG : (PORT Offset: 0x40) (R/W 8) GROUP Pin Configuration n -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t PMUXEN:1; /*!< bit: 0 Peripheral Multiplexer Enable */
+ uint8_t INEN:1; /*!< bit: 1 Input Enable */
+ uint8_t PULLEN:1; /*!< bit: 2 Pull Enable */
+ uint8_t :3; /*!< bit: 3.. 5 Reserved */
+ uint8_t DRVSTR:1; /*!< bit: 6 Output Driver Strength Selection */
+ uint8_t :1; /*!< bit: 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} PORT_PINCFG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define PORT_PINCFG_OFFSET 0x40 /**< \brief (PORT_PINCFG offset) Pin Configuration n */
+#define PORT_PINCFG_RESETVALUE 0x00ul /**< \brief (PORT_PINCFG reset_value) Pin Configuration n */
+
+#define PORT_PINCFG_PMUXEN_Pos 0 /**< \brief (PORT_PINCFG) Peripheral Multiplexer Enable */
+#define PORT_PINCFG_PMUXEN (0x1ul << PORT_PINCFG_PMUXEN_Pos)
+#define PORT_PINCFG_INEN_Pos 1 /**< \brief (PORT_PINCFG) Input Enable */
+#define PORT_PINCFG_INEN (0x1ul << PORT_PINCFG_INEN_Pos)
+#define PORT_PINCFG_PULLEN_Pos 2 /**< \brief (PORT_PINCFG) Pull Enable */
+#define PORT_PINCFG_PULLEN (0x1ul << PORT_PINCFG_PULLEN_Pos)
+#define PORT_PINCFG_DRVSTR_Pos 6 /**< \brief (PORT_PINCFG) Output Driver Strength Selection */
+#define PORT_PINCFG_DRVSTR (0x1ul << PORT_PINCFG_DRVSTR_Pos)
+#define PORT_PINCFG_MASK 0x47ul /**< \brief (PORT_PINCFG) MASK Register */
+
+/** \brief PortGroup hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO PORT_DIR_Type DIR; /**< \brief Offset: 0x00 (R/W 32) Data Direction */
+ __IO PORT_DIRCLR_Type DIRCLR; /**< \brief Offset: 0x04 (R/W 32) Data Direction Clear */
+ __IO PORT_DIRSET_Type DIRSET; /**< \brief Offset: 0x08 (R/W 32) Data Direction Set */
+ __IO PORT_DIRTGL_Type DIRTGL; /**< \brief Offset: 0x0C (R/W 32) Data Direction Toggle */
+ __IO PORT_OUT_Type OUT; /**< \brief Offset: 0x10 (R/W 32) Data Output Value */
+ __IO PORT_OUTCLR_Type OUTCLR; /**< \brief Offset: 0x14 (R/W 32) Data Output Value Clear */
+ __IO PORT_OUTSET_Type OUTSET; /**< \brief Offset: 0x18 (R/W 32) Data Output Value Set */
+ __IO PORT_OUTTGL_Type OUTTGL; /**< \brief Offset: 0x1C (R/W 32) Data Output Value Toggle */
+ __I PORT_IN_Type IN; /**< \brief Offset: 0x20 (R/ 32) Data Input Value */
+ __IO PORT_CTRL_Type CTRL; /**< \brief Offset: 0x24 (R/W 32) Control */
+ __O PORT_WRCONFIG_Type WRCONFIG; /**< \brief Offset: 0x28 ( /W 32) Write Configuration */
+ RoReg8 Reserved1[0x4];
+ __IO PORT_PMUX_Type PMUX[16]; /**< \brief Offset: 0x30 (R/W 8) Peripheral Multiplexing n */
+ __IO PORT_PINCFG_Type PINCFG[32]; /**< \brief Offset: 0x40 (R/W 8) Pin Configuration n */
+ RoReg8 Reserved2[0x20];
+} PortGroup;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief PORT hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ PortGroup Group[2]; /**< \brief Offset: 0x00 PortGroup groups [GROUPS] */
+} Port;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SECTION_PORT_IOBUS
+
+/*@}*/
+
+#endif /* _SAMD21_PORT_COMPONENT_ */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/component/rtc.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/component/rtc.h
new file mode 100644
index 0000000000000000000000000000000000000000..64fac32f1870e1daec4ad5c9635397dffa7f4068
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/component/rtc.h
@@ -0,0 +1,1062 @@
+/**
+ * \file
+ *
+ * \brief Component description for RTC
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_RTC_COMPONENT_
+#define _SAMD21_RTC_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR RTC */
+/* ========================================================================== */
+/** \addtogroup SAMD21_RTC Real-Time Counter */
+/*@{*/
+
+#define RTC_U2202
+#define REV_RTC 0x101
+
+/* -------- RTC_MODE0_CTRL : (RTC Offset: 0x00) (R/W 16) MODE0 MODE0 Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint16_t ENABLE:1; /*!< bit: 1 Enable */
+ uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */
+ uint16_t :3; /*!< bit: 4.. 6 Reserved */
+ uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */
+ uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} RTC_MODE0_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE0_CTRL_OFFSET 0x00 /**< \brief (RTC_MODE0_CTRL offset) MODE0 Control */
+#define RTC_MODE0_CTRL_RESETVALUE 0x0000ul /**< \brief (RTC_MODE0_CTRL reset_value) MODE0 Control */
+
+#define RTC_MODE0_CTRL_SWRST_Pos 0 /**< \brief (RTC_MODE0_CTRL) Software Reset */
+#define RTC_MODE0_CTRL_SWRST (0x1ul << RTC_MODE0_CTRL_SWRST_Pos)
+#define RTC_MODE0_CTRL_ENABLE_Pos 1 /**< \brief (RTC_MODE0_CTRL) Enable */
+#define RTC_MODE0_CTRL_ENABLE (0x1ul << RTC_MODE0_CTRL_ENABLE_Pos)
+#define RTC_MODE0_CTRL_MODE_Pos 2 /**< \brief (RTC_MODE0_CTRL) Operating Mode */
+#define RTC_MODE0_CTRL_MODE_Msk (0x3ul << RTC_MODE0_CTRL_MODE_Pos)
+#define RTC_MODE0_CTRL_MODE(value) (RTC_MODE0_CTRL_MODE_Msk & ((value) << RTC_MODE0_CTRL_MODE_Pos))
+#define RTC_MODE0_CTRL_MODE_COUNT32_Val 0x0ul /**< \brief (RTC_MODE0_CTRL) Mode 0: 32-bit Counter */
+#define RTC_MODE0_CTRL_MODE_COUNT16_Val 0x1ul /**< \brief (RTC_MODE0_CTRL) Mode 1: 16-bit Counter */
+#define RTC_MODE0_CTRL_MODE_CLOCK_Val 0x2ul /**< \brief (RTC_MODE0_CTRL) Mode 2: Clock/Calendar */
+#define RTC_MODE0_CTRL_MODE_COUNT32 (RTC_MODE0_CTRL_MODE_COUNT32_Val << RTC_MODE0_CTRL_MODE_Pos)
+#define RTC_MODE0_CTRL_MODE_COUNT16 (RTC_MODE0_CTRL_MODE_COUNT16_Val << RTC_MODE0_CTRL_MODE_Pos)
+#define RTC_MODE0_CTRL_MODE_CLOCK (RTC_MODE0_CTRL_MODE_CLOCK_Val << RTC_MODE0_CTRL_MODE_Pos)
+#define RTC_MODE0_CTRL_MATCHCLR_Pos 7 /**< \brief (RTC_MODE0_CTRL) Clear on Match */
+#define RTC_MODE0_CTRL_MATCHCLR (0x1ul << RTC_MODE0_CTRL_MATCHCLR_Pos)
+#define RTC_MODE0_CTRL_PRESCALER_Pos 8 /**< \brief (RTC_MODE0_CTRL) Prescaler */
+#define RTC_MODE0_CTRL_PRESCALER_Msk (0xFul << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_PRESCALER(value) (RTC_MODE0_CTRL_PRESCALER_Msk & ((value) << RTC_MODE0_CTRL_PRESCALER_Pos))
+#define RTC_MODE0_CTRL_PRESCALER_DIV1_Val 0x0ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/1 */
+#define RTC_MODE0_CTRL_PRESCALER_DIV2_Val 0x1ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/2 */
+#define RTC_MODE0_CTRL_PRESCALER_DIV4_Val 0x2ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/4 */
+#define RTC_MODE0_CTRL_PRESCALER_DIV8_Val 0x3ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/8 */
+#define RTC_MODE0_CTRL_PRESCALER_DIV16_Val 0x4ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/16 */
+#define RTC_MODE0_CTRL_PRESCALER_DIV32_Val 0x5ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/32 */
+#define RTC_MODE0_CTRL_PRESCALER_DIV64_Val 0x6ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/64 */
+#define RTC_MODE0_CTRL_PRESCALER_DIV128_Val 0x7ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/128 */
+#define RTC_MODE0_CTRL_PRESCALER_DIV256_Val 0x8ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/256 */
+#define RTC_MODE0_CTRL_PRESCALER_DIV512_Val 0x9ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/512 */
+#define RTC_MODE0_CTRL_PRESCALER_DIV1024_Val 0xAul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/1024 */
+#define RTC_MODE0_CTRL_PRESCALER_DIV1 (RTC_MODE0_CTRL_PRESCALER_DIV1_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_PRESCALER_DIV2 (RTC_MODE0_CTRL_PRESCALER_DIV2_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_PRESCALER_DIV4 (RTC_MODE0_CTRL_PRESCALER_DIV4_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_PRESCALER_DIV8 (RTC_MODE0_CTRL_PRESCALER_DIV8_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_PRESCALER_DIV16 (RTC_MODE0_CTRL_PRESCALER_DIV16_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_PRESCALER_DIV32 (RTC_MODE0_CTRL_PRESCALER_DIV32_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_PRESCALER_DIV64 (RTC_MODE0_CTRL_PRESCALER_DIV64_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_PRESCALER_DIV128 (RTC_MODE0_CTRL_PRESCALER_DIV128_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_PRESCALER_DIV256 (RTC_MODE0_CTRL_PRESCALER_DIV256_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_PRESCALER_DIV512 (RTC_MODE0_CTRL_PRESCALER_DIV512_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_PRESCALER_DIV1024 (RTC_MODE0_CTRL_PRESCALER_DIV1024_Val << RTC_MODE0_CTRL_PRESCALER_Pos)
+#define RTC_MODE0_CTRL_MASK 0x0F8Ful /**< \brief (RTC_MODE0_CTRL) MASK Register */
+
+/* -------- RTC_MODE1_CTRL : (RTC Offset: 0x00) (R/W 16) MODE1 MODE1 Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint16_t ENABLE:1; /*!< bit: 1 Enable */
+ uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */
+ uint16_t :4; /*!< bit: 4.. 7 Reserved */
+ uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} RTC_MODE1_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_CTRL_OFFSET 0x00 /**< \brief (RTC_MODE1_CTRL offset) MODE1 Control */
+#define RTC_MODE1_CTRL_RESETVALUE 0x0000ul /**< \brief (RTC_MODE1_CTRL reset_value) MODE1 Control */
+
+#define RTC_MODE1_CTRL_SWRST_Pos 0 /**< \brief (RTC_MODE1_CTRL) Software Reset */
+#define RTC_MODE1_CTRL_SWRST (0x1ul << RTC_MODE1_CTRL_SWRST_Pos)
+#define RTC_MODE1_CTRL_ENABLE_Pos 1 /**< \brief (RTC_MODE1_CTRL) Enable */
+#define RTC_MODE1_CTRL_ENABLE (0x1ul << RTC_MODE1_CTRL_ENABLE_Pos)
+#define RTC_MODE1_CTRL_MODE_Pos 2 /**< \brief (RTC_MODE1_CTRL) Operating Mode */
+#define RTC_MODE1_CTRL_MODE_Msk (0x3ul << RTC_MODE1_CTRL_MODE_Pos)
+#define RTC_MODE1_CTRL_MODE(value) (RTC_MODE1_CTRL_MODE_Msk & ((value) << RTC_MODE1_CTRL_MODE_Pos))
+#define RTC_MODE1_CTRL_MODE_COUNT32_Val 0x0ul /**< \brief (RTC_MODE1_CTRL) Mode 0: 32-bit Counter */
+#define RTC_MODE1_CTRL_MODE_COUNT16_Val 0x1ul /**< \brief (RTC_MODE1_CTRL) Mode 1: 16-bit Counter */
+#define RTC_MODE1_CTRL_MODE_CLOCK_Val 0x2ul /**< \brief (RTC_MODE1_CTRL) Mode 2: Clock/Calendar */
+#define RTC_MODE1_CTRL_MODE_COUNT32 (RTC_MODE1_CTRL_MODE_COUNT32_Val << RTC_MODE1_CTRL_MODE_Pos)
+#define RTC_MODE1_CTRL_MODE_COUNT16 (RTC_MODE1_CTRL_MODE_COUNT16_Val << RTC_MODE1_CTRL_MODE_Pos)
+#define RTC_MODE1_CTRL_MODE_CLOCK (RTC_MODE1_CTRL_MODE_CLOCK_Val << RTC_MODE1_CTRL_MODE_Pos)
+#define RTC_MODE1_CTRL_PRESCALER_Pos 8 /**< \brief (RTC_MODE1_CTRL) Prescaler */
+#define RTC_MODE1_CTRL_PRESCALER_Msk (0xFul << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_PRESCALER(value) (RTC_MODE1_CTRL_PRESCALER_Msk & ((value) << RTC_MODE1_CTRL_PRESCALER_Pos))
+#define RTC_MODE1_CTRL_PRESCALER_DIV1_Val 0x0ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/1 */
+#define RTC_MODE1_CTRL_PRESCALER_DIV2_Val 0x1ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/2 */
+#define RTC_MODE1_CTRL_PRESCALER_DIV4_Val 0x2ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/4 */
+#define RTC_MODE1_CTRL_PRESCALER_DIV8_Val 0x3ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/8 */
+#define RTC_MODE1_CTRL_PRESCALER_DIV16_Val 0x4ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/16 */
+#define RTC_MODE1_CTRL_PRESCALER_DIV32_Val 0x5ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/32 */
+#define RTC_MODE1_CTRL_PRESCALER_DIV64_Val 0x6ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/64 */
+#define RTC_MODE1_CTRL_PRESCALER_DIV128_Val 0x7ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/128 */
+#define RTC_MODE1_CTRL_PRESCALER_DIV256_Val 0x8ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/256 */
+#define RTC_MODE1_CTRL_PRESCALER_DIV512_Val 0x9ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/512 */
+#define RTC_MODE1_CTRL_PRESCALER_DIV1024_Val 0xAul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/1024 */
+#define RTC_MODE1_CTRL_PRESCALER_DIV1 (RTC_MODE1_CTRL_PRESCALER_DIV1_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_PRESCALER_DIV2 (RTC_MODE1_CTRL_PRESCALER_DIV2_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_PRESCALER_DIV4 (RTC_MODE1_CTRL_PRESCALER_DIV4_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_PRESCALER_DIV8 (RTC_MODE1_CTRL_PRESCALER_DIV8_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_PRESCALER_DIV16 (RTC_MODE1_CTRL_PRESCALER_DIV16_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_PRESCALER_DIV32 (RTC_MODE1_CTRL_PRESCALER_DIV32_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_PRESCALER_DIV64 (RTC_MODE1_CTRL_PRESCALER_DIV64_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_PRESCALER_DIV128 (RTC_MODE1_CTRL_PRESCALER_DIV128_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_PRESCALER_DIV256 (RTC_MODE1_CTRL_PRESCALER_DIV256_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_PRESCALER_DIV512 (RTC_MODE1_CTRL_PRESCALER_DIV512_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_PRESCALER_DIV1024 (RTC_MODE1_CTRL_PRESCALER_DIV1024_Val << RTC_MODE1_CTRL_PRESCALER_Pos)
+#define RTC_MODE1_CTRL_MASK 0x0F0Ful /**< \brief (RTC_MODE1_CTRL) MASK Register */
+
+/* -------- RTC_MODE2_CTRL : (RTC Offset: 0x00) (R/W 16) MODE2 MODE2 Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint16_t ENABLE:1; /*!< bit: 1 Enable */
+ uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */
+ uint16_t :2; /*!< bit: 4.. 5 Reserved */
+ uint16_t CLKREP:1; /*!< bit: 6 Clock Representation */
+ uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */
+ uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} RTC_MODE2_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_CTRL_OFFSET 0x00 /**< \brief (RTC_MODE2_CTRL offset) MODE2 Control */
+#define RTC_MODE2_CTRL_RESETVALUE 0x0000ul /**< \brief (RTC_MODE2_CTRL reset_value) MODE2 Control */
+
+#define RTC_MODE2_CTRL_SWRST_Pos 0 /**< \brief (RTC_MODE2_CTRL) Software Reset */
+#define RTC_MODE2_CTRL_SWRST (0x1ul << RTC_MODE2_CTRL_SWRST_Pos)
+#define RTC_MODE2_CTRL_ENABLE_Pos 1 /**< \brief (RTC_MODE2_CTRL) Enable */
+#define RTC_MODE2_CTRL_ENABLE (0x1ul << RTC_MODE2_CTRL_ENABLE_Pos)
+#define RTC_MODE2_CTRL_MODE_Pos 2 /**< \brief (RTC_MODE2_CTRL) Operating Mode */
+#define RTC_MODE2_CTRL_MODE_Msk (0x3ul << RTC_MODE2_CTRL_MODE_Pos)
+#define RTC_MODE2_CTRL_MODE(value) (RTC_MODE2_CTRL_MODE_Msk & ((value) << RTC_MODE2_CTRL_MODE_Pos))
+#define RTC_MODE2_CTRL_MODE_COUNT32_Val 0x0ul /**< \brief (RTC_MODE2_CTRL) Mode 0: 32-bit Counter */
+#define RTC_MODE2_CTRL_MODE_COUNT16_Val 0x1ul /**< \brief (RTC_MODE2_CTRL) Mode 1: 16-bit Counter */
+#define RTC_MODE2_CTRL_MODE_CLOCK_Val 0x2ul /**< \brief (RTC_MODE2_CTRL) Mode 2: Clock/Calendar */
+#define RTC_MODE2_CTRL_MODE_COUNT32 (RTC_MODE2_CTRL_MODE_COUNT32_Val << RTC_MODE2_CTRL_MODE_Pos)
+#define RTC_MODE2_CTRL_MODE_COUNT16 (RTC_MODE2_CTRL_MODE_COUNT16_Val << RTC_MODE2_CTRL_MODE_Pos)
+#define RTC_MODE2_CTRL_MODE_CLOCK (RTC_MODE2_CTRL_MODE_CLOCK_Val << RTC_MODE2_CTRL_MODE_Pos)
+#define RTC_MODE2_CTRL_CLKREP_Pos 6 /**< \brief (RTC_MODE2_CTRL) Clock Representation */
+#define RTC_MODE2_CTRL_CLKREP (0x1ul << RTC_MODE2_CTRL_CLKREP_Pos)
+#define RTC_MODE2_CTRL_MATCHCLR_Pos 7 /**< \brief (RTC_MODE2_CTRL) Clear on Match */
+#define RTC_MODE2_CTRL_MATCHCLR (0x1ul << RTC_MODE2_CTRL_MATCHCLR_Pos)
+#define RTC_MODE2_CTRL_PRESCALER_Pos 8 /**< \brief (RTC_MODE2_CTRL) Prescaler */
+#define RTC_MODE2_CTRL_PRESCALER_Msk (0xFul << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_PRESCALER(value) (RTC_MODE2_CTRL_PRESCALER_Msk & ((value) << RTC_MODE2_CTRL_PRESCALER_Pos))
+#define RTC_MODE2_CTRL_PRESCALER_DIV1_Val 0x0ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/1 */
+#define RTC_MODE2_CTRL_PRESCALER_DIV2_Val 0x1ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/2 */
+#define RTC_MODE2_CTRL_PRESCALER_DIV4_Val 0x2ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/4 */
+#define RTC_MODE2_CTRL_PRESCALER_DIV8_Val 0x3ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/8 */
+#define RTC_MODE2_CTRL_PRESCALER_DIV16_Val 0x4ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/16 */
+#define RTC_MODE2_CTRL_PRESCALER_DIV32_Val 0x5ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/32 */
+#define RTC_MODE2_CTRL_PRESCALER_DIV64_Val 0x6ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/64 */
+#define RTC_MODE2_CTRL_PRESCALER_DIV128_Val 0x7ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/128 */
+#define RTC_MODE2_CTRL_PRESCALER_DIV256_Val 0x8ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/256 */
+#define RTC_MODE2_CTRL_PRESCALER_DIV512_Val 0x9ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/512 */
+#define RTC_MODE2_CTRL_PRESCALER_DIV1024_Val 0xAul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/1024 */
+#define RTC_MODE2_CTRL_PRESCALER_DIV1 (RTC_MODE2_CTRL_PRESCALER_DIV1_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_PRESCALER_DIV2 (RTC_MODE2_CTRL_PRESCALER_DIV2_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_PRESCALER_DIV4 (RTC_MODE2_CTRL_PRESCALER_DIV4_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_PRESCALER_DIV8 (RTC_MODE2_CTRL_PRESCALER_DIV8_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_PRESCALER_DIV16 (RTC_MODE2_CTRL_PRESCALER_DIV16_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_PRESCALER_DIV32 (RTC_MODE2_CTRL_PRESCALER_DIV32_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_PRESCALER_DIV64 (RTC_MODE2_CTRL_PRESCALER_DIV64_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_PRESCALER_DIV128 (RTC_MODE2_CTRL_PRESCALER_DIV128_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_PRESCALER_DIV256 (RTC_MODE2_CTRL_PRESCALER_DIV256_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_PRESCALER_DIV512 (RTC_MODE2_CTRL_PRESCALER_DIV512_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_PRESCALER_DIV1024 (RTC_MODE2_CTRL_PRESCALER_DIV1024_Val << RTC_MODE2_CTRL_PRESCALER_Pos)
+#define RTC_MODE2_CTRL_MASK 0x0FCFul /**< \brief (RTC_MODE2_CTRL) MASK Register */
+
+/* -------- RTC_READREQ : (RTC Offset: 0x02) (R/W 16) Read Request -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t ADDR:6; /*!< bit: 0.. 5 Address */
+ uint16_t :8; /*!< bit: 6..13 Reserved */
+ uint16_t RCONT:1; /*!< bit: 14 Read Continuously */
+ uint16_t RREQ:1; /*!< bit: 15 Read Request */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} RTC_READREQ_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_READREQ_OFFSET 0x02 /**< \brief (RTC_READREQ offset) Read Request */
+#define RTC_READREQ_RESETVALUE 0x0010ul /**< \brief (RTC_READREQ reset_value) Read Request */
+
+#define RTC_READREQ_ADDR_Pos 0 /**< \brief (RTC_READREQ) Address */
+#define RTC_READREQ_ADDR_Msk (0x3Ful << RTC_READREQ_ADDR_Pos)
+#define RTC_READREQ_ADDR(value) (RTC_READREQ_ADDR_Msk & ((value) << RTC_READREQ_ADDR_Pos))
+#define RTC_READREQ_RCONT_Pos 14 /**< \brief (RTC_READREQ) Read Continuously */
+#define RTC_READREQ_RCONT (0x1ul << RTC_READREQ_RCONT_Pos)
+#define RTC_READREQ_RREQ_Pos 15 /**< \brief (RTC_READREQ) Read Request */
+#define RTC_READREQ_RREQ (0x1ul << RTC_READREQ_RREQ_Pos)
+#define RTC_READREQ_MASK 0xC03Ful /**< \brief (RTC_READREQ) MASK Register */
+
+/* -------- RTC_MODE0_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE0 MODE0 Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */
+ uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */
+ uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */
+ uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */
+ uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */
+ uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */
+ uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */
+ uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */
+ uint16_t CMPEO0:1; /*!< bit: 8 Compare 0 Event Output Enable */
+ uint16_t :6; /*!< bit: 9..14 Reserved */
+ uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */
+ uint16_t CMPEO:1; /*!< bit: 8 Compare x Event Output Enable */
+ uint16_t :7; /*!< bit: 9..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} RTC_MODE0_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE0_EVCTRL_OFFSET 0x04 /**< \brief (RTC_MODE0_EVCTRL offset) MODE0 Event Control */
+#define RTC_MODE0_EVCTRL_RESETVALUE 0x0000ul /**< \brief (RTC_MODE0_EVCTRL reset_value) MODE0 Event Control */
+
+#define RTC_MODE0_EVCTRL_PEREO0_Pos 0 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 0 Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO0 (1 << RTC_MODE0_EVCTRL_PEREO0_Pos)
+#define RTC_MODE0_EVCTRL_PEREO1_Pos 1 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 1 Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO1 (1 << RTC_MODE0_EVCTRL_PEREO1_Pos)
+#define RTC_MODE0_EVCTRL_PEREO2_Pos 2 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 2 Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO2 (1 << RTC_MODE0_EVCTRL_PEREO2_Pos)
+#define RTC_MODE0_EVCTRL_PEREO3_Pos 3 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 3 Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO3 (1 << RTC_MODE0_EVCTRL_PEREO3_Pos)
+#define RTC_MODE0_EVCTRL_PEREO4_Pos 4 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 4 Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO4 (1 << RTC_MODE0_EVCTRL_PEREO4_Pos)
+#define RTC_MODE0_EVCTRL_PEREO5_Pos 5 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 5 Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO5 (1 << RTC_MODE0_EVCTRL_PEREO5_Pos)
+#define RTC_MODE0_EVCTRL_PEREO6_Pos 6 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 6 Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO6 (1 << RTC_MODE0_EVCTRL_PEREO6_Pos)
+#define RTC_MODE0_EVCTRL_PEREO7_Pos 7 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 7 Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO7 (1 << RTC_MODE0_EVCTRL_PEREO7_Pos)
+#define RTC_MODE0_EVCTRL_PEREO_Pos 0 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval x Event Output Enable */
+#define RTC_MODE0_EVCTRL_PEREO_Msk (0xFFul << RTC_MODE0_EVCTRL_PEREO_Pos)
+#define RTC_MODE0_EVCTRL_PEREO(value) (RTC_MODE0_EVCTRL_PEREO_Msk & ((value) << RTC_MODE0_EVCTRL_PEREO_Pos))
+#define RTC_MODE0_EVCTRL_CMPEO0_Pos 8 /**< \brief (RTC_MODE0_EVCTRL) Compare 0 Event Output Enable */
+#define RTC_MODE0_EVCTRL_CMPEO0 (1 << RTC_MODE0_EVCTRL_CMPEO0_Pos)
+#define RTC_MODE0_EVCTRL_CMPEO_Pos 8 /**< \brief (RTC_MODE0_EVCTRL) Compare x Event Output Enable */
+#define RTC_MODE0_EVCTRL_CMPEO_Msk (0x1ul << RTC_MODE0_EVCTRL_CMPEO_Pos)
+#define RTC_MODE0_EVCTRL_CMPEO(value) (RTC_MODE0_EVCTRL_CMPEO_Msk & ((value) << RTC_MODE0_EVCTRL_CMPEO_Pos))
+#define RTC_MODE0_EVCTRL_OVFEO_Pos 15 /**< \brief (RTC_MODE0_EVCTRL) Overflow Event Output Enable */
+#define RTC_MODE0_EVCTRL_OVFEO (0x1ul << RTC_MODE0_EVCTRL_OVFEO_Pos)
+#define RTC_MODE0_EVCTRL_MASK 0x81FFul /**< \brief (RTC_MODE0_EVCTRL) MASK Register */
+
+/* -------- RTC_MODE1_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE1 MODE1 Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */
+ uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */
+ uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */
+ uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */
+ uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */
+ uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */
+ uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */
+ uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */
+ uint16_t CMPEO0:1; /*!< bit: 8 Compare 0 Event Output Enable */
+ uint16_t CMPEO1:1; /*!< bit: 9 Compare 1 Event Output Enable */
+ uint16_t :5; /*!< bit: 10..14 Reserved */
+ uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */
+ uint16_t CMPEO:2; /*!< bit: 8.. 9 Compare x Event Output Enable */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} RTC_MODE1_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_EVCTRL_OFFSET 0x04 /**< \brief (RTC_MODE1_EVCTRL offset) MODE1 Event Control */
+#define RTC_MODE1_EVCTRL_RESETVALUE 0x0000ul /**< \brief (RTC_MODE1_EVCTRL reset_value) MODE1 Event Control */
+
+#define RTC_MODE1_EVCTRL_PEREO0_Pos 0 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 0 Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO0 (1 << RTC_MODE1_EVCTRL_PEREO0_Pos)
+#define RTC_MODE1_EVCTRL_PEREO1_Pos 1 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 1 Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO1 (1 << RTC_MODE1_EVCTRL_PEREO1_Pos)
+#define RTC_MODE1_EVCTRL_PEREO2_Pos 2 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 2 Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO2 (1 << RTC_MODE1_EVCTRL_PEREO2_Pos)
+#define RTC_MODE1_EVCTRL_PEREO3_Pos 3 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 3 Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO3 (1 << RTC_MODE1_EVCTRL_PEREO3_Pos)
+#define RTC_MODE1_EVCTRL_PEREO4_Pos 4 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 4 Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO4 (1 << RTC_MODE1_EVCTRL_PEREO4_Pos)
+#define RTC_MODE1_EVCTRL_PEREO5_Pos 5 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 5 Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO5 (1 << RTC_MODE1_EVCTRL_PEREO5_Pos)
+#define RTC_MODE1_EVCTRL_PEREO6_Pos 6 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 6 Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO6 (1 << RTC_MODE1_EVCTRL_PEREO6_Pos)
+#define RTC_MODE1_EVCTRL_PEREO7_Pos 7 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 7 Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO7 (1 << RTC_MODE1_EVCTRL_PEREO7_Pos)
+#define RTC_MODE1_EVCTRL_PEREO_Pos 0 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval x Event Output Enable */
+#define RTC_MODE1_EVCTRL_PEREO_Msk (0xFFul << RTC_MODE1_EVCTRL_PEREO_Pos)
+#define RTC_MODE1_EVCTRL_PEREO(value) (RTC_MODE1_EVCTRL_PEREO_Msk & ((value) << RTC_MODE1_EVCTRL_PEREO_Pos))
+#define RTC_MODE1_EVCTRL_CMPEO0_Pos 8 /**< \brief (RTC_MODE1_EVCTRL) Compare 0 Event Output Enable */
+#define RTC_MODE1_EVCTRL_CMPEO0 (1 << RTC_MODE1_EVCTRL_CMPEO0_Pos)
+#define RTC_MODE1_EVCTRL_CMPEO1_Pos 9 /**< \brief (RTC_MODE1_EVCTRL) Compare 1 Event Output Enable */
+#define RTC_MODE1_EVCTRL_CMPEO1 (1 << RTC_MODE1_EVCTRL_CMPEO1_Pos)
+#define RTC_MODE1_EVCTRL_CMPEO_Pos 8 /**< \brief (RTC_MODE1_EVCTRL) Compare x Event Output Enable */
+#define RTC_MODE1_EVCTRL_CMPEO_Msk (0x3ul << RTC_MODE1_EVCTRL_CMPEO_Pos)
+#define RTC_MODE1_EVCTRL_CMPEO(value) (RTC_MODE1_EVCTRL_CMPEO_Msk & ((value) << RTC_MODE1_EVCTRL_CMPEO_Pos))
+#define RTC_MODE1_EVCTRL_OVFEO_Pos 15 /**< \brief (RTC_MODE1_EVCTRL) Overflow Event Output Enable */
+#define RTC_MODE1_EVCTRL_OVFEO (0x1ul << RTC_MODE1_EVCTRL_OVFEO_Pos)
+#define RTC_MODE1_EVCTRL_MASK 0x83FFul /**< \brief (RTC_MODE1_EVCTRL) MASK Register */
+
+/* -------- RTC_MODE2_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE2 MODE2 Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */
+ uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */
+ uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */
+ uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */
+ uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */
+ uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */
+ uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */
+ uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */
+ uint16_t ALARMEO0:1; /*!< bit: 8 Alarm 0 Event Output Enable */
+ uint16_t :6; /*!< bit: 9..14 Reserved */
+ uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */
+ uint16_t ALARMEO:1; /*!< bit: 8 Alarm x Event Output Enable */
+ uint16_t :7; /*!< bit: 9..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} RTC_MODE2_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_EVCTRL_OFFSET 0x04 /**< \brief (RTC_MODE2_EVCTRL offset) MODE2 Event Control */
+#define RTC_MODE2_EVCTRL_RESETVALUE 0x0000ul /**< \brief (RTC_MODE2_EVCTRL reset_value) MODE2 Event Control */
+
+#define RTC_MODE2_EVCTRL_PEREO0_Pos 0 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 0 Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO0 (1 << RTC_MODE2_EVCTRL_PEREO0_Pos)
+#define RTC_MODE2_EVCTRL_PEREO1_Pos 1 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 1 Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO1 (1 << RTC_MODE2_EVCTRL_PEREO1_Pos)
+#define RTC_MODE2_EVCTRL_PEREO2_Pos 2 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 2 Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO2 (1 << RTC_MODE2_EVCTRL_PEREO2_Pos)
+#define RTC_MODE2_EVCTRL_PEREO3_Pos 3 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 3 Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO3 (1 << RTC_MODE2_EVCTRL_PEREO3_Pos)
+#define RTC_MODE2_EVCTRL_PEREO4_Pos 4 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 4 Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO4 (1 << RTC_MODE2_EVCTRL_PEREO4_Pos)
+#define RTC_MODE2_EVCTRL_PEREO5_Pos 5 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 5 Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO5 (1 << RTC_MODE2_EVCTRL_PEREO5_Pos)
+#define RTC_MODE2_EVCTRL_PEREO6_Pos 6 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 6 Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO6 (1 << RTC_MODE2_EVCTRL_PEREO6_Pos)
+#define RTC_MODE2_EVCTRL_PEREO7_Pos 7 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 7 Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO7 (1 << RTC_MODE2_EVCTRL_PEREO7_Pos)
+#define RTC_MODE2_EVCTRL_PEREO_Pos 0 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval x Event Output Enable */
+#define RTC_MODE2_EVCTRL_PEREO_Msk (0xFFul << RTC_MODE2_EVCTRL_PEREO_Pos)
+#define RTC_MODE2_EVCTRL_PEREO(value) (RTC_MODE2_EVCTRL_PEREO_Msk & ((value) << RTC_MODE2_EVCTRL_PEREO_Pos))
+#define RTC_MODE2_EVCTRL_ALARMEO0_Pos 8 /**< \brief (RTC_MODE2_EVCTRL) Alarm 0 Event Output Enable */
+#define RTC_MODE2_EVCTRL_ALARMEO0 (1 << RTC_MODE2_EVCTRL_ALARMEO0_Pos)
+#define RTC_MODE2_EVCTRL_ALARMEO_Pos 8 /**< \brief (RTC_MODE2_EVCTRL) Alarm x Event Output Enable */
+#define RTC_MODE2_EVCTRL_ALARMEO_Msk (0x1ul << RTC_MODE2_EVCTRL_ALARMEO_Pos)
+#define RTC_MODE2_EVCTRL_ALARMEO(value) (RTC_MODE2_EVCTRL_ALARMEO_Msk & ((value) << RTC_MODE2_EVCTRL_ALARMEO_Pos))
+#define RTC_MODE2_EVCTRL_OVFEO_Pos 15 /**< \brief (RTC_MODE2_EVCTRL) Overflow Event Output Enable */
+#define RTC_MODE2_EVCTRL_OVFEO (0x1ul << RTC_MODE2_EVCTRL_OVFEO_Pos)
+#define RTC_MODE2_EVCTRL_MASK 0x81FFul /**< \brief (RTC_MODE2_EVCTRL) MASK Register */
+
+/* -------- RTC_MODE0_INTENCLR : (RTC Offset: 0x06) (R/W 8) MODE0 MODE0 Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
+ uint8_t :5; /*!< bit: 1.. 5 Reserved */
+ uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
+ uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t CMP:1; /*!< bit: 0 Compare x Interrupt Enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} RTC_MODE0_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE0_INTENCLR_OFFSET 0x06 /**< \brief (RTC_MODE0_INTENCLR offset) MODE0 Interrupt Enable Clear */
+#define RTC_MODE0_INTENCLR_RESETVALUE 0x00ul /**< \brief (RTC_MODE0_INTENCLR reset_value) MODE0 Interrupt Enable Clear */
+
+#define RTC_MODE0_INTENCLR_CMP0_Pos 0 /**< \brief (RTC_MODE0_INTENCLR) Compare 0 Interrupt Enable */
+#define RTC_MODE0_INTENCLR_CMP0 (1 << RTC_MODE0_INTENCLR_CMP0_Pos)
+#define RTC_MODE0_INTENCLR_CMP_Pos 0 /**< \brief (RTC_MODE0_INTENCLR) Compare x Interrupt Enable */
+#define RTC_MODE0_INTENCLR_CMP_Msk (0x1ul << RTC_MODE0_INTENCLR_CMP_Pos)
+#define RTC_MODE0_INTENCLR_CMP(value) (RTC_MODE0_INTENCLR_CMP_Msk & ((value) << RTC_MODE0_INTENCLR_CMP_Pos))
+#define RTC_MODE0_INTENCLR_SYNCRDY_Pos 6 /**< \brief (RTC_MODE0_INTENCLR) Synchronization Ready Interrupt Enable */
+#define RTC_MODE0_INTENCLR_SYNCRDY (0x1ul << RTC_MODE0_INTENCLR_SYNCRDY_Pos)
+#define RTC_MODE0_INTENCLR_OVF_Pos 7 /**< \brief (RTC_MODE0_INTENCLR) Overflow Interrupt Enable */
+#define RTC_MODE0_INTENCLR_OVF (0x1ul << RTC_MODE0_INTENCLR_OVF_Pos)
+#define RTC_MODE0_INTENCLR_MASK 0xC1ul /**< \brief (RTC_MODE0_INTENCLR) MASK Register */
+
+/* -------- RTC_MODE1_INTENCLR : (RTC Offset: 0x06) (R/W 8) MODE1 MODE1 Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
+ uint8_t CMP1:1; /*!< bit: 1 Compare 1 Interrupt Enable */
+ uint8_t :4; /*!< bit: 2.. 5 Reserved */
+ uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
+ uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t CMP:2; /*!< bit: 0.. 1 Compare x Interrupt Enable */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} RTC_MODE1_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_INTENCLR_OFFSET 0x06 /**< \brief (RTC_MODE1_INTENCLR offset) MODE1 Interrupt Enable Clear */
+#define RTC_MODE1_INTENCLR_RESETVALUE 0x00ul /**< \brief (RTC_MODE1_INTENCLR reset_value) MODE1 Interrupt Enable Clear */
+
+#define RTC_MODE1_INTENCLR_CMP0_Pos 0 /**< \brief (RTC_MODE1_INTENCLR) Compare 0 Interrupt Enable */
+#define RTC_MODE1_INTENCLR_CMP0 (1 << RTC_MODE1_INTENCLR_CMP0_Pos)
+#define RTC_MODE1_INTENCLR_CMP1_Pos 1 /**< \brief (RTC_MODE1_INTENCLR) Compare 1 Interrupt Enable */
+#define RTC_MODE1_INTENCLR_CMP1 (1 << RTC_MODE1_INTENCLR_CMP1_Pos)
+#define RTC_MODE1_INTENCLR_CMP_Pos 0 /**< \brief (RTC_MODE1_INTENCLR) Compare x Interrupt Enable */
+#define RTC_MODE1_INTENCLR_CMP_Msk (0x3ul << RTC_MODE1_INTENCLR_CMP_Pos)
+#define RTC_MODE1_INTENCLR_CMP(value) (RTC_MODE1_INTENCLR_CMP_Msk & ((value) << RTC_MODE1_INTENCLR_CMP_Pos))
+#define RTC_MODE1_INTENCLR_SYNCRDY_Pos 6 /**< \brief (RTC_MODE1_INTENCLR) Synchronization Ready Interrupt Enable */
+#define RTC_MODE1_INTENCLR_SYNCRDY (0x1ul << RTC_MODE1_INTENCLR_SYNCRDY_Pos)
+#define RTC_MODE1_INTENCLR_OVF_Pos 7 /**< \brief (RTC_MODE1_INTENCLR) Overflow Interrupt Enable */
+#define RTC_MODE1_INTENCLR_OVF (0x1ul << RTC_MODE1_INTENCLR_OVF_Pos)
+#define RTC_MODE1_INTENCLR_MASK 0xC3ul /**< \brief (RTC_MODE1_INTENCLR) MASK Register */
+
+/* -------- RTC_MODE2_INTENCLR : (RTC Offset: 0x06) (R/W 8) MODE2 MODE2 Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 Interrupt Enable */
+ uint8_t :5; /*!< bit: 1.. 5 Reserved */
+ uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
+ uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t ALARM:1; /*!< bit: 0 Alarm x Interrupt Enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} RTC_MODE2_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_INTENCLR_OFFSET 0x06 /**< \brief (RTC_MODE2_INTENCLR offset) MODE2 Interrupt Enable Clear */
+#define RTC_MODE2_INTENCLR_RESETVALUE 0x00ul /**< \brief (RTC_MODE2_INTENCLR reset_value) MODE2 Interrupt Enable Clear */
+
+#define RTC_MODE2_INTENCLR_ALARM0_Pos 0 /**< \brief (RTC_MODE2_INTENCLR) Alarm 0 Interrupt Enable */
+#define RTC_MODE2_INTENCLR_ALARM0 (1 << RTC_MODE2_INTENCLR_ALARM0_Pos)
+#define RTC_MODE2_INTENCLR_ALARM_Pos 0 /**< \brief (RTC_MODE2_INTENCLR) Alarm x Interrupt Enable */
+#define RTC_MODE2_INTENCLR_ALARM_Msk (0x1ul << RTC_MODE2_INTENCLR_ALARM_Pos)
+#define RTC_MODE2_INTENCLR_ALARM(value) (RTC_MODE2_INTENCLR_ALARM_Msk & ((value) << RTC_MODE2_INTENCLR_ALARM_Pos))
+#define RTC_MODE2_INTENCLR_SYNCRDY_Pos 6 /**< \brief (RTC_MODE2_INTENCLR) Synchronization Ready Interrupt Enable */
+#define RTC_MODE2_INTENCLR_SYNCRDY (0x1ul << RTC_MODE2_INTENCLR_SYNCRDY_Pos)
+#define RTC_MODE2_INTENCLR_OVF_Pos 7 /**< \brief (RTC_MODE2_INTENCLR) Overflow Interrupt Enable */
+#define RTC_MODE2_INTENCLR_OVF (0x1ul << RTC_MODE2_INTENCLR_OVF_Pos)
+#define RTC_MODE2_INTENCLR_MASK 0xC1ul /**< \brief (RTC_MODE2_INTENCLR) MASK Register */
+
+/* -------- RTC_MODE0_INTENSET : (RTC Offset: 0x07) (R/W 8) MODE0 MODE0 Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
+ uint8_t :5; /*!< bit: 1.. 5 Reserved */
+ uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
+ uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t CMP:1; /*!< bit: 0 Compare x Interrupt Enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} RTC_MODE0_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE0_INTENSET_OFFSET 0x07 /**< \brief (RTC_MODE0_INTENSET offset) MODE0 Interrupt Enable Set */
+#define RTC_MODE0_INTENSET_RESETVALUE 0x00ul /**< \brief (RTC_MODE0_INTENSET reset_value) MODE0 Interrupt Enable Set */
+
+#define RTC_MODE0_INTENSET_CMP0_Pos 0 /**< \brief (RTC_MODE0_INTENSET) Compare 0 Interrupt Enable */
+#define RTC_MODE0_INTENSET_CMP0 (1 << RTC_MODE0_INTENSET_CMP0_Pos)
+#define RTC_MODE0_INTENSET_CMP_Pos 0 /**< \brief (RTC_MODE0_INTENSET) Compare x Interrupt Enable */
+#define RTC_MODE0_INTENSET_CMP_Msk (0x1ul << RTC_MODE0_INTENSET_CMP_Pos)
+#define RTC_MODE0_INTENSET_CMP(value) (RTC_MODE0_INTENSET_CMP_Msk & ((value) << RTC_MODE0_INTENSET_CMP_Pos))
+#define RTC_MODE0_INTENSET_SYNCRDY_Pos 6 /**< \brief (RTC_MODE0_INTENSET) Synchronization Ready Interrupt Enable */
+#define RTC_MODE0_INTENSET_SYNCRDY (0x1ul << RTC_MODE0_INTENSET_SYNCRDY_Pos)
+#define RTC_MODE0_INTENSET_OVF_Pos 7 /**< \brief (RTC_MODE0_INTENSET) Overflow Interrupt Enable */
+#define RTC_MODE0_INTENSET_OVF (0x1ul << RTC_MODE0_INTENSET_OVF_Pos)
+#define RTC_MODE0_INTENSET_MASK 0xC1ul /**< \brief (RTC_MODE0_INTENSET) MASK Register */
+
+/* -------- RTC_MODE1_INTENSET : (RTC Offset: 0x07) (R/W 8) MODE1 MODE1 Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
+ uint8_t CMP1:1; /*!< bit: 1 Compare 1 Interrupt Enable */
+ uint8_t :4; /*!< bit: 2.. 5 Reserved */
+ uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
+ uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t CMP:2; /*!< bit: 0.. 1 Compare x Interrupt Enable */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} RTC_MODE1_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_INTENSET_OFFSET 0x07 /**< \brief (RTC_MODE1_INTENSET offset) MODE1 Interrupt Enable Set */
+#define RTC_MODE1_INTENSET_RESETVALUE 0x00ul /**< \brief (RTC_MODE1_INTENSET reset_value) MODE1 Interrupt Enable Set */
+
+#define RTC_MODE1_INTENSET_CMP0_Pos 0 /**< \brief (RTC_MODE1_INTENSET) Compare 0 Interrupt Enable */
+#define RTC_MODE1_INTENSET_CMP0 (1 << RTC_MODE1_INTENSET_CMP0_Pos)
+#define RTC_MODE1_INTENSET_CMP1_Pos 1 /**< \brief (RTC_MODE1_INTENSET) Compare 1 Interrupt Enable */
+#define RTC_MODE1_INTENSET_CMP1 (1 << RTC_MODE1_INTENSET_CMP1_Pos)
+#define RTC_MODE1_INTENSET_CMP_Pos 0 /**< \brief (RTC_MODE1_INTENSET) Compare x Interrupt Enable */
+#define RTC_MODE1_INTENSET_CMP_Msk (0x3ul << RTC_MODE1_INTENSET_CMP_Pos)
+#define RTC_MODE1_INTENSET_CMP(value) (RTC_MODE1_INTENSET_CMP_Msk & ((value) << RTC_MODE1_INTENSET_CMP_Pos))
+#define RTC_MODE1_INTENSET_SYNCRDY_Pos 6 /**< \brief (RTC_MODE1_INTENSET) Synchronization Ready Interrupt Enable */
+#define RTC_MODE1_INTENSET_SYNCRDY (0x1ul << RTC_MODE1_INTENSET_SYNCRDY_Pos)
+#define RTC_MODE1_INTENSET_OVF_Pos 7 /**< \brief (RTC_MODE1_INTENSET) Overflow Interrupt Enable */
+#define RTC_MODE1_INTENSET_OVF (0x1ul << RTC_MODE1_INTENSET_OVF_Pos)
+#define RTC_MODE1_INTENSET_MASK 0xC3ul /**< \brief (RTC_MODE1_INTENSET) MASK Register */
+
+/* -------- RTC_MODE2_INTENSET : (RTC Offset: 0x07) (R/W 8) MODE2 MODE2 Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 Interrupt Enable */
+ uint8_t :5; /*!< bit: 1.. 5 Reserved */
+ uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
+ uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t ALARM:1; /*!< bit: 0 Alarm x Interrupt Enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} RTC_MODE2_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_INTENSET_OFFSET 0x07 /**< \brief (RTC_MODE2_INTENSET offset) MODE2 Interrupt Enable Set */
+#define RTC_MODE2_INTENSET_RESETVALUE 0x00ul /**< \brief (RTC_MODE2_INTENSET reset_value) MODE2 Interrupt Enable Set */
+
+#define RTC_MODE2_INTENSET_ALARM0_Pos 0 /**< \brief (RTC_MODE2_INTENSET) Alarm 0 Interrupt Enable */
+#define RTC_MODE2_INTENSET_ALARM0 (1 << RTC_MODE2_INTENSET_ALARM0_Pos)
+#define RTC_MODE2_INTENSET_ALARM_Pos 0 /**< \brief (RTC_MODE2_INTENSET) Alarm x Interrupt Enable */
+#define RTC_MODE2_INTENSET_ALARM_Msk (0x1ul << RTC_MODE2_INTENSET_ALARM_Pos)
+#define RTC_MODE2_INTENSET_ALARM(value) (RTC_MODE2_INTENSET_ALARM_Msk & ((value) << RTC_MODE2_INTENSET_ALARM_Pos))
+#define RTC_MODE2_INTENSET_SYNCRDY_Pos 6 /**< \brief (RTC_MODE2_INTENSET) Synchronization Ready Interrupt Enable */
+#define RTC_MODE2_INTENSET_SYNCRDY (0x1ul << RTC_MODE2_INTENSET_SYNCRDY_Pos)
+#define RTC_MODE2_INTENSET_OVF_Pos 7 /**< \brief (RTC_MODE2_INTENSET) Overflow Interrupt Enable */
+#define RTC_MODE2_INTENSET_OVF (0x1ul << RTC_MODE2_INTENSET_OVF_Pos)
+#define RTC_MODE2_INTENSET_MASK 0xC1ul /**< \brief (RTC_MODE2_INTENSET) MASK Register */
+
+/* -------- RTC_MODE0_INTFLAG : (RTC Offset: 0x08) (R/W 8) MODE0 MODE0 Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint8_t CMP0:1; /*!< bit: 0 Compare 0 */
+ __I uint8_t :5; /*!< bit: 1.. 5 Reserved */
+ __I uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */
+ __I uint8_t OVF:1; /*!< bit: 7 Overflow */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ __I uint8_t CMP:1; /*!< bit: 0 Compare x */
+ __I uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} RTC_MODE0_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE0_INTFLAG_OFFSET 0x08 /**< \brief (RTC_MODE0_INTFLAG offset) MODE0 Interrupt Flag Status and Clear */
+#define RTC_MODE0_INTFLAG_RESETVALUE 0x00ul /**< \brief (RTC_MODE0_INTFLAG reset_value) MODE0 Interrupt Flag Status and Clear */
+
+#define RTC_MODE0_INTFLAG_CMP0_Pos 0 /**< \brief (RTC_MODE0_INTFLAG) Compare 0 */
+#define RTC_MODE0_INTFLAG_CMP0 (1 << RTC_MODE0_INTFLAG_CMP0_Pos)
+#define RTC_MODE0_INTFLAG_CMP_Pos 0 /**< \brief (RTC_MODE0_INTFLAG) Compare x */
+#define RTC_MODE0_INTFLAG_CMP_Msk (0x1ul << RTC_MODE0_INTFLAG_CMP_Pos)
+#define RTC_MODE0_INTFLAG_CMP(value) (RTC_MODE0_INTFLAG_CMP_Msk & ((value) << RTC_MODE0_INTFLAG_CMP_Pos))
+#define RTC_MODE0_INTFLAG_SYNCRDY_Pos 6 /**< \brief (RTC_MODE0_INTFLAG) Synchronization Ready */
+#define RTC_MODE0_INTFLAG_SYNCRDY (0x1ul << RTC_MODE0_INTFLAG_SYNCRDY_Pos)
+#define RTC_MODE0_INTFLAG_OVF_Pos 7 /**< \brief (RTC_MODE0_INTFLAG) Overflow */
+#define RTC_MODE0_INTFLAG_OVF (0x1ul << RTC_MODE0_INTFLAG_OVF_Pos)
+#define RTC_MODE0_INTFLAG_MASK 0xC1ul /**< \brief (RTC_MODE0_INTFLAG) MASK Register */
+
+/* -------- RTC_MODE1_INTFLAG : (RTC Offset: 0x08) (R/W 8) MODE1 MODE1 Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint8_t CMP0:1; /*!< bit: 0 Compare 0 */
+ __I uint8_t CMP1:1; /*!< bit: 1 Compare 1 */
+ __I uint8_t :4; /*!< bit: 2.. 5 Reserved */
+ __I uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */
+ __I uint8_t OVF:1; /*!< bit: 7 Overflow */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ __I uint8_t CMP:2; /*!< bit: 0.. 1 Compare x */
+ __I uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} RTC_MODE1_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_INTFLAG_OFFSET 0x08 /**< \brief (RTC_MODE1_INTFLAG offset) MODE1 Interrupt Flag Status and Clear */
+#define RTC_MODE1_INTFLAG_RESETVALUE 0x00ul /**< \brief (RTC_MODE1_INTFLAG reset_value) MODE1 Interrupt Flag Status and Clear */
+
+#define RTC_MODE1_INTFLAG_CMP0_Pos 0 /**< \brief (RTC_MODE1_INTFLAG) Compare 0 */
+#define RTC_MODE1_INTFLAG_CMP0 (1 << RTC_MODE1_INTFLAG_CMP0_Pos)
+#define RTC_MODE1_INTFLAG_CMP1_Pos 1 /**< \brief (RTC_MODE1_INTFLAG) Compare 1 */
+#define RTC_MODE1_INTFLAG_CMP1 (1 << RTC_MODE1_INTFLAG_CMP1_Pos)
+#define RTC_MODE1_INTFLAG_CMP_Pos 0 /**< \brief (RTC_MODE1_INTFLAG) Compare x */
+#define RTC_MODE1_INTFLAG_CMP_Msk (0x3ul << RTC_MODE1_INTFLAG_CMP_Pos)
+#define RTC_MODE1_INTFLAG_CMP(value) (RTC_MODE1_INTFLAG_CMP_Msk & ((value) << RTC_MODE1_INTFLAG_CMP_Pos))
+#define RTC_MODE1_INTFLAG_SYNCRDY_Pos 6 /**< \brief (RTC_MODE1_INTFLAG) Synchronization Ready */
+#define RTC_MODE1_INTFLAG_SYNCRDY (0x1ul << RTC_MODE1_INTFLAG_SYNCRDY_Pos)
+#define RTC_MODE1_INTFLAG_OVF_Pos 7 /**< \brief (RTC_MODE1_INTFLAG) Overflow */
+#define RTC_MODE1_INTFLAG_OVF (0x1ul << RTC_MODE1_INTFLAG_OVF_Pos)
+#define RTC_MODE1_INTFLAG_MASK 0xC3ul /**< \brief (RTC_MODE1_INTFLAG) MASK Register */
+
+/* -------- RTC_MODE2_INTFLAG : (RTC Offset: 0x08) (R/W 8) MODE2 MODE2 Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 */
+ __I uint8_t :5; /*!< bit: 1.. 5 Reserved */
+ __I uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */
+ __I uint8_t OVF:1; /*!< bit: 7 Overflow */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ __I uint8_t ALARM:1; /*!< bit: 0 Alarm x */
+ __I uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} RTC_MODE2_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_INTFLAG_OFFSET 0x08 /**< \brief (RTC_MODE2_INTFLAG offset) MODE2 Interrupt Flag Status and Clear */
+#define RTC_MODE2_INTFLAG_RESETVALUE 0x00ul /**< \brief (RTC_MODE2_INTFLAG reset_value) MODE2 Interrupt Flag Status and Clear */
+
+#define RTC_MODE2_INTFLAG_ALARM0_Pos 0 /**< \brief (RTC_MODE2_INTFLAG) Alarm 0 */
+#define RTC_MODE2_INTFLAG_ALARM0 (1 << RTC_MODE2_INTFLAG_ALARM0_Pos)
+#define RTC_MODE2_INTFLAG_ALARM_Pos 0 /**< \brief (RTC_MODE2_INTFLAG) Alarm x */
+#define RTC_MODE2_INTFLAG_ALARM_Msk (0x1ul << RTC_MODE2_INTFLAG_ALARM_Pos)
+#define RTC_MODE2_INTFLAG_ALARM(value) (RTC_MODE2_INTFLAG_ALARM_Msk & ((value) << RTC_MODE2_INTFLAG_ALARM_Pos))
+#define RTC_MODE2_INTFLAG_SYNCRDY_Pos 6 /**< \brief (RTC_MODE2_INTFLAG) Synchronization Ready */
+#define RTC_MODE2_INTFLAG_SYNCRDY (0x1ul << RTC_MODE2_INTFLAG_SYNCRDY_Pos)
+#define RTC_MODE2_INTFLAG_OVF_Pos 7 /**< \brief (RTC_MODE2_INTFLAG) Overflow */
+#define RTC_MODE2_INTFLAG_OVF (0x1ul << RTC_MODE2_INTFLAG_OVF_Pos)
+#define RTC_MODE2_INTFLAG_MASK 0xC1ul /**< \brief (RTC_MODE2_INTFLAG) MASK Register */
+
+/* -------- RTC_STATUS : (RTC Offset: 0x0A) (R/W 8) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t :7; /*!< bit: 0.. 6 Reserved */
+ uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} RTC_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_STATUS_OFFSET 0x0A /**< \brief (RTC_STATUS offset) Status */
+#define RTC_STATUS_RESETVALUE 0x00ul /**< \brief (RTC_STATUS reset_value) Status */
+
+#define RTC_STATUS_SYNCBUSY_Pos 7 /**< \brief (RTC_STATUS) Synchronization Busy */
+#define RTC_STATUS_SYNCBUSY (0x1ul << RTC_STATUS_SYNCBUSY_Pos)
+#define RTC_STATUS_MASK 0x80ul /**< \brief (RTC_STATUS) MASK Register */
+
+/* -------- RTC_DBGCTRL : (RTC Offset: 0x0B) (R/W 8) Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DBGRUN:1; /*!< bit: 0 Run During Debug */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} RTC_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_DBGCTRL_OFFSET 0x0B /**< \brief (RTC_DBGCTRL offset) Debug Control */
+#define RTC_DBGCTRL_RESETVALUE 0x00ul /**< \brief (RTC_DBGCTRL reset_value) Debug Control */
+
+#define RTC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (RTC_DBGCTRL) Run During Debug */
+#define RTC_DBGCTRL_DBGRUN (0x1ul << RTC_DBGCTRL_DBGRUN_Pos)
+#define RTC_DBGCTRL_MASK 0x01ul /**< \brief (RTC_DBGCTRL) MASK Register */
+
+/* -------- RTC_FREQCORR : (RTC Offset: 0x0C) (R/W 8) Frequency Correction -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t VALUE:7; /*!< bit: 0.. 6 Correction Value */
+ uint8_t SIGN:1; /*!< bit: 7 Correction Sign */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} RTC_FREQCORR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_FREQCORR_OFFSET 0x0C /**< \brief (RTC_FREQCORR offset) Frequency Correction */
+#define RTC_FREQCORR_RESETVALUE 0x00ul /**< \brief (RTC_FREQCORR reset_value) Frequency Correction */
+
+#define RTC_FREQCORR_VALUE_Pos 0 /**< \brief (RTC_FREQCORR) Correction Value */
+#define RTC_FREQCORR_VALUE_Msk (0x7Ful << RTC_FREQCORR_VALUE_Pos)
+#define RTC_FREQCORR_VALUE(value) (RTC_FREQCORR_VALUE_Msk & ((value) << RTC_FREQCORR_VALUE_Pos))
+#define RTC_FREQCORR_SIGN_Pos 7 /**< \brief (RTC_FREQCORR) Correction Sign */
+#define RTC_FREQCORR_SIGN (0x1ul << RTC_FREQCORR_SIGN_Pos)
+#define RTC_FREQCORR_MASK 0xFFul /**< \brief (RTC_FREQCORR) MASK Register */
+
+/* -------- RTC_MODE0_COUNT : (RTC Offset: 0x10) (R/W 32) MODE0 MODE0 Counter Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t COUNT:32; /*!< bit: 0..31 Counter Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} RTC_MODE0_COUNT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE0_COUNT_OFFSET 0x10 /**< \brief (RTC_MODE0_COUNT offset) MODE0 Counter Value */
+#define RTC_MODE0_COUNT_RESETVALUE 0x00000000ul /**< \brief (RTC_MODE0_COUNT reset_value) MODE0 Counter Value */
+
+#define RTC_MODE0_COUNT_COUNT_Pos 0 /**< \brief (RTC_MODE0_COUNT) Counter Value */
+#define RTC_MODE0_COUNT_COUNT_Msk (0xFFFFFFFFul << RTC_MODE0_COUNT_COUNT_Pos)
+#define RTC_MODE0_COUNT_COUNT(value) (RTC_MODE0_COUNT_COUNT_Msk & ((value) << RTC_MODE0_COUNT_COUNT_Pos))
+#define RTC_MODE0_COUNT_MASK 0xFFFFFFFFul /**< \brief (RTC_MODE0_COUNT) MASK Register */
+
+/* -------- RTC_MODE1_COUNT : (RTC Offset: 0x10) (R/W 16) MODE1 MODE1 Counter Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t COUNT:16; /*!< bit: 0..15 Counter Value */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} RTC_MODE1_COUNT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_COUNT_OFFSET 0x10 /**< \brief (RTC_MODE1_COUNT offset) MODE1 Counter Value */
+#define RTC_MODE1_COUNT_RESETVALUE 0x0000ul /**< \brief (RTC_MODE1_COUNT reset_value) MODE1 Counter Value */
+
+#define RTC_MODE1_COUNT_COUNT_Pos 0 /**< \brief (RTC_MODE1_COUNT) Counter Value */
+#define RTC_MODE1_COUNT_COUNT_Msk (0xFFFFul << RTC_MODE1_COUNT_COUNT_Pos)
+#define RTC_MODE1_COUNT_COUNT(value) (RTC_MODE1_COUNT_COUNT_Msk & ((value) << RTC_MODE1_COUNT_COUNT_Pos))
+#define RTC_MODE1_COUNT_MASK 0xFFFFul /**< \brief (RTC_MODE1_COUNT) MASK Register */
+
+/* -------- RTC_MODE2_CLOCK : (RTC Offset: 0x10) (R/W 32) MODE2 MODE2 Clock Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SECOND:6; /*!< bit: 0.. 5 Second */
+ uint32_t MINUTE:6; /*!< bit: 6..11 Minute */
+ uint32_t HOUR:5; /*!< bit: 12..16 Hour */
+ uint32_t DAY:5; /*!< bit: 17..21 Day */
+ uint32_t MONTH:4; /*!< bit: 22..25 Month */
+ uint32_t YEAR:6; /*!< bit: 26..31 Year */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} RTC_MODE2_CLOCK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_CLOCK_OFFSET 0x10 /**< \brief (RTC_MODE2_CLOCK offset) MODE2 Clock Value */
+#define RTC_MODE2_CLOCK_RESETVALUE 0x00000000ul /**< \brief (RTC_MODE2_CLOCK reset_value) MODE2 Clock Value */
+
+#define RTC_MODE2_CLOCK_SECOND_Pos 0 /**< \brief (RTC_MODE2_CLOCK) Second */
+#define RTC_MODE2_CLOCK_SECOND_Msk (0x3Ful << RTC_MODE2_CLOCK_SECOND_Pos)
+#define RTC_MODE2_CLOCK_SECOND(value) (RTC_MODE2_CLOCK_SECOND_Msk & ((value) << RTC_MODE2_CLOCK_SECOND_Pos))
+#define RTC_MODE2_CLOCK_MINUTE_Pos 6 /**< \brief (RTC_MODE2_CLOCK) Minute */
+#define RTC_MODE2_CLOCK_MINUTE_Msk (0x3Ful << RTC_MODE2_CLOCK_MINUTE_Pos)
+#define RTC_MODE2_CLOCK_MINUTE(value) (RTC_MODE2_CLOCK_MINUTE_Msk & ((value) << RTC_MODE2_CLOCK_MINUTE_Pos))
+#define RTC_MODE2_CLOCK_HOUR_Pos 12 /**< \brief (RTC_MODE2_CLOCK) Hour */
+#define RTC_MODE2_CLOCK_HOUR_Msk (0x1Ful << RTC_MODE2_CLOCK_HOUR_Pos)
+#define RTC_MODE2_CLOCK_HOUR(value) (RTC_MODE2_CLOCK_HOUR_Msk & ((value) << RTC_MODE2_CLOCK_HOUR_Pos))
+#define RTC_MODE2_CLOCK_HOUR_PM_Val 0x10ul /**< \brief (RTC_MODE2_CLOCK) Afternoon Hour */
+#define RTC_MODE2_CLOCK_HOUR_PM (RTC_MODE2_CLOCK_HOUR_PM_Val << RTC_MODE2_CLOCK_HOUR_Pos)
+#define RTC_MODE2_CLOCK_DAY_Pos 17 /**< \brief (RTC_MODE2_CLOCK) Day */
+#define RTC_MODE2_CLOCK_DAY_Msk (0x1Ful << RTC_MODE2_CLOCK_DAY_Pos)
+#define RTC_MODE2_CLOCK_DAY(value) (RTC_MODE2_CLOCK_DAY_Msk & ((value) << RTC_MODE2_CLOCK_DAY_Pos))
+#define RTC_MODE2_CLOCK_MONTH_Pos 22 /**< \brief (RTC_MODE2_CLOCK) Month */
+#define RTC_MODE2_CLOCK_MONTH_Msk (0xFul << RTC_MODE2_CLOCK_MONTH_Pos)
+#define RTC_MODE2_CLOCK_MONTH(value) (RTC_MODE2_CLOCK_MONTH_Msk & ((value) << RTC_MODE2_CLOCK_MONTH_Pos))
+#define RTC_MODE2_CLOCK_YEAR_Pos 26 /**< \brief (RTC_MODE2_CLOCK) Year */
+#define RTC_MODE2_CLOCK_YEAR_Msk (0x3Ful << RTC_MODE2_CLOCK_YEAR_Pos)
+#define RTC_MODE2_CLOCK_YEAR(value) (RTC_MODE2_CLOCK_YEAR_Msk & ((value) << RTC_MODE2_CLOCK_YEAR_Pos))
+#define RTC_MODE2_CLOCK_MASK 0xFFFFFFFFul /**< \brief (RTC_MODE2_CLOCK) MASK Register */
+
+/* -------- RTC_MODE1_PER : (RTC Offset: 0x14) (R/W 16) MODE1 MODE1 Counter Period -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t PER:16; /*!< bit: 0..15 Counter Period */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} RTC_MODE1_PER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_PER_OFFSET 0x14 /**< \brief (RTC_MODE1_PER offset) MODE1 Counter Period */
+#define RTC_MODE1_PER_RESETVALUE 0x0000ul /**< \brief (RTC_MODE1_PER reset_value) MODE1 Counter Period */
+
+#define RTC_MODE1_PER_PER_Pos 0 /**< \brief (RTC_MODE1_PER) Counter Period */
+#define RTC_MODE1_PER_PER_Msk (0xFFFFul << RTC_MODE1_PER_PER_Pos)
+#define RTC_MODE1_PER_PER(value) (RTC_MODE1_PER_PER_Msk & ((value) << RTC_MODE1_PER_PER_Pos))
+#define RTC_MODE1_PER_MASK 0xFFFFul /**< \brief (RTC_MODE1_PER) MASK Register */
+
+/* -------- RTC_MODE0_COMP : (RTC Offset: 0x18) (R/W 32) MODE0 MODE0 Compare n Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t COMP:32; /*!< bit: 0..31 Compare Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} RTC_MODE0_COMP_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE0_COMP_OFFSET 0x18 /**< \brief (RTC_MODE0_COMP offset) MODE0 Compare n Value */
+#define RTC_MODE0_COMP_RESETVALUE 0x00000000ul /**< \brief (RTC_MODE0_COMP reset_value) MODE0 Compare n Value */
+
+#define RTC_MODE0_COMP_COMP_Pos 0 /**< \brief (RTC_MODE0_COMP) Compare Value */
+#define RTC_MODE0_COMP_COMP_Msk (0xFFFFFFFFul << RTC_MODE0_COMP_COMP_Pos)
+#define RTC_MODE0_COMP_COMP(value) (RTC_MODE0_COMP_COMP_Msk & ((value) << RTC_MODE0_COMP_COMP_Pos))
+#define RTC_MODE0_COMP_MASK 0xFFFFFFFFul /**< \brief (RTC_MODE0_COMP) MASK Register */
+
+/* -------- RTC_MODE1_COMP : (RTC Offset: 0x18) (R/W 16) MODE1 MODE1 Compare n Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t COMP:16; /*!< bit: 0..15 Compare Value */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} RTC_MODE1_COMP_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE1_COMP_OFFSET 0x18 /**< \brief (RTC_MODE1_COMP offset) MODE1 Compare n Value */
+#define RTC_MODE1_COMP_RESETVALUE 0x0000ul /**< \brief (RTC_MODE1_COMP reset_value) MODE1 Compare n Value */
+
+#define RTC_MODE1_COMP_COMP_Pos 0 /**< \brief (RTC_MODE1_COMP) Compare Value */
+#define RTC_MODE1_COMP_COMP_Msk (0xFFFFul << RTC_MODE1_COMP_COMP_Pos)
+#define RTC_MODE1_COMP_COMP(value) (RTC_MODE1_COMP_COMP_Msk & ((value) << RTC_MODE1_COMP_COMP_Pos))
+#define RTC_MODE1_COMP_MASK 0xFFFFul /**< \brief (RTC_MODE1_COMP) MASK Register */
+
+/* -------- RTC_MODE2_ALARM : (RTC Offset: 0x18) (R/W 32) MODE2 MODE2_ALARM Alarm n Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SECOND:6; /*!< bit: 0.. 5 Second */
+ uint32_t MINUTE:6; /*!< bit: 6..11 Minute */
+ uint32_t HOUR:5; /*!< bit: 12..16 Hour */
+ uint32_t DAY:5; /*!< bit: 17..21 Day */
+ uint32_t MONTH:4; /*!< bit: 22..25 Month */
+ uint32_t YEAR:6; /*!< bit: 26..31 Year */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} RTC_MODE2_ALARM_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_ALARM_OFFSET 0x18 /**< \brief (RTC_MODE2_ALARM offset) MODE2_ALARM Alarm n Value */
+#define RTC_MODE2_ALARM_RESETVALUE 0x00000000ul /**< \brief (RTC_MODE2_ALARM reset_value) MODE2_ALARM Alarm n Value */
+
+#define RTC_MODE2_ALARM_SECOND_Pos 0 /**< \brief (RTC_MODE2_ALARM) Second */
+#define RTC_MODE2_ALARM_SECOND_Msk (0x3Ful << RTC_MODE2_ALARM_SECOND_Pos)
+#define RTC_MODE2_ALARM_SECOND(value) (RTC_MODE2_ALARM_SECOND_Msk & ((value) << RTC_MODE2_ALARM_SECOND_Pos))
+#define RTC_MODE2_ALARM_MINUTE_Pos 6 /**< \brief (RTC_MODE2_ALARM) Minute */
+#define RTC_MODE2_ALARM_MINUTE_Msk (0x3Ful << RTC_MODE2_ALARM_MINUTE_Pos)
+#define RTC_MODE2_ALARM_MINUTE(value) (RTC_MODE2_ALARM_MINUTE_Msk & ((value) << RTC_MODE2_ALARM_MINUTE_Pos))
+#define RTC_MODE2_ALARM_HOUR_Pos 12 /**< \brief (RTC_MODE2_ALARM) Hour */
+#define RTC_MODE2_ALARM_HOUR_Msk (0x1Ful << RTC_MODE2_ALARM_HOUR_Pos)
+#define RTC_MODE2_ALARM_HOUR(value) (RTC_MODE2_ALARM_HOUR_Msk & ((value) << RTC_MODE2_ALARM_HOUR_Pos))
+#define RTC_MODE2_ALARM_DAY_Pos 17 /**< \brief (RTC_MODE2_ALARM) Day */
+#define RTC_MODE2_ALARM_DAY_Msk (0x1Ful << RTC_MODE2_ALARM_DAY_Pos)
+#define RTC_MODE2_ALARM_DAY(value) (RTC_MODE2_ALARM_DAY_Msk & ((value) << RTC_MODE2_ALARM_DAY_Pos))
+#define RTC_MODE2_ALARM_MONTH_Pos 22 /**< \brief (RTC_MODE2_ALARM) Month */
+#define RTC_MODE2_ALARM_MONTH_Msk (0xFul << RTC_MODE2_ALARM_MONTH_Pos)
+#define RTC_MODE2_ALARM_MONTH(value) (RTC_MODE2_ALARM_MONTH_Msk & ((value) << RTC_MODE2_ALARM_MONTH_Pos))
+#define RTC_MODE2_ALARM_YEAR_Pos 26 /**< \brief (RTC_MODE2_ALARM) Year */
+#define RTC_MODE2_ALARM_YEAR_Msk (0x3Ful << RTC_MODE2_ALARM_YEAR_Pos)
+#define RTC_MODE2_ALARM_YEAR(value) (RTC_MODE2_ALARM_YEAR_Msk & ((value) << RTC_MODE2_ALARM_YEAR_Pos))
+#define RTC_MODE2_ALARM_MASK 0xFFFFFFFFul /**< \brief (RTC_MODE2_ALARM) MASK Register */
+
+/* -------- RTC_MODE2_MASK : (RTC Offset: 0x1C) (R/W 8) MODE2 MODE2_ALARM Alarm n Mask -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SEL:3; /*!< bit: 0.. 2 Alarm Mask Selection */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} RTC_MODE2_MASK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define RTC_MODE2_MASK_OFFSET 0x1C /**< \brief (RTC_MODE2_MASK offset) MODE2_ALARM Alarm n Mask */
+#define RTC_MODE2_MASK_RESETVALUE 0x00ul /**< \brief (RTC_MODE2_MASK reset_value) MODE2_ALARM Alarm n Mask */
+
+#define RTC_MODE2_MASK_SEL_Pos 0 /**< \brief (RTC_MODE2_MASK) Alarm Mask Selection */
+#define RTC_MODE2_MASK_SEL_Msk (0x7ul << RTC_MODE2_MASK_SEL_Pos)
+#define RTC_MODE2_MASK_SEL(value) (RTC_MODE2_MASK_SEL_Msk & ((value) << RTC_MODE2_MASK_SEL_Pos))
+#define RTC_MODE2_MASK_SEL_OFF_Val 0x0ul /**< \brief (RTC_MODE2_MASK) Alarm Disabled */
+#define RTC_MODE2_MASK_SEL_SS_Val 0x1ul /**< \brief (RTC_MODE2_MASK) Match seconds only */
+#define RTC_MODE2_MASK_SEL_MMSS_Val 0x2ul /**< \brief (RTC_MODE2_MASK) Match seconds and minutes only */
+#define RTC_MODE2_MASK_SEL_HHMMSS_Val 0x3ul /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, and hours only */
+#define RTC_MODE2_MASK_SEL_DDHHMMSS_Val 0x4ul /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, hours, and days only */
+#define RTC_MODE2_MASK_SEL_MMDDHHMMSS_Val 0x5ul /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, hours, days, and months only */
+#define RTC_MODE2_MASK_SEL_YYMMDDHHMMSS_Val 0x6ul /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, hours, days, months, and years */
+#define RTC_MODE2_MASK_SEL_OFF (RTC_MODE2_MASK_SEL_OFF_Val << RTC_MODE2_MASK_SEL_Pos)
+#define RTC_MODE2_MASK_SEL_SS (RTC_MODE2_MASK_SEL_SS_Val << RTC_MODE2_MASK_SEL_Pos)
+#define RTC_MODE2_MASK_SEL_MMSS (RTC_MODE2_MASK_SEL_MMSS_Val << RTC_MODE2_MASK_SEL_Pos)
+#define RTC_MODE2_MASK_SEL_HHMMSS (RTC_MODE2_MASK_SEL_HHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)
+#define RTC_MODE2_MASK_SEL_DDHHMMSS (RTC_MODE2_MASK_SEL_DDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)
+#define RTC_MODE2_MASK_SEL_MMDDHHMMSS (RTC_MODE2_MASK_SEL_MMDDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)
+#define RTC_MODE2_MASK_SEL_YYMMDDHHMMSS (RTC_MODE2_MASK_SEL_YYMMDDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos)
+#define RTC_MODE2_MASK_MASK 0x07ul /**< \brief (RTC_MODE2_MASK) MASK Register */
+
+/** \brief RtcMode2Alarm hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO RTC_MODE2_ALARM_Type ALARM; /**< \brief Offset: 0x00 (R/W 32) MODE2_ALARM Alarm n Value */
+ __IO RTC_MODE2_MASK_Type MASK; /**< \brief Offset: 0x04 (R/W 8) MODE2_ALARM Alarm n Mask */
+ RoReg8 Reserved1[0x3];
+} RtcMode2Alarm;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief RTC_MODE0 hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* 32-bit Counter with Single 32-bit Compare */
+ __IO RTC_MODE0_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE0 Control */
+ __IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
+ __IO RTC_MODE0_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE0 Event Control */
+ __IO RTC_MODE0_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE0 Interrupt Enable Clear */
+ __IO RTC_MODE0_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE0 Interrupt Enable Set */
+ __IO RTC_MODE0_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE0 Interrupt Flag Status and Clear */
+ RoReg8 Reserved1[0x1];
+ __IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */
+ __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */
+ __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */
+ RoReg8 Reserved2[0x3];
+ __IO RTC_MODE0_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 32) MODE0 Counter Value */
+ RoReg8 Reserved3[0x4];
+ __IO RTC_MODE0_COMP_Type COMP[1]; /**< \brief Offset: 0x18 (R/W 32) MODE0 Compare n Value */
+} RtcMode0;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief RTC_MODE1 hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* 16-bit Counter with Two 16-bit Compares */
+ __IO RTC_MODE1_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE1 Control */
+ __IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
+ __IO RTC_MODE1_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE1 Event Control */
+ __IO RTC_MODE1_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE1 Interrupt Enable Clear */
+ __IO RTC_MODE1_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE1 Interrupt Enable Set */
+ __IO RTC_MODE1_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE1 Interrupt Flag Status and Clear */
+ RoReg8 Reserved1[0x1];
+ __IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */
+ __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */
+ __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */
+ RoReg8 Reserved2[0x3];
+ __IO RTC_MODE1_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 16) MODE1 Counter Value */
+ RoReg8 Reserved3[0x2];
+ __IO RTC_MODE1_PER_Type PER; /**< \brief Offset: 0x14 (R/W 16) MODE1 Counter Period */
+ RoReg8 Reserved4[0x2];
+ __IO RTC_MODE1_COMP_Type COMP[2]; /**< \brief Offset: 0x18 (R/W 16) MODE1 Compare n Value */
+} RtcMode1;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief RTC_MODE2 hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* Clock/Calendar with Alarm */
+ __IO RTC_MODE2_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE2 Control */
+ __IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
+ __IO RTC_MODE2_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE2 Event Control */
+ __IO RTC_MODE2_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE2 Interrupt Enable Clear */
+ __IO RTC_MODE2_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE2 Interrupt Enable Set */
+ __IO RTC_MODE2_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE2 Interrupt Flag Status and Clear */
+ RoReg8 Reserved1[0x1];
+ __IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */
+ __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */
+ __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */
+ RoReg8 Reserved2[0x3];
+ __IO RTC_MODE2_CLOCK_Type CLOCK; /**< \brief Offset: 0x10 (R/W 32) MODE2 Clock Value */
+ RoReg8 Reserved3[0x4];
+ RtcMode2Alarm Mode2Alarm[1]; /**< \brief Offset: 0x18 RtcMode2Alarm groups [ALARM_NUM] */
+} RtcMode2;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ RtcMode0 MODE0; /**< \brief Offset: 0x00 32-bit Counter with Single 32-bit Compare */
+ RtcMode1 MODE1; /**< \brief Offset: 0x00 16-bit Counter with Two 16-bit Compares */
+ RtcMode2 MODE2; /**< \brief Offset: 0x00 Clock/Calendar with Alarm */
+} Rtc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_RTC_COMPONENT_ */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/component/sercom.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/component/sercom.h
new file mode 100644
index 0000000000000000000000000000000000000000..0ad9d0a803695710ddc9d6e249bbf465d85e4ab1
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/component/sercom.h
@@ -0,0 +1,1508 @@
+/**
+ * \file
+ *
+ * \brief Component description for SERCOM
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_SERCOM_COMPONENT_
+#define _SAMD21_SERCOM_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR SERCOM */
+/* ========================================================================== */
+/** \addtogroup SAMD21_SERCOM Serial Communication Interface */
+/*@{*/
+
+#define SERCOM_U2201
+#define REV_SERCOM 0x200
+
+/* -------- SERCOM_I2CM_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CM I2CM Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable */
+ uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */
+ uint32_t :2; /*!< bit: 5.. 6 Reserved */
+ uint32_t RUNSTDBY:1; /*!< bit: 7 Run in Standby */
+ uint32_t :8; /*!< bit: 8..15 Reserved */
+ uint32_t PINOUT:1; /*!< bit: 16 Pin Usage */
+ uint32_t :3; /*!< bit: 17..19 Reserved */
+ uint32_t SDAHOLD:2; /*!< bit: 20..21 SDA Hold Time */
+ uint32_t MEXTTOEN:1; /*!< bit: 22 Master SCL Low Extend Timeout */
+ uint32_t SEXTTOEN:1; /*!< bit: 23 Slave SCL Low Extend Timeout */
+ uint32_t SPEED:2; /*!< bit: 24..25 Transfer Speed */
+ uint32_t :1; /*!< bit: 26 Reserved */
+ uint32_t SCLSM:1; /*!< bit: 27 SCL Clock Stretch Mode */
+ uint32_t INACTOUT:2; /*!< bit: 28..29 Inactive Time-Out */
+ uint32_t LOWTOUTEN:1; /*!< bit: 30 SCL Low Timeout Enable */
+ uint32_t :1; /*!< bit: 31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_I2CM_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_I2CM_CTRLA offset) I2CM Control A */
+#define SERCOM_I2CM_CTRLA_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CM_CTRLA reset_value) I2CM Control A */
+
+#define SERCOM_I2CM_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_I2CM_CTRLA) Software Reset */
+#define SERCOM_I2CM_CTRLA_SWRST (0x1ul << SERCOM_I2CM_CTRLA_SWRST_Pos)
+#define SERCOM_I2CM_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_I2CM_CTRLA) Enable */
+#define SERCOM_I2CM_CTRLA_ENABLE (0x1ul << SERCOM_I2CM_CTRLA_ENABLE_Pos)
+#define SERCOM_I2CM_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_I2CM_CTRLA) Operating Mode */
+#define SERCOM_I2CM_CTRLA_MODE_Msk (0x7ul << SERCOM_I2CM_CTRLA_MODE_Pos)
+#define SERCOM_I2CM_CTRLA_MODE(value) (SERCOM_I2CM_CTRLA_MODE_Msk & ((value) << SERCOM_I2CM_CTRLA_MODE_Pos))
+#define SERCOM_I2CM_CTRLA_MODE_USART_EXT_CLK_Val 0x0ul /**< \brief (SERCOM_I2CM_CTRLA) USART mode with external clock */
+#define SERCOM_I2CM_CTRLA_MODE_USART_INT_CLK_Val 0x1ul /**< \brief (SERCOM_I2CM_CTRLA) USART mode with internal clock */
+#define SERCOM_I2CM_CTRLA_MODE_SPI_SLAVE_Val 0x2ul /**< \brief (SERCOM_I2CM_CTRLA) SPI mode with external clock */
+#define SERCOM_I2CM_CTRLA_MODE_SPI_MASTER_Val 0x3ul /**< \brief (SERCOM_I2CM_CTRLA) SPI mode with internal clock */
+#define SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE_Val 0x4ul /**< \brief (SERCOM_I2CM_CTRLA) I2C mode with external clock */
+#define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER_Val 0x5ul /**< \brief (SERCOM_I2CM_CTRLA) I2C mode with internal clock */
+#define SERCOM_I2CM_CTRLA_MODE_USART_EXT_CLK (SERCOM_I2CM_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_I2CM_CTRLA_MODE_Pos)
+#define SERCOM_I2CM_CTRLA_MODE_USART_INT_CLK (SERCOM_I2CM_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_I2CM_CTRLA_MODE_Pos)
+#define SERCOM_I2CM_CTRLA_MODE_SPI_SLAVE (SERCOM_I2CM_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_I2CM_CTRLA_MODE_Pos)
+#define SERCOM_I2CM_CTRLA_MODE_SPI_MASTER (SERCOM_I2CM_CTRLA_MODE_SPI_MASTER_Val << SERCOM_I2CM_CTRLA_MODE_Pos)
+#define SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE (SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_I2CM_CTRLA_MODE_Pos)
+#define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER (SERCOM_I2CM_CTRLA_MODE_I2C_MASTER_Val << SERCOM_I2CM_CTRLA_MODE_Pos)
+#define SERCOM_I2CM_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_I2CM_CTRLA) Run in Standby */
+#define SERCOM_I2CM_CTRLA_RUNSTDBY (0x1ul << SERCOM_I2CM_CTRLA_RUNSTDBY_Pos)
+#define SERCOM_I2CM_CTRLA_PINOUT_Pos 16 /**< \brief (SERCOM_I2CM_CTRLA) Pin Usage */
+#define SERCOM_I2CM_CTRLA_PINOUT (0x1ul << SERCOM_I2CM_CTRLA_PINOUT_Pos)
+#define SERCOM_I2CM_CTRLA_SDAHOLD_Pos 20 /**< \brief (SERCOM_I2CM_CTRLA) SDA Hold Time */
+#define SERCOM_I2CM_CTRLA_SDAHOLD_Msk (0x3ul << SERCOM_I2CM_CTRLA_SDAHOLD_Pos)
+#define SERCOM_I2CM_CTRLA_SDAHOLD(value) (SERCOM_I2CM_CTRLA_SDAHOLD_Msk & ((value) << SERCOM_I2CM_CTRLA_SDAHOLD_Pos))
+#define SERCOM_I2CM_CTRLA_MEXTTOEN_Pos 22 /**< \brief (SERCOM_I2CM_CTRLA) Master SCL Low Extend Timeout */
+#define SERCOM_I2CM_CTRLA_MEXTTOEN (0x1ul << SERCOM_I2CM_CTRLA_MEXTTOEN_Pos)
+#define SERCOM_I2CM_CTRLA_SEXTTOEN_Pos 23 /**< \brief (SERCOM_I2CM_CTRLA) Slave SCL Low Extend Timeout */
+#define SERCOM_I2CM_CTRLA_SEXTTOEN (0x1ul << SERCOM_I2CM_CTRLA_SEXTTOEN_Pos)
+#define SERCOM_I2CM_CTRLA_SPEED_Pos 24 /**< \brief (SERCOM_I2CM_CTRLA) Transfer Speed */
+#define SERCOM_I2CM_CTRLA_SPEED_Msk (0x3ul << SERCOM_I2CM_CTRLA_SPEED_Pos)
+#define SERCOM_I2CM_CTRLA_SPEED(value) (SERCOM_I2CM_CTRLA_SPEED_Msk & ((value) << SERCOM_I2CM_CTRLA_SPEED_Pos))
+#define SERCOM_I2CM_CTRLA_SCLSM_Pos 27 /**< \brief (SERCOM_I2CM_CTRLA) SCL Clock Stretch Mode */
+#define SERCOM_I2CM_CTRLA_SCLSM (0x1ul << SERCOM_I2CM_CTRLA_SCLSM_Pos)
+#define SERCOM_I2CM_CTRLA_INACTOUT_Pos 28 /**< \brief (SERCOM_I2CM_CTRLA) Inactive Time-Out */
+#define SERCOM_I2CM_CTRLA_INACTOUT_Msk (0x3ul << SERCOM_I2CM_CTRLA_INACTOUT_Pos)
+#define SERCOM_I2CM_CTRLA_INACTOUT(value) (SERCOM_I2CM_CTRLA_INACTOUT_Msk & ((value) << SERCOM_I2CM_CTRLA_INACTOUT_Pos))
+#define SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos 30 /**< \brief (SERCOM_I2CM_CTRLA) SCL Low Timeout Enable */
+#define SERCOM_I2CM_CTRLA_LOWTOUTEN (0x1ul << SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos)
+#define SERCOM_I2CM_CTRLA_MASK 0x7BF1009Ful /**< \brief (SERCOM_I2CM_CTRLA) MASK Register */
+
+/* -------- SERCOM_I2CS_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CS I2CS Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable */
+ uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */
+ uint32_t :2; /*!< bit: 5.. 6 Reserved */
+ uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */
+ uint32_t :8; /*!< bit: 8..15 Reserved */
+ uint32_t PINOUT:1; /*!< bit: 16 Pin Usage */
+ uint32_t :3; /*!< bit: 17..19 Reserved */
+ uint32_t SDAHOLD:2; /*!< bit: 20..21 SDA Hold Time */
+ uint32_t :1; /*!< bit: 22 Reserved */
+ uint32_t SEXTTOEN:1; /*!< bit: 23 Slave SCL Low Extend Timeout */
+ uint32_t SPEED:2; /*!< bit: 24..25 Transfer Speed */
+ uint32_t :1; /*!< bit: 26 Reserved */
+ uint32_t SCLSM:1; /*!< bit: 27 SCL Clock Stretch Mode */
+ uint32_t :2; /*!< bit: 28..29 Reserved */
+ uint32_t LOWTOUTEN:1; /*!< bit: 30 SCL Low Timeout Enable */
+ uint32_t :1; /*!< bit: 31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_I2CS_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_I2CS_CTRLA offset) I2CS Control A */
+#define SERCOM_I2CS_CTRLA_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CS_CTRLA reset_value) I2CS Control A */
+
+#define SERCOM_I2CS_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_I2CS_CTRLA) Software Reset */
+#define SERCOM_I2CS_CTRLA_SWRST (0x1ul << SERCOM_I2CS_CTRLA_SWRST_Pos)
+#define SERCOM_I2CS_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_I2CS_CTRLA) Enable */
+#define SERCOM_I2CS_CTRLA_ENABLE (0x1ul << SERCOM_I2CS_CTRLA_ENABLE_Pos)
+#define SERCOM_I2CS_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_I2CS_CTRLA) Operating Mode */
+#define SERCOM_I2CS_CTRLA_MODE_Msk (0x7ul << SERCOM_I2CS_CTRLA_MODE_Pos)
+#define SERCOM_I2CS_CTRLA_MODE(value) (SERCOM_I2CS_CTRLA_MODE_Msk & ((value) << SERCOM_I2CS_CTRLA_MODE_Pos))
+#define SERCOM_I2CS_CTRLA_MODE_USART_EXT_CLK_Val 0x0ul /**< \brief (SERCOM_I2CS_CTRLA) USART mode with external clock */
+#define SERCOM_I2CS_CTRLA_MODE_USART_INT_CLK_Val 0x1ul /**< \brief (SERCOM_I2CS_CTRLA) USART mode with internal clock */
+#define SERCOM_I2CS_CTRLA_MODE_SPI_SLAVE_Val 0x2ul /**< \brief (SERCOM_I2CS_CTRLA) SPI mode with external clock */
+#define SERCOM_I2CS_CTRLA_MODE_SPI_MASTER_Val 0x3ul /**< \brief (SERCOM_I2CS_CTRLA) SPI mode with internal clock */
+#define SERCOM_I2CS_CTRLA_MODE_I2C_SLAVE_Val 0x4ul /**< \brief (SERCOM_I2CS_CTRLA) I2C mode with external clock */
+#define SERCOM_I2CS_CTRLA_MODE_I2C_MASTER_Val 0x5ul /**< \brief (SERCOM_I2CS_CTRLA) I2C mode with internal clock */
+#define SERCOM_I2CS_CTRLA_MODE_USART_EXT_CLK (SERCOM_I2CS_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_I2CS_CTRLA_MODE_Pos)
+#define SERCOM_I2CS_CTRLA_MODE_USART_INT_CLK (SERCOM_I2CS_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_I2CS_CTRLA_MODE_Pos)
+#define SERCOM_I2CS_CTRLA_MODE_SPI_SLAVE (SERCOM_I2CS_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_I2CS_CTRLA_MODE_Pos)
+#define SERCOM_I2CS_CTRLA_MODE_SPI_MASTER (SERCOM_I2CS_CTRLA_MODE_SPI_MASTER_Val << SERCOM_I2CS_CTRLA_MODE_Pos)
+#define SERCOM_I2CS_CTRLA_MODE_I2C_SLAVE (SERCOM_I2CS_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_I2CS_CTRLA_MODE_Pos)
+#define SERCOM_I2CS_CTRLA_MODE_I2C_MASTER (SERCOM_I2CS_CTRLA_MODE_I2C_MASTER_Val << SERCOM_I2CS_CTRLA_MODE_Pos)
+#define SERCOM_I2CS_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_I2CS_CTRLA) Run during Standby */
+#define SERCOM_I2CS_CTRLA_RUNSTDBY (0x1ul << SERCOM_I2CS_CTRLA_RUNSTDBY_Pos)
+#define SERCOM_I2CS_CTRLA_PINOUT_Pos 16 /**< \brief (SERCOM_I2CS_CTRLA) Pin Usage */
+#define SERCOM_I2CS_CTRLA_PINOUT (0x1ul << SERCOM_I2CS_CTRLA_PINOUT_Pos)
+#define SERCOM_I2CS_CTRLA_SDAHOLD_Pos 20 /**< \brief (SERCOM_I2CS_CTRLA) SDA Hold Time */
+#define SERCOM_I2CS_CTRLA_SDAHOLD_Msk (0x3ul << SERCOM_I2CS_CTRLA_SDAHOLD_Pos)
+#define SERCOM_I2CS_CTRLA_SDAHOLD(value) (SERCOM_I2CS_CTRLA_SDAHOLD_Msk & ((value) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos))
+#define SERCOM_I2CS_CTRLA_SEXTTOEN_Pos 23 /**< \brief (SERCOM_I2CS_CTRLA) Slave SCL Low Extend Timeout */
+#define SERCOM_I2CS_CTRLA_SEXTTOEN (0x1ul << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos)
+#define SERCOM_I2CS_CTRLA_SPEED_Pos 24 /**< \brief (SERCOM_I2CS_CTRLA) Transfer Speed */
+#define SERCOM_I2CS_CTRLA_SPEED_Msk (0x3ul << SERCOM_I2CS_CTRLA_SPEED_Pos)
+#define SERCOM_I2CS_CTRLA_SPEED(value) (SERCOM_I2CS_CTRLA_SPEED_Msk & ((value) << SERCOM_I2CS_CTRLA_SPEED_Pos))
+#define SERCOM_I2CS_CTRLA_SCLSM_Pos 27 /**< \brief (SERCOM_I2CS_CTRLA) SCL Clock Stretch Mode */
+#define SERCOM_I2CS_CTRLA_SCLSM (0x1ul << SERCOM_I2CS_CTRLA_SCLSM_Pos)
+#define SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos 30 /**< \brief (SERCOM_I2CS_CTRLA) SCL Low Timeout Enable */
+#define SERCOM_I2CS_CTRLA_LOWTOUTEN (0x1ul << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos)
+#define SERCOM_I2CS_CTRLA_MASK 0x4BB1009Ful /**< \brief (SERCOM_I2CS_CTRLA) MASK Register */
+
+/* -------- SERCOM_SPI_CTRLA : (SERCOM Offset: 0x00) (R/W 32) SPI SPI Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable */
+ uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */
+ uint32_t :2; /*!< bit: 5.. 6 Reserved */
+ uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */
+ uint32_t IBON:1; /*!< bit: 8 Immediate Buffer Overflow Notification */
+ uint32_t :7; /*!< bit: 9..15 Reserved */
+ uint32_t DOPO:2; /*!< bit: 16..17 Data Out Pinout */
+ uint32_t :2; /*!< bit: 18..19 Reserved */
+ uint32_t DIPO:2; /*!< bit: 20..21 Data In Pinout */
+ uint32_t :2; /*!< bit: 22..23 Reserved */
+ uint32_t FORM:4; /*!< bit: 24..27 Frame Format */
+ uint32_t CPHA:1; /*!< bit: 28 Clock Phase */
+ uint32_t CPOL:1; /*!< bit: 29 Clock Polarity */
+ uint32_t DORD:1; /*!< bit: 30 Data Order */
+ uint32_t :1; /*!< bit: 31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_SPI_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_SPI_CTRLA offset) SPI Control A */
+#define SERCOM_SPI_CTRLA_RESETVALUE 0x00000000ul /**< \brief (SERCOM_SPI_CTRLA reset_value) SPI Control A */
+
+#define SERCOM_SPI_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_SPI_CTRLA) Software Reset */
+#define SERCOM_SPI_CTRLA_SWRST (0x1ul << SERCOM_SPI_CTRLA_SWRST_Pos)
+#define SERCOM_SPI_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_SPI_CTRLA) Enable */
+#define SERCOM_SPI_CTRLA_ENABLE (0x1ul << SERCOM_SPI_CTRLA_ENABLE_Pos)
+#define SERCOM_SPI_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_SPI_CTRLA) Operating Mode */
+#define SERCOM_SPI_CTRLA_MODE_Msk (0x7ul << SERCOM_SPI_CTRLA_MODE_Pos)
+#define SERCOM_SPI_CTRLA_MODE(value) (SERCOM_SPI_CTRLA_MODE_Msk & ((value) << SERCOM_SPI_CTRLA_MODE_Pos))
+#define SERCOM_SPI_CTRLA_MODE_USART_EXT_CLK_Val 0x0ul /**< \brief (SERCOM_SPI_CTRLA) USART mode with external clock */
+#define SERCOM_SPI_CTRLA_MODE_USART_INT_CLK_Val 0x1ul /**< \brief (SERCOM_SPI_CTRLA) USART mode with internal clock */
+#define SERCOM_SPI_CTRLA_MODE_SPI_SLAVE_Val 0x2ul /**< \brief (SERCOM_SPI_CTRLA) SPI mode with external clock */
+#define SERCOM_SPI_CTRLA_MODE_SPI_MASTER_Val 0x3ul /**< \brief (SERCOM_SPI_CTRLA) SPI mode with internal clock */
+#define SERCOM_SPI_CTRLA_MODE_I2C_SLAVE_Val 0x4ul /**< \brief (SERCOM_SPI_CTRLA) I2C mode with external clock */
+#define SERCOM_SPI_CTRLA_MODE_I2C_MASTER_Val 0x5ul /**< \brief (SERCOM_SPI_CTRLA) I2C mode with internal clock */
+#define SERCOM_SPI_CTRLA_MODE_USART_EXT_CLK (SERCOM_SPI_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_SPI_CTRLA_MODE_Pos)
+#define SERCOM_SPI_CTRLA_MODE_USART_INT_CLK (SERCOM_SPI_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_SPI_CTRLA_MODE_Pos)
+#define SERCOM_SPI_CTRLA_MODE_SPI_SLAVE (SERCOM_SPI_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_SPI_CTRLA_MODE_Pos)
+#define SERCOM_SPI_CTRLA_MODE_SPI_MASTER (SERCOM_SPI_CTRLA_MODE_SPI_MASTER_Val << SERCOM_SPI_CTRLA_MODE_Pos)
+#define SERCOM_SPI_CTRLA_MODE_I2C_SLAVE (SERCOM_SPI_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_SPI_CTRLA_MODE_Pos)
+#define SERCOM_SPI_CTRLA_MODE_I2C_MASTER (SERCOM_SPI_CTRLA_MODE_I2C_MASTER_Val << SERCOM_SPI_CTRLA_MODE_Pos)
+#define SERCOM_SPI_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_SPI_CTRLA) Run during Standby */
+#define SERCOM_SPI_CTRLA_RUNSTDBY (0x1ul << SERCOM_SPI_CTRLA_RUNSTDBY_Pos)
+#define SERCOM_SPI_CTRLA_IBON_Pos 8 /**< \brief (SERCOM_SPI_CTRLA) Immediate Buffer Overflow Notification */
+#define SERCOM_SPI_CTRLA_IBON (0x1ul << SERCOM_SPI_CTRLA_IBON_Pos)
+#define SERCOM_SPI_CTRLA_DOPO_Pos 16 /**< \brief (SERCOM_SPI_CTRLA) Data Out Pinout */
+#define SERCOM_SPI_CTRLA_DOPO_Msk (0x3ul << SERCOM_SPI_CTRLA_DOPO_Pos)
+#define SERCOM_SPI_CTRLA_DOPO(value) (SERCOM_SPI_CTRLA_DOPO_Msk & ((value) << SERCOM_SPI_CTRLA_DOPO_Pos))
+#define SERCOM_SPI_CTRLA_DIPO_Pos 20 /**< \brief (SERCOM_SPI_CTRLA) Data In Pinout */
+#define SERCOM_SPI_CTRLA_DIPO_Msk (0x3ul << SERCOM_SPI_CTRLA_DIPO_Pos)
+#define SERCOM_SPI_CTRLA_DIPO(value) (SERCOM_SPI_CTRLA_DIPO_Msk & ((value) << SERCOM_SPI_CTRLA_DIPO_Pos))
+#define SERCOM_SPI_CTRLA_FORM_Pos 24 /**< \brief (SERCOM_SPI_CTRLA) Frame Format */
+#define SERCOM_SPI_CTRLA_FORM_Msk (0xFul << SERCOM_SPI_CTRLA_FORM_Pos)
+#define SERCOM_SPI_CTRLA_FORM(value) (SERCOM_SPI_CTRLA_FORM_Msk & ((value) << SERCOM_SPI_CTRLA_FORM_Pos))
+#define SERCOM_SPI_CTRLA_CPHA_Pos 28 /**< \brief (SERCOM_SPI_CTRLA) Clock Phase */
+#define SERCOM_SPI_CTRLA_CPHA (0x1ul << SERCOM_SPI_CTRLA_CPHA_Pos)
+#define SERCOM_SPI_CTRLA_CPOL_Pos 29 /**< \brief (SERCOM_SPI_CTRLA) Clock Polarity */
+#define SERCOM_SPI_CTRLA_CPOL (0x1ul << SERCOM_SPI_CTRLA_CPOL_Pos)
+#define SERCOM_SPI_CTRLA_DORD_Pos 30 /**< \brief (SERCOM_SPI_CTRLA) Data Order */
+#define SERCOM_SPI_CTRLA_DORD (0x1ul << SERCOM_SPI_CTRLA_DORD_Pos)
+#define SERCOM_SPI_CTRLA_MASK 0x7F33019Ful /**< \brief (SERCOM_SPI_CTRLA) MASK Register */
+
+/* -------- SERCOM_USART_CTRLA : (SERCOM Offset: 0x00) (R/W 32) USART USART Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable */
+ uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */
+ uint32_t :2; /*!< bit: 5.. 6 Reserved */
+ uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */
+ uint32_t IBON:1; /*!< bit: 8 Immediate Buffer Overflow Notification */
+ uint32_t :4; /*!< bit: 9..12 Reserved */
+ uint32_t SAMPR:3; /*!< bit: 13..15 Sample */
+ uint32_t TXPO:2; /*!< bit: 16..17 Transmit Data Pinout */
+ uint32_t :2; /*!< bit: 18..19 Reserved */
+ uint32_t RXPO:2; /*!< bit: 20..21 Receive Data Pinout */
+ uint32_t SAMPA:2; /*!< bit: 22..23 Sample Adjustment */
+ uint32_t FORM:4; /*!< bit: 24..27 Frame Format */
+ uint32_t CMODE:1; /*!< bit: 28 Communication Mode */
+ uint32_t CPOL:1; /*!< bit: 29 Clock Polarity */
+ uint32_t DORD:1; /*!< bit: 30 Data Order */
+ uint32_t :1; /*!< bit: 31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_USART_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_USART_CTRLA offset) USART Control A */
+#define SERCOM_USART_CTRLA_RESETVALUE 0x00000000ul /**< \brief (SERCOM_USART_CTRLA reset_value) USART Control A */
+
+#define SERCOM_USART_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_USART_CTRLA) Software Reset */
+#define SERCOM_USART_CTRLA_SWRST (0x1ul << SERCOM_USART_CTRLA_SWRST_Pos)
+#define SERCOM_USART_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_USART_CTRLA) Enable */
+#define SERCOM_USART_CTRLA_ENABLE (0x1ul << SERCOM_USART_CTRLA_ENABLE_Pos)
+#define SERCOM_USART_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_USART_CTRLA) Operating Mode */
+#define SERCOM_USART_CTRLA_MODE_Msk (0x7ul << SERCOM_USART_CTRLA_MODE_Pos)
+#define SERCOM_USART_CTRLA_MODE(value) (SERCOM_USART_CTRLA_MODE_Msk & ((value) << SERCOM_USART_CTRLA_MODE_Pos))
+#define SERCOM_USART_CTRLA_MODE_USART_EXT_CLK_Val 0x0ul /**< \brief (SERCOM_USART_CTRLA) USART mode with external clock */
+#define SERCOM_USART_CTRLA_MODE_USART_INT_CLK_Val 0x1ul /**< \brief (SERCOM_USART_CTRLA) USART mode with internal clock */
+#define SERCOM_USART_CTRLA_MODE_SPI_SLAVE_Val 0x2ul /**< \brief (SERCOM_USART_CTRLA) SPI mode with external clock */
+#define SERCOM_USART_CTRLA_MODE_SPI_MASTER_Val 0x3ul /**< \brief (SERCOM_USART_CTRLA) SPI mode with internal clock */
+#define SERCOM_USART_CTRLA_MODE_I2C_SLAVE_Val 0x4ul /**< \brief (SERCOM_USART_CTRLA) I2C mode with external clock */
+#define SERCOM_USART_CTRLA_MODE_I2C_MASTER_Val 0x5ul /**< \brief (SERCOM_USART_CTRLA) I2C mode with internal clock */
+#define SERCOM_USART_CTRLA_MODE_USART_EXT_CLK (SERCOM_USART_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_USART_CTRLA_MODE_Pos)
+#define SERCOM_USART_CTRLA_MODE_USART_INT_CLK (SERCOM_USART_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_USART_CTRLA_MODE_Pos)
+#define SERCOM_USART_CTRLA_MODE_SPI_SLAVE (SERCOM_USART_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_USART_CTRLA_MODE_Pos)
+#define SERCOM_USART_CTRLA_MODE_SPI_MASTER (SERCOM_USART_CTRLA_MODE_SPI_MASTER_Val << SERCOM_USART_CTRLA_MODE_Pos)
+#define SERCOM_USART_CTRLA_MODE_I2C_SLAVE (SERCOM_USART_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_USART_CTRLA_MODE_Pos)
+#define SERCOM_USART_CTRLA_MODE_I2C_MASTER (SERCOM_USART_CTRLA_MODE_I2C_MASTER_Val << SERCOM_USART_CTRLA_MODE_Pos)
+#define SERCOM_USART_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_USART_CTRLA) Run during Standby */
+#define SERCOM_USART_CTRLA_RUNSTDBY (0x1ul << SERCOM_USART_CTRLA_RUNSTDBY_Pos)
+#define SERCOM_USART_CTRLA_IBON_Pos 8 /**< \brief (SERCOM_USART_CTRLA) Immediate Buffer Overflow Notification */
+#define SERCOM_USART_CTRLA_IBON (0x1ul << SERCOM_USART_CTRLA_IBON_Pos)
+#define SERCOM_USART_CTRLA_SAMPR_Pos 13 /**< \brief (SERCOM_USART_CTRLA) Sample */
+#define SERCOM_USART_CTRLA_SAMPR_Msk (0x7ul << SERCOM_USART_CTRLA_SAMPR_Pos)
+#define SERCOM_USART_CTRLA_SAMPR(value) (SERCOM_USART_CTRLA_SAMPR_Msk & ((value) << SERCOM_USART_CTRLA_SAMPR_Pos))
+#define SERCOM_USART_CTRLA_TXPO_Pos 16 /**< \brief (SERCOM_USART_CTRLA) Transmit Data Pinout */
+#define SERCOM_USART_CTRLA_TXPO_Msk (0x3ul << SERCOM_USART_CTRLA_TXPO_Pos)
+#define SERCOM_USART_CTRLA_TXPO(value) (SERCOM_USART_CTRLA_TXPO_Msk & ((value) << SERCOM_USART_CTRLA_TXPO_Pos))
+#define SERCOM_USART_CTRLA_RXPO_Pos 20 /**< \brief (SERCOM_USART_CTRLA) Receive Data Pinout */
+#define SERCOM_USART_CTRLA_RXPO_Msk (0x3ul << SERCOM_USART_CTRLA_RXPO_Pos)
+#define SERCOM_USART_CTRLA_RXPO(value) (SERCOM_USART_CTRLA_RXPO_Msk & ((value) << SERCOM_USART_CTRLA_RXPO_Pos))
+#define SERCOM_USART_CTRLA_SAMPA_Pos 22 /**< \brief (SERCOM_USART_CTRLA) Sample Adjustment */
+#define SERCOM_USART_CTRLA_SAMPA_Msk (0x3ul << SERCOM_USART_CTRLA_SAMPA_Pos)
+#define SERCOM_USART_CTRLA_SAMPA(value) (SERCOM_USART_CTRLA_SAMPA_Msk & ((value) << SERCOM_USART_CTRLA_SAMPA_Pos))
+#define SERCOM_USART_CTRLA_FORM_Pos 24 /**< \brief (SERCOM_USART_CTRLA) Frame Format */
+#define SERCOM_USART_CTRLA_FORM_Msk (0xFul << SERCOM_USART_CTRLA_FORM_Pos)
+#define SERCOM_USART_CTRLA_FORM(value) (SERCOM_USART_CTRLA_FORM_Msk & ((value) << SERCOM_USART_CTRLA_FORM_Pos))
+#define SERCOM_USART_CTRLA_CMODE_Pos 28 /**< \brief (SERCOM_USART_CTRLA) Communication Mode */
+#define SERCOM_USART_CTRLA_CMODE (0x1ul << SERCOM_USART_CTRLA_CMODE_Pos)
+#define SERCOM_USART_CTRLA_CPOL_Pos 29 /**< \brief (SERCOM_USART_CTRLA) Clock Polarity */
+#define SERCOM_USART_CTRLA_CPOL (0x1ul << SERCOM_USART_CTRLA_CPOL_Pos)
+#define SERCOM_USART_CTRLA_DORD_Pos 30 /**< \brief (SERCOM_USART_CTRLA) Data Order */
+#define SERCOM_USART_CTRLA_DORD (0x1ul << SERCOM_USART_CTRLA_DORD_Pos)
+#define SERCOM_USART_CTRLA_MASK 0x7FF3E19Ful /**< \brief (SERCOM_USART_CTRLA) MASK Register */
+
+/* -------- SERCOM_I2CM_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CM I2CM Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :8; /*!< bit: 0.. 7 Reserved */
+ uint32_t SMEN:1; /*!< bit: 8 Smart Mode Enable */
+ uint32_t QCEN:1; /*!< bit: 9 Quick Command Enable */
+ uint32_t :6; /*!< bit: 10..15 Reserved */
+ uint32_t CMD:2; /*!< bit: 16..17 Command */
+ uint32_t ACKACT:1; /*!< bit: 18 Acknowledge Action */
+ uint32_t :13; /*!< bit: 19..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_I2CM_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_I2CM_CTRLB offset) I2CM Control B */
+#define SERCOM_I2CM_CTRLB_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CM_CTRLB reset_value) I2CM Control B */
+
+#define SERCOM_I2CM_CTRLB_SMEN_Pos 8 /**< \brief (SERCOM_I2CM_CTRLB) Smart Mode Enable */
+#define SERCOM_I2CM_CTRLB_SMEN (0x1ul << SERCOM_I2CM_CTRLB_SMEN_Pos)
+#define SERCOM_I2CM_CTRLB_QCEN_Pos 9 /**< \brief (SERCOM_I2CM_CTRLB) Quick Command Enable */
+#define SERCOM_I2CM_CTRLB_QCEN (0x1ul << SERCOM_I2CM_CTRLB_QCEN_Pos)
+#define SERCOM_I2CM_CTRLB_CMD_Pos 16 /**< \brief (SERCOM_I2CM_CTRLB) Command */
+#define SERCOM_I2CM_CTRLB_CMD_Msk (0x3ul << SERCOM_I2CM_CTRLB_CMD_Pos)
+#define SERCOM_I2CM_CTRLB_CMD(value) (SERCOM_I2CM_CTRLB_CMD_Msk & ((value) << SERCOM_I2CM_CTRLB_CMD_Pos))
+#define SERCOM_I2CM_CTRLB_ACKACT_Pos 18 /**< \brief (SERCOM_I2CM_CTRLB) Acknowledge Action */
+#define SERCOM_I2CM_CTRLB_ACKACT (0x1ul << SERCOM_I2CM_CTRLB_ACKACT_Pos)
+#define SERCOM_I2CM_CTRLB_MASK 0x00070300ul /**< \brief (SERCOM_I2CM_CTRLB) MASK Register */
+
+/* -------- SERCOM_I2CS_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CS I2CS Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :8; /*!< bit: 0.. 7 Reserved */
+ uint32_t SMEN:1; /*!< bit: 8 Smart Mode Enable */
+ uint32_t GCMD:1; /*!< bit: 9 PMBus Group Command */
+ uint32_t AACKEN:1; /*!< bit: 10 Automatic Address Acknowledge */
+ uint32_t :3; /*!< bit: 11..13 Reserved */
+ uint32_t AMODE:2; /*!< bit: 14..15 Address Mode */
+ uint32_t CMD:2; /*!< bit: 16..17 Command */
+ uint32_t ACKACT:1; /*!< bit: 18 Acknowledge Action */
+ uint32_t :13; /*!< bit: 19..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_I2CS_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_I2CS_CTRLB offset) I2CS Control B */
+#define SERCOM_I2CS_CTRLB_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CS_CTRLB reset_value) I2CS Control B */
+
+#define SERCOM_I2CS_CTRLB_SMEN_Pos 8 /**< \brief (SERCOM_I2CS_CTRLB) Smart Mode Enable */
+#define SERCOM_I2CS_CTRLB_SMEN (0x1ul << SERCOM_I2CS_CTRLB_SMEN_Pos)
+#define SERCOM_I2CS_CTRLB_GCMD_Pos 9 /**< \brief (SERCOM_I2CS_CTRLB) PMBus Group Command */
+#define SERCOM_I2CS_CTRLB_GCMD (0x1ul << SERCOM_I2CS_CTRLB_GCMD_Pos)
+#define SERCOM_I2CS_CTRLB_AACKEN_Pos 10 /**< \brief (SERCOM_I2CS_CTRLB) Automatic Address Acknowledge */
+#define SERCOM_I2CS_CTRLB_AACKEN (0x1ul << SERCOM_I2CS_CTRLB_AACKEN_Pos)
+#define SERCOM_I2CS_CTRLB_AMODE_Pos 14 /**< \brief (SERCOM_I2CS_CTRLB) Address Mode */
+#define SERCOM_I2CS_CTRLB_AMODE_Msk (0x3ul << SERCOM_I2CS_CTRLB_AMODE_Pos)
+#define SERCOM_I2CS_CTRLB_AMODE(value) (SERCOM_I2CS_CTRLB_AMODE_Msk & ((value) << SERCOM_I2CS_CTRLB_AMODE_Pos))
+#define SERCOM_I2CS_CTRLB_CMD_Pos 16 /**< \brief (SERCOM_I2CS_CTRLB) Command */
+#define SERCOM_I2CS_CTRLB_CMD_Msk (0x3ul << SERCOM_I2CS_CTRLB_CMD_Pos)
+#define SERCOM_I2CS_CTRLB_CMD(value) (SERCOM_I2CS_CTRLB_CMD_Msk & ((value) << SERCOM_I2CS_CTRLB_CMD_Pos))
+#define SERCOM_I2CS_CTRLB_ACKACT_Pos 18 /**< \brief (SERCOM_I2CS_CTRLB) Acknowledge Action */
+#define SERCOM_I2CS_CTRLB_ACKACT (0x1ul << SERCOM_I2CS_CTRLB_ACKACT_Pos)
+#define SERCOM_I2CS_CTRLB_MASK 0x0007C700ul /**< \brief (SERCOM_I2CS_CTRLB) MASK Register */
+
+/* -------- SERCOM_SPI_CTRLB : (SERCOM Offset: 0x04) (R/W 32) SPI SPI Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CHSIZE:3; /*!< bit: 0.. 2 Character Size */
+ uint32_t :3; /*!< bit: 3.. 5 Reserved */
+ uint32_t PLOADEN:1; /*!< bit: 6 Data Preload Enable */
+ uint32_t :2; /*!< bit: 7.. 8 Reserved */
+ uint32_t SSDE:1; /*!< bit: 9 Slave Select Low Detect Enable */
+ uint32_t :3; /*!< bit: 10..12 Reserved */
+ uint32_t MSSEN:1; /*!< bit: 13 Master Slave Select Enable */
+ uint32_t AMODE:2; /*!< bit: 14..15 Address Mode */
+ uint32_t :1; /*!< bit: 16 Reserved */
+ uint32_t RXEN:1; /*!< bit: 17 Receiver Enable */
+ uint32_t :14; /*!< bit: 18..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_SPI_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_SPI_CTRLB offset) SPI Control B */
+#define SERCOM_SPI_CTRLB_RESETVALUE 0x00000000ul /**< \brief (SERCOM_SPI_CTRLB reset_value) SPI Control B */
+
+#define SERCOM_SPI_CTRLB_CHSIZE_Pos 0 /**< \brief (SERCOM_SPI_CTRLB) Character Size */
+#define SERCOM_SPI_CTRLB_CHSIZE_Msk (0x7ul << SERCOM_SPI_CTRLB_CHSIZE_Pos)
+#define SERCOM_SPI_CTRLB_CHSIZE(value) (SERCOM_SPI_CTRLB_CHSIZE_Msk & ((value) << SERCOM_SPI_CTRLB_CHSIZE_Pos))
+#define SERCOM_SPI_CTRLB_PLOADEN_Pos 6 /**< \brief (SERCOM_SPI_CTRLB) Data Preload Enable */
+#define SERCOM_SPI_CTRLB_PLOADEN (0x1ul << SERCOM_SPI_CTRLB_PLOADEN_Pos)
+#define SERCOM_SPI_CTRLB_SSDE_Pos 9 /**< \brief (SERCOM_SPI_CTRLB) Slave Select Low Detect Enable */
+#define SERCOM_SPI_CTRLB_SSDE (0x1ul << SERCOM_SPI_CTRLB_SSDE_Pos)
+#define SERCOM_SPI_CTRLB_MSSEN_Pos 13 /**< \brief (SERCOM_SPI_CTRLB) Master Slave Select Enable */
+#define SERCOM_SPI_CTRLB_MSSEN (0x1ul << SERCOM_SPI_CTRLB_MSSEN_Pos)
+#define SERCOM_SPI_CTRLB_AMODE_Pos 14 /**< \brief (SERCOM_SPI_CTRLB) Address Mode */
+#define SERCOM_SPI_CTRLB_AMODE_Msk (0x3ul << SERCOM_SPI_CTRLB_AMODE_Pos)
+#define SERCOM_SPI_CTRLB_AMODE(value) (SERCOM_SPI_CTRLB_AMODE_Msk & ((value) << SERCOM_SPI_CTRLB_AMODE_Pos))
+#define SERCOM_SPI_CTRLB_RXEN_Pos 17 /**< \brief (SERCOM_SPI_CTRLB) Receiver Enable */
+#define SERCOM_SPI_CTRLB_RXEN (0x1ul << SERCOM_SPI_CTRLB_RXEN_Pos)
+#define SERCOM_SPI_CTRLB_MASK 0x0002E247ul /**< \brief (SERCOM_SPI_CTRLB) MASK Register */
+
+/* -------- SERCOM_USART_CTRLB : (SERCOM Offset: 0x04) (R/W 32) USART USART Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CHSIZE:3; /*!< bit: 0.. 2 Character Size */
+ uint32_t :3; /*!< bit: 3.. 5 Reserved */
+ uint32_t SBMODE:1; /*!< bit: 6 Stop Bit Mode */
+ uint32_t :1; /*!< bit: 7 Reserved */
+ uint32_t COLDEN:1; /*!< bit: 8 Collision Detection Enable */
+ uint32_t SFDE:1; /*!< bit: 9 Start of Frame Detection Enable */
+ uint32_t ENC:1; /*!< bit: 10 Encoding Format */
+ uint32_t :2; /*!< bit: 11..12 Reserved */
+ uint32_t PMODE:1; /*!< bit: 13 Parity Mode */
+ uint32_t :2; /*!< bit: 14..15 Reserved */
+ uint32_t TXEN:1; /*!< bit: 16 Transmitter Enable */
+ uint32_t RXEN:1; /*!< bit: 17 Receiver Enable */
+ uint32_t :14; /*!< bit: 18..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_USART_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_USART_CTRLB offset) USART Control B */
+#define SERCOM_USART_CTRLB_RESETVALUE 0x00000000ul /**< \brief (SERCOM_USART_CTRLB reset_value) USART Control B */
+
+#define SERCOM_USART_CTRLB_CHSIZE_Pos 0 /**< \brief (SERCOM_USART_CTRLB) Character Size */
+#define SERCOM_USART_CTRLB_CHSIZE_Msk (0x7ul << SERCOM_USART_CTRLB_CHSIZE_Pos)
+#define SERCOM_USART_CTRLB_CHSIZE(value) (SERCOM_USART_CTRLB_CHSIZE_Msk & ((value) << SERCOM_USART_CTRLB_CHSIZE_Pos))
+#define SERCOM_USART_CTRLB_SBMODE_Pos 6 /**< \brief (SERCOM_USART_CTRLB) Stop Bit Mode */
+#define SERCOM_USART_CTRLB_SBMODE (0x1ul << SERCOM_USART_CTRLB_SBMODE_Pos)
+#define SERCOM_USART_CTRLB_COLDEN_Pos 8 /**< \brief (SERCOM_USART_CTRLB) Collision Detection Enable */
+#define SERCOM_USART_CTRLB_COLDEN (0x1ul << SERCOM_USART_CTRLB_COLDEN_Pos)
+#define SERCOM_USART_CTRLB_SFDE_Pos 9 /**< \brief (SERCOM_USART_CTRLB) Start of Frame Detection Enable */
+#define SERCOM_USART_CTRLB_SFDE (0x1ul << SERCOM_USART_CTRLB_SFDE_Pos)
+#define SERCOM_USART_CTRLB_ENC_Pos 10 /**< \brief (SERCOM_USART_CTRLB) Encoding Format */
+#define SERCOM_USART_CTRLB_ENC (0x1ul << SERCOM_USART_CTRLB_ENC_Pos)
+#define SERCOM_USART_CTRLB_PMODE_Pos 13 /**< \brief (SERCOM_USART_CTRLB) Parity Mode */
+#define SERCOM_USART_CTRLB_PMODE (0x1ul << SERCOM_USART_CTRLB_PMODE_Pos)
+#define SERCOM_USART_CTRLB_TXEN_Pos 16 /**< \brief (SERCOM_USART_CTRLB) Transmitter Enable */
+#define SERCOM_USART_CTRLB_TXEN (0x1ul << SERCOM_USART_CTRLB_TXEN_Pos)
+#define SERCOM_USART_CTRLB_RXEN_Pos 17 /**< \brief (SERCOM_USART_CTRLB) Receiver Enable */
+#define SERCOM_USART_CTRLB_RXEN (0x1ul << SERCOM_USART_CTRLB_RXEN_Pos)
+#define SERCOM_USART_CTRLB_MASK 0x00032747ul /**< \brief (SERCOM_USART_CTRLB) MASK Register */
+
+/* -------- SERCOM_I2CM_BAUD : (SERCOM Offset: 0x0C) (R/W 32) I2CM I2CM Baud Rate -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t BAUD:8; /*!< bit: 0.. 7 Baud Rate Value */
+ uint32_t BAUDLOW:8; /*!< bit: 8..15 Baud Rate Value Low */
+ uint32_t HSBAUD:8; /*!< bit: 16..23 High Speed Baud Rate Value */
+ uint32_t HSBAUDLOW:8; /*!< bit: 24..31 High Speed Baud Rate Value Low */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_I2CM_BAUD_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_BAUD_OFFSET 0x0C /**< \brief (SERCOM_I2CM_BAUD offset) I2CM Baud Rate */
+#define SERCOM_I2CM_BAUD_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CM_BAUD reset_value) I2CM Baud Rate */
+
+#define SERCOM_I2CM_BAUD_BAUD_Pos 0 /**< \brief (SERCOM_I2CM_BAUD) Baud Rate Value */
+#define SERCOM_I2CM_BAUD_BAUD_Msk (0xFFul << SERCOM_I2CM_BAUD_BAUD_Pos)
+#define SERCOM_I2CM_BAUD_BAUD(value) (SERCOM_I2CM_BAUD_BAUD_Msk & ((value) << SERCOM_I2CM_BAUD_BAUD_Pos))
+#define SERCOM_I2CM_BAUD_BAUDLOW_Pos 8 /**< \brief (SERCOM_I2CM_BAUD) Baud Rate Value Low */
+#define SERCOM_I2CM_BAUD_BAUDLOW_Msk (0xFFul << SERCOM_I2CM_BAUD_BAUDLOW_Pos)
+#define SERCOM_I2CM_BAUD_BAUDLOW(value) (SERCOM_I2CM_BAUD_BAUDLOW_Msk & ((value) << SERCOM_I2CM_BAUD_BAUDLOW_Pos))
+#define SERCOM_I2CM_BAUD_HSBAUD_Pos 16 /**< \brief (SERCOM_I2CM_BAUD) High Speed Baud Rate Value */
+#define SERCOM_I2CM_BAUD_HSBAUD_Msk (0xFFul << SERCOM_I2CM_BAUD_HSBAUD_Pos)
+#define SERCOM_I2CM_BAUD_HSBAUD(value) (SERCOM_I2CM_BAUD_HSBAUD_Msk & ((value) << SERCOM_I2CM_BAUD_HSBAUD_Pos))
+#define SERCOM_I2CM_BAUD_HSBAUDLOW_Pos 24 /**< \brief (SERCOM_I2CM_BAUD) High Speed Baud Rate Value Low */
+#define SERCOM_I2CM_BAUD_HSBAUDLOW_Msk (0xFFul << SERCOM_I2CM_BAUD_HSBAUDLOW_Pos)
+#define SERCOM_I2CM_BAUD_HSBAUDLOW(value) (SERCOM_I2CM_BAUD_HSBAUDLOW_Msk & ((value) << SERCOM_I2CM_BAUD_HSBAUDLOW_Pos))
+#define SERCOM_I2CM_BAUD_MASK 0xFFFFFFFFul /**< \brief (SERCOM_I2CM_BAUD) MASK Register */
+
+/* -------- SERCOM_SPI_BAUD : (SERCOM Offset: 0x0C) (R/W 8) SPI SPI Baud Rate -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t BAUD:8; /*!< bit: 0.. 7 Baud Rate Value */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_SPI_BAUD_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_BAUD_OFFSET 0x0C /**< \brief (SERCOM_SPI_BAUD offset) SPI Baud Rate */
+#define SERCOM_SPI_BAUD_RESETVALUE 0x00ul /**< \brief (SERCOM_SPI_BAUD reset_value) SPI Baud Rate */
+
+#define SERCOM_SPI_BAUD_BAUD_Pos 0 /**< \brief (SERCOM_SPI_BAUD) Baud Rate Value */
+#define SERCOM_SPI_BAUD_BAUD_Msk (0xFFul << SERCOM_SPI_BAUD_BAUD_Pos)
+#define SERCOM_SPI_BAUD_BAUD(value) (SERCOM_SPI_BAUD_BAUD_Msk & ((value) << SERCOM_SPI_BAUD_BAUD_Pos))
+#define SERCOM_SPI_BAUD_MASK 0xFFul /**< \brief (SERCOM_SPI_BAUD) MASK Register */
+
+/* -------- SERCOM_USART_BAUD : (SERCOM Offset: 0x0C) (R/W 16) USART USART Baud Rate -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t BAUD:16; /*!< bit: 0..15 Baud Rate Value */
+ } bit; /*!< Structure used for bit access */
+ struct { // FRAC mode
+ uint16_t BAUD:13; /*!< bit: 0..12 Baud Rate Value */
+ uint16_t FP:3; /*!< bit: 13..15 Fractional Part */
+ } FRAC; /*!< Structure used for FRAC */
+ struct { // FRACFP mode
+ uint16_t BAUD:13; /*!< bit: 0..12 Baud Rate Value */
+ uint16_t FP:3; /*!< bit: 13..15 Fractional Part */
+ } FRACFP; /*!< Structure used for FRACFP */
+ struct { // USARTFP mode
+ uint16_t BAUD:16; /*!< bit: 0..15 Baud Rate Value */
+ } USARTFP; /*!< Structure used for USARTFP */
+ uint16_t reg; /*!< Type used for register access */
+} SERCOM_USART_BAUD_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_BAUD_OFFSET 0x0C /**< \brief (SERCOM_USART_BAUD offset) USART Baud Rate */
+#define SERCOM_USART_BAUD_RESETVALUE 0x0000ul /**< \brief (SERCOM_USART_BAUD reset_value) USART Baud Rate */
+
+#define SERCOM_USART_BAUD_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD) Baud Rate Value */
+#define SERCOM_USART_BAUD_BAUD_Msk (0xFFFFul << SERCOM_USART_BAUD_BAUD_Pos)
+#define SERCOM_USART_BAUD_BAUD(value) (SERCOM_USART_BAUD_BAUD_Msk & ((value) << SERCOM_USART_BAUD_BAUD_Pos))
+#define SERCOM_USART_BAUD_MASK 0xFFFFul /**< \brief (SERCOM_USART_BAUD) MASK Register */
+
+// FRAC mode
+#define SERCOM_USART_BAUD_FRAC_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD_FRAC) Baud Rate Value */
+#define SERCOM_USART_BAUD_FRAC_BAUD_Msk (0x1FFFul << SERCOM_USART_BAUD_FRAC_BAUD_Pos)
+#define SERCOM_USART_BAUD_FRAC_BAUD(value) (SERCOM_USART_BAUD_FRAC_BAUD_Msk & ((value) << SERCOM_USART_BAUD_FRAC_BAUD_Pos))
+#define SERCOM_USART_BAUD_FRAC_FP_Pos 13 /**< \brief (SERCOM_USART_BAUD_FRAC) Fractional Part */
+#define SERCOM_USART_BAUD_FRAC_FP_Msk (0x7ul << SERCOM_USART_BAUD_FRAC_FP_Pos)
+#define SERCOM_USART_BAUD_FRAC_FP(value) (SERCOM_USART_BAUD_FRAC_FP_Msk & ((value) << SERCOM_USART_BAUD_FRAC_FP_Pos))
+#define SERCOM_USART_BAUD_FRAC_MASK 0xFFFFul /**< \brief (SERCOM_USART_BAUD_FRAC) MASK Register */
+
+// FRACFP mode
+#define SERCOM_USART_BAUD_FRACFP_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD_FRACFP) Baud Rate Value */
+#define SERCOM_USART_BAUD_FRACFP_BAUD_Msk (0x1FFFul << SERCOM_USART_BAUD_FRACFP_BAUD_Pos)
+#define SERCOM_USART_BAUD_FRACFP_BAUD(value) (SERCOM_USART_BAUD_FRACFP_BAUD_Msk & ((value) << SERCOM_USART_BAUD_FRACFP_BAUD_Pos))
+#define SERCOM_USART_BAUD_FRACFP_FP_Pos 13 /**< \brief (SERCOM_USART_BAUD_FRACFP) Fractional Part */
+#define SERCOM_USART_BAUD_FRACFP_FP_Msk (0x7ul << SERCOM_USART_BAUD_FRACFP_FP_Pos)
+#define SERCOM_USART_BAUD_FRACFP_FP(value) (SERCOM_USART_BAUD_FRACFP_FP_Msk & ((value) << SERCOM_USART_BAUD_FRACFP_FP_Pos))
+#define SERCOM_USART_BAUD_FRACFP_MASK 0xFFFFul /**< \brief (SERCOM_USART_BAUD_FRACFP) MASK Register */
+
+// USARTFP mode
+#define SERCOM_USART_BAUD_USARTFP_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD_USARTFP) Baud Rate Value */
+#define SERCOM_USART_BAUD_USARTFP_BAUD_Msk (0xFFFFul << SERCOM_USART_BAUD_USARTFP_BAUD_Pos)
+#define SERCOM_USART_BAUD_USARTFP_BAUD(value) (SERCOM_USART_BAUD_USARTFP_BAUD_Msk & ((value) << SERCOM_USART_BAUD_USARTFP_BAUD_Pos))
+#define SERCOM_USART_BAUD_USARTFP_MASK 0xFFFFul /**< \brief (SERCOM_USART_BAUD_USARTFP) MASK Register */
+
+/* -------- SERCOM_USART_RXPL : (SERCOM Offset: 0x0E) (R/W 8) USART USART Receive Pulse Length -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t RXPL:8; /*!< bit: 0.. 7 Receive Pulse Length */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_USART_RXPL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_RXPL_OFFSET 0x0E /**< \brief (SERCOM_USART_RXPL offset) USART Receive Pulse Length */
+#define SERCOM_USART_RXPL_RESETVALUE 0x00ul /**< \brief (SERCOM_USART_RXPL reset_value) USART Receive Pulse Length */
+
+#define SERCOM_USART_RXPL_RXPL_Pos 0 /**< \brief (SERCOM_USART_RXPL) Receive Pulse Length */
+#define SERCOM_USART_RXPL_RXPL_Msk (0xFFul << SERCOM_USART_RXPL_RXPL_Pos)
+#define SERCOM_USART_RXPL_RXPL(value) (SERCOM_USART_RXPL_RXPL_Msk & ((value) << SERCOM_USART_RXPL_RXPL_Pos))
+#define SERCOM_USART_RXPL_MASK 0xFFul /**< \brief (SERCOM_USART_RXPL) MASK Register */
+
+/* -------- SERCOM_I2CM_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) I2CM I2CM Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt Disable */
+ uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt Disable */
+ uint8_t :5; /*!< bit: 2.. 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_I2CM_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_INTENCLR_OFFSET 0x14 /**< \brief (SERCOM_I2CM_INTENCLR offset) I2CM Interrupt Enable Clear */
+#define SERCOM_I2CM_INTENCLR_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CM_INTENCLR reset_value) I2CM Interrupt Enable Clear */
+
+#define SERCOM_I2CM_INTENCLR_MB_Pos 0 /**< \brief (SERCOM_I2CM_INTENCLR) Master On Bus Interrupt Disable */
+#define SERCOM_I2CM_INTENCLR_MB (0x1ul << SERCOM_I2CM_INTENCLR_MB_Pos)
+#define SERCOM_I2CM_INTENCLR_SB_Pos 1 /**< \brief (SERCOM_I2CM_INTENCLR) Slave On Bus Interrupt Disable */
+#define SERCOM_I2CM_INTENCLR_SB (0x1ul << SERCOM_I2CM_INTENCLR_SB_Pos)
+#define SERCOM_I2CM_INTENCLR_ERROR_Pos 7 /**< \brief (SERCOM_I2CM_INTENCLR) Combined Error Interrupt Disable */
+#define SERCOM_I2CM_INTENCLR_ERROR (0x1ul << SERCOM_I2CM_INTENCLR_ERROR_Pos)
+#define SERCOM_I2CM_INTENCLR_MASK 0x83ul /**< \brief (SERCOM_I2CM_INTENCLR) MASK Register */
+
+/* -------- SERCOM_I2CS_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) I2CS I2CS Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt Disable */
+ uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt Disable */
+ uint8_t DRDY:1; /*!< bit: 2 Data Interrupt Disable */
+ uint8_t :4; /*!< bit: 3.. 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_I2CS_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_INTENCLR_OFFSET 0x14 /**< \brief (SERCOM_I2CS_INTENCLR offset) I2CS Interrupt Enable Clear */
+#define SERCOM_I2CS_INTENCLR_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CS_INTENCLR reset_value) I2CS Interrupt Enable Clear */
+
+#define SERCOM_I2CS_INTENCLR_PREC_Pos 0 /**< \brief (SERCOM_I2CS_INTENCLR) Stop Received Interrupt Disable */
+#define SERCOM_I2CS_INTENCLR_PREC (0x1ul << SERCOM_I2CS_INTENCLR_PREC_Pos)
+#define SERCOM_I2CS_INTENCLR_AMATCH_Pos 1 /**< \brief (SERCOM_I2CS_INTENCLR) Address Match Interrupt Disable */
+#define SERCOM_I2CS_INTENCLR_AMATCH (0x1ul << SERCOM_I2CS_INTENCLR_AMATCH_Pos)
+#define SERCOM_I2CS_INTENCLR_DRDY_Pos 2 /**< \brief (SERCOM_I2CS_INTENCLR) Data Interrupt Disable */
+#define SERCOM_I2CS_INTENCLR_DRDY (0x1ul << SERCOM_I2CS_INTENCLR_DRDY_Pos)
+#define SERCOM_I2CS_INTENCLR_ERROR_Pos 7 /**< \brief (SERCOM_I2CS_INTENCLR) Combined Error Interrupt Disable */
+#define SERCOM_I2CS_INTENCLR_ERROR (0x1ul << SERCOM_I2CS_INTENCLR_ERROR_Pos)
+#define SERCOM_I2CS_INTENCLR_MASK 0x87ul /**< \brief (SERCOM_I2CS_INTENCLR) MASK Register */
+
+/* -------- SERCOM_SPI_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) SPI SPI Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Disable */
+ uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Disable */
+ uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Disable */
+ uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Disable */
+ uint8_t :3; /*!< bit: 4.. 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_SPI_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_INTENCLR_OFFSET 0x14 /**< \brief (SERCOM_SPI_INTENCLR offset) SPI Interrupt Enable Clear */
+#define SERCOM_SPI_INTENCLR_RESETVALUE 0x00ul /**< \brief (SERCOM_SPI_INTENCLR reset_value) SPI Interrupt Enable Clear */
+
+#define SERCOM_SPI_INTENCLR_DRE_Pos 0 /**< \brief (SERCOM_SPI_INTENCLR) Data Register Empty Interrupt Disable */
+#define SERCOM_SPI_INTENCLR_DRE (0x1ul << SERCOM_SPI_INTENCLR_DRE_Pos)
+#define SERCOM_SPI_INTENCLR_TXC_Pos 1 /**< \brief (SERCOM_SPI_INTENCLR) Transmit Complete Interrupt Disable */
+#define SERCOM_SPI_INTENCLR_TXC (0x1ul << SERCOM_SPI_INTENCLR_TXC_Pos)
+#define SERCOM_SPI_INTENCLR_RXC_Pos 2 /**< \brief (SERCOM_SPI_INTENCLR) Receive Complete Interrupt Disable */
+#define SERCOM_SPI_INTENCLR_RXC (0x1ul << SERCOM_SPI_INTENCLR_RXC_Pos)
+#define SERCOM_SPI_INTENCLR_SSL_Pos 3 /**< \brief (SERCOM_SPI_INTENCLR) Slave Select Low Interrupt Disable */
+#define SERCOM_SPI_INTENCLR_SSL (0x1ul << SERCOM_SPI_INTENCLR_SSL_Pos)
+#define SERCOM_SPI_INTENCLR_ERROR_Pos 7 /**< \brief (SERCOM_SPI_INTENCLR) Combined Error Interrupt Disable */
+#define SERCOM_SPI_INTENCLR_ERROR (0x1ul << SERCOM_SPI_INTENCLR_ERROR_Pos)
+#define SERCOM_SPI_INTENCLR_MASK 0x8Ful /**< \brief (SERCOM_SPI_INTENCLR) MASK Register */
+
+/* -------- SERCOM_USART_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) USART USART Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Disable */
+ uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Disable */
+ uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Disable */
+ uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt Disable */
+ uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt Disable */
+ uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt Disable */
+ uint8_t :1; /*!< bit: 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_USART_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_INTENCLR_OFFSET 0x14 /**< \brief (SERCOM_USART_INTENCLR offset) USART Interrupt Enable Clear */
+#define SERCOM_USART_INTENCLR_RESETVALUE 0x00ul /**< \brief (SERCOM_USART_INTENCLR reset_value) USART Interrupt Enable Clear */
+
+#define SERCOM_USART_INTENCLR_DRE_Pos 0 /**< \brief (SERCOM_USART_INTENCLR) Data Register Empty Interrupt Disable */
+#define SERCOM_USART_INTENCLR_DRE (0x1ul << SERCOM_USART_INTENCLR_DRE_Pos)
+#define SERCOM_USART_INTENCLR_TXC_Pos 1 /**< \brief (SERCOM_USART_INTENCLR) Transmit Complete Interrupt Disable */
+#define SERCOM_USART_INTENCLR_TXC (0x1ul << SERCOM_USART_INTENCLR_TXC_Pos)
+#define SERCOM_USART_INTENCLR_RXC_Pos 2 /**< \brief (SERCOM_USART_INTENCLR) Receive Complete Interrupt Disable */
+#define SERCOM_USART_INTENCLR_RXC (0x1ul << SERCOM_USART_INTENCLR_RXC_Pos)
+#define SERCOM_USART_INTENCLR_RXS_Pos 3 /**< \brief (SERCOM_USART_INTENCLR) Receive Start Interrupt Disable */
+#define SERCOM_USART_INTENCLR_RXS (0x1ul << SERCOM_USART_INTENCLR_RXS_Pos)
+#define SERCOM_USART_INTENCLR_CTSIC_Pos 4 /**< \brief (SERCOM_USART_INTENCLR) Clear To Send Input Change Interrupt Disable */
+#define SERCOM_USART_INTENCLR_CTSIC (0x1ul << SERCOM_USART_INTENCLR_CTSIC_Pos)
+#define SERCOM_USART_INTENCLR_RXBRK_Pos 5 /**< \brief (SERCOM_USART_INTENCLR) Break Received Interrupt Disable */
+#define SERCOM_USART_INTENCLR_RXBRK (0x1ul << SERCOM_USART_INTENCLR_RXBRK_Pos)
+#define SERCOM_USART_INTENCLR_ERROR_Pos 7 /**< \brief (SERCOM_USART_INTENCLR) Combined Error Interrupt Disable */
+#define SERCOM_USART_INTENCLR_ERROR (0x1ul << SERCOM_USART_INTENCLR_ERROR_Pos)
+#define SERCOM_USART_INTENCLR_MASK 0xBFul /**< \brief (SERCOM_USART_INTENCLR) MASK Register */
+
+/* -------- SERCOM_I2CM_INTENSET : (SERCOM Offset: 0x16) (R/W 8) I2CM I2CM Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt Enable */
+ uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt Enable */
+ uint8_t :5; /*!< bit: 2.. 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_I2CM_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_INTENSET_OFFSET 0x16 /**< \brief (SERCOM_I2CM_INTENSET offset) I2CM Interrupt Enable Set */
+#define SERCOM_I2CM_INTENSET_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CM_INTENSET reset_value) I2CM Interrupt Enable Set */
+
+#define SERCOM_I2CM_INTENSET_MB_Pos 0 /**< \brief (SERCOM_I2CM_INTENSET) Master On Bus Interrupt Enable */
+#define SERCOM_I2CM_INTENSET_MB (0x1ul << SERCOM_I2CM_INTENSET_MB_Pos)
+#define SERCOM_I2CM_INTENSET_SB_Pos 1 /**< \brief (SERCOM_I2CM_INTENSET) Slave On Bus Interrupt Enable */
+#define SERCOM_I2CM_INTENSET_SB (0x1ul << SERCOM_I2CM_INTENSET_SB_Pos)
+#define SERCOM_I2CM_INTENSET_ERROR_Pos 7 /**< \brief (SERCOM_I2CM_INTENSET) Combined Error Interrupt Enable */
+#define SERCOM_I2CM_INTENSET_ERROR (0x1ul << SERCOM_I2CM_INTENSET_ERROR_Pos)
+#define SERCOM_I2CM_INTENSET_MASK 0x83ul /**< \brief (SERCOM_I2CM_INTENSET) MASK Register */
+
+/* -------- SERCOM_I2CS_INTENSET : (SERCOM Offset: 0x16) (R/W 8) I2CS I2CS Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt Enable */
+ uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt Enable */
+ uint8_t DRDY:1; /*!< bit: 2 Data Interrupt Enable */
+ uint8_t :4; /*!< bit: 3.. 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_I2CS_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_INTENSET_OFFSET 0x16 /**< \brief (SERCOM_I2CS_INTENSET offset) I2CS Interrupt Enable Set */
+#define SERCOM_I2CS_INTENSET_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CS_INTENSET reset_value) I2CS Interrupt Enable Set */
+
+#define SERCOM_I2CS_INTENSET_PREC_Pos 0 /**< \brief (SERCOM_I2CS_INTENSET) Stop Received Interrupt Enable */
+#define SERCOM_I2CS_INTENSET_PREC (0x1ul << SERCOM_I2CS_INTENSET_PREC_Pos)
+#define SERCOM_I2CS_INTENSET_AMATCH_Pos 1 /**< \brief (SERCOM_I2CS_INTENSET) Address Match Interrupt Enable */
+#define SERCOM_I2CS_INTENSET_AMATCH (0x1ul << SERCOM_I2CS_INTENSET_AMATCH_Pos)
+#define SERCOM_I2CS_INTENSET_DRDY_Pos 2 /**< \brief (SERCOM_I2CS_INTENSET) Data Interrupt Enable */
+#define SERCOM_I2CS_INTENSET_DRDY (0x1ul << SERCOM_I2CS_INTENSET_DRDY_Pos)
+#define SERCOM_I2CS_INTENSET_ERROR_Pos 7 /**< \brief (SERCOM_I2CS_INTENSET) Combined Error Interrupt Enable */
+#define SERCOM_I2CS_INTENSET_ERROR (0x1ul << SERCOM_I2CS_INTENSET_ERROR_Pos)
+#define SERCOM_I2CS_INTENSET_MASK 0x87ul /**< \brief (SERCOM_I2CS_INTENSET) MASK Register */
+
+/* -------- SERCOM_SPI_INTENSET : (SERCOM Offset: 0x16) (R/W 8) SPI SPI Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Enable */
+ uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Enable */
+ uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Enable */
+ uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Enable */
+ uint8_t :3; /*!< bit: 4.. 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_SPI_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_INTENSET_OFFSET 0x16 /**< \brief (SERCOM_SPI_INTENSET offset) SPI Interrupt Enable Set */
+#define SERCOM_SPI_INTENSET_RESETVALUE 0x00ul /**< \brief (SERCOM_SPI_INTENSET reset_value) SPI Interrupt Enable Set */
+
+#define SERCOM_SPI_INTENSET_DRE_Pos 0 /**< \brief (SERCOM_SPI_INTENSET) Data Register Empty Interrupt Enable */
+#define SERCOM_SPI_INTENSET_DRE (0x1ul << SERCOM_SPI_INTENSET_DRE_Pos)
+#define SERCOM_SPI_INTENSET_TXC_Pos 1 /**< \brief (SERCOM_SPI_INTENSET) Transmit Complete Interrupt Enable */
+#define SERCOM_SPI_INTENSET_TXC (0x1ul << SERCOM_SPI_INTENSET_TXC_Pos)
+#define SERCOM_SPI_INTENSET_RXC_Pos 2 /**< \brief (SERCOM_SPI_INTENSET) Receive Complete Interrupt Enable */
+#define SERCOM_SPI_INTENSET_RXC (0x1ul << SERCOM_SPI_INTENSET_RXC_Pos)
+#define SERCOM_SPI_INTENSET_SSL_Pos 3 /**< \brief (SERCOM_SPI_INTENSET) Slave Select Low Interrupt Enable */
+#define SERCOM_SPI_INTENSET_SSL (0x1ul << SERCOM_SPI_INTENSET_SSL_Pos)
+#define SERCOM_SPI_INTENSET_ERROR_Pos 7 /**< \brief (SERCOM_SPI_INTENSET) Combined Error Interrupt Enable */
+#define SERCOM_SPI_INTENSET_ERROR (0x1ul << SERCOM_SPI_INTENSET_ERROR_Pos)
+#define SERCOM_SPI_INTENSET_MASK 0x8Ful /**< \brief (SERCOM_SPI_INTENSET) MASK Register */
+
+/* -------- SERCOM_USART_INTENSET : (SERCOM Offset: 0x16) (R/W 8) USART USART Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Enable */
+ uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Enable */
+ uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Enable */
+ uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt Enable */
+ uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt Enable */
+ uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt Enable */
+ uint8_t :1; /*!< bit: 6 Reserved */
+ uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_USART_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_INTENSET_OFFSET 0x16 /**< \brief (SERCOM_USART_INTENSET offset) USART Interrupt Enable Set */
+#define SERCOM_USART_INTENSET_RESETVALUE 0x00ul /**< \brief (SERCOM_USART_INTENSET reset_value) USART Interrupt Enable Set */
+
+#define SERCOM_USART_INTENSET_DRE_Pos 0 /**< \brief (SERCOM_USART_INTENSET) Data Register Empty Interrupt Enable */
+#define SERCOM_USART_INTENSET_DRE (0x1ul << SERCOM_USART_INTENSET_DRE_Pos)
+#define SERCOM_USART_INTENSET_TXC_Pos 1 /**< \brief (SERCOM_USART_INTENSET) Transmit Complete Interrupt Enable */
+#define SERCOM_USART_INTENSET_TXC (0x1ul << SERCOM_USART_INTENSET_TXC_Pos)
+#define SERCOM_USART_INTENSET_RXC_Pos 2 /**< \brief (SERCOM_USART_INTENSET) Receive Complete Interrupt Enable */
+#define SERCOM_USART_INTENSET_RXC (0x1ul << SERCOM_USART_INTENSET_RXC_Pos)
+#define SERCOM_USART_INTENSET_RXS_Pos 3 /**< \brief (SERCOM_USART_INTENSET) Receive Start Interrupt Enable */
+#define SERCOM_USART_INTENSET_RXS (0x1ul << SERCOM_USART_INTENSET_RXS_Pos)
+#define SERCOM_USART_INTENSET_CTSIC_Pos 4 /**< \brief (SERCOM_USART_INTENSET) Clear To Send Input Change Interrupt Enable */
+#define SERCOM_USART_INTENSET_CTSIC (0x1ul << SERCOM_USART_INTENSET_CTSIC_Pos)
+#define SERCOM_USART_INTENSET_RXBRK_Pos 5 /**< \brief (SERCOM_USART_INTENSET) Break Received Interrupt Enable */
+#define SERCOM_USART_INTENSET_RXBRK (0x1ul << SERCOM_USART_INTENSET_RXBRK_Pos)
+#define SERCOM_USART_INTENSET_ERROR_Pos 7 /**< \brief (SERCOM_USART_INTENSET) Combined Error Interrupt Enable */
+#define SERCOM_USART_INTENSET_ERROR (0x1ul << SERCOM_USART_INTENSET_ERROR_Pos)
+#define SERCOM_USART_INTENSET_MASK 0xBFul /**< \brief (SERCOM_USART_INTENSET) MASK Register */
+
+/* -------- SERCOM_I2CM_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) I2CM I2CM Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt */
+ __I uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt */
+ __I uint8_t :5; /*!< bit: 2.. 6 Reserved */
+ __I uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_I2CM_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_INTFLAG_OFFSET 0x18 /**< \brief (SERCOM_I2CM_INTFLAG offset) I2CM Interrupt Flag Status and Clear */
+#define SERCOM_I2CM_INTFLAG_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CM_INTFLAG reset_value) I2CM Interrupt Flag Status and Clear */
+
+#define SERCOM_I2CM_INTFLAG_MB_Pos 0 /**< \brief (SERCOM_I2CM_INTFLAG) Master On Bus Interrupt */
+#define SERCOM_I2CM_INTFLAG_MB (0x1ul << SERCOM_I2CM_INTFLAG_MB_Pos)
+#define SERCOM_I2CM_INTFLAG_SB_Pos 1 /**< \brief (SERCOM_I2CM_INTFLAG) Slave On Bus Interrupt */
+#define SERCOM_I2CM_INTFLAG_SB (0x1ul << SERCOM_I2CM_INTFLAG_SB_Pos)
+#define SERCOM_I2CM_INTFLAG_ERROR_Pos 7 /**< \brief (SERCOM_I2CM_INTFLAG) Combined Error Interrupt */
+#define SERCOM_I2CM_INTFLAG_ERROR (0x1ul << SERCOM_I2CM_INTFLAG_ERROR_Pos)
+#define SERCOM_I2CM_INTFLAG_MASK 0x83ul /**< \brief (SERCOM_I2CM_INTFLAG) MASK Register */
+
+/* -------- SERCOM_I2CS_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) I2CS I2CS Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt */
+ __I uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt */
+ __I uint8_t DRDY:1; /*!< bit: 2 Data Interrupt */
+ __I uint8_t :4; /*!< bit: 3.. 6 Reserved */
+ __I uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_I2CS_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_INTFLAG_OFFSET 0x18 /**< \brief (SERCOM_I2CS_INTFLAG offset) I2CS Interrupt Flag Status and Clear */
+#define SERCOM_I2CS_INTFLAG_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CS_INTFLAG reset_value) I2CS Interrupt Flag Status and Clear */
+
+#define SERCOM_I2CS_INTFLAG_PREC_Pos 0 /**< \brief (SERCOM_I2CS_INTFLAG) Stop Received Interrupt */
+#define SERCOM_I2CS_INTFLAG_PREC (0x1ul << SERCOM_I2CS_INTFLAG_PREC_Pos)
+#define SERCOM_I2CS_INTFLAG_AMATCH_Pos 1 /**< \brief (SERCOM_I2CS_INTFLAG) Address Match Interrupt */
+#define SERCOM_I2CS_INTFLAG_AMATCH (0x1ul << SERCOM_I2CS_INTFLAG_AMATCH_Pos)
+#define SERCOM_I2CS_INTFLAG_DRDY_Pos 2 /**< \brief (SERCOM_I2CS_INTFLAG) Data Interrupt */
+#define SERCOM_I2CS_INTFLAG_DRDY (0x1ul << SERCOM_I2CS_INTFLAG_DRDY_Pos)
+#define SERCOM_I2CS_INTFLAG_ERROR_Pos 7 /**< \brief (SERCOM_I2CS_INTFLAG) Combined Error Interrupt */
+#define SERCOM_I2CS_INTFLAG_ERROR (0x1ul << SERCOM_I2CS_INTFLAG_ERROR_Pos)
+#define SERCOM_I2CS_INTFLAG_MASK 0x87ul /**< \brief (SERCOM_I2CS_INTFLAG) MASK Register */
+
+/* -------- SERCOM_SPI_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) SPI SPI Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt */
+ __I uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt */
+ __I uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt */
+ __I uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Flag */
+ __I uint8_t :3; /*!< bit: 4.. 6 Reserved */
+ __I uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_SPI_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_INTFLAG_OFFSET 0x18 /**< \brief (SERCOM_SPI_INTFLAG offset) SPI Interrupt Flag Status and Clear */
+#define SERCOM_SPI_INTFLAG_RESETVALUE 0x00ul /**< \brief (SERCOM_SPI_INTFLAG reset_value) SPI Interrupt Flag Status and Clear */
+
+#define SERCOM_SPI_INTFLAG_DRE_Pos 0 /**< \brief (SERCOM_SPI_INTFLAG) Data Register Empty Interrupt */
+#define SERCOM_SPI_INTFLAG_DRE (0x1ul << SERCOM_SPI_INTFLAG_DRE_Pos)
+#define SERCOM_SPI_INTFLAG_TXC_Pos 1 /**< \brief (SERCOM_SPI_INTFLAG) Transmit Complete Interrupt */
+#define SERCOM_SPI_INTFLAG_TXC (0x1ul << SERCOM_SPI_INTFLAG_TXC_Pos)
+#define SERCOM_SPI_INTFLAG_RXC_Pos 2 /**< \brief (SERCOM_SPI_INTFLAG) Receive Complete Interrupt */
+#define SERCOM_SPI_INTFLAG_RXC (0x1ul << SERCOM_SPI_INTFLAG_RXC_Pos)
+#define SERCOM_SPI_INTFLAG_SSL_Pos 3 /**< \brief (SERCOM_SPI_INTFLAG) Slave Select Low Interrupt Flag */
+#define SERCOM_SPI_INTFLAG_SSL (0x1ul << SERCOM_SPI_INTFLAG_SSL_Pos)
+#define SERCOM_SPI_INTFLAG_ERROR_Pos 7 /**< \brief (SERCOM_SPI_INTFLAG) Combined Error Interrupt */
+#define SERCOM_SPI_INTFLAG_ERROR (0x1ul << SERCOM_SPI_INTFLAG_ERROR_Pos)
+#define SERCOM_SPI_INTFLAG_MASK 0x8Ful /**< \brief (SERCOM_SPI_INTFLAG) MASK Register */
+
+/* -------- SERCOM_USART_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) USART USART Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt */
+ __I uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt */
+ __I uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt */
+ __I uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt */
+ __I uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt */
+ __I uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt */
+ __I uint8_t :1; /*!< bit: 6 Reserved */
+ __I uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_USART_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_INTFLAG_OFFSET 0x18 /**< \brief (SERCOM_USART_INTFLAG offset) USART Interrupt Flag Status and Clear */
+#define SERCOM_USART_INTFLAG_RESETVALUE 0x00ul /**< \brief (SERCOM_USART_INTFLAG reset_value) USART Interrupt Flag Status and Clear */
+
+#define SERCOM_USART_INTFLAG_DRE_Pos 0 /**< \brief (SERCOM_USART_INTFLAG) Data Register Empty Interrupt */
+#define SERCOM_USART_INTFLAG_DRE (0x1ul << SERCOM_USART_INTFLAG_DRE_Pos)
+#define SERCOM_USART_INTFLAG_TXC_Pos 1 /**< \brief (SERCOM_USART_INTFLAG) Transmit Complete Interrupt */
+#define SERCOM_USART_INTFLAG_TXC (0x1ul << SERCOM_USART_INTFLAG_TXC_Pos)
+#define SERCOM_USART_INTFLAG_RXC_Pos 2 /**< \brief (SERCOM_USART_INTFLAG) Receive Complete Interrupt */
+#define SERCOM_USART_INTFLAG_RXC (0x1ul << SERCOM_USART_INTFLAG_RXC_Pos)
+#define SERCOM_USART_INTFLAG_RXS_Pos 3 /**< \brief (SERCOM_USART_INTFLAG) Receive Start Interrupt */
+#define SERCOM_USART_INTFLAG_RXS (0x1ul << SERCOM_USART_INTFLAG_RXS_Pos)
+#define SERCOM_USART_INTFLAG_CTSIC_Pos 4 /**< \brief (SERCOM_USART_INTFLAG) Clear To Send Input Change Interrupt */
+#define SERCOM_USART_INTFLAG_CTSIC (0x1ul << SERCOM_USART_INTFLAG_CTSIC_Pos)
+#define SERCOM_USART_INTFLAG_RXBRK_Pos 5 /**< \brief (SERCOM_USART_INTFLAG) Break Received Interrupt */
+#define SERCOM_USART_INTFLAG_RXBRK (0x1ul << SERCOM_USART_INTFLAG_RXBRK_Pos)
+#define SERCOM_USART_INTFLAG_ERROR_Pos 7 /**< \brief (SERCOM_USART_INTFLAG) Combined Error Interrupt */
+#define SERCOM_USART_INTFLAG_ERROR (0x1ul << SERCOM_USART_INTFLAG_ERROR_Pos)
+#define SERCOM_USART_INTFLAG_MASK 0xBFul /**< \brief (SERCOM_USART_INTFLAG) MASK Register */
+
+/* -------- SERCOM_I2CM_STATUS : (SERCOM Offset: 0x1A) (R/W 16) I2CM I2CM Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t BUSERR:1; /*!< bit: 0 Bus Error */
+ uint16_t ARBLOST:1; /*!< bit: 1 Arbitration Lost */
+ uint16_t RXNACK:1; /*!< bit: 2 Received Not Acknowledge */
+ uint16_t :1; /*!< bit: 3 Reserved */
+ uint16_t BUSSTATE:2; /*!< bit: 4.. 5 Bus State */
+ uint16_t LOWTOUT:1; /*!< bit: 6 SCL Low Timeout */
+ uint16_t CLKHOLD:1; /*!< bit: 7 Clock Hold */
+ uint16_t MEXTTOUT:1; /*!< bit: 8 Master SCL Low Extend Timeout */
+ uint16_t SEXTTOUT:1; /*!< bit: 9 Slave SCL Low Extend Timeout */
+ uint16_t LENERR:1; /*!< bit: 10 Length Error */
+ uint16_t :5; /*!< bit: 11..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} SERCOM_I2CM_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_STATUS_OFFSET 0x1A /**< \brief (SERCOM_I2CM_STATUS offset) I2CM Status */
+#define SERCOM_I2CM_STATUS_RESETVALUE 0x0000ul /**< \brief (SERCOM_I2CM_STATUS reset_value) I2CM Status */
+
+#define SERCOM_I2CM_STATUS_BUSERR_Pos 0 /**< \brief (SERCOM_I2CM_STATUS) Bus Error */
+#define SERCOM_I2CM_STATUS_BUSERR (0x1ul << SERCOM_I2CM_STATUS_BUSERR_Pos)
+#define SERCOM_I2CM_STATUS_ARBLOST_Pos 1 /**< \brief (SERCOM_I2CM_STATUS) Arbitration Lost */
+#define SERCOM_I2CM_STATUS_ARBLOST (0x1ul << SERCOM_I2CM_STATUS_ARBLOST_Pos)
+#define SERCOM_I2CM_STATUS_RXNACK_Pos 2 /**< \brief (SERCOM_I2CM_STATUS) Received Not Acknowledge */
+#define SERCOM_I2CM_STATUS_RXNACK (0x1ul << SERCOM_I2CM_STATUS_RXNACK_Pos)
+#define SERCOM_I2CM_STATUS_BUSSTATE_Pos 4 /**< \brief (SERCOM_I2CM_STATUS) Bus State */
+#define SERCOM_I2CM_STATUS_BUSSTATE_Msk (0x3ul << SERCOM_I2CM_STATUS_BUSSTATE_Pos)
+#define SERCOM_I2CM_STATUS_BUSSTATE(value) (SERCOM_I2CM_STATUS_BUSSTATE_Msk & ((value) << SERCOM_I2CM_STATUS_BUSSTATE_Pos))
+#define SERCOM_I2CM_STATUS_LOWTOUT_Pos 6 /**< \brief (SERCOM_I2CM_STATUS) SCL Low Timeout */
+#define SERCOM_I2CM_STATUS_LOWTOUT (0x1ul << SERCOM_I2CM_STATUS_LOWTOUT_Pos)
+#define SERCOM_I2CM_STATUS_CLKHOLD_Pos 7 /**< \brief (SERCOM_I2CM_STATUS) Clock Hold */
+#define SERCOM_I2CM_STATUS_CLKHOLD (0x1ul << SERCOM_I2CM_STATUS_CLKHOLD_Pos)
+#define SERCOM_I2CM_STATUS_MEXTTOUT_Pos 8 /**< \brief (SERCOM_I2CM_STATUS) Master SCL Low Extend Timeout */
+#define SERCOM_I2CM_STATUS_MEXTTOUT (0x1ul << SERCOM_I2CM_STATUS_MEXTTOUT_Pos)
+#define SERCOM_I2CM_STATUS_SEXTTOUT_Pos 9 /**< \brief (SERCOM_I2CM_STATUS) Slave SCL Low Extend Timeout */
+#define SERCOM_I2CM_STATUS_SEXTTOUT (0x1ul << SERCOM_I2CM_STATUS_SEXTTOUT_Pos)
+#define SERCOM_I2CM_STATUS_LENERR_Pos 10 /**< \brief (SERCOM_I2CM_STATUS) Length Error */
+#define SERCOM_I2CM_STATUS_LENERR (0x1ul << SERCOM_I2CM_STATUS_LENERR_Pos)
+#define SERCOM_I2CM_STATUS_MASK 0x07F7ul /**< \brief (SERCOM_I2CM_STATUS) MASK Register */
+
+/* -------- SERCOM_I2CS_STATUS : (SERCOM Offset: 0x1A) (R/W 16) I2CS I2CS Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t BUSERR:1; /*!< bit: 0 Bus Error */
+ uint16_t COLL:1; /*!< bit: 1 Transmit Collision */
+ uint16_t RXNACK:1; /*!< bit: 2 Received Not Acknowledge */
+ uint16_t DIR:1; /*!< bit: 3 Read/Write Direction */
+ uint16_t SR:1; /*!< bit: 4 Repeated Start */
+ uint16_t :1; /*!< bit: 5 Reserved */
+ uint16_t LOWTOUT:1; /*!< bit: 6 SCL Low Timeout */
+ uint16_t CLKHOLD:1; /*!< bit: 7 Clock Hold */
+ uint16_t :1; /*!< bit: 8 Reserved */
+ uint16_t SEXTTOUT:1; /*!< bit: 9 Slave SCL Low Extend Timeout */
+ uint16_t HS:1; /*!< bit: 10 High Speed */
+ uint16_t :5; /*!< bit: 11..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} SERCOM_I2CS_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_STATUS_OFFSET 0x1A /**< \brief (SERCOM_I2CS_STATUS offset) I2CS Status */
+#define SERCOM_I2CS_STATUS_RESETVALUE 0x0000ul /**< \brief (SERCOM_I2CS_STATUS reset_value) I2CS Status */
+
+#define SERCOM_I2CS_STATUS_BUSERR_Pos 0 /**< \brief (SERCOM_I2CS_STATUS) Bus Error */
+#define SERCOM_I2CS_STATUS_BUSERR (0x1ul << SERCOM_I2CS_STATUS_BUSERR_Pos)
+#define SERCOM_I2CS_STATUS_COLL_Pos 1 /**< \brief (SERCOM_I2CS_STATUS) Transmit Collision */
+#define SERCOM_I2CS_STATUS_COLL (0x1ul << SERCOM_I2CS_STATUS_COLL_Pos)
+#define SERCOM_I2CS_STATUS_RXNACK_Pos 2 /**< \brief (SERCOM_I2CS_STATUS) Received Not Acknowledge */
+#define SERCOM_I2CS_STATUS_RXNACK (0x1ul << SERCOM_I2CS_STATUS_RXNACK_Pos)
+#define SERCOM_I2CS_STATUS_DIR_Pos 3 /**< \brief (SERCOM_I2CS_STATUS) Read/Write Direction */
+#define SERCOM_I2CS_STATUS_DIR (0x1ul << SERCOM_I2CS_STATUS_DIR_Pos)
+#define SERCOM_I2CS_STATUS_SR_Pos 4 /**< \brief (SERCOM_I2CS_STATUS) Repeated Start */
+#define SERCOM_I2CS_STATUS_SR (0x1ul << SERCOM_I2CS_STATUS_SR_Pos)
+#define SERCOM_I2CS_STATUS_LOWTOUT_Pos 6 /**< \brief (SERCOM_I2CS_STATUS) SCL Low Timeout */
+#define SERCOM_I2CS_STATUS_LOWTOUT (0x1ul << SERCOM_I2CS_STATUS_LOWTOUT_Pos)
+#define SERCOM_I2CS_STATUS_CLKHOLD_Pos 7 /**< \brief (SERCOM_I2CS_STATUS) Clock Hold */
+#define SERCOM_I2CS_STATUS_CLKHOLD (0x1ul << SERCOM_I2CS_STATUS_CLKHOLD_Pos)
+#define SERCOM_I2CS_STATUS_SEXTTOUT_Pos 9 /**< \brief (SERCOM_I2CS_STATUS) Slave SCL Low Extend Timeout */
+#define SERCOM_I2CS_STATUS_SEXTTOUT (0x1ul << SERCOM_I2CS_STATUS_SEXTTOUT_Pos)
+#define SERCOM_I2CS_STATUS_HS_Pos 10 /**< \brief (SERCOM_I2CS_STATUS) High Speed */
+#define SERCOM_I2CS_STATUS_HS (0x1ul << SERCOM_I2CS_STATUS_HS_Pos)
+#define SERCOM_I2CS_STATUS_MASK 0x06DFul /**< \brief (SERCOM_I2CS_STATUS) MASK Register */
+
+/* -------- SERCOM_SPI_STATUS : (SERCOM Offset: 0x1A) (R/W 16) SPI SPI Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t :2; /*!< bit: 0.. 1 Reserved */
+ uint16_t BUFOVF:1; /*!< bit: 2 Buffer Overflow */
+ uint16_t :13; /*!< bit: 3..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} SERCOM_SPI_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_STATUS_OFFSET 0x1A /**< \brief (SERCOM_SPI_STATUS offset) SPI Status */
+#define SERCOM_SPI_STATUS_RESETVALUE 0x0000ul /**< \brief (SERCOM_SPI_STATUS reset_value) SPI Status */
+
+#define SERCOM_SPI_STATUS_BUFOVF_Pos 2 /**< \brief (SERCOM_SPI_STATUS) Buffer Overflow */
+#define SERCOM_SPI_STATUS_BUFOVF (0x1ul << SERCOM_SPI_STATUS_BUFOVF_Pos)
+#define SERCOM_SPI_STATUS_MASK 0x0004ul /**< \brief (SERCOM_SPI_STATUS) MASK Register */
+
+/* -------- SERCOM_USART_STATUS : (SERCOM Offset: 0x1A) (R/W 16) USART USART Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t PERR:1; /*!< bit: 0 Parity Error */
+ uint16_t FERR:1; /*!< bit: 1 Frame Error */
+ uint16_t BUFOVF:1; /*!< bit: 2 Buffer Overflow */
+ uint16_t CTS:1; /*!< bit: 3 Clear To Send */
+ uint16_t ISF:1; /*!< bit: 4 Inconsistent Sync Field */
+ uint16_t COLL:1; /*!< bit: 5 Collision Detected */
+ uint16_t :10; /*!< bit: 6..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} SERCOM_USART_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_STATUS_OFFSET 0x1A /**< \brief (SERCOM_USART_STATUS offset) USART Status */
+#define SERCOM_USART_STATUS_RESETVALUE 0x0000ul /**< \brief (SERCOM_USART_STATUS reset_value) USART Status */
+
+#define SERCOM_USART_STATUS_PERR_Pos 0 /**< \brief (SERCOM_USART_STATUS) Parity Error */
+#define SERCOM_USART_STATUS_PERR (0x1ul << SERCOM_USART_STATUS_PERR_Pos)
+#define SERCOM_USART_STATUS_FERR_Pos 1 /**< \brief (SERCOM_USART_STATUS) Frame Error */
+#define SERCOM_USART_STATUS_FERR (0x1ul << SERCOM_USART_STATUS_FERR_Pos)
+#define SERCOM_USART_STATUS_BUFOVF_Pos 2 /**< \brief (SERCOM_USART_STATUS) Buffer Overflow */
+#define SERCOM_USART_STATUS_BUFOVF (0x1ul << SERCOM_USART_STATUS_BUFOVF_Pos)
+#define SERCOM_USART_STATUS_CTS_Pos 3 /**< \brief (SERCOM_USART_STATUS) Clear To Send */
+#define SERCOM_USART_STATUS_CTS (0x1ul << SERCOM_USART_STATUS_CTS_Pos)
+#define SERCOM_USART_STATUS_ISF_Pos 4 /**< \brief (SERCOM_USART_STATUS) Inconsistent Sync Field */
+#define SERCOM_USART_STATUS_ISF (0x1ul << SERCOM_USART_STATUS_ISF_Pos)
+#define SERCOM_USART_STATUS_COLL_Pos 5 /**< \brief (SERCOM_USART_STATUS) Collision Detected */
+#define SERCOM_USART_STATUS_COLL (0x1ul << SERCOM_USART_STATUS_COLL_Pos)
+#define SERCOM_USART_STATUS_MASK 0x003Ful /**< \brief (SERCOM_USART_STATUS) MASK Register */
+
+/* -------- SERCOM_I2CM_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) I2CM I2CM Syncbusy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
+ uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */
+ uint32_t SYSOP:1; /*!< bit: 2 System Operation Synchronization Busy */
+ uint32_t :29; /*!< bit: 3..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_I2CM_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_I2CM_SYNCBUSY offset) I2CM Syncbusy */
+#define SERCOM_I2CM_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CM_SYNCBUSY reset_value) I2CM Syncbusy */
+
+#define SERCOM_I2CM_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_I2CM_SYNCBUSY) Software Reset Synchronization Busy */
+#define SERCOM_I2CM_SYNCBUSY_SWRST (0x1ul << SERCOM_I2CM_SYNCBUSY_SWRST_Pos)
+#define SERCOM_I2CM_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SERCOM_I2CM_SYNCBUSY) SERCOM Enable Synchronization Busy */
+#define SERCOM_I2CM_SYNCBUSY_ENABLE (0x1ul << SERCOM_I2CM_SYNCBUSY_ENABLE_Pos)
+#define SERCOM_I2CM_SYNCBUSY_SYSOP_Pos 2 /**< \brief (SERCOM_I2CM_SYNCBUSY) System Operation Synchronization Busy */
+#define SERCOM_I2CM_SYNCBUSY_SYSOP (0x1ul << SERCOM_I2CM_SYNCBUSY_SYSOP_Pos)
+#define SERCOM_I2CM_SYNCBUSY_MASK 0x00000007ul /**< \brief (SERCOM_I2CM_SYNCBUSY) MASK Register */
+
+/* -------- SERCOM_I2CS_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) I2CS I2CS Syncbusy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
+ uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */
+ uint32_t :30; /*!< bit: 2..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_I2CS_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_I2CS_SYNCBUSY offset) I2CS Syncbusy */
+#define SERCOM_I2CS_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CS_SYNCBUSY reset_value) I2CS Syncbusy */
+
+#define SERCOM_I2CS_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_I2CS_SYNCBUSY) Software Reset Synchronization Busy */
+#define SERCOM_I2CS_SYNCBUSY_SWRST (0x1ul << SERCOM_I2CS_SYNCBUSY_SWRST_Pos)
+#define SERCOM_I2CS_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SERCOM_I2CS_SYNCBUSY) SERCOM Enable Synchronization Busy */
+#define SERCOM_I2CS_SYNCBUSY_ENABLE (0x1ul << SERCOM_I2CS_SYNCBUSY_ENABLE_Pos)
+#define SERCOM_I2CS_SYNCBUSY_MASK 0x00000003ul /**< \brief (SERCOM_I2CS_SYNCBUSY) MASK Register */
+
+/* -------- SERCOM_SPI_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) SPI SPI Syncbusy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
+ uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */
+ uint32_t CTRLB:1; /*!< bit: 2 CTRLB Synchronization Busy */
+ uint32_t :29; /*!< bit: 3..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_SPI_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_SPI_SYNCBUSY offset) SPI Syncbusy */
+#define SERCOM_SPI_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (SERCOM_SPI_SYNCBUSY reset_value) SPI Syncbusy */
+
+#define SERCOM_SPI_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_SPI_SYNCBUSY) Software Reset Synchronization Busy */
+#define SERCOM_SPI_SYNCBUSY_SWRST (0x1ul << SERCOM_SPI_SYNCBUSY_SWRST_Pos)
+#define SERCOM_SPI_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SERCOM_SPI_SYNCBUSY) SERCOM Enable Synchronization Busy */
+#define SERCOM_SPI_SYNCBUSY_ENABLE (0x1ul << SERCOM_SPI_SYNCBUSY_ENABLE_Pos)
+#define SERCOM_SPI_SYNCBUSY_CTRLB_Pos 2 /**< \brief (SERCOM_SPI_SYNCBUSY) CTRLB Synchronization Busy */
+#define SERCOM_SPI_SYNCBUSY_CTRLB (0x1ul << SERCOM_SPI_SYNCBUSY_CTRLB_Pos)
+#define SERCOM_SPI_SYNCBUSY_MASK 0x00000007ul /**< \brief (SERCOM_SPI_SYNCBUSY) MASK Register */
+
+/* -------- SERCOM_USART_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) USART USART Syncbusy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
+ uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */
+ uint32_t CTRLB:1; /*!< bit: 2 CTRLB Synchronization Busy */
+ uint32_t :29; /*!< bit: 3..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_USART_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_USART_SYNCBUSY offset) USART Syncbusy */
+#define SERCOM_USART_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (SERCOM_USART_SYNCBUSY reset_value) USART Syncbusy */
+
+#define SERCOM_USART_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_USART_SYNCBUSY) Software Reset Synchronization Busy */
+#define SERCOM_USART_SYNCBUSY_SWRST (0x1ul << SERCOM_USART_SYNCBUSY_SWRST_Pos)
+#define SERCOM_USART_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SERCOM_USART_SYNCBUSY) SERCOM Enable Synchronization Busy */
+#define SERCOM_USART_SYNCBUSY_ENABLE (0x1ul << SERCOM_USART_SYNCBUSY_ENABLE_Pos)
+#define SERCOM_USART_SYNCBUSY_CTRLB_Pos 2 /**< \brief (SERCOM_USART_SYNCBUSY) CTRLB Synchronization Busy */
+#define SERCOM_USART_SYNCBUSY_CTRLB (0x1ul << SERCOM_USART_SYNCBUSY_CTRLB_Pos)
+#define SERCOM_USART_SYNCBUSY_MASK 0x00000007ul /**< \brief (SERCOM_USART_SYNCBUSY) MASK Register */
+
+/* -------- SERCOM_I2CM_ADDR : (SERCOM Offset: 0x24) (R/W 32) I2CM I2CM Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ADDR:11; /*!< bit: 0..10 Address Value */
+ uint32_t :2; /*!< bit: 11..12 Reserved */
+ uint32_t LENEN:1; /*!< bit: 13 Length Enable */
+ uint32_t HS:1; /*!< bit: 14 High Speed Mode */
+ uint32_t TENBITEN:1; /*!< bit: 15 Ten Bit Addressing Enable */
+ uint32_t LEN:8; /*!< bit: 16..23 Length */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_I2CM_ADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_ADDR_OFFSET 0x24 /**< \brief (SERCOM_I2CM_ADDR offset) I2CM Address */
+#define SERCOM_I2CM_ADDR_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CM_ADDR reset_value) I2CM Address */
+
+#define SERCOM_I2CM_ADDR_ADDR_Pos 0 /**< \brief (SERCOM_I2CM_ADDR) Address Value */
+#define SERCOM_I2CM_ADDR_ADDR_Msk (0x7FFul << SERCOM_I2CM_ADDR_ADDR_Pos)
+#define SERCOM_I2CM_ADDR_ADDR(value) (SERCOM_I2CM_ADDR_ADDR_Msk & ((value) << SERCOM_I2CM_ADDR_ADDR_Pos))
+#define SERCOM_I2CM_ADDR_LENEN_Pos 13 /**< \brief (SERCOM_I2CM_ADDR) Length Enable */
+#define SERCOM_I2CM_ADDR_LENEN (0x1ul << SERCOM_I2CM_ADDR_LENEN_Pos)
+#define SERCOM_I2CM_ADDR_HS_Pos 14 /**< \brief (SERCOM_I2CM_ADDR) High Speed Mode */
+#define SERCOM_I2CM_ADDR_HS (0x1ul << SERCOM_I2CM_ADDR_HS_Pos)
+#define SERCOM_I2CM_ADDR_TENBITEN_Pos 15 /**< \brief (SERCOM_I2CM_ADDR) Ten Bit Addressing Enable */
+#define SERCOM_I2CM_ADDR_TENBITEN (0x1ul << SERCOM_I2CM_ADDR_TENBITEN_Pos)
+#define SERCOM_I2CM_ADDR_LEN_Pos 16 /**< \brief (SERCOM_I2CM_ADDR) Length */
+#define SERCOM_I2CM_ADDR_LEN_Msk (0xFFul << SERCOM_I2CM_ADDR_LEN_Pos)
+#define SERCOM_I2CM_ADDR_LEN(value) (SERCOM_I2CM_ADDR_LEN_Msk & ((value) << SERCOM_I2CM_ADDR_LEN_Pos))
+#define SERCOM_I2CM_ADDR_MASK 0x00FFE7FFul /**< \brief (SERCOM_I2CM_ADDR) MASK Register */
+
+/* -------- SERCOM_I2CS_ADDR : (SERCOM Offset: 0x24) (R/W 32) I2CS I2CS Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t GENCEN:1; /*!< bit: 0 General Call Address Enable */
+ uint32_t ADDR:10; /*!< bit: 1..10 Address Value */
+ uint32_t :4; /*!< bit: 11..14 Reserved */
+ uint32_t TENBITEN:1; /*!< bit: 15 Ten Bit Addressing Enable */
+ uint32_t :1; /*!< bit: 16 Reserved */
+ uint32_t ADDRMASK:10; /*!< bit: 17..26 Address Mask */
+ uint32_t :5; /*!< bit: 27..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_I2CS_ADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_ADDR_OFFSET 0x24 /**< \brief (SERCOM_I2CS_ADDR offset) I2CS Address */
+#define SERCOM_I2CS_ADDR_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CS_ADDR reset_value) I2CS Address */
+
+#define SERCOM_I2CS_ADDR_GENCEN_Pos 0 /**< \brief (SERCOM_I2CS_ADDR) General Call Address Enable */
+#define SERCOM_I2CS_ADDR_GENCEN (0x1ul << SERCOM_I2CS_ADDR_GENCEN_Pos)
+#define SERCOM_I2CS_ADDR_ADDR_Pos 1 /**< \brief (SERCOM_I2CS_ADDR) Address Value */
+#define SERCOM_I2CS_ADDR_ADDR_Msk (0x3FFul << SERCOM_I2CS_ADDR_ADDR_Pos)
+#define SERCOM_I2CS_ADDR_ADDR(value) (SERCOM_I2CS_ADDR_ADDR_Msk & ((value) << SERCOM_I2CS_ADDR_ADDR_Pos))
+#define SERCOM_I2CS_ADDR_TENBITEN_Pos 15 /**< \brief (SERCOM_I2CS_ADDR) Ten Bit Addressing Enable */
+#define SERCOM_I2CS_ADDR_TENBITEN (0x1ul << SERCOM_I2CS_ADDR_TENBITEN_Pos)
+#define SERCOM_I2CS_ADDR_ADDRMASK_Pos 17 /**< \brief (SERCOM_I2CS_ADDR) Address Mask */
+#define SERCOM_I2CS_ADDR_ADDRMASK_Msk (0x3FFul << SERCOM_I2CS_ADDR_ADDRMASK_Pos)
+#define SERCOM_I2CS_ADDR_ADDRMASK(value) (SERCOM_I2CS_ADDR_ADDRMASK_Msk & ((value) << SERCOM_I2CS_ADDR_ADDRMASK_Pos))
+#define SERCOM_I2CS_ADDR_MASK 0x07FE87FFul /**< \brief (SERCOM_I2CS_ADDR) MASK Register */
+
+/* -------- SERCOM_SPI_ADDR : (SERCOM Offset: 0x24) (R/W 32) SPI SPI Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ADDR:8; /*!< bit: 0.. 7 Address Value */
+ uint32_t :8; /*!< bit: 8..15 Reserved */
+ uint32_t ADDRMASK:8; /*!< bit: 16..23 Address Mask */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_SPI_ADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_ADDR_OFFSET 0x24 /**< \brief (SERCOM_SPI_ADDR offset) SPI Address */
+#define SERCOM_SPI_ADDR_RESETVALUE 0x00000000ul /**< \brief (SERCOM_SPI_ADDR reset_value) SPI Address */
+
+#define SERCOM_SPI_ADDR_ADDR_Pos 0 /**< \brief (SERCOM_SPI_ADDR) Address Value */
+#define SERCOM_SPI_ADDR_ADDR_Msk (0xFFul << SERCOM_SPI_ADDR_ADDR_Pos)
+#define SERCOM_SPI_ADDR_ADDR(value) (SERCOM_SPI_ADDR_ADDR_Msk & ((value) << SERCOM_SPI_ADDR_ADDR_Pos))
+#define SERCOM_SPI_ADDR_ADDRMASK_Pos 16 /**< \brief (SERCOM_SPI_ADDR) Address Mask */
+#define SERCOM_SPI_ADDR_ADDRMASK_Msk (0xFFul << SERCOM_SPI_ADDR_ADDRMASK_Pos)
+#define SERCOM_SPI_ADDR_ADDRMASK(value) (SERCOM_SPI_ADDR_ADDRMASK_Msk & ((value) << SERCOM_SPI_ADDR_ADDRMASK_Pos))
+#define SERCOM_SPI_ADDR_MASK 0x00FF00FFul /**< \brief (SERCOM_SPI_ADDR) MASK Register */
+
+/* -------- SERCOM_I2CM_DATA : (SERCOM Offset: 0x28) (R/W 8) I2CM I2CM Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DATA:8; /*!< bit: 0.. 7 Data Value */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_I2CM_DATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_DATA_OFFSET 0x28 /**< \brief (SERCOM_I2CM_DATA offset) I2CM Data */
+#define SERCOM_I2CM_DATA_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CM_DATA reset_value) I2CM Data */
+
+#define SERCOM_I2CM_DATA_DATA_Pos 0 /**< \brief (SERCOM_I2CM_DATA) Data Value */
+#define SERCOM_I2CM_DATA_DATA_Msk (0xFFul << SERCOM_I2CM_DATA_DATA_Pos)
+#define SERCOM_I2CM_DATA_DATA(value) (SERCOM_I2CM_DATA_DATA_Msk & ((value) << SERCOM_I2CM_DATA_DATA_Pos))
+#define SERCOM_I2CM_DATA_MASK 0xFFul /**< \brief (SERCOM_I2CM_DATA) MASK Register */
+
+/* -------- SERCOM_I2CS_DATA : (SERCOM Offset: 0x28) (R/W 8) I2CS I2CS Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DATA:8; /*!< bit: 0.. 7 Data Value */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_I2CS_DATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CS_DATA_OFFSET 0x28 /**< \brief (SERCOM_I2CS_DATA offset) I2CS Data */
+#define SERCOM_I2CS_DATA_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CS_DATA reset_value) I2CS Data */
+
+#define SERCOM_I2CS_DATA_DATA_Pos 0 /**< \brief (SERCOM_I2CS_DATA) Data Value */
+#define SERCOM_I2CS_DATA_DATA_Msk (0xFFul << SERCOM_I2CS_DATA_DATA_Pos)
+#define SERCOM_I2CS_DATA_DATA(value) (SERCOM_I2CS_DATA_DATA_Msk & ((value) << SERCOM_I2CS_DATA_DATA_Pos))
+#define SERCOM_I2CS_DATA_MASK 0xFFul /**< \brief (SERCOM_I2CS_DATA) MASK Register */
+
+/* -------- SERCOM_SPI_DATA : (SERCOM Offset: 0x28) (R/W 32) SPI SPI Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DATA:9; /*!< bit: 0.. 8 Data Value */
+ uint32_t :23; /*!< bit: 9..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SERCOM_SPI_DATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_DATA_OFFSET 0x28 /**< \brief (SERCOM_SPI_DATA offset) SPI Data */
+#define SERCOM_SPI_DATA_RESETVALUE 0x00000000ul /**< \brief (SERCOM_SPI_DATA reset_value) SPI Data */
+
+#define SERCOM_SPI_DATA_DATA_Pos 0 /**< \brief (SERCOM_SPI_DATA) Data Value */
+#define SERCOM_SPI_DATA_DATA_Msk (0x1FFul << SERCOM_SPI_DATA_DATA_Pos)
+#define SERCOM_SPI_DATA_DATA(value) (SERCOM_SPI_DATA_DATA_Msk & ((value) << SERCOM_SPI_DATA_DATA_Pos))
+#define SERCOM_SPI_DATA_MASK 0x000001FFul /**< \brief (SERCOM_SPI_DATA) MASK Register */
+
+/* -------- SERCOM_USART_DATA : (SERCOM Offset: 0x28) (R/W 16) USART USART Data -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t DATA:9; /*!< bit: 0.. 8 Data Value */
+ uint16_t :7; /*!< bit: 9..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} SERCOM_USART_DATA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_DATA_OFFSET 0x28 /**< \brief (SERCOM_USART_DATA offset) USART Data */
+#define SERCOM_USART_DATA_RESETVALUE 0x0000ul /**< \brief (SERCOM_USART_DATA reset_value) USART Data */
+
+#define SERCOM_USART_DATA_DATA_Pos 0 /**< \brief (SERCOM_USART_DATA) Data Value */
+#define SERCOM_USART_DATA_DATA_Msk (0x1FFul << SERCOM_USART_DATA_DATA_Pos)
+#define SERCOM_USART_DATA_DATA(value) (SERCOM_USART_DATA_DATA_Msk & ((value) << SERCOM_USART_DATA_DATA_Pos))
+#define SERCOM_USART_DATA_MASK 0x01FFul /**< \brief (SERCOM_USART_DATA) MASK Register */
+
+/* -------- SERCOM_I2CM_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) I2CM I2CM Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_I2CM_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_I2CM_DBGCTRL_OFFSET 0x30 /**< \brief (SERCOM_I2CM_DBGCTRL offset) I2CM Debug Control */
+#define SERCOM_I2CM_DBGCTRL_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CM_DBGCTRL reset_value) I2CM Debug Control */
+
+#define SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos 0 /**< \brief (SERCOM_I2CM_DBGCTRL) Debug Mode */
+#define SERCOM_I2CM_DBGCTRL_DBGSTOP (0x1ul << SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos)
+#define SERCOM_I2CM_DBGCTRL_MASK 0x01ul /**< \brief (SERCOM_I2CM_DBGCTRL) MASK Register */
+
+/* -------- SERCOM_SPI_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) SPI SPI Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_SPI_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_SPI_DBGCTRL_OFFSET 0x30 /**< \brief (SERCOM_SPI_DBGCTRL offset) SPI Debug Control */
+#define SERCOM_SPI_DBGCTRL_RESETVALUE 0x00ul /**< \brief (SERCOM_SPI_DBGCTRL reset_value) SPI Debug Control */
+
+#define SERCOM_SPI_DBGCTRL_DBGSTOP_Pos 0 /**< \brief (SERCOM_SPI_DBGCTRL) Debug Mode */
+#define SERCOM_SPI_DBGCTRL_DBGSTOP (0x1ul << SERCOM_SPI_DBGCTRL_DBGSTOP_Pos)
+#define SERCOM_SPI_DBGCTRL_MASK 0x01ul /**< \brief (SERCOM_SPI_DBGCTRL) MASK Register */
+
+/* -------- SERCOM_USART_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) USART USART Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SERCOM_USART_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SERCOM_USART_DBGCTRL_OFFSET 0x30 /**< \brief (SERCOM_USART_DBGCTRL offset) USART Debug Control */
+#define SERCOM_USART_DBGCTRL_RESETVALUE 0x00ul /**< \brief (SERCOM_USART_DBGCTRL reset_value) USART Debug Control */
+
+#define SERCOM_USART_DBGCTRL_DBGSTOP_Pos 0 /**< \brief (SERCOM_USART_DBGCTRL) Debug Mode */
+#define SERCOM_USART_DBGCTRL_DBGSTOP (0x1ul << SERCOM_USART_DBGCTRL_DBGSTOP_Pos)
+#define SERCOM_USART_DBGCTRL_MASK 0x01ul /**< \brief (SERCOM_USART_DBGCTRL) MASK Register */
+
+/** \brief SERCOM_I2CM hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* I2C Master Mode */
+ __IO SERCOM_I2CM_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) I2CM Control A */
+ __IO SERCOM_I2CM_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) I2CM Control B */
+ RoReg8 Reserved1[0x4];
+ __IO SERCOM_I2CM_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 32) I2CM Baud Rate */
+ RoReg8 Reserved2[0x4];
+ __IO SERCOM_I2CM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) I2CM Interrupt Enable Clear */
+ RoReg8 Reserved3[0x1];
+ __IO SERCOM_I2CM_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) I2CM Interrupt Enable Set */
+ RoReg8 Reserved4[0x1];
+ __IO SERCOM_I2CM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) I2CM Interrupt Flag Status and Clear */
+ RoReg8 Reserved5[0x1];
+ __IO SERCOM_I2CM_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) I2CM Status */
+ __I SERCOM_I2CM_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) I2CM Syncbusy */
+ RoReg8 Reserved6[0x4];
+ __IO SERCOM_I2CM_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) I2CM Address */
+ __IO SERCOM_I2CM_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 8) I2CM Data */
+ RoReg8 Reserved7[0x7];
+ __IO SERCOM_I2CM_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) I2CM Debug Control */
+} SercomI2cm;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief SERCOM_I2CS hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* I2C Slave Mode */
+ __IO SERCOM_I2CS_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) I2CS Control A */
+ __IO SERCOM_I2CS_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) I2CS Control B */
+ RoReg8 Reserved1[0xC];
+ __IO SERCOM_I2CS_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) I2CS Interrupt Enable Clear */
+ RoReg8 Reserved2[0x1];
+ __IO SERCOM_I2CS_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) I2CS Interrupt Enable Set */
+ RoReg8 Reserved3[0x1];
+ __IO SERCOM_I2CS_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) I2CS Interrupt Flag Status and Clear */
+ RoReg8 Reserved4[0x1];
+ __IO SERCOM_I2CS_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) I2CS Status */
+ __I SERCOM_I2CS_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) I2CS Syncbusy */
+ RoReg8 Reserved5[0x4];
+ __IO SERCOM_I2CS_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) I2CS Address */
+ __IO SERCOM_I2CS_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 8) I2CS Data */
+} SercomI2cs;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief SERCOM_SPI hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* SPI Mode */
+ __IO SERCOM_SPI_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) SPI Control A */
+ __IO SERCOM_SPI_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) SPI Control B */
+ RoReg8 Reserved1[0x4];
+ __IO SERCOM_SPI_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 8) SPI Baud Rate */
+ RoReg8 Reserved2[0x7];
+ __IO SERCOM_SPI_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) SPI Interrupt Enable Clear */
+ RoReg8 Reserved3[0x1];
+ __IO SERCOM_SPI_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) SPI Interrupt Enable Set */
+ RoReg8 Reserved4[0x1];
+ __IO SERCOM_SPI_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) SPI Interrupt Flag Status and Clear */
+ RoReg8 Reserved5[0x1];
+ __IO SERCOM_SPI_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) SPI Status */
+ __I SERCOM_SPI_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) SPI Syncbusy */
+ RoReg8 Reserved6[0x4];
+ __IO SERCOM_SPI_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) SPI Address */
+ __IO SERCOM_SPI_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 32) SPI Data */
+ RoReg8 Reserved7[0x4];
+ __IO SERCOM_SPI_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) SPI Debug Control */
+} SercomSpi;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief SERCOM_USART hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* USART Mode */
+ __IO SERCOM_USART_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) USART Control A */
+ __IO SERCOM_USART_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) USART Control B */
+ RoReg8 Reserved1[0x4];
+ __IO SERCOM_USART_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 16) USART Baud Rate */
+ __IO SERCOM_USART_RXPL_Type RXPL; /**< \brief Offset: 0x0E (R/W 8) USART Receive Pulse Length */
+ RoReg8 Reserved2[0x5];
+ __IO SERCOM_USART_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) USART Interrupt Enable Clear */
+ RoReg8 Reserved3[0x1];
+ __IO SERCOM_USART_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) USART Interrupt Enable Set */
+ RoReg8 Reserved4[0x1];
+ __IO SERCOM_USART_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) USART Interrupt Flag Status and Clear */
+ RoReg8 Reserved5[0x1];
+ __IO SERCOM_USART_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) USART Status */
+ __I SERCOM_USART_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) USART Syncbusy */
+ RoReg8 Reserved6[0x8];
+ __IO SERCOM_USART_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 16) USART Data */
+ RoReg8 Reserved7[0x6];
+ __IO SERCOM_USART_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) USART Debug Control */
+} SercomUsart;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ SercomI2cm I2CM; /**< \brief Offset: 0x00 I2C Master Mode */
+ SercomI2cs I2CS; /**< \brief Offset: 0x00 I2C Slave Mode */
+ SercomSpi SPI; /**< \brief Offset: 0x00 SPI Mode */
+ SercomUsart USART; /**< \brief Offset: 0x00 USART Mode */
+} Sercom;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_SERCOM_COMPONENT_ */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/component/sysctrl.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/component/sysctrl.h
new file mode 100644
index 0000000000000000000000000000000000000000..3a8d723824d6cb2a0fbef0f07cee5b5fcb9a2ead
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/component/sysctrl.h
@@ -0,0 +1,948 @@
+/**
+ * \file
+ *
+ * \brief Component description for SYSCTRL
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_SYSCTRL_COMPONENT_
+#define _SAMD21_SYSCTRL_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR SYSCTRL */
+/* ========================================================================== */
+/** \addtogroup SAMD21_SYSCTRL System Control */
+/*@{*/
+
+#define SYSCTRL_U2100
+#define REV_SYSCTRL 0x201
+
+/* -------- SYSCTRL_INTENCLR : (SYSCTRL Offset: 0x00) (R/W 32) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready Interrupt Enable */
+ uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready Interrupt Enable */
+ uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready Interrupt Enable */
+ uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready Interrupt Enable */
+ uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready Interrupt Enable */
+ uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds Interrupt Enable */
+ uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine Interrupt Enable */
+ uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse Interrupt Enable */
+ uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped Interrupt Enable */
+ uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready Interrupt Enable */
+ uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection Interrupt Enable */
+ uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready Interrupt Enable */
+ uint32_t :3; /*!< bit: 12..14 Reserved */
+ uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise Interrupt Enable */
+ uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall Interrupt Enable */
+ uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout Interrupt Enable */
+ uint32_t :14; /*!< bit: 18..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SYSCTRL_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_INTENCLR_OFFSET 0x00 /**< \brief (SYSCTRL_INTENCLR offset) Interrupt Enable Clear */
+#define SYSCTRL_INTENCLR_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define SYSCTRL_INTENCLR_XOSCRDY_Pos 0 /**< \brief (SYSCTRL_INTENCLR) XOSC Ready Interrupt Enable */
+#define SYSCTRL_INTENCLR_XOSCRDY (0x1ul << SYSCTRL_INTENCLR_XOSCRDY_Pos)
+#define SYSCTRL_INTENCLR_XOSC32KRDY_Pos 1 /**< \brief (SYSCTRL_INTENCLR) XOSC32K Ready Interrupt Enable */
+#define SYSCTRL_INTENCLR_XOSC32KRDY (0x1ul << SYSCTRL_INTENCLR_XOSC32KRDY_Pos)
+#define SYSCTRL_INTENCLR_OSC32KRDY_Pos 2 /**< \brief (SYSCTRL_INTENCLR) OSC32K Ready Interrupt Enable */
+#define SYSCTRL_INTENCLR_OSC32KRDY (0x1ul << SYSCTRL_INTENCLR_OSC32KRDY_Pos)
+#define SYSCTRL_INTENCLR_OSC8MRDY_Pos 3 /**< \brief (SYSCTRL_INTENCLR) OSC8M Ready Interrupt Enable */
+#define SYSCTRL_INTENCLR_OSC8MRDY (0x1ul << SYSCTRL_INTENCLR_OSC8MRDY_Pos)
+#define SYSCTRL_INTENCLR_DFLLRDY_Pos 4 /**< \brief (SYSCTRL_INTENCLR) DFLL Ready Interrupt Enable */
+#define SYSCTRL_INTENCLR_DFLLRDY (0x1ul << SYSCTRL_INTENCLR_DFLLRDY_Pos)
+#define SYSCTRL_INTENCLR_DFLLOOB_Pos 5 /**< \brief (SYSCTRL_INTENCLR) DFLL Out Of Bounds Interrupt Enable */
+#define SYSCTRL_INTENCLR_DFLLOOB (0x1ul << SYSCTRL_INTENCLR_DFLLOOB_Pos)
+#define SYSCTRL_INTENCLR_DFLLLCKF_Pos 6 /**< \brief (SYSCTRL_INTENCLR) DFLL Lock Fine Interrupt Enable */
+#define SYSCTRL_INTENCLR_DFLLLCKF (0x1ul << SYSCTRL_INTENCLR_DFLLLCKF_Pos)
+#define SYSCTRL_INTENCLR_DFLLLCKC_Pos 7 /**< \brief (SYSCTRL_INTENCLR) DFLL Lock Coarse Interrupt Enable */
+#define SYSCTRL_INTENCLR_DFLLLCKC (0x1ul << SYSCTRL_INTENCLR_DFLLLCKC_Pos)
+#define SYSCTRL_INTENCLR_DFLLRCS_Pos 8 /**< \brief (SYSCTRL_INTENCLR) DFLL Reference Clock Stopped Interrupt Enable */
+#define SYSCTRL_INTENCLR_DFLLRCS (0x1ul << SYSCTRL_INTENCLR_DFLLRCS_Pos)
+#define SYSCTRL_INTENCLR_BOD33RDY_Pos 9 /**< \brief (SYSCTRL_INTENCLR) BOD33 Ready Interrupt Enable */
+#define SYSCTRL_INTENCLR_BOD33RDY (0x1ul << SYSCTRL_INTENCLR_BOD33RDY_Pos)
+#define SYSCTRL_INTENCLR_BOD33DET_Pos 10 /**< \brief (SYSCTRL_INTENCLR) BOD33 Detection Interrupt Enable */
+#define SYSCTRL_INTENCLR_BOD33DET (0x1ul << SYSCTRL_INTENCLR_BOD33DET_Pos)
+#define SYSCTRL_INTENCLR_B33SRDY_Pos 11 /**< \brief (SYSCTRL_INTENCLR) BOD33 Synchronization Ready Interrupt Enable */
+#define SYSCTRL_INTENCLR_B33SRDY (0x1ul << SYSCTRL_INTENCLR_B33SRDY_Pos)
+#define SYSCTRL_INTENCLR_DPLLLCKR_Pos 15 /**< \brief (SYSCTRL_INTENCLR) DPLL Lock Rise Interrupt Enable */
+#define SYSCTRL_INTENCLR_DPLLLCKR (0x1ul << SYSCTRL_INTENCLR_DPLLLCKR_Pos)
+#define SYSCTRL_INTENCLR_DPLLLCKF_Pos 16 /**< \brief (SYSCTRL_INTENCLR) DPLL Lock Fall Interrupt Enable */
+#define SYSCTRL_INTENCLR_DPLLLCKF (0x1ul << SYSCTRL_INTENCLR_DPLLLCKF_Pos)
+#define SYSCTRL_INTENCLR_DPLLLTO_Pos 17 /**< \brief (SYSCTRL_INTENCLR) DPLL Lock Timeout Interrupt Enable */
+#define SYSCTRL_INTENCLR_DPLLLTO (0x1ul << SYSCTRL_INTENCLR_DPLLLTO_Pos)
+#define SYSCTRL_INTENCLR_MASK 0x00038FFFul /**< \brief (SYSCTRL_INTENCLR) MASK Register */
+
+/* -------- SYSCTRL_INTENSET : (SYSCTRL Offset: 0x04) (R/W 32) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready Interrupt Enable */
+ uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready Interrupt Enable */
+ uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready Interrupt Enable */
+ uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready Interrupt Enable */
+ uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready Interrupt Enable */
+ uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds Interrupt Enable */
+ uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine Interrupt Enable */
+ uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse Interrupt Enable */
+ uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped Interrupt Enable */
+ uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready Interrupt Enable */
+ uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection Interrupt Enable */
+ uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready Interrupt Enable */
+ uint32_t :3; /*!< bit: 12..14 Reserved */
+ uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise Interrupt Enable */
+ uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall Interrupt Enable */
+ uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout Interrupt Enable */
+ uint32_t :14; /*!< bit: 18..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SYSCTRL_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_INTENSET_OFFSET 0x04 /**< \brief (SYSCTRL_INTENSET offset) Interrupt Enable Set */
+#define SYSCTRL_INTENSET_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_INTENSET reset_value) Interrupt Enable Set */
+
+#define SYSCTRL_INTENSET_XOSCRDY_Pos 0 /**< \brief (SYSCTRL_INTENSET) XOSC Ready Interrupt Enable */
+#define SYSCTRL_INTENSET_XOSCRDY (0x1ul << SYSCTRL_INTENSET_XOSCRDY_Pos)
+#define SYSCTRL_INTENSET_XOSC32KRDY_Pos 1 /**< \brief (SYSCTRL_INTENSET) XOSC32K Ready Interrupt Enable */
+#define SYSCTRL_INTENSET_XOSC32KRDY (0x1ul << SYSCTRL_INTENSET_XOSC32KRDY_Pos)
+#define SYSCTRL_INTENSET_OSC32KRDY_Pos 2 /**< \brief (SYSCTRL_INTENSET) OSC32K Ready Interrupt Enable */
+#define SYSCTRL_INTENSET_OSC32KRDY (0x1ul << SYSCTRL_INTENSET_OSC32KRDY_Pos)
+#define SYSCTRL_INTENSET_OSC8MRDY_Pos 3 /**< \brief (SYSCTRL_INTENSET) OSC8M Ready Interrupt Enable */
+#define SYSCTRL_INTENSET_OSC8MRDY (0x1ul << SYSCTRL_INTENSET_OSC8MRDY_Pos)
+#define SYSCTRL_INTENSET_DFLLRDY_Pos 4 /**< \brief (SYSCTRL_INTENSET) DFLL Ready Interrupt Enable */
+#define SYSCTRL_INTENSET_DFLLRDY (0x1ul << SYSCTRL_INTENSET_DFLLRDY_Pos)
+#define SYSCTRL_INTENSET_DFLLOOB_Pos 5 /**< \brief (SYSCTRL_INTENSET) DFLL Out Of Bounds Interrupt Enable */
+#define SYSCTRL_INTENSET_DFLLOOB (0x1ul << SYSCTRL_INTENSET_DFLLOOB_Pos)
+#define SYSCTRL_INTENSET_DFLLLCKF_Pos 6 /**< \brief (SYSCTRL_INTENSET) DFLL Lock Fine Interrupt Enable */
+#define SYSCTRL_INTENSET_DFLLLCKF (0x1ul << SYSCTRL_INTENSET_DFLLLCKF_Pos)
+#define SYSCTRL_INTENSET_DFLLLCKC_Pos 7 /**< \brief (SYSCTRL_INTENSET) DFLL Lock Coarse Interrupt Enable */
+#define SYSCTRL_INTENSET_DFLLLCKC (0x1ul << SYSCTRL_INTENSET_DFLLLCKC_Pos)
+#define SYSCTRL_INTENSET_DFLLRCS_Pos 8 /**< \brief (SYSCTRL_INTENSET) DFLL Reference Clock Stopped Interrupt Enable */
+#define SYSCTRL_INTENSET_DFLLRCS (0x1ul << SYSCTRL_INTENSET_DFLLRCS_Pos)
+#define SYSCTRL_INTENSET_BOD33RDY_Pos 9 /**< \brief (SYSCTRL_INTENSET) BOD33 Ready Interrupt Enable */
+#define SYSCTRL_INTENSET_BOD33RDY (0x1ul << SYSCTRL_INTENSET_BOD33RDY_Pos)
+#define SYSCTRL_INTENSET_BOD33DET_Pos 10 /**< \brief (SYSCTRL_INTENSET) BOD33 Detection Interrupt Enable */
+#define SYSCTRL_INTENSET_BOD33DET (0x1ul << SYSCTRL_INTENSET_BOD33DET_Pos)
+#define SYSCTRL_INTENSET_B33SRDY_Pos 11 /**< \brief (SYSCTRL_INTENSET) BOD33 Synchronization Ready Interrupt Enable */
+#define SYSCTRL_INTENSET_B33SRDY (0x1ul << SYSCTRL_INTENSET_B33SRDY_Pos)
+#define SYSCTRL_INTENSET_DPLLLCKR_Pos 15 /**< \brief (SYSCTRL_INTENSET) DPLL Lock Rise Interrupt Enable */
+#define SYSCTRL_INTENSET_DPLLLCKR (0x1ul << SYSCTRL_INTENSET_DPLLLCKR_Pos)
+#define SYSCTRL_INTENSET_DPLLLCKF_Pos 16 /**< \brief (SYSCTRL_INTENSET) DPLL Lock Fall Interrupt Enable */
+#define SYSCTRL_INTENSET_DPLLLCKF (0x1ul << SYSCTRL_INTENSET_DPLLLCKF_Pos)
+#define SYSCTRL_INTENSET_DPLLLTO_Pos 17 /**< \brief (SYSCTRL_INTENSET) DPLL Lock Timeout Interrupt Enable */
+#define SYSCTRL_INTENSET_DPLLLTO (0x1ul << SYSCTRL_INTENSET_DPLLLTO_Pos)
+#define SYSCTRL_INTENSET_MASK 0x00038FFFul /**< \brief (SYSCTRL_INTENSET) MASK Register */
+
+/* -------- SYSCTRL_INTFLAG : (SYSCTRL Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready */
+ __I uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready */
+ __I uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready */
+ __I uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready */
+ __I uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready */
+ __I uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds */
+ __I uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine */
+ __I uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse */
+ __I uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped */
+ __I uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready */
+ __I uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection */
+ __I uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready */
+ __I uint32_t :3; /*!< bit: 12..14 Reserved */
+ __I uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise */
+ __I uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall */
+ __I uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout */
+ __I uint32_t :14; /*!< bit: 18..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SYSCTRL_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_INTFLAG_OFFSET 0x08 /**< \brief (SYSCTRL_INTFLAG offset) Interrupt Flag Status and Clear */
+#define SYSCTRL_INTFLAG_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define SYSCTRL_INTFLAG_XOSCRDY_Pos 0 /**< \brief (SYSCTRL_INTFLAG) XOSC Ready */
+#define SYSCTRL_INTFLAG_XOSCRDY (0x1ul << SYSCTRL_INTFLAG_XOSCRDY_Pos)
+#define SYSCTRL_INTFLAG_XOSC32KRDY_Pos 1 /**< \brief (SYSCTRL_INTFLAG) XOSC32K Ready */
+#define SYSCTRL_INTFLAG_XOSC32KRDY (0x1ul << SYSCTRL_INTFLAG_XOSC32KRDY_Pos)
+#define SYSCTRL_INTFLAG_OSC32KRDY_Pos 2 /**< \brief (SYSCTRL_INTFLAG) OSC32K Ready */
+#define SYSCTRL_INTFLAG_OSC32KRDY (0x1ul << SYSCTRL_INTFLAG_OSC32KRDY_Pos)
+#define SYSCTRL_INTFLAG_OSC8MRDY_Pos 3 /**< \brief (SYSCTRL_INTFLAG) OSC8M Ready */
+#define SYSCTRL_INTFLAG_OSC8MRDY (0x1ul << SYSCTRL_INTFLAG_OSC8MRDY_Pos)
+#define SYSCTRL_INTFLAG_DFLLRDY_Pos 4 /**< \brief (SYSCTRL_INTFLAG) DFLL Ready */
+#define SYSCTRL_INTFLAG_DFLLRDY (0x1ul << SYSCTRL_INTFLAG_DFLLRDY_Pos)
+#define SYSCTRL_INTFLAG_DFLLOOB_Pos 5 /**< \brief (SYSCTRL_INTFLAG) DFLL Out Of Bounds */
+#define SYSCTRL_INTFLAG_DFLLOOB (0x1ul << SYSCTRL_INTFLAG_DFLLOOB_Pos)
+#define SYSCTRL_INTFLAG_DFLLLCKF_Pos 6 /**< \brief (SYSCTRL_INTFLAG) DFLL Lock Fine */
+#define SYSCTRL_INTFLAG_DFLLLCKF (0x1ul << SYSCTRL_INTFLAG_DFLLLCKF_Pos)
+#define SYSCTRL_INTFLAG_DFLLLCKC_Pos 7 /**< \brief (SYSCTRL_INTFLAG) DFLL Lock Coarse */
+#define SYSCTRL_INTFLAG_DFLLLCKC (0x1ul << SYSCTRL_INTFLAG_DFLLLCKC_Pos)
+#define SYSCTRL_INTFLAG_DFLLRCS_Pos 8 /**< \brief (SYSCTRL_INTFLAG) DFLL Reference Clock Stopped */
+#define SYSCTRL_INTFLAG_DFLLRCS (0x1ul << SYSCTRL_INTFLAG_DFLLRCS_Pos)
+#define SYSCTRL_INTFLAG_BOD33RDY_Pos 9 /**< \brief (SYSCTRL_INTFLAG) BOD33 Ready */
+#define SYSCTRL_INTFLAG_BOD33RDY (0x1ul << SYSCTRL_INTFLAG_BOD33RDY_Pos)
+#define SYSCTRL_INTFLAG_BOD33DET_Pos 10 /**< \brief (SYSCTRL_INTFLAG) BOD33 Detection */
+#define SYSCTRL_INTFLAG_BOD33DET (0x1ul << SYSCTRL_INTFLAG_BOD33DET_Pos)
+#define SYSCTRL_INTFLAG_B33SRDY_Pos 11 /**< \brief (SYSCTRL_INTFLAG) BOD33 Synchronization Ready */
+#define SYSCTRL_INTFLAG_B33SRDY (0x1ul << SYSCTRL_INTFLAG_B33SRDY_Pos)
+#define SYSCTRL_INTFLAG_DPLLLCKR_Pos 15 /**< \brief (SYSCTRL_INTFLAG) DPLL Lock Rise */
+#define SYSCTRL_INTFLAG_DPLLLCKR (0x1ul << SYSCTRL_INTFLAG_DPLLLCKR_Pos)
+#define SYSCTRL_INTFLAG_DPLLLCKF_Pos 16 /**< \brief (SYSCTRL_INTFLAG) DPLL Lock Fall */
+#define SYSCTRL_INTFLAG_DPLLLCKF (0x1ul << SYSCTRL_INTFLAG_DPLLLCKF_Pos)
+#define SYSCTRL_INTFLAG_DPLLLTO_Pos 17 /**< \brief (SYSCTRL_INTFLAG) DPLL Lock Timeout */
+#define SYSCTRL_INTFLAG_DPLLLTO (0x1ul << SYSCTRL_INTFLAG_DPLLLTO_Pos)
+#define SYSCTRL_INTFLAG_MASK 0x00038FFFul /**< \brief (SYSCTRL_INTFLAG) MASK Register */
+
+/* -------- SYSCTRL_PCLKSR : (SYSCTRL Offset: 0x0C) (R/ 32) Power and Clocks Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready */
+ uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready */
+ uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready */
+ uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready */
+ uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready */
+ uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds */
+ uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine */
+ uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse */
+ uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped */
+ uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready */
+ uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection */
+ uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready */
+ uint32_t :3; /*!< bit: 12..14 Reserved */
+ uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise */
+ uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall */
+ uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout */
+ uint32_t :14; /*!< bit: 18..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SYSCTRL_PCLKSR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_PCLKSR_OFFSET 0x0C /**< \brief (SYSCTRL_PCLKSR offset) Power and Clocks Status */
+#define SYSCTRL_PCLKSR_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_PCLKSR reset_value) Power and Clocks Status */
+
+#define SYSCTRL_PCLKSR_XOSCRDY_Pos 0 /**< \brief (SYSCTRL_PCLKSR) XOSC Ready */
+#define SYSCTRL_PCLKSR_XOSCRDY (0x1ul << SYSCTRL_PCLKSR_XOSCRDY_Pos)
+#define SYSCTRL_PCLKSR_XOSC32KRDY_Pos 1 /**< \brief (SYSCTRL_PCLKSR) XOSC32K Ready */
+#define SYSCTRL_PCLKSR_XOSC32KRDY (0x1ul << SYSCTRL_PCLKSR_XOSC32KRDY_Pos)
+#define SYSCTRL_PCLKSR_OSC32KRDY_Pos 2 /**< \brief (SYSCTRL_PCLKSR) OSC32K Ready */
+#define SYSCTRL_PCLKSR_OSC32KRDY (0x1ul << SYSCTRL_PCLKSR_OSC32KRDY_Pos)
+#define SYSCTRL_PCLKSR_OSC8MRDY_Pos 3 /**< \brief (SYSCTRL_PCLKSR) OSC8M Ready */
+#define SYSCTRL_PCLKSR_OSC8MRDY (0x1ul << SYSCTRL_PCLKSR_OSC8MRDY_Pos)
+#define SYSCTRL_PCLKSR_DFLLRDY_Pos 4 /**< \brief (SYSCTRL_PCLKSR) DFLL Ready */
+#define SYSCTRL_PCLKSR_DFLLRDY (0x1ul << SYSCTRL_PCLKSR_DFLLRDY_Pos)
+#define SYSCTRL_PCLKSR_DFLLOOB_Pos 5 /**< \brief (SYSCTRL_PCLKSR) DFLL Out Of Bounds */
+#define SYSCTRL_PCLKSR_DFLLOOB (0x1ul << SYSCTRL_PCLKSR_DFLLOOB_Pos)
+#define SYSCTRL_PCLKSR_DFLLLCKF_Pos 6 /**< \brief (SYSCTRL_PCLKSR) DFLL Lock Fine */
+#define SYSCTRL_PCLKSR_DFLLLCKF (0x1ul << SYSCTRL_PCLKSR_DFLLLCKF_Pos)
+#define SYSCTRL_PCLKSR_DFLLLCKC_Pos 7 /**< \brief (SYSCTRL_PCLKSR) DFLL Lock Coarse */
+#define SYSCTRL_PCLKSR_DFLLLCKC (0x1ul << SYSCTRL_PCLKSR_DFLLLCKC_Pos)
+#define SYSCTRL_PCLKSR_DFLLRCS_Pos 8 /**< \brief (SYSCTRL_PCLKSR) DFLL Reference Clock Stopped */
+#define SYSCTRL_PCLKSR_DFLLRCS (0x1ul << SYSCTRL_PCLKSR_DFLLRCS_Pos)
+#define SYSCTRL_PCLKSR_BOD33RDY_Pos 9 /**< \brief (SYSCTRL_PCLKSR) BOD33 Ready */
+#define SYSCTRL_PCLKSR_BOD33RDY (0x1ul << SYSCTRL_PCLKSR_BOD33RDY_Pos)
+#define SYSCTRL_PCLKSR_BOD33DET_Pos 10 /**< \brief (SYSCTRL_PCLKSR) BOD33 Detection */
+#define SYSCTRL_PCLKSR_BOD33DET (0x1ul << SYSCTRL_PCLKSR_BOD33DET_Pos)
+#define SYSCTRL_PCLKSR_B33SRDY_Pos 11 /**< \brief (SYSCTRL_PCLKSR) BOD33 Synchronization Ready */
+#define SYSCTRL_PCLKSR_B33SRDY (0x1ul << SYSCTRL_PCLKSR_B33SRDY_Pos)
+#define SYSCTRL_PCLKSR_DPLLLCKR_Pos 15 /**< \brief (SYSCTRL_PCLKSR) DPLL Lock Rise */
+#define SYSCTRL_PCLKSR_DPLLLCKR (0x1ul << SYSCTRL_PCLKSR_DPLLLCKR_Pos)
+#define SYSCTRL_PCLKSR_DPLLLCKF_Pos 16 /**< \brief (SYSCTRL_PCLKSR) DPLL Lock Fall */
+#define SYSCTRL_PCLKSR_DPLLLCKF (0x1ul << SYSCTRL_PCLKSR_DPLLLCKF_Pos)
+#define SYSCTRL_PCLKSR_DPLLLTO_Pos 17 /**< \brief (SYSCTRL_PCLKSR) DPLL Lock Timeout */
+#define SYSCTRL_PCLKSR_DPLLLTO (0x1ul << SYSCTRL_PCLKSR_DPLLLTO_Pos)
+#define SYSCTRL_PCLKSR_MASK 0x00038FFFul /**< \brief (SYSCTRL_PCLKSR) MASK Register */
+
+/* -------- SYSCTRL_XOSC : (SYSCTRL Offset: 0x10) (R/W 16) External Multipurpose Crystal Oscillator (XOSC) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t :1; /*!< bit: 0 Reserved */
+ uint16_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
+ uint16_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */
+ uint16_t :3; /*!< bit: 3.. 5 Reserved */
+ uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
+ uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
+ uint16_t GAIN:3; /*!< bit: 8..10 Oscillator Gain */
+ uint16_t AMPGC:1; /*!< bit: 11 Automatic Amplitude Gain Control */
+ uint16_t STARTUP:4; /*!< bit: 12..15 Start-Up Time */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} SYSCTRL_XOSC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_XOSC_OFFSET 0x10 /**< \brief (SYSCTRL_XOSC offset) External Multipurpose Crystal Oscillator (XOSC) Control */
+#define SYSCTRL_XOSC_RESETVALUE 0x0080ul /**< \brief (SYSCTRL_XOSC reset_value) External Multipurpose Crystal Oscillator (XOSC) Control */
+
+#define SYSCTRL_XOSC_ENABLE_Pos 1 /**< \brief (SYSCTRL_XOSC) Oscillator Enable */
+#define SYSCTRL_XOSC_ENABLE (0x1ul << SYSCTRL_XOSC_ENABLE_Pos)
+#define SYSCTRL_XOSC_XTALEN_Pos 2 /**< \brief (SYSCTRL_XOSC) Crystal Oscillator Enable */
+#define SYSCTRL_XOSC_XTALEN (0x1ul << SYSCTRL_XOSC_XTALEN_Pos)
+#define SYSCTRL_XOSC_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_XOSC) Run in Standby */
+#define SYSCTRL_XOSC_RUNSTDBY (0x1ul << SYSCTRL_XOSC_RUNSTDBY_Pos)
+#define SYSCTRL_XOSC_ONDEMAND_Pos 7 /**< \brief (SYSCTRL_XOSC) On Demand Control */
+#define SYSCTRL_XOSC_ONDEMAND (0x1ul << SYSCTRL_XOSC_ONDEMAND_Pos)
+#define SYSCTRL_XOSC_GAIN_Pos 8 /**< \brief (SYSCTRL_XOSC) Oscillator Gain */
+#define SYSCTRL_XOSC_GAIN_Msk (0x7ul << SYSCTRL_XOSC_GAIN_Pos)
+#define SYSCTRL_XOSC_GAIN(value) (SYSCTRL_XOSC_GAIN_Msk & ((value) << SYSCTRL_XOSC_GAIN_Pos))
+#define SYSCTRL_XOSC_GAIN_0_Val 0x0ul /**< \brief (SYSCTRL_XOSC) 2MHz */
+#define SYSCTRL_XOSC_GAIN_1_Val 0x1ul /**< \brief (SYSCTRL_XOSC) 4MHz */
+#define SYSCTRL_XOSC_GAIN_2_Val 0x2ul /**< \brief (SYSCTRL_XOSC) 8MHz */
+#define SYSCTRL_XOSC_GAIN_3_Val 0x3ul /**< \brief (SYSCTRL_XOSC) 16MHz */
+#define SYSCTRL_XOSC_GAIN_4_Val 0x4ul /**< \brief (SYSCTRL_XOSC) 30MHz */
+#define SYSCTRL_XOSC_GAIN_0 (SYSCTRL_XOSC_GAIN_0_Val << SYSCTRL_XOSC_GAIN_Pos)
+#define SYSCTRL_XOSC_GAIN_1 (SYSCTRL_XOSC_GAIN_1_Val << SYSCTRL_XOSC_GAIN_Pos)
+#define SYSCTRL_XOSC_GAIN_2 (SYSCTRL_XOSC_GAIN_2_Val << SYSCTRL_XOSC_GAIN_Pos)
+#define SYSCTRL_XOSC_GAIN_3 (SYSCTRL_XOSC_GAIN_3_Val << SYSCTRL_XOSC_GAIN_Pos)
+#define SYSCTRL_XOSC_GAIN_4 (SYSCTRL_XOSC_GAIN_4_Val << SYSCTRL_XOSC_GAIN_Pos)
+#define SYSCTRL_XOSC_AMPGC_Pos 11 /**< \brief (SYSCTRL_XOSC) Automatic Amplitude Gain Control */
+#define SYSCTRL_XOSC_AMPGC (0x1ul << SYSCTRL_XOSC_AMPGC_Pos)
+#define SYSCTRL_XOSC_STARTUP_Pos 12 /**< \brief (SYSCTRL_XOSC) Start-Up Time */
+#define SYSCTRL_XOSC_STARTUP_Msk (0xFul << SYSCTRL_XOSC_STARTUP_Pos)
+#define SYSCTRL_XOSC_STARTUP(value) (SYSCTRL_XOSC_STARTUP_Msk & ((value) << SYSCTRL_XOSC_STARTUP_Pos))
+#define SYSCTRL_XOSC_MASK 0xFFC6ul /**< \brief (SYSCTRL_XOSC) MASK Register */
+
+/* -------- SYSCTRL_XOSC32K : (SYSCTRL Offset: 0x14) (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t :1; /*!< bit: 0 Reserved */
+ uint16_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
+ uint16_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */
+ uint16_t EN32K:1; /*!< bit: 3 32kHz Output Enable */
+ uint16_t EN1K:1; /*!< bit: 4 1kHz Output Enable */
+ uint16_t AAMPEN:1; /*!< bit: 5 Automatic Amplitude Control Enable */
+ uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
+ uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
+ uint16_t STARTUP:3; /*!< bit: 8..10 Oscillator Start-Up Time */
+ uint16_t :1; /*!< bit: 11 Reserved */
+ uint16_t WRTLOCK:1; /*!< bit: 12 Write Lock */
+ uint16_t :3; /*!< bit: 13..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} SYSCTRL_XOSC32K_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_XOSC32K_OFFSET 0x14 /**< \brief (SYSCTRL_XOSC32K offset) 32kHz External Crystal Oscillator (XOSC32K) Control */
+#define SYSCTRL_XOSC32K_RESETVALUE 0x0080ul /**< \brief (SYSCTRL_XOSC32K reset_value) 32kHz External Crystal Oscillator (XOSC32K) Control */
+
+#define SYSCTRL_XOSC32K_ENABLE_Pos 1 /**< \brief (SYSCTRL_XOSC32K) Oscillator Enable */
+#define SYSCTRL_XOSC32K_ENABLE (0x1ul << SYSCTRL_XOSC32K_ENABLE_Pos)
+#define SYSCTRL_XOSC32K_XTALEN_Pos 2 /**< \brief (SYSCTRL_XOSC32K) Crystal Oscillator Enable */
+#define SYSCTRL_XOSC32K_XTALEN (0x1ul << SYSCTRL_XOSC32K_XTALEN_Pos)
+#define SYSCTRL_XOSC32K_EN32K_Pos 3 /**< \brief (SYSCTRL_XOSC32K) 32kHz Output Enable */
+#define SYSCTRL_XOSC32K_EN32K (0x1ul << SYSCTRL_XOSC32K_EN32K_Pos)
+#define SYSCTRL_XOSC32K_EN1K_Pos 4 /**< \brief (SYSCTRL_XOSC32K) 1kHz Output Enable */
+#define SYSCTRL_XOSC32K_EN1K (0x1ul << SYSCTRL_XOSC32K_EN1K_Pos)
+#define SYSCTRL_XOSC32K_AAMPEN_Pos 5 /**< \brief (SYSCTRL_XOSC32K) Automatic Amplitude Control Enable */
+#define SYSCTRL_XOSC32K_AAMPEN (0x1ul << SYSCTRL_XOSC32K_AAMPEN_Pos)
+#define SYSCTRL_XOSC32K_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_XOSC32K) Run in Standby */
+#define SYSCTRL_XOSC32K_RUNSTDBY (0x1ul << SYSCTRL_XOSC32K_RUNSTDBY_Pos)
+#define SYSCTRL_XOSC32K_ONDEMAND_Pos 7 /**< \brief (SYSCTRL_XOSC32K) On Demand Control */
+#define SYSCTRL_XOSC32K_ONDEMAND (0x1ul << SYSCTRL_XOSC32K_ONDEMAND_Pos)
+#define SYSCTRL_XOSC32K_STARTUP_Pos 8 /**< \brief (SYSCTRL_XOSC32K) Oscillator Start-Up Time */
+#define SYSCTRL_XOSC32K_STARTUP_Msk (0x7ul << SYSCTRL_XOSC32K_STARTUP_Pos)
+#define SYSCTRL_XOSC32K_STARTUP(value) (SYSCTRL_XOSC32K_STARTUP_Msk & ((value) << SYSCTRL_XOSC32K_STARTUP_Pos))
+#define SYSCTRL_XOSC32K_WRTLOCK_Pos 12 /**< \brief (SYSCTRL_XOSC32K) Write Lock */
+#define SYSCTRL_XOSC32K_WRTLOCK (0x1ul << SYSCTRL_XOSC32K_WRTLOCK_Pos)
+#define SYSCTRL_XOSC32K_MASK 0x17FEul /**< \brief (SYSCTRL_XOSC32K) MASK Register */
+
+/* -------- SYSCTRL_OSC32K : (SYSCTRL Offset: 0x18) (R/W 32) 32kHz Internal Oscillator (OSC32K) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :1; /*!< bit: 0 Reserved */
+ uint32_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
+ uint32_t EN32K:1; /*!< bit: 2 32kHz Output Enable */
+ uint32_t EN1K:1; /*!< bit: 3 1kHz Output Enable */
+ uint32_t :2; /*!< bit: 4.. 5 Reserved */
+ uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
+ uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
+ uint32_t STARTUP:3; /*!< bit: 8..10 Oscillator Start-Up Time */
+ uint32_t :1; /*!< bit: 11 Reserved */
+ uint32_t WRTLOCK:1; /*!< bit: 12 Write Lock */
+ uint32_t :3; /*!< bit: 13..15 Reserved */
+ uint32_t CALIB:7; /*!< bit: 16..22 Oscillator Calibration */
+ uint32_t :9; /*!< bit: 23..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SYSCTRL_OSC32K_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_OSC32K_OFFSET 0x18 /**< \brief (SYSCTRL_OSC32K offset) 32kHz Internal Oscillator (OSC32K) Control */
+#define SYSCTRL_OSC32K_RESETVALUE 0x003F0080ul /**< \brief (SYSCTRL_OSC32K reset_value) 32kHz Internal Oscillator (OSC32K) Control */
+
+#define SYSCTRL_OSC32K_ENABLE_Pos 1 /**< \brief (SYSCTRL_OSC32K) Oscillator Enable */
+#define SYSCTRL_OSC32K_ENABLE (0x1ul << SYSCTRL_OSC32K_ENABLE_Pos)
+#define SYSCTRL_OSC32K_EN32K_Pos 2 /**< \brief (SYSCTRL_OSC32K) 32kHz Output Enable */
+#define SYSCTRL_OSC32K_EN32K (0x1ul << SYSCTRL_OSC32K_EN32K_Pos)
+#define SYSCTRL_OSC32K_EN1K_Pos 3 /**< \brief (SYSCTRL_OSC32K) 1kHz Output Enable */
+#define SYSCTRL_OSC32K_EN1K (0x1ul << SYSCTRL_OSC32K_EN1K_Pos)
+#define SYSCTRL_OSC32K_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_OSC32K) Run in Standby */
+#define SYSCTRL_OSC32K_RUNSTDBY (0x1ul << SYSCTRL_OSC32K_RUNSTDBY_Pos)
+#define SYSCTRL_OSC32K_ONDEMAND_Pos 7 /**< \brief (SYSCTRL_OSC32K) On Demand Control */
+#define SYSCTRL_OSC32K_ONDEMAND (0x1ul << SYSCTRL_OSC32K_ONDEMAND_Pos)
+#define SYSCTRL_OSC32K_STARTUP_Pos 8 /**< \brief (SYSCTRL_OSC32K) Oscillator Start-Up Time */
+#define SYSCTRL_OSC32K_STARTUP_Msk (0x7ul << SYSCTRL_OSC32K_STARTUP_Pos)
+#define SYSCTRL_OSC32K_STARTUP(value) (SYSCTRL_OSC32K_STARTUP_Msk & ((value) << SYSCTRL_OSC32K_STARTUP_Pos))
+#define SYSCTRL_OSC32K_WRTLOCK_Pos 12 /**< \brief (SYSCTRL_OSC32K) Write Lock */
+#define SYSCTRL_OSC32K_WRTLOCK (0x1ul << SYSCTRL_OSC32K_WRTLOCK_Pos)
+#define SYSCTRL_OSC32K_CALIB_Pos 16 /**< \brief (SYSCTRL_OSC32K) Oscillator Calibration */
+#define SYSCTRL_OSC32K_CALIB_Msk (0x7Ful << SYSCTRL_OSC32K_CALIB_Pos)
+#define SYSCTRL_OSC32K_CALIB(value) (SYSCTRL_OSC32K_CALIB_Msk & ((value) << SYSCTRL_OSC32K_CALIB_Pos))
+#define SYSCTRL_OSC32K_MASK 0x007F17CEul /**< \brief (SYSCTRL_OSC32K) MASK Register */
+
+/* -------- SYSCTRL_OSCULP32K : (SYSCTRL Offset: 0x1C) (R/W 8) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t CALIB:5; /*!< bit: 0.. 4 Oscillator Calibration */
+ uint8_t :2; /*!< bit: 5.. 6 Reserved */
+ uint8_t WRTLOCK:1; /*!< bit: 7 Write Lock */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SYSCTRL_OSCULP32K_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_OSCULP32K_OFFSET 0x1C /**< \brief (SYSCTRL_OSCULP32K offset) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
+#define SYSCTRL_OSCULP32K_RESETVALUE 0x1Ful /**< \brief (SYSCTRL_OSCULP32K reset_value) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
+
+#define SYSCTRL_OSCULP32K_CALIB_Pos 0 /**< \brief (SYSCTRL_OSCULP32K) Oscillator Calibration */
+#define SYSCTRL_OSCULP32K_CALIB_Msk (0x1Ful << SYSCTRL_OSCULP32K_CALIB_Pos)
+#define SYSCTRL_OSCULP32K_CALIB(value) (SYSCTRL_OSCULP32K_CALIB_Msk & ((value) << SYSCTRL_OSCULP32K_CALIB_Pos))
+#define SYSCTRL_OSCULP32K_WRTLOCK_Pos 7 /**< \brief (SYSCTRL_OSCULP32K) Write Lock */
+#define SYSCTRL_OSCULP32K_WRTLOCK (0x1ul << SYSCTRL_OSCULP32K_WRTLOCK_Pos)
+#define SYSCTRL_OSCULP32K_MASK 0x9Ful /**< \brief (SYSCTRL_OSCULP32K) MASK Register */
+
+/* -------- SYSCTRL_OSC8M : (SYSCTRL Offset: 0x20) (R/W 32) 8MHz Internal Oscillator (OSC8M) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :1; /*!< bit: 0 Reserved */
+ uint32_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
+ uint32_t :4; /*!< bit: 2.. 5 Reserved */
+ uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
+ uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
+ uint32_t PRESC:2; /*!< bit: 8.. 9 Oscillator Prescaler */
+ uint32_t :6; /*!< bit: 10..15 Reserved */
+ uint32_t CALIB:12; /*!< bit: 16..27 Oscillator Calibration */
+ uint32_t :2; /*!< bit: 28..29 Reserved */
+ uint32_t FRANGE:2; /*!< bit: 30..31 Oscillator Frequency Range */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SYSCTRL_OSC8M_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_OSC8M_OFFSET 0x20 /**< \brief (SYSCTRL_OSC8M offset) 8MHz Internal Oscillator (OSC8M) Control */
+#define SYSCTRL_OSC8M_RESETVALUE 0x87070382ul /**< \brief (SYSCTRL_OSC8M reset_value) 8MHz Internal Oscillator (OSC8M) Control */
+
+#define SYSCTRL_OSC8M_ENABLE_Pos 1 /**< \brief (SYSCTRL_OSC8M) Oscillator Enable */
+#define SYSCTRL_OSC8M_ENABLE (0x1ul << SYSCTRL_OSC8M_ENABLE_Pos)
+#define SYSCTRL_OSC8M_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_OSC8M) Run in Standby */
+#define SYSCTRL_OSC8M_RUNSTDBY (0x1ul << SYSCTRL_OSC8M_RUNSTDBY_Pos)
+#define SYSCTRL_OSC8M_ONDEMAND_Pos 7 /**< \brief (SYSCTRL_OSC8M) On Demand Control */
+#define SYSCTRL_OSC8M_ONDEMAND (0x1ul << SYSCTRL_OSC8M_ONDEMAND_Pos)
+#define SYSCTRL_OSC8M_PRESC_Pos 8 /**< \brief (SYSCTRL_OSC8M) Oscillator Prescaler */
+#define SYSCTRL_OSC8M_PRESC_Msk (0x3ul << SYSCTRL_OSC8M_PRESC_Pos)
+#define SYSCTRL_OSC8M_PRESC(value) (SYSCTRL_OSC8M_PRESC_Msk & ((value) << SYSCTRL_OSC8M_PRESC_Pos))
+#define SYSCTRL_OSC8M_PRESC_0_Val 0x0ul /**< \brief (SYSCTRL_OSC8M) 1 */
+#define SYSCTRL_OSC8M_PRESC_1_Val 0x1ul /**< \brief (SYSCTRL_OSC8M) 2 */
+#define SYSCTRL_OSC8M_PRESC_2_Val 0x2ul /**< \brief (SYSCTRL_OSC8M) 4 */
+#define SYSCTRL_OSC8M_PRESC_3_Val 0x3ul /**< \brief (SYSCTRL_OSC8M) 8 */
+#define SYSCTRL_OSC8M_PRESC_0 (SYSCTRL_OSC8M_PRESC_0_Val << SYSCTRL_OSC8M_PRESC_Pos)
+#define SYSCTRL_OSC8M_PRESC_1 (SYSCTRL_OSC8M_PRESC_1_Val << SYSCTRL_OSC8M_PRESC_Pos)
+#define SYSCTRL_OSC8M_PRESC_2 (SYSCTRL_OSC8M_PRESC_2_Val << SYSCTRL_OSC8M_PRESC_Pos)
+#define SYSCTRL_OSC8M_PRESC_3 (SYSCTRL_OSC8M_PRESC_3_Val << SYSCTRL_OSC8M_PRESC_Pos)
+#define SYSCTRL_OSC8M_CALIB_Pos 16 /**< \brief (SYSCTRL_OSC8M) Oscillator Calibration */
+#define SYSCTRL_OSC8M_CALIB_Msk (0xFFFul << SYSCTRL_OSC8M_CALIB_Pos)
+#define SYSCTRL_OSC8M_CALIB(value) (SYSCTRL_OSC8M_CALIB_Msk & ((value) << SYSCTRL_OSC8M_CALIB_Pos))
+#define SYSCTRL_OSC8M_FRANGE_Pos 30 /**< \brief (SYSCTRL_OSC8M) Oscillator Frequency Range */
+#define SYSCTRL_OSC8M_FRANGE_Msk (0x3ul << SYSCTRL_OSC8M_FRANGE_Pos)
+#define SYSCTRL_OSC8M_FRANGE(value) (SYSCTRL_OSC8M_FRANGE_Msk & ((value) << SYSCTRL_OSC8M_FRANGE_Pos))
+#define SYSCTRL_OSC8M_FRANGE_0_Val 0x0ul /**< \brief (SYSCTRL_OSC8M) 4 to 6MHz */
+#define SYSCTRL_OSC8M_FRANGE_1_Val 0x1ul /**< \brief (SYSCTRL_OSC8M) 6 to 8MHz */
+#define SYSCTRL_OSC8M_FRANGE_2_Val 0x2ul /**< \brief (SYSCTRL_OSC8M) 8 to 11MHz */
+#define SYSCTRL_OSC8M_FRANGE_3_Val 0x3ul /**< \brief (SYSCTRL_OSC8M) 11 to 15MHz */
+#define SYSCTRL_OSC8M_FRANGE_0 (SYSCTRL_OSC8M_FRANGE_0_Val << SYSCTRL_OSC8M_FRANGE_Pos)
+#define SYSCTRL_OSC8M_FRANGE_1 (SYSCTRL_OSC8M_FRANGE_1_Val << SYSCTRL_OSC8M_FRANGE_Pos)
+#define SYSCTRL_OSC8M_FRANGE_2 (SYSCTRL_OSC8M_FRANGE_2_Val << SYSCTRL_OSC8M_FRANGE_Pos)
+#define SYSCTRL_OSC8M_FRANGE_3 (SYSCTRL_OSC8M_FRANGE_3_Val << SYSCTRL_OSC8M_FRANGE_Pos)
+#define SYSCTRL_OSC8M_MASK 0xCFFF03C2ul /**< \brief (SYSCTRL_OSC8M) MASK Register */
+
+/* -------- SYSCTRL_DFLLCTRL : (SYSCTRL Offset: 0x24) (R/W 16) DFLL48M Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t :1; /*!< bit: 0 Reserved */
+ uint16_t ENABLE:1; /*!< bit: 1 DFLL Enable */
+ uint16_t MODE:1; /*!< bit: 2 Operating Mode Selection */
+ uint16_t STABLE:1; /*!< bit: 3 Stable DFLL Frequency */
+ uint16_t LLAW:1; /*!< bit: 4 Lose Lock After Wake */
+ uint16_t USBCRM:1; /*!< bit: 5 USB Clock Recovery Mode */
+ uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
+ uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
+ uint16_t CCDIS:1; /*!< bit: 8 Chill Cycle Disable */
+ uint16_t QLDIS:1; /*!< bit: 9 Quick Lock Disable */
+ uint16_t BPLCKC:1; /*!< bit: 10 Bypass Coarse Lock */
+ uint16_t WAITLOCK:1; /*!< bit: 11 Wait Lock */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} SYSCTRL_DFLLCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_DFLLCTRL_OFFSET 0x24 /**< \brief (SYSCTRL_DFLLCTRL offset) DFLL48M Control */
+#define SYSCTRL_DFLLCTRL_RESETVALUE 0x0080ul /**< \brief (SYSCTRL_DFLLCTRL reset_value) DFLL48M Control */
+
+#define SYSCTRL_DFLLCTRL_ENABLE_Pos 1 /**< \brief (SYSCTRL_DFLLCTRL) DFLL Enable */
+#define SYSCTRL_DFLLCTRL_ENABLE (0x1ul << SYSCTRL_DFLLCTRL_ENABLE_Pos)
+#define SYSCTRL_DFLLCTRL_MODE_Pos 2 /**< \brief (SYSCTRL_DFLLCTRL) Operating Mode Selection */
+#define SYSCTRL_DFLLCTRL_MODE (0x1ul << SYSCTRL_DFLLCTRL_MODE_Pos)
+#define SYSCTRL_DFLLCTRL_STABLE_Pos 3 /**< \brief (SYSCTRL_DFLLCTRL) Stable DFLL Frequency */
+#define SYSCTRL_DFLLCTRL_STABLE (0x1ul << SYSCTRL_DFLLCTRL_STABLE_Pos)
+#define SYSCTRL_DFLLCTRL_LLAW_Pos 4 /**< \brief (SYSCTRL_DFLLCTRL) Lose Lock After Wake */
+#define SYSCTRL_DFLLCTRL_LLAW (0x1ul << SYSCTRL_DFLLCTRL_LLAW_Pos)
+#define SYSCTRL_DFLLCTRL_USBCRM_Pos 5 /**< \brief (SYSCTRL_DFLLCTRL) USB Clock Recovery Mode */
+#define SYSCTRL_DFLLCTRL_USBCRM (0x1ul << SYSCTRL_DFLLCTRL_USBCRM_Pos)
+#define SYSCTRL_DFLLCTRL_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_DFLLCTRL) Run in Standby */
+#define SYSCTRL_DFLLCTRL_RUNSTDBY (0x1ul << SYSCTRL_DFLLCTRL_RUNSTDBY_Pos)
+#define SYSCTRL_DFLLCTRL_ONDEMAND_Pos 7 /**< \brief (SYSCTRL_DFLLCTRL) On Demand Control */
+#define SYSCTRL_DFLLCTRL_ONDEMAND (0x1ul << SYSCTRL_DFLLCTRL_ONDEMAND_Pos)
+#define SYSCTRL_DFLLCTRL_CCDIS_Pos 8 /**< \brief (SYSCTRL_DFLLCTRL) Chill Cycle Disable */
+#define SYSCTRL_DFLLCTRL_CCDIS (0x1ul << SYSCTRL_DFLLCTRL_CCDIS_Pos)
+#define SYSCTRL_DFLLCTRL_QLDIS_Pos 9 /**< \brief (SYSCTRL_DFLLCTRL) Quick Lock Disable */
+#define SYSCTRL_DFLLCTRL_QLDIS (0x1ul << SYSCTRL_DFLLCTRL_QLDIS_Pos)
+#define SYSCTRL_DFLLCTRL_BPLCKC_Pos 10 /**< \brief (SYSCTRL_DFLLCTRL) Bypass Coarse Lock */
+#define SYSCTRL_DFLLCTRL_BPLCKC (0x1ul << SYSCTRL_DFLLCTRL_BPLCKC_Pos)
+#define SYSCTRL_DFLLCTRL_WAITLOCK_Pos 11 /**< \brief (SYSCTRL_DFLLCTRL) Wait Lock */
+#define SYSCTRL_DFLLCTRL_WAITLOCK (0x1ul << SYSCTRL_DFLLCTRL_WAITLOCK_Pos)
+#define SYSCTRL_DFLLCTRL_MASK 0x0FFEul /**< \brief (SYSCTRL_DFLLCTRL) MASK Register */
+
+/* -------- SYSCTRL_DFLLVAL : (SYSCTRL Offset: 0x28) (R/W 32) DFLL48M Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t FINE:10; /*!< bit: 0.. 9 Fine Value */
+ uint32_t COARSE:6; /*!< bit: 10..15 Coarse Value */
+ uint32_t DIFF:16; /*!< bit: 16..31 Multiplication Ratio Difference */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SYSCTRL_DFLLVAL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_DFLLVAL_OFFSET 0x28 /**< \brief (SYSCTRL_DFLLVAL offset) DFLL48M Value */
+#define SYSCTRL_DFLLVAL_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_DFLLVAL reset_value) DFLL48M Value */
+
+#define SYSCTRL_DFLLVAL_FINE_Pos 0 /**< \brief (SYSCTRL_DFLLVAL) Fine Value */
+#define SYSCTRL_DFLLVAL_FINE_Msk (0x3FFul << SYSCTRL_DFLLVAL_FINE_Pos)
+#define SYSCTRL_DFLLVAL_FINE(value) (SYSCTRL_DFLLVAL_FINE_Msk & ((value) << SYSCTRL_DFLLVAL_FINE_Pos))
+#define SYSCTRL_DFLLVAL_COARSE_Pos 10 /**< \brief (SYSCTRL_DFLLVAL) Coarse Value */
+#define SYSCTRL_DFLLVAL_COARSE_Msk (0x3Ful << SYSCTRL_DFLLVAL_COARSE_Pos)
+#define SYSCTRL_DFLLVAL_COARSE(value) (SYSCTRL_DFLLVAL_COARSE_Msk & ((value) << SYSCTRL_DFLLVAL_COARSE_Pos))
+#define SYSCTRL_DFLLVAL_DIFF_Pos 16 /**< \brief (SYSCTRL_DFLLVAL) Multiplication Ratio Difference */
+#define SYSCTRL_DFLLVAL_DIFF_Msk (0xFFFFul << SYSCTRL_DFLLVAL_DIFF_Pos)
+#define SYSCTRL_DFLLVAL_DIFF(value) (SYSCTRL_DFLLVAL_DIFF_Msk & ((value) << SYSCTRL_DFLLVAL_DIFF_Pos))
+#define SYSCTRL_DFLLVAL_MASK 0xFFFFFFFFul /**< \brief (SYSCTRL_DFLLVAL) MASK Register */
+
+/* -------- SYSCTRL_DFLLMUL : (SYSCTRL Offset: 0x2C) (R/W 32) DFLL48M Multiplier -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t MUL:16; /*!< bit: 0..15 DFLL Multiply Factor */
+ uint32_t FSTEP:10; /*!< bit: 16..25 Fine Maximum Step */
+ uint32_t CSTEP:6; /*!< bit: 26..31 Coarse Maximum Step */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SYSCTRL_DFLLMUL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_DFLLMUL_OFFSET 0x2C /**< \brief (SYSCTRL_DFLLMUL offset) DFLL48M Multiplier */
+#define SYSCTRL_DFLLMUL_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_DFLLMUL reset_value) DFLL48M Multiplier */
+
+#define SYSCTRL_DFLLMUL_MUL_Pos 0 /**< \brief (SYSCTRL_DFLLMUL) DFLL Multiply Factor */
+#define SYSCTRL_DFLLMUL_MUL_Msk (0xFFFFul << SYSCTRL_DFLLMUL_MUL_Pos)
+#define SYSCTRL_DFLLMUL_MUL(value) (SYSCTRL_DFLLMUL_MUL_Msk & ((value) << SYSCTRL_DFLLMUL_MUL_Pos))
+#define SYSCTRL_DFLLMUL_FSTEP_Pos 16 /**< \brief (SYSCTRL_DFLLMUL) Fine Maximum Step */
+#define SYSCTRL_DFLLMUL_FSTEP_Msk (0x3FFul << SYSCTRL_DFLLMUL_FSTEP_Pos)
+#define SYSCTRL_DFLLMUL_FSTEP(value) (SYSCTRL_DFLLMUL_FSTEP_Msk & ((value) << SYSCTRL_DFLLMUL_FSTEP_Pos))
+#define SYSCTRL_DFLLMUL_CSTEP_Pos 26 /**< \brief (SYSCTRL_DFLLMUL) Coarse Maximum Step */
+#define SYSCTRL_DFLLMUL_CSTEP_Msk (0x3Ful << SYSCTRL_DFLLMUL_CSTEP_Pos)
+#define SYSCTRL_DFLLMUL_CSTEP(value) (SYSCTRL_DFLLMUL_CSTEP_Msk & ((value) << SYSCTRL_DFLLMUL_CSTEP_Pos))
+#define SYSCTRL_DFLLMUL_MASK 0xFFFFFFFFul /**< \brief (SYSCTRL_DFLLMUL) MASK Register */
+
+/* -------- SYSCTRL_DFLLSYNC : (SYSCTRL Offset: 0x30) (R/W 8) DFLL48M Synchronization -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t :7; /*!< bit: 0.. 6 Reserved */
+ uint8_t READREQ:1; /*!< bit: 7 Read Request */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SYSCTRL_DFLLSYNC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_DFLLSYNC_OFFSET 0x30 /**< \brief (SYSCTRL_DFLLSYNC offset) DFLL48M Synchronization */
+#define SYSCTRL_DFLLSYNC_RESETVALUE 0x00ul /**< \brief (SYSCTRL_DFLLSYNC reset_value) DFLL48M Synchronization */
+
+#define SYSCTRL_DFLLSYNC_READREQ_Pos 7 /**< \brief (SYSCTRL_DFLLSYNC) Read Request */
+#define SYSCTRL_DFLLSYNC_READREQ (0x1ul << SYSCTRL_DFLLSYNC_READREQ_Pos)
+#define SYSCTRL_DFLLSYNC_MASK 0x80ul /**< \brief (SYSCTRL_DFLLSYNC) MASK Register */
+
+/* -------- SYSCTRL_BOD33 : (SYSCTRL Offset: 0x34) (R/W 32) 3.3V Brown-Out Detector (BOD33) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :1; /*!< bit: 0 Reserved */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable */
+ uint32_t HYST:1; /*!< bit: 2 Hysteresis */
+ uint32_t ACTION:2; /*!< bit: 3.. 4 BOD33 Action */
+ uint32_t :1; /*!< bit: 5 Reserved */
+ uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
+ uint32_t :1; /*!< bit: 7 Reserved */
+ uint32_t MODE:1; /*!< bit: 8 Operation Mode */
+ uint32_t CEN:1; /*!< bit: 9 Clock Enable */
+ uint32_t :2; /*!< bit: 10..11 Reserved */
+ uint32_t PSEL:4; /*!< bit: 12..15 Prescaler Select */
+ uint32_t LEVEL:6; /*!< bit: 16..21 BOD33 Threshold Level */
+ uint32_t :10; /*!< bit: 22..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SYSCTRL_BOD33_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_BOD33_OFFSET 0x34 /**< \brief (SYSCTRL_BOD33 offset) 3.3V Brown-Out Detector (BOD33) Control */
+#define SYSCTRL_BOD33_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_BOD33 reset_value) 3.3V Brown-Out Detector (BOD33) Control */
+
+#define SYSCTRL_BOD33_ENABLE_Pos 1 /**< \brief (SYSCTRL_BOD33) Enable */
+#define SYSCTRL_BOD33_ENABLE (0x1ul << SYSCTRL_BOD33_ENABLE_Pos)
+#define SYSCTRL_BOD33_HYST_Pos 2 /**< \brief (SYSCTRL_BOD33) Hysteresis */
+#define SYSCTRL_BOD33_HYST (0x1ul << SYSCTRL_BOD33_HYST_Pos)
+#define SYSCTRL_BOD33_ACTION_Pos 3 /**< \brief (SYSCTRL_BOD33) BOD33 Action */
+#define SYSCTRL_BOD33_ACTION_Msk (0x3ul << SYSCTRL_BOD33_ACTION_Pos)
+#define SYSCTRL_BOD33_ACTION(value) (SYSCTRL_BOD33_ACTION_Msk & ((value) << SYSCTRL_BOD33_ACTION_Pos))
+#define SYSCTRL_BOD33_ACTION_NONE_Val 0x0ul /**< \brief (SYSCTRL_BOD33) No action */
+#define SYSCTRL_BOD33_ACTION_RESET_Val 0x1ul /**< \brief (SYSCTRL_BOD33) The BOD33 generates a reset */
+#define SYSCTRL_BOD33_ACTION_INTERRUPT_Val 0x2ul /**< \brief (SYSCTRL_BOD33) The BOD33 generates an interrupt */
+#define SYSCTRL_BOD33_ACTION_NONE (SYSCTRL_BOD33_ACTION_NONE_Val << SYSCTRL_BOD33_ACTION_Pos)
+#define SYSCTRL_BOD33_ACTION_RESET (SYSCTRL_BOD33_ACTION_RESET_Val << SYSCTRL_BOD33_ACTION_Pos)
+#define SYSCTRL_BOD33_ACTION_INTERRUPT (SYSCTRL_BOD33_ACTION_INTERRUPT_Val << SYSCTRL_BOD33_ACTION_Pos)
+#define SYSCTRL_BOD33_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_BOD33) Run in Standby */
+#define SYSCTRL_BOD33_RUNSTDBY (0x1ul << SYSCTRL_BOD33_RUNSTDBY_Pos)
+#define SYSCTRL_BOD33_MODE_Pos 8 /**< \brief (SYSCTRL_BOD33) Operation Mode */
+#define SYSCTRL_BOD33_MODE (0x1ul << SYSCTRL_BOD33_MODE_Pos)
+#define SYSCTRL_BOD33_CEN_Pos 9 /**< \brief (SYSCTRL_BOD33) Clock Enable */
+#define SYSCTRL_BOD33_CEN (0x1ul << SYSCTRL_BOD33_CEN_Pos)
+#define SYSCTRL_BOD33_PSEL_Pos 12 /**< \brief (SYSCTRL_BOD33) Prescaler Select */
+#define SYSCTRL_BOD33_PSEL_Msk (0xFul << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL(value) (SYSCTRL_BOD33_PSEL_Msk & ((value) << SYSCTRL_BOD33_PSEL_Pos))
+#define SYSCTRL_BOD33_PSEL_DIV2_Val 0x0ul /**< \brief (SYSCTRL_BOD33) Divide clock by 2 */
+#define SYSCTRL_BOD33_PSEL_DIV4_Val 0x1ul /**< \brief (SYSCTRL_BOD33) Divide clock by 4 */
+#define SYSCTRL_BOD33_PSEL_DIV8_Val 0x2ul /**< \brief (SYSCTRL_BOD33) Divide clock by 8 */
+#define SYSCTRL_BOD33_PSEL_DIV16_Val 0x3ul /**< \brief (SYSCTRL_BOD33) Divide clock by 16 */
+#define SYSCTRL_BOD33_PSEL_DIV32_Val 0x4ul /**< \brief (SYSCTRL_BOD33) Divide clock by 32 */
+#define SYSCTRL_BOD33_PSEL_DIV64_Val 0x5ul /**< \brief (SYSCTRL_BOD33) Divide clock by 64 */
+#define SYSCTRL_BOD33_PSEL_DIV128_Val 0x6ul /**< \brief (SYSCTRL_BOD33) Divide clock by 128 */
+#define SYSCTRL_BOD33_PSEL_DIV256_Val 0x7ul /**< \brief (SYSCTRL_BOD33) Divide clock by 256 */
+#define SYSCTRL_BOD33_PSEL_DIV512_Val 0x8ul /**< \brief (SYSCTRL_BOD33) Divide clock by 512 */
+#define SYSCTRL_BOD33_PSEL_DIV1K_Val 0x9ul /**< \brief (SYSCTRL_BOD33) Divide clock by 1024 */
+#define SYSCTRL_BOD33_PSEL_DIV2K_Val 0xAul /**< \brief (SYSCTRL_BOD33) Divide clock by 2048 */
+#define SYSCTRL_BOD33_PSEL_DIV4K_Val 0xBul /**< \brief (SYSCTRL_BOD33) Divide clock by 4096 */
+#define SYSCTRL_BOD33_PSEL_DIV8K_Val 0xCul /**< \brief (SYSCTRL_BOD33) Divide clock by 8192 */
+#define SYSCTRL_BOD33_PSEL_DIV16K_Val 0xDul /**< \brief (SYSCTRL_BOD33) Divide clock by 16384 */
+#define SYSCTRL_BOD33_PSEL_DIV32K_Val 0xEul /**< \brief (SYSCTRL_BOD33) Divide clock by 32768 */
+#define SYSCTRL_BOD33_PSEL_DIV64K_Val 0xFul /**< \brief (SYSCTRL_BOD33) Divide clock by 65536 */
+#define SYSCTRL_BOD33_PSEL_DIV2 (SYSCTRL_BOD33_PSEL_DIV2_Val << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV4 (SYSCTRL_BOD33_PSEL_DIV4_Val << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV8 (SYSCTRL_BOD33_PSEL_DIV8_Val << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV16 (SYSCTRL_BOD33_PSEL_DIV16_Val << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV32 (SYSCTRL_BOD33_PSEL_DIV32_Val << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV64 (SYSCTRL_BOD33_PSEL_DIV64_Val << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV128 (SYSCTRL_BOD33_PSEL_DIV128_Val << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV256 (SYSCTRL_BOD33_PSEL_DIV256_Val << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV512 (SYSCTRL_BOD33_PSEL_DIV512_Val << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV1K (SYSCTRL_BOD33_PSEL_DIV1K_Val << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV2K (SYSCTRL_BOD33_PSEL_DIV2K_Val << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV4K (SYSCTRL_BOD33_PSEL_DIV4K_Val << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV8K (SYSCTRL_BOD33_PSEL_DIV8K_Val << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV16K (SYSCTRL_BOD33_PSEL_DIV16K_Val << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV32K (SYSCTRL_BOD33_PSEL_DIV32K_Val << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_PSEL_DIV64K (SYSCTRL_BOD33_PSEL_DIV64K_Val << SYSCTRL_BOD33_PSEL_Pos)
+#define SYSCTRL_BOD33_LEVEL_Pos 16 /**< \brief (SYSCTRL_BOD33) BOD33 Threshold Level */
+#define SYSCTRL_BOD33_LEVEL_Msk (0x3Ful << SYSCTRL_BOD33_LEVEL_Pos)
+#define SYSCTRL_BOD33_LEVEL(value) (SYSCTRL_BOD33_LEVEL_Msk & ((value) << SYSCTRL_BOD33_LEVEL_Pos))
+#define SYSCTRL_BOD33_MASK 0x003FF35Eul /**< \brief (SYSCTRL_BOD33) MASK Register */
+
+/* -------- SYSCTRL_VREG : (SYSCTRL Offset: 0x3C) (R/W 16) Voltage Regulator System (VREG) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t :6; /*!< bit: 0.. 5 Reserved */
+ uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
+ uint16_t :6; /*!< bit: 7..12 Reserved */
+ uint16_t FORCELDO:1; /*!< bit: 13 Force LDO Voltage Regulator */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} SYSCTRL_VREG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_VREG_OFFSET 0x3C /**< \brief (SYSCTRL_VREG offset) Voltage Regulator System (VREG) Control */
+#define SYSCTRL_VREG_RESETVALUE 0x0000ul /**< \brief (SYSCTRL_VREG reset_value) Voltage Regulator System (VREG) Control */
+
+#define SYSCTRL_VREG_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_VREG) Run in Standby */
+#define SYSCTRL_VREG_RUNSTDBY (0x1ul << SYSCTRL_VREG_RUNSTDBY_Pos)
+#define SYSCTRL_VREG_FORCELDO_Pos 13 /**< \brief (SYSCTRL_VREG) Force LDO Voltage Regulator */
+#define SYSCTRL_VREG_FORCELDO (0x1ul << SYSCTRL_VREG_FORCELDO_Pos)
+#define SYSCTRL_VREG_MASK 0x2040ul /**< \brief (SYSCTRL_VREG) MASK Register */
+
+/* -------- SYSCTRL_VREF : (SYSCTRL Offset: 0x40) (R/W 32) Voltage References System (VREF) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t :1; /*!< bit: 0 Reserved */
+ uint32_t TSEN:1; /*!< bit: 1 Temperature Sensor Enable */
+ uint32_t BGOUTEN:1; /*!< bit: 2 Bandgap Output Enable */
+ uint32_t :13; /*!< bit: 3..15 Reserved */
+ uint32_t CALIB:11; /*!< bit: 16..26 Bandgap Voltage Generator Calibration */
+ uint32_t :5; /*!< bit: 27..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SYSCTRL_VREF_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_VREF_OFFSET 0x40 /**< \brief (SYSCTRL_VREF offset) Voltage References System (VREF) Control */
+#define SYSCTRL_VREF_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_VREF reset_value) Voltage References System (VREF) Control */
+
+#define SYSCTRL_VREF_TSEN_Pos 1 /**< \brief (SYSCTRL_VREF) Temperature Sensor Enable */
+#define SYSCTRL_VREF_TSEN (0x1ul << SYSCTRL_VREF_TSEN_Pos)
+#define SYSCTRL_VREF_BGOUTEN_Pos 2 /**< \brief (SYSCTRL_VREF) Bandgap Output Enable */
+#define SYSCTRL_VREF_BGOUTEN (0x1ul << SYSCTRL_VREF_BGOUTEN_Pos)
+#define SYSCTRL_VREF_CALIB_Pos 16 /**< \brief (SYSCTRL_VREF) Bandgap Voltage Generator Calibration */
+#define SYSCTRL_VREF_CALIB_Msk (0x7FFul << SYSCTRL_VREF_CALIB_Pos)
+#define SYSCTRL_VREF_CALIB(value) (SYSCTRL_VREF_CALIB_Msk & ((value) << SYSCTRL_VREF_CALIB_Pos))
+#define SYSCTRL_VREF_MASK 0x07FF0006ul /**< \brief (SYSCTRL_VREF) MASK Register */
+
+/* -------- SYSCTRL_DPLLCTRLA : (SYSCTRL Offset: 0x44) (R/W 8) DPLL Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t :1; /*!< bit: 0 Reserved */
+ uint8_t ENABLE:1; /*!< bit: 1 DPLL Enable */
+ uint8_t :4; /*!< bit: 2.. 5 Reserved */
+ uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
+ uint8_t ONDEMAND:1; /*!< bit: 7 On Demand Clock Activation */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SYSCTRL_DPLLCTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_DPLLCTRLA_OFFSET 0x44 /**< \brief (SYSCTRL_DPLLCTRLA offset) DPLL Control A */
+#define SYSCTRL_DPLLCTRLA_RESETVALUE 0x80ul /**< \brief (SYSCTRL_DPLLCTRLA reset_value) DPLL Control A */
+
+#define SYSCTRL_DPLLCTRLA_ENABLE_Pos 1 /**< \brief (SYSCTRL_DPLLCTRLA) DPLL Enable */
+#define SYSCTRL_DPLLCTRLA_ENABLE (0x1ul << SYSCTRL_DPLLCTRLA_ENABLE_Pos)
+#define SYSCTRL_DPLLCTRLA_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_DPLLCTRLA) Run in Standby */
+#define SYSCTRL_DPLLCTRLA_RUNSTDBY (0x1ul << SYSCTRL_DPLLCTRLA_RUNSTDBY_Pos)
+#define SYSCTRL_DPLLCTRLA_ONDEMAND_Pos 7 /**< \brief (SYSCTRL_DPLLCTRLA) On Demand Clock Activation */
+#define SYSCTRL_DPLLCTRLA_ONDEMAND (0x1ul << SYSCTRL_DPLLCTRLA_ONDEMAND_Pos)
+#define SYSCTRL_DPLLCTRLA_MASK 0xC2ul /**< \brief (SYSCTRL_DPLLCTRLA) MASK Register */
+
+/* -------- SYSCTRL_DPLLRATIO : (SYSCTRL Offset: 0x48) (R/W 32) DPLL Ratio Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t LDR:12; /*!< bit: 0..11 Loop Divider Ratio */
+ uint32_t :4; /*!< bit: 12..15 Reserved */
+ uint32_t LDRFRAC:4; /*!< bit: 16..19 Loop Divider Ratio Fractional Part */
+ uint32_t :12; /*!< bit: 20..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SYSCTRL_DPLLRATIO_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_DPLLRATIO_OFFSET 0x48 /**< \brief (SYSCTRL_DPLLRATIO offset) DPLL Ratio Control */
+#define SYSCTRL_DPLLRATIO_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_DPLLRATIO reset_value) DPLL Ratio Control */
+
+#define SYSCTRL_DPLLRATIO_LDR_Pos 0 /**< \brief (SYSCTRL_DPLLRATIO) Loop Divider Ratio */
+#define SYSCTRL_DPLLRATIO_LDR_Msk (0xFFFul << SYSCTRL_DPLLRATIO_LDR_Pos)
+#define SYSCTRL_DPLLRATIO_LDR(value) (SYSCTRL_DPLLRATIO_LDR_Msk & ((value) << SYSCTRL_DPLLRATIO_LDR_Pos))
+#define SYSCTRL_DPLLRATIO_LDRFRAC_Pos 16 /**< \brief (SYSCTRL_DPLLRATIO) Loop Divider Ratio Fractional Part */
+#define SYSCTRL_DPLLRATIO_LDRFRAC_Msk (0xFul << SYSCTRL_DPLLRATIO_LDRFRAC_Pos)
+#define SYSCTRL_DPLLRATIO_LDRFRAC(value) (SYSCTRL_DPLLRATIO_LDRFRAC_Msk & ((value) << SYSCTRL_DPLLRATIO_LDRFRAC_Pos))
+#define SYSCTRL_DPLLRATIO_MASK 0x000F0FFFul /**< \brief (SYSCTRL_DPLLRATIO) MASK Register */
+
+/* -------- SYSCTRL_DPLLCTRLB : (SYSCTRL Offset: 0x4C) (R/W 32) DPLL Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t FILTER:2; /*!< bit: 0.. 1 Proportional Integral Filter Selection */
+ uint32_t LPEN:1; /*!< bit: 2 Low-Power Enable */
+ uint32_t WUF:1; /*!< bit: 3 Wake Up Fast */
+ uint32_t REFCLK:2; /*!< bit: 4.. 5 Reference Clock Selection */
+ uint32_t :2; /*!< bit: 6.. 7 Reserved */
+ uint32_t LTIME:3; /*!< bit: 8..10 Lock Time */
+ uint32_t :1; /*!< bit: 11 Reserved */
+ uint32_t LBYPASS:1; /*!< bit: 12 Lock Bypass */
+ uint32_t :3; /*!< bit: 13..15 Reserved */
+ uint32_t DIV:11; /*!< bit: 16..26 Clock Divider */
+ uint32_t :5; /*!< bit: 27..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} SYSCTRL_DPLLCTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_DPLLCTRLB_OFFSET 0x4C /**< \brief (SYSCTRL_DPLLCTRLB offset) DPLL Control B */
+#define SYSCTRL_DPLLCTRLB_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_DPLLCTRLB reset_value) DPLL Control B */
+
+#define SYSCTRL_DPLLCTRLB_FILTER_Pos 0 /**< \brief (SYSCTRL_DPLLCTRLB) Proportional Integral Filter Selection */
+#define SYSCTRL_DPLLCTRLB_FILTER_Msk (0x3ul << SYSCTRL_DPLLCTRLB_FILTER_Pos)
+#define SYSCTRL_DPLLCTRLB_FILTER(value) (SYSCTRL_DPLLCTRLB_FILTER_Msk & ((value) << SYSCTRL_DPLLCTRLB_FILTER_Pos))
+#define SYSCTRL_DPLLCTRLB_FILTER_DEFAULT_Val 0x0ul /**< \brief (SYSCTRL_DPLLCTRLB) Default filter mode */
+#define SYSCTRL_DPLLCTRLB_FILTER_LBFILT_Val 0x1ul /**< \brief (SYSCTRL_DPLLCTRLB) Low bandwidth filter */
+#define SYSCTRL_DPLLCTRLB_FILTER_HBFILT_Val 0x2ul /**< \brief (SYSCTRL_DPLLCTRLB) High bandwidth filter */
+#define SYSCTRL_DPLLCTRLB_FILTER_HDFILT_Val 0x3ul /**< \brief (SYSCTRL_DPLLCTRLB) High damping filter */
+#define SYSCTRL_DPLLCTRLB_FILTER_DEFAULT (SYSCTRL_DPLLCTRLB_FILTER_DEFAULT_Val << SYSCTRL_DPLLCTRLB_FILTER_Pos)
+#define SYSCTRL_DPLLCTRLB_FILTER_LBFILT (SYSCTRL_DPLLCTRLB_FILTER_LBFILT_Val << SYSCTRL_DPLLCTRLB_FILTER_Pos)
+#define SYSCTRL_DPLLCTRLB_FILTER_HBFILT (SYSCTRL_DPLLCTRLB_FILTER_HBFILT_Val << SYSCTRL_DPLLCTRLB_FILTER_Pos)
+#define SYSCTRL_DPLLCTRLB_FILTER_HDFILT (SYSCTRL_DPLLCTRLB_FILTER_HDFILT_Val << SYSCTRL_DPLLCTRLB_FILTER_Pos)
+#define SYSCTRL_DPLLCTRLB_LPEN_Pos 2 /**< \brief (SYSCTRL_DPLLCTRLB) Low-Power Enable */
+#define SYSCTRL_DPLLCTRLB_LPEN (0x1ul << SYSCTRL_DPLLCTRLB_LPEN_Pos)
+#define SYSCTRL_DPLLCTRLB_WUF_Pos 3 /**< \brief (SYSCTRL_DPLLCTRLB) Wake Up Fast */
+#define SYSCTRL_DPLLCTRLB_WUF (0x1ul << SYSCTRL_DPLLCTRLB_WUF_Pos)
+#define SYSCTRL_DPLLCTRLB_REFCLK_Pos 4 /**< \brief (SYSCTRL_DPLLCTRLB) Reference Clock Selection */
+#define SYSCTRL_DPLLCTRLB_REFCLK_Msk (0x3ul << SYSCTRL_DPLLCTRLB_REFCLK_Pos)
+#define SYSCTRL_DPLLCTRLB_REFCLK(value) (SYSCTRL_DPLLCTRLB_REFCLK_Msk & ((value) << SYSCTRL_DPLLCTRLB_REFCLK_Pos))
+#define SYSCTRL_DPLLCTRLB_REFCLK_REF0_Val 0x0ul /**< \brief (SYSCTRL_DPLLCTRLB) CLK_DPLL_REF0 clock reference */
+#define SYSCTRL_DPLLCTRLB_REFCLK_REF1_Val 0x1ul /**< \brief (SYSCTRL_DPLLCTRLB) CLK_DPLL_REF1 clock reference */
+#define SYSCTRL_DPLLCTRLB_REFCLK_GCLK_Val 0x2ul /**< \brief (SYSCTRL_DPLLCTRLB) GCLK_DPLL clock reference */
+#define SYSCTRL_DPLLCTRLB_REFCLK_REF0 (SYSCTRL_DPLLCTRLB_REFCLK_REF0_Val << SYSCTRL_DPLLCTRLB_REFCLK_Pos)
+#define SYSCTRL_DPLLCTRLB_REFCLK_REF1 (SYSCTRL_DPLLCTRLB_REFCLK_REF1_Val << SYSCTRL_DPLLCTRLB_REFCLK_Pos)
+#define SYSCTRL_DPLLCTRLB_REFCLK_GCLK (SYSCTRL_DPLLCTRLB_REFCLK_GCLK_Val << SYSCTRL_DPLLCTRLB_REFCLK_Pos)
+#define SYSCTRL_DPLLCTRLB_LTIME_Pos 8 /**< \brief (SYSCTRL_DPLLCTRLB) Lock Time */
+#define SYSCTRL_DPLLCTRLB_LTIME_Msk (0x7ul << SYSCTRL_DPLLCTRLB_LTIME_Pos)
+#define SYSCTRL_DPLLCTRLB_LTIME(value) (SYSCTRL_DPLLCTRLB_LTIME_Msk & ((value) << SYSCTRL_DPLLCTRLB_LTIME_Pos))
+#define SYSCTRL_DPLLCTRLB_LTIME_DEFAULT_Val 0x0ul /**< \brief (SYSCTRL_DPLLCTRLB) No time-out */
+#define SYSCTRL_DPLLCTRLB_LTIME_8MS_Val 0x4ul /**< \brief (SYSCTRL_DPLLCTRLB) Time-out if no lock within 8 ms */
+#define SYSCTRL_DPLLCTRLB_LTIME_9MS_Val 0x5ul /**< \brief (SYSCTRL_DPLLCTRLB) Time-out if no lock within 9 ms */
+#define SYSCTRL_DPLLCTRLB_LTIME_10MS_Val 0x6ul /**< \brief (SYSCTRL_DPLLCTRLB) Time-out if no lock within 10 ms */
+#define SYSCTRL_DPLLCTRLB_LTIME_11MS_Val 0x7ul /**< \brief (SYSCTRL_DPLLCTRLB) Time-out if no lock within 11 ms */
+#define SYSCTRL_DPLLCTRLB_LTIME_DEFAULT (SYSCTRL_DPLLCTRLB_LTIME_DEFAULT_Val << SYSCTRL_DPLLCTRLB_LTIME_Pos)
+#define SYSCTRL_DPLLCTRLB_LTIME_8MS (SYSCTRL_DPLLCTRLB_LTIME_8MS_Val << SYSCTRL_DPLLCTRLB_LTIME_Pos)
+#define SYSCTRL_DPLLCTRLB_LTIME_9MS (SYSCTRL_DPLLCTRLB_LTIME_9MS_Val << SYSCTRL_DPLLCTRLB_LTIME_Pos)
+#define SYSCTRL_DPLLCTRLB_LTIME_10MS (SYSCTRL_DPLLCTRLB_LTIME_10MS_Val << SYSCTRL_DPLLCTRLB_LTIME_Pos)
+#define SYSCTRL_DPLLCTRLB_LTIME_11MS (SYSCTRL_DPLLCTRLB_LTIME_11MS_Val << SYSCTRL_DPLLCTRLB_LTIME_Pos)
+#define SYSCTRL_DPLLCTRLB_LBYPASS_Pos 12 /**< \brief (SYSCTRL_DPLLCTRLB) Lock Bypass */
+#define SYSCTRL_DPLLCTRLB_LBYPASS (0x1ul << SYSCTRL_DPLLCTRLB_LBYPASS_Pos)
+#define SYSCTRL_DPLLCTRLB_DIV_Pos 16 /**< \brief (SYSCTRL_DPLLCTRLB) Clock Divider */
+#define SYSCTRL_DPLLCTRLB_DIV_Msk (0x7FFul << SYSCTRL_DPLLCTRLB_DIV_Pos)
+#define SYSCTRL_DPLLCTRLB_DIV(value) (SYSCTRL_DPLLCTRLB_DIV_Msk & ((value) << SYSCTRL_DPLLCTRLB_DIV_Pos))
+#define SYSCTRL_DPLLCTRLB_MASK 0x07FF173Ful /**< \brief (SYSCTRL_DPLLCTRLB) MASK Register */
+
+/* -------- SYSCTRL_DPLLSTATUS : (SYSCTRL Offset: 0x50) (R/ 8) DPLL Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t LOCK:1; /*!< bit: 0 DPLL Lock Status */
+ uint8_t CLKRDY:1; /*!< bit: 1 Output Clock Ready */
+ uint8_t ENABLE:1; /*!< bit: 2 DPLL Enable */
+ uint8_t DIV:1; /*!< bit: 3 Divider Enable */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} SYSCTRL_DPLLSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SYSCTRL_DPLLSTATUS_OFFSET 0x50 /**< \brief (SYSCTRL_DPLLSTATUS offset) DPLL Status */
+#define SYSCTRL_DPLLSTATUS_RESETVALUE 0x00ul /**< \brief (SYSCTRL_DPLLSTATUS reset_value) DPLL Status */
+
+#define SYSCTRL_DPLLSTATUS_LOCK_Pos 0 /**< \brief (SYSCTRL_DPLLSTATUS) DPLL Lock Status */
+#define SYSCTRL_DPLLSTATUS_LOCK (0x1ul << SYSCTRL_DPLLSTATUS_LOCK_Pos)
+#define SYSCTRL_DPLLSTATUS_CLKRDY_Pos 1 /**< \brief (SYSCTRL_DPLLSTATUS) Output Clock Ready */
+#define SYSCTRL_DPLLSTATUS_CLKRDY (0x1ul << SYSCTRL_DPLLSTATUS_CLKRDY_Pos)
+#define SYSCTRL_DPLLSTATUS_ENABLE_Pos 2 /**< \brief (SYSCTRL_DPLLSTATUS) DPLL Enable */
+#define SYSCTRL_DPLLSTATUS_ENABLE (0x1ul << SYSCTRL_DPLLSTATUS_ENABLE_Pos)
+#define SYSCTRL_DPLLSTATUS_DIV_Pos 3 /**< \brief (SYSCTRL_DPLLSTATUS) Divider Enable */
+#define SYSCTRL_DPLLSTATUS_DIV (0x1ul << SYSCTRL_DPLLSTATUS_DIV_Pos)
+#define SYSCTRL_DPLLSTATUS_MASK 0x0Ful /**< \brief (SYSCTRL_DPLLSTATUS) MASK Register */
+
+/** \brief SYSCTRL hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO SYSCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x00 (R/W 32) Interrupt Enable Clear */
+ __IO SYSCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Set */
+ __IO SYSCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear */
+ __I SYSCTRL_PCLKSR_Type PCLKSR; /**< \brief Offset: 0x0C (R/ 32) Power and Clocks Status */
+ __IO SYSCTRL_XOSC_Type XOSC; /**< \brief Offset: 0x10 (R/W 16) External Multipurpose Crystal Oscillator (XOSC) Control */
+ RoReg8 Reserved1[0x2];
+ __IO SYSCTRL_XOSC32K_Type XOSC32K; /**< \brief Offset: 0x14 (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control */
+ RoReg8 Reserved2[0x2];
+ __IO SYSCTRL_OSC32K_Type OSC32K; /**< \brief Offset: 0x18 (R/W 32) 32kHz Internal Oscillator (OSC32K) Control */
+ __IO SYSCTRL_OSCULP32K_Type OSCULP32K; /**< \brief Offset: 0x1C (R/W 8) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
+ RoReg8 Reserved3[0x3];
+ __IO SYSCTRL_OSC8M_Type OSC8M; /**< \brief Offset: 0x20 (R/W 32) 8MHz Internal Oscillator (OSC8M) Control */
+ __IO SYSCTRL_DFLLCTRL_Type DFLLCTRL; /**< \brief Offset: 0x24 (R/W 16) DFLL48M Control */
+ RoReg8 Reserved4[0x2];
+ __IO SYSCTRL_DFLLVAL_Type DFLLVAL; /**< \brief Offset: 0x28 (R/W 32) DFLL48M Value */
+ __IO SYSCTRL_DFLLMUL_Type DFLLMUL; /**< \brief Offset: 0x2C (R/W 32) DFLL48M Multiplier */
+ __IO SYSCTRL_DFLLSYNC_Type DFLLSYNC; /**< \brief Offset: 0x30 (R/W 8) DFLL48M Synchronization */
+ RoReg8 Reserved5[0x3];
+ __IO SYSCTRL_BOD33_Type BOD33; /**< \brief Offset: 0x34 (R/W 32) 3.3V Brown-Out Detector (BOD33) Control */
+ RoReg8 Reserved6[0x4];
+ __IO SYSCTRL_VREG_Type VREG; /**< \brief Offset: 0x3C (R/W 16) Voltage Regulator System (VREG) Control */
+ RoReg8 Reserved7[0x2];
+ __IO SYSCTRL_VREF_Type VREF; /**< \brief Offset: 0x40 (R/W 32) Voltage References System (VREF) Control */
+ __IO SYSCTRL_DPLLCTRLA_Type DPLLCTRLA; /**< \brief Offset: 0x44 (R/W 8) DPLL Control A */
+ RoReg8 Reserved8[0x3];
+ __IO SYSCTRL_DPLLRATIO_Type DPLLRATIO; /**< \brief Offset: 0x48 (R/W 32) DPLL Ratio Control */
+ __IO SYSCTRL_DPLLCTRLB_Type DPLLCTRLB; /**< \brief Offset: 0x4C (R/W 32) DPLL Control B */
+ __I SYSCTRL_DPLLSTATUS_Type DPLLSTATUS; /**< \brief Offset: 0x50 (R/ 8) DPLL Status */
+} Sysctrl;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_SYSCTRL_COMPONENT_ */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/component/tc.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/component/tc.h
new file mode 100644
index 0000000000000000000000000000000000000000..31c3244e921812345e1002c8db440a034ee183d4
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/component/tc.h
@@ -0,0 +1,684 @@
+/**
+ * \file
+ *
+ * \brief Component description for TC
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_TC_COMPONENT_
+#define _SAMD21_TC_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR TC */
+/* ========================================================================== */
+/** \addtogroup SAMD21_TC Basic Timer Counter */
+/*@{*/
+
+#define TC_U2212
+#define REV_TC 0x121
+
+/* -------- TC_CTRLA : (TC Offset: 0x00) (R/W 16) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint16_t ENABLE:1; /*!< bit: 1 Enable */
+ uint16_t MODE:2; /*!< bit: 2.. 3 TC Mode */
+ uint16_t :1; /*!< bit: 4 Reserved */
+ uint16_t WAVEGEN:2; /*!< bit: 5.. 6 Waveform Generation Operation */
+ uint16_t :1; /*!< bit: 7 Reserved */
+ uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler */
+ uint16_t RUNSTDBY:1; /*!< bit: 11 Run in Standby */
+ uint16_t PRESCSYNC:2; /*!< bit: 12..13 Prescaler and Counter Synchronization */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} TC_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_CTRLA_OFFSET 0x00 /**< \brief (TC_CTRLA offset) Control A */
+#define TC_CTRLA_RESETVALUE 0x0000ul /**< \brief (TC_CTRLA reset_value) Control A */
+
+#define TC_CTRLA_SWRST_Pos 0 /**< \brief (TC_CTRLA) Software Reset */
+#define TC_CTRLA_SWRST (0x1ul << TC_CTRLA_SWRST_Pos)
+#define TC_CTRLA_ENABLE_Pos 1 /**< \brief (TC_CTRLA) Enable */
+#define TC_CTRLA_ENABLE (0x1ul << TC_CTRLA_ENABLE_Pos)
+#define TC_CTRLA_MODE_Pos 2 /**< \brief (TC_CTRLA) TC Mode */
+#define TC_CTRLA_MODE_Msk (0x3ul << TC_CTRLA_MODE_Pos)
+#define TC_CTRLA_MODE(value) (TC_CTRLA_MODE_Msk & ((value) << TC_CTRLA_MODE_Pos))
+#define TC_CTRLA_MODE_COUNT16_Val 0x0ul /**< \brief (TC_CTRLA) Counter in 16-bit mode */
+#define TC_CTRLA_MODE_COUNT8_Val 0x1ul /**< \brief (TC_CTRLA) Counter in 8-bit mode */
+#define TC_CTRLA_MODE_COUNT32_Val 0x2ul /**< \brief (TC_CTRLA) Counter in 32-bit mode */
+#define TC_CTRLA_MODE_COUNT16 (TC_CTRLA_MODE_COUNT16_Val << TC_CTRLA_MODE_Pos)
+#define TC_CTRLA_MODE_COUNT8 (TC_CTRLA_MODE_COUNT8_Val << TC_CTRLA_MODE_Pos)
+#define TC_CTRLA_MODE_COUNT32 (TC_CTRLA_MODE_COUNT32_Val << TC_CTRLA_MODE_Pos)
+#define TC_CTRLA_WAVEGEN_Pos 5 /**< \brief (TC_CTRLA) Waveform Generation Operation */
+#define TC_CTRLA_WAVEGEN_Msk (0x3ul << TC_CTRLA_WAVEGEN_Pos)
+#define TC_CTRLA_WAVEGEN(value) (TC_CTRLA_WAVEGEN_Msk & ((value) << TC_CTRLA_WAVEGEN_Pos))
+#define TC_CTRLA_WAVEGEN_NFRQ_Val 0x0ul /**< \brief (TC_CTRLA) */
+#define TC_CTRLA_WAVEGEN_MFRQ_Val 0x1ul /**< \brief (TC_CTRLA) */
+#define TC_CTRLA_WAVEGEN_NPWM_Val 0x2ul /**< \brief (TC_CTRLA) */
+#define TC_CTRLA_WAVEGEN_MPWM_Val 0x3ul /**< \brief (TC_CTRLA) */
+#define TC_CTRLA_WAVEGEN_NFRQ (TC_CTRLA_WAVEGEN_NFRQ_Val << TC_CTRLA_WAVEGEN_Pos)
+#define TC_CTRLA_WAVEGEN_MFRQ (TC_CTRLA_WAVEGEN_MFRQ_Val << TC_CTRLA_WAVEGEN_Pos)
+#define TC_CTRLA_WAVEGEN_NPWM (TC_CTRLA_WAVEGEN_NPWM_Val << TC_CTRLA_WAVEGEN_Pos)
+#define TC_CTRLA_WAVEGEN_MPWM (TC_CTRLA_WAVEGEN_MPWM_Val << TC_CTRLA_WAVEGEN_Pos)
+#define TC_CTRLA_PRESCALER_Pos 8 /**< \brief (TC_CTRLA) Prescaler */
+#define TC_CTRLA_PRESCALER_Msk (0x7ul << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_PRESCALER(value) (TC_CTRLA_PRESCALER_Msk & ((value) << TC_CTRLA_PRESCALER_Pos))
+#define TC_CTRLA_PRESCALER_DIV1_Val 0x0ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC */
+#define TC_CTRLA_PRESCALER_DIV2_Val 0x1ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/2 */
+#define TC_CTRLA_PRESCALER_DIV4_Val 0x2ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/4 */
+#define TC_CTRLA_PRESCALER_DIV8_Val 0x3ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/8 */
+#define TC_CTRLA_PRESCALER_DIV16_Val 0x4ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/16 */
+#define TC_CTRLA_PRESCALER_DIV64_Val 0x5ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/64 */
+#define TC_CTRLA_PRESCALER_DIV256_Val 0x6ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/256 */
+#define TC_CTRLA_PRESCALER_DIV1024_Val 0x7ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/1024 */
+#define TC_CTRLA_PRESCALER_DIV1 (TC_CTRLA_PRESCALER_DIV1_Val << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_PRESCALER_DIV2 (TC_CTRLA_PRESCALER_DIV2_Val << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_PRESCALER_DIV4 (TC_CTRLA_PRESCALER_DIV4_Val << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_PRESCALER_DIV8 (TC_CTRLA_PRESCALER_DIV8_Val << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_PRESCALER_DIV16 (TC_CTRLA_PRESCALER_DIV16_Val << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_PRESCALER_DIV64 (TC_CTRLA_PRESCALER_DIV64_Val << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_PRESCALER_DIV256 (TC_CTRLA_PRESCALER_DIV256_Val << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_PRESCALER_DIV1024 (TC_CTRLA_PRESCALER_DIV1024_Val << TC_CTRLA_PRESCALER_Pos)
+#define TC_CTRLA_RUNSTDBY_Pos 11 /**< \brief (TC_CTRLA) Run in Standby */
+#define TC_CTRLA_RUNSTDBY (0x1ul << TC_CTRLA_RUNSTDBY_Pos)
+#define TC_CTRLA_PRESCSYNC_Pos 12 /**< \brief (TC_CTRLA) Prescaler and Counter Synchronization */
+#define TC_CTRLA_PRESCSYNC_Msk (0x3ul << TC_CTRLA_PRESCSYNC_Pos)
+#define TC_CTRLA_PRESCSYNC(value) (TC_CTRLA_PRESCSYNC_Msk & ((value) << TC_CTRLA_PRESCSYNC_Pos))
+#define TC_CTRLA_PRESCSYNC_GCLK_Val 0x0ul /**< \brief (TC_CTRLA) Reload or reset the counter on next generic clock */
+#define TC_CTRLA_PRESCSYNC_PRESC_Val 0x1ul /**< \brief (TC_CTRLA) Reload or reset the counter on next prescaler clock */
+#define TC_CTRLA_PRESCSYNC_RESYNC_Val 0x2ul /**< \brief (TC_CTRLA) Reload or reset the counter on next generic clock. Reset the prescaler counter */
+#define TC_CTRLA_PRESCSYNC_GCLK (TC_CTRLA_PRESCSYNC_GCLK_Val << TC_CTRLA_PRESCSYNC_Pos)
+#define TC_CTRLA_PRESCSYNC_PRESC (TC_CTRLA_PRESCSYNC_PRESC_Val << TC_CTRLA_PRESCSYNC_Pos)
+#define TC_CTRLA_PRESCSYNC_RESYNC (TC_CTRLA_PRESCSYNC_RESYNC_Val << TC_CTRLA_PRESCSYNC_Pos)
+#define TC_CTRLA_MASK 0x3F6Ful /**< \brief (TC_CTRLA) MASK Register */
+
+/* -------- TC_READREQ : (TC Offset: 0x02) (R/W 16) Read Request -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t ADDR:5; /*!< bit: 0.. 4 Address */
+ uint16_t :9; /*!< bit: 5..13 Reserved */
+ uint16_t RCONT:1; /*!< bit: 14 Read Continuously */
+ uint16_t RREQ:1; /*!< bit: 15 Read Request */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} TC_READREQ_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_READREQ_OFFSET 0x02 /**< \brief (TC_READREQ offset) Read Request */
+#define TC_READREQ_RESETVALUE 0x0000ul /**< \brief (TC_READREQ reset_value) Read Request */
+
+#define TC_READREQ_ADDR_Pos 0 /**< \brief (TC_READREQ) Address */
+#define TC_READREQ_ADDR_Msk (0x1Ful << TC_READREQ_ADDR_Pos)
+#define TC_READREQ_ADDR(value) (TC_READREQ_ADDR_Msk & ((value) << TC_READREQ_ADDR_Pos))
+#define TC_READREQ_RCONT_Pos 14 /**< \brief (TC_READREQ) Read Continuously */
+#define TC_READREQ_RCONT (0x1ul << TC_READREQ_RCONT_Pos)
+#define TC_READREQ_RREQ_Pos 15 /**< \brief (TC_READREQ) Read Request */
+#define TC_READREQ_RREQ (0x1ul << TC_READREQ_RREQ_Pos)
+#define TC_READREQ_MASK 0xC01Ful /**< \brief (TC_READREQ) MASK Register */
+
+/* -------- TC_CTRLBCLR : (TC Offset: 0x04) (R/W 8) Control B Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DIR:1; /*!< bit: 0 Counter Direction */
+ uint8_t :1; /*!< bit: 1 Reserved */
+ uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
+ uint8_t :3; /*!< bit: 3.. 5 Reserved */
+ uint8_t CMD:2; /*!< bit: 6.. 7 Command */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} TC_CTRLBCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_CTRLBCLR_OFFSET 0x04 /**< \brief (TC_CTRLBCLR offset) Control B Clear */
+#define TC_CTRLBCLR_RESETVALUE 0x02ul /**< \brief (TC_CTRLBCLR reset_value) Control B Clear */
+
+#define TC_CTRLBCLR_DIR_Pos 0 /**< \brief (TC_CTRLBCLR) Counter Direction */
+#define TC_CTRLBCLR_DIR (0x1ul << TC_CTRLBCLR_DIR_Pos)
+#define TC_CTRLBCLR_ONESHOT_Pos 2 /**< \brief (TC_CTRLBCLR) One-Shot */
+#define TC_CTRLBCLR_ONESHOT (0x1ul << TC_CTRLBCLR_ONESHOT_Pos)
+#define TC_CTRLBCLR_CMD_Pos 6 /**< \brief (TC_CTRLBCLR) Command */
+#define TC_CTRLBCLR_CMD_Msk (0x3ul << TC_CTRLBCLR_CMD_Pos)
+#define TC_CTRLBCLR_CMD(value) (TC_CTRLBCLR_CMD_Msk & ((value) << TC_CTRLBCLR_CMD_Pos))
+#define TC_CTRLBCLR_CMD_NONE_Val 0x0ul /**< \brief (TC_CTRLBCLR) No action */
+#define TC_CTRLBCLR_CMD_RETRIGGER_Val 0x1ul /**< \brief (TC_CTRLBCLR) Force a start, restart or retrigger */
+#define TC_CTRLBCLR_CMD_STOP_Val 0x2ul /**< \brief (TC_CTRLBCLR) Force a stop */
+#define TC_CTRLBCLR_CMD_NONE (TC_CTRLBCLR_CMD_NONE_Val << TC_CTRLBCLR_CMD_Pos)
+#define TC_CTRLBCLR_CMD_RETRIGGER (TC_CTRLBCLR_CMD_RETRIGGER_Val << TC_CTRLBCLR_CMD_Pos)
+#define TC_CTRLBCLR_CMD_STOP (TC_CTRLBCLR_CMD_STOP_Val << TC_CTRLBCLR_CMD_Pos)
+#define TC_CTRLBCLR_MASK 0xC5ul /**< \brief (TC_CTRLBCLR) MASK Register */
+
+/* -------- TC_CTRLBSET : (TC Offset: 0x05) (R/W 8) Control B Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DIR:1; /*!< bit: 0 Counter Direction */
+ uint8_t :1; /*!< bit: 1 Reserved */
+ uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
+ uint8_t :3; /*!< bit: 3.. 5 Reserved */
+ uint8_t CMD:2; /*!< bit: 6.. 7 Command */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} TC_CTRLBSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_CTRLBSET_OFFSET 0x05 /**< \brief (TC_CTRLBSET offset) Control B Set */
+#define TC_CTRLBSET_RESETVALUE 0x00ul /**< \brief (TC_CTRLBSET reset_value) Control B Set */
+
+#define TC_CTRLBSET_DIR_Pos 0 /**< \brief (TC_CTRLBSET) Counter Direction */
+#define TC_CTRLBSET_DIR (0x1ul << TC_CTRLBSET_DIR_Pos)
+#define TC_CTRLBSET_ONESHOT_Pos 2 /**< \brief (TC_CTRLBSET) One-Shot */
+#define TC_CTRLBSET_ONESHOT (0x1ul << TC_CTRLBSET_ONESHOT_Pos)
+#define TC_CTRLBSET_CMD_Pos 6 /**< \brief (TC_CTRLBSET) Command */
+#define TC_CTRLBSET_CMD_Msk (0x3ul << TC_CTRLBSET_CMD_Pos)
+#define TC_CTRLBSET_CMD(value) (TC_CTRLBSET_CMD_Msk & ((value) << TC_CTRLBSET_CMD_Pos))
+#define TC_CTRLBSET_CMD_NONE_Val 0x0ul /**< \brief (TC_CTRLBSET) No action */
+#define TC_CTRLBSET_CMD_RETRIGGER_Val 0x1ul /**< \brief (TC_CTRLBSET) Force a start, restart or retrigger */
+#define TC_CTRLBSET_CMD_STOP_Val 0x2ul /**< \brief (TC_CTRLBSET) Force a stop */
+#define TC_CTRLBSET_CMD_NONE (TC_CTRLBSET_CMD_NONE_Val << TC_CTRLBSET_CMD_Pos)
+#define TC_CTRLBSET_CMD_RETRIGGER (TC_CTRLBSET_CMD_RETRIGGER_Val << TC_CTRLBSET_CMD_Pos)
+#define TC_CTRLBSET_CMD_STOP (TC_CTRLBSET_CMD_STOP_Val << TC_CTRLBSET_CMD_Pos)
+#define TC_CTRLBSET_MASK 0xC5ul /**< \brief (TC_CTRLBSET) MASK Register */
+
+/* -------- TC_CTRLC : (TC Offset: 0x06) (R/W 8) Control C -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t INVEN0:1; /*!< bit: 0 Output Waveform 0 Invert Enable */
+ uint8_t INVEN1:1; /*!< bit: 1 Output Waveform 1 Invert Enable */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t CPTEN0:1; /*!< bit: 4 Capture Channel 0 Enable */
+ uint8_t CPTEN1:1; /*!< bit: 5 Capture Channel 1 Enable */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t INVEN:2; /*!< bit: 0.. 1 Output Waveform x Invert Enable */
+ uint8_t :2; /*!< bit: 2.. 3 Reserved */
+ uint8_t CPTEN:2; /*!< bit: 4.. 5 Capture Channel x Enable */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} TC_CTRLC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_CTRLC_OFFSET 0x06 /**< \brief (TC_CTRLC offset) Control C */
+#define TC_CTRLC_RESETVALUE 0x00ul /**< \brief (TC_CTRLC reset_value) Control C */
+
+#define TC_CTRLC_INVEN0_Pos 0 /**< \brief (TC_CTRLC) Output Waveform 0 Invert Enable */
+#define TC_CTRLC_INVEN0 (1 << TC_CTRLC_INVEN0_Pos)
+#define TC_CTRLC_INVEN1_Pos 1 /**< \brief (TC_CTRLC) Output Waveform 1 Invert Enable */
+#define TC_CTRLC_INVEN1 (1 << TC_CTRLC_INVEN1_Pos)
+#define TC_CTRLC_INVEN_Pos 0 /**< \brief (TC_CTRLC) Output Waveform x Invert Enable */
+#define TC_CTRLC_INVEN_Msk (0x3ul << TC_CTRLC_INVEN_Pos)
+#define TC_CTRLC_INVEN(value) (TC_CTRLC_INVEN_Msk & ((value) << TC_CTRLC_INVEN_Pos))
+#define TC_CTRLC_CPTEN0_Pos 4 /**< \brief (TC_CTRLC) Capture Channel 0 Enable */
+#define TC_CTRLC_CPTEN0 (1 << TC_CTRLC_CPTEN0_Pos)
+#define TC_CTRLC_CPTEN1_Pos 5 /**< \brief (TC_CTRLC) Capture Channel 1 Enable */
+#define TC_CTRLC_CPTEN1 (1 << TC_CTRLC_CPTEN1_Pos)
+#define TC_CTRLC_CPTEN_Pos 4 /**< \brief (TC_CTRLC) Capture Channel x Enable */
+#define TC_CTRLC_CPTEN_Msk (0x3ul << TC_CTRLC_CPTEN_Pos)
+#define TC_CTRLC_CPTEN(value) (TC_CTRLC_CPTEN_Msk & ((value) << TC_CTRLC_CPTEN_Pos))
+#define TC_CTRLC_MASK 0x33ul /**< \brief (TC_CTRLC) MASK Register */
+
+/* -------- TC_DBGCTRL : (TC Offset: 0x08) (R/W 8) Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DBGRUN:1; /*!< bit: 0 Debug Run Mode */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} TC_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_DBGCTRL_OFFSET 0x08 /**< \brief (TC_DBGCTRL offset) Debug Control */
+#define TC_DBGCTRL_RESETVALUE 0x00ul /**< \brief (TC_DBGCTRL reset_value) Debug Control */
+
+#define TC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (TC_DBGCTRL) Debug Run Mode */
+#define TC_DBGCTRL_DBGRUN (0x1ul << TC_DBGCTRL_DBGRUN_Pos)
+#define TC_DBGCTRL_MASK 0x01ul /**< \brief (TC_DBGCTRL) MASK Register */
+
+/* -------- TC_EVCTRL : (TC Offset: 0x0A) (R/W 16) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t EVACT:3; /*!< bit: 0.. 2 Event Action */
+ uint16_t :1; /*!< bit: 3 Reserved */
+ uint16_t TCINV:1; /*!< bit: 4 TC Inverted Event Input */
+ uint16_t TCEI:1; /*!< bit: 5 TC Event Input */
+ uint16_t :2; /*!< bit: 6.. 7 Reserved */
+ uint16_t OVFEO:1; /*!< bit: 8 Overflow/Underflow Event Output Enable */
+ uint16_t :3; /*!< bit: 9..11 Reserved */
+ uint16_t MCEO0:1; /*!< bit: 12 Match or Capture Channel 0 Event Output Enable */
+ uint16_t MCEO1:1; /*!< bit: 13 Match or Capture Channel 1 Event Output Enable */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t :12; /*!< bit: 0..11 Reserved */
+ uint16_t MCEO:2; /*!< bit: 12..13 Match or Capture Channel x Event Output Enable */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} TC_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_EVCTRL_OFFSET 0x0A /**< \brief (TC_EVCTRL offset) Event Control */
+#define TC_EVCTRL_RESETVALUE 0x0000ul /**< \brief (TC_EVCTRL reset_value) Event Control */
+
+#define TC_EVCTRL_EVACT_Pos 0 /**< \brief (TC_EVCTRL) Event Action */
+#define TC_EVCTRL_EVACT_Msk (0x7ul << TC_EVCTRL_EVACT_Pos)
+#define TC_EVCTRL_EVACT(value) (TC_EVCTRL_EVACT_Msk & ((value) << TC_EVCTRL_EVACT_Pos))
+#define TC_EVCTRL_EVACT_OFF_Val 0x0ul /**< \brief (TC_EVCTRL) Event action disabled */
+#define TC_EVCTRL_EVACT_RETRIGGER_Val 0x1ul /**< \brief (TC_EVCTRL) Start, restart or retrigger TC on event */
+#define TC_EVCTRL_EVACT_COUNT_Val 0x2ul /**< \brief (TC_EVCTRL) Count on event */
+#define TC_EVCTRL_EVACT_START_Val 0x3ul /**< \brief (TC_EVCTRL) Start TC on event */
+#define TC_EVCTRL_EVACT_PPW_Val 0x5ul /**< \brief (TC_EVCTRL) Period captured in CC0, pulse width in CC1 */
+#define TC_EVCTRL_EVACT_PWP_Val 0x6ul /**< \brief (TC_EVCTRL) Period captured in CC1, pulse width in CC0 */
+#define TC_EVCTRL_EVACT_OFF (TC_EVCTRL_EVACT_OFF_Val << TC_EVCTRL_EVACT_Pos)
+#define TC_EVCTRL_EVACT_RETRIGGER (TC_EVCTRL_EVACT_RETRIGGER_Val << TC_EVCTRL_EVACT_Pos)
+#define TC_EVCTRL_EVACT_COUNT (TC_EVCTRL_EVACT_COUNT_Val << TC_EVCTRL_EVACT_Pos)
+#define TC_EVCTRL_EVACT_START (TC_EVCTRL_EVACT_START_Val << TC_EVCTRL_EVACT_Pos)
+#define TC_EVCTRL_EVACT_PPW (TC_EVCTRL_EVACT_PPW_Val << TC_EVCTRL_EVACT_Pos)
+#define TC_EVCTRL_EVACT_PWP (TC_EVCTRL_EVACT_PWP_Val << TC_EVCTRL_EVACT_Pos)
+#define TC_EVCTRL_TCINV_Pos 4 /**< \brief (TC_EVCTRL) TC Inverted Event Input */
+#define TC_EVCTRL_TCINV (0x1ul << TC_EVCTRL_TCINV_Pos)
+#define TC_EVCTRL_TCEI_Pos 5 /**< \brief (TC_EVCTRL) TC Event Input */
+#define TC_EVCTRL_TCEI (0x1ul << TC_EVCTRL_TCEI_Pos)
+#define TC_EVCTRL_OVFEO_Pos 8 /**< \brief (TC_EVCTRL) Overflow/Underflow Event Output Enable */
+#define TC_EVCTRL_OVFEO (0x1ul << TC_EVCTRL_OVFEO_Pos)
+#define TC_EVCTRL_MCEO0_Pos 12 /**< \brief (TC_EVCTRL) Match or Capture Channel 0 Event Output Enable */
+#define TC_EVCTRL_MCEO0 (1 << TC_EVCTRL_MCEO0_Pos)
+#define TC_EVCTRL_MCEO1_Pos 13 /**< \brief (TC_EVCTRL) Match or Capture Channel 1 Event Output Enable */
+#define TC_EVCTRL_MCEO1 (1 << TC_EVCTRL_MCEO1_Pos)
+#define TC_EVCTRL_MCEO_Pos 12 /**< \brief (TC_EVCTRL) Match or Capture Channel x Event Output Enable */
+#define TC_EVCTRL_MCEO_Msk (0x3ul << TC_EVCTRL_MCEO_Pos)
+#define TC_EVCTRL_MCEO(value) (TC_EVCTRL_MCEO_Msk & ((value) << TC_EVCTRL_MCEO_Pos))
+#define TC_EVCTRL_MASK 0x3137ul /**< \brief (TC_EVCTRL) MASK Register */
+
+/* -------- TC_INTENCLR : (TC Offset: 0x0C) (R/W 8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
+ uint8_t ERR:1; /*!< bit: 1 Error Interrupt Enable */
+ uint8_t :1; /*!< bit: 2 Reserved */
+ uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
+ uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 Interrupt Enable */
+ uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 Interrupt Enable */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t :4; /*!< bit: 0.. 3 Reserved */
+ uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x Interrupt Enable */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} TC_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_INTENCLR_OFFSET 0x0C /**< \brief (TC_INTENCLR offset) Interrupt Enable Clear */
+#define TC_INTENCLR_RESETVALUE 0x00ul /**< \brief (TC_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define TC_INTENCLR_OVF_Pos 0 /**< \brief (TC_INTENCLR) Overflow Interrupt Enable */
+#define TC_INTENCLR_OVF (0x1ul << TC_INTENCLR_OVF_Pos)
+#define TC_INTENCLR_ERR_Pos 1 /**< \brief (TC_INTENCLR) Error Interrupt Enable */
+#define TC_INTENCLR_ERR (0x1ul << TC_INTENCLR_ERR_Pos)
+#define TC_INTENCLR_SYNCRDY_Pos 3 /**< \brief (TC_INTENCLR) Synchronization Ready Interrupt Enable */
+#define TC_INTENCLR_SYNCRDY (0x1ul << TC_INTENCLR_SYNCRDY_Pos)
+#define TC_INTENCLR_MC0_Pos 4 /**< \brief (TC_INTENCLR) Match or Capture Channel 0 Interrupt Enable */
+#define TC_INTENCLR_MC0 (1 << TC_INTENCLR_MC0_Pos)
+#define TC_INTENCLR_MC1_Pos 5 /**< \brief (TC_INTENCLR) Match or Capture Channel 1 Interrupt Enable */
+#define TC_INTENCLR_MC1 (1 << TC_INTENCLR_MC1_Pos)
+#define TC_INTENCLR_MC_Pos 4 /**< \brief (TC_INTENCLR) Match or Capture Channel x Interrupt Enable */
+#define TC_INTENCLR_MC_Msk (0x3ul << TC_INTENCLR_MC_Pos)
+#define TC_INTENCLR_MC(value) (TC_INTENCLR_MC_Msk & ((value) << TC_INTENCLR_MC_Pos))
+#define TC_INTENCLR_MASK 0x3Bul /**< \brief (TC_INTENCLR) MASK Register */
+
+/* -------- TC_INTENSET : (TC Offset: 0x0D) (R/W 8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
+ uint8_t ERR:1; /*!< bit: 1 Error Interrupt Enable */
+ uint8_t :1; /*!< bit: 2 Reserved */
+ uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
+ uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 Interrupt Enable */
+ uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 Interrupt Enable */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t :4; /*!< bit: 0.. 3 Reserved */
+ uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x Interrupt Enable */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} TC_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_INTENSET_OFFSET 0x0D /**< \brief (TC_INTENSET offset) Interrupt Enable Set */
+#define TC_INTENSET_RESETVALUE 0x00ul /**< \brief (TC_INTENSET reset_value) Interrupt Enable Set */
+
+#define TC_INTENSET_OVF_Pos 0 /**< \brief (TC_INTENSET) Overflow Interrupt Enable */
+#define TC_INTENSET_OVF (0x1ul << TC_INTENSET_OVF_Pos)
+#define TC_INTENSET_ERR_Pos 1 /**< \brief (TC_INTENSET) Error Interrupt Enable */
+#define TC_INTENSET_ERR (0x1ul << TC_INTENSET_ERR_Pos)
+#define TC_INTENSET_SYNCRDY_Pos 3 /**< \brief (TC_INTENSET) Synchronization Ready Interrupt Enable */
+#define TC_INTENSET_SYNCRDY (0x1ul << TC_INTENSET_SYNCRDY_Pos)
+#define TC_INTENSET_MC0_Pos 4 /**< \brief (TC_INTENSET) Match or Capture Channel 0 Interrupt Enable */
+#define TC_INTENSET_MC0 (1 << TC_INTENSET_MC0_Pos)
+#define TC_INTENSET_MC1_Pos 5 /**< \brief (TC_INTENSET) Match or Capture Channel 1 Interrupt Enable */
+#define TC_INTENSET_MC1 (1 << TC_INTENSET_MC1_Pos)
+#define TC_INTENSET_MC_Pos 4 /**< \brief (TC_INTENSET) Match or Capture Channel x Interrupt Enable */
+#define TC_INTENSET_MC_Msk (0x3ul << TC_INTENSET_MC_Pos)
+#define TC_INTENSET_MC(value) (TC_INTENSET_MC_Msk & ((value) << TC_INTENSET_MC_Pos))
+#define TC_INTENSET_MASK 0x3Bul /**< \brief (TC_INTENSET) MASK Register */
+
+/* -------- TC_INTFLAG : (TC Offset: 0x0E) (R/W 8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint8_t OVF:1; /*!< bit: 0 Overflow */
+ __I uint8_t ERR:1; /*!< bit: 1 Error */
+ __I uint8_t :1; /*!< bit: 2 Reserved */
+ __I uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */
+ __I uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 */
+ __I uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 */
+ __I uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ __I uint8_t :4; /*!< bit: 0.. 3 Reserved */
+ __I uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x */
+ __I uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} TC_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_INTFLAG_OFFSET 0x0E /**< \brief (TC_INTFLAG offset) Interrupt Flag Status and Clear */
+#define TC_INTFLAG_RESETVALUE 0x00ul /**< \brief (TC_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define TC_INTFLAG_OVF_Pos 0 /**< \brief (TC_INTFLAG) Overflow */
+#define TC_INTFLAG_OVF (0x1ul << TC_INTFLAG_OVF_Pos)
+#define TC_INTFLAG_ERR_Pos 1 /**< \brief (TC_INTFLAG) Error */
+#define TC_INTFLAG_ERR (0x1ul << TC_INTFLAG_ERR_Pos)
+#define TC_INTFLAG_SYNCRDY_Pos 3 /**< \brief (TC_INTFLAG) Synchronization Ready */
+#define TC_INTFLAG_SYNCRDY (0x1ul << TC_INTFLAG_SYNCRDY_Pos)
+#define TC_INTFLAG_MC0_Pos 4 /**< \brief (TC_INTFLAG) Match or Capture Channel 0 */
+#define TC_INTFLAG_MC0 (1 << TC_INTFLAG_MC0_Pos)
+#define TC_INTFLAG_MC1_Pos 5 /**< \brief (TC_INTFLAG) Match or Capture Channel 1 */
+#define TC_INTFLAG_MC1 (1 << TC_INTFLAG_MC1_Pos)
+#define TC_INTFLAG_MC_Pos 4 /**< \brief (TC_INTFLAG) Match or Capture Channel x */
+#define TC_INTFLAG_MC_Msk (0x3ul << TC_INTFLAG_MC_Pos)
+#define TC_INTFLAG_MC(value) (TC_INTFLAG_MC_Msk & ((value) << TC_INTFLAG_MC_Pos))
+#define TC_INTFLAG_MASK 0x3Bul /**< \brief (TC_INTFLAG) MASK Register */
+
+/* -------- TC_STATUS : (TC Offset: 0x0F) (R/ 8) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t :3; /*!< bit: 0.. 2 Reserved */
+ uint8_t STOP:1; /*!< bit: 3 Stop */
+ uint8_t SLAVE:1; /*!< bit: 4 Slave */
+ uint8_t :2; /*!< bit: 5.. 6 Reserved */
+ uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} TC_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_STATUS_OFFSET 0x0F /**< \brief (TC_STATUS offset) Status */
+#define TC_STATUS_RESETVALUE 0x08ul /**< \brief (TC_STATUS reset_value) Status */
+
+#define TC_STATUS_STOP_Pos 3 /**< \brief (TC_STATUS) Stop */
+#define TC_STATUS_STOP (0x1ul << TC_STATUS_STOP_Pos)
+#define TC_STATUS_SLAVE_Pos 4 /**< \brief (TC_STATUS) Slave */
+#define TC_STATUS_SLAVE (0x1ul << TC_STATUS_SLAVE_Pos)
+#define TC_STATUS_SYNCBUSY_Pos 7 /**< \brief (TC_STATUS) Synchronization Busy */
+#define TC_STATUS_SYNCBUSY (0x1ul << TC_STATUS_SYNCBUSY_Pos)
+#define TC_STATUS_MASK 0x98ul /**< \brief (TC_STATUS) MASK Register */
+
+/* -------- TC_COUNT16_COUNT : (TC Offset: 0x10) (R/W 16) COUNT16 COUNT16 Counter Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t COUNT:16; /*!< bit: 0..15 Count Value */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} TC_COUNT16_COUNT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT16_COUNT_OFFSET 0x10 /**< \brief (TC_COUNT16_COUNT offset) COUNT16 Counter Value */
+#define TC_COUNT16_COUNT_RESETVALUE 0x0000ul /**< \brief (TC_COUNT16_COUNT reset_value) COUNT16 Counter Value */
+
+#define TC_COUNT16_COUNT_COUNT_Pos 0 /**< \brief (TC_COUNT16_COUNT) Count Value */
+#define TC_COUNT16_COUNT_COUNT_Msk (0xFFFFul << TC_COUNT16_COUNT_COUNT_Pos)
+#define TC_COUNT16_COUNT_COUNT(value) (TC_COUNT16_COUNT_COUNT_Msk & ((value) << TC_COUNT16_COUNT_COUNT_Pos))
+#define TC_COUNT16_COUNT_MASK 0xFFFFul /**< \brief (TC_COUNT16_COUNT) MASK Register */
+
+/* -------- TC_COUNT32_COUNT : (TC Offset: 0x10) (R/W 32) COUNT32 COUNT32 Counter Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t COUNT:32; /*!< bit: 0..31 Count Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} TC_COUNT32_COUNT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT32_COUNT_OFFSET 0x10 /**< \brief (TC_COUNT32_COUNT offset) COUNT32 Counter Value */
+#define TC_COUNT32_COUNT_RESETVALUE 0x00000000ul /**< \brief (TC_COUNT32_COUNT reset_value) COUNT32 Counter Value */
+
+#define TC_COUNT32_COUNT_COUNT_Pos 0 /**< \brief (TC_COUNT32_COUNT) Count Value */
+#define TC_COUNT32_COUNT_COUNT_Msk (0xFFFFFFFFul << TC_COUNT32_COUNT_COUNT_Pos)
+#define TC_COUNT32_COUNT_COUNT(value) (TC_COUNT32_COUNT_COUNT_Msk & ((value) << TC_COUNT32_COUNT_COUNT_Pos))
+#define TC_COUNT32_COUNT_MASK 0xFFFFFFFFul /**< \brief (TC_COUNT32_COUNT) MASK Register */
+
+/* -------- TC_COUNT8_COUNT : (TC Offset: 0x10) (R/W 8) COUNT8 COUNT8 Counter Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t COUNT:8; /*!< bit: 0.. 7 Counter Value */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} TC_COUNT8_COUNT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT8_COUNT_OFFSET 0x10 /**< \brief (TC_COUNT8_COUNT offset) COUNT8 Counter Value */
+#define TC_COUNT8_COUNT_RESETVALUE 0x00ul /**< \brief (TC_COUNT8_COUNT reset_value) COUNT8 Counter Value */
+
+#define TC_COUNT8_COUNT_COUNT_Pos 0 /**< \brief (TC_COUNT8_COUNT) Counter Value */
+#define TC_COUNT8_COUNT_COUNT_Msk (0xFFul << TC_COUNT8_COUNT_COUNT_Pos)
+#define TC_COUNT8_COUNT_COUNT(value) (TC_COUNT8_COUNT_COUNT_Msk & ((value) << TC_COUNT8_COUNT_COUNT_Pos))
+#define TC_COUNT8_COUNT_MASK 0xFFul /**< \brief (TC_COUNT8_COUNT) MASK Register */
+
+/* -------- TC_COUNT8_PER : (TC Offset: 0x14) (R/W 8) COUNT8 COUNT8 Period Value -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t PER:8; /*!< bit: 0.. 7 Period Value */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} TC_COUNT8_PER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT8_PER_OFFSET 0x14 /**< \brief (TC_COUNT8_PER offset) COUNT8 Period Value */
+#define TC_COUNT8_PER_RESETVALUE 0xFFul /**< \brief (TC_COUNT8_PER reset_value) COUNT8 Period Value */
+
+#define TC_COUNT8_PER_PER_Pos 0 /**< \brief (TC_COUNT8_PER) Period Value */
+#define TC_COUNT8_PER_PER_Msk (0xFFul << TC_COUNT8_PER_PER_Pos)
+#define TC_COUNT8_PER_PER(value) (TC_COUNT8_PER_PER_Msk & ((value) << TC_COUNT8_PER_PER_Pos))
+#define TC_COUNT8_PER_MASK 0xFFul /**< \brief (TC_COUNT8_PER) MASK Register */
+
+/* -------- TC_COUNT16_CC : (TC Offset: 0x18) (R/W 16) COUNT16 COUNT16 Compare/Capture -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t CC:16; /*!< bit: 0..15 Compare/Capture Value */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} TC_COUNT16_CC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT16_CC_OFFSET 0x18 /**< \brief (TC_COUNT16_CC offset) COUNT16 Compare/Capture */
+#define TC_COUNT16_CC_RESETVALUE 0x0000ul /**< \brief (TC_COUNT16_CC reset_value) COUNT16 Compare/Capture */
+
+#define TC_COUNT16_CC_CC_Pos 0 /**< \brief (TC_COUNT16_CC) Compare/Capture Value */
+#define TC_COUNT16_CC_CC_Msk (0xFFFFul << TC_COUNT16_CC_CC_Pos)
+#define TC_COUNT16_CC_CC(value) (TC_COUNT16_CC_CC_Msk & ((value) << TC_COUNT16_CC_CC_Pos))
+#define TC_COUNT16_CC_MASK 0xFFFFul /**< \brief (TC_COUNT16_CC) MASK Register */
+
+/* -------- TC_COUNT32_CC : (TC Offset: 0x18) (R/W 32) COUNT32 COUNT32 Compare/Capture -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t CC:32; /*!< bit: 0..31 Compare/Capture Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} TC_COUNT32_CC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT32_CC_OFFSET 0x18 /**< \brief (TC_COUNT32_CC offset) COUNT32 Compare/Capture */
+#define TC_COUNT32_CC_RESETVALUE 0x00000000ul /**< \brief (TC_COUNT32_CC reset_value) COUNT32 Compare/Capture */
+
+#define TC_COUNT32_CC_CC_Pos 0 /**< \brief (TC_COUNT32_CC) Compare/Capture Value */
+#define TC_COUNT32_CC_CC_Msk (0xFFFFFFFFul << TC_COUNT32_CC_CC_Pos)
+#define TC_COUNT32_CC_CC(value) (TC_COUNT32_CC_CC_Msk & ((value) << TC_COUNT32_CC_CC_Pos))
+#define TC_COUNT32_CC_MASK 0xFFFFFFFFul /**< \brief (TC_COUNT32_CC) MASK Register */
+
+/* -------- TC_COUNT8_CC : (TC Offset: 0x18) (R/W 8) COUNT8 COUNT8 Compare/Capture -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t CC:8; /*!< bit: 0.. 7 Compare/Capture Value */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} TC_COUNT8_CC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TC_COUNT8_CC_OFFSET 0x18 /**< \brief (TC_COUNT8_CC offset) COUNT8 Compare/Capture */
+#define TC_COUNT8_CC_RESETVALUE 0x00ul /**< \brief (TC_COUNT8_CC reset_value) COUNT8 Compare/Capture */
+
+#define TC_COUNT8_CC_CC_Pos 0 /**< \brief (TC_COUNT8_CC) Compare/Capture Value */
+#define TC_COUNT8_CC_CC_Msk (0xFFul << TC_COUNT8_CC_CC_Pos)
+#define TC_COUNT8_CC_CC(value) (TC_COUNT8_CC_CC_Msk & ((value) << TC_COUNT8_CC_CC_Pos))
+#define TC_COUNT8_CC_MASK 0xFFul /**< \brief (TC_COUNT8_CC) MASK Register */
+
+/** \brief TC_COUNT8 hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* 8-bit Counter Mode */
+ __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
+ __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
+ __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
+ __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
+ __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */
+ RoReg8 Reserved1[0x1];
+ __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */
+ RoReg8 Reserved2[0x1];
+ __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */
+ __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
+ __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */
+ __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */
+ __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */
+ __IO TC_COUNT8_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 8) COUNT8 Counter Value */
+ RoReg8 Reserved3[0x3];
+ __IO TC_COUNT8_PER_Type PER; /**< \brief Offset: 0x14 (R/W 8) COUNT8 Period Value */
+ RoReg8 Reserved4[0x3];
+ __IO TC_COUNT8_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 8) COUNT8 Compare/Capture */
+} TcCount8;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief TC_COUNT16 hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* 16-bit Counter Mode */
+ __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
+ __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
+ __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
+ __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
+ __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */
+ RoReg8 Reserved1[0x1];
+ __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */
+ RoReg8 Reserved2[0x1];
+ __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */
+ __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
+ __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */
+ __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */
+ __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */
+ __IO TC_COUNT16_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 16) COUNT16 Counter Value */
+ RoReg8 Reserved3[0x6];
+ __IO TC_COUNT16_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 16) COUNT16 Compare/Capture */
+} TcCount16;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief TC_COUNT32 hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* 32-bit Counter Mode */
+ __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
+ __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
+ __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
+ __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
+ __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */
+ RoReg8 Reserved1[0x1];
+ __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */
+ RoReg8 Reserved2[0x1];
+ __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */
+ __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
+ __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */
+ __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */
+ __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */
+ __IO TC_COUNT32_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 32) COUNT32 Counter Value */
+ RoReg8 Reserved3[0x4];
+ __IO TC_COUNT32_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 32) COUNT32 Compare/Capture */
+} TcCount32;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ TcCount8 COUNT8; /**< \brief Offset: 0x00 8-bit Counter Mode */
+ TcCount16 COUNT16; /**< \brief Offset: 0x00 16-bit Counter Mode */
+ TcCount32 COUNT32; /**< \brief Offset: 0x00 32-bit Counter Mode */
+} Tc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_TC_COMPONENT_ */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/component/tcc.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/component/tcc.h
new file mode 100644
index 0000000000000000000000000000000000000000..2243dfbfa2aff682233ae0024f41edae7c0df72c
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/component/tcc.h
@@ -0,0 +1,1817 @@
+/**
+ * \file
+ *
+ * \brief Component description for TCC
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_TCC_COMPONENT_
+#define _SAMD21_TCC_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR TCC */
+/* ========================================================================== */
+/** \addtogroup SAMD21_TCC Timer Counter Control */
+/*@{*/
+
+#define TCC_U2213
+#define REV_TCC 0x101
+
+/* -------- TCC_CTRLA : (TCC Offset: 0x00) (R/W 32) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable */
+ uint32_t :3; /*!< bit: 2.. 4 Reserved */
+ uint32_t RESOLUTION:2; /*!< bit: 5.. 6 Enhanced Resolution */
+ uint32_t :1; /*!< bit: 7 Reserved */
+ uint32_t PRESCALER:3; /*!< bit: 8..10 Prescaler */
+ uint32_t RUNSTDBY:1; /*!< bit: 11 Run in Standby */
+ uint32_t PRESCSYNC:2; /*!< bit: 12..13 Prescaler and Counter Synchronization Selection */
+ uint32_t ALOCK:1; /*!< bit: 14 Auto Lock */
+ uint32_t :9; /*!< bit: 15..23 Reserved */
+ uint32_t CPTEN0:1; /*!< bit: 24 Capture Channel 0 Enable */
+ uint32_t CPTEN1:1; /*!< bit: 25 Capture Channel 1 Enable */
+ uint32_t CPTEN2:1; /*!< bit: 26 Capture Channel 2 Enable */
+ uint32_t CPTEN3:1; /*!< bit: 27 Capture Channel 3 Enable */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :24; /*!< bit: 0..23 Reserved */
+ uint32_t CPTEN:4; /*!< bit: 24..27 Capture Channel x Enable */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_CTRLA_OFFSET 0x00 /**< \brief (TCC_CTRLA offset) Control A */
+#define TCC_CTRLA_RESETVALUE 0x00000000ul /**< \brief (TCC_CTRLA reset_value) Control A */
+
+#define TCC_CTRLA_SWRST_Pos 0 /**< \brief (TCC_CTRLA) Software Reset */
+#define TCC_CTRLA_SWRST (0x1ul << TCC_CTRLA_SWRST_Pos)
+#define TCC_CTRLA_ENABLE_Pos 1 /**< \brief (TCC_CTRLA) Enable */
+#define TCC_CTRLA_ENABLE (0x1ul << TCC_CTRLA_ENABLE_Pos)
+#define TCC_CTRLA_RESOLUTION_Pos 5 /**< \brief (TCC_CTRLA) Enhanced Resolution */
+#define TCC_CTRLA_RESOLUTION_Msk (0x3ul << TCC_CTRLA_RESOLUTION_Pos)
+#define TCC_CTRLA_RESOLUTION(value) (TCC_CTRLA_RESOLUTION_Msk & ((value) << TCC_CTRLA_RESOLUTION_Pos))
+#define TCC_CTRLA_RESOLUTION_NONE_Val 0x0ul /**< \brief (TCC_CTRLA) Dithering is disabled */
+#define TCC_CTRLA_RESOLUTION_DITH4_Val 0x1ul /**< \brief (TCC_CTRLA) Dithering is done every 16 PWM frames */
+#define TCC_CTRLA_RESOLUTION_DITH5_Val 0x2ul /**< \brief (TCC_CTRLA) Dithering is done every 32 PWM frames */
+#define TCC_CTRLA_RESOLUTION_DITH6_Val 0x3ul /**< \brief (TCC_CTRLA) Dithering is done every 64 PWM frames */
+#define TCC_CTRLA_RESOLUTION_NONE (TCC_CTRLA_RESOLUTION_NONE_Val << TCC_CTRLA_RESOLUTION_Pos)
+#define TCC_CTRLA_RESOLUTION_DITH4 (TCC_CTRLA_RESOLUTION_DITH4_Val << TCC_CTRLA_RESOLUTION_Pos)
+#define TCC_CTRLA_RESOLUTION_DITH5 (TCC_CTRLA_RESOLUTION_DITH5_Val << TCC_CTRLA_RESOLUTION_Pos)
+#define TCC_CTRLA_RESOLUTION_DITH6 (TCC_CTRLA_RESOLUTION_DITH6_Val << TCC_CTRLA_RESOLUTION_Pos)
+#define TCC_CTRLA_PRESCALER_Pos 8 /**< \brief (TCC_CTRLA) Prescaler */
+#define TCC_CTRLA_PRESCALER_Msk (0x7ul << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER(value) (TCC_CTRLA_PRESCALER_Msk & ((value) << TCC_CTRLA_PRESCALER_Pos))
+#define TCC_CTRLA_PRESCALER_DIV1_Val 0x0ul /**< \brief (TCC_CTRLA) No division */
+#define TCC_CTRLA_PRESCALER_DIV2_Val 0x1ul /**< \brief (TCC_CTRLA) Divide by 2 */
+#define TCC_CTRLA_PRESCALER_DIV4_Val 0x2ul /**< \brief (TCC_CTRLA) Divide by 4 */
+#define TCC_CTRLA_PRESCALER_DIV8_Val 0x3ul /**< \brief (TCC_CTRLA) Divide by 8 */
+#define TCC_CTRLA_PRESCALER_DIV16_Val 0x4ul /**< \brief (TCC_CTRLA) Divide by 16 */
+#define TCC_CTRLA_PRESCALER_DIV64_Val 0x5ul /**< \brief (TCC_CTRLA) Divide by 64 */
+#define TCC_CTRLA_PRESCALER_DIV256_Val 0x6ul /**< \brief (TCC_CTRLA) Divide by 256 */
+#define TCC_CTRLA_PRESCALER_DIV1024_Val 0x7ul /**< \brief (TCC_CTRLA) Divide by 1024 */
+#define TCC_CTRLA_PRESCALER_DIV1 (TCC_CTRLA_PRESCALER_DIV1_Val << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV2 (TCC_CTRLA_PRESCALER_DIV2_Val << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV4 (TCC_CTRLA_PRESCALER_DIV4_Val << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV8 (TCC_CTRLA_PRESCALER_DIV8_Val << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV16 (TCC_CTRLA_PRESCALER_DIV16_Val << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV64 (TCC_CTRLA_PRESCALER_DIV64_Val << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV256 (TCC_CTRLA_PRESCALER_DIV256_Val << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_PRESCALER_DIV1024 (TCC_CTRLA_PRESCALER_DIV1024_Val << TCC_CTRLA_PRESCALER_Pos)
+#define TCC_CTRLA_RUNSTDBY_Pos 11 /**< \brief (TCC_CTRLA) Run in Standby */
+#define TCC_CTRLA_RUNSTDBY (0x1ul << TCC_CTRLA_RUNSTDBY_Pos)
+#define TCC_CTRLA_PRESCSYNC_Pos 12 /**< \brief (TCC_CTRLA) Prescaler and Counter Synchronization Selection */
+#define TCC_CTRLA_PRESCSYNC_Msk (0x3ul << TCC_CTRLA_PRESCSYNC_Pos)
+#define TCC_CTRLA_PRESCSYNC(value) (TCC_CTRLA_PRESCSYNC_Msk & ((value) << TCC_CTRLA_PRESCSYNC_Pos))
+#define TCC_CTRLA_PRESCSYNC_GCLK_Val 0x0ul /**< \brief (TCC_CTRLA) Reload or reset counter on next GCLK */
+#define TCC_CTRLA_PRESCSYNC_PRESC_Val 0x1ul /**< \brief (TCC_CTRLA) Reload or reset counter on next prescaler clock */
+#define TCC_CTRLA_PRESCSYNC_RESYNC_Val 0x2ul /**< \brief (TCC_CTRLA) Reload or reset counter on next GCLK and reset prescaler counter */
+#define TCC_CTRLA_PRESCSYNC_GCLK (TCC_CTRLA_PRESCSYNC_GCLK_Val << TCC_CTRLA_PRESCSYNC_Pos)
+#define TCC_CTRLA_PRESCSYNC_PRESC (TCC_CTRLA_PRESCSYNC_PRESC_Val << TCC_CTRLA_PRESCSYNC_Pos)
+#define TCC_CTRLA_PRESCSYNC_RESYNC (TCC_CTRLA_PRESCSYNC_RESYNC_Val << TCC_CTRLA_PRESCSYNC_Pos)
+#define TCC_CTRLA_ALOCK_Pos 14 /**< \brief (TCC_CTRLA) Auto Lock */
+#define TCC_CTRLA_ALOCK (0x1ul << TCC_CTRLA_ALOCK_Pos)
+#define TCC_CTRLA_CPTEN0_Pos 24 /**< \brief (TCC_CTRLA) Capture Channel 0 Enable */
+#define TCC_CTRLA_CPTEN0 (1 << TCC_CTRLA_CPTEN0_Pos)
+#define TCC_CTRLA_CPTEN1_Pos 25 /**< \brief (TCC_CTRLA) Capture Channel 1 Enable */
+#define TCC_CTRLA_CPTEN1 (1 << TCC_CTRLA_CPTEN1_Pos)
+#define TCC_CTRLA_CPTEN2_Pos 26 /**< \brief (TCC_CTRLA) Capture Channel 2 Enable */
+#define TCC_CTRLA_CPTEN2 (1 << TCC_CTRLA_CPTEN2_Pos)
+#define TCC_CTRLA_CPTEN3_Pos 27 /**< \brief (TCC_CTRLA) Capture Channel 3 Enable */
+#define TCC_CTRLA_CPTEN3 (1 << TCC_CTRLA_CPTEN3_Pos)
+#define TCC_CTRLA_CPTEN_Pos 24 /**< \brief (TCC_CTRLA) Capture Channel x Enable */
+#define TCC_CTRLA_CPTEN_Msk (0xFul << TCC_CTRLA_CPTEN_Pos)
+#define TCC_CTRLA_CPTEN(value) (TCC_CTRLA_CPTEN_Msk & ((value) << TCC_CTRLA_CPTEN_Pos))
+#define TCC_CTRLA_MASK 0x0F007F63ul /**< \brief (TCC_CTRLA) MASK Register */
+
+/* -------- TCC_CTRLBCLR : (TCC Offset: 0x04) (R/W 8) Control B Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DIR:1; /*!< bit: 0 Counter Direction */
+ uint8_t LUPD:1; /*!< bit: 1 Lock Update */
+ uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
+ uint8_t IDXCMD:2; /*!< bit: 3.. 4 Ramp Index Command */
+ uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} TCC_CTRLBCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_CTRLBCLR_OFFSET 0x04 /**< \brief (TCC_CTRLBCLR offset) Control B Clear */
+#define TCC_CTRLBCLR_RESETVALUE 0x00ul /**< \brief (TCC_CTRLBCLR reset_value) Control B Clear */
+
+#define TCC_CTRLBCLR_DIR_Pos 0 /**< \brief (TCC_CTRLBCLR) Counter Direction */
+#define TCC_CTRLBCLR_DIR (0x1ul << TCC_CTRLBCLR_DIR_Pos)
+#define TCC_CTRLBCLR_LUPD_Pos 1 /**< \brief (TCC_CTRLBCLR) Lock Update */
+#define TCC_CTRLBCLR_LUPD (0x1ul << TCC_CTRLBCLR_LUPD_Pos)
+#define TCC_CTRLBCLR_ONESHOT_Pos 2 /**< \brief (TCC_CTRLBCLR) One-Shot */
+#define TCC_CTRLBCLR_ONESHOT (0x1ul << TCC_CTRLBCLR_ONESHOT_Pos)
+#define TCC_CTRLBCLR_IDXCMD_Pos 3 /**< \brief (TCC_CTRLBCLR) Ramp Index Command */
+#define TCC_CTRLBCLR_IDXCMD_Msk (0x3ul << TCC_CTRLBCLR_IDXCMD_Pos)
+#define TCC_CTRLBCLR_IDXCMD(value) (TCC_CTRLBCLR_IDXCMD_Msk & ((value) << TCC_CTRLBCLR_IDXCMD_Pos))
+#define TCC_CTRLBCLR_IDXCMD_DISABLE_Val 0x0ul /**< \brief (TCC_CTRLBCLR) Command disabled: Index toggles between cycles A and B */
+#define TCC_CTRLBCLR_IDXCMD_SET_Val 0x1ul /**< \brief (TCC_CTRLBCLR) Set index: cycle B will be forced in the next cycle */
+#define TCC_CTRLBCLR_IDXCMD_CLEAR_Val 0x2ul /**< \brief (TCC_CTRLBCLR) Clear index: cycle A will be forced in the next cycle */
+#define TCC_CTRLBCLR_IDXCMD_HOLD_Val 0x3ul /**< \brief (TCC_CTRLBCLR) Hold index: the next cycle will be the same as the current cycle */
+#define TCC_CTRLBCLR_IDXCMD_DISABLE (TCC_CTRLBCLR_IDXCMD_DISABLE_Val << TCC_CTRLBCLR_IDXCMD_Pos)
+#define TCC_CTRLBCLR_IDXCMD_SET (TCC_CTRLBCLR_IDXCMD_SET_Val << TCC_CTRLBCLR_IDXCMD_Pos)
+#define TCC_CTRLBCLR_IDXCMD_CLEAR (TCC_CTRLBCLR_IDXCMD_CLEAR_Val << TCC_CTRLBCLR_IDXCMD_Pos)
+#define TCC_CTRLBCLR_IDXCMD_HOLD (TCC_CTRLBCLR_IDXCMD_HOLD_Val << TCC_CTRLBCLR_IDXCMD_Pos)
+#define TCC_CTRLBCLR_CMD_Pos 5 /**< \brief (TCC_CTRLBCLR) TCC Command */
+#define TCC_CTRLBCLR_CMD_Msk (0x7ul << TCC_CTRLBCLR_CMD_Pos)
+#define TCC_CTRLBCLR_CMD(value) (TCC_CTRLBCLR_CMD_Msk & ((value) << TCC_CTRLBCLR_CMD_Pos))
+#define TCC_CTRLBCLR_CMD_NONE_Val 0x0ul /**< \brief (TCC_CTRLBCLR) No action */
+#define TCC_CTRLBCLR_CMD_RETRIGGER_Val 0x1ul /**< \brief (TCC_CTRLBCLR) Clear start, restart or retrigger */
+#define TCC_CTRLBCLR_CMD_STOP_Val 0x2ul /**< \brief (TCC_CTRLBCLR) Force stop */
+#define TCC_CTRLBCLR_CMD_UPDATE_Val 0x3ul /**< \brief (TCC_CTRLBCLR) Force update of double buffered registers */
+#define TCC_CTRLBCLR_CMD_READSYNC_Val 0x4ul /**< \brief (TCC_CTRLBCLR) Force COUNT read synchronization */
+#define TCC_CTRLBCLR_CMD_NONE (TCC_CTRLBCLR_CMD_NONE_Val << TCC_CTRLBCLR_CMD_Pos)
+#define TCC_CTRLBCLR_CMD_RETRIGGER (TCC_CTRLBCLR_CMD_RETRIGGER_Val << TCC_CTRLBCLR_CMD_Pos)
+#define TCC_CTRLBCLR_CMD_STOP (TCC_CTRLBCLR_CMD_STOP_Val << TCC_CTRLBCLR_CMD_Pos)
+#define TCC_CTRLBCLR_CMD_UPDATE (TCC_CTRLBCLR_CMD_UPDATE_Val << TCC_CTRLBCLR_CMD_Pos)
+#define TCC_CTRLBCLR_CMD_READSYNC (TCC_CTRLBCLR_CMD_READSYNC_Val << TCC_CTRLBCLR_CMD_Pos)
+#define TCC_CTRLBCLR_MASK 0xFFul /**< \brief (TCC_CTRLBCLR) MASK Register */
+
+/* -------- TCC_CTRLBSET : (TCC Offset: 0x05) (R/W 8) Control B Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DIR:1; /*!< bit: 0 Counter Direction */
+ uint8_t LUPD:1; /*!< bit: 1 Lock Update */
+ uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
+ uint8_t IDXCMD:2; /*!< bit: 3.. 4 Ramp Index Command */
+ uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} TCC_CTRLBSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_CTRLBSET_OFFSET 0x05 /**< \brief (TCC_CTRLBSET offset) Control B Set */
+#define TCC_CTRLBSET_RESETVALUE 0x00ul /**< \brief (TCC_CTRLBSET reset_value) Control B Set */
+
+#define TCC_CTRLBSET_DIR_Pos 0 /**< \brief (TCC_CTRLBSET) Counter Direction */
+#define TCC_CTRLBSET_DIR (0x1ul << TCC_CTRLBSET_DIR_Pos)
+#define TCC_CTRLBSET_LUPD_Pos 1 /**< \brief (TCC_CTRLBSET) Lock Update */
+#define TCC_CTRLBSET_LUPD (0x1ul << TCC_CTRLBSET_LUPD_Pos)
+#define TCC_CTRLBSET_ONESHOT_Pos 2 /**< \brief (TCC_CTRLBSET) One-Shot */
+#define TCC_CTRLBSET_ONESHOT (0x1ul << TCC_CTRLBSET_ONESHOT_Pos)
+#define TCC_CTRLBSET_IDXCMD_Pos 3 /**< \brief (TCC_CTRLBSET) Ramp Index Command */
+#define TCC_CTRLBSET_IDXCMD_Msk (0x3ul << TCC_CTRLBSET_IDXCMD_Pos)
+#define TCC_CTRLBSET_IDXCMD(value) (TCC_CTRLBSET_IDXCMD_Msk & ((value) << TCC_CTRLBSET_IDXCMD_Pos))
+#define TCC_CTRLBSET_IDXCMD_DISABLE_Val 0x0ul /**< \brief (TCC_CTRLBSET) Command disabled: Index toggles between cycles A and B */
+#define TCC_CTRLBSET_IDXCMD_SET_Val 0x1ul /**< \brief (TCC_CTRLBSET) Set index: cycle B will be forced in the next cycle */
+#define TCC_CTRLBSET_IDXCMD_CLEAR_Val 0x2ul /**< \brief (TCC_CTRLBSET) Clear index: cycle A will be forced in the next cycle */
+#define TCC_CTRLBSET_IDXCMD_HOLD_Val 0x3ul /**< \brief (TCC_CTRLBSET) Hold index: the next cycle will be the same as the current cycle */
+#define TCC_CTRLBSET_IDXCMD_DISABLE (TCC_CTRLBSET_IDXCMD_DISABLE_Val << TCC_CTRLBSET_IDXCMD_Pos)
+#define TCC_CTRLBSET_IDXCMD_SET (TCC_CTRLBSET_IDXCMD_SET_Val << TCC_CTRLBSET_IDXCMD_Pos)
+#define TCC_CTRLBSET_IDXCMD_CLEAR (TCC_CTRLBSET_IDXCMD_CLEAR_Val << TCC_CTRLBSET_IDXCMD_Pos)
+#define TCC_CTRLBSET_IDXCMD_HOLD (TCC_CTRLBSET_IDXCMD_HOLD_Val << TCC_CTRLBSET_IDXCMD_Pos)
+#define TCC_CTRLBSET_CMD_Pos 5 /**< \brief (TCC_CTRLBSET) TCC Command */
+#define TCC_CTRLBSET_CMD_Msk (0x7ul << TCC_CTRLBSET_CMD_Pos)
+#define TCC_CTRLBSET_CMD(value) (TCC_CTRLBSET_CMD_Msk & ((value) << TCC_CTRLBSET_CMD_Pos))
+#define TCC_CTRLBSET_CMD_NONE_Val 0x0ul /**< \brief (TCC_CTRLBSET) No action */
+#define TCC_CTRLBSET_CMD_RETRIGGER_Val 0x1ul /**< \brief (TCC_CTRLBSET) Clear start, restart or retrigger */
+#define TCC_CTRLBSET_CMD_STOP_Val 0x2ul /**< \brief (TCC_CTRLBSET) Force stop */
+#define TCC_CTRLBSET_CMD_UPDATE_Val 0x3ul /**< \brief (TCC_CTRLBSET) Force update of double buffered registers */
+#define TCC_CTRLBSET_CMD_READSYNC_Val 0x4ul /**< \brief (TCC_CTRLBSET) Force COUNT read synchronization */
+#define TCC_CTRLBSET_CMD_NONE (TCC_CTRLBSET_CMD_NONE_Val << TCC_CTRLBSET_CMD_Pos)
+#define TCC_CTRLBSET_CMD_RETRIGGER (TCC_CTRLBSET_CMD_RETRIGGER_Val << TCC_CTRLBSET_CMD_Pos)
+#define TCC_CTRLBSET_CMD_STOP (TCC_CTRLBSET_CMD_STOP_Val << TCC_CTRLBSET_CMD_Pos)
+#define TCC_CTRLBSET_CMD_UPDATE (TCC_CTRLBSET_CMD_UPDATE_Val << TCC_CTRLBSET_CMD_Pos)
+#define TCC_CTRLBSET_CMD_READSYNC (TCC_CTRLBSET_CMD_READSYNC_Val << TCC_CTRLBSET_CMD_Pos)
+#define TCC_CTRLBSET_MASK 0xFFul /**< \brief (TCC_CTRLBSET) MASK Register */
+
+/* -------- TCC_SYNCBUSY : (TCC Offset: 0x08) (R/ 32) Synchronization Busy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SWRST:1; /*!< bit: 0 Swrst Busy */
+ uint32_t ENABLE:1; /*!< bit: 1 Enable Busy */
+ uint32_t CTRLB:1; /*!< bit: 2 Ctrlb Busy */
+ uint32_t STATUS:1; /*!< bit: 3 Status Busy */
+ uint32_t COUNT:1; /*!< bit: 4 Count Busy */
+ uint32_t PATT:1; /*!< bit: 5 Pattern Busy */
+ uint32_t WAVE:1; /*!< bit: 6 Wave Busy */
+ uint32_t PER:1; /*!< bit: 7 Period busy */
+ uint32_t CC0:1; /*!< bit: 8 Compare Channel 0 Busy */
+ uint32_t CC1:1; /*!< bit: 9 Compare Channel 1 Busy */
+ uint32_t CC2:1; /*!< bit: 10 Compare Channel 2 Busy */
+ uint32_t CC3:1; /*!< bit: 11 Compare Channel 3 Busy */
+ uint32_t :4; /*!< bit: 12..15 Reserved */
+ uint32_t PATTB:1; /*!< bit: 16 Pattern Buffer Busy */
+ uint32_t WAVEB:1; /*!< bit: 17 Wave Buffer Busy */
+ uint32_t PERB:1; /*!< bit: 18 Period Buffer Busy */
+ uint32_t CCB0:1; /*!< bit: 19 Compare Channel Buffer 0 Busy */
+ uint32_t CCB1:1; /*!< bit: 20 Compare Channel Buffer 1 Busy */
+ uint32_t CCB2:1; /*!< bit: 21 Compare Channel Buffer 2 Busy */
+ uint32_t CCB3:1; /*!< bit: 22 Compare Channel Buffer 3 Busy */
+ uint32_t :9; /*!< bit: 23..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :8; /*!< bit: 0.. 7 Reserved */
+ uint32_t CC:4; /*!< bit: 8..11 Compare Channel x Busy */
+ uint32_t :7; /*!< bit: 12..18 Reserved */
+ uint32_t CCB:4; /*!< bit: 19..22 Compare Channel Buffer x Busy */
+ uint32_t :9; /*!< bit: 23..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_SYNCBUSY_OFFSET 0x08 /**< \brief (TCC_SYNCBUSY offset) Synchronization Busy */
+#define TCC_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (TCC_SYNCBUSY reset_value) Synchronization Busy */
+
+#define TCC_SYNCBUSY_SWRST_Pos 0 /**< \brief (TCC_SYNCBUSY) Swrst Busy */
+#define TCC_SYNCBUSY_SWRST (0x1ul << TCC_SYNCBUSY_SWRST_Pos)
+#define TCC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (TCC_SYNCBUSY) Enable Busy */
+#define TCC_SYNCBUSY_ENABLE (0x1ul << TCC_SYNCBUSY_ENABLE_Pos)
+#define TCC_SYNCBUSY_CTRLB_Pos 2 /**< \brief (TCC_SYNCBUSY) Ctrlb Busy */
+#define TCC_SYNCBUSY_CTRLB (0x1ul << TCC_SYNCBUSY_CTRLB_Pos)
+#define TCC_SYNCBUSY_STATUS_Pos 3 /**< \brief (TCC_SYNCBUSY) Status Busy */
+#define TCC_SYNCBUSY_STATUS (0x1ul << TCC_SYNCBUSY_STATUS_Pos)
+#define TCC_SYNCBUSY_COUNT_Pos 4 /**< \brief (TCC_SYNCBUSY) Count Busy */
+#define TCC_SYNCBUSY_COUNT (0x1ul << TCC_SYNCBUSY_COUNT_Pos)
+#define TCC_SYNCBUSY_PATT_Pos 5 /**< \brief (TCC_SYNCBUSY) Pattern Busy */
+#define TCC_SYNCBUSY_PATT (0x1ul << TCC_SYNCBUSY_PATT_Pos)
+#define TCC_SYNCBUSY_WAVE_Pos 6 /**< \brief (TCC_SYNCBUSY) Wave Busy */
+#define TCC_SYNCBUSY_WAVE (0x1ul << TCC_SYNCBUSY_WAVE_Pos)
+#define TCC_SYNCBUSY_PER_Pos 7 /**< \brief (TCC_SYNCBUSY) Period busy */
+#define TCC_SYNCBUSY_PER (0x1ul << TCC_SYNCBUSY_PER_Pos)
+#define TCC_SYNCBUSY_CC0_Pos 8 /**< \brief (TCC_SYNCBUSY) Compare Channel 0 Busy */
+#define TCC_SYNCBUSY_CC0 (1 << TCC_SYNCBUSY_CC0_Pos)
+#define TCC_SYNCBUSY_CC1_Pos 9 /**< \brief (TCC_SYNCBUSY) Compare Channel 1 Busy */
+#define TCC_SYNCBUSY_CC1 (1 << TCC_SYNCBUSY_CC1_Pos)
+#define TCC_SYNCBUSY_CC2_Pos 10 /**< \brief (TCC_SYNCBUSY) Compare Channel 2 Busy */
+#define TCC_SYNCBUSY_CC2 (1 << TCC_SYNCBUSY_CC2_Pos)
+#define TCC_SYNCBUSY_CC3_Pos 11 /**< \brief (TCC_SYNCBUSY) Compare Channel 3 Busy */
+#define TCC_SYNCBUSY_CC3 (1 << TCC_SYNCBUSY_CC3_Pos)
+#define TCC_SYNCBUSY_CC_Pos 8 /**< \brief (TCC_SYNCBUSY) Compare Channel x Busy */
+#define TCC_SYNCBUSY_CC_Msk (0xFul << TCC_SYNCBUSY_CC_Pos)
+#define TCC_SYNCBUSY_CC(value) (TCC_SYNCBUSY_CC_Msk & ((value) << TCC_SYNCBUSY_CC_Pos))
+#define TCC_SYNCBUSY_PATTB_Pos 16 /**< \brief (TCC_SYNCBUSY) Pattern Buffer Busy */
+#define TCC_SYNCBUSY_PATTB (0x1ul << TCC_SYNCBUSY_PATTB_Pos)
+#define TCC_SYNCBUSY_WAVEB_Pos 17 /**< \brief (TCC_SYNCBUSY) Wave Buffer Busy */
+#define TCC_SYNCBUSY_WAVEB (0x1ul << TCC_SYNCBUSY_WAVEB_Pos)
+#define TCC_SYNCBUSY_PERB_Pos 18 /**< \brief (TCC_SYNCBUSY) Period Buffer Busy */
+#define TCC_SYNCBUSY_PERB (0x1ul << TCC_SYNCBUSY_PERB_Pos)
+#define TCC_SYNCBUSY_CCB0_Pos 19 /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 0 Busy */
+#define TCC_SYNCBUSY_CCB0 (1 << TCC_SYNCBUSY_CCB0_Pos)
+#define TCC_SYNCBUSY_CCB1_Pos 20 /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 1 Busy */
+#define TCC_SYNCBUSY_CCB1 (1 << TCC_SYNCBUSY_CCB1_Pos)
+#define TCC_SYNCBUSY_CCB2_Pos 21 /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 2 Busy */
+#define TCC_SYNCBUSY_CCB2 (1 << TCC_SYNCBUSY_CCB2_Pos)
+#define TCC_SYNCBUSY_CCB3_Pos 22 /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 3 Busy */
+#define TCC_SYNCBUSY_CCB3 (1 << TCC_SYNCBUSY_CCB3_Pos)
+#define TCC_SYNCBUSY_CCB_Pos 19 /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer x Busy */
+#define TCC_SYNCBUSY_CCB_Msk (0xFul << TCC_SYNCBUSY_CCB_Pos)
+#define TCC_SYNCBUSY_CCB(value) (TCC_SYNCBUSY_CCB_Msk & ((value) << TCC_SYNCBUSY_CCB_Pos))
+#define TCC_SYNCBUSY_MASK 0x007F0FFFul /**< \brief (TCC_SYNCBUSY) MASK Register */
+
+/* -------- TCC_FCTRLA : (TCC Offset: 0x0C) (R/W 32) Recoverable Fault A Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SRC:2; /*!< bit: 0.. 1 Fault A Source */
+ uint32_t :1; /*!< bit: 2 Reserved */
+ uint32_t KEEP:1; /*!< bit: 3 Fault A Keeper */
+ uint32_t QUAL:1; /*!< bit: 4 Fault A Qualification */
+ uint32_t BLANK:2; /*!< bit: 5.. 6 Fault A Blanking Mode */
+ uint32_t RESTART:1; /*!< bit: 7 Fault A Restart */
+ uint32_t HALT:2; /*!< bit: 8.. 9 Fault A Halt Mode */
+ uint32_t CHSEL:2; /*!< bit: 10..11 Fault A Capture Channel */
+ uint32_t CAPTURE:3; /*!< bit: 12..14 Fault A Capture Action */
+ uint32_t :1; /*!< bit: 15 Reserved */
+ uint32_t BLANKVAL:8; /*!< bit: 16..23 Fault A Blanking Time */
+ uint32_t FILTERVAL:4; /*!< bit: 24..27 Fault A Filter Value */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_FCTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_FCTRLA_OFFSET 0x0C /**< \brief (TCC_FCTRLA offset) Recoverable Fault A Configuration */
+#define TCC_FCTRLA_RESETVALUE 0x00000000ul /**< \brief (TCC_FCTRLA reset_value) Recoverable Fault A Configuration */
+
+#define TCC_FCTRLA_SRC_Pos 0 /**< \brief (TCC_FCTRLA) Fault A Source */
+#define TCC_FCTRLA_SRC_Msk (0x3ul << TCC_FCTRLA_SRC_Pos)
+#define TCC_FCTRLA_SRC(value) (TCC_FCTRLA_SRC_Msk & ((value) << TCC_FCTRLA_SRC_Pos))
+#define TCC_FCTRLA_SRC_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLA) Fault input disabled */
+#define TCC_FCTRLA_SRC_ENABLE_Val 0x1ul /**< \brief (TCC_FCTRLA) MCEx (x=0,1) event input */
+#define TCC_FCTRLA_SRC_INVERT_Val 0x2ul /**< \brief (TCC_FCTRLA) Inverted MCEx (x=0,1) event input */
+#define TCC_FCTRLA_SRC_ALTFAULT_Val 0x3ul /**< \brief (TCC_FCTRLA) Alternate fault (A or B) state at the end of the previous period */
+#define TCC_FCTRLA_SRC_DISABLE (TCC_FCTRLA_SRC_DISABLE_Val << TCC_FCTRLA_SRC_Pos)
+#define TCC_FCTRLA_SRC_ENABLE (TCC_FCTRLA_SRC_ENABLE_Val << TCC_FCTRLA_SRC_Pos)
+#define TCC_FCTRLA_SRC_INVERT (TCC_FCTRLA_SRC_INVERT_Val << TCC_FCTRLA_SRC_Pos)
+#define TCC_FCTRLA_SRC_ALTFAULT (TCC_FCTRLA_SRC_ALTFAULT_Val << TCC_FCTRLA_SRC_Pos)
+#define TCC_FCTRLA_KEEP_Pos 3 /**< \brief (TCC_FCTRLA) Fault A Keeper */
+#define TCC_FCTRLA_KEEP (0x1ul << TCC_FCTRLA_KEEP_Pos)
+#define TCC_FCTRLA_QUAL_Pos 4 /**< \brief (TCC_FCTRLA) Fault A Qualification */
+#define TCC_FCTRLA_QUAL (0x1ul << TCC_FCTRLA_QUAL_Pos)
+#define TCC_FCTRLA_BLANK_Pos 5 /**< \brief (TCC_FCTRLA) Fault A Blanking Mode */
+#define TCC_FCTRLA_BLANK_Msk (0x3ul << TCC_FCTRLA_BLANK_Pos)
+#define TCC_FCTRLA_BLANK(value) (TCC_FCTRLA_BLANK_Msk & ((value) << TCC_FCTRLA_BLANK_Pos))
+#define TCC_FCTRLA_BLANK_NONE_Val 0x0ul /**< \brief (TCC_FCTRLA) No blanking applied */
+#define TCC_FCTRLA_BLANK_RISE_Val 0x1ul /**< \brief (TCC_FCTRLA) Blanking applied from rising edge of the output waveform */
+#define TCC_FCTRLA_BLANK_FALL_Val 0x2ul /**< \brief (TCC_FCTRLA) Blanking applied from falling edge of the output waveform */
+#define TCC_FCTRLA_BLANK_BOTH_Val 0x3ul /**< \brief (TCC_FCTRLA) Blanking applied from each toggle of the output waveform */
+#define TCC_FCTRLA_BLANK_NONE (TCC_FCTRLA_BLANK_NONE_Val << TCC_FCTRLA_BLANK_Pos)
+#define TCC_FCTRLA_BLANK_RISE (TCC_FCTRLA_BLANK_RISE_Val << TCC_FCTRLA_BLANK_Pos)
+#define TCC_FCTRLA_BLANK_FALL (TCC_FCTRLA_BLANK_FALL_Val << TCC_FCTRLA_BLANK_Pos)
+#define TCC_FCTRLA_BLANK_BOTH (TCC_FCTRLA_BLANK_BOTH_Val << TCC_FCTRLA_BLANK_Pos)
+#define TCC_FCTRLA_RESTART_Pos 7 /**< \brief (TCC_FCTRLA) Fault A Restart */
+#define TCC_FCTRLA_RESTART (0x1ul << TCC_FCTRLA_RESTART_Pos)
+#define TCC_FCTRLA_HALT_Pos 8 /**< \brief (TCC_FCTRLA) Fault A Halt Mode */
+#define TCC_FCTRLA_HALT_Msk (0x3ul << TCC_FCTRLA_HALT_Pos)
+#define TCC_FCTRLA_HALT(value) (TCC_FCTRLA_HALT_Msk & ((value) << TCC_FCTRLA_HALT_Pos))
+#define TCC_FCTRLA_HALT_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLA) Halt action disabled */
+#define TCC_FCTRLA_HALT_HW_Val 0x1ul /**< \brief (TCC_FCTRLA) Hardware halt action */
+#define TCC_FCTRLA_HALT_SW_Val 0x2ul /**< \brief (TCC_FCTRLA) Software halt action */
+#define TCC_FCTRLA_HALT_NR_Val 0x3ul /**< \brief (TCC_FCTRLA) Non-recoverable fault */
+#define TCC_FCTRLA_HALT_DISABLE (TCC_FCTRLA_HALT_DISABLE_Val << TCC_FCTRLA_HALT_Pos)
+#define TCC_FCTRLA_HALT_HW (TCC_FCTRLA_HALT_HW_Val << TCC_FCTRLA_HALT_Pos)
+#define TCC_FCTRLA_HALT_SW (TCC_FCTRLA_HALT_SW_Val << TCC_FCTRLA_HALT_Pos)
+#define TCC_FCTRLA_HALT_NR (TCC_FCTRLA_HALT_NR_Val << TCC_FCTRLA_HALT_Pos)
+#define TCC_FCTRLA_CHSEL_Pos 10 /**< \brief (TCC_FCTRLA) Fault A Capture Channel */
+#define TCC_FCTRLA_CHSEL_Msk (0x3ul << TCC_FCTRLA_CHSEL_Pos)
+#define TCC_FCTRLA_CHSEL(value) (TCC_FCTRLA_CHSEL_Msk & ((value) << TCC_FCTRLA_CHSEL_Pos))
+#define TCC_FCTRLA_CHSEL_CC0_Val 0x0ul /**< \brief (TCC_FCTRLA) Capture value stored in channel 0 */
+#define TCC_FCTRLA_CHSEL_CC1_Val 0x1ul /**< \brief (TCC_FCTRLA) Capture value stored in channel 1 */
+#define TCC_FCTRLA_CHSEL_CC2_Val 0x2ul /**< \brief (TCC_FCTRLA) Capture value stored in channel 2 */
+#define TCC_FCTRLA_CHSEL_CC3_Val 0x3ul /**< \brief (TCC_FCTRLA) Capture value stored in channel 3 */
+#define TCC_FCTRLA_CHSEL_CC0 (TCC_FCTRLA_CHSEL_CC0_Val << TCC_FCTRLA_CHSEL_Pos)
+#define TCC_FCTRLA_CHSEL_CC1 (TCC_FCTRLA_CHSEL_CC1_Val << TCC_FCTRLA_CHSEL_Pos)
+#define TCC_FCTRLA_CHSEL_CC2 (TCC_FCTRLA_CHSEL_CC2_Val << TCC_FCTRLA_CHSEL_Pos)
+#define TCC_FCTRLA_CHSEL_CC3 (TCC_FCTRLA_CHSEL_CC3_Val << TCC_FCTRLA_CHSEL_Pos)
+#define TCC_FCTRLA_CAPTURE_Pos 12 /**< \brief (TCC_FCTRLA) Fault A Capture Action */
+#define TCC_FCTRLA_CAPTURE_Msk (0x7ul << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE(value) (TCC_FCTRLA_CAPTURE_Msk & ((value) << TCC_FCTRLA_CAPTURE_Pos))
+#define TCC_FCTRLA_CAPTURE_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLA) No capture */
+#define TCC_FCTRLA_CAPTURE_CAPT_Val 0x1ul /**< \brief (TCC_FCTRLA) Capture on fault */
+#define TCC_FCTRLA_CAPTURE_CAPTMIN_Val 0x2ul /**< \brief (TCC_FCTRLA) Minimum capture */
+#define TCC_FCTRLA_CAPTURE_CAPTMAX_Val 0x3ul /**< \brief (TCC_FCTRLA) Maximum capture */
+#define TCC_FCTRLA_CAPTURE_LOCMIN_Val 0x4ul /**< \brief (TCC_FCTRLA) Minimum local detection */
+#define TCC_FCTRLA_CAPTURE_LOCMAX_Val 0x5ul /**< \brief (TCC_FCTRLA) Maximum local detection */
+#define TCC_FCTRLA_CAPTURE_DERIV0_Val 0x6ul /**< \brief (TCC_FCTRLA) Minimum and maximum local detection */
+#define TCC_FCTRLA_CAPTURE_DISABLE (TCC_FCTRLA_CAPTURE_DISABLE_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE_CAPT (TCC_FCTRLA_CAPTURE_CAPT_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE_CAPTMIN (TCC_FCTRLA_CAPTURE_CAPTMIN_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE_CAPTMAX (TCC_FCTRLA_CAPTURE_CAPTMAX_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE_LOCMIN (TCC_FCTRLA_CAPTURE_LOCMIN_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE_LOCMAX (TCC_FCTRLA_CAPTURE_LOCMAX_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_CAPTURE_DERIV0 (TCC_FCTRLA_CAPTURE_DERIV0_Val << TCC_FCTRLA_CAPTURE_Pos)
+#define TCC_FCTRLA_BLANKVAL_Pos 16 /**< \brief (TCC_FCTRLA) Fault A Blanking Time */
+#define TCC_FCTRLA_BLANKVAL_Msk (0xFFul << TCC_FCTRLA_BLANKVAL_Pos)
+#define TCC_FCTRLA_BLANKVAL(value) (TCC_FCTRLA_BLANKVAL_Msk & ((value) << TCC_FCTRLA_BLANKVAL_Pos))
+#define TCC_FCTRLA_FILTERVAL_Pos 24 /**< \brief (TCC_FCTRLA) Fault A Filter Value */
+#define TCC_FCTRLA_FILTERVAL_Msk (0xFul << TCC_FCTRLA_FILTERVAL_Pos)
+#define TCC_FCTRLA_FILTERVAL(value) (TCC_FCTRLA_FILTERVAL_Msk & ((value) << TCC_FCTRLA_FILTERVAL_Pos))
+#define TCC_FCTRLA_MASK 0x0FFF7FFBul /**< \brief (TCC_FCTRLA) MASK Register */
+
+/* -------- TCC_FCTRLB : (TCC Offset: 0x10) (R/W 32) Recoverable Fault B Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t SRC:2; /*!< bit: 0.. 1 Fault B Source */
+ uint32_t :1; /*!< bit: 2 Reserved */
+ uint32_t KEEP:1; /*!< bit: 3 Fault B Keeper */
+ uint32_t QUAL:1; /*!< bit: 4 Fault B Qualification */
+ uint32_t BLANK:2; /*!< bit: 5.. 6 Fault B Blanking Mode */
+ uint32_t RESTART:1; /*!< bit: 7 Fault B Restart */
+ uint32_t HALT:2; /*!< bit: 8.. 9 Fault B Halt Mode */
+ uint32_t CHSEL:2; /*!< bit: 10..11 Fault B Capture Channel */
+ uint32_t CAPTURE:3; /*!< bit: 12..14 Fault B Capture Action */
+ uint32_t :1; /*!< bit: 15 Reserved */
+ uint32_t BLANKVAL:8; /*!< bit: 16..23 Fault B Blanking Time */
+ uint32_t FILTERVAL:4; /*!< bit: 24..27 Fault B Filter Value */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_FCTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_FCTRLB_OFFSET 0x10 /**< \brief (TCC_FCTRLB offset) Recoverable Fault B Configuration */
+#define TCC_FCTRLB_RESETVALUE 0x00000000ul /**< \brief (TCC_FCTRLB reset_value) Recoverable Fault B Configuration */
+
+#define TCC_FCTRLB_SRC_Pos 0 /**< \brief (TCC_FCTRLB) Fault B Source */
+#define TCC_FCTRLB_SRC_Msk (0x3ul << TCC_FCTRLB_SRC_Pos)
+#define TCC_FCTRLB_SRC(value) (TCC_FCTRLB_SRC_Msk & ((value) << TCC_FCTRLB_SRC_Pos))
+#define TCC_FCTRLB_SRC_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLB) Fault input disabled */
+#define TCC_FCTRLB_SRC_ENABLE_Val 0x1ul /**< \brief (TCC_FCTRLB) MCEx (x=0,1) event input */
+#define TCC_FCTRLB_SRC_INVERT_Val 0x2ul /**< \brief (TCC_FCTRLB) Inverted MCEx (x=0,1) event input */
+#define TCC_FCTRLB_SRC_ALTFAULT_Val 0x3ul /**< \brief (TCC_FCTRLB) Alternate fault (A or B) state at the end of the previous period */
+#define TCC_FCTRLB_SRC_DISABLE (TCC_FCTRLB_SRC_DISABLE_Val << TCC_FCTRLB_SRC_Pos)
+#define TCC_FCTRLB_SRC_ENABLE (TCC_FCTRLB_SRC_ENABLE_Val << TCC_FCTRLB_SRC_Pos)
+#define TCC_FCTRLB_SRC_INVERT (TCC_FCTRLB_SRC_INVERT_Val << TCC_FCTRLB_SRC_Pos)
+#define TCC_FCTRLB_SRC_ALTFAULT (TCC_FCTRLB_SRC_ALTFAULT_Val << TCC_FCTRLB_SRC_Pos)
+#define TCC_FCTRLB_KEEP_Pos 3 /**< \brief (TCC_FCTRLB) Fault B Keeper */
+#define TCC_FCTRLB_KEEP (0x1ul << TCC_FCTRLB_KEEP_Pos)
+#define TCC_FCTRLB_QUAL_Pos 4 /**< \brief (TCC_FCTRLB) Fault B Qualification */
+#define TCC_FCTRLB_QUAL (0x1ul << TCC_FCTRLB_QUAL_Pos)
+#define TCC_FCTRLB_BLANK_Pos 5 /**< \brief (TCC_FCTRLB) Fault B Blanking Mode */
+#define TCC_FCTRLB_BLANK_Msk (0x3ul << TCC_FCTRLB_BLANK_Pos)
+#define TCC_FCTRLB_BLANK(value) (TCC_FCTRLB_BLANK_Msk & ((value) << TCC_FCTRLB_BLANK_Pos))
+#define TCC_FCTRLB_BLANK_NONE_Val 0x0ul /**< \brief (TCC_FCTRLB) No blanking applied */
+#define TCC_FCTRLB_BLANK_RISE_Val 0x1ul /**< \brief (TCC_FCTRLB) Blanking applied from rising edge of the output waveform */
+#define TCC_FCTRLB_BLANK_FALL_Val 0x2ul /**< \brief (TCC_FCTRLB) Blanking applied from falling edge of the output waveform */
+#define TCC_FCTRLB_BLANK_BOTH_Val 0x3ul /**< \brief (TCC_FCTRLB) Blanking applied from each toggle of the output waveform */
+#define TCC_FCTRLB_BLANK_NONE (TCC_FCTRLB_BLANK_NONE_Val << TCC_FCTRLB_BLANK_Pos)
+#define TCC_FCTRLB_BLANK_RISE (TCC_FCTRLB_BLANK_RISE_Val << TCC_FCTRLB_BLANK_Pos)
+#define TCC_FCTRLB_BLANK_FALL (TCC_FCTRLB_BLANK_FALL_Val << TCC_FCTRLB_BLANK_Pos)
+#define TCC_FCTRLB_BLANK_BOTH (TCC_FCTRLB_BLANK_BOTH_Val << TCC_FCTRLB_BLANK_Pos)
+#define TCC_FCTRLB_RESTART_Pos 7 /**< \brief (TCC_FCTRLB) Fault B Restart */
+#define TCC_FCTRLB_RESTART (0x1ul << TCC_FCTRLB_RESTART_Pos)
+#define TCC_FCTRLB_HALT_Pos 8 /**< \brief (TCC_FCTRLB) Fault B Halt Mode */
+#define TCC_FCTRLB_HALT_Msk (0x3ul << TCC_FCTRLB_HALT_Pos)
+#define TCC_FCTRLB_HALT(value) (TCC_FCTRLB_HALT_Msk & ((value) << TCC_FCTRLB_HALT_Pos))
+#define TCC_FCTRLB_HALT_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLB) Halt action disabled */
+#define TCC_FCTRLB_HALT_HW_Val 0x1ul /**< \brief (TCC_FCTRLB) Hardware halt action */
+#define TCC_FCTRLB_HALT_SW_Val 0x2ul /**< \brief (TCC_FCTRLB) Software halt action */
+#define TCC_FCTRLB_HALT_NR_Val 0x3ul /**< \brief (TCC_FCTRLB) Non-recoverable fault */
+#define TCC_FCTRLB_HALT_DISABLE (TCC_FCTRLB_HALT_DISABLE_Val << TCC_FCTRLB_HALT_Pos)
+#define TCC_FCTRLB_HALT_HW (TCC_FCTRLB_HALT_HW_Val << TCC_FCTRLB_HALT_Pos)
+#define TCC_FCTRLB_HALT_SW (TCC_FCTRLB_HALT_SW_Val << TCC_FCTRLB_HALT_Pos)
+#define TCC_FCTRLB_HALT_NR (TCC_FCTRLB_HALT_NR_Val << TCC_FCTRLB_HALT_Pos)
+#define TCC_FCTRLB_CHSEL_Pos 10 /**< \brief (TCC_FCTRLB) Fault B Capture Channel */
+#define TCC_FCTRLB_CHSEL_Msk (0x3ul << TCC_FCTRLB_CHSEL_Pos)
+#define TCC_FCTRLB_CHSEL(value) (TCC_FCTRLB_CHSEL_Msk & ((value) << TCC_FCTRLB_CHSEL_Pos))
+#define TCC_FCTRLB_CHSEL_CC0_Val 0x0ul /**< \brief (TCC_FCTRLB) Capture value stored in channel 0 */
+#define TCC_FCTRLB_CHSEL_CC1_Val 0x1ul /**< \brief (TCC_FCTRLB) Capture value stored in channel 1 */
+#define TCC_FCTRLB_CHSEL_CC2_Val 0x2ul /**< \brief (TCC_FCTRLB) Capture value stored in channel 2 */
+#define TCC_FCTRLB_CHSEL_CC3_Val 0x3ul /**< \brief (TCC_FCTRLB) Capture value stored in channel 3 */
+#define TCC_FCTRLB_CHSEL_CC0 (TCC_FCTRLB_CHSEL_CC0_Val << TCC_FCTRLB_CHSEL_Pos)
+#define TCC_FCTRLB_CHSEL_CC1 (TCC_FCTRLB_CHSEL_CC1_Val << TCC_FCTRLB_CHSEL_Pos)
+#define TCC_FCTRLB_CHSEL_CC2 (TCC_FCTRLB_CHSEL_CC2_Val << TCC_FCTRLB_CHSEL_Pos)
+#define TCC_FCTRLB_CHSEL_CC3 (TCC_FCTRLB_CHSEL_CC3_Val << TCC_FCTRLB_CHSEL_Pos)
+#define TCC_FCTRLB_CAPTURE_Pos 12 /**< \brief (TCC_FCTRLB) Fault B Capture Action */
+#define TCC_FCTRLB_CAPTURE_Msk (0x7ul << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE(value) (TCC_FCTRLB_CAPTURE_Msk & ((value) << TCC_FCTRLB_CAPTURE_Pos))
+#define TCC_FCTRLB_CAPTURE_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLB) No capture */
+#define TCC_FCTRLB_CAPTURE_CAPT_Val 0x1ul /**< \brief (TCC_FCTRLB) Capture on fault */
+#define TCC_FCTRLB_CAPTURE_CAPTMIN_Val 0x2ul /**< \brief (TCC_FCTRLB) Minimum capture */
+#define TCC_FCTRLB_CAPTURE_CAPTMAX_Val 0x3ul /**< \brief (TCC_FCTRLB) Maximum capture */
+#define TCC_FCTRLB_CAPTURE_LOCMIN_Val 0x4ul /**< \brief (TCC_FCTRLB) Minimum local detection */
+#define TCC_FCTRLB_CAPTURE_LOCMAX_Val 0x5ul /**< \brief (TCC_FCTRLB) Maximum local detection */
+#define TCC_FCTRLB_CAPTURE_DERIV0_Val 0x6ul /**< \brief (TCC_FCTRLB) Minimum and maximum local detection */
+#define TCC_FCTRLB_CAPTURE_DISABLE (TCC_FCTRLB_CAPTURE_DISABLE_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE_CAPT (TCC_FCTRLB_CAPTURE_CAPT_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE_CAPTMIN (TCC_FCTRLB_CAPTURE_CAPTMIN_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE_CAPTMAX (TCC_FCTRLB_CAPTURE_CAPTMAX_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE_LOCMIN (TCC_FCTRLB_CAPTURE_LOCMIN_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE_LOCMAX (TCC_FCTRLB_CAPTURE_LOCMAX_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_CAPTURE_DERIV0 (TCC_FCTRLB_CAPTURE_DERIV0_Val << TCC_FCTRLB_CAPTURE_Pos)
+#define TCC_FCTRLB_BLANKVAL_Pos 16 /**< \brief (TCC_FCTRLB) Fault B Blanking Time */
+#define TCC_FCTRLB_BLANKVAL_Msk (0xFFul << TCC_FCTRLB_BLANKVAL_Pos)
+#define TCC_FCTRLB_BLANKVAL(value) (TCC_FCTRLB_BLANKVAL_Msk & ((value) << TCC_FCTRLB_BLANKVAL_Pos))
+#define TCC_FCTRLB_FILTERVAL_Pos 24 /**< \brief (TCC_FCTRLB) Fault B Filter Value */
+#define TCC_FCTRLB_FILTERVAL_Msk (0xFul << TCC_FCTRLB_FILTERVAL_Pos)
+#define TCC_FCTRLB_FILTERVAL(value) (TCC_FCTRLB_FILTERVAL_Msk & ((value) << TCC_FCTRLB_FILTERVAL_Pos))
+#define TCC_FCTRLB_MASK 0x0FFF7FFBul /**< \brief (TCC_FCTRLB) MASK Register */
+
+/* -------- TCC_WEXCTRL : (TCC Offset: 0x14) (R/W 32) Waveform Extension Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t OTMX:2; /*!< bit: 0.. 1 Output Matrix */
+ uint32_t :6; /*!< bit: 2.. 7 Reserved */
+ uint32_t DTIEN0:1; /*!< bit: 8 Dead-time Insertion Generator 0 Enable */
+ uint32_t DTIEN1:1; /*!< bit: 9 Dead-time Insertion Generator 1 Enable */
+ uint32_t DTIEN2:1; /*!< bit: 10 Dead-time Insertion Generator 2 Enable */
+ uint32_t DTIEN3:1; /*!< bit: 11 Dead-time Insertion Generator 3 Enable */
+ uint32_t :4; /*!< bit: 12..15 Reserved */
+ uint32_t DTLS:8; /*!< bit: 16..23 Dead-time Low Side Outputs Value */
+ uint32_t DTHS:8; /*!< bit: 24..31 Dead-time High Side Outputs Value */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :8; /*!< bit: 0.. 7 Reserved */
+ uint32_t DTIEN:4; /*!< bit: 8..11 Dead-time Insertion Generator x Enable */
+ uint32_t :20; /*!< bit: 12..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_WEXCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_WEXCTRL_OFFSET 0x14 /**< \brief (TCC_WEXCTRL offset) Waveform Extension Configuration */
+#define TCC_WEXCTRL_RESETVALUE 0x00000000ul /**< \brief (TCC_WEXCTRL reset_value) Waveform Extension Configuration */
+
+#define TCC_WEXCTRL_OTMX_Pos 0 /**< \brief (TCC_WEXCTRL) Output Matrix */
+#define TCC_WEXCTRL_OTMX_Msk (0x3ul << TCC_WEXCTRL_OTMX_Pos)
+#define TCC_WEXCTRL_OTMX(value) (TCC_WEXCTRL_OTMX_Msk & ((value) << TCC_WEXCTRL_OTMX_Pos))
+#define TCC_WEXCTRL_DTIEN0_Pos 8 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 0 Enable */
+#define TCC_WEXCTRL_DTIEN0 (1 << TCC_WEXCTRL_DTIEN0_Pos)
+#define TCC_WEXCTRL_DTIEN1_Pos 9 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 1 Enable */
+#define TCC_WEXCTRL_DTIEN1 (1 << TCC_WEXCTRL_DTIEN1_Pos)
+#define TCC_WEXCTRL_DTIEN2_Pos 10 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 2 Enable */
+#define TCC_WEXCTRL_DTIEN2 (1 << TCC_WEXCTRL_DTIEN2_Pos)
+#define TCC_WEXCTRL_DTIEN3_Pos 11 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 3 Enable */
+#define TCC_WEXCTRL_DTIEN3 (1 << TCC_WEXCTRL_DTIEN3_Pos)
+#define TCC_WEXCTRL_DTIEN_Pos 8 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator x Enable */
+#define TCC_WEXCTRL_DTIEN_Msk (0xFul << TCC_WEXCTRL_DTIEN_Pos)
+#define TCC_WEXCTRL_DTIEN(value) (TCC_WEXCTRL_DTIEN_Msk & ((value) << TCC_WEXCTRL_DTIEN_Pos))
+#define TCC_WEXCTRL_DTLS_Pos 16 /**< \brief (TCC_WEXCTRL) Dead-time Low Side Outputs Value */
+#define TCC_WEXCTRL_DTLS_Msk (0xFFul << TCC_WEXCTRL_DTLS_Pos)
+#define TCC_WEXCTRL_DTLS(value) (TCC_WEXCTRL_DTLS_Msk & ((value) << TCC_WEXCTRL_DTLS_Pos))
+#define TCC_WEXCTRL_DTHS_Pos 24 /**< \brief (TCC_WEXCTRL) Dead-time High Side Outputs Value */
+#define TCC_WEXCTRL_DTHS_Msk (0xFFul << TCC_WEXCTRL_DTHS_Pos)
+#define TCC_WEXCTRL_DTHS(value) (TCC_WEXCTRL_DTHS_Msk & ((value) << TCC_WEXCTRL_DTHS_Pos))
+#define TCC_WEXCTRL_MASK 0xFFFF0F03ul /**< \brief (TCC_WEXCTRL) MASK Register */
+
+/* -------- TCC_DRVCTRL : (TCC Offset: 0x18) (R/W 32) Driver Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t NRE0:1; /*!< bit: 0 Non-Recoverable State 0 Output Enable */
+ uint32_t NRE1:1; /*!< bit: 1 Non-Recoverable State 1 Output Enable */
+ uint32_t NRE2:1; /*!< bit: 2 Non-Recoverable State 2 Output Enable */
+ uint32_t NRE3:1; /*!< bit: 3 Non-Recoverable State 3 Output Enable */
+ uint32_t NRE4:1; /*!< bit: 4 Non-Recoverable State 4 Output Enable */
+ uint32_t NRE5:1; /*!< bit: 5 Non-Recoverable State 5 Output Enable */
+ uint32_t NRE6:1; /*!< bit: 6 Non-Recoverable State 6 Output Enable */
+ uint32_t NRE7:1; /*!< bit: 7 Non-Recoverable State 7 Output Enable */
+ uint32_t NRV0:1; /*!< bit: 8 Non-Recoverable State 0 Output Value */
+ uint32_t NRV1:1; /*!< bit: 9 Non-Recoverable State 1 Output Value */
+ uint32_t NRV2:1; /*!< bit: 10 Non-Recoverable State 2 Output Value */
+ uint32_t NRV3:1; /*!< bit: 11 Non-Recoverable State 3 Output Value */
+ uint32_t NRV4:1; /*!< bit: 12 Non-Recoverable State 4 Output Value */
+ uint32_t NRV5:1; /*!< bit: 13 Non-Recoverable State 5 Output Value */
+ uint32_t NRV6:1; /*!< bit: 14 Non-Recoverable State 6 Output Value */
+ uint32_t NRV7:1; /*!< bit: 15 Non-Recoverable State 7 Output Value */
+ uint32_t INVEN0:1; /*!< bit: 16 Output Waveform 0 Inversion */
+ uint32_t INVEN1:1; /*!< bit: 17 Output Waveform 1 Inversion */
+ uint32_t INVEN2:1; /*!< bit: 18 Output Waveform 2 Inversion */
+ uint32_t INVEN3:1; /*!< bit: 19 Output Waveform 3 Inversion */
+ uint32_t INVEN4:1; /*!< bit: 20 Output Waveform 4 Inversion */
+ uint32_t INVEN5:1; /*!< bit: 21 Output Waveform 5 Inversion */
+ uint32_t INVEN6:1; /*!< bit: 22 Output Waveform 6 Inversion */
+ uint32_t INVEN7:1; /*!< bit: 23 Output Waveform 7 Inversion */
+ uint32_t FILTERVAL0:4; /*!< bit: 24..27 Non-Recoverable Fault Input 0 Filter Value */
+ uint32_t FILTERVAL1:4; /*!< bit: 28..31 Non-Recoverable Fault Input 1 Filter Value */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t NRE:8; /*!< bit: 0.. 7 Non-Recoverable State x Output Enable */
+ uint32_t NRV:8; /*!< bit: 8..15 Non-Recoverable State x Output Value */
+ uint32_t INVEN:8; /*!< bit: 16..23 Output Waveform x Inversion */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_DRVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_DRVCTRL_OFFSET 0x18 /**< \brief (TCC_DRVCTRL offset) Driver Control */
+#define TCC_DRVCTRL_RESETVALUE 0x00000000ul /**< \brief (TCC_DRVCTRL reset_value) Driver Control */
+
+#define TCC_DRVCTRL_NRE0_Pos 0 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 0 Output Enable */
+#define TCC_DRVCTRL_NRE0 (1 << TCC_DRVCTRL_NRE0_Pos)
+#define TCC_DRVCTRL_NRE1_Pos 1 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 1 Output Enable */
+#define TCC_DRVCTRL_NRE1 (1 << TCC_DRVCTRL_NRE1_Pos)
+#define TCC_DRVCTRL_NRE2_Pos 2 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 2 Output Enable */
+#define TCC_DRVCTRL_NRE2 (1 << TCC_DRVCTRL_NRE2_Pos)
+#define TCC_DRVCTRL_NRE3_Pos 3 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 3 Output Enable */
+#define TCC_DRVCTRL_NRE3 (1 << TCC_DRVCTRL_NRE3_Pos)
+#define TCC_DRVCTRL_NRE4_Pos 4 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 4 Output Enable */
+#define TCC_DRVCTRL_NRE4 (1 << TCC_DRVCTRL_NRE4_Pos)
+#define TCC_DRVCTRL_NRE5_Pos 5 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 5 Output Enable */
+#define TCC_DRVCTRL_NRE5 (1 << TCC_DRVCTRL_NRE5_Pos)
+#define TCC_DRVCTRL_NRE6_Pos 6 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 6 Output Enable */
+#define TCC_DRVCTRL_NRE6 (1 << TCC_DRVCTRL_NRE6_Pos)
+#define TCC_DRVCTRL_NRE7_Pos 7 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 7 Output Enable */
+#define TCC_DRVCTRL_NRE7 (1 << TCC_DRVCTRL_NRE7_Pos)
+#define TCC_DRVCTRL_NRE_Pos 0 /**< \brief (TCC_DRVCTRL) Non-Recoverable State x Output Enable */
+#define TCC_DRVCTRL_NRE_Msk (0xFFul << TCC_DRVCTRL_NRE_Pos)
+#define TCC_DRVCTRL_NRE(value) (TCC_DRVCTRL_NRE_Msk & ((value) << TCC_DRVCTRL_NRE_Pos))
+#define TCC_DRVCTRL_NRV0_Pos 8 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 0 Output Value */
+#define TCC_DRVCTRL_NRV0 (1 << TCC_DRVCTRL_NRV0_Pos)
+#define TCC_DRVCTRL_NRV1_Pos 9 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 1 Output Value */
+#define TCC_DRVCTRL_NRV1 (1 << TCC_DRVCTRL_NRV1_Pos)
+#define TCC_DRVCTRL_NRV2_Pos 10 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 2 Output Value */
+#define TCC_DRVCTRL_NRV2 (1 << TCC_DRVCTRL_NRV2_Pos)
+#define TCC_DRVCTRL_NRV3_Pos 11 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 3 Output Value */
+#define TCC_DRVCTRL_NRV3 (1 << TCC_DRVCTRL_NRV3_Pos)
+#define TCC_DRVCTRL_NRV4_Pos 12 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 4 Output Value */
+#define TCC_DRVCTRL_NRV4 (1 << TCC_DRVCTRL_NRV4_Pos)
+#define TCC_DRVCTRL_NRV5_Pos 13 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 5 Output Value */
+#define TCC_DRVCTRL_NRV5 (1 << TCC_DRVCTRL_NRV5_Pos)
+#define TCC_DRVCTRL_NRV6_Pos 14 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 6 Output Value */
+#define TCC_DRVCTRL_NRV6 (1 << TCC_DRVCTRL_NRV6_Pos)
+#define TCC_DRVCTRL_NRV7_Pos 15 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 7 Output Value */
+#define TCC_DRVCTRL_NRV7 (1 << TCC_DRVCTRL_NRV7_Pos)
+#define TCC_DRVCTRL_NRV_Pos 8 /**< \brief (TCC_DRVCTRL) Non-Recoverable State x Output Value */
+#define TCC_DRVCTRL_NRV_Msk (0xFFul << TCC_DRVCTRL_NRV_Pos)
+#define TCC_DRVCTRL_NRV(value) (TCC_DRVCTRL_NRV_Msk & ((value) << TCC_DRVCTRL_NRV_Pos))
+#define TCC_DRVCTRL_INVEN0_Pos 16 /**< \brief (TCC_DRVCTRL) Output Waveform 0 Inversion */
+#define TCC_DRVCTRL_INVEN0 (1 << TCC_DRVCTRL_INVEN0_Pos)
+#define TCC_DRVCTRL_INVEN1_Pos 17 /**< \brief (TCC_DRVCTRL) Output Waveform 1 Inversion */
+#define TCC_DRVCTRL_INVEN1 (1 << TCC_DRVCTRL_INVEN1_Pos)
+#define TCC_DRVCTRL_INVEN2_Pos 18 /**< \brief (TCC_DRVCTRL) Output Waveform 2 Inversion */
+#define TCC_DRVCTRL_INVEN2 (1 << TCC_DRVCTRL_INVEN2_Pos)
+#define TCC_DRVCTRL_INVEN3_Pos 19 /**< \brief (TCC_DRVCTRL) Output Waveform 3 Inversion */
+#define TCC_DRVCTRL_INVEN3 (1 << TCC_DRVCTRL_INVEN3_Pos)
+#define TCC_DRVCTRL_INVEN4_Pos 20 /**< \brief (TCC_DRVCTRL) Output Waveform 4 Inversion */
+#define TCC_DRVCTRL_INVEN4 (1 << TCC_DRVCTRL_INVEN4_Pos)
+#define TCC_DRVCTRL_INVEN5_Pos 21 /**< \brief (TCC_DRVCTRL) Output Waveform 5 Inversion */
+#define TCC_DRVCTRL_INVEN5 (1 << TCC_DRVCTRL_INVEN5_Pos)
+#define TCC_DRVCTRL_INVEN6_Pos 22 /**< \brief (TCC_DRVCTRL) Output Waveform 6 Inversion */
+#define TCC_DRVCTRL_INVEN6 (1 << TCC_DRVCTRL_INVEN6_Pos)
+#define TCC_DRVCTRL_INVEN7_Pos 23 /**< \brief (TCC_DRVCTRL) Output Waveform 7 Inversion */
+#define TCC_DRVCTRL_INVEN7 (1 << TCC_DRVCTRL_INVEN7_Pos)
+#define TCC_DRVCTRL_INVEN_Pos 16 /**< \brief (TCC_DRVCTRL) Output Waveform x Inversion */
+#define TCC_DRVCTRL_INVEN_Msk (0xFFul << TCC_DRVCTRL_INVEN_Pos)
+#define TCC_DRVCTRL_INVEN(value) (TCC_DRVCTRL_INVEN_Msk & ((value) << TCC_DRVCTRL_INVEN_Pos))
+#define TCC_DRVCTRL_FILTERVAL0_Pos 24 /**< \brief (TCC_DRVCTRL) Non-Recoverable Fault Input 0 Filter Value */
+#define TCC_DRVCTRL_FILTERVAL0_Msk (0xFul << TCC_DRVCTRL_FILTERVAL0_Pos)
+#define TCC_DRVCTRL_FILTERVAL0(value) (TCC_DRVCTRL_FILTERVAL0_Msk & ((value) << TCC_DRVCTRL_FILTERVAL0_Pos))
+#define TCC_DRVCTRL_FILTERVAL1_Pos 28 /**< \brief (TCC_DRVCTRL) Non-Recoverable Fault Input 1 Filter Value */
+#define TCC_DRVCTRL_FILTERVAL1_Msk (0xFul << TCC_DRVCTRL_FILTERVAL1_Pos)
+#define TCC_DRVCTRL_FILTERVAL1(value) (TCC_DRVCTRL_FILTERVAL1_Msk & ((value) << TCC_DRVCTRL_FILTERVAL1_Pos))
+#define TCC_DRVCTRL_MASK 0xFFFFFFFFul /**< \brief (TCC_DRVCTRL) MASK Register */
+
+/* -------- TCC_DBGCTRL : (TCC Offset: 0x1E) (R/W 8) Debug Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DBGRUN:1; /*!< bit: 0 Debug Running Mode */
+ uint8_t :1; /*!< bit: 1 Reserved */
+ uint8_t FDDBD:1; /*!< bit: 2 Fault Detection on Debug Break Detection */
+ uint8_t :5; /*!< bit: 3.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} TCC_DBGCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_DBGCTRL_OFFSET 0x1E /**< \brief (TCC_DBGCTRL offset) Debug Control */
+#define TCC_DBGCTRL_RESETVALUE 0x00ul /**< \brief (TCC_DBGCTRL reset_value) Debug Control */
+
+#define TCC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (TCC_DBGCTRL) Debug Running Mode */
+#define TCC_DBGCTRL_DBGRUN (0x1ul << TCC_DBGCTRL_DBGRUN_Pos)
+#define TCC_DBGCTRL_FDDBD_Pos 2 /**< \brief (TCC_DBGCTRL) Fault Detection on Debug Break Detection */
+#define TCC_DBGCTRL_FDDBD (0x1ul << TCC_DBGCTRL_FDDBD_Pos)
+#define TCC_DBGCTRL_MASK 0x05ul /**< \brief (TCC_DBGCTRL) MASK Register */
+
+/* -------- TCC_EVCTRL : (TCC Offset: 0x20) (R/W 32) Event Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t EVACT0:3; /*!< bit: 0.. 2 Timer/counter Input Event0 Action */
+ uint32_t EVACT1:3; /*!< bit: 3.. 5 Timer/counter Input Event1 Action */
+ uint32_t CNTSEL:2; /*!< bit: 6.. 7 Timer/counter Output Event Mode */
+ uint32_t OVFEO:1; /*!< bit: 8 Overflow/Underflow Output Event Enable */
+ uint32_t TRGEO:1; /*!< bit: 9 Retrigger Output Event Enable */
+ uint32_t CNTEO:1; /*!< bit: 10 Timer/counter Output Event Enable */
+ uint32_t :1; /*!< bit: 11 Reserved */
+ uint32_t TCINV0:1; /*!< bit: 12 Inverted Event 0 Input Enable */
+ uint32_t TCINV1:1; /*!< bit: 13 Inverted Event 1 Input Enable */
+ uint32_t TCEI0:1; /*!< bit: 14 Timer/counter Event 0 Input Enable */
+ uint32_t TCEI1:1; /*!< bit: 15 Timer/counter Event 1 Input Enable */
+ uint32_t MCEI0:1; /*!< bit: 16 Match or Capture Channel 0 Event Input Enable */
+ uint32_t MCEI1:1; /*!< bit: 17 Match or Capture Channel 1 Event Input Enable */
+ uint32_t MCEI2:1; /*!< bit: 18 Match or Capture Channel 2 Event Input Enable */
+ uint32_t MCEI3:1; /*!< bit: 19 Match or Capture Channel 3 Event Input Enable */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t MCEO0:1; /*!< bit: 24 Match or Capture Channel 0 Event Output Enable */
+ uint32_t MCEO1:1; /*!< bit: 25 Match or Capture Channel 1 Event Output Enable */
+ uint32_t MCEO2:1; /*!< bit: 26 Match or Capture Channel 2 Event Output Enable */
+ uint32_t MCEO3:1; /*!< bit: 27 Match or Capture Channel 3 Event Output Enable */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :12; /*!< bit: 0..11 Reserved */
+ uint32_t TCINV:2; /*!< bit: 12..13 Inverted Event x Input Enable */
+ uint32_t TCEI:2; /*!< bit: 14..15 Timer/counter Event x Input Enable */
+ uint32_t MCEI:4; /*!< bit: 16..19 Match or Capture Channel x Event Input Enable */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t MCEO:4; /*!< bit: 24..27 Match or Capture Channel x Event Output Enable */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_EVCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_EVCTRL_OFFSET 0x20 /**< \brief (TCC_EVCTRL offset) Event Control */
+#define TCC_EVCTRL_RESETVALUE 0x00000000ul /**< \brief (TCC_EVCTRL reset_value) Event Control */
+
+#define TCC_EVCTRL_EVACT0_Pos 0 /**< \brief (TCC_EVCTRL) Timer/counter Input Event0 Action */
+#define TCC_EVCTRL_EVACT0_Msk (0x7ul << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0(value) (TCC_EVCTRL_EVACT0_Msk & ((value) << TCC_EVCTRL_EVACT0_Pos))
+#define TCC_EVCTRL_EVACT0_OFF_Val 0x0ul /**< \brief (TCC_EVCTRL) Event action disabled */
+#define TCC_EVCTRL_EVACT0_RETRIGGER_Val 0x1ul /**< \brief (TCC_EVCTRL) Start, restart or re-trigger counter on event */
+#define TCC_EVCTRL_EVACT0_COUNTEV_Val 0x2ul /**< \brief (TCC_EVCTRL) Count on event */
+#define TCC_EVCTRL_EVACT0_START_Val 0x3ul /**< \brief (TCC_EVCTRL) Start counter on event */
+#define TCC_EVCTRL_EVACT0_INC_Val 0x4ul /**< \brief (TCC_EVCTRL) Increment counter on event */
+#define TCC_EVCTRL_EVACT0_COUNT_Val 0x5ul /**< \brief (TCC_EVCTRL) Count on active state of asynchronous event */
+#define TCC_EVCTRL_EVACT0_FAULT_Val 0x7ul /**< \brief (TCC_EVCTRL) Non-recoverable fault */
+#define TCC_EVCTRL_EVACT0_OFF (TCC_EVCTRL_EVACT0_OFF_Val << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0_RETRIGGER (TCC_EVCTRL_EVACT0_RETRIGGER_Val << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0_COUNTEV (TCC_EVCTRL_EVACT0_COUNTEV_Val << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0_START (TCC_EVCTRL_EVACT0_START_Val << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0_INC (TCC_EVCTRL_EVACT0_INC_Val << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0_COUNT (TCC_EVCTRL_EVACT0_COUNT_Val << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT0_FAULT (TCC_EVCTRL_EVACT0_FAULT_Val << TCC_EVCTRL_EVACT0_Pos)
+#define TCC_EVCTRL_EVACT1_Pos 3 /**< \brief (TCC_EVCTRL) Timer/counter Input Event1 Action */
+#define TCC_EVCTRL_EVACT1_Msk (0x7ul << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1(value) (TCC_EVCTRL_EVACT1_Msk & ((value) << TCC_EVCTRL_EVACT1_Pos))
+#define TCC_EVCTRL_EVACT1_OFF_Val 0x0ul /**< \brief (TCC_EVCTRL) Event action disabled */
+#define TCC_EVCTRL_EVACT1_RETRIGGER_Val 0x1ul /**< \brief (TCC_EVCTRL) Re-trigger counter on event */
+#define TCC_EVCTRL_EVACT1_DIR_Val 0x2ul /**< \brief (TCC_EVCTRL) Direction control */
+#define TCC_EVCTRL_EVACT1_STOP_Val 0x3ul /**< \brief (TCC_EVCTRL) Stop counter on event */
+#define TCC_EVCTRL_EVACT1_DEC_Val 0x4ul /**< \brief (TCC_EVCTRL) Decrement counter on event */
+#define TCC_EVCTRL_EVACT1_PPW_Val 0x5ul /**< \brief (TCC_EVCTRL) Period capture value in CC0 register, pulse width capture value in CC1 register */
+#define TCC_EVCTRL_EVACT1_PWP_Val 0x6ul /**< \brief (TCC_EVCTRL) Period capture value in CC1 register, pulse width capture value in CC0 register */
+#define TCC_EVCTRL_EVACT1_FAULT_Val 0x7ul /**< \brief (TCC_EVCTRL) Non-recoverable fault */
+#define TCC_EVCTRL_EVACT1_OFF (TCC_EVCTRL_EVACT1_OFF_Val << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_RETRIGGER (TCC_EVCTRL_EVACT1_RETRIGGER_Val << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_DIR (TCC_EVCTRL_EVACT1_DIR_Val << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_STOP (TCC_EVCTRL_EVACT1_STOP_Val << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_DEC (TCC_EVCTRL_EVACT1_DEC_Val << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_PPW (TCC_EVCTRL_EVACT1_PPW_Val << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_PWP (TCC_EVCTRL_EVACT1_PWP_Val << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_EVACT1_FAULT (TCC_EVCTRL_EVACT1_FAULT_Val << TCC_EVCTRL_EVACT1_Pos)
+#define TCC_EVCTRL_CNTSEL_Pos 6 /**< \brief (TCC_EVCTRL) Timer/counter Output Event Mode */
+#define TCC_EVCTRL_CNTSEL_Msk (0x3ul << TCC_EVCTRL_CNTSEL_Pos)
+#define TCC_EVCTRL_CNTSEL(value) (TCC_EVCTRL_CNTSEL_Msk & ((value) << TCC_EVCTRL_CNTSEL_Pos))
+#define TCC_EVCTRL_CNTSEL_START_Val 0x0ul /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a new counter cycle starts */
+#define TCC_EVCTRL_CNTSEL_END_Val 0x1ul /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a counter cycle ends */
+#define TCC_EVCTRL_CNTSEL_BETWEEN_Val 0x2ul /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a counter cycle ends, except for the first and last cycles */
+#define TCC_EVCTRL_CNTSEL_BOUNDARY_Val 0x3ul /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a new counter cycle starts or a counter cycle ends */
+#define TCC_EVCTRL_CNTSEL_START (TCC_EVCTRL_CNTSEL_START_Val << TCC_EVCTRL_CNTSEL_Pos)
+#define TCC_EVCTRL_CNTSEL_END (TCC_EVCTRL_CNTSEL_END_Val << TCC_EVCTRL_CNTSEL_Pos)
+#define TCC_EVCTRL_CNTSEL_BETWEEN (TCC_EVCTRL_CNTSEL_BETWEEN_Val << TCC_EVCTRL_CNTSEL_Pos)
+#define TCC_EVCTRL_CNTSEL_BOUNDARY (TCC_EVCTRL_CNTSEL_BOUNDARY_Val << TCC_EVCTRL_CNTSEL_Pos)
+#define TCC_EVCTRL_OVFEO_Pos 8 /**< \brief (TCC_EVCTRL) Overflow/Underflow Output Event Enable */
+#define TCC_EVCTRL_OVFEO (0x1ul << TCC_EVCTRL_OVFEO_Pos)
+#define TCC_EVCTRL_TRGEO_Pos 9 /**< \brief (TCC_EVCTRL) Retrigger Output Event Enable */
+#define TCC_EVCTRL_TRGEO (0x1ul << TCC_EVCTRL_TRGEO_Pos)
+#define TCC_EVCTRL_CNTEO_Pos 10 /**< \brief (TCC_EVCTRL) Timer/counter Output Event Enable */
+#define TCC_EVCTRL_CNTEO (0x1ul << TCC_EVCTRL_CNTEO_Pos)
+#define TCC_EVCTRL_TCINV0_Pos 12 /**< \brief (TCC_EVCTRL) Inverted Event 0 Input Enable */
+#define TCC_EVCTRL_TCINV0 (1 << TCC_EVCTRL_TCINV0_Pos)
+#define TCC_EVCTRL_TCINV1_Pos 13 /**< \brief (TCC_EVCTRL) Inverted Event 1 Input Enable */
+#define TCC_EVCTRL_TCINV1 (1 << TCC_EVCTRL_TCINV1_Pos)
+#define TCC_EVCTRL_TCINV_Pos 12 /**< \brief (TCC_EVCTRL) Inverted Event x Input Enable */
+#define TCC_EVCTRL_TCINV_Msk (0x3ul << TCC_EVCTRL_TCINV_Pos)
+#define TCC_EVCTRL_TCINV(value) (TCC_EVCTRL_TCINV_Msk & ((value) << TCC_EVCTRL_TCINV_Pos))
+#define TCC_EVCTRL_TCEI0_Pos 14 /**< \brief (TCC_EVCTRL) Timer/counter Event 0 Input Enable */
+#define TCC_EVCTRL_TCEI0 (1 << TCC_EVCTRL_TCEI0_Pos)
+#define TCC_EVCTRL_TCEI1_Pos 15 /**< \brief (TCC_EVCTRL) Timer/counter Event 1 Input Enable */
+#define TCC_EVCTRL_TCEI1 (1 << TCC_EVCTRL_TCEI1_Pos)
+#define TCC_EVCTRL_TCEI_Pos 14 /**< \brief (TCC_EVCTRL) Timer/counter Event x Input Enable */
+#define TCC_EVCTRL_TCEI_Msk (0x3ul << TCC_EVCTRL_TCEI_Pos)
+#define TCC_EVCTRL_TCEI(value) (TCC_EVCTRL_TCEI_Msk & ((value) << TCC_EVCTRL_TCEI_Pos))
+#define TCC_EVCTRL_MCEI0_Pos 16 /**< \brief (TCC_EVCTRL) Match or Capture Channel 0 Event Input Enable */
+#define TCC_EVCTRL_MCEI0 (1 << TCC_EVCTRL_MCEI0_Pos)
+#define TCC_EVCTRL_MCEI1_Pos 17 /**< \brief (TCC_EVCTRL) Match or Capture Channel 1 Event Input Enable */
+#define TCC_EVCTRL_MCEI1 (1 << TCC_EVCTRL_MCEI1_Pos)
+#define TCC_EVCTRL_MCEI2_Pos 18 /**< \brief (TCC_EVCTRL) Match or Capture Channel 2 Event Input Enable */
+#define TCC_EVCTRL_MCEI2 (1 << TCC_EVCTRL_MCEI2_Pos)
+#define TCC_EVCTRL_MCEI3_Pos 19 /**< \brief (TCC_EVCTRL) Match or Capture Channel 3 Event Input Enable */
+#define TCC_EVCTRL_MCEI3 (1 << TCC_EVCTRL_MCEI3_Pos)
+#define TCC_EVCTRL_MCEI_Pos 16 /**< \brief (TCC_EVCTRL) Match or Capture Channel x Event Input Enable */
+#define TCC_EVCTRL_MCEI_Msk (0xFul << TCC_EVCTRL_MCEI_Pos)
+#define TCC_EVCTRL_MCEI(value) (TCC_EVCTRL_MCEI_Msk & ((value) << TCC_EVCTRL_MCEI_Pos))
+#define TCC_EVCTRL_MCEO0_Pos 24 /**< \brief (TCC_EVCTRL) Match or Capture Channel 0 Event Output Enable */
+#define TCC_EVCTRL_MCEO0 (1 << TCC_EVCTRL_MCEO0_Pos)
+#define TCC_EVCTRL_MCEO1_Pos 25 /**< \brief (TCC_EVCTRL) Match or Capture Channel 1 Event Output Enable */
+#define TCC_EVCTRL_MCEO1 (1 << TCC_EVCTRL_MCEO1_Pos)
+#define TCC_EVCTRL_MCEO2_Pos 26 /**< \brief (TCC_EVCTRL) Match or Capture Channel 2 Event Output Enable */
+#define TCC_EVCTRL_MCEO2 (1 << TCC_EVCTRL_MCEO2_Pos)
+#define TCC_EVCTRL_MCEO3_Pos 27 /**< \brief (TCC_EVCTRL) Match or Capture Channel 3 Event Output Enable */
+#define TCC_EVCTRL_MCEO3 (1 << TCC_EVCTRL_MCEO3_Pos)
+#define TCC_EVCTRL_MCEO_Pos 24 /**< \brief (TCC_EVCTRL) Match or Capture Channel x Event Output Enable */
+#define TCC_EVCTRL_MCEO_Msk (0xFul << TCC_EVCTRL_MCEO_Pos)
+#define TCC_EVCTRL_MCEO(value) (TCC_EVCTRL_MCEO_Msk & ((value) << TCC_EVCTRL_MCEO_Pos))
+#define TCC_EVCTRL_MASK 0x0F0FF7FFul /**< \brief (TCC_EVCTRL) MASK Register */
+
+/* -------- TCC_INTENCLR : (TCC Offset: 0x24) (R/W 32) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
+ uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */
+ uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */
+ uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */
+ uint32_t :7; /*!< bit: 4..10 Reserved */
+ uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault Interrupt Enable */
+ uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A Interrupt Enable */
+ uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B Interrupt Enable */
+ uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 Interrupt Enable */
+ uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 Interrupt Enable */
+ uint32_t MC0:1; /*!< bit: 16 Match or Capture Channel 0 Interrupt Enable */
+ uint32_t MC1:1; /*!< bit: 17 Match or Capture Channel 1 Interrupt Enable */
+ uint32_t MC2:1; /*!< bit: 18 Match or Capture Channel 2 Interrupt Enable */
+ uint32_t MC3:1; /*!< bit: 19 Match or Capture Channel 3 Interrupt Enable */
+ uint32_t :12; /*!< bit: 20..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :16; /*!< bit: 0..15 Reserved */
+ uint32_t MC:4; /*!< bit: 16..19 Match or Capture Channel x Interrupt Enable */
+ uint32_t :12; /*!< bit: 20..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_INTENCLR_OFFSET 0x24 /**< \brief (TCC_INTENCLR offset) Interrupt Enable Clear */
+#define TCC_INTENCLR_RESETVALUE 0x00000000ul /**< \brief (TCC_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define TCC_INTENCLR_OVF_Pos 0 /**< \brief (TCC_INTENCLR) Overflow Interrupt Enable */
+#define TCC_INTENCLR_OVF (0x1ul << TCC_INTENCLR_OVF_Pos)
+#define TCC_INTENCLR_TRG_Pos 1 /**< \brief (TCC_INTENCLR) Retrigger Interrupt Enable */
+#define TCC_INTENCLR_TRG (0x1ul << TCC_INTENCLR_TRG_Pos)
+#define TCC_INTENCLR_CNT_Pos 2 /**< \brief (TCC_INTENCLR) Counter Interrupt Enable */
+#define TCC_INTENCLR_CNT (0x1ul << TCC_INTENCLR_CNT_Pos)
+#define TCC_INTENCLR_ERR_Pos 3 /**< \brief (TCC_INTENCLR) Error Interrupt Enable */
+#define TCC_INTENCLR_ERR (0x1ul << TCC_INTENCLR_ERR_Pos)
+#define TCC_INTENCLR_DFS_Pos 11 /**< \brief (TCC_INTENCLR) Non-Recoverable Debug Fault Interrupt Enable */
+#define TCC_INTENCLR_DFS (0x1ul << TCC_INTENCLR_DFS_Pos)
+#define TCC_INTENCLR_FAULTA_Pos 12 /**< \brief (TCC_INTENCLR) Recoverable Fault A Interrupt Enable */
+#define TCC_INTENCLR_FAULTA (0x1ul << TCC_INTENCLR_FAULTA_Pos)
+#define TCC_INTENCLR_FAULTB_Pos 13 /**< \brief (TCC_INTENCLR) Recoverable Fault B Interrupt Enable */
+#define TCC_INTENCLR_FAULTB (0x1ul << TCC_INTENCLR_FAULTB_Pos)
+#define TCC_INTENCLR_FAULT0_Pos 14 /**< \brief (TCC_INTENCLR) Non-Recoverable Fault 0 Interrupt Enable */
+#define TCC_INTENCLR_FAULT0 (0x1ul << TCC_INTENCLR_FAULT0_Pos)
+#define TCC_INTENCLR_FAULT1_Pos 15 /**< \brief (TCC_INTENCLR) Non-Recoverable Fault 1 Interrupt Enable */
+#define TCC_INTENCLR_FAULT1 (0x1ul << TCC_INTENCLR_FAULT1_Pos)
+#define TCC_INTENCLR_MC0_Pos 16 /**< \brief (TCC_INTENCLR) Match or Capture Channel 0 Interrupt Enable */
+#define TCC_INTENCLR_MC0 (1 << TCC_INTENCLR_MC0_Pos)
+#define TCC_INTENCLR_MC1_Pos 17 /**< \brief (TCC_INTENCLR) Match or Capture Channel 1 Interrupt Enable */
+#define TCC_INTENCLR_MC1 (1 << TCC_INTENCLR_MC1_Pos)
+#define TCC_INTENCLR_MC2_Pos 18 /**< \brief (TCC_INTENCLR) Match or Capture Channel 2 Interrupt Enable */
+#define TCC_INTENCLR_MC2 (1 << TCC_INTENCLR_MC2_Pos)
+#define TCC_INTENCLR_MC3_Pos 19 /**< \brief (TCC_INTENCLR) Match or Capture Channel 3 Interrupt Enable */
+#define TCC_INTENCLR_MC3 (1 << TCC_INTENCLR_MC3_Pos)
+#define TCC_INTENCLR_MC_Pos 16 /**< \brief (TCC_INTENCLR) Match or Capture Channel x Interrupt Enable */
+#define TCC_INTENCLR_MC_Msk (0xFul << TCC_INTENCLR_MC_Pos)
+#define TCC_INTENCLR_MC(value) (TCC_INTENCLR_MC_Msk & ((value) << TCC_INTENCLR_MC_Pos))
+#define TCC_INTENCLR_MASK 0x000FF80Ful /**< \brief (TCC_INTENCLR) MASK Register */
+
+/* -------- TCC_INTENSET : (TCC Offset: 0x28) (R/W 32) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
+ uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */
+ uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */
+ uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */
+ uint32_t :7; /*!< bit: 4..10 Reserved */
+ uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault Interrupt Enable */
+ uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A Interrupt Enable */
+ uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B Interrupt Enable */
+ uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 Interrupt Enable */
+ uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 Interrupt Enable */
+ uint32_t MC0:1; /*!< bit: 16 Match or Capture Channel 0 Interrupt Enable */
+ uint32_t MC1:1; /*!< bit: 17 Match or Capture Channel 1 Interrupt Enable */
+ uint32_t MC2:1; /*!< bit: 18 Match or Capture Channel 2 Interrupt Enable */
+ uint32_t MC3:1; /*!< bit: 19 Match or Capture Channel 3 Interrupt Enable */
+ uint32_t :12; /*!< bit: 20..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :16; /*!< bit: 0..15 Reserved */
+ uint32_t MC:4; /*!< bit: 16..19 Match or Capture Channel x Interrupt Enable */
+ uint32_t :12; /*!< bit: 20..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_INTENSET_OFFSET 0x28 /**< \brief (TCC_INTENSET offset) Interrupt Enable Set */
+#define TCC_INTENSET_RESETVALUE 0x00000000ul /**< \brief (TCC_INTENSET reset_value) Interrupt Enable Set */
+
+#define TCC_INTENSET_OVF_Pos 0 /**< \brief (TCC_INTENSET) Overflow Interrupt Enable */
+#define TCC_INTENSET_OVF (0x1ul << TCC_INTENSET_OVF_Pos)
+#define TCC_INTENSET_TRG_Pos 1 /**< \brief (TCC_INTENSET) Retrigger Interrupt Enable */
+#define TCC_INTENSET_TRG (0x1ul << TCC_INTENSET_TRG_Pos)
+#define TCC_INTENSET_CNT_Pos 2 /**< \brief (TCC_INTENSET) Counter Interrupt Enable */
+#define TCC_INTENSET_CNT (0x1ul << TCC_INTENSET_CNT_Pos)
+#define TCC_INTENSET_ERR_Pos 3 /**< \brief (TCC_INTENSET) Error Interrupt Enable */
+#define TCC_INTENSET_ERR (0x1ul << TCC_INTENSET_ERR_Pos)
+#define TCC_INTENSET_DFS_Pos 11 /**< \brief (TCC_INTENSET) Non-Recoverable Debug Fault Interrupt Enable */
+#define TCC_INTENSET_DFS (0x1ul << TCC_INTENSET_DFS_Pos)
+#define TCC_INTENSET_FAULTA_Pos 12 /**< \brief (TCC_INTENSET) Recoverable Fault A Interrupt Enable */
+#define TCC_INTENSET_FAULTA (0x1ul << TCC_INTENSET_FAULTA_Pos)
+#define TCC_INTENSET_FAULTB_Pos 13 /**< \brief (TCC_INTENSET) Recoverable Fault B Interrupt Enable */
+#define TCC_INTENSET_FAULTB (0x1ul << TCC_INTENSET_FAULTB_Pos)
+#define TCC_INTENSET_FAULT0_Pos 14 /**< \brief (TCC_INTENSET) Non-Recoverable Fault 0 Interrupt Enable */
+#define TCC_INTENSET_FAULT0 (0x1ul << TCC_INTENSET_FAULT0_Pos)
+#define TCC_INTENSET_FAULT1_Pos 15 /**< \brief (TCC_INTENSET) Non-Recoverable Fault 1 Interrupt Enable */
+#define TCC_INTENSET_FAULT1 (0x1ul << TCC_INTENSET_FAULT1_Pos)
+#define TCC_INTENSET_MC0_Pos 16 /**< \brief (TCC_INTENSET) Match or Capture Channel 0 Interrupt Enable */
+#define TCC_INTENSET_MC0 (1 << TCC_INTENSET_MC0_Pos)
+#define TCC_INTENSET_MC1_Pos 17 /**< \brief (TCC_INTENSET) Match or Capture Channel 1 Interrupt Enable */
+#define TCC_INTENSET_MC1 (1 << TCC_INTENSET_MC1_Pos)
+#define TCC_INTENSET_MC2_Pos 18 /**< \brief (TCC_INTENSET) Match or Capture Channel 2 Interrupt Enable */
+#define TCC_INTENSET_MC2 (1 << TCC_INTENSET_MC2_Pos)
+#define TCC_INTENSET_MC3_Pos 19 /**< \brief (TCC_INTENSET) Match or Capture Channel 3 Interrupt Enable */
+#define TCC_INTENSET_MC3 (1 << TCC_INTENSET_MC3_Pos)
+#define TCC_INTENSET_MC_Pos 16 /**< \brief (TCC_INTENSET) Match or Capture Channel x Interrupt Enable */
+#define TCC_INTENSET_MC_Msk (0xFul << TCC_INTENSET_MC_Pos)
+#define TCC_INTENSET_MC(value) (TCC_INTENSET_MC_Msk & ((value) << TCC_INTENSET_MC_Pos))
+#define TCC_INTENSET_MASK 0x000FF80Ful /**< \brief (TCC_INTENSET) MASK Register */
+
+/* -------- TCC_INTFLAG : (TCC Offset: 0x2C) (R/W 32) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint32_t OVF:1; /*!< bit: 0 Overflow */
+ __I uint32_t TRG:1; /*!< bit: 1 Retrigger */
+ __I uint32_t CNT:1; /*!< bit: 2 Counter */
+ __I uint32_t ERR:1; /*!< bit: 3 Error */
+ __I uint32_t :7; /*!< bit: 4..10 Reserved */
+ __I uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault */
+ __I uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A */
+ __I uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B */
+ __I uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 */
+ __I uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 */
+ __I uint32_t MC0:1; /*!< bit: 16 Match or Capture 0 */
+ __I uint32_t MC1:1; /*!< bit: 17 Match or Capture 1 */
+ __I uint32_t MC2:1; /*!< bit: 18 Match or Capture 2 */
+ __I uint32_t MC3:1; /*!< bit: 19 Match or Capture 3 */
+ __I uint32_t :12; /*!< bit: 20..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ __I uint32_t :16; /*!< bit: 0..15 Reserved */
+ __I uint32_t MC:4; /*!< bit: 16..19 Match or Capture x */
+ __I uint32_t :12; /*!< bit: 20..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_INTFLAG_OFFSET 0x2C /**< \brief (TCC_INTFLAG offset) Interrupt Flag Status and Clear */
+#define TCC_INTFLAG_RESETVALUE 0x00000000ul /**< \brief (TCC_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define TCC_INTFLAG_OVF_Pos 0 /**< \brief (TCC_INTFLAG) Overflow */
+#define TCC_INTFLAG_OVF (0x1ul << TCC_INTFLAG_OVF_Pos)
+#define TCC_INTFLAG_TRG_Pos 1 /**< \brief (TCC_INTFLAG) Retrigger */
+#define TCC_INTFLAG_TRG (0x1ul << TCC_INTFLAG_TRG_Pos)
+#define TCC_INTFLAG_CNT_Pos 2 /**< \brief (TCC_INTFLAG) Counter */
+#define TCC_INTFLAG_CNT (0x1ul << TCC_INTFLAG_CNT_Pos)
+#define TCC_INTFLAG_ERR_Pos 3 /**< \brief (TCC_INTFLAG) Error */
+#define TCC_INTFLAG_ERR (0x1ul << TCC_INTFLAG_ERR_Pos)
+#define TCC_INTFLAG_DFS_Pos 11 /**< \brief (TCC_INTFLAG) Non-Recoverable Debug Fault */
+#define TCC_INTFLAG_DFS (0x1ul << TCC_INTFLAG_DFS_Pos)
+#define TCC_INTFLAG_FAULTA_Pos 12 /**< \brief (TCC_INTFLAG) Recoverable Fault A */
+#define TCC_INTFLAG_FAULTA (0x1ul << TCC_INTFLAG_FAULTA_Pos)
+#define TCC_INTFLAG_FAULTB_Pos 13 /**< \brief (TCC_INTFLAG) Recoverable Fault B */
+#define TCC_INTFLAG_FAULTB (0x1ul << TCC_INTFLAG_FAULTB_Pos)
+#define TCC_INTFLAG_FAULT0_Pos 14 /**< \brief (TCC_INTFLAG) Non-Recoverable Fault 0 */
+#define TCC_INTFLAG_FAULT0 (0x1ul << TCC_INTFLAG_FAULT0_Pos)
+#define TCC_INTFLAG_FAULT1_Pos 15 /**< \brief (TCC_INTFLAG) Non-Recoverable Fault 1 */
+#define TCC_INTFLAG_FAULT1 (0x1ul << TCC_INTFLAG_FAULT1_Pos)
+#define TCC_INTFLAG_MC0_Pos 16 /**< \brief (TCC_INTFLAG) Match or Capture 0 */
+#define TCC_INTFLAG_MC0 (1 << TCC_INTFLAG_MC0_Pos)
+#define TCC_INTFLAG_MC1_Pos 17 /**< \brief (TCC_INTFLAG) Match or Capture 1 */
+#define TCC_INTFLAG_MC1 (1 << TCC_INTFLAG_MC1_Pos)
+#define TCC_INTFLAG_MC2_Pos 18 /**< \brief (TCC_INTFLAG) Match or Capture 2 */
+#define TCC_INTFLAG_MC2 (1 << TCC_INTFLAG_MC2_Pos)
+#define TCC_INTFLAG_MC3_Pos 19 /**< \brief (TCC_INTFLAG) Match or Capture 3 */
+#define TCC_INTFLAG_MC3 (1 << TCC_INTFLAG_MC3_Pos)
+#define TCC_INTFLAG_MC_Pos 16 /**< \brief (TCC_INTFLAG) Match or Capture x */
+#define TCC_INTFLAG_MC_Msk (0xFul << TCC_INTFLAG_MC_Pos)
+#define TCC_INTFLAG_MC(value) (TCC_INTFLAG_MC_Msk & ((value) << TCC_INTFLAG_MC_Pos))
+#define TCC_INTFLAG_MASK 0x000FF80Ful /**< \brief (TCC_INTFLAG) MASK Register */
+
+/* -------- TCC_STATUS : (TCC Offset: 0x30) (R/W 32) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t STOP:1; /*!< bit: 0 Stop */
+ uint32_t IDX:1; /*!< bit: 1 Ramp */
+ uint32_t :1; /*!< bit: 2 Reserved */
+ uint32_t DFS:1; /*!< bit: 3 Non-Recoverable Debug Fault State */
+ uint32_t SLAVE:1; /*!< bit: 4 Slave */
+ uint32_t PATTBV:1; /*!< bit: 5 Pattern Buffer Valid */
+ uint32_t WAVEBV:1; /*!< bit: 6 Wave Buffer Valid */
+ uint32_t PERBV:1; /*!< bit: 7 Period Buffer Valid */
+ uint32_t FAULTAIN:1; /*!< bit: 8 Recoverable Fault A Input */
+ uint32_t FAULTBIN:1; /*!< bit: 9 Recoverable Fault B Input */
+ uint32_t FAULT0IN:1; /*!< bit: 10 Non-Recoverable Fault0 Input */
+ uint32_t FAULT1IN:1; /*!< bit: 11 Non-Recoverable Fault1 Input */
+ uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A State */
+ uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B State */
+ uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 State */
+ uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 State */
+ uint32_t CCBV0:1; /*!< bit: 16 Compare Channel 0 Buffer Valid */
+ uint32_t CCBV1:1; /*!< bit: 17 Compare Channel 1 Buffer Valid */
+ uint32_t CCBV2:1; /*!< bit: 18 Compare Channel 2 Buffer Valid */
+ uint32_t CCBV3:1; /*!< bit: 19 Compare Channel 3 Buffer Valid */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t CMP0:1; /*!< bit: 24 Compare Channel 0 Value */
+ uint32_t CMP1:1; /*!< bit: 25 Compare Channel 1 Value */
+ uint32_t CMP2:1; /*!< bit: 26 Compare Channel 2 Value */
+ uint32_t CMP3:1; /*!< bit: 27 Compare Channel 3 Value */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :16; /*!< bit: 0..15 Reserved */
+ uint32_t CCBV:4; /*!< bit: 16..19 Compare Channel x Buffer Valid */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t CMP:4; /*!< bit: 24..27 Compare Channel x Value */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_STATUS_OFFSET 0x30 /**< \brief (TCC_STATUS offset) Status */
+#define TCC_STATUS_RESETVALUE 0x00000001ul /**< \brief (TCC_STATUS reset_value) Status */
+
+#define TCC_STATUS_STOP_Pos 0 /**< \brief (TCC_STATUS) Stop */
+#define TCC_STATUS_STOP (0x1ul << TCC_STATUS_STOP_Pos)
+#define TCC_STATUS_IDX_Pos 1 /**< \brief (TCC_STATUS) Ramp */
+#define TCC_STATUS_IDX (0x1ul << TCC_STATUS_IDX_Pos)
+#define TCC_STATUS_DFS_Pos 3 /**< \brief (TCC_STATUS) Non-Recoverable Debug Fault State */
+#define TCC_STATUS_DFS (0x1ul << TCC_STATUS_DFS_Pos)
+#define TCC_STATUS_SLAVE_Pos 4 /**< \brief (TCC_STATUS) Slave */
+#define TCC_STATUS_SLAVE (0x1ul << TCC_STATUS_SLAVE_Pos)
+#define TCC_STATUS_PATTBV_Pos 5 /**< \brief (TCC_STATUS) Pattern Buffer Valid */
+#define TCC_STATUS_PATTBV (0x1ul << TCC_STATUS_PATTBV_Pos)
+#define TCC_STATUS_WAVEBV_Pos 6 /**< \brief (TCC_STATUS) Wave Buffer Valid */
+#define TCC_STATUS_WAVEBV (0x1ul << TCC_STATUS_WAVEBV_Pos)
+#define TCC_STATUS_PERBV_Pos 7 /**< \brief (TCC_STATUS) Period Buffer Valid */
+#define TCC_STATUS_PERBV (0x1ul << TCC_STATUS_PERBV_Pos)
+#define TCC_STATUS_FAULTAIN_Pos 8 /**< \brief (TCC_STATUS) Recoverable Fault A Input */
+#define TCC_STATUS_FAULTAIN (0x1ul << TCC_STATUS_FAULTAIN_Pos)
+#define TCC_STATUS_FAULTBIN_Pos 9 /**< \brief (TCC_STATUS) Recoverable Fault B Input */
+#define TCC_STATUS_FAULTBIN (0x1ul << TCC_STATUS_FAULTBIN_Pos)
+#define TCC_STATUS_FAULT0IN_Pos 10 /**< \brief (TCC_STATUS) Non-Recoverable Fault0 Input */
+#define TCC_STATUS_FAULT0IN (0x1ul << TCC_STATUS_FAULT0IN_Pos)
+#define TCC_STATUS_FAULT1IN_Pos 11 /**< \brief (TCC_STATUS) Non-Recoverable Fault1 Input */
+#define TCC_STATUS_FAULT1IN (0x1ul << TCC_STATUS_FAULT1IN_Pos)
+#define TCC_STATUS_FAULTA_Pos 12 /**< \brief (TCC_STATUS) Recoverable Fault A State */
+#define TCC_STATUS_FAULTA (0x1ul << TCC_STATUS_FAULTA_Pos)
+#define TCC_STATUS_FAULTB_Pos 13 /**< \brief (TCC_STATUS) Recoverable Fault B State */
+#define TCC_STATUS_FAULTB (0x1ul << TCC_STATUS_FAULTB_Pos)
+#define TCC_STATUS_FAULT0_Pos 14 /**< \brief (TCC_STATUS) Non-Recoverable Fault 0 State */
+#define TCC_STATUS_FAULT0 (0x1ul << TCC_STATUS_FAULT0_Pos)
+#define TCC_STATUS_FAULT1_Pos 15 /**< \brief (TCC_STATUS) Non-Recoverable Fault 1 State */
+#define TCC_STATUS_FAULT1 (0x1ul << TCC_STATUS_FAULT1_Pos)
+#define TCC_STATUS_CCBV0_Pos 16 /**< \brief (TCC_STATUS) Compare Channel 0 Buffer Valid */
+#define TCC_STATUS_CCBV0 (1 << TCC_STATUS_CCBV0_Pos)
+#define TCC_STATUS_CCBV1_Pos 17 /**< \brief (TCC_STATUS) Compare Channel 1 Buffer Valid */
+#define TCC_STATUS_CCBV1 (1 << TCC_STATUS_CCBV1_Pos)
+#define TCC_STATUS_CCBV2_Pos 18 /**< \brief (TCC_STATUS) Compare Channel 2 Buffer Valid */
+#define TCC_STATUS_CCBV2 (1 << TCC_STATUS_CCBV2_Pos)
+#define TCC_STATUS_CCBV3_Pos 19 /**< \brief (TCC_STATUS) Compare Channel 3 Buffer Valid */
+#define TCC_STATUS_CCBV3 (1 << TCC_STATUS_CCBV3_Pos)
+#define TCC_STATUS_CCBV_Pos 16 /**< \brief (TCC_STATUS) Compare Channel x Buffer Valid */
+#define TCC_STATUS_CCBV_Msk (0xFul << TCC_STATUS_CCBV_Pos)
+#define TCC_STATUS_CCBV(value) (TCC_STATUS_CCBV_Msk & ((value) << TCC_STATUS_CCBV_Pos))
+#define TCC_STATUS_CMP0_Pos 24 /**< \brief (TCC_STATUS) Compare Channel 0 Value */
+#define TCC_STATUS_CMP0 (1 << TCC_STATUS_CMP0_Pos)
+#define TCC_STATUS_CMP1_Pos 25 /**< \brief (TCC_STATUS) Compare Channel 1 Value */
+#define TCC_STATUS_CMP1 (1 << TCC_STATUS_CMP1_Pos)
+#define TCC_STATUS_CMP2_Pos 26 /**< \brief (TCC_STATUS) Compare Channel 2 Value */
+#define TCC_STATUS_CMP2 (1 << TCC_STATUS_CMP2_Pos)
+#define TCC_STATUS_CMP3_Pos 27 /**< \brief (TCC_STATUS) Compare Channel 3 Value */
+#define TCC_STATUS_CMP3 (1 << TCC_STATUS_CMP3_Pos)
+#define TCC_STATUS_CMP_Pos 24 /**< \brief (TCC_STATUS) Compare Channel x Value */
+#define TCC_STATUS_CMP_Msk (0xFul << TCC_STATUS_CMP_Pos)
+#define TCC_STATUS_CMP(value) (TCC_STATUS_CMP_Msk & ((value) << TCC_STATUS_CMP_Pos))
+#define TCC_STATUS_MASK 0x0F0FFFFBul /**< \brief (TCC_STATUS) MASK Register */
+
+/* -------- TCC_COUNT : (TCC Offset: 0x34) (R/W 32) Count -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct { // DITH4 mode
+ uint32_t :4; /*!< bit: 0.. 3 Reserved */
+ uint32_t COUNT:20; /*!< bit: 4..23 Counter Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH4; /*!< Structure used for DITH4 */
+ struct { // DITH5 mode
+ uint32_t :5; /*!< bit: 0.. 4 Reserved */
+ uint32_t COUNT:19; /*!< bit: 5..23 Counter Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH5; /*!< Structure used for DITH5 */
+ struct { // DITH6 mode
+ uint32_t :6; /*!< bit: 0.. 5 Reserved */
+ uint32_t COUNT:18; /*!< bit: 6..23 Counter Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH6; /*!< Structure used for DITH6 */
+ struct {
+ uint32_t COUNT:24; /*!< bit: 0..23 Counter Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_COUNT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_COUNT_OFFSET 0x34 /**< \brief (TCC_COUNT offset) Count */
+#define TCC_COUNT_RESETVALUE 0x00000000ul /**< \brief (TCC_COUNT reset_value) Count */
+
+// DITH4 mode
+#define TCC_COUNT_DITH4_COUNT_Pos 4 /**< \brief (TCC_COUNT_DITH4) Counter Value */
+#define TCC_COUNT_DITH4_COUNT_Msk (0xFFFFFul << TCC_COUNT_DITH4_COUNT_Pos)
+#define TCC_COUNT_DITH4_COUNT(value) (TCC_COUNT_DITH4_COUNT_Msk & ((value) << TCC_COUNT_DITH4_COUNT_Pos))
+#define TCC_COUNT_DITH4_MASK 0x00FFFFF0ul /**< \brief (TCC_COUNT_DITH4) MASK Register */
+
+// DITH5 mode
+#define TCC_COUNT_DITH5_COUNT_Pos 5 /**< \brief (TCC_COUNT_DITH5) Counter Value */
+#define TCC_COUNT_DITH5_COUNT_Msk (0x7FFFFul << TCC_COUNT_DITH5_COUNT_Pos)
+#define TCC_COUNT_DITH5_COUNT(value) (TCC_COUNT_DITH5_COUNT_Msk & ((value) << TCC_COUNT_DITH5_COUNT_Pos))
+#define TCC_COUNT_DITH5_MASK 0x00FFFFE0ul /**< \brief (TCC_COUNT_DITH5) MASK Register */
+
+// DITH6 mode
+#define TCC_COUNT_DITH6_COUNT_Pos 6 /**< \brief (TCC_COUNT_DITH6) Counter Value */
+#define TCC_COUNT_DITH6_COUNT_Msk (0x3FFFFul << TCC_COUNT_DITH6_COUNT_Pos)
+#define TCC_COUNT_DITH6_COUNT(value) (TCC_COUNT_DITH6_COUNT_Msk & ((value) << TCC_COUNT_DITH6_COUNT_Pos))
+#define TCC_COUNT_DITH6_MASK 0x00FFFFC0ul /**< \brief (TCC_COUNT_DITH6) MASK Register */
+
+#define TCC_COUNT_COUNT_Pos 0 /**< \brief (TCC_COUNT) Counter Value */
+#define TCC_COUNT_COUNT_Msk (0xFFFFFFul << TCC_COUNT_COUNT_Pos)
+#define TCC_COUNT_COUNT(value) (TCC_COUNT_COUNT_Msk & ((value) << TCC_COUNT_COUNT_Pos))
+#define TCC_COUNT_MASK 0x00FFFFFFul /**< \brief (TCC_COUNT) MASK Register */
+
+/* -------- TCC_PATT : (TCC Offset: 0x38) (R/W 16) Pattern -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t PGE0:1; /*!< bit: 0 Pattern Generator 0 Output Enable */
+ uint16_t PGE1:1; /*!< bit: 1 Pattern Generator 1 Output Enable */
+ uint16_t PGE2:1; /*!< bit: 2 Pattern Generator 2 Output Enable */
+ uint16_t PGE3:1; /*!< bit: 3 Pattern Generator 3 Output Enable */
+ uint16_t PGE4:1; /*!< bit: 4 Pattern Generator 4 Output Enable */
+ uint16_t PGE5:1; /*!< bit: 5 Pattern Generator 5 Output Enable */
+ uint16_t PGE6:1; /*!< bit: 6 Pattern Generator 6 Output Enable */
+ uint16_t PGE7:1; /*!< bit: 7 Pattern Generator 7 Output Enable */
+ uint16_t PGV0:1; /*!< bit: 8 Pattern Generator 0 Output Value */
+ uint16_t PGV1:1; /*!< bit: 9 Pattern Generator 1 Output Value */
+ uint16_t PGV2:1; /*!< bit: 10 Pattern Generator 2 Output Value */
+ uint16_t PGV3:1; /*!< bit: 11 Pattern Generator 3 Output Value */
+ uint16_t PGV4:1; /*!< bit: 12 Pattern Generator 4 Output Value */
+ uint16_t PGV5:1; /*!< bit: 13 Pattern Generator 5 Output Value */
+ uint16_t PGV6:1; /*!< bit: 14 Pattern Generator 6 Output Value */
+ uint16_t PGV7:1; /*!< bit: 15 Pattern Generator 7 Output Value */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t PGE:8; /*!< bit: 0.. 7 Pattern Generator x Output Enable */
+ uint16_t PGV:8; /*!< bit: 8..15 Pattern Generator x Output Value */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} TCC_PATT_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_PATT_OFFSET 0x38 /**< \brief (TCC_PATT offset) Pattern */
+#define TCC_PATT_RESETVALUE 0x0000ul /**< \brief (TCC_PATT reset_value) Pattern */
+
+#define TCC_PATT_PGE0_Pos 0 /**< \brief (TCC_PATT) Pattern Generator 0 Output Enable */
+#define TCC_PATT_PGE0 (1 << TCC_PATT_PGE0_Pos)
+#define TCC_PATT_PGE1_Pos 1 /**< \brief (TCC_PATT) Pattern Generator 1 Output Enable */
+#define TCC_PATT_PGE1 (1 << TCC_PATT_PGE1_Pos)
+#define TCC_PATT_PGE2_Pos 2 /**< \brief (TCC_PATT) Pattern Generator 2 Output Enable */
+#define TCC_PATT_PGE2 (1 << TCC_PATT_PGE2_Pos)
+#define TCC_PATT_PGE3_Pos 3 /**< \brief (TCC_PATT) Pattern Generator 3 Output Enable */
+#define TCC_PATT_PGE3 (1 << TCC_PATT_PGE3_Pos)
+#define TCC_PATT_PGE4_Pos 4 /**< \brief (TCC_PATT) Pattern Generator 4 Output Enable */
+#define TCC_PATT_PGE4 (1 << TCC_PATT_PGE4_Pos)
+#define TCC_PATT_PGE5_Pos 5 /**< \brief (TCC_PATT) Pattern Generator 5 Output Enable */
+#define TCC_PATT_PGE5 (1 << TCC_PATT_PGE5_Pos)
+#define TCC_PATT_PGE6_Pos 6 /**< \brief (TCC_PATT) Pattern Generator 6 Output Enable */
+#define TCC_PATT_PGE6 (1 << TCC_PATT_PGE6_Pos)
+#define TCC_PATT_PGE7_Pos 7 /**< \brief (TCC_PATT) Pattern Generator 7 Output Enable */
+#define TCC_PATT_PGE7 (1 << TCC_PATT_PGE7_Pos)
+#define TCC_PATT_PGE_Pos 0 /**< \brief (TCC_PATT) Pattern Generator x Output Enable */
+#define TCC_PATT_PGE_Msk (0xFFul << TCC_PATT_PGE_Pos)
+#define TCC_PATT_PGE(value) (TCC_PATT_PGE_Msk & ((value) << TCC_PATT_PGE_Pos))
+#define TCC_PATT_PGV0_Pos 8 /**< \brief (TCC_PATT) Pattern Generator 0 Output Value */
+#define TCC_PATT_PGV0 (1 << TCC_PATT_PGV0_Pos)
+#define TCC_PATT_PGV1_Pos 9 /**< \brief (TCC_PATT) Pattern Generator 1 Output Value */
+#define TCC_PATT_PGV1 (1 << TCC_PATT_PGV1_Pos)
+#define TCC_PATT_PGV2_Pos 10 /**< \brief (TCC_PATT) Pattern Generator 2 Output Value */
+#define TCC_PATT_PGV2 (1 << TCC_PATT_PGV2_Pos)
+#define TCC_PATT_PGV3_Pos 11 /**< \brief (TCC_PATT) Pattern Generator 3 Output Value */
+#define TCC_PATT_PGV3 (1 << TCC_PATT_PGV3_Pos)
+#define TCC_PATT_PGV4_Pos 12 /**< \brief (TCC_PATT) Pattern Generator 4 Output Value */
+#define TCC_PATT_PGV4 (1 << TCC_PATT_PGV4_Pos)
+#define TCC_PATT_PGV5_Pos 13 /**< \brief (TCC_PATT) Pattern Generator 5 Output Value */
+#define TCC_PATT_PGV5 (1 << TCC_PATT_PGV5_Pos)
+#define TCC_PATT_PGV6_Pos 14 /**< \brief (TCC_PATT) Pattern Generator 6 Output Value */
+#define TCC_PATT_PGV6 (1 << TCC_PATT_PGV6_Pos)
+#define TCC_PATT_PGV7_Pos 15 /**< \brief (TCC_PATT) Pattern Generator 7 Output Value */
+#define TCC_PATT_PGV7 (1 << TCC_PATT_PGV7_Pos)
+#define TCC_PATT_PGV_Pos 8 /**< \brief (TCC_PATT) Pattern Generator x Output Value */
+#define TCC_PATT_PGV_Msk (0xFFul << TCC_PATT_PGV_Pos)
+#define TCC_PATT_PGV(value) (TCC_PATT_PGV_Msk & ((value) << TCC_PATT_PGV_Pos))
+#define TCC_PATT_MASK 0xFFFFul /**< \brief (TCC_PATT) MASK Register */
+
+/* -------- TCC_WAVE : (TCC Offset: 0x3C) (R/W 32) Waveform Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t WAVEGEN:3; /*!< bit: 0.. 2 Waveform Generation */
+ uint32_t :1; /*!< bit: 3 Reserved */
+ uint32_t RAMP:2; /*!< bit: 4.. 5 Ramp Mode */
+ uint32_t :1; /*!< bit: 6 Reserved */
+ uint32_t CIPEREN:1; /*!< bit: 7 Circular period Enable */
+ uint32_t CICCEN0:1; /*!< bit: 8 Circular Channel 0 Enable */
+ uint32_t CICCEN1:1; /*!< bit: 9 Circular Channel 1 Enable */
+ uint32_t CICCEN2:1; /*!< bit: 10 Circular Channel 2 Enable */
+ uint32_t CICCEN3:1; /*!< bit: 11 Circular Channel 3 Enable */
+ uint32_t :4; /*!< bit: 12..15 Reserved */
+ uint32_t POL0:1; /*!< bit: 16 Channel 0 Polarity */
+ uint32_t POL1:1; /*!< bit: 17 Channel 1 Polarity */
+ uint32_t POL2:1; /*!< bit: 18 Channel 2 Polarity */
+ uint32_t POL3:1; /*!< bit: 19 Channel 3 Polarity */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t SWAP0:1; /*!< bit: 24 Swap DTI Output Pair 0 */
+ uint32_t SWAP1:1; /*!< bit: 25 Swap DTI Output Pair 1 */
+ uint32_t SWAP2:1; /*!< bit: 26 Swap DTI Output Pair 2 */
+ uint32_t SWAP3:1; /*!< bit: 27 Swap DTI Output Pair 3 */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :8; /*!< bit: 0.. 7 Reserved */
+ uint32_t CICCEN:4; /*!< bit: 8..11 Circular Channel x Enable */
+ uint32_t :4; /*!< bit: 12..15 Reserved */
+ uint32_t POL:4; /*!< bit: 16..19 Channel x Polarity */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t SWAP:4; /*!< bit: 24..27 Swap DTI Output Pair x */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_WAVE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_WAVE_OFFSET 0x3C /**< \brief (TCC_WAVE offset) Waveform Control */
+#define TCC_WAVE_RESETVALUE 0x00000000ul /**< \brief (TCC_WAVE reset_value) Waveform Control */
+
+#define TCC_WAVE_WAVEGEN_Pos 0 /**< \brief (TCC_WAVE) Waveform Generation */
+#define TCC_WAVE_WAVEGEN_Msk (0x7ul << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN(value) (TCC_WAVE_WAVEGEN_Msk & ((value) << TCC_WAVE_WAVEGEN_Pos))
+#define TCC_WAVE_WAVEGEN_NFRQ_Val 0x0ul /**< \brief (TCC_WAVE) Normal frequency */
+#define TCC_WAVE_WAVEGEN_MFRQ_Val 0x1ul /**< \brief (TCC_WAVE) Match frequency */
+#define TCC_WAVE_WAVEGEN_NPWM_Val 0x2ul /**< \brief (TCC_WAVE) Normal PWM */
+#define TCC_WAVE_WAVEGEN_DSCRITICAL_Val 0x4ul /**< \brief (TCC_WAVE) Dual-slope critical */
+#define TCC_WAVE_WAVEGEN_DSBOTTOM_Val 0x5ul /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches ZERO */
+#define TCC_WAVE_WAVEGEN_DSBOTH_Val 0x6ul /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP */
+#define TCC_WAVE_WAVEGEN_DSTOP_Val 0x7ul /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches TOP */
+#define TCC_WAVE_WAVEGEN_NFRQ (TCC_WAVE_WAVEGEN_NFRQ_Val << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN_MFRQ (TCC_WAVE_WAVEGEN_MFRQ_Val << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN_NPWM (TCC_WAVE_WAVEGEN_NPWM_Val << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN_DSCRITICAL (TCC_WAVE_WAVEGEN_DSCRITICAL_Val << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN_DSBOTTOM (TCC_WAVE_WAVEGEN_DSBOTTOM_Val << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN_DSBOTH (TCC_WAVE_WAVEGEN_DSBOTH_Val << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_WAVEGEN_DSTOP (TCC_WAVE_WAVEGEN_DSTOP_Val << TCC_WAVE_WAVEGEN_Pos)
+#define TCC_WAVE_RAMP_Pos 4 /**< \brief (TCC_WAVE) Ramp Mode */
+#define TCC_WAVE_RAMP_Msk (0x3ul << TCC_WAVE_RAMP_Pos)
+#define TCC_WAVE_RAMP(value) (TCC_WAVE_RAMP_Msk & ((value) << TCC_WAVE_RAMP_Pos))
+#define TCC_WAVE_RAMP_RAMP1_Val 0x0ul /**< \brief (TCC_WAVE) RAMP1 operation */
+#define TCC_WAVE_RAMP_RAMP2A_Val 0x1ul /**< \brief (TCC_WAVE) Alternative RAMP2 operation */
+#define TCC_WAVE_RAMP_RAMP2_Val 0x2ul /**< \brief (TCC_WAVE) RAMP2 operation */
+#define TCC_WAVE_RAMP_RAMP1 (TCC_WAVE_RAMP_RAMP1_Val << TCC_WAVE_RAMP_Pos)
+#define TCC_WAVE_RAMP_RAMP2A (TCC_WAVE_RAMP_RAMP2A_Val << TCC_WAVE_RAMP_Pos)
+#define TCC_WAVE_RAMP_RAMP2 (TCC_WAVE_RAMP_RAMP2_Val << TCC_WAVE_RAMP_Pos)
+#define TCC_WAVE_CIPEREN_Pos 7 /**< \brief (TCC_WAVE) Circular period Enable */
+#define TCC_WAVE_CIPEREN (0x1ul << TCC_WAVE_CIPEREN_Pos)
+#define TCC_WAVE_CICCEN0_Pos 8 /**< \brief (TCC_WAVE) Circular Channel 0 Enable */
+#define TCC_WAVE_CICCEN0 (1 << TCC_WAVE_CICCEN0_Pos)
+#define TCC_WAVE_CICCEN1_Pos 9 /**< \brief (TCC_WAVE) Circular Channel 1 Enable */
+#define TCC_WAVE_CICCEN1 (1 << TCC_WAVE_CICCEN1_Pos)
+#define TCC_WAVE_CICCEN2_Pos 10 /**< \brief (TCC_WAVE) Circular Channel 2 Enable */
+#define TCC_WAVE_CICCEN2 (1 << TCC_WAVE_CICCEN2_Pos)
+#define TCC_WAVE_CICCEN3_Pos 11 /**< \brief (TCC_WAVE) Circular Channel 3 Enable */
+#define TCC_WAVE_CICCEN3 (1 << TCC_WAVE_CICCEN3_Pos)
+#define TCC_WAVE_CICCEN_Pos 8 /**< \brief (TCC_WAVE) Circular Channel x Enable */
+#define TCC_WAVE_CICCEN_Msk (0xFul << TCC_WAVE_CICCEN_Pos)
+#define TCC_WAVE_CICCEN(value) (TCC_WAVE_CICCEN_Msk & ((value) << TCC_WAVE_CICCEN_Pos))
+#define TCC_WAVE_POL0_Pos 16 /**< \brief (TCC_WAVE) Channel 0 Polarity */
+#define TCC_WAVE_POL0 (1 << TCC_WAVE_POL0_Pos)
+#define TCC_WAVE_POL1_Pos 17 /**< \brief (TCC_WAVE) Channel 1 Polarity */
+#define TCC_WAVE_POL1 (1 << TCC_WAVE_POL1_Pos)
+#define TCC_WAVE_POL2_Pos 18 /**< \brief (TCC_WAVE) Channel 2 Polarity */
+#define TCC_WAVE_POL2 (1 << TCC_WAVE_POL2_Pos)
+#define TCC_WAVE_POL3_Pos 19 /**< \brief (TCC_WAVE) Channel 3 Polarity */
+#define TCC_WAVE_POL3 (1 << TCC_WAVE_POL3_Pos)
+#define TCC_WAVE_POL_Pos 16 /**< \brief (TCC_WAVE) Channel x Polarity */
+#define TCC_WAVE_POL_Msk (0xFul << TCC_WAVE_POL_Pos)
+#define TCC_WAVE_POL(value) (TCC_WAVE_POL_Msk & ((value) << TCC_WAVE_POL_Pos))
+#define TCC_WAVE_SWAP0_Pos 24 /**< \brief (TCC_WAVE) Swap DTI Output Pair 0 */
+#define TCC_WAVE_SWAP0 (1 << TCC_WAVE_SWAP0_Pos)
+#define TCC_WAVE_SWAP1_Pos 25 /**< \brief (TCC_WAVE) Swap DTI Output Pair 1 */
+#define TCC_WAVE_SWAP1 (1 << TCC_WAVE_SWAP1_Pos)
+#define TCC_WAVE_SWAP2_Pos 26 /**< \brief (TCC_WAVE) Swap DTI Output Pair 2 */
+#define TCC_WAVE_SWAP2 (1 << TCC_WAVE_SWAP2_Pos)
+#define TCC_WAVE_SWAP3_Pos 27 /**< \brief (TCC_WAVE) Swap DTI Output Pair 3 */
+#define TCC_WAVE_SWAP3 (1 << TCC_WAVE_SWAP3_Pos)
+#define TCC_WAVE_SWAP_Pos 24 /**< \brief (TCC_WAVE) Swap DTI Output Pair x */
+#define TCC_WAVE_SWAP_Msk (0xFul << TCC_WAVE_SWAP_Pos)
+#define TCC_WAVE_SWAP(value) (TCC_WAVE_SWAP_Msk & ((value) << TCC_WAVE_SWAP_Pos))
+#define TCC_WAVE_MASK 0x0F0F0FB7ul /**< \brief (TCC_WAVE) MASK Register */
+
+/* -------- TCC_PER : (TCC Offset: 0x40) (R/W 32) Period -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct { // DITH4 mode
+ uint32_t DITHERCY:4; /*!< bit: 0.. 3 Dithering Cycle Number */
+ uint32_t PER:20; /*!< bit: 4..23 Period Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH4; /*!< Structure used for DITH4 */
+ struct { // DITH5 mode
+ uint32_t DITHERCY:5; /*!< bit: 0.. 4 Dithering Cycle Number */
+ uint32_t PER:19; /*!< bit: 5..23 Period Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH5; /*!< Structure used for DITH5 */
+ struct { // DITH6 mode
+ uint32_t DITHERCY:6; /*!< bit: 0.. 5 Dithering Cycle Number */
+ uint32_t PER:18; /*!< bit: 6..23 Period Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH6; /*!< Structure used for DITH6 */
+ struct {
+ uint32_t PER:24; /*!< bit: 0..23 Period Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_PER_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_PER_OFFSET 0x40 /**< \brief (TCC_PER offset) Period */
+#define TCC_PER_RESETVALUE 0xFFFFFFFFul /**< \brief (TCC_PER reset_value) Period */
+
+// DITH4 mode
+#define TCC_PER_DITH4_DITHERCY_Pos 0 /**< \brief (TCC_PER_DITH4) Dithering Cycle Number */
+#define TCC_PER_DITH4_DITHERCY_Msk (0xFul << TCC_PER_DITH4_DITHERCY_Pos)
+#define TCC_PER_DITH4_DITHERCY(value) (TCC_PER_DITH4_DITHERCY_Msk & ((value) << TCC_PER_DITH4_DITHERCY_Pos))
+#define TCC_PER_DITH4_PER_Pos 4 /**< \brief (TCC_PER_DITH4) Period Value */
+#define TCC_PER_DITH4_PER_Msk (0xFFFFFul << TCC_PER_DITH4_PER_Pos)
+#define TCC_PER_DITH4_PER(value) (TCC_PER_DITH4_PER_Msk & ((value) << TCC_PER_DITH4_PER_Pos))
+#define TCC_PER_DITH4_MASK 0x00FFFFFFul /**< \brief (TCC_PER_DITH4) MASK Register */
+
+// DITH5 mode
+#define TCC_PER_DITH5_DITHERCY_Pos 0 /**< \brief (TCC_PER_DITH5) Dithering Cycle Number */
+#define TCC_PER_DITH5_DITHERCY_Msk (0x1Ful << TCC_PER_DITH5_DITHERCY_Pos)
+#define TCC_PER_DITH5_DITHERCY(value) (TCC_PER_DITH5_DITHERCY_Msk & ((value) << TCC_PER_DITH5_DITHERCY_Pos))
+#define TCC_PER_DITH5_PER_Pos 5 /**< \brief (TCC_PER_DITH5) Period Value */
+#define TCC_PER_DITH5_PER_Msk (0x7FFFFul << TCC_PER_DITH5_PER_Pos)
+#define TCC_PER_DITH5_PER(value) (TCC_PER_DITH5_PER_Msk & ((value) << TCC_PER_DITH5_PER_Pos))
+#define TCC_PER_DITH5_MASK 0x00FFFFFFul /**< \brief (TCC_PER_DITH5) MASK Register */
+
+// DITH6 mode
+#define TCC_PER_DITH6_DITHERCY_Pos 0 /**< \brief (TCC_PER_DITH6) Dithering Cycle Number */
+#define TCC_PER_DITH6_DITHERCY_Msk (0x3Ful << TCC_PER_DITH6_DITHERCY_Pos)
+#define TCC_PER_DITH6_DITHERCY(value) (TCC_PER_DITH6_DITHERCY_Msk & ((value) << TCC_PER_DITH6_DITHERCY_Pos))
+#define TCC_PER_DITH6_PER_Pos 6 /**< \brief (TCC_PER_DITH6) Period Value */
+#define TCC_PER_DITH6_PER_Msk (0x3FFFFul << TCC_PER_DITH6_PER_Pos)
+#define TCC_PER_DITH6_PER(value) (TCC_PER_DITH6_PER_Msk & ((value) << TCC_PER_DITH6_PER_Pos))
+#define TCC_PER_DITH6_MASK 0x00FFFFFFul /**< \brief (TCC_PER_DITH6) MASK Register */
+
+#define TCC_PER_PER_Pos 0 /**< \brief (TCC_PER) Period Value */
+#define TCC_PER_PER_Msk (0xFFFFFFul << TCC_PER_PER_Pos)
+#define TCC_PER_PER(value) (TCC_PER_PER_Msk & ((value) << TCC_PER_PER_Pos))
+#define TCC_PER_MASK 0x00FFFFFFul /**< \brief (TCC_PER) MASK Register */
+
+/* -------- TCC_CC : (TCC Offset: 0x44) (R/W 32) Compare and Capture -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct { // DITH4 mode
+ uint32_t DITHERCY:4; /*!< bit: 0.. 3 Dithering Cycle Number */
+ uint32_t CC:20; /*!< bit: 4..23 Channel Compare/Capture Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH4; /*!< Structure used for DITH4 */
+ struct { // DITH5 mode
+ uint32_t DITHERCY:5; /*!< bit: 0.. 4 Dithering Cycle Number */
+ uint32_t CC:19; /*!< bit: 5..23 Channel Compare/Capture Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH5; /*!< Structure used for DITH5 */
+ struct { // DITH6 mode
+ uint32_t DITHERCY:6; /*!< bit: 0.. 5 Dithering Cycle Number */
+ uint32_t CC:18; /*!< bit: 6..23 Channel Compare/Capture Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH6; /*!< Structure used for DITH6 */
+ struct {
+ uint32_t CC:24; /*!< bit: 0..23 Channel Compare/Capture Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_CC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_CC_OFFSET 0x44 /**< \brief (TCC_CC offset) Compare and Capture */
+#define TCC_CC_RESETVALUE 0x00000000ul /**< \brief (TCC_CC reset_value) Compare and Capture */
+
+// DITH4 mode
+#define TCC_CC_DITH4_DITHERCY_Pos 0 /**< \brief (TCC_CC_DITH4) Dithering Cycle Number */
+#define TCC_CC_DITH4_DITHERCY_Msk (0xFul << TCC_CC_DITH4_DITHERCY_Pos)
+#define TCC_CC_DITH4_DITHERCY(value) (TCC_CC_DITH4_DITHERCY_Msk & ((value) << TCC_CC_DITH4_DITHERCY_Pos))
+#define TCC_CC_DITH4_CC_Pos 4 /**< \brief (TCC_CC_DITH4) Channel Compare/Capture Value */
+#define TCC_CC_DITH4_CC_Msk (0xFFFFFul << TCC_CC_DITH4_CC_Pos)
+#define TCC_CC_DITH4_CC(value) (TCC_CC_DITH4_CC_Msk & ((value) << TCC_CC_DITH4_CC_Pos))
+#define TCC_CC_DITH4_MASK 0x00FFFFFFul /**< \brief (TCC_CC_DITH4) MASK Register */
+
+// DITH5 mode
+#define TCC_CC_DITH5_DITHERCY_Pos 0 /**< \brief (TCC_CC_DITH5) Dithering Cycle Number */
+#define TCC_CC_DITH5_DITHERCY_Msk (0x1Ful << TCC_CC_DITH5_DITHERCY_Pos)
+#define TCC_CC_DITH5_DITHERCY(value) (TCC_CC_DITH5_DITHERCY_Msk & ((value) << TCC_CC_DITH5_DITHERCY_Pos))
+#define TCC_CC_DITH5_CC_Pos 5 /**< \brief (TCC_CC_DITH5) Channel Compare/Capture Value */
+#define TCC_CC_DITH5_CC_Msk (0x7FFFFul << TCC_CC_DITH5_CC_Pos)
+#define TCC_CC_DITH5_CC(value) (TCC_CC_DITH5_CC_Msk & ((value) << TCC_CC_DITH5_CC_Pos))
+#define TCC_CC_DITH5_MASK 0x00FFFFFFul /**< \brief (TCC_CC_DITH5) MASK Register */
+
+// DITH6 mode
+#define TCC_CC_DITH6_DITHERCY_Pos 0 /**< \brief (TCC_CC_DITH6) Dithering Cycle Number */
+#define TCC_CC_DITH6_DITHERCY_Msk (0x3Ful << TCC_CC_DITH6_DITHERCY_Pos)
+#define TCC_CC_DITH6_DITHERCY(value) (TCC_CC_DITH6_DITHERCY_Msk & ((value) << TCC_CC_DITH6_DITHERCY_Pos))
+#define TCC_CC_DITH6_CC_Pos 6 /**< \brief (TCC_CC_DITH6) Channel Compare/Capture Value */
+#define TCC_CC_DITH6_CC_Msk (0x3FFFFul << TCC_CC_DITH6_CC_Pos)
+#define TCC_CC_DITH6_CC(value) (TCC_CC_DITH6_CC_Msk & ((value) << TCC_CC_DITH6_CC_Pos))
+#define TCC_CC_DITH6_MASK 0x00FFFFFFul /**< \brief (TCC_CC_DITH6) MASK Register */
+
+#define TCC_CC_CC_Pos 0 /**< \brief (TCC_CC) Channel Compare/Capture Value */
+#define TCC_CC_CC_Msk (0xFFFFFFul << TCC_CC_CC_Pos)
+#define TCC_CC_CC(value) (TCC_CC_CC_Msk & ((value) << TCC_CC_CC_Pos))
+#define TCC_CC_MASK 0x00FFFFFFul /**< \brief (TCC_CC) MASK Register */
+
+/* -------- TCC_PATTB : (TCC Offset: 0x64) (R/W 16) Pattern Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t PGEB0:1; /*!< bit: 0 Pattern Generator 0 Output Enable Buffer */
+ uint16_t PGEB1:1; /*!< bit: 1 Pattern Generator 1 Output Enable Buffer */
+ uint16_t PGEB2:1; /*!< bit: 2 Pattern Generator 2 Output Enable Buffer */
+ uint16_t PGEB3:1; /*!< bit: 3 Pattern Generator 3 Output Enable Buffer */
+ uint16_t PGEB4:1; /*!< bit: 4 Pattern Generator 4 Output Enable Buffer */
+ uint16_t PGEB5:1; /*!< bit: 5 Pattern Generator 5 Output Enable Buffer */
+ uint16_t PGEB6:1; /*!< bit: 6 Pattern Generator 6 Output Enable Buffer */
+ uint16_t PGEB7:1; /*!< bit: 7 Pattern Generator 7 Output Enable Buffer */
+ uint16_t PGVB0:1; /*!< bit: 8 Pattern Generator 0 Output Enable */
+ uint16_t PGVB1:1; /*!< bit: 9 Pattern Generator 1 Output Enable */
+ uint16_t PGVB2:1; /*!< bit: 10 Pattern Generator 2 Output Enable */
+ uint16_t PGVB3:1; /*!< bit: 11 Pattern Generator 3 Output Enable */
+ uint16_t PGVB4:1; /*!< bit: 12 Pattern Generator 4 Output Enable */
+ uint16_t PGVB5:1; /*!< bit: 13 Pattern Generator 5 Output Enable */
+ uint16_t PGVB6:1; /*!< bit: 14 Pattern Generator 6 Output Enable */
+ uint16_t PGVB7:1; /*!< bit: 15 Pattern Generator 7 Output Enable */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t PGEB:8; /*!< bit: 0.. 7 Pattern Generator x Output Enable Buffer */
+ uint16_t PGVB:8; /*!< bit: 8..15 Pattern Generator x Output Enable */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} TCC_PATTB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_PATTB_OFFSET 0x64 /**< \brief (TCC_PATTB offset) Pattern Buffer */
+#define TCC_PATTB_RESETVALUE 0x0000ul /**< \brief (TCC_PATTB reset_value) Pattern Buffer */
+
+#define TCC_PATTB_PGEB0_Pos 0 /**< \brief (TCC_PATTB) Pattern Generator 0 Output Enable Buffer */
+#define TCC_PATTB_PGEB0 (1 << TCC_PATTB_PGEB0_Pos)
+#define TCC_PATTB_PGEB1_Pos 1 /**< \brief (TCC_PATTB) Pattern Generator 1 Output Enable Buffer */
+#define TCC_PATTB_PGEB1 (1 << TCC_PATTB_PGEB1_Pos)
+#define TCC_PATTB_PGEB2_Pos 2 /**< \brief (TCC_PATTB) Pattern Generator 2 Output Enable Buffer */
+#define TCC_PATTB_PGEB2 (1 << TCC_PATTB_PGEB2_Pos)
+#define TCC_PATTB_PGEB3_Pos 3 /**< \brief (TCC_PATTB) Pattern Generator 3 Output Enable Buffer */
+#define TCC_PATTB_PGEB3 (1 << TCC_PATTB_PGEB3_Pos)
+#define TCC_PATTB_PGEB4_Pos 4 /**< \brief (TCC_PATTB) Pattern Generator 4 Output Enable Buffer */
+#define TCC_PATTB_PGEB4 (1 << TCC_PATTB_PGEB4_Pos)
+#define TCC_PATTB_PGEB5_Pos 5 /**< \brief (TCC_PATTB) Pattern Generator 5 Output Enable Buffer */
+#define TCC_PATTB_PGEB5 (1 << TCC_PATTB_PGEB5_Pos)
+#define TCC_PATTB_PGEB6_Pos 6 /**< \brief (TCC_PATTB) Pattern Generator 6 Output Enable Buffer */
+#define TCC_PATTB_PGEB6 (1 << TCC_PATTB_PGEB6_Pos)
+#define TCC_PATTB_PGEB7_Pos 7 /**< \brief (TCC_PATTB) Pattern Generator 7 Output Enable Buffer */
+#define TCC_PATTB_PGEB7 (1 << TCC_PATTB_PGEB7_Pos)
+#define TCC_PATTB_PGEB_Pos 0 /**< \brief (TCC_PATTB) Pattern Generator x Output Enable Buffer */
+#define TCC_PATTB_PGEB_Msk (0xFFul << TCC_PATTB_PGEB_Pos)
+#define TCC_PATTB_PGEB(value) (TCC_PATTB_PGEB_Msk & ((value) << TCC_PATTB_PGEB_Pos))
+#define TCC_PATTB_PGVB0_Pos 8 /**< \brief (TCC_PATTB) Pattern Generator 0 Output Enable */
+#define TCC_PATTB_PGVB0 (1 << TCC_PATTB_PGVB0_Pos)
+#define TCC_PATTB_PGVB1_Pos 9 /**< \brief (TCC_PATTB) Pattern Generator 1 Output Enable */
+#define TCC_PATTB_PGVB1 (1 << TCC_PATTB_PGVB1_Pos)
+#define TCC_PATTB_PGVB2_Pos 10 /**< \brief (TCC_PATTB) Pattern Generator 2 Output Enable */
+#define TCC_PATTB_PGVB2 (1 << TCC_PATTB_PGVB2_Pos)
+#define TCC_PATTB_PGVB3_Pos 11 /**< \brief (TCC_PATTB) Pattern Generator 3 Output Enable */
+#define TCC_PATTB_PGVB3 (1 << TCC_PATTB_PGVB3_Pos)
+#define TCC_PATTB_PGVB4_Pos 12 /**< \brief (TCC_PATTB) Pattern Generator 4 Output Enable */
+#define TCC_PATTB_PGVB4 (1 << TCC_PATTB_PGVB4_Pos)
+#define TCC_PATTB_PGVB5_Pos 13 /**< \brief (TCC_PATTB) Pattern Generator 5 Output Enable */
+#define TCC_PATTB_PGVB5 (1 << TCC_PATTB_PGVB5_Pos)
+#define TCC_PATTB_PGVB6_Pos 14 /**< \brief (TCC_PATTB) Pattern Generator 6 Output Enable */
+#define TCC_PATTB_PGVB6 (1 << TCC_PATTB_PGVB6_Pos)
+#define TCC_PATTB_PGVB7_Pos 15 /**< \brief (TCC_PATTB) Pattern Generator 7 Output Enable */
+#define TCC_PATTB_PGVB7 (1 << TCC_PATTB_PGVB7_Pos)
+#define TCC_PATTB_PGVB_Pos 8 /**< \brief (TCC_PATTB) Pattern Generator x Output Enable */
+#define TCC_PATTB_PGVB_Msk (0xFFul << TCC_PATTB_PGVB_Pos)
+#define TCC_PATTB_PGVB(value) (TCC_PATTB_PGVB_Msk & ((value) << TCC_PATTB_PGVB_Pos))
+#define TCC_PATTB_MASK 0xFFFFul /**< \brief (TCC_PATTB) MASK Register */
+
+/* -------- TCC_WAVEB : (TCC Offset: 0x68) (R/W 32) Waveform Control Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t WAVEGENB:3; /*!< bit: 0.. 2 Waveform Generation Buffer */
+ uint32_t :1; /*!< bit: 3 Reserved */
+ uint32_t RAMPB:2; /*!< bit: 4.. 5 Ramp Mode Buffer */
+ uint32_t :1; /*!< bit: 6 Reserved */
+ uint32_t CIPERENB:1; /*!< bit: 7 Circular Period Enable Buffer */
+ uint32_t CICCENB0:1; /*!< bit: 8 Circular Channel 0 Enable Buffer */
+ uint32_t CICCENB1:1; /*!< bit: 9 Circular Channel 1 Enable Buffer */
+ uint32_t CICCENB2:1; /*!< bit: 10 Circular Channel 2 Enable Buffer */
+ uint32_t CICCENB3:1; /*!< bit: 11 Circular Channel 3 Enable Buffer */
+ uint32_t :4; /*!< bit: 12..15 Reserved */
+ uint32_t POLB0:1; /*!< bit: 16 Channel 0 Polarity Buffer */
+ uint32_t POLB1:1; /*!< bit: 17 Channel 1 Polarity Buffer */
+ uint32_t POLB2:1; /*!< bit: 18 Channel 2 Polarity Buffer */
+ uint32_t POLB3:1; /*!< bit: 19 Channel 3 Polarity Buffer */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t SWAPB0:1; /*!< bit: 24 Swap DTI Output Pair 0 Buffer */
+ uint32_t SWAPB1:1; /*!< bit: 25 Swap DTI Output Pair 1 Buffer */
+ uint32_t SWAPB2:1; /*!< bit: 26 Swap DTI Output Pair 2 Buffer */
+ uint32_t SWAPB3:1; /*!< bit: 27 Swap DTI Output Pair 3 Buffer */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint32_t :8; /*!< bit: 0.. 7 Reserved */
+ uint32_t CICCENB:4; /*!< bit: 8..11 Circular Channel x Enable Buffer */
+ uint32_t :4; /*!< bit: 12..15 Reserved */
+ uint32_t POLB:4; /*!< bit: 16..19 Channel x Polarity Buffer */
+ uint32_t :4; /*!< bit: 20..23 Reserved */
+ uint32_t SWAPB:4; /*!< bit: 24..27 Swap DTI Output Pair x Buffer */
+ uint32_t :4; /*!< bit: 28..31 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_WAVEB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_WAVEB_OFFSET 0x68 /**< \brief (TCC_WAVEB offset) Waveform Control Buffer */
+#define TCC_WAVEB_RESETVALUE 0x00000000ul /**< \brief (TCC_WAVEB reset_value) Waveform Control Buffer */
+
+#define TCC_WAVEB_WAVEGENB_Pos 0 /**< \brief (TCC_WAVEB) Waveform Generation Buffer */
+#define TCC_WAVEB_WAVEGENB_Msk (0x7ul << TCC_WAVEB_WAVEGENB_Pos)
+#define TCC_WAVEB_WAVEGENB(value) (TCC_WAVEB_WAVEGENB_Msk & ((value) << TCC_WAVEB_WAVEGENB_Pos))
+#define TCC_WAVEB_WAVEGENB_NFRQ_Val 0x0ul /**< \brief (TCC_WAVEB) Normal frequency */
+#define TCC_WAVEB_WAVEGENB_MFRQ_Val 0x1ul /**< \brief (TCC_WAVEB) Match frequency */
+#define TCC_WAVEB_WAVEGENB_NPWM_Val 0x2ul /**< \brief (TCC_WAVEB) Normal PWM */
+#define TCC_WAVEB_WAVEGENB_DSCRITICAL_Val 0x4ul /**< \brief (TCC_WAVEB) Dual-slope critical */
+#define TCC_WAVEB_WAVEGENB_DSBOTTOM_Val 0x5ul /**< \brief (TCC_WAVEB) Dual-slope with interrupt/event condition when COUNT reaches ZERO */
+#define TCC_WAVEB_WAVEGENB_DSBOTH_Val 0x6ul /**< \brief (TCC_WAVEB) Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP */
+#define TCC_WAVEB_WAVEGENB_DSTOP_Val 0x7ul /**< \brief (TCC_WAVEB) Dual-slope with interrupt/event condition when COUNT reaches TOP */
+#define TCC_WAVEB_WAVEGENB_NFRQ (TCC_WAVEB_WAVEGENB_NFRQ_Val << TCC_WAVEB_WAVEGENB_Pos)
+#define TCC_WAVEB_WAVEGENB_MFRQ (TCC_WAVEB_WAVEGENB_MFRQ_Val << TCC_WAVEB_WAVEGENB_Pos)
+#define TCC_WAVEB_WAVEGENB_NPWM (TCC_WAVEB_WAVEGENB_NPWM_Val << TCC_WAVEB_WAVEGENB_Pos)
+#define TCC_WAVEB_WAVEGENB_DSCRITICAL (TCC_WAVEB_WAVEGENB_DSCRITICAL_Val << TCC_WAVEB_WAVEGENB_Pos)
+#define TCC_WAVEB_WAVEGENB_DSBOTTOM (TCC_WAVEB_WAVEGENB_DSBOTTOM_Val << TCC_WAVEB_WAVEGENB_Pos)
+#define TCC_WAVEB_WAVEGENB_DSBOTH (TCC_WAVEB_WAVEGENB_DSBOTH_Val << TCC_WAVEB_WAVEGENB_Pos)
+#define TCC_WAVEB_WAVEGENB_DSTOP (TCC_WAVEB_WAVEGENB_DSTOP_Val << TCC_WAVEB_WAVEGENB_Pos)
+#define TCC_WAVEB_RAMPB_Pos 4 /**< \brief (TCC_WAVEB) Ramp Mode Buffer */
+#define TCC_WAVEB_RAMPB_Msk (0x3ul << TCC_WAVEB_RAMPB_Pos)
+#define TCC_WAVEB_RAMPB(value) (TCC_WAVEB_RAMPB_Msk & ((value) << TCC_WAVEB_RAMPB_Pos))
+#define TCC_WAVEB_RAMPB_RAMP1_Val 0x0ul /**< \brief (TCC_WAVEB) RAMP1 operation */
+#define TCC_WAVEB_RAMPB_RAMP2A_Val 0x1ul /**< \brief (TCC_WAVEB) Alternative RAMP2 operation */
+#define TCC_WAVEB_RAMPB_RAMP2_Val 0x2ul /**< \brief (TCC_WAVEB) RAMP2 operation */
+#define TCC_WAVEB_RAMPB_RAMP1 (TCC_WAVEB_RAMPB_RAMP1_Val << TCC_WAVEB_RAMPB_Pos)
+#define TCC_WAVEB_RAMPB_RAMP2A (TCC_WAVEB_RAMPB_RAMP2A_Val << TCC_WAVEB_RAMPB_Pos)
+#define TCC_WAVEB_RAMPB_RAMP2 (TCC_WAVEB_RAMPB_RAMP2_Val << TCC_WAVEB_RAMPB_Pos)
+#define TCC_WAVEB_CIPERENB_Pos 7 /**< \brief (TCC_WAVEB) Circular Period Enable Buffer */
+#define TCC_WAVEB_CIPERENB (0x1ul << TCC_WAVEB_CIPERENB_Pos)
+#define TCC_WAVEB_CICCENB0_Pos 8 /**< \brief (TCC_WAVEB) Circular Channel 0 Enable Buffer */
+#define TCC_WAVEB_CICCENB0 (1 << TCC_WAVEB_CICCENB0_Pos)
+#define TCC_WAVEB_CICCENB1_Pos 9 /**< \brief (TCC_WAVEB) Circular Channel 1 Enable Buffer */
+#define TCC_WAVEB_CICCENB1 (1 << TCC_WAVEB_CICCENB1_Pos)
+#define TCC_WAVEB_CICCENB2_Pos 10 /**< \brief (TCC_WAVEB) Circular Channel 2 Enable Buffer */
+#define TCC_WAVEB_CICCENB2 (1 << TCC_WAVEB_CICCENB2_Pos)
+#define TCC_WAVEB_CICCENB3_Pos 11 /**< \brief (TCC_WAVEB) Circular Channel 3 Enable Buffer */
+#define TCC_WAVEB_CICCENB3 (1 << TCC_WAVEB_CICCENB3_Pos)
+#define TCC_WAVEB_CICCENB_Pos 8 /**< \brief (TCC_WAVEB) Circular Channel x Enable Buffer */
+#define TCC_WAVEB_CICCENB_Msk (0xFul << TCC_WAVEB_CICCENB_Pos)
+#define TCC_WAVEB_CICCENB(value) (TCC_WAVEB_CICCENB_Msk & ((value) << TCC_WAVEB_CICCENB_Pos))
+#define TCC_WAVEB_POLB0_Pos 16 /**< \brief (TCC_WAVEB) Channel 0 Polarity Buffer */
+#define TCC_WAVEB_POLB0 (1 << TCC_WAVEB_POLB0_Pos)
+#define TCC_WAVEB_POLB1_Pos 17 /**< \brief (TCC_WAVEB) Channel 1 Polarity Buffer */
+#define TCC_WAVEB_POLB1 (1 << TCC_WAVEB_POLB1_Pos)
+#define TCC_WAVEB_POLB2_Pos 18 /**< \brief (TCC_WAVEB) Channel 2 Polarity Buffer */
+#define TCC_WAVEB_POLB2 (1 << TCC_WAVEB_POLB2_Pos)
+#define TCC_WAVEB_POLB3_Pos 19 /**< \brief (TCC_WAVEB) Channel 3 Polarity Buffer */
+#define TCC_WAVEB_POLB3 (1 << TCC_WAVEB_POLB3_Pos)
+#define TCC_WAVEB_POLB_Pos 16 /**< \brief (TCC_WAVEB) Channel x Polarity Buffer */
+#define TCC_WAVEB_POLB_Msk (0xFul << TCC_WAVEB_POLB_Pos)
+#define TCC_WAVEB_POLB(value) (TCC_WAVEB_POLB_Msk & ((value) << TCC_WAVEB_POLB_Pos))
+#define TCC_WAVEB_SWAPB0_Pos 24 /**< \brief (TCC_WAVEB) Swap DTI Output Pair 0 Buffer */
+#define TCC_WAVEB_SWAPB0 (1 << TCC_WAVEB_SWAPB0_Pos)
+#define TCC_WAVEB_SWAPB1_Pos 25 /**< \brief (TCC_WAVEB) Swap DTI Output Pair 1 Buffer */
+#define TCC_WAVEB_SWAPB1 (1 << TCC_WAVEB_SWAPB1_Pos)
+#define TCC_WAVEB_SWAPB2_Pos 26 /**< \brief (TCC_WAVEB) Swap DTI Output Pair 2 Buffer */
+#define TCC_WAVEB_SWAPB2 (1 << TCC_WAVEB_SWAPB2_Pos)
+#define TCC_WAVEB_SWAPB3_Pos 27 /**< \brief (TCC_WAVEB) Swap DTI Output Pair 3 Buffer */
+#define TCC_WAVEB_SWAPB3 (1 << TCC_WAVEB_SWAPB3_Pos)
+#define TCC_WAVEB_SWAPB_Pos 24 /**< \brief (TCC_WAVEB) Swap DTI Output Pair x Buffer */
+#define TCC_WAVEB_SWAPB_Msk (0xFul << TCC_WAVEB_SWAPB_Pos)
+#define TCC_WAVEB_SWAPB(value) (TCC_WAVEB_SWAPB_Msk & ((value) << TCC_WAVEB_SWAPB_Pos))
+#define TCC_WAVEB_MASK 0x0F0F0FB7ul /**< \brief (TCC_WAVEB) MASK Register */
+
+/* -------- TCC_PERB : (TCC Offset: 0x6C) (R/W 32) Period Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct { // DITH4 mode
+ uint32_t DITHERCYB:4; /*!< bit: 0.. 3 Dithering Buffer Cycle Number */
+ uint32_t PERB:20; /*!< bit: 4..23 Period Buffer Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH4; /*!< Structure used for DITH4 */
+ struct { // DITH5 mode
+ uint32_t DITHERCYB:5; /*!< bit: 0.. 4 Dithering Buffer Cycle Number */
+ uint32_t PERB:19; /*!< bit: 5..23 Period Buffer Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH5; /*!< Structure used for DITH5 */
+ struct { // DITH6 mode
+ uint32_t DITHERCYB:6; /*!< bit: 0.. 5 Dithering Buffer Cycle Number */
+ uint32_t PERB:18; /*!< bit: 6..23 Period Buffer Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH6; /*!< Structure used for DITH6 */
+ struct {
+ uint32_t PERB:24; /*!< bit: 0..23 Period Buffer Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_PERB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_PERB_OFFSET 0x6C /**< \brief (TCC_PERB offset) Period Buffer */
+#define TCC_PERB_RESETVALUE 0xFFFFFFFFul /**< \brief (TCC_PERB reset_value) Period Buffer */
+
+// DITH4 mode
+#define TCC_PERB_DITH4_DITHERCYB_Pos 0 /**< \brief (TCC_PERB_DITH4) Dithering Buffer Cycle Number */
+#define TCC_PERB_DITH4_DITHERCYB_Msk (0xFul << TCC_PERB_DITH4_DITHERCYB_Pos)
+#define TCC_PERB_DITH4_DITHERCYB(value) (TCC_PERB_DITH4_DITHERCYB_Msk & ((value) << TCC_PERB_DITH4_DITHERCYB_Pos))
+#define TCC_PERB_DITH4_PERB_Pos 4 /**< \brief (TCC_PERB_DITH4) Period Buffer Value */
+#define TCC_PERB_DITH4_PERB_Msk (0xFFFFFul << TCC_PERB_DITH4_PERB_Pos)
+#define TCC_PERB_DITH4_PERB(value) (TCC_PERB_DITH4_PERB_Msk & ((value) << TCC_PERB_DITH4_PERB_Pos))
+#define TCC_PERB_DITH4_MASK 0x00FFFFFFul /**< \brief (TCC_PERB_DITH4) MASK Register */
+
+// DITH5 mode
+#define TCC_PERB_DITH5_DITHERCYB_Pos 0 /**< \brief (TCC_PERB_DITH5) Dithering Buffer Cycle Number */
+#define TCC_PERB_DITH5_DITHERCYB_Msk (0x1Ful << TCC_PERB_DITH5_DITHERCYB_Pos)
+#define TCC_PERB_DITH5_DITHERCYB(value) (TCC_PERB_DITH5_DITHERCYB_Msk & ((value) << TCC_PERB_DITH5_DITHERCYB_Pos))
+#define TCC_PERB_DITH5_PERB_Pos 5 /**< \brief (TCC_PERB_DITH5) Period Buffer Value */
+#define TCC_PERB_DITH5_PERB_Msk (0x7FFFFul << TCC_PERB_DITH5_PERB_Pos)
+#define TCC_PERB_DITH5_PERB(value) (TCC_PERB_DITH5_PERB_Msk & ((value) << TCC_PERB_DITH5_PERB_Pos))
+#define TCC_PERB_DITH5_MASK 0x00FFFFFFul /**< \brief (TCC_PERB_DITH5) MASK Register */
+
+// DITH6 mode
+#define TCC_PERB_DITH6_DITHERCYB_Pos 0 /**< \brief (TCC_PERB_DITH6) Dithering Buffer Cycle Number */
+#define TCC_PERB_DITH6_DITHERCYB_Msk (0x3Ful << TCC_PERB_DITH6_DITHERCYB_Pos)
+#define TCC_PERB_DITH6_DITHERCYB(value) (TCC_PERB_DITH6_DITHERCYB_Msk & ((value) << TCC_PERB_DITH6_DITHERCYB_Pos))
+#define TCC_PERB_DITH6_PERB_Pos 6 /**< \brief (TCC_PERB_DITH6) Period Buffer Value */
+#define TCC_PERB_DITH6_PERB_Msk (0x3FFFFul << TCC_PERB_DITH6_PERB_Pos)
+#define TCC_PERB_DITH6_PERB(value) (TCC_PERB_DITH6_PERB_Msk & ((value) << TCC_PERB_DITH6_PERB_Pos))
+#define TCC_PERB_DITH6_MASK 0x00FFFFFFul /**< \brief (TCC_PERB_DITH6) MASK Register */
+
+#define TCC_PERB_PERB_Pos 0 /**< \brief (TCC_PERB) Period Buffer Value */
+#define TCC_PERB_PERB_Msk (0xFFFFFFul << TCC_PERB_PERB_Pos)
+#define TCC_PERB_PERB(value) (TCC_PERB_PERB_Msk & ((value) << TCC_PERB_PERB_Pos))
+#define TCC_PERB_MASK 0x00FFFFFFul /**< \brief (TCC_PERB) MASK Register */
+
+/* -------- TCC_CCB : (TCC Offset: 0x70) (R/W 32) Compare and Capture Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct { // DITH4 mode
+ uint32_t DITHERCYB:4; /*!< bit: 0.. 3 Dithering Buffer Cycle Number */
+ uint32_t CCB:20; /*!< bit: 4..23 Channel Compare/Capture Buffer Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH4; /*!< Structure used for DITH4 */
+ struct { // DITH5 mode
+ uint32_t DITHERCYB:5; /*!< bit: 0.. 4 Dithering Buffer Cycle Number */
+ uint32_t CCB:19; /*!< bit: 5..23 Channel Compare/Capture Buffer Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH5; /*!< Structure used for DITH5 */
+ struct { // DITH6 mode
+ uint32_t DITHERCYB:6; /*!< bit: 0.. 5 Dithering Buffer Cycle Number */
+ uint32_t CCB:18; /*!< bit: 6..23 Channel Compare/Capture Buffer Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } DITH6; /*!< Structure used for DITH6 */
+ struct {
+ uint32_t CCB:24; /*!< bit: 0..23 Channel Compare/Capture Buffer Value */
+ uint32_t :8; /*!< bit: 24..31 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} TCC_CCB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define TCC_CCB_OFFSET 0x70 /**< \brief (TCC_CCB offset) Compare and Capture Buffer */
+#define TCC_CCB_RESETVALUE 0x00000000ul /**< \brief (TCC_CCB reset_value) Compare and Capture Buffer */
+
+// DITH4 mode
+#define TCC_CCB_DITH4_DITHERCYB_Pos 0 /**< \brief (TCC_CCB_DITH4) Dithering Buffer Cycle Number */
+#define TCC_CCB_DITH4_DITHERCYB_Msk (0xFul << TCC_CCB_DITH4_DITHERCYB_Pos)
+#define TCC_CCB_DITH4_DITHERCYB(value) (TCC_CCB_DITH4_DITHERCYB_Msk & ((value) << TCC_CCB_DITH4_DITHERCYB_Pos))
+#define TCC_CCB_DITH4_CCB_Pos 4 /**< \brief (TCC_CCB_DITH4) Channel Compare/Capture Buffer Value */
+#define TCC_CCB_DITH4_CCB_Msk (0xFFFFFul << TCC_CCB_DITH4_CCB_Pos)
+#define TCC_CCB_DITH4_CCB(value) (TCC_CCB_DITH4_CCB_Msk & ((value) << TCC_CCB_DITH4_CCB_Pos))
+#define TCC_CCB_DITH4_MASK 0x00FFFFFFul /**< \brief (TCC_CCB_DITH4) MASK Register */
+
+// DITH5 mode
+#define TCC_CCB_DITH5_DITHERCYB_Pos 0 /**< \brief (TCC_CCB_DITH5) Dithering Buffer Cycle Number */
+#define TCC_CCB_DITH5_DITHERCYB_Msk (0x1Ful << TCC_CCB_DITH5_DITHERCYB_Pos)
+#define TCC_CCB_DITH5_DITHERCYB(value) (TCC_CCB_DITH5_DITHERCYB_Msk & ((value) << TCC_CCB_DITH5_DITHERCYB_Pos))
+#define TCC_CCB_DITH5_CCB_Pos 5 /**< \brief (TCC_CCB_DITH5) Channel Compare/Capture Buffer Value */
+#define TCC_CCB_DITH5_CCB_Msk (0x7FFFFul << TCC_CCB_DITH5_CCB_Pos)
+#define TCC_CCB_DITH5_CCB(value) (TCC_CCB_DITH5_CCB_Msk & ((value) << TCC_CCB_DITH5_CCB_Pos))
+#define TCC_CCB_DITH5_MASK 0x00FFFFFFul /**< \brief (TCC_CCB_DITH5) MASK Register */
+
+// DITH6 mode
+#define TCC_CCB_DITH6_DITHERCYB_Pos 0 /**< \brief (TCC_CCB_DITH6) Dithering Buffer Cycle Number */
+#define TCC_CCB_DITH6_DITHERCYB_Msk (0x3Ful << TCC_CCB_DITH6_DITHERCYB_Pos)
+#define TCC_CCB_DITH6_DITHERCYB(value) (TCC_CCB_DITH6_DITHERCYB_Msk & ((value) << TCC_CCB_DITH6_DITHERCYB_Pos))
+#define TCC_CCB_DITH6_CCB_Pos 6 /**< \brief (TCC_CCB_DITH6) Channel Compare/Capture Buffer Value */
+#define TCC_CCB_DITH6_CCB_Msk (0x3FFFFul << TCC_CCB_DITH6_CCB_Pos)
+#define TCC_CCB_DITH6_CCB(value) (TCC_CCB_DITH6_CCB_Msk & ((value) << TCC_CCB_DITH6_CCB_Pos))
+#define TCC_CCB_DITH6_MASK 0x00FFFFFFul /**< \brief (TCC_CCB_DITH6) MASK Register */
+
+#define TCC_CCB_CCB_Pos 0 /**< \brief (TCC_CCB) Channel Compare/Capture Buffer Value */
+#define TCC_CCB_CCB_Msk (0xFFFFFFul << TCC_CCB_CCB_Pos)
+#define TCC_CCB_CCB(value) (TCC_CCB_CCB_Msk & ((value) << TCC_CCB_CCB_Pos))
+#define TCC_CCB_MASK 0x00FFFFFFul /**< \brief (TCC_CCB) MASK Register */
+
+/** \brief TCC hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO TCC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */
+ __IO TCC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
+ __IO TCC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
+ RoReg8 Reserved1[0x2];
+ __I TCC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x08 (R/ 32) Synchronization Busy */
+ __IO TCC_FCTRLA_Type FCTRLA; /**< \brief Offset: 0x0C (R/W 32) Recoverable Fault A Configuration */
+ __IO TCC_FCTRLB_Type FCTRLB; /**< \brief Offset: 0x10 (R/W 32) Recoverable Fault B Configuration */
+ __IO TCC_WEXCTRL_Type WEXCTRL; /**< \brief Offset: 0x14 (R/W 32) Waveform Extension Configuration */
+ __IO TCC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x18 (R/W 32) Driver Control */
+ RoReg8 Reserved2[0x2];
+ __IO TCC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x1E (R/W 8) Debug Control */
+ RoReg8 Reserved3[0x1];
+ __IO TCC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x20 (R/W 32) Event Control */
+ __IO TCC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x24 (R/W 32) Interrupt Enable Clear */
+ __IO TCC_INTENSET_Type INTENSET; /**< \brief Offset: 0x28 (R/W 32) Interrupt Enable Set */
+ __IO TCC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x2C (R/W 32) Interrupt Flag Status and Clear */
+ __IO TCC_STATUS_Type STATUS; /**< \brief Offset: 0x30 (R/W 32) Status */
+ __IO TCC_COUNT_Type COUNT; /**< \brief Offset: 0x34 (R/W 32) Count */
+ __IO TCC_PATT_Type PATT; /**< \brief Offset: 0x38 (R/W 16) Pattern */
+ RoReg8 Reserved4[0x2];
+ __IO TCC_WAVE_Type WAVE; /**< \brief Offset: 0x3C (R/W 32) Waveform Control */
+ __IO TCC_PER_Type PER; /**< \brief Offset: 0x40 (R/W 32) Period */
+ __IO TCC_CC_Type CC[4]; /**< \brief Offset: 0x44 (R/W 32) Compare and Capture */
+ RoReg8 Reserved5[0x10];
+ __IO TCC_PATTB_Type PATTB; /**< \brief Offset: 0x64 (R/W 16) Pattern Buffer */
+ RoReg8 Reserved6[0x2];
+ __IO TCC_WAVEB_Type WAVEB; /**< \brief Offset: 0x68 (R/W 32) Waveform Control Buffer */
+ __IO TCC_PERB_Type PERB; /**< \brief Offset: 0x6C (R/W 32) Period Buffer */
+ __IO TCC_CCB_Type CCB[4]; /**< \brief Offset: 0x70 (R/W 32) Compare and Capture Buffer */
+} Tcc;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_TCC_COMPONENT_ */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/component/usb.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/component/usb.h
new file mode 100644
index 0000000000000000000000000000000000000000..babfcc22cb5dee2333e53ae60919c15d4c80c4cd
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/component/usb.h
@@ -0,0 +1,1805 @@
+/**
+ * \file
+ *
+ * \brief Component description for USB
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_USB_COMPONENT_
+#define _SAMD21_USB_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR USB */
+/* ========================================================================== */
+/** \addtogroup SAMD21_USB Universal Serial Bus */
+/*@{*/
+
+#define USB_U2222
+#define REV_USB 0x101
+
+/* -------- USB_CTRLA : (USB Offset: 0x000) (R/W 8) Control A -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset */
+ uint8_t ENABLE:1; /*!< bit: 1 Enable */
+ uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby Mode */
+ uint8_t :4; /*!< bit: 3.. 6 Reserved */
+ uint8_t MODE:1; /*!< bit: 7 Operating Mode */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_CTRLA_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_CTRLA_OFFSET 0x000 /**< \brief (USB_CTRLA offset) Control A */
+#define USB_CTRLA_RESETVALUE 0x00ul /**< \brief (USB_CTRLA reset_value) Control A */
+
+#define USB_CTRLA_SWRST_Pos 0 /**< \brief (USB_CTRLA) Software Reset */
+#define USB_CTRLA_SWRST (0x1ul << USB_CTRLA_SWRST_Pos)
+#define USB_CTRLA_ENABLE_Pos 1 /**< \brief (USB_CTRLA) Enable */
+#define USB_CTRLA_ENABLE (0x1ul << USB_CTRLA_ENABLE_Pos)
+#define USB_CTRLA_RUNSTDBY_Pos 2 /**< \brief (USB_CTRLA) Run in Standby Mode */
+#define USB_CTRLA_RUNSTDBY (0x1ul << USB_CTRLA_RUNSTDBY_Pos)
+#define USB_CTRLA_MODE_Pos 7 /**< \brief (USB_CTRLA) Operating Mode */
+#define USB_CTRLA_MODE (0x1ul << USB_CTRLA_MODE_Pos)
+#define USB_CTRLA_MODE_DEVICE_Val 0x0ul /**< \brief (USB_CTRLA) Device Mode */
+#define USB_CTRLA_MODE_HOST_Val 0x1ul /**< \brief (USB_CTRLA) Host Mode */
+#define USB_CTRLA_MODE_DEVICE (USB_CTRLA_MODE_DEVICE_Val << USB_CTRLA_MODE_Pos)
+#define USB_CTRLA_MODE_HOST (USB_CTRLA_MODE_HOST_Val << USB_CTRLA_MODE_Pos)
+#define USB_CTRLA_MASK 0x87ul /**< \brief (USB_CTRLA) MASK Register */
+
+/* -------- USB_SYNCBUSY : (USB Offset: 0x002) (R/ 8) Synchronization Busy -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
+ uint8_t ENABLE:1; /*!< bit: 1 Enable Synchronization Busy */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_SYNCBUSY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_SYNCBUSY_OFFSET 0x002 /**< \brief (USB_SYNCBUSY offset) Synchronization Busy */
+#define USB_SYNCBUSY_RESETVALUE 0x00ul /**< \brief (USB_SYNCBUSY reset_value) Synchronization Busy */
+
+#define USB_SYNCBUSY_SWRST_Pos 0 /**< \brief (USB_SYNCBUSY) Software Reset Synchronization Busy */
+#define USB_SYNCBUSY_SWRST (0x1ul << USB_SYNCBUSY_SWRST_Pos)
+#define USB_SYNCBUSY_ENABLE_Pos 1 /**< \brief (USB_SYNCBUSY) Enable Synchronization Busy */
+#define USB_SYNCBUSY_ENABLE (0x1ul << USB_SYNCBUSY_ENABLE_Pos)
+#define USB_SYNCBUSY_MASK 0x03ul /**< \brief (USB_SYNCBUSY) MASK Register */
+
+/* -------- USB_QOSCTRL : (USB Offset: 0x003) (R/W 8) USB Quality Of Service -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t CQOS:2; /*!< bit: 0.. 1 Configuration Quality of Service */
+ uint8_t DQOS:2; /*!< bit: 2.. 3 Data Quality of Service */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_QOSCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_QOSCTRL_OFFSET 0x003 /**< \brief (USB_QOSCTRL offset) USB Quality Of Service */
+#define USB_QOSCTRL_RESETVALUE 0x05ul /**< \brief (USB_QOSCTRL reset_value) USB Quality Of Service */
+
+#define USB_QOSCTRL_CQOS_Pos 0 /**< \brief (USB_QOSCTRL) Configuration Quality of Service */
+#define USB_QOSCTRL_CQOS_Msk (0x3ul << USB_QOSCTRL_CQOS_Pos)
+#define USB_QOSCTRL_CQOS(value) (USB_QOSCTRL_CQOS_Msk & ((value) << USB_QOSCTRL_CQOS_Pos))
+#define USB_QOSCTRL_CQOS_DISABLE_Val 0x0ul /**< \brief (USB_QOSCTRL) Background (no sensitive operation) */
+#define USB_QOSCTRL_CQOS_LOW_Val 0x1ul /**< \brief (USB_QOSCTRL) Sensitive Bandwidth */
+#define USB_QOSCTRL_CQOS_MEDIUM_Val 0x2ul /**< \brief (USB_QOSCTRL) Sensitive Latency */
+#define USB_QOSCTRL_CQOS_HIGH_Val 0x3ul /**< \brief (USB_QOSCTRL) Critical Latency */
+#define USB_QOSCTRL_CQOS_DISABLE (USB_QOSCTRL_CQOS_DISABLE_Val << USB_QOSCTRL_CQOS_Pos)
+#define USB_QOSCTRL_CQOS_LOW (USB_QOSCTRL_CQOS_LOW_Val << USB_QOSCTRL_CQOS_Pos)
+#define USB_QOSCTRL_CQOS_MEDIUM (USB_QOSCTRL_CQOS_MEDIUM_Val << USB_QOSCTRL_CQOS_Pos)
+#define USB_QOSCTRL_CQOS_HIGH (USB_QOSCTRL_CQOS_HIGH_Val << USB_QOSCTRL_CQOS_Pos)
+#define USB_QOSCTRL_DQOS_Pos 2 /**< \brief (USB_QOSCTRL) Data Quality of Service */
+#define USB_QOSCTRL_DQOS_Msk (0x3ul << USB_QOSCTRL_DQOS_Pos)
+#define USB_QOSCTRL_DQOS(value) (USB_QOSCTRL_DQOS_Msk & ((value) << USB_QOSCTRL_DQOS_Pos))
+#define USB_QOSCTRL_DQOS_DISABLE_Val 0x0ul /**< \brief (USB_QOSCTRL) Background (no sensitive operation) */
+#define USB_QOSCTRL_DQOS_LOW_Val 0x1ul /**< \brief (USB_QOSCTRL) Sensitive Bandwidth */
+#define USB_QOSCTRL_DQOS_MEDIUM_Val 0x2ul /**< \brief (USB_QOSCTRL) Sensitive Latency */
+#define USB_QOSCTRL_DQOS_HIGH_Val 0x3ul /**< \brief (USB_QOSCTRL) Critical Latency */
+#define USB_QOSCTRL_DQOS_DISABLE (USB_QOSCTRL_DQOS_DISABLE_Val << USB_QOSCTRL_DQOS_Pos)
+#define USB_QOSCTRL_DQOS_LOW (USB_QOSCTRL_DQOS_LOW_Val << USB_QOSCTRL_DQOS_Pos)
+#define USB_QOSCTRL_DQOS_MEDIUM (USB_QOSCTRL_DQOS_MEDIUM_Val << USB_QOSCTRL_DQOS_Pos)
+#define USB_QOSCTRL_DQOS_HIGH (USB_QOSCTRL_DQOS_HIGH_Val << USB_QOSCTRL_DQOS_Pos)
+#define USB_QOSCTRL_MASK 0x0Ful /**< \brief (USB_QOSCTRL) MASK Register */
+
+/* -------- USB_DEVICE_CTRLB : (USB Offset: 0x008) (R/W 16) DEVICE DEVICE Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t DETACH:1; /*!< bit: 0 Detach */
+ uint16_t UPRSM:1; /*!< bit: 1 Upstream Resume */
+ uint16_t SPDCONF:2; /*!< bit: 2.. 3 Speed Configuration */
+ uint16_t NREPLY:1; /*!< bit: 4 No Reply */
+ uint16_t TSTJ:1; /*!< bit: 5 Test mode J */
+ uint16_t TSTK:1; /*!< bit: 6 Test mode K */
+ uint16_t TSTPCKT:1; /*!< bit: 7 Test packet mode */
+ uint16_t OPMODE2:1; /*!< bit: 8 Specific Operational Mode */
+ uint16_t GNAK:1; /*!< bit: 9 Global NAK */
+ uint16_t LPMHDSK:2; /*!< bit: 10..11 Link Power Management Handshake */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_DEVICE_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_CTRLB_OFFSET 0x008 /**< \brief (USB_DEVICE_CTRLB offset) DEVICE Control B */
+#define USB_DEVICE_CTRLB_RESETVALUE 0x0001ul /**< \brief (USB_DEVICE_CTRLB reset_value) DEVICE Control B */
+
+#define USB_DEVICE_CTRLB_DETACH_Pos 0 /**< \brief (USB_DEVICE_CTRLB) Detach */
+#define USB_DEVICE_CTRLB_DETACH (0x1ul << USB_DEVICE_CTRLB_DETACH_Pos)
+#define USB_DEVICE_CTRLB_UPRSM_Pos 1 /**< \brief (USB_DEVICE_CTRLB) Upstream Resume */
+#define USB_DEVICE_CTRLB_UPRSM (0x1ul << USB_DEVICE_CTRLB_UPRSM_Pos)
+#define USB_DEVICE_CTRLB_SPDCONF_Pos 2 /**< \brief (USB_DEVICE_CTRLB) Speed Configuration */
+#define USB_DEVICE_CTRLB_SPDCONF_Msk (0x3ul << USB_DEVICE_CTRLB_SPDCONF_Pos)
+#define USB_DEVICE_CTRLB_SPDCONF(value) (USB_DEVICE_CTRLB_SPDCONF_Msk & ((value) << USB_DEVICE_CTRLB_SPDCONF_Pos))
+#define USB_DEVICE_CTRLB_SPDCONF_FS_Val 0x0ul /**< \brief (USB_DEVICE_CTRLB) FS : Full Speed */
+#define USB_DEVICE_CTRLB_SPDCONF_LS_Val 0x1ul /**< \brief (USB_DEVICE_CTRLB) LS : Low Speed */
+#define USB_DEVICE_CTRLB_SPDCONF_HS_Val 0x2ul /**< \brief (USB_DEVICE_CTRLB) HS : High Speed capable */
+#define USB_DEVICE_CTRLB_SPDCONF_HSTM_Val 0x3ul /**< \brief (USB_DEVICE_CTRLB) HSTM: High Speed Test Mode (force high-speed mode for test mode) */
+#define USB_DEVICE_CTRLB_SPDCONF_FS (USB_DEVICE_CTRLB_SPDCONF_FS_Val << USB_DEVICE_CTRLB_SPDCONF_Pos)
+#define USB_DEVICE_CTRLB_SPDCONF_LS (USB_DEVICE_CTRLB_SPDCONF_LS_Val << USB_DEVICE_CTRLB_SPDCONF_Pos)
+#define USB_DEVICE_CTRLB_SPDCONF_HS (USB_DEVICE_CTRLB_SPDCONF_HS_Val << USB_DEVICE_CTRLB_SPDCONF_Pos)
+#define USB_DEVICE_CTRLB_SPDCONF_HSTM (USB_DEVICE_CTRLB_SPDCONF_HSTM_Val << USB_DEVICE_CTRLB_SPDCONF_Pos)
+#define USB_DEVICE_CTRLB_NREPLY_Pos 4 /**< \brief (USB_DEVICE_CTRLB) No Reply */
+#define USB_DEVICE_CTRLB_NREPLY (0x1ul << USB_DEVICE_CTRLB_NREPLY_Pos)
+#define USB_DEVICE_CTRLB_TSTJ_Pos 5 /**< \brief (USB_DEVICE_CTRLB) Test mode J */
+#define USB_DEVICE_CTRLB_TSTJ (0x1ul << USB_DEVICE_CTRLB_TSTJ_Pos)
+#define USB_DEVICE_CTRLB_TSTK_Pos 6 /**< \brief (USB_DEVICE_CTRLB) Test mode K */
+#define USB_DEVICE_CTRLB_TSTK (0x1ul << USB_DEVICE_CTRLB_TSTK_Pos)
+#define USB_DEVICE_CTRLB_TSTPCKT_Pos 7 /**< \brief (USB_DEVICE_CTRLB) Test packet mode */
+#define USB_DEVICE_CTRLB_TSTPCKT (0x1ul << USB_DEVICE_CTRLB_TSTPCKT_Pos)
+#define USB_DEVICE_CTRLB_OPMODE2_Pos 8 /**< \brief (USB_DEVICE_CTRLB) Specific Operational Mode */
+#define USB_DEVICE_CTRLB_OPMODE2 (0x1ul << USB_DEVICE_CTRLB_OPMODE2_Pos)
+#define USB_DEVICE_CTRLB_GNAK_Pos 9 /**< \brief (USB_DEVICE_CTRLB) Global NAK */
+#define USB_DEVICE_CTRLB_GNAK (0x1ul << USB_DEVICE_CTRLB_GNAK_Pos)
+#define USB_DEVICE_CTRLB_LPMHDSK_Pos 10 /**< \brief (USB_DEVICE_CTRLB) Link Power Management Handshake */
+#define USB_DEVICE_CTRLB_LPMHDSK_Msk (0x3ul << USB_DEVICE_CTRLB_LPMHDSK_Pos)
+#define USB_DEVICE_CTRLB_LPMHDSK(value) (USB_DEVICE_CTRLB_LPMHDSK_Msk & ((value) << USB_DEVICE_CTRLB_LPMHDSK_Pos))
+#define USB_DEVICE_CTRLB_LPMHDSK_NO_Val 0x0ul /**< \brief (USB_DEVICE_CTRLB) No handshake. LPM is not supported */
+#define USB_DEVICE_CTRLB_LPMHDSK_ACK_Val 0x1ul /**< \brief (USB_DEVICE_CTRLB) ACK */
+#define USB_DEVICE_CTRLB_LPMHDSK_NYET_Val 0x2ul /**< \brief (USB_DEVICE_CTRLB) NYET */
+#define USB_DEVICE_CTRLB_LPMHDSK_STALL_Val 0x3ul /**< \brief (USB_DEVICE_CTRLB) STALL */
+#define USB_DEVICE_CTRLB_LPMHDSK_NO (USB_DEVICE_CTRLB_LPMHDSK_NO_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos)
+#define USB_DEVICE_CTRLB_LPMHDSK_ACK (USB_DEVICE_CTRLB_LPMHDSK_ACK_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos)
+#define USB_DEVICE_CTRLB_LPMHDSK_NYET (USB_DEVICE_CTRLB_LPMHDSK_NYET_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos)
+#define USB_DEVICE_CTRLB_LPMHDSK_STALL (USB_DEVICE_CTRLB_LPMHDSK_STALL_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos)
+#define USB_DEVICE_CTRLB_MASK 0x0FFFul /**< \brief (USB_DEVICE_CTRLB) MASK Register */
+
+/* -------- USB_HOST_CTRLB : (USB Offset: 0x008) (R/W 16) HOST HOST Control B -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t :1; /*!< bit: 0 Reserved */
+ uint16_t RESUME:1; /*!< bit: 1 Send USB Resume */
+ uint16_t SPDCONF:2; /*!< bit: 2.. 3 Speed Configuration for Host */
+ uint16_t :1; /*!< bit: 4 Reserved */
+ uint16_t TSTJ:1; /*!< bit: 5 Test mode J */
+ uint16_t TSTK:1; /*!< bit: 6 Test mode K */
+ uint16_t :1; /*!< bit: 7 Reserved */
+ uint16_t SOFE:1; /*!< bit: 8 Start of Frame Generation Enable */
+ uint16_t BUSRESET:1; /*!< bit: 9 Send USB Reset */
+ uint16_t VBUSOK:1; /*!< bit: 10 VBUS is OK */
+ uint16_t L1RESUME:1; /*!< bit: 11 Send L1 Resume */
+ uint16_t :4; /*!< bit: 12..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_HOST_CTRLB_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_CTRLB_OFFSET 0x008 /**< \brief (USB_HOST_CTRLB offset) HOST Control B */
+#define USB_HOST_CTRLB_RESETVALUE 0x0000ul /**< \brief (USB_HOST_CTRLB reset_value) HOST Control B */
+
+#define USB_HOST_CTRLB_RESUME_Pos 1 /**< \brief (USB_HOST_CTRLB) Send USB Resume */
+#define USB_HOST_CTRLB_RESUME (0x1ul << USB_HOST_CTRLB_RESUME_Pos)
+#define USB_HOST_CTRLB_SPDCONF_Pos 2 /**< \brief (USB_HOST_CTRLB) Speed Configuration for Host */
+#define USB_HOST_CTRLB_SPDCONF_Msk (0x3ul << USB_HOST_CTRLB_SPDCONF_Pos)
+#define USB_HOST_CTRLB_SPDCONF(value) (USB_HOST_CTRLB_SPDCONF_Msk & ((value) << USB_HOST_CTRLB_SPDCONF_Pos))
+#define USB_HOST_CTRLB_SPDCONF_NORMAL_Val 0x0ul /**< \brief (USB_HOST_CTRLB) Normal mode:the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable. */
+#define USB_HOST_CTRLB_SPDCONF_FS_Val 0x3ul /**< \brief (USB_HOST_CTRLB) Full-speed:the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only. */
+#define USB_HOST_CTRLB_SPDCONF_NORMAL (USB_HOST_CTRLB_SPDCONF_NORMAL_Val << USB_HOST_CTRLB_SPDCONF_Pos)
+#define USB_HOST_CTRLB_SPDCONF_FS (USB_HOST_CTRLB_SPDCONF_FS_Val << USB_HOST_CTRLB_SPDCONF_Pos)
+#define USB_HOST_CTRLB_TSTJ_Pos 5 /**< \brief (USB_HOST_CTRLB) Test mode J */
+#define USB_HOST_CTRLB_TSTJ (0x1ul << USB_HOST_CTRLB_TSTJ_Pos)
+#define USB_HOST_CTRLB_TSTK_Pos 6 /**< \brief (USB_HOST_CTRLB) Test mode K */
+#define USB_HOST_CTRLB_TSTK (0x1ul << USB_HOST_CTRLB_TSTK_Pos)
+#define USB_HOST_CTRLB_SOFE_Pos 8 /**< \brief (USB_HOST_CTRLB) Start of Frame Generation Enable */
+#define USB_HOST_CTRLB_SOFE (0x1ul << USB_HOST_CTRLB_SOFE_Pos)
+#define USB_HOST_CTRLB_BUSRESET_Pos 9 /**< \brief (USB_HOST_CTRLB) Send USB Reset */
+#define USB_HOST_CTRLB_BUSRESET (0x1ul << USB_HOST_CTRLB_BUSRESET_Pos)
+#define USB_HOST_CTRLB_VBUSOK_Pos 10 /**< \brief (USB_HOST_CTRLB) VBUS is OK */
+#define USB_HOST_CTRLB_VBUSOK (0x1ul << USB_HOST_CTRLB_VBUSOK_Pos)
+#define USB_HOST_CTRLB_L1RESUME_Pos 11 /**< \brief (USB_HOST_CTRLB) Send L1 Resume */
+#define USB_HOST_CTRLB_L1RESUME (0x1ul << USB_HOST_CTRLB_L1RESUME_Pos)
+#define USB_HOST_CTRLB_MASK 0x0F6Eul /**< \brief (USB_HOST_CTRLB) MASK Register */
+
+/* -------- USB_DEVICE_DADD : (USB Offset: 0x00A) (R/W 8) DEVICE DEVICE Device Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DADD:7; /*!< bit: 0.. 6 Device Address */
+ uint8_t ADDEN:1; /*!< bit: 7 Device Address Enable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_DEVICE_DADD_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_DADD_OFFSET 0x00A /**< \brief (USB_DEVICE_DADD offset) DEVICE Device Address */
+#define USB_DEVICE_DADD_RESETVALUE 0x00ul /**< \brief (USB_DEVICE_DADD reset_value) DEVICE Device Address */
+
+#define USB_DEVICE_DADD_DADD_Pos 0 /**< \brief (USB_DEVICE_DADD) Device Address */
+#define USB_DEVICE_DADD_DADD_Msk (0x7Ful << USB_DEVICE_DADD_DADD_Pos)
+#define USB_DEVICE_DADD_DADD(value) (USB_DEVICE_DADD_DADD_Msk & ((value) << USB_DEVICE_DADD_DADD_Pos))
+#define USB_DEVICE_DADD_ADDEN_Pos 7 /**< \brief (USB_DEVICE_DADD) Device Address Enable */
+#define USB_DEVICE_DADD_ADDEN (0x1ul << USB_DEVICE_DADD_ADDEN_Pos)
+#define USB_DEVICE_DADD_MASK 0xFFul /**< \brief (USB_DEVICE_DADD) MASK Register */
+
+/* -------- USB_HOST_HSOFC : (USB Offset: 0x00A) (R/W 8) HOST HOST Host Start Of Frame Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t FLENC:4; /*!< bit: 0.. 3 Frame Length Control */
+ uint8_t :3; /*!< bit: 4.. 6 Reserved */
+ uint8_t FLENCE:1; /*!< bit: 7 Frame Length Control Enable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_HOST_HSOFC_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_HSOFC_OFFSET 0x00A /**< \brief (USB_HOST_HSOFC offset) HOST Host Start Of Frame Control */
+#define USB_HOST_HSOFC_RESETVALUE 0x00ul /**< \brief (USB_HOST_HSOFC reset_value) HOST Host Start Of Frame Control */
+
+#define USB_HOST_HSOFC_FLENC_Pos 0 /**< \brief (USB_HOST_HSOFC) Frame Length Control */
+#define USB_HOST_HSOFC_FLENC_Msk (0xFul << USB_HOST_HSOFC_FLENC_Pos)
+#define USB_HOST_HSOFC_FLENC(value) (USB_HOST_HSOFC_FLENC_Msk & ((value) << USB_HOST_HSOFC_FLENC_Pos))
+#define USB_HOST_HSOFC_FLENCE_Pos 7 /**< \brief (USB_HOST_HSOFC) Frame Length Control Enable */
+#define USB_HOST_HSOFC_FLENCE (0x1ul << USB_HOST_HSOFC_FLENCE_Pos)
+#define USB_HOST_HSOFC_MASK 0x8Ful /**< \brief (USB_HOST_HSOFC) MASK Register */
+
+/* -------- USB_DEVICE_STATUS : (USB Offset: 0x00C) (R/ 8) DEVICE DEVICE Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t :2; /*!< bit: 0.. 1 Reserved */
+ uint8_t SPEED:2; /*!< bit: 2.. 3 Speed Status */
+ uint8_t :2; /*!< bit: 4.. 5 Reserved */
+ uint8_t LINESTATE:2; /*!< bit: 6.. 7 USB Line State Status */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_DEVICE_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_STATUS_OFFSET 0x00C /**< \brief (USB_DEVICE_STATUS offset) DEVICE Status */
+#define USB_DEVICE_STATUS_RESETVALUE 0x40ul /**< \brief (USB_DEVICE_STATUS reset_value) DEVICE Status */
+
+#define USB_DEVICE_STATUS_SPEED_Pos 2 /**< \brief (USB_DEVICE_STATUS) Speed Status */
+#define USB_DEVICE_STATUS_SPEED_Msk (0x3ul << USB_DEVICE_STATUS_SPEED_Pos)
+#define USB_DEVICE_STATUS_SPEED(value) (USB_DEVICE_STATUS_SPEED_Msk & ((value) << USB_DEVICE_STATUS_SPEED_Pos))
+#define USB_DEVICE_STATUS_SPEED_FS_Val 0x0ul /**< \brief (USB_DEVICE_STATUS) Full-speed mode */
+#define USB_DEVICE_STATUS_SPEED_HS_Val 0x1ul /**< \brief (USB_DEVICE_STATUS) High-speed mode */
+#define USB_DEVICE_STATUS_SPEED_LS_Val 0x2ul /**< \brief (USB_DEVICE_STATUS) Low-speed mode */
+#define USB_DEVICE_STATUS_SPEED_FS (USB_DEVICE_STATUS_SPEED_FS_Val << USB_DEVICE_STATUS_SPEED_Pos)
+#define USB_DEVICE_STATUS_SPEED_HS (USB_DEVICE_STATUS_SPEED_HS_Val << USB_DEVICE_STATUS_SPEED_Pos)
+#define USB_DEVICE_STATUS_SPEED_LS (USB_DEVICE_STATUS_SPEED_LS_Val << USB_DEVICE_STATUS_SPEED_Pos)
+#define USB_DEVICE_STATUS_LINESTATE_Pos 6 /**< \brief (USB_DEVICE_STATUS) USB Line State Status */
+#define USB_DEVICE_STATUS_LINESTATE_Msk (0x3ul << USB_DEVICE_STATUS_LINESTATE_Pos)
+#define USB_DEVICE_STATUS_LINESTATE(value) (USB_DEVICE_STATUS_LINESTATE_Msk & ((value) << USB_DEVICE_STATUS_LINESTATE_Pos))
+#define USB_DEVICE_STATUS_LINESTATE_0_Val 0x0ul /**< \brief (USB_DEVICE_STATUS) SE0/RESET */
+#define USB_DEVICE_STATUS_LINESTATE_1_Val 0x1ul /**< \brief (USB_DEVICE_STATUS) FS-J or LS-K State */
+#define USB_DEVICE_STATUS_LINESTATE_2_Val 0x2ul /**< \brief (USB_DEVICE_STATUS) FS-K or LS-J State */
+#define USB_DEVICE_STATUS_LINESTATE_0 (USB_DEVICE_STATUS_LINESTATE_0_Val << USB_DEVICE_STATUS_LINESTATE_Pos)
+#define USB_DEVICE_STATUS_LINESTATE_1 (USB_DEVICE_STATUS_LINESTATE_1_Val << USB_DEVICE_STATUS_LINESTATE_Pos)
+#define USB_DEVICE_STATUS_LINESTATE_2 (USB_DEVICE_STATUS_LINESTATE_2_Val << USB_DEVICE_STATUS_LINESTATE_Pos)
+#define USB_DEVICE_STATUS_MASK 0xCCul /**< \brief (USB_DEVICE_STATUS) MASK Register */
+
+/* -------- USB_HOST_STATUS : (USB Offset: 0x00C) (R/W 8) HOST HOST Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t :2; /*!< bit: 0.. 1 Reserved */
+ uint8_t SPEED:2; /*!< bit: 2.. 3 Speed Status */
+ uint8_t :2; /*!< bit: 4.. 5 Reserved */
+ uint8_t LINESTATE:2; /*!< bit: 6.. 7 USB Line State Status */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_HOST_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_STATUS_OFFSET 0x00C /**< \brief (USB_HOST_STATUS offset) HOST Status */
+#define USB_HOST_STATUS_RESETVALUE 0x00ul /**< \brief (USB_HOST_STATUS reset_value) HOST Status */
+
+#define USB_HOST_STATUS_SPEED_Pos 2 /**< \brief (USB_HOST_STATUS) Speed Status */
+#define USB_HOST_STATUS_SPEED_Msk (0x3ul << USB_HOST_STATUS_SPEED_Pos)
+#define USB_HOST_STATUS_SPEED(value) (USB_HOST_STATUS_SPEED_Msk & ((value) << USB_HOST_STATUS_SPEED_Pos))
+#define USB_HOST_STATUS_LINESTATE_Pos 6 /**< \brief (USB_HOST_STATUS) USB Line State Status */
+#define USB_HOST_STATUS_LINESTATE_Msk (0x3ul << USB_HOST_STATUS_LINESTATE_Pos)
+#define USB_HOST_STATUS_LINESTATE(value) (USB_HOST_STATUS_LINESTATE_Msk & ((value) << USB_HOST_STATUS_LINESTATE_Pos))
+#define USB_HOST_STATUS_MASK 0xCCul /**< \brief (USB_HOST_STATUS) MASK Register */
+
+/* -------- USB_FSMSTATUS : (USB Offset: 0x00D) (R/ 8) Finite State Machine Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t FSMSTATE:6; /*!< bit: 0.. 5 Fine State Machine Status */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_FSMSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_FSMSTATUS_OFFSET 0x00D /**< \brief (USB_FSMSTATUS offset) Finite State Machine Status */
+#define USB_FSMSTATUS_RESETVALUE 0x01ul /**< \brief (USB_FSMSTATUS reset_value) Finite State Machine Status */
+
+#define USB_FSMSTATUS_FSMSTATE_Pos 0 /**< \brief (USB_FSMSTATUS) Fine State Machine Status */
+#define USB_FSMSTATUS_FSMSTATE_Msk (0x3Ful << USB_FSMSTATUS_FSMSTATE_Pos)
+#define USB_FSMSTATUS_FSMSTATE(value) (USB_FSMSTATUS_FSMSTATE_Msk & ((value) << USB_FSMSTATUS_FSMSTATE_Pos))
+#define USB_FSMSTATUS_FSMSTATE_OFF_Val 0x1ul /**< \brief (USB_FSMSTATUS) OFF (L3). It corresponds to the powered-off, disconnected, and disabled state */
+#define USB_FSMSTATUS_FSMSTATE_ON_Val 0x2ul /**< \brief (USB_FSMSTATUS) ON (L0). It corresponds to the Idle and Active states */
+#define USB_FSMSTATUS_FSMSTATE_SUSPEND_Val 0x4ul /**< \brief (USB_FSMSTATUS) SUSPEND (L2) */
+#define USB_FSMSTATUS_FSMSTATE_SLEEP_Val 0x8ul /**< \brief (USB_FSMSTATUS) SLEEP (L1) */
+#define USB_FSMSTATUS_FSMSTATE_DNRESUME_Val 0x10ul /**< \brief (USB_FSMSTATUS) DNRESUME. Down Stream Resume. */
+#define USB_FSMSTATUS_FSMSTATE_UPRESUME_Val 0x20ul /**< \brief (USB_FSMSTATUS) UPRESUME. Up Stream Resume. */
+#define USB_FSMSTATUS_FSMSTATE_RESET_Val 0x40ul /**< \brief (USB_FSMSTATUS) RESET. USB lines Reset. */
+#define USB_FSMSTATUS_FSMSTATE_OFF (USB_FSMSTATUS_FSMSTATE_OFF_Val << USB_FSMSTATUS_FSMSTATE_Pos)
+#define USB_FSMSTATUS_FSMSTATE_ON (USB_FSMSTATUS_FSMSTATE_ON_Val << USB_FSMSTATUS_FSMSTATE_Pos)
+#define USB_FSMSTATUS_FSMSTATE_SUSPEND (USB_FSMSTATUS_FSMSTATE_SUSPEND_Val << USB_FSMSTATUS_FSMSTATE_Pos)
+#define USB_FSMSTATUS_FSMSTATE_SLEEP (USB_FSMSTATUS_FSMSTATE_SLEEP_Val << USB_FSMSTATUS_FSMSTATE_Pos)
+#define USB_FSMSTATUS_FSMSTATE_DNRESUME (USB_FSMSTATUS_FSMSTATE_DNRESUME_Val << USB_FSMSTATUS_FSMSTATE_Pos)
+#define USB_FSMSTATUS_FSMSTATE_UPRESUME (USB_FSMSTATUS_FSMSTATE_UPRESUME_Val << USB_FSMSTATUS_FSMSTATE_Pos)
+#define USB_FSMSTATUS_FSMSTATE_RESET (USB_FSMSTATUS_FSMSTATE_RESET_Val << USB_FSMSTATUS_FSMSTATE_Pos)
+#define USB_FSMSTATUS_MASK 0x3Ful /**< \brief (USB_FSMSTATUS) MASK Register */
+
+/* -------- USB_DEVICE_FNUM : (USB Offset: 0x010) (R/ 16) DEVICE DEVICE Device Frame Number -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t MFNUM:3; /*!< bit: 0.. 2 Micro Frame Number */
+ uint16_t FNUM:11; /*!< bit: 3..13 Frame Number */
+ uint16_t :1; /*!< bit: 14 Reserved */
+ uint16_t FNCERR:1; /*!< bit: 15 Frame Number CRC Error */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_DEVICE_FNUM_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_FNUM_OFFSET 0x010 /**< \brief (USB_DEVICE_FNUM offset) DEVICE Device Frame Number */
+#define USB_DEVICE_FNUM_RESETVALUE 0x0000ul /**< \brief (USB_DEVICE_FNUM reset_value) DEVICE Device Frame Number */
+
+#define USB_DEVICE_FNUM_MFNUM_Pos 0 /**< \brief (USB_DEVICE_FNUM) Micro Frame Number */
+#define USB_DEVICE_FNUM_MFNUM_Msk (0x7ul << USB_DEVICE_FNUM_MFNUM_Pos)
+#define USB_DEVICE_FNUM_MFNUM(value) (USB_DEVICE_FNUM_MFNUM_Msk & ((value) << USB_DEVICE_FNUM_MFNUM_Pos))
+#define USB_DEVICE_FNUM_FNUM_Pos 3 /**< \brief (USB_DEVICE_FNUM) Frame Number */
+#define USB_DEVICE_FNUM_FNUM_Msk (0x7FFul << USB_DEVICE_FNUM_FNUM_Pos)
+#define USB_DEVICE_FNUM_FNUM(value) (USB_DEVICE_FNUM_FNUM_Msk & ((value) << USB_DEVICE_FNUM_FNUM_Pos))
+#define USB_DEVICE_FNUM_FNCERR_Pos 15 /**< \brief (USB_DEVICE_FNUM) Frame Number CRC Error */
+#define USB_DEVICE_FNUM_FNCERR (0x1ul << USB_DEVICE_FNUM_FNCERR_Pos)
+#define USB_DEVICE_FNUM_MASK 0xBFFFul /**< \brief (USB_DEVICE_FNUM) MASK Register */
+
+/* -------- USB_HOST_FNUM : (USB Offset: 0x010) (R/W 16) HOST HOST Host Frame Number -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t MFNUM:3; /*!< bit: 0.. 2 Micro Frame Number */
+ uint16_t FNUM:11; /*!< bit: 3..13 Frame Number */
+ uint16_t :2; /*!< bit: 14..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_HOST_FNUM_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_FNUM_OFFSET 0x010 /**< \brief (USB_HOST_FNUM offset) HOST Host Frame Number */
+#define USB_HOST_FNUM_RESETVALUE 0x0000ul /**< \brief (USB_HOST_FNUM reset_value) HOST Host Frame Number */
+
+#define USB_HOST_FNUM_MFNUM_Pos 0 /**< \brief (USB_HOST_FNUM) Micro Frame Number */
+#define USB_HOST_FNUM_MFNUM_Msk (0x7ul << USB_HOST_FNUM_MFNUM_Pos)
+#define USB_HOST_FNUM_MFNUM(value) (USB_HOST_FNUM_MFNUM_Msk & ((value) << USB_HOST_FNUM_MFNUM_Pos))
+#define USB_HOST_FNUM_FNUM_Pos 3 /**< \brief (USB_HOST_FNUM) Frame Number */
+#define USB_HOST_FNUM_FNUM_Msk (0x7FFul << USB_HOST_FNUM_FNUM_Pos)
+#define USB_HOST_FNUM_FNUM(value) (USB_HOST_FNUM_FNUM_Msk & ((value) << USB_HOST_FNUM_FNUM_Pos))
+#define USB_HOST_FNUM_MASK 0x3FFFul /**< \brief (USB_HOST_FNUM) MASK Register */
+
+/* -------- USB_HOST_FLENHIGH : (USB Offset: 0x012) (R/ 8) HOST HOST Host Frame Length -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t FLENHIGH:8; /*!< bit: 0.. 7 Frame Length */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_HOST_FLENHIGH_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_FLENHIGH_OFFSET 0x012 /**< \brief (USB_HOST_FLENHIGH offset) HOST Host Frame Length */
+#define USB_HOST_FLENHIGH_RESETVALUE 0x00ul /**< \brief (USB_HOST_FLENHIGH reset_value) HOST Host Frame Length */
+
+#define USB_HOST_FLENHIGH_FLENHIGH_Pos 0 /**< \brief (USB_HOST_FLENHIGH) Frame Length */
+#define USB_HOST_FLENHIGH_FLENHIGH_Msk (0xFFul << USB_HOST_FLENHIGH_FLENHIGH_Pos)
+#define USB_HOST_FLENHIGH_FLENHIGH(value) (USB_HOST_FLENHIGH_FLENHIGH_Msk & ((value) << USB_HOST_FLENHIGH_FLENHIGH_Pos))
+#define USB_HOST_FLENHIGH_MASK 0xFFul /**< \brief (USB_HOST_FLENHIGH) MASK Register */
+
+/* -------- USB_DEVICE_INTENCLR : (USB Offset: 0x014) (R/W 16) DEVICE DEVICE Device Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t SUSPEND:1; /*!< bit: 0 Suspend Interrupt Enable */
+ uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame Interrupt Enable in High Speed Mode */
+ uint16_t SOF:1; /*!< bit: 2 Start Of Frame Interrupt Enable */
+ uint16_t EORST:1; /*!< bit: 3 End of Reset Interrupt Enable */
+ uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */
+ uint16_t EORSM:1; /*!< bit: 5 End Of Resume Interrupt Enable */
+ uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume Interrupt Enable */
+ uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */
+ uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet Interrupt Enable */
+ uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend Interrupt Enable */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_DEVICE_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_INTENCLR_OFFSET 0x014 /**< \brief (USB_DEVICE_INTENCLR offset) DEVICE Device Interrupt Enable Clear */
+#define USB_DEVICE_INTENCLR_RESETVALUE 0x0000ul /**< \brief (USB_DEVICE_INTENCLR reset_value) DEVICE Device Interrupt Enable Clear */
+
+#define USB_DEVICE_INTENCLR_SUSPEND_Pos 0 /**< \brief (USB_DEVICE_INTENCLR) Suspend Interrupt Enable */
+#define USB_DEVICE_INTENCLR_SUSPEND (0x1ul << USB_DEVICE_INTENCLR_SUSPEND_Pos)
+#define USB_DEVICE_INTENCLR_MSOF_Pos 1 /**< \brief (USB_DEVICE_INTENCLR) Micro Start of Frame Interrupt Enable in High Speed Mode */
+#define USB_DEVICE_INTENCLR_MSOF (0x1ul << USB_DEVICE_INTENCLR_MSOF_Pos)
+#define USB_DEVICE_INTENCLR_SOF_Pos 2 /**< \brief (USB_DEVICE_INTENCLR) Start Of Frame Interrupt Enable */
+#define USB_DEVICE_INTENCLR_SOF (0x1ul << USB_DEVICE_INTENCLR_SOF_Pos)
+#define USB_DEVICE_INTENCLR_EORST_Pos 3 /**< \brief (USB_DEVICE_INTENCLR) End of Reset Interrupt Enable */
+#define USB_DEVICE_INTENCLR_EORST (0x1ul << USB_DEVICE_INTENCLR_EORST_Pos)
+#define USB_DEVICE_INTENCLR_WAKEUP_Pos 4 /**< \brief (USB_DEVICE_INTENCLR) Wake Up Interrupt Enable */
+#define USB_DEVICE_INTENCLR_WAKEUP (0x1ul << USB_DEVICE_INTENCLR_WAKEUP_Pos)
+#define USB_DEVICE_INTENCLR_EORSM_Pos 5 /**< \brief (USB_DEVICE_INTENCLR) End Of Resume Interrupt Enable */
+#define USB_DEVICE_INTENCLR_EORSM (0x1ul << USB_DEVICE_INTENCLR_EORSM_Pos)
+#define USB_DEVICE_INTENCLR_UPRSM_Pos 6 /**< \brief (USB_DEVICE_INTENCLR) Upstream Resume Interrupt Enable */
+#define USB_DEVICE_INTENCLR_UPRSM (0x1ul << USB_DEVICE_INTENCLR_UPRSM_Pos)
+#define USB_DEVICE_INTENCLR_RAMACER_Pos 7 /**< \brief (USB_DEVICE_INTENCLR) Ram Access Interrupt Enable */
+#define USB_DEVICE_INTENCLR_RAMACER (0x1ul << USB_DEVICE_INTENCLR_RAMACER_Pos)
+#define USB_DEVICE_INTENCLR_LPMNYET_Pos 8 /**< \brief (USB_DEVICE_INTENCLR) Link Power Management Not Yet Interrupt Enable */
+#define USB_DEVICE_INTENCLR_LPMNYET (0x1ul << USB_DEVICE_INTENCLR_LPMNYET_Pos)
+#define USB_DEVICE_INTENCLR_LPMSUSP_Pos 9 /**< \brief (USB_DEVICE_INTENCLR) Link Power Management Suspend Interrupt Enable */
+#define USB_DEVICE_INTENCLR_LPMSUSP (0x1ul << USB_DEVICE_INTENCLR_LPMSUSP_Pos)
+#define USB_DEVICE_INTENCLR_MASK 0x03FFul /**< \brief (USB_DEVICE_INTENCLR) MASK Register */
+
+/* -------- USB_HOST_INTENCLR : (USB Offset: 0x014) (R/W 16) HOST HOST Host Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t :2; /*!< bit: 0.. 1 Reserved */
+ uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame Interrupt Disable */
+ uint16_t RST:1; /*!< bit: 3 BUS Reset Interrupt Disable */
+ uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Disable */
+ uint16_t DNRSM:1; /*!< bit: 5 DownStream to Device Interrupt Disable */
+ uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume from Device Interrupt Disable */
+ uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Disable */
+ uint16_t DCONN:1; /*!< bit: 8 Device Connection Interrupt Disable */
+ uint16_t DDISC:1; /*!< bit: 9 Device Disconnection Interrupt Disable */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_HOST_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_INTENCLR_OFFSET 0x014 /**< \brief (USB_HOST_INTENCLR offset) HOST Host Interrupt Enable Clear */
+#define USB_HOST_INTENCLR_RESETVALUE 0x0000ul /**< \brief (USB_HOST_INTENCLR reset_value) HOST Host Interrupt Enable Clear */
+
+#define USB_HOST_INTENCLR_HSOF_Pos 2 /**< \brief (USB_HOST_INTENCLR) Host Start Of Frame Interrupt Disable */
+#define USB_HOST_INTENCLR_HSOF (0x1ul << USB_HOST_INTENCLR_HSOF_Pos)
+#define USB_HOST_INTENCLR_RST_Pos 3 /**< \brief (USB_HOST_INTENCLR) BUS Reset Interrupt Disable */
+#define USB_HOST_INTENCLR_RST (0x1ul << USB_HOST_INTENCLR_RST_Pos)
+#define USB_HOST_INTENCLR_WAKEUP_Pos 4 /**< \brief (USB_HOST_INTENCLR) Wake Up Interrupt Disable */
+#define USB_HOST_INTENCLR_WAKEUP (0x1ul << USB_HOST_INTENCLR_WAKEUP_Pos)
+#define USB_HOST_INTENCLR_DNRSM_Pos 5 /**< \brief (USB_HOST_INTENCLR) DownStream to Device Interrupt Disable */
+#define USB_HOST_INTENCLR_DNRSM (0x1ul << USB_HOST_INTENCLR_DNRSM_Pos)
+#define USB_HOST_INTENCLR_UPRSM_Pos 6 /**< \brief (USB_HOST_INTENCLR) Upstream Resume from Device Interrupt Disable */
+#define USB_HOST_INTENCLR_UPRSM (0x1ul << USB_HOST_INTENCLR_UPRSM_Pos)
+#define USB_HOST_INTENCLR_RAMACER_Pos 7 /**< \brief (USB_HOST_INTENCLR) Ram Access Interrupt Disable */
+#define USB_HOST_INTENCLR_RAMACER (0x1ul << USB_HOST_INTENCLR_RAMACER_Pos)
+#define USB_HOST_INTENCLR_DCONN_Pos 8 /**< \brief (USB_HOST_INTENCLR) Device Connection Interrupt Disable */
+#define USB_HOST_INTENCLR_DCONN (0x1ul << USB_HOST_INTENCLR_DCONN_Pos)
+#define USB_HOST_INTENCLR_DDISC_Pos 9 /**< \brief (USB_HOST_INTENCLR) Device Disconnection Interrupt Disable */
+#define USB_HOST_INTENCLR_DDISC (0x1ul << USB_HOST_INTENCLR_DDISC_Pos)
+#define USB_HOST_INTENCLR_MASK 0x03FCul /**< \brief (USB_HOST_INTENCLR) MASK Register */
+
+/* -------- USB_DEVICE_INTENSET : (USB Offset: 0x018) (R/W 16) DEVICE DEVICE Device Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t SUSPEND:1; /*!< bit: 0 Suspend Interrupt Enable */
+ uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame Interrupt Enable in High Speed Mode */
+ uint16_t SOF:1; /*!< bit: 2 Start Of Frame Interrupt Enable */
+ uint16_t EORST:1; /*!< bit: 3 End of Reset Interrupt Enable */
+ uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */
+ uint16_t EORSM:1; /*!< bit: 5 End Of Resume Interrupt Enable */
+ uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume Interrupt Enable */
+ uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */
+ uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet Interrupt Enable */
+ uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend Interrupt Enable */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_DEVICE_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_INTENSET_OFFSET 0x018 /**< \brief (USB_DEVICE_INTENSET offset) DEVICE Device Interrupt Enable Set */
+#define USB_DEVICE_INTENSET_RESETVALUE 0x0000ul /**< \brief (USB_DEVICE_INTENSET reset_value) DEVICE Device Interrupt Enable Set */
+
+#define USB_DEVICE_INTENSET_SUSPEND_Pos 0 /**< \brief (USB_DEVICE_INTENSET) Suspend Interrupt Enable */
+#define USB_DEVICE_INTENSET_SUSPEND (0x1ul << USB_DEVICE_INTENSET_SUSPEND_Pos)
+#define USB_DEVICE_INTENSET_MSOF_Pos 1 /**< \brief (USB_DEVICE_INTENSET) Micro Start of Frame Interrupt Enable in High Speed Mode */
+#define USB_DEVICE_INTENSET_MSOF (0x1ul << USB_DEVICE_INTENSET_MSOF_Pos)
+#define USB_DEVICE_INTENSET_SOF_Pos 2 /**< \brief (USB_DEVICE_INTENSET) Start Of Frame Interrupt Enable */
+#define USB_DEVICE_INTENSET_SOF (0x1ul << USB_DEVICE_INTENSET_SOF_Pos)
+#define USB_DEVICE_INTENSET_EORST_Pos 3 /**< \brief (USB_DEVICE_INTENSET) End of Reset Interrupt Enable */
+#define USB_DEVICE_INTENSET_EORST (0x1ul << USB_DEVICE_INTENSET_EORST_Pos)
+#define USB_DEVICE_INTENSET_WAKEUP_Pos 4 /**< \brief (USB_DEVICE_INTENSET) Wake Up Interrupt Enable */
+#define USB_DEVICE_INTENSET_WAKEUP (0x1ul << USB_DEVICE_INTENSET_WAKEUP_Pos)
+#define USB_DEVICE_INTENSET_EORSM_Pos 5 /**< \brief (USB_DEVICE_INTENSET) End Of Resume Interrupt Enable */
+#define USB_DEVICE_INTENSET_EORSM (0x1ul << USB_DEVICE_INTENSET_EORSM_Pos)
+#define USB_DEVICE_INTENSET_UPRSM_Pos 6 /**< \brief (USB_DEVICE_INTENSET) Upstream Resume Interrupt Enable */
+#define USB_DEVICE_INTENSET_UPRSM (0x1ul << USB_DEVICE_INTENSET_UPRSM_Pos)
+#define USB_DEVICE_INTENSET_RAMACER_Pos 7 /**< \brief (USB_DEVICE_INTENSET) Ram Access Interrupt Enable */
+#define USB_DEVICE_INTENSET_RAMACER (0x1ul << USB_DEVICE_INTENSET_RAMACER_Pos)
+#define USB_DEVICE_INTENSET_LPMNYET_Pos 8 /**< \brief (USB_DEVICE_INTENSET) Link Power Management Not Yet Interrupt Enable */
+#define USB_DEVICE_INTENSET_LPMNYET (0x1ul << USB_DEVICE_INTENSET_LPMNYET_Pos)
+#define USB_DEVICE_INTENSET_LPMSUSP_Pos 9 /**< \brief (USB_DEVICE_INTENSET) Link Power Management Suspend Interrupt Enable */
+#define USB_DEVICE_INTENSET_LPMSUSP (0x1ul << USB_DEVICE_INTENSET_LPMSUSP_Pos)
+#define USB_DEVICE_INTENSET_MASK 0x03FFul /**< \brief (USB_DEVICE_INTENSET) MASK Register */
+
+/* -------- USB_HOST_INTENSET : (USB Offset: 0x018) (R/W 16) HOST HOST Host Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t :2; /*!< bit: 0.. 1 Reserved */
+ uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame Interrupt Enable */
+ uint16_t RST:1; /*!< bit: 3 Bus Reset Interrupt Enable */
+ uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */
+ uint16_t DNRSM:1; /*!< bit: 5 DownStream to the Device Interrupt Enable */
+ uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume fromthe device Interrupt Enable */
+ uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */
+ uint16_t DCONN:1; /*!< bit: 8 Link Power Management Interrupt Enable */
+ uint16_t DDISC:1; /*!< bit: 9 Device Disconnection Interrupt Enable */
+ uint16_t :6; /*!< bit: 10..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_HOST_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_INTENSET_OFFSET 0x018 /**< \brief (USB_HOST_INTENSET offset) HOST Host Interrupt Enable Set */
+#define USB_HOST_INTENSET_RESETVALUE 0x0000ul /**< \brief (USB_HOST_INTENSET reset_value) HOST Host Interrupt Enable Set */
+
+#define USB_HOST_INTENSET_HSOF_Pos 2 /**< \brief (USB_HOST_INTENSET) Host Start Of Frame Interrupt Enable */
+#define USB_HOST_INTENSET_HSOF (0x1ul << USB_HOST_INTENSET_HSOF_Pos)
+#define USB_HOST_INTENSET_RST_Pos 3 /**< \brief (USB_HOST_INTENSET) Bus Reset Interrupt Enable */
+#define USB_HOST_INTENSET_RST (0x1ul << USB_HOST_INTENSET_RST_Pos)
+#define USB_HOST_INTENSET_WAKEUP_Pos 4 /**< \brief (USB_HOST_INTENSET) Wake Up Interrupt Enable */
+#define USB_HOST_INTENSET_WAKEUP (0x1ul << USB_HOST_INTENSET_WAKEUP_Pos)
+#define USB_HOST_INTENSET_DNRSM_Pos 5 /**< \brief (USB_HOST_INTENSET) DownStream to the Device Interrupt Enable */
+#define USB_HOST_INTENSET_DNRSM (0x1ul << USB_HOST_INTENSET_DNRSM_Pos)
+#define USB_HOST_INTENSET_UPRSM_Pos 6 /**< \brief (USB_HOST_INTENSET) Upstream Resume fromthe device Interrupt Enable */
+#define USB_HOST_INTENSET_UPRSM (0x1ul << USB_HOST_INTENSET_UPRSM_Pos)
+#define USB_HOST_INTENSET_RAMACER_Pos 7 /**< \brief (USB_HOST_INTENSET) Ram Access Interrupt Enable */
+#define USB_HOST_INTENSET_RAMACER (0x1ul << USB_HOST_INTENSET_RAMACER_Pos)
+#define USB_HOST_INTENSET_DCONN_Pos 8 /**< \brief (USB_HOST_INTENSET) Link Power Management Interrupt Enable */
+#define USB_HOST_INTENSET_DCONN (0x1ul << USB_HOST_INTENSET_DCONN_Pos)
+#define USB_HOST_INTENSET_DDISC_Pos 9 /**< \brief (USB_HOST_INTENSET) Device Disconnection Interrupt Enable */
+#define USB_HOST_INTENSET_DDISC (0x1ul << USB_HOST_INTENSET_DDISC_Pos)
+#define USB_HOST_INTENSET_MASK 0x03FCul /**< \brief (USB_HOST_INTENSET) MASK Register */
+
+/* -------- USB_DEVICE_INTFLAG : (USB Offset: 0x01C) (R/W 16) DEVICE DEVICE Device Interrupt Flag -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint16_t SUSPEND:1; /*!< bit: 0 Suspend */
+ __I uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame in High Speed Mode */
+ __I uint16_t SOF:1; /*!< bit: 2 Start Of Frame */
+ __I uint16_t EORST:1; /*!< bit: 3 End of Reset */
+ __I uint16_t WAKEUP:1; /*!< bit: 4 Wake Up */
+ __I uint16_t EORSM:1; /*!< bit: 5 End Of Resume */
+ __I uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume */
+ __I uint16_t RAMACER:1; /*!< bit: 7 Ram Access */
+ __I uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet */
+ __I uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend */
+ __I uint16_t :6; /*!< bit: 10..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_DEVICE_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_INTFLAG_OFFSET 0x01C /**< \brief (USB_DEVICE_INTFLAG offset) DEVICE Device Interrupt Flag */
+#define USB_DEVICE_INTFLAG_RESETVALUE 0x0000ul /**< \brief (USB_DEVICE_INTFLAG reset_value) DEVICE Device Interrupt Flag */
+
+#define USB_DEVICE_INTFLAG_SUSPEND_Pos 0 /**< \brief (USB_DEVICE_INTFLAG) Suspend */
+#define USB_DEVICE_INTFLAG_SUSPEND (0x1ul << USB_DEVICE_INTFLAG_SUSPEND_Pos)
+#define USB_DEVICE_INTFLAG_MSOF_Pos 1 /**< \brief (USB_DEVICE_INTFLAG) Micro Start of Frame in High Speed Mode */
+#define USB_DEVICE_INTFLAG_MSOF (0x1ul << USB_DEVICE_INTFLAG_MSOF_Pos)
+#define USB_DEVICE_INTFLAG_SOF_Pos 2 /**< \brief (USB_DEVICE_INTFLAG) Start Of Frame */
+#define USB_DEVICE_INTFLAG_SOF (0x1ul << USB_DEVICE_INTFLAG_SOF_Pos)
+#define USB_DEVICE_INTFLAG_EORST_Pos 3 /**< \brief (USB_DEVICE_INTFLAG) End of Reset */
+#define USB_DEVICE_INTFLAG_EORST (0x1ul << USB_DEVICE_INTFLAG_EORST_Pos)
+#define USB_DEVICE_INTFLAG_WAKEUP_Pos 4 /**< \brief (USB_DEVICE_INTFLAG) Wake Up */
+#define USB_DEVICE_INTFLAG_WAKEUP (0x1ul << USB_DEVICE_INTFLAG_WAKEUP_Pos)
+#define USB_DEVICE_INTFLAG_EORSM_Pos 5 /**< \brief (USB_DEVICE_INTFLAG) End Of Resume */
+#define USB_DEVICE_INTFLAG_EORSM (0x1ul << USB_DEVICE_INTFLAG_EORSM_Pos)
+#define USB_DEVICE_INTFLAG_UPRSM_Pos 6 /**< \brief (USB_DEVICE_INTFLAG) Upstream Resume */
+#define USB_DEVICE_INTFLAG_UPRSM (0x1ul << USB_DEVICE_INTFLAG_UPRSM_Pos)
+#define USB_DEVICE_INTFLAG_RAMACER_Pos 7 /**< \brief (USB_DEVICE_INTFLAG) Ram Access */
+#define USB_DEVICE_INTFLAG_RAMACER (0x1ul << USB_DEVICE_INTFLAG_RAMACER_Pos)
+#define USB_DEVICE_INTFLAG_LPMNYET_Pos 8 /**< \brief (USB_DEVICE_INTFLAG) Link Power Management Not Yet */
+#define USB_DEVICE_INTFLAG_LPMNYET (0x1ul << USB_DEVICE_INTFLAG_LPMNYET_Pos)
+#define USB_DEVICE_INTFLAG_LPMSUSP_Pos 9 /**< \brief (USB_DEVICE_INTFLAG) Link Power Management Suspend */
+#define USB_DEVICE_INTFLAG_LPMSUSP (0x1ul << USB_DEVICE_INTFLAG_LPMSUSP_Pos)
+#define USB_DEVICE_INTFLAG_MASK 0x03FFul /**< \brief (USB_DEVICE_INTFLAG) MASK Register */
+
+/* -------- USB_HOST_INTFLAG : (USB Offset: 0x01C) (R/W 16) HOST HOST Host Interrupt Flag -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint16_t :2; /*!< bit: 0.. 1 Reserved */
+ __I uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame */
+ __I uint16_t RST:1; /*!< bit: 3 Bus Reset */
+ __I uint16_t WAKEUP:1; /*!< bit: 4 Wake Up */
+ __I uint16_t DNRSM:1; /*!< bit: 5 Downstream */
+ __I uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume from the Device */
+ __I uint16_t RAMACER:1; /*!< bit: 7 Ram Access */
+ __I uint16_t DCONN:1; /*!< bit: 8 Device Connection */
+ __I uint16_t DDISC:1; /*!< bit: 9 Device Disconnection */
+ __I uint16_t :6; /*!< bit: 10..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_HOST_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_INTFLAG_OFFSET 0x01C /**< \brief (USB_HOST_INTFLAG offset) HOST Host Interrupt Flag */
+#define USB_HOST_INTFLAG_RESETVALUE 0x0000ul /**< \brief (USB_HOST_INTFLAG reset_value) HOST Host Interrupt Flag */
+
+#define USB_HOST_INTFLAG_HSOF_Pos 2 /**< \brief (USB_HOST_INTFLAG) Host Start Of Frame */
+#define USB_HOST_INTFLAG_HSOF (0x1ul << USB_HOST_INTFLAG_HSOF_Pos)
+#define USB_HOST_INTFLAG_RST_Pos 3 /**< \brief (USB_HOST_INTFLAG) Bus Reset */
+#define USB_HOST_INTFLAG_RST (0x1ul << USB_HOST_INTFLAG_RST_Pos)
+#define USB_HOST_INTFLAG_WAKEUP_Pos 4 /**< \brief (USB_HOST_INTFLAG) Wake Up */
+#define USB_HOST_INTFLAG_WAKEUP (0x1ul << USB_HOST_INTFLAG_WAKEUP_Pos)
+#define USB_HOST_INTFLAG_DNRSM_Pos 5 /**< \brief (USB_HOST_INTFLAG) Downstream */
+#define USB_HOST_INTFLAG_DNRSM (0x1ul << USB_HOST_INTFLAG_DNRSM_Pos)
+#define USB_HOST_INTFLAG_UPRSM_Pos 6 /**< \brief (USB_HOST_INTFLAG) Upstream Resume from the Device */
+#define USB_HOST_INTFLAG_UPRSM (0x1ul << USB_HOST_INTFLAG_UPRSM_Pos)
+#define USB_HOST_INTFLAG_RAMACER_Pos 7 /**< \brief (USB_HOST_INTFLAG) Ram Access */
+#define USB_HOST_INTFLAG_RAMACER (0x1ul << USB_HOST_INTFLAG_RAMACER_Pos)
+#define USB_HOST_INTFLAG_DCONN_Pos 8 /**< \brief (USB_HOST_INTFLAG) Device Connection */
+#define USB_HOST_INTFLAG_DCONN (0x1ul << USB_HOST_INTFLAG_DCONN_Pos)
+#define USB_HOST_INTFLAG_DDISC_Pos 9 /**< \brief (USB_HOST_INTFLAG) Device Disconnection */
+#define USB_HOST_INTFLAG_DDISC (0x1ul << USB_HOST_INTFLAG_DDISC_Pos)
+#define USB_HOST_INTFLAG_MASK 0x03FCul /**< \brief (USB_HOST_INTFLAG) MASK Register */
+
+/* -------- USB_DEVICE_EPINTSMRY : (USB Offset: 0x020) (R/ 16) DEVICE DEVICE End Point Interrupt Summary -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t EPINT0:1; /*!< bit: 0 End Point 0 Interrupt */
+ uint16_t EPINT1:1; /*!< bit: 1 End Point 1 Interrupt */
+ uint16_t EPINT2:1; /*!< bit: 2 End Point 2 Interrupt */
+ uint16_t EPINT3:1; /*!< bit: 3 End Point 3 Interrupt */
+ uint16_t EPINT4:1; /*!< bit: 4 End Point 4 Interrupt */
+ uint16_t EPINT5:1; /*!< bit: 5 End Point 5 Interrupt */
+ uint16_t EPINT6:1; /*!< bit: 6 End Point 6 Interrupt */
+ uint16_t EPINT7:1; /*!< bit: 7 End Point 7 Interrupt */
+ uint16_t :8; /*!< bit: 8..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t EPINT:8; /*!< bit: 0.. 7 End Point x Interrupt */
+ uint16_t :8; /*!< bit: 8..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_DEVICE_EPINTSMRY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_EPINTSMRY_OFFSET 0x020 /**< \brief (USB_DEVICE_EPINTSMRY offset) DEVICE End Point Interrupt Summary */
+#define USB_DEVICE_EPINTSMRY_RESETVALUE 0x0000ul /**< \brief (USB_DEVICE_EPINTSMRY reset_value) DEVICE End Point Interrupt Summary */
+
+#define USB_DEVICE_EPINTSMRY_EPINT0_Pos 0 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 0 Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT0 (1 << USB_DEVICE_EPINTSMRY_EPINT0_Pos)
+#define USB_DEVICE_EPINTSMRY_EPINT1_Pos 1 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 1 Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT1 (1 << USB_DEVICE_EPINTSMRY_EPINT1_Pos)
+#define USB_DEVICE_EPINTSMRY_EPINT2_Pos 2 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 2 Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT2 (1 << USB_DEVICE_EPINTSMRY_EPINT2_Pos)
+#define USB_DEVICE_EPINTSMRY_EPINT3_Pos 3 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 3 Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT3 (1 << USB_DEVICE_EPINTSMRY_EPINT3_Pos)
+#define USB_DEVICE_EPINTSMRY_EPINT4_Pos 4 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 4 Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT4 (1 << USB_DEVICE_EPINTSMRY_EPINT4_Pos)
+#define USB_DEVICE_EPINTSMRY_EPINT5_Pos 5 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 5 Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT5 (1 << USB_DEVICE_EPINTSMRY_EPINT5_Pos)
+#define USB_DEVICE_EPINTSMRY_EPINT6_Pos 6 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 6 Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT6 (1 << USB_DEVICE_EPINTSMRY_EPINT6_Pos)
+#define USB_DEVICE_EPINTSMRY_EPINT7_Pos 7 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 7 Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT7 (1 << USB_DEVICE_EPINTSMRY_EPINT7_Pos)
+#define USB_DEVICE_EPINTSMRY_EPINT_Pos 0 /**< \brief (USB_DEVICE_EPINTSMRY) End Point x Interrupt */
+#define USB_DEVICE_EPINTSMRY_EPINT_Msk (0xFFul << USB_DEVICE_EPINTSMRY_EPINT_Pos)
+#define USB_DEVICE_EPINTSMRY_EPINT(value) (USB_DEVICE_EPINTSMRY_EPINT_Msk & ((value) << USB_DEVICE_EPINTSMRY_EPINT_Pos))
+#define USB_DEVICE_EPINTSMRY_MASK 0x00FFul /**< \brief (USB_DEVICE_EPINTSMRY) MASK Register */
+
+/* -------- USB_HOST_PINTSMRY : (USB Offset: 0x020) (R/ 16) HOST HOST Pipe Interrupt Summary -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t EPINT0:1; /*!< bit: 0 Pipe 0 Interrupt */
+ uint16_t EPINT1:1; /*!< bit: 1 Pipe 1 Interrupt */
+ uint16_t EPINT2:1; /*!< bit: 2 Pipe 2 Interrupt */
+ uint16_t EPINT3:1; /*!< bit: 3 Pipe 3 Interrupt */
+ uint16_t EPINT4:1; /*!< bit: 4 Pipe 4 Interrupt */
+ uint16_t EPINT5:1; /*!< bit: 5 Pipe 5 Interrupt */
+ uint16_t EPINT6:1; /*!< bit: 6 Pipe 6 Interrupt */
+ uint16_t EPINT7:1; /*!< bit: 7 Pipe 7 Interrupt */
+ uint16_t :8; /*!< bit: 8..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint16_t EPINT:8; /*!< bit: 0.. 7 Pipe x Interrupt */
+ uint16_t :8; /*!< bit: 8..15 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_HOST_PINTSMRY_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_PINTSMRY_OFFSET 0x020 /**< \brief (USB_HOST_PINTSMRY offset) HOST Pipe Interrupt Summary */
+#define USB_HOST_PINTSMRY_RESETVALUE 0x0000ul /**< \brief (USB_HOST_PINTSMRY reset_value) HOST Pipe Interrupt Summary */
+
+#define USB_HOST_PINTSMRY_EPINT0_Pos 0 /**< \brief (USB_HOST_PINTSMRY) Pipe 0 Interrupt */
+#define USB_HOST_PINTSMRY_EPINT0 (1 << USB_HOST_PINTSMRY_EPINT0_Pos)
+#define USB_HOST_PINTSMRY_EPINT1_Pos 1 /**< \brief (USB_HOST_PINTSMRY) Pipe 1 Interrupt */
+#define USB_HOST_PINTSMRY_EPINT1 (1 << USB_HOST_PINTSMRY_EPINT1_Pos)
+#define USB_HOST_PINTSMRY_EPINT2_Pos 2 /**< \brief (USB_HOST_PINTSMRY) Pipe 2 Interrupt */
+#define USB_HOST_PINTSMRY_EPINT2 (1 << USB_HOST_PINTSMRY_EPINT2_Pos)
+#define USB_HOST_PINTSMRY_EPINT3_Pos 3 /**< \brief (USB_HOST_PINTSMRY) Pipe 3 Interrupt */
+#define USB_HOST_PINTSMRY_EPINT3 (1 << USB_HOST_PINTSMRY_EPINT3_Pos)
+#define USB_HOST_PINTSMRY_EPINT4_Pos 4 /**< \brief (USB_HOST_PINTSMRY) Pipe 4 Interrupt */
+#define USB_HOST_PINTSMRY_EPINT4 (1 << USB_HOST_PINTSMRY_EPINT4_Pos)
+#define USB_HOST_PINTSMRY_EPINT5_Pos 5 /**< \brief (USB_HOST_PINTSMRY) Pipe 5 Interrupt */
+#define USB_HOST_PINTSMRY_EPINT5 (1 << USB_HOST_PINTSMRY_EPINT5_Pos)
+#define USB_HOST_PINTSMRY_EPINT6_Pos 6 /**< \brief (USB_HOST_PINTSMRY) Pipe 6 Interrupt */
+#define USB_HOST_PINTSMRY_EPINT6 (1 << USB_HOST_PINTSMRY_EPINT6_Pos)
+#define USB_HOST_PINTSMRY_EPINT7_Pos 7 /**< \brief (USB_HOST_PINTSMRY) Pipe 7 Interrupt */
+#define USB_HOST_PINTSMRY_EPINT7 (1 << USB_HOST_PINTSMRY_EPINT7_Pos)
+#define USB_HOST_PINTSMRY_EPINT_Pos 0 /**< \brief (USB_HOST_PINTSMRY) Pipe x Interrupt */
+#define USB_HOST_PINTSMRY_EPINT_Msk (0xFFul << USB_HOST_PINTSMRY_EPINT_Pos)
+#define USB_HOST_PINTSMRY_EPINT(value) (USB_HOST_PINTSMRY_EPINT_Msk & ((value) << USB_HOST_PINTSMRY_EPINT_Pos))
+#define USB_HOST_PINTSMRY_MASK 0x00FFul /**< \brief (USB_HOST_PINTSMRY) MASK Register */
+
+/* -------- USB_DESCADD : (USB Offset: 0x024) (R/W 32) Descriptor Address -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t DESCADD:32; /*!< bit: 0..31 Descriptor Address Value */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} USB_DESCADD_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DESCADD_OFFSET 0x024 /**< \brief (USB_DESCADD offset) Descriptor Address */
+#define USB_DESCADD_RESETVALUE 0x00000000ul /**< \brief (USB_DESCADD reset_value) Descriptor Address */
+
+#define USB_DESCADD_DESCADD_Pos 0 /**< \brief (USB_DESCADD) Descriptor Address Value */
+#define USB_DESCADD_DESCADD_Msk (0xFFFFFFFFul << USB_DESCADD_DESCADD_Pos)
+#define USB_DESCADD_DESCADD(value) (USB_DESCADD_DESCADD_Msk & ((value) << USB_DESCADD_DESCADD_Pos))
+#define USB_DESCADD_MASK 0xFFFFFFFFul /**< \brief (USB_DESCADD) MASK Register */
+
+/* -------- USB_PADCAL : (USB Offset: 0x028) (R/W 16) USB PAD Calibration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t TRANSP:5; /*!< bit: 0.. 4 USB Pad Transp calibration */
+ uint16_t :1; /*!< bit: 5 Reserved */
+ uint16_t TRANSN:5; /*!< bit: 6..10 USB Pad Transn calibration */
+ uint16_t :1; /*!< bit: 11 Reserved */
+ uint16_t TRIM:3; /*!< bit: 12..14 USB Pad Trim calibration */
+ uint16_t :1; /*!< bit: 15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_PADCAL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_PADCAL_OFFSET 0x028 /**< \brief (USB_PADCAL offset) USB PAD Calibration */
+#define USB_PADCAL_RESETVALUE 0x0000ul /**< \brief (USB_PADCAL reset_value) USB PAD Calibration */
+
+#define USB_PADCAL_TRANSP_Pos 0 /**< \brief (USB_PADCAL) USB Pad Transp calibration */
+#define USB_PADCAL_TRANSP_Msk (0x1Ful << USB_PADCAL_TRANSP_Pos)
+#define USB_PADCAL_TRANSP(value) (USB_PADCAL_TRANSP_Msk & ((value) << USB_PADCAL_TRANSP_Pos))
+#define USB_PADCAL_TRANSN_Pos 6 /**< \brief (USB_PADCAL) USB Pad Transn calibration */
+#define USB_PADCAL_TRANSN_Msk (0x1Ful << USB_PADCAL_TRANSN_Pos)
+#define USB_PADCAL_TRANSN(value) (USB_PADCAL_TRANSN_Msk & ((value) << USB_PADCAL_TRANSN_Pos))
+#define USB_PADCAL_TRIM_Pos 12 /**< \brief (USB_PADCAL) USB Pad Trim calibration */
+#define USB_PADCAL_TRIM_Msk (0x7ul << USB_PADCAL_TRIM_Pos)
+#define USB_PADCAL_TRIM(value) (USB_PADCAL_TRIM_Msk & ((value) << USB_PADCAL_TRIM_Pos))
+#define USB_PADCAL_MASK 0x77DFul /**< \brief (USB_PADCAL) MASK Register */
+
+/* -------- USB_DEVICE_EPCFG : (USB Offset: 0x100) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t EPTYPE0:3; /*!< bit: 0.. 2 End Point Type0 */
+ uint8_t :1; /*!< bit: 3 Reserved */
+ uint8_t EPTYPE1:3; /*!< bit: 4.. 6 End Point Type1 */
+ uint8_t NYETDIS:1; /*!< bit: 7 NYET Token Disable */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_DEVICE_EPCFG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_EPCFG_OFFSET 0x100 /**< \brief (USB_DEVICE_EPCFG offset) DEVICE_ENDPOINT End Point Configuration */
+#define USB_DEVICE_EPCFG_RESETVALUE 0x00ul /**< \brief (USB_DEVICE_EPCFG reset_value) DEVICE_ENDPOINT End Point Configuration */
+
+#define USB_DEVICE_EPCFG_EPTYPE0_Pos 0 /**< \brief (USB_DEVICE_EPCFG) End Point Type0 */
+#define USB_DEVICE_EPCFG_EPTYPE0_Msk (0x7ul << USB_DEVICE_EPCFG_EPTYPE0_Pos)
+#define USB_DEVICE_EPCFG_EPTYPE0(value) (USB_DEVICE_EPCFG_EPTYPE0_Msk & ((value) << USB_DEVICE_EPCFG_EPTYPE0_Pos))
+#define USB_DEVICE_EPCFG_EPTYPE1_Pos 4 /**< \brief (USB_DEVICE_EPCFG) End Point Type1 */
+#define USB_DEVICE_EPCFG_EPTYPE1_Msk (0x7ul << USB_DEVICE_EPCFG_EPTYPE1_Pos)
+#define USB_DEVICE_EPCFG_EPTYPE1(value) (USB_DEVICE_EPCFG_EPTYPE1_Msk & ((value) << USB_DEVICE_EPCFG_EPTYPE1_Pos))
+#define USB_DEVICE_EPCFG_NYETDIS_Pos 7 /**< \brief (USB_DEVICE_EPCFG) NYET Token Disable */
+#define USB_DEVICE_EPCFG_NYETDIS (0x1ul << USB_DEVICE_EPCFG_NYETDIS_Pos)
+#define USB_DEVICE_EPCFG_MASK 0xF7ul /**< \brief (USB_DEVICE_EPCFG) MASK Register */
+
+/* -------- USB_HOST_PCFG : (USB Offset: 0x100) (R/W 8) HOST HOST_PIPE End Point Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t PTOKEN:2; /*!< bit: 0.. 1 Pipe Token */
+ uint8_t BK:1; /*!< bit: 2 Pipe Bank */
+ uint8_t PTYPE:3; /*!< bit: 3.. 5 Pipe Type */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_HOST_PCFG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_PCFG_OFFSET 0x100 /**< \brief (USB_HOST_PCFG offset) HOST_PIPE End Point Configuration */
+#define USB_HOST_PCFG_RESETVALUE 0x00ul /**< \brief (USB_HOST_PCFG reset_value) HOST_PIPE End Point Configuration */
+
+#define USB_HOST_PCFG_PTOKEN_Pos 0 /**< \brief (USB_HOST_PCFG) Pipe Token */
+#define USB_HOST_PCFG_PTOKEN_Msk (0x3ul << USB_HOST_PCFG_PTOKEN_Pos)
+#define USB_HOST_PCFG_PTOKEN(value) (USB_HOST_PCFG_PTOKEN_Msk & ((value) << USB_HOST_PCFG_PTOKEN_Pos))
+#define USB_HOST_PCFG_BK_Pos 2 /**< \brief (USB_HOST_PCFG) Pipe Bank */
+#define USB_HOST_PCFG_BK (0x1ul << USB_HOST_PCFG_BK_Pos)
+#define USB_HOST_PCFG_PTYPE_Pos 3 /**< \brief (USB_HOST_PCFG) Pipe Type */
+#define USB_HOST_PCFG_PTYPE_Msk (0x7ul << USB_HOST_PCFG_PTYPE_Pos)
+#define USB_HOST_PCFG_PTYPE(value) (USB_HOST_PCFG_PTYPE_Msk & ((value) << USB_HOST_PCFG_PTYPE_Pos))
+#define USB_HOST_PCFG_MASK 0x3Ful /**< \brief (USB_HOST_PCFG) MASK Register */
+
+/* -------- USB_HOST_BINTERVAL : (USB Offset: 0x103) (R/W 8) HOST HOST_PIPE Bus Access Period of Pipe -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t BITINTERVAL:8; /*!< bit: 0.. 7 Bit Interval */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_HOST_BINTERVAL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_BINTERVAL_OFFSET 0x103 /**< \brief (USB_HOST_BINTERVAL offset) HOST_PIPE Bus Access Period of Pipe */
+#define USB_HOST_BINTERVAL_RESETVALUE 0x00ul /**< \brief (USB_HOST_BINTERVAL reset_value) HOST_PIPE Bus Access Period of Pipe */
+
+#define USB_HOST_BINTERVAL_BITINTERVAL_Pos 0 /**< \brief (USB_HOST_BINTERVAL) Bit Interval */
+#define USB_HOST_BINTERVAL_BITINTERVAL_Msk (0xFFul << USB_HOST_BINTERVAL_BITINTERVAL_Pos)
+#define USB_HOST_BINTERVAL_BITINTERVAL(value) (USB_HOST_BINTERVAL_BITINTERVAL_Msk & ((value) << USB_HOST_BINTERVAL_BITINTERVAL_Pos))
+#define USB_HOST_BINTERVAL_MASK 0xFFul /**< \brief (USB_HOST_BINTERVAL) MASK Register */
+
+/* -------- USB_DEVICE_EPSTATUSCLR : (USB Offset: 0x104) ( /W 8) DEVICE DEVICE_ENDPOINT End Point Pipe Status Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle OUT Clear */
+ uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle IN Clear */
+ uint8_t CURBK:1; /*!< bit: 2 Curren Bank Clear */
+ uint8_t :1; /*!< bit: 3 Reserved */
+ uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request Clear */
+ uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request Clear */
+ uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Clear */
+ uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Clear */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t :4; /*!< bit: 0.. 3 Reserved */
+ uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request Clear */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_DEVICE_EPSTATUSCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_EPSTATUSCLR_OFFSET 0x104 /**< \brief (USB_DEVICE_EPSTATUSCLR offset) DEVICE_ENDPOINT End Point Pipe Status Clear */
+#define USB_DEVICE_EPSTATUSCLR_RESETVALUE 0x00ul /**< \brief (USB_DEVICE_EPSTATUSCLR reset_value) DEVICE_ENDPOINT End Point Pipe Status Clear */
+
+#define USB_DEVICE_EPSTATUSCLR_DTGLOUT_Pos 0 /**< \brief (USB_DEVICE_EPSTATUSCLR) Data Toggle OUT Clear */
+#define USB_DEVICE_EPSTATUSCLR_DTGLOUT (0x1ul << USB_DEVICE_EPSTATUSCLR_DTGLOUT_Pos)
+#define USB_DEVICE_EPSTATUSCLR_DTGLIN_Pos 1 /**< \brief (USB_DEVICE_EPSTATUSCLR) Data Toggle IN Clear */
+#define USB_DEVICE_EPSTATUSCLR_DTGLIN (0x1ul << USB_DEVICE_EPSTATUSCLR_DTGLIN_Pos)
+#define USB_DEVICE_EPSTATUSCLR_CURBK_Pos 2 /**< \brief (USB_DEVICE_EPSTATUSCLR) Curren Bank Clear */
+#define USB_DEVICE_EPSTATUSCLR_CURBK (0x1ul << USB_DEVICE_EPSTATUSCLR_CURBK_Pos)
+#define USB_DEVICE_EPSTATUSCLR_STALLRQ0_Pos 4 /**< \brief (USB_DEVICE_EPSTATUSCLR) Stall 0 Request Clear */
+#define USB_DEVICE_EPSTATUSCLR_STALLRQ0 (1 << USB_DEVICE_EPSTATUSCLR_STALLRQ0_Pos)
+#define USB_DEVICE_EPSTATUSCLR_STALLRQ1_Pos 5 /**< \brief (USB_DEVICE_EPSTATUSCLR) Stall 1 Request Clear */
+#define USB_DEVICE_EPSTATUSCLR_STALLRQ1 (1 << USB_DEVICE_EPSTATUSCLR_STALLRQ1_Pos)
+#define USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos 4 /**< \brief (USB_DEVICE_EPSTATUSCLR) Stall x Request Clear */
+#define USB_DEVICE_EPSTATUSCLR_STALLRQ_Msk (0x3ul << USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos)
+#define USB_DEVICE_EPSTATUSCLR_STALLRQ(value) (USB_DEVICE_EPSTATUSCLR_STALLRQ_Msk & ((value) << USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos))
+#define USB_DEVICE_EPSTATUSCLR_BK0RDY_Pos 6 /**< \brief (USB_DEVICE_EPSTATUSCLR) Bank 0 Ready Clear */
+#define USB_DEVICE_EPSTATUSCLR_BK0RDY (0x1ul << USB_DEVICE_EPSTATUSCLR_BK0RDY_Pos)
+#define USB_DEVICE_EPSTATUSCLR_BK1RDY_Pos 7 /**< \brief (USB_DEVICE_EPSTATUSCLR) Bank 1 Ready Clear */
+#define USB_DEVICE_EPSTATUSCLR_BK1RDY (0x1ul << USB_DEVICE_EPSTATUSCLR_BK1RDY_Pos)
+#define USB_DEVICE_EPSTATUSCLR_MASK 0xF7ul /**< \brief (USB_DEVICE_EPSTATUSCLR) MASK Register */
+
+/* -------- USB_HOST_PSTATUSCLR : (USB Offset: 0x104) ( /W 8) HOST HOST_PIPE End Point Pipe Status Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DTGL:1; /*!< bit: 0 Data Toggle clear */
+ uint8_t :1; /*!< bit: 1 Reserved */
+ uint8_t CURBK:1; /*!< bit: 2 Curren Bank clear */
+ uint8_t :1; /*!< bit: 3 Reserved */
+ uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze Clear */
+ uint8_t :1; /*!< bit: 5 Reserved */
+ uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Clear */
+ uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Clear */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_HOST_PSTATUSCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_PSTATUSCLR_OFFSET 0x104 /**< \brief (USB_HOST_PSTATUSCLR offset) HOST_PIPE End Point Pipe Status Clear */
+#define USB_HOST_PSTATUSCLR_RESETVALUE 0x00ul /**< \brief (USB_HOST_PSTATUSCLR reset_value) HOST_PIPE End Point Pipe Status Clear */
+
+#define USB_HOST_PSTATUSCLR_DTGL_Pos 0 /**< \brief (USB_HOST_PSTATUSCLR) Data Toggle clear */
+#define USB_HOST_PSTATUSCLR_DTGL (0x1ul << USB_HOST_PSTATUSCLR_DTGL_Pos)
+#define USB_HOST_PSTATUSCLR_CURBK_Pos 2 /**< \brief (USB_HOST_PSTATUSCLR) Curren Bank clear */
+#define USB_HOST_PSTATUSCLR_CURBK (0x1ul << USB_HOST_PSTATUSCLR_CURBK_Pos)
+#define USB_HOST_PSTATUSCLR_PFREEZE_Pos 4 /**< \brief (USB_HOST_PSTATUSCLR) Pipe Freeze Clear */
+#define USB_HOST_PSTATUSCLR_PFREEZE (0x1ul << USB_HOST_PSTATUSCLR_PFREEZE_Pos)
+#define USB_HOST_PSTATUSCLR_BK0RDY_Pos 6 /**< \brief (USB_HOST_PSTATUSCLR) Bank 0 Ready Clear */
+#define USB_HOST_PSTATUSCLR_BK0RDY (0x1ul << USB_HOST_PSTATUSCLR_BK0RDY_Pos)
+#define USB_HOST_PSTATUSCLR_BK1RDY_Pos 7 /**< \brief (USB_HOST_PSTATUSCLR) Bank 1 Ready Clear */
+#define USB_HOST_PSTATUSCLR_BK1RDY (0x1ul << USB_HOST_PSTATUSCLR_BK1RDY_Pos)
+#define USB_HOST_PSTATUSCLR_MASK 0xD5ul /**< \brief (USB_HOST_PSTATUSCLR) MASK Register */
+
+/* -------- USB_DEVICE_EPSTATUSSET : (USB Offset: 0x105) ( /W 8) DEVICE DEVICE_ENDPOINT End Point Pipe Status Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle OUT Set */
+ uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle IN Set */
+ uint8_t CURBK:1; /*!< bit: 2 Current Bank Set */
+ uint8_t :1; /*!< bit: 3 Reserved */
+ uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request Set */
+ uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request Set */
+ uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Set */
+ uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Set */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t :4; /*!< bit: 0.. 3 Reserved */
+ uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request Set */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_DEVICE_EPSTATUSSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_EPSTATUSSET_OFFSET 0x105 /**< \brief (USB_DEVICE_EPSTATUSSET offset) DEVICE_ENDPOINT End Point Pipe Status Set */
+#define USB_DEVICE_EPSTATUSSET_RESETVALUE 0x00ul /**< \brief (USB_DEVICE_EPSTATUSSET reset_value) DEVICE_ENDPOINT End Point Pipe Status Set */
+
+#define USB_DEVICE_EPSTATUSSET_DTGLOUT_Pos 0 /**< \brief (USB_DEVICE_EPSTATUSSET) Data Toggle OUT Set */
+#define USB_DEVICE_EPSTATUSSET_DTGLOUT (0x1ul << USB_DEVICE_EPSTATUSSET_DTGLOUT_Pos)
+#define USB_DEVICE_EPSTATUSSET_DTGLIN_Pos 1 /**< \brief (USB_DEVICE_EPSTATUSSET) Data Toggle IN Set */
+#define USB_DEVICE_EPSTATUSSET_DTGLIN (0x1ul << USB_DEVICE_EPSTATUSSET_DTGLIN_Pos)
+#define USB_DEVICE_EPSTATUSSET_CURBK_Pos 2 /**< \brief (USB_DEVICE_EPSTATUSSET) Current Bank Set */
+#define USB_DEVICE_EPSTATUSSET_CURBK (0x1ul << USB_DEVICE_EPSTATUSSET_CURBK_Pos)
+#define USB_DEVICE_EPSTATUSSET_STALLRQ0_Pos 4 /**< \brief (USB_DEVICE_EPSTATUSSET) Stall 0 Request Set */
+#define USB_DEVICE_EPSTATUSSET_STALLRQ0 (1 << USB_DEVICE_EPSTATUSSET_STALLRQ0_Pos)
+#define USB_DEVICE_EPSTATUSSET_STALLRQ1_Pos 5 /**< \brief (USB_DEVICE_EPSTATUSSET) Stall 1 Request Set */
+#define USB_DEVICE_EPSTATUSSET_STALLRQ1 (1 << USB_DEVICE_EPSTATUSSET_STALLRQ1_Pos)
+#define USB_DEVICE_EPSTATUSSET_STALLRQ_Pos 4 /**< \brief (USB_DEVICE_EPSTATUSSET) Stall x Request Set */
+#define USB_DEVICE_EPSTATUSSET_STALLRQ_Msk (0x3ul << USB_DEVICE_EPSTATUSSET_STALLRQ_Pos)
+#define USB_DEVICE_EPSTATUSSET_STALLRQ(value) (USB_DEVICE_EPSTATUSSET_STALLRQ_Msk & ((value) << USB_DEVICE_EPSTATUSSET_STALLRQ_Pos))
+#define USB_DEVICE_EPSTATUSSET_BK0RDY_Pos 6 /**< \brief (USB_DEVICE_EPSTATUSSET) Bank 0 Ready Set */
+#define USB_DEVICE_EPSTATUSSET_BK0RDY (0x1ul << USB_DEVICE_EPSTATUSSET_BK0RDY_Pos)
+#define USB_DEVICE_EPSTATUSSET_BK1RDY_Pos 7 /**< \brief (USB_DEVICE_EPSTATUSSET) Bank 1 Ready Set */
+#define USB_DEVICE_EPSTATUSSET_BK1RDY (0x1ul << USB_DEVICE_EPSTATUSSET_BK1RDY_Pos)
+#define USB_DEVICE_EPSTATUSSET_MASK 0xF7ul /**< \brief (USB_DEVICE_EPSTATUSSET) MASK Register */
+
+/* -------- USB_HOST_PSTATUSSET : (USB Offset: 0x105) ( /W 8) HOST HOST_PIPE End Point Pipe Status Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DTGL:1; /*!< bit: 0 Data Toggle Set */
+ uint8_t :1; /*!< bit: 1 Reserved */
+ uint8_t CURBK:1; /*!< bit: 2 Current Bank Set */
+ uint8_t :1; /*!< bit: 3 Reserved */
+ uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze Set */
+ uint8_t :1; /*!< bit: 5 Reserved */
+ uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Set */
+ uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Set */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_HOST_PSTATUSSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_PSTATUSSET_OFFSET 0x105 /**< \brief (USB_HOST_PSTATUSSET offset) HOST_PIPE End Point Pipe Status Set */
+#define USB_HOST_PSTATUSSET_RESETVALUE 0x00ul /**< \brief (USB_HOST_PSTATUSSET reset_value) HOST_PIPE End Point Pipe Status Set */
+
+#define USB_HOST_PSTATUSSET_DTGL_Pos 0 /**< \brief (USB_HOST_PSTATUSSET) Data Toggle Set */
+#define USB_HOST_PSTATUSSET_DTGL (0x1ul << USB_HOST_PSTATUSSET_DTGL_Pos)
+#define USB_HOST_PSTATUSSET_CURBK_Pos 2 /**< \brief (USB_HOST_PSTATUSSET) Current Bank Set */
+#define USB_HOST_PSTATUSSET_CURBK (0x1ul << USB_HOST_PSTATUSSET_CURBK_Pos)
+#define USB_HOST_PSTATUSSET_PFREEZE_Pos 4 /**< \brief (USB_HOST_PSTATUSSET) Pipe Freeze Set */
+#define USB_HOST_PSTATUSSET_PFREEZE (0x1ul << USB_HOST_PSTATUSSET_PFREEZE_Pos)
+#define USB_HOST_PSTATUSSET_BK0RDY_Pos 6 /**< \brief (USB_HOST_PSTATUSSET) Bank 0 Ready Set */
+#define USB_HOST_PSTATUSSET_BK0RDY (0x1ul << USB_HOST_PSTATUSSET_BK0RDY_Pos)
+#define USB_HOST_PSTATUSSET_BK1RDY_Pos 7 /**< \brief (USB_HOST_PSTATUSSET) Bank 1 Ready Set */
+#define USB_HOST_PSTATUSSET_BK1RDY (0x1ul << USB_HOST_PSTATUSSET_BK1RDY_Pos)
+#define USB_HOST_PSTATUSSET_MASK 0xD5ul /**< \brief (USB_HOST_PSTATUSSET) MASK Register */
+
+/* -------- USB_DEVICE_EPSTATUS : (USB Offset: 0x106) (R/ 8) DEVICE DEVICE_ENDPOINT End Point Pipe Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle Out */
+ uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle In */
+ uint8_t CURBK:1; /*!< bit: 2 Current Bank */
+ uint8_t :1; /*!< bit: 3 Reserved */
+ uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request */
+ uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request */
+ uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 ready */
+ uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 ready */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t :4; /*!< bit: 0.. 3 Reserved */
+ uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_DEVICE_EPSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_EPSTATUS_OFFSET 0x106 /**< \brief (USB_DEVICE_EPSTATUS offset) DEVICE_ENDPOINT End Point Pipe Status */
+#define USB_DEVICE_EPSTATUS_RESETVALUE 0x00ul /**< \brief (USB_DEVICE_EPSTATUS reset_value) DEVICE_ENDPOINT End Point Pipe Status */
+
+#define USB_DEVICE_EPSTATUS_DTGLOUT_Pos 0 /**< \brief (USB_DEVICE_EPSTATUS) Data Toggle Out */
+#define USB_DEVICE_EPSTATUS_DTGLOUT (0x1ul << USB_DEVICE_EPSTATUS_DTGLOUT_Pos)
+#define USB_DEVICE_EPSTATUS_DTGLIN_Pos 1 /**< \brief (USB_DEVICE_EPSTATUS) Data Toggle In */
+#define USB_DEVICE_EPSTATUS_DTGLIN (0x1ul << USB_DEVICE_EPSTATUS_DTGLIN_Pos)
+#define USB_DEVICE_EPSTATUS_CURBK_Pos 2 /**< \brief (USB_DEVICE_EPSTATUS) Current Bank */
+#define USB_DEVICE_EPSTATUS_CURBK (0x1ul << USB_DEVICE_EPSTATUS_CURBK_Pos)
+#define USB_DEVICE_EPSTATUS_STALLRQ0_Pos 4 /**< \brief (USB_DEVICE_EPSTATUS) Stall 0 Request */
+#define USB_DEVICE_EPSTATUS_STALLRQ0 (1 << USB_DEVICE_EPSTATUS_STALLRQ0_Pos)
+#define USB_DEVICE_EPSTATUS_STALLRQ1_Pos 5 /**< \brief (USB_DEVICE_EPSTATUS) Stall 1 Request */
+#define USB_DEVICE_EPSTATUS_STALLRQ1 (1 << USB_DEVICE_EPSTATUS_STALLRQ1_Pos)
+#define USB_DEVICE_EPSTATUS_STALLRQ_Pos 4 /**< \brief (USB_DEVICE_EPSTATUS) Stall x Request */
+#define USB_DEVICE_EPSTATUS_STALLRQ_Msk (0x3ul << USB_DEVICE_EPSTATUS_STALLRQ_Pos)
+#define USB_DEVICE_EPSTATUS_STALLRQ(value) (USB_DEVICE_EPSTATUS_STALLRQ_Msk & ((value) << USB_DEVICE_EPSTATUS_STALLRQ_Pos))
+#define USB_DEVICE_EPSTATUS_BK0RDY_Pos 6 /**< \brief (USB_DEVICE_EPSTATUS) Bank 0 ready */
+#define USB_DEVICE_EPSTATUS_BK0RDY (0x1ul << USB_DEVICE_EPSTATUS_BK0RDY_Pos)
+#define USB_DEVICE_EPSTATUS_BK1RDY_Pos 7 /**< \brief (USB_DEVICE_EPSTATUS) Bank 1 ready */
+#define USB_DEVICE_EPSTATUS_BK1RDY (0x1ul << USB_DEVICE_EPSTATUS_BK1RDY_Pos)
+#define USB_DEVICE_EPSTATUS_MASK 0xF7ul /**< \brief (USB_DEVICE_EPSTATUS) MASK Register */
+
+/* -------- USB_HOST_PSTATUS : (USB Offset: 0x106) (R/ 8) HOST HOST_PIPE End Point Pipe Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t DTGL:1; /*!< bit: 0 Data Toggle */
+ uint8_t :1; /*!< bit: 1 Reserved */
+ uint8_t CURBK:1; /*!< bit: 2 Current Bank */
+ uint8_t :1; /*!< bit: 3 Reserved */
+ uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze */
+ uint8_t :1; /*!< bit: 5 Reserved */
+ uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 ready */
+ uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 ready */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_HOST_PSTATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_PSTATUS_OFFSET 0x106 /**< \brief (USB_HOST_PSTATUS offset) HOST_PIPE End Point Pipe Status */
+#define USB_HOST_PSTATUS_RESETVALUE 0x00ul /**< \brief (USB_HOST_PSTATUS reset_value) HOST_PIPE End Point Pipe Status */
+
+#define USB_HOST_PSTATUS_DTGL_Pos 0 /**< \brief (USB_HOST_PSTATUS) Data Toggle */
+#define USB_HOST_PSTATUS_DTGL (0x1ul << USB_HOST_PSTATUS_DTGL_Pos)
+#define USB_HOST_PSTATUS_CURBK_Pos 2 /**< \brief (USB_HOST_PSTATUS) Current Bank */
+#define USB_HOST_PSTATUS_CURBK (0x1ul << USB_HOST_PSTATUS_CURBK_Pos)
+#define USB_HOST_PSTATUS_PFREEZE_Pos 4 /**< \brief (USB_HOST_PSTATUS) Pipe Freeze */
+#define USB_HOST_PSTATUS_PFREEZE (0x1ul << USB_HOST_PSTATUS_PFREEZE_Pos)
+#define USB_HOST_PSTATUS_BK0RDY_Pos 6 /**< \brief (USB_HOST_PSTATUS) Bank 0 ready */
+#define USB_HOST_PSTATUS_BK0RDY (0x1ul << USB_HOST_PSTATUS_BK0RDY_Pos)
+#define USB_HOST_PSTATUS_BK1RDY_Pos 7 /**< \brief (USB_HOST_PSTATUS) Bank 1 ready */
+#define USB_HOST_PSTATUS_BK1RDY (0x1ul << USB_HOST_PSTATUS_BK1RDY_Pos)
+#define USB_HOST_PSTATUS_MASK 0xD5ul /**< \brief (USB_HOST_PSTATUS) MASK Register */
+
+/* -------- USB_DEVICE_EPINTFLAG : (USB Offset: 0x107) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Interrupt Flag -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 */
+ __I uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 */
+ __I uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 */
+ __I uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 */
+ __I uint8_t RXSTP:1; /*!< bit: 4 Received Setup */
+ __I uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/out */
+ __I uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/out */
+ __I uint8_t :1; /*!< bit: 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ __I uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x */
+ __I uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x */
+ __I uint8_t :1; /*!< bit: 4 Reserved */
+ __I uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/out */
+ __I uint8_t :1; /*!< bit: 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_DEVICE_EPINTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_EPINTFLAG_OFFSET 0x107 /**< \brief (USB_DEVICE_EPINTFLAG offset) DEVICE_ENDPOINT End Point Interrupt Flag */
+#define USB_DEVICE_EPINTFLAG_RESETVALUE 0x00ul /**< \brief (USB_DEVICE_EPINTFLAG reset_value) DEVICE_ENDPOINT End Point Interrupt Flag */
+
+#define USB_DEVICE_EPINTFLAG_TRCPT0_Pos 0 /**< \brief (USB_DEVICE_EPINTFLAG) Transfer Complete 0 */
+#define USB_DEVICE_EPINTFLAG_TRCPT0 (1 << USB_DEVICE_EPINTFLAG_TRCPT0_Pos)
+#define USB_DEVICE_EPINTFLAG_TRCPT1_Pos 1 /**< \brief (USB_DEVICE_EPINTFLAG) Transfer Complete 1 */
+#define USB_DEVICE_EPINTFLAG_TRCPT1 (1 << USB_DEVICE_EPINTFLAG_TRCPT1_Pos)
+#define USB_DEVICE_EPINTFLAG_TRCPT_Pos 0 /**< \brief (USB_DEVICE_EPINTFLAG) Transfer Complete x */
+#define USB_DEVICE_EPINTFLAG_TRCPT_Msk (0x3ul << USB_DEVICE_EPINTFLAG_TRCPT_Pos)
+#define USB_DEVICE_EPINTFLAG_TRCPT(value) (USB_DEVICE_EPINTFLAG_TRCPT_Msk & ((value) << USB_DEVICE_EPINTFLAG_TRCPT_Pos))
+#define USB_DEVICE_EPINTFLAG_TRFAIL0_Pos 2 /**< \brief (USB_DEVICE_EPINTFLAG) Error Flow 0 */
+#define USB_DEVICE_EPINTFLAG_TRFAIL0 (1 << USB_DEVICE_EPINTFLAG_TRFAIL0_Pos)
+#define USB_DEVICE_EPINTFLAG_TRFAIL1_Pos 3 /**< \brief (USB_DEVICE_EPINTFLAG) Error Flow 1 */
+#define USB_DEVICE_EPINTFLAG_TRFAIL1 (1 << USB_DEVICE_EPINTFLAG_TRFAIL1_Pos)
+#define USB_DEVICE_EPINTFLAG_TRFAIL_Pos 2 /**< \brief (USB_DEVICE_EPINTFLAG) Error Flow x */
+#define USB_DEVICE_EPINTFLAG_TRFAIL_Msk (0x3ul << USB_DEVICE_EPINTFLAG_TRFAIL_Pos)
+#define USB_DEVICE_EPINTFLAG_TRFAIL(value) (USB_DEVICE_EPINTFLAG_TRFAIL_Msk & ((value) << USB_DEVICE_EPINTFLAG_TRFAIL_Pos))
+#define USB_DEVICE_EPINTFLAG_RXSTP_Pos 4 /**< \brief (USB_DEVICE_EPINTFLAG) Received Setup */
+#define USB_DEVICE_EPINTFLAG_RXSTP (0x1ul << USB_DEVICE_EPINTFLAG_RXSTP_Pos)
+#define USB_DEVICE_EPINTFLAG_STALL0_Pos 5 /**< \brief (USB_DEVICE_EPINTFLAG) Stall 0 In/out */
+#define USB_DEVICE_EPINTFLAG_STALL0 (1 << USB_DEVICE_EPINTFLAG_STALL0_Pos)
+#define USB_DEVICE_EPINTFLAG_STALL1_Pos 6 /**< \brief (USB_DEVICE_EPINTFLAG) Stall 1 In/out */
+#define USB_DEVICE_EPINTFLAG_STALL1 (1 << USB_DEVICE_EPINTFLAG_STALL1_Pos)
+#define USB_DEVICE_EPINTFLAG_STALL_Pos 5 /**< \brief (USB_DEVICE_EPINTFLAG) Stall x In/out */
+#define USB_DEVICE_EPINTFLAG_STALL_Msk (0x3ul << USB_DEVICE_EPINTFLAG_STALL_Pos)
+#define USB_DEVICE_EPINTFLAG_STALL(value) (USB_DEVICE_EPINTFLAG_STALL_Msk & ((value) << USB_DEVICE_EPINTFLAG_STALL_Pos))
+#define USB_DEVICE_EPINTFLAG_MASK 0x7Ful /**< \brief (USB_DEVICE_EPINTFLAG) MASK Register */
+
+/* -------- USB_HOST_PINTFLAG : (USB Offset: 0x107) (R/W 8) HOST HOST_PIPE Pipe Interrupt Flag -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Flag */
+ __I uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Flag */
+ __I uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Flag */
+ __I uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Flag */
+ __I uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Flag */
+ __I uint8_t STALL:1; /*!< bit: 5 Stall Interrupt Flag */
+ __I uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ __I uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Flag */
+ __I uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_HOST_PINTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_PINTFLAG_OFFSET 0x107 /**< \brief (USB_HOST_PINTFLAG offset) HOST_PIPE Pipe Interrupt Flag */
+#define USB_HOST_PINTFLAG_RESETVALUE 0x00ul /**< \brief (USB_HOST_PINTFLAG reset_value) HOST_PIPE Pipe Interrupt Flag */
+
+#define USB_HOST_PINTFLAG_TRCPT0_Pos 0 /**< \brief (USB_HOST_PINTFLAG) Transfer Complete 0 Interrupt Flag */
+#define USB_HOST_PINTFLAG_TRCPT0 (1 << USB_HOST_PINTFLAG_TRCPT0_Pos)
+#define USB_HOST_PINTFLAG_TRCPT1_Pos 1 /**< \brief (USB_HOST_PINTFLAG) Transfer Complete 1 Interrupt Flag */
+#define USB_HOST_PINTFLAG_TRCPT1 (1 << USB_HOST_PINTFLAG_TRCPT1_Pos)
+#define USB_HOST_PINTFLAG_TRCPT_Pos 0 /**< \brief (USB_HOST_PINTFLAG) Transfer Complete x Interrupt Flag */
+#define USB_HOST_PINTFLAG_TRCPT_Msk (0x3ul << USB_HOST_PINTFLAG_TRCPT_Pos)
+#define USB_HOST_PINTFLAG_TRCPT(value) (USB_HOST_PINTFLAG_TRCPT_Msk & ((value) << USB_HOST_PINTFLAG_TRCPT_Pos))
+#define USB_HOST_PINTFLAG_TRFAIL_Pos 2 /**< \brief (USB_HOST_PINTFLAG) Error Flow Interrupt Flag */
+#define USB_HOST_PINTFLAG_TRFAIL (0x1ul << USB_HOST_PINTFLAG_TRFAIL_Pos)
+#define USB_HOST_PINTFLAG_PERR_Pos 3 /**< \brief (USB_HOST_PINTFLAG) Pipe Error Interrupt Flag */
+#define USB_HOST_PINTFLAG_PERR (0x1ul << USB_HOST_PINTFLAG_PERR_Pos)
+#define USB_HOST_PINTFLAG_TXSTP_Pos 4 /**< \brief (USB_HOST_PINTFLAG) Transmit Setup Interrupt Flag */
+#define USB_HOST_PINTFLAG_TXSTP (0x1ul << USB_HOST_PINTFLAG_TXSTP_Pos)
+#define USB_HOST_PINTFLAG_STALL_Pos 5 /**< \brief (USB_HOST_PINTFLAG) Stall Interrupt Flag */
+#define USB_HOST_PINTFLAG_STALL (0x1ul << USB_HOST_PINTFLAG_STALL_Pos)
+#define USB_HOST_PINTFLAG_MASK 0x3Ful /**< \brief (USB_HOST_PINTFLAG) MASK Register */
+
+/* -------- USB_DEVICE_EPINTENCLR : (USB Offset: 0x108) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Interrupt Clear Flag -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Disable */
+ uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Disable */
+ uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 Interrupt Disable */
+ uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 Interrupt Disable */
+ uint8_t RXSTP:1; /*!< bit: 4 Received Setup Interrupt Disable */
+ uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/Out Interrupt Disable */
+ uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/Out Interrupt Disable */
+ uint8_t :1; /*!< bit: 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Disable */
+ uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x Interrupt Disable */
+ uint8_t :1; /*!< bit: 4 Reserved */
+ uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/Out Interrupt Disable */
+ uint8_t :1; /*!< bit: 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_DEVICE_EPINTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_EPINTENCLR_OFFSET 0x108 /**< \brief (USB_DEVICE_EPINTENCLR offset) DEVICE_ENDPOINT End Point Interrupt Clear Flag */
+#define USB_DEVICE_EPINTENCLR_RESETVALUE 0x00ul /**< \brief (USB_DEVICE_EPINTENCLR reset_value) DEVICE_ENDPOINT End Point Interrupt Clear Flag */
+
+#define USB_DEVICE_EPINTENCLR_TRCPT0_Pos 0 /**< \brief (USB_DEVICE_EPINTENCLR) Transfer Complete 0 Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_TRCPT0 (1 << USB_DEVICE_EPINTENCLR_TRCPT0_Pos)
+#define USB_DEVICE_EPINTENCLR_TRCPT1_Pos 1 /**< \brief (USB_DEVICE_EPINTENCLR) Transfer Complete 1 Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_TRCPT1 (1 << USB_DEVICE_EPINTENCLR_TRCPT1_Pos)
+#define USB_DEVICE_EPINTENCLR_TRCPT_Pos 0 /**< \brief (USB_DEVICE_EPINTENCLR) Transfer Complete x Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_TRCPT_Msk (0x3ul << USB_DEVICE_EPINTENCLR_TRCPT_Pos)
+#define USB_DEVICE_EPINTENCLR_TRCPT(value) (USB_DEVICE_EPINTENCLR_TRCPT_Msk & ((value) << USB_DEVICE_EPINTENCLR_TRCPT_Pos))
+#define USB_DEVICE_EPINTENCLR_TRFAIL0_Pos 2 /**< \brief (USB_DEVICE_EPINTENCLR) Error Flow 0 Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_TRFAIL0 (1 << USB_DEVICE_EPINTENCLR_TRFAIL0_Pos)
+#define USB_DEVICE_EPINTENCLR_TRFAIL1_Pos 3 /**< \brief (USB_DEVICE_EPINTENCLR) Error Flow 1 Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_TRFAIL1 (1 << USB_DEVICE_EPINTENCLR_TRFAIL1_Pos)
+#define USB_DEVICE_EPINTENCLR_TRFAIL_Pos 2 /**< \brief (USB_DEVICE_EPINTENCLR) Error Flow x Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_TRFAIL_Msk (0x3ul << USB_DEVICE_EPINTENCLR_TRFAIL_Pos)
+#define USB_DEVICE_EPINTENCLR_TRFAIL(value) (USB_DEVICE_EPINTENCLR_TRFAIL_Msk & ((value) << USB_DEVICE_EPINTENCLR_TRFAIL_Pos))
+#define USB_DEVICE_EPINTENCLR_RXSTP_Pos 4 /**< \brief (USB_DEVICE_EPINTENCLR) Received Setup Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_RXSTP (0x1ul << USB_DEVICE_EPINTENCLR_RXSTP_Pos)
+#define USB_DEVICE_EPINTENCLR_STALL0_Pos 5 /**< \brief (USB_DEVICE_EPINTENCLR) Stall 0 In/Out Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_STALL0 (1 << USB_DEVICE_EPINTENCLR_STALL0_Pos)
+#define USB_DEVICE_EPINTENCLR_STALL1_Pos 6 /**< \brief (USB_DEVICE_EPINTENCLR) Stall 1 In/Out Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_STALL1 (1 << USB_DEVICE_EPINTENCLR_STALL1_Pos)
+#define USB_DEVICE_EPINTENCLR_STALL_Pos 5 /**< \brief (USB_DEVICE_EPINTENCLR) Stall x In/Out Interrupt Disable */
+#define USB_DEVICE_EPINTENCLR_STALL_Msk (0x3ul << USB_DEVICE_EPINTENCLR_STALL_Pos)
+#define USB_DEVICE_EPINTENCLR_STALL(value) (USB_DEVICE_EPINTENCLR_STALL_Msk & ((value) << USB_DEVICE_EPINTENCLR_STALL_Pos))
+#define USB_DEVICE_EPINTENCLR_MASK 0x7Ful /**< \brief (USB_DEVICE_EPINTENCLR) MASK Register */
+
+/* -------- USB_HOST_PINTENCLR : (USB Offset: 0x108) (R/W 8) HOST HOST_PIPE Pipe Interrupt Flag Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Disable */
+ uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Disable */
+ uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Disable */
+ uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Disable */
+ uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Disable */
+ uint8_t STALL:1; /*!< bit: 5 Stall Inetrrupt Disable */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Disable */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_HOST_PINTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_PINTENCLR_OFFSET 0x108 /**< \brief (USB_HOST_PINTENCLR offset) HOST_PIPE Pipe Interrupt Flag Clear */
+#define USB_HOST_PINTENCLR_RESETVALUE 0x00ul /**< \brief (USB_HOST_PINTENCLR reset_value) HOST_PIPE Pipe Interrupt Flag Clear */
+
+#define USB_HOST_PINTENCLR_TRCPT0_Pos 0 /**< \brief (USB_HOST_PINTENCLR) Transfer Complete 0 Disable */
+#define USB_HOST_PINTENCLR_TRCPT0 (1 << USB_HOST_PINTENCLR_TRCPT0_Pos)
+#define USB_HOST_PINTENCLR_TRCPT1_Pos 1 /**< \brief (USB_HOST_PINTENCLR) Transfer Complete 1 Disable */
+#define USB_HOST_PINTENCLR_TRCPT1 (1 << USB_HOST_PINTENCLR_TRCPT1_Pos)
+#define USB_HOST_PINTENCLR_TRCPT_Pos 0 /**< \brief (USB_HOST_PINTENCLR) Transfer Complete x Disable */
+#define USB_HOST_PINTENCLR_TRCPT_Msk (0x3ul << USB_HOST_PINTENCLR_TRCPT_Pos)
+#define USB_HOST_PINTENCLR_TRCPT(value) (USB_HOST_PINTENCLR_TRCPT_Msk & ((value) << USB_HOST_PINTENCLR_TRCPT_Pos))
+#define USB_HOST_PINTENCLR_TRFAIL_Pos 2 /**< \brief (USB_HOST_PINTENCLR) Error Flow Interrupt Disable */
+#define USB_HOST_PINTENCLR_TRFAIL (0x1ul << USB_HOST_PINTENCLR_TRFAIL_Pos)
+#define USB_HOST_PINTENCLR_PERR_Pos 3 /**< \brief (USB_HOST_PINTENCLR) Pipe Error Interrupt Disable */
+#define USB_HOST_PINTENCLR_PERR (0x1ul << USB_HOST_PINTENCLR_PERR_Pos)
+#define USB_HOST_PINTENCLR_TXSTP_Pos 4 /**< \brief (USB_HOST_PINTENCLR) Transmit Setup Interrupt Disable */
+#define USB_HOST_PINTENCLR_TXSTP (0x1ul << USB_HOST_PINTENCLR_TXSTP_Pos)
+#define USB_HOST_PINTENCLR_STALL_Pos 5 /**< \brief (USB_HOST_PINTENCLR) Stall Inetrrupt Disable */
+#define USB_HOST_PINTENCLR_STALL (0x1ul << USB_HOST_PINTENCLR_STALL_Pos)
+#define USB_HOST_PINTENCLR_MASK 0x3Ful /**< \brief (USB_HOST_PINTENCLR) MASK Register */
+
+/* -------- USB_DEVICE_EPINTENSET : (USB Offset: 0x109) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Interrupt Set Flag -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Enable */
+ uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Enable */
+ uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 Interrupt Enable */
+ uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 Interrupt Enable */
+ uint8_t RXSTP:1; /*!< bit: 4 Received Setup Interrupt Enable */
+ uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/out Interrupt enable */
+ uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/out Interrupt enable */
+ uint8_t :1; /*!< bit: 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Enable */
+ uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x Interrupt Enable */
+ uint8_t :1; /*!< bit: 4 Reserved */
+ uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/out Interrupt enable */
+ uint8_t :1; /*!< bit: 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_DEVICE_EPINTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_EPINTENSET_OFFSET 0x109 /**< \brief (USB_DEVICE_EPINTENSET offset) DEVICE_ENDPOINT End Point Interrupt Set Flag */
+#define USB_DEVICE_EPINTENSET_RESETVALUE 0x00ul /**< \brief (USB_DEVICE_EPINTENSET reset_value) DEVICE_ENDPOINT End Point Interrupt Set Flag */
+
+#define USB_DEVICE_EPINTENSET_TRCPT0_Pos 0 /**< \brief (USB_DEVICE_EPINTENSET) Transfer Complete 0 Interrupt Enable */
+#define USB_DEVICE_EPINTENSET_TRCPT0 (1 << USB_DEVICE_EPINTENSET_TRCPT0_Pos)
+#define USB_DEVICE_EPINTENSET_TRCPT1_Pos 1 /**< \brief (USB_DEVICE_EPINTENSET) Transfer Complete 1 Interrupt Enable */
+#define USB_DEVICE_EPINTENSET_TRCPT1 (1 << USB_DEVICE_EPINTENSET_TRCPT1_Pos)
+#define USB_DEVICE_EPINTENSET_TRCPT_Pos 0 /**< \brief (USB_DEVICE_EPINTENSET) Transfer Complete x Interrupt Enable */
+#define USB_DEVICE_EPINTENSET_TRCPT_Msk (0x3ul << USB_DEVICE_EPINTENSET_TRCPT_Pos)
+#define USB_DEVICE_EPINTENSET_TRCPT(value) (USB_DEVICE_EPINTENSET_TRCPT_Msk & ((value) << USB_DEVICE_EPINTENSET_TRCPT_Pos))
+#define USB_DEVICE_EPINTENSET_TRFAIL0_Pos 2 /**< \brief (USB_DEVICE_EPINTENSET) Error Flow 0 Interrupt Enable */
+#define USB_DEVICE_EPINTENSET_TRFAIL0 (1 << USB_DEVICE_EPINTENSET_TRFAIL0_Pos)
+#define USB_DEVICE_EPINTENSET_TRFAIL1_Pos 3 /**< \brief (USB_DEVICE_EPINTENSET) Error Flow 1 Interrupt Enable */
+#define USB_DEVICE_EPINTENSET_TRFAIL1 (1 << USB_DEVICE_EPINTENSET_TRFAIL1_Pos)
+#define USB_DEVICE_EPINTENSET_TRFAIL_Pos 2 /**< \brief (USB_DEVICE_EPINTENSET) Error Flow x Interrupt Enable */
+#define USB_DEVICE_EPINTENSET_TRFAIL_Msk (0x3ul << USB_DEVICE_EPINTENSET_TRFAIL_Pos)
+#define USB_DEVICE_EPINTENSET_TRFAIL(value) (USB_DEVICE_EPINTENSET_TRFAIL_Msk & ((value) << USB_DEVICE_EPINTENSET_TRFAIL_Pos))
+#define USB_DEVICE_EPINTENSET_RXSTP_Pos 4 /**< \brief (USB_DEVICE_EPINTENSET) Received Setup Interrupt Enable */
+#define USB_DEVICE_EPINTENSET_RXSTP (0x1ul << USB_DEVICE_EPINTENSET_RXSTP_Pos)
+#define USB_DEVICE_EPINTENSET_STALL0_Pos 5 /**< \brief (USB_DEVICE_EPINTENSET) Stall 0 In/out Interrupt enable */
+#define USB_DEVICE_EPINTENSET_STALL0 (1 << USB_DEVICE_EPINTENSET_STALL0_Pos)
+#define USB_DEVICE_EPINTENSET_STALL1_Pos 6 /**< \brief (USB_DEVICE_EPINTENSET) Stall 1 In/out Interrupt enable */
+#define USB_DEVICE_EPINTENSET_STALL1 (1 << USB_DEVICE_EPINTENSET_STALL1_Pos)
+#define USB_DEVICE_EPINTENSET_STALL_Pos 5 /**< \brief (USB_DEVICE_EPINTENSET) Stall x In/out Interrupt enable */
+#define USB_DEVICE_EPINTENSET_STALL_Msk (0x3ul << USB_DEVICE_EPINTENSET_STALL_Pos)
+#define USB_DEVICE_EPINTENSET_STALL(value) (USB_DEVICE_EPINTENSET_STALL_Msk & ((value) << USB_DEVICE_EPINTENSET_STALL_Pos))
+#define USB_DEVICE_EPINTENSET_MASK 0x7Ful /**< \brief (USB_DEVICE_EPINTENSET) MASK Register */
+
+/* -------- USB_HOST_PINTENSET : (USB Offset: 0x109) (R/W 8) HOST HOST_PIPE Pipe Interrupt Flag Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Enable */
+ uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Enable */
+ uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Enable */
+ uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Enable */
+ uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Enable */
+ uint8_t STALL:1; /*!< bit: 5 Stall Interrupt Enable */
+ uint8_t :2; /*!< bit: 6.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ struct {
+ uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Enable */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } vec; /*!< Structure used for vec access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_HOST_PINTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_PINTENSET_OFFSET 0x109 /**< \brief (USB_HOST_PINTENSET offset) HOST_PIPE Pipe Interrupt Flag Set */
+#define USB_HOST_PINTENSET_RESETVALUE 0x00ul /**< \brief (USB_HOST_PINTENSET reset_value) HOST_PIPE Pipe Interrupt Flag Set */
+
+#define USB_HOST_PINTENSET_TRCPT0_Pos 0 /**< \brief (USB_HOST_PINTENSET) Transfer Complete 0 Interrupt Enable */
+#define USB_HOST_PINTENSET_TRCPT0 (1 << USB_HOST_PINTENSET_TRCPT0_Pos)
+#define USB_HOST_PINTENSET_TRCPT1_Pos 1 /**< \brief (USB_HOST_PINTENSET) Transfer Complete 1 Interrupt Enable */
+#define USB_HOST_PINTENSET_TRCPT1 (1 << USB_HOST_PINTENSET_TRCPT1_Pos)
+#define USB_HOST_PINTENSET_TRCPT_Pos 0 /**< \brief (USB_HOST_PINTENSET) Transfer Complete x Interrupt Enable */
+#define USB_HOST_PINTENSET_TRCPT_Msk (0x3ul << USB_HOST_PINTENSET_TRCPT_Pos)
+#define USB_HOST_PINTENSET_TRCPT(value) (USB_HOST_PINTENSET_TRCPT_Msk & ((value) << USB_HOST_PINTENSET_TRCPT_Pos))
+#define USB_HOST_PINTENSET_TRFAIL_Pos 2 /**< \brief (USB_HOST_PINTENSET) Error Flow Interrupt Enable */
+#define USB_HOST_PINTENSET_TRFAIL (0x1ul << USB_HOST_PINTENSET_TRFAIL_Pos)
+#define USB_HOST_PINTENSET_PERR_Pos 3 /**< \brief (USB_HOST_PINTENSET) Pipe Error Interrupt Enable */
+#define USB_HOST_PINTENSET_PERR (0x1ul << USB_HOST_PINTENSET_PERR_Pos)
+#define USB_HOST_PINTENSET_TXSTP_Pos 4 /**< \brief (USB_HOST_PINTENSET) Transmit Setup Interrupt Enable */
+#define USB_HOST_PINTENSET_TXSTP (0x1ul << USB_HOST_PINTENSET_TXSTP_Pos)
+#define USB_HOST_PINTENSET_STALL_Pos 5 /**< \brief (USB_HOST_PINTENSET) Stall Interrupt Enable */
+#define USB_HOST_PINTENSET_STALL (0x1ul << USB_HOST_PINTENSET_STALL_Pos)
+#define USB_HOST_PINTENSET_MASK 0x3Ful /**< \brief (USB_HOST_PINTENSET) MASK Register */
+
+/* -------- USB_DEVICE_ADDR : (USB Offset: 0x000) (R/W 32) DEVICE DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ADDR:32; /*!< bit: 0..31 Adress of data buffer */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} USB_DEVICE_ADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_ADDR_OFFSET 0x000 /**< \brief (USB_DEVICE_ADDR offset) DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer */
+
+#define USB_DEVICE_ADDR_ADDR_Pos 0 /**< \brief (USB_DEVICE_ADDR) Adress of data buffer */
+#define USB_DEVICE_ADDR_ADDR_Msk (0xFFFFFFFFul << USB_DEVICE_ADDR_ADDR_Pos)
+#define USB_DEVICE_ADDR_ADDR(value) (USB_DEVICE_ADDR_ADDR_Msk & ((value) << USB_DEVICE_ADDR_ADDR_Pos))
+#define USB_DEVICE_ADDR_MASK 0xFFFFFFFFul /**< \brief (USB_DEVICE_ADDR) MASK Register */
+
+/* -------- USB_HOST_ADDR : (USB Offset: 0x000) (R/W 32) HOST HOST_DESC_BANK Host Bank, Adress of Data Buffer -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t ADDR:32; /*!< bit: 0..31 Adress of data buffer */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} USB_HOST_ADDR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_ADDR_OFFSET 0x000 /**< \brief (USB_HOST_ADDR offset) HOST_DESC_BANK Host Bank, Adress of Data Buffer */
+
+#define USB_HOST_ADDR_ADDR_Pos 0 /**< \brief (USB_HOST_ADDR) Adress of data buffer */
+#define USB_HOST_ADDR_ADDR_Msk (0xFFFFFFFFul << USB_HOST_ADDR_ADDR_Pos)
+#define USB_HOST_ADDR_ADDR(value) (USB_HOST_ADDR_ADDR_Msk & ((value) << USB_HOST_ADDR_ADDR_Pos))
+#define USB_HOST_ADDR_MASK 0xFFFFFFFFul /**< \brief (USB_HOST_ADDR) MASK Register */
+
+/* -------- USB_DEVICE_PCKSIZE : (USB Offset: 0x004) (R/W 32) DEVICE DEVICE_DESC_BANK Endpoint Bank, Packet Size -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t BYTE_COUNT:14; /*!< bit: 0..13 Byte Count */
+ uint32_t MULTI_PACKET_SIZE:14; /*!< bit: 14..27 Multi Packet In or Out size */
+ uint32_t SIZE:3; /*!< bit: 28..30 Enpoint size */
+ uint32_t AUTO_ZLP:1; /*!< bit: 31 Automatic Zero Length Packet */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} USB_DEVICE_PCKSIZE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_PCKSIZE_OFFSET 0x004 /**< \brief (USB_DEVICE_PCKSIZE offset) DEVICE_DESC_BANK Endpoint Bank, Packet Size */
+
+#define USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos 0 /**< \brief (USB_DEVICE_PCKSIZE) Byte Count */
+#define USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk (0x3FFFul << USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos)
+#define USB_DEVICE_PCKSIZE_BYTE_COUNT(value) (USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk & ((value) << USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos))
+#define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos 14 /**< \brief (USB_DEVICE_PCKSIZE) Multi Packet In or Out size */
+#define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk (0x3FFFul << USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos)
+#define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(value) (USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk & ((value) << USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos))
+#define USB_DEVICE_PCKSIZE_SIZE_Pos 28 /**< \brief (USB_DEVICE_PCKSIZE) Enpoint size */
+#define USB_DEVICE_PCKSIZE_SIZE_Msk (0x7ul << USB_DEVICE_PCKSIZE_SIZE_Pos)
+#define USB_DEVICE_PCKSIZE_SIZE(value) (USB_DEVICE_PCKSIZE_SIZE_Msk & ((value) << USB_DEVICE_PCKSIZE_SIZE_Pos))
+#define USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos 31 /**< \brief (USB_DEVICE_PCKSIZE) Automatic Zero Length Packet */
+#define USB_DEVICE_PCKSIZE_AUTO_ZLP (0x1ul << USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos)
+#define USB_DEVICE_PCKSIZE_MASK 0xFFFFFFFFul /**< \brief (USB_DEVICE_PCKSIZE) MASK Register */
+
+/* -------- USB_HOST_PCKSIZE : (USB Offset: 0x004) (R/W 32) HOST HOST_DESC_BANK Host Bank, Packet Size -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint32_t BYTE_COUNT:14; /*!< bit: 0..13 Byte Count */
+ uint32_t MULTI_PACKET_SIZE:14; /*!< bit: 14..27 Multi Packet In or Out size */
+ uint32_t SIZE:3; /*!< bit: 28..30 Pipe size */
+ uint32_t AUTO_ZLP:1; /*!< bit: 31 Automatic Zero Length Packet */
+ } bit; /*!< Structure used for bit access */
+ uint32_t reg; /*!< Type used for register access */
+} USB_HOST_PCKSIZE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_PCKSIZE_OFFSET 0x004 /**< \brief (USB_HOST_PCKSIZE offset) HOST_DESC_BANK Host Bank, Packet Size */
+
+#define USB_HOST_PCKSIZE_BYTE_COUNT_Pos 0 /**< \brief (USB_HOST_PCKSIZE) Byte Count */
+#define USB_HOST_PCKSIZE_BYTE_COUNT_Msk (0x3FFFul << USB_HOST_PCKSIZE_BYTE_COUNT_Pos)
+#define USB_HOST_PCKSIZE_BYTE_COUNT(value) (USB_HOST_PCKSIZE_BYTE_COUNT_Msk & ((value) << USB_HOST_PCKSIZE_BYTE_COUNT_Pos))
+#define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos 14 /**< \brief (USB_HOST_PCKSIZE) Multi Packet In or Out size */
+#define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk (0x3FFFul << USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos)
+#define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(value) (USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk & ((value) << USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos))
+#define USB_HOST_PCKSIZE_SIZE_Pos 28 /**< \brief (USB_HOST_PCKSIZE) Pipe size */
+#define USB_HOST_PCKSIZE_SIZE_Msk (0x7ul << USB_HOST_PCKSIZE_SIZE_Pos)
+#define USB_HOST_PCKSIZE_SIZE(value) (USB_HOST_PCKSIZE_SIZE_Msk & ((value) << USB_HOST_PCKSIZE_SIZE_Pos))
+#define USB_HOST_PCKSIZE_AUTO_ZLP_Pos 31 /**< \brief (USB_HOST_PCKSIZE) Automatic Zero Length Packet */
+#define USB_HOST_PCKSIZE_AUTO_ZLP (0x1ul << USB_HOST_PCKSIZE_AUTO_ZLP_Pos)
+#define USB_HOST_PCKSIZE_MASK 0xFFFFFFFFul /**< \brief (USB_HOST_PCKSIZE) MASK Register */
+
+/* -------- USB_DEVICE_EXTREG : (USB Offset: 0x008) (R/W 16) DEVICE DEVICE_DESC_BANK Endpoint Bank, Extended -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t SUBPID:4; /*!< bit: 0.. 3 SUBPID field send with extended token */
+ uint16_t VARIABLE:11; /*!< bit: 4..14 Variable field send with extended token */
+ uint16_t :1; /*!< bit: 15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_DEVICE_EXTREG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_EXTREG_OFFSET 0x008 /**< \brief (USB_DEVICE_EXTREG offset) DEVICE_DESC_BANK Endpoint Bank, Extended */
+
+#define USB_DEVICE_EXTREG_SUBPID_Pos 0 /**< \brief (USB_DEVICE_EXTREG) SUBPID field send with extended token */
+#define USB_DEVICE_EXTREG_SUBPID_Msk (0xFul << USB_DEVICE_EXTREG_SUBPID_Pos)
+#define USB_DEVICE_EXTREG_SUBPID(value) (USB_DEVICE_EXTREG_SUBPID_Msk & ((value) << USB_DEVICE_EXTREG_SUBPID_Pos))
+#define USB_DEVICE_EXTREG_VARIABLE_Pos 4 /**< \brief (USB_DEVICE_EXTREG) Variable field send with extended token */
+#define USB_DEVICE_EXTREG_VARIABLE_Msk (0x7FFul << USB_DEVICE_EXTREG_VARIABLE_Pos)
+#define USB_DEVICE_EXTREG_VARIABLE(value) (USB_DEVICE_EXTREG_VARIABLE_Msk & ((value) << USB_DEVICE_EXTREG_VARIABLE_Pos))
+#define USB_DEVICE_EXTREG_MASK 0x7FFFul /**< \brief (USB_DEVICE_EXTREG) MASK Register */
+
+/* -------- USB_HOST_EXTREG : (USB Offset: 0x008) (R/W 16) HOST HOST_DESC_BANK Host Bank, Extended -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t SUBPID:4; /*!< bit: 0.. 3 SUBPID field send with extended token */
+ uint16_t VARIABLE:11; /*!< bit: 4..14 Variable field send with extended token */
+ uint16_t :1; /*!< bit: 15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_HOST_EXTREG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_EXTREG_OFFSET 0x008 /**< \brief (USB_HOST_EXTREG offset) HOST_DESC_BANK Host Bank, Extended */
+
+#define USB_HOST_EXTREG_SUBPID_Pos 0 /**< \brief (USB_HOST_EXTREG) SUBPID field send with extended token */
+#define USB_HOST_EXTREG_SUBPID_Msk (0xFul << USB_HOST_EXTREG_SUBPID_Pos)
+#define USB_HOST_EXTREG_SUBPID(value) (USB_HOST_EXTREG_SUBPID_Msk & ((value) << USB_HOST_EXTREG_SUBPID_Pos))
+#define USB_HOST_EXTREG_VARIABLE_Pos 4 /**< \brief (USB_HOST_EXTREG) Variable field send with extended token */
+#define USB_HOST_EXTREG_VARIABLE_Msk (0x7FFul << USB_HOST_EXTREG_VARIABLE_Pos)
+#define USB_HOST_EXTREG_VARIABLE(value) (USB_HOST_EXTREG_VARIABLE_Msk & ((value) << USB_HOST_EXTREG_VARIABLE_Pos))
+#define USB_HOST_EXTREG_MASK 0x7FFFul /**< \brief (USB_HOST_EXTREG) MASK Register */
+
+/* -------- USB_DEVICE_STATUS_BK : (USB Offset: 0x00A) (R/W 8) DEVICE DEVICE_DESC_BANK Enpoint Bank, Status of Bank -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t CRCERR:1; /*!< bit: 0 CRC Error Status */
+ uint8_t ERRORFLOW:1; /*!< bit: 1 Error Flow Status */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_DEVICE_STATUS_BK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_DEVICE_STATUS_BK_OFFSET 0x00A /**< \brief (USB_DEVICE_STATUS_BK offset) DEVICE_DESC_BANK Enpoint Bank, Status of Bank */
+
+#define USB_DEVICE_STATUS_BK_CRCERR_Pos 0 /**< \brief (USB_DEVICE_STATUS_BK) CRC Error Status */
+#define USB_DEVICE_STATUS_BK_CRCERR (0x1ul << USB_DEVICE_STATUS_BK_CRCERR_Pos)
+#define USB_DEVICE_STATUS_BK_ERRORFLOW_Pos 1 /**< \brief (USB_DEVICE_STATUS_BK) Error Flow Status */
+#define USB_DEVICE_STATUS_BK_ERRORFLOW (0x1ul << USB_DEVICE_STATUS_BK_ERRORFLOW_Pos)
+#define USB_DEVICE_STATUS_BK_MASK 0x03ul /**< \brief (USB_DEVICE_STATUS_BK) MASK Register */
+
+/* -------- USB_HOST_STATUS_BK : (USB Offset: 0x00A) (R/W 8) HOST HOST_DESC_BANK Host Bank, Status of Bank -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t CRCERR:1; /*!< bit: 0 CRC Error Status */
+ uint8_t ERRORFLOW:1; /*!< bit: 1 Error Flow Status */
+ uint8_t :6; /*!< bit: 2.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} USB_HOST_STATUS_BK_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_STATUS_BK_OFFSET 0x00A /**< \brief (USB_HOST_STATUS_BK offset) HOST_DESC_BANK Host Bank, Status of Bank */
+
+#define USB_HOST_STATUS_BK_CRCERR_Pos 0 /**< \brief (USB_HOST_STATUS_BK) CRC Error Status */
+#define USB_HOST_STATUS_BK_CRCERR (0x1ul << USB_HOST_STATUS_BK_CRCERR_Pos)
+#define USB_HOST_STATUS_BK_ERRORFLOW_Pos 1 /**< \brief (USB_HOST_STATUS_BK) Error Flow Status */
+#define USB_HOST_STATUS_BK_ERRORFLOW (0x1ul << USB_HOST_STATUS_BK_ERRORFLOW_Pos)
+#define USB_HOST_STATUS_BK_MASK 0x03ul /**< \brief (USB_HOST_STATUS_BK) MASK Register */
+
+/* -------- USB_HOST_CTRL_PIPE : (USB Offset: 0x00C) (R/W 16) HOST HOST_DESC_BANK Host Bank, Host Control Pipe -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t PDADDR:7; /*!< bit: 0.. 6 Pipe Device Adress */
+ uint16_t :1; /*!< bit: 7 Reserved */
+ uint16_t PEPNUM:4; /*!< bit: 8..11 Pipe Endpoint Number */
+ uint16_t PERMAX:4; /*!< bit: 12..15 Pipe Error Max Number */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_HOST_CTRL_PIPE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_CTRL_PIPE_OFFSET 0x00C /**< \brief (USB_HOST_CTRL_PIPE offset) HOST_DESC_BANK Host Bank, Host Control Pipe */
+#define USB_HOST_CTRL_PIPE_RESETVALUE 0x0000ul /**< \brief (USB_HOST_CTRL_PIPE reset_value) HOST_DESC_BANK Host Bank, Host Control Pipe */
+
+#define USB_HOST_CTRL_PIPE_PDADDR_Pos 0 /**< \brief (USB_HOST_CTRL_PIPE) Pipe Device Adress */
+#define USB_HOST_CTRL_PIPE_PDADDR_Msk (0x7Ful << USB_HOST_CTRL_PIPE_PDADDR_Pos)
+#define USB_HOST_CTRL_PIPE_PDADDR(value) (USB_HOST_CTRL_PIPE_PDADDR_Msk & ((value) << USB_HOST_CTRL_PIPE_PDADDR_Pos))
+#define USB_HOST_CTRL_PIPE_PEPNUM_Pos 8 /**< \brief (USB_HOST_CTRL_PIPE) Pipe Endpoint Number */
+#define USB_HOST_CTRL_PIPE_PEPNUM_Msk (0xFul << USB_HOST_CTRL_PIPE_PEPNUM_Pos)
+#define USB_HOST_CTRL_PIPE_PEPNUM(value) (USB_HOST_CTRL_PIPE_PEPNUM_Msk & ((value) << USB_HOST_CTRL_PIPE_PEPNUM_Pos))
+#define USB_HOST_CTRL_PIPE_PERMAX_Pos 12 /**< \brief (USB_HOST_CTRL_PIPE) Pipe Error Max Number */
+#define USB_HOST_CTRL_PIPE_PERMAX_Msk (0xFul << USB_HOST_CTRL_PIPE_PERMAX_Pos)
+#define USB_HOST_CTRL_PIPE_PERMAX(value) (USB_HOST_CTRL_PIPE_PERMAX_Msk & ((value) << USB_HOST_CTRL_PIPE_PERMAX_Pos))
+#define USB_HOST_CTRL_PIPE_MASK 0xFF7Ful /**< \brief (USB_HOST_CTRL_PIPE) MASK Register */
+
+/* -------- USB_HOST_STATUS_PIPE : (USB Offset: 0x00E) (R/W 16) HOST HOST_DESC_BANK Host Bank, Host Status Pipe -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint16_t DTGLER:1; /*!< bit: 0 Data Toggle Error */
+ uint16_t DAPIDER:1; /*!< bit: 1 Data PID Error */
+ uint16_t PIDER:1; /*!< bit: 2 PID Error */
+ uint16_t TOUTER:1; /*!< bit: 3 Time Out Error */
+ uint16_t CRC16ER:1; /*!< bit: 4 CRC16 Error */
+ uint16_t ERCNT:3; /*!< bit: 5.. 7 Pipe Error Count */
+ uint16_t :8; /*!< bit: 8..15 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint16_t reg; /*!< Type used for register access */
+} USB_HOST_STATUS_PIPE_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define USB_HOST_STATUS_PIPE_OFFSET 0x00E /**< \brief (USB_HOST_STATUS_PIPE offset) HOST_DESC_BANK Host Bank, Host Status Pipe */
+
+#define USB_HOST_STATUS_PIPE_DTGLER_Pos 0 /**< \brief (USB_HOST_STATUS_PIPE) Data Toggle Error */
+#define USB_HOST_STATUS_PIPE_DTGLER (0x1ul << USB_HOST_STATUS_PIPE_DTGLER_Pos)
+#define USB_HOST_STATUS_PIPE_DAPIDER_Pos 1 /**< \brief (USB_HOST_STATUS_PIPE) Data PID Error */
+#define USB_HOST_STATUS_PIPE_DAPIDER (0x1ul << USB_HOST_STATUS_PIPE_DAPIDER_Pos)
+#define USB_HOST_STATUS_PIPE_PIDER_Pos 2 /**< \brief (USB_HOST_STATUS_PIPE) PID Error */
+#define USB_HOST_STATUS_PIPE_PIDER (0x1ul << USB_HOST_STATUS_PIPE_PIDER_Pos)
+#define USB_HOST_STATUS_PIPE_TOUTER_Pos 3 /**< \brief (USB_HOST_STATUS_PIPE) Time Out Error */
+#define USB_HOST_STATUS_PIPE_TOUTER (0x1ul << USB_HOST_STATUS_PIPE_TOUTER_Pos)
+#define USB_HOST_STATUS_PIPE_CRC16ER_Pos 4 /**< \brief (USB_HOST_STATUS_PIPE) CRC16 Error */
+#define USB_HOST_STATUS_PIPE_CRC16ER (0x1ul << USB_HOST_STATUS_PIPE_CRC16ER_Pos)
+#define USB_HOST_STATUS_PIPE_ERCNT_Pos 5 /**< \brief (USB_HOST_STATUS_PIPE) Pipe Error Count */
+#define USB_HOST_STATUS_PIPE_ERCNT_Msk (0x7ul << USB_HOST_STATUS_PIPE_ERCNT_Pos)
+#define USB_HOST_STATUS_PIPE_ERCNT(value) (USB_HOST_STATUS_PIPE_ERCNT_Msk & ((value) << USB_HOST_STATUS_PIPE_ERCNT_Pos))
+#define USB_HOST_STATUS_PIPE_MASK 0x00FFul /**< \brief (USB_HOST_STATUS_PIPE) MASK Register */
+
+/** \brief UsbDeviceDescBank SRAM registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO USB_DEVICE_ADDR_Type ADDR; /**< \brief Offset: 0x000 (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer */
+ __IO USB_DEVICE_PCKSIZE_Type PCKSIZE; /**< \brief Offset: 0x004 (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Packet Size */
+ __IO USB_DEVICE_EXTREG_Type EXTREG; /**< \brief Offset: 0x008 (R/W 16) DEVICE_DESC_BANK Endpoint Bank, Extended */
+ __IO USB_DEVICE_STATUS_BK_Type STATUS_BK; /**< \brief Offset: 0x00A (R/W 8) DEVICE_DESC_BANK Enpoint Bank, Status of Bank */
+ RoReg8 Reserved1[0x5];
+} UsbDeviceDescBank;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief UsbHostDescBank SRAM registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO USB_HOST_ADDR_Type ADDR; /**< \brief Offset: 0x000 (R/W 32) HOST_DESC_BANK Host Bank, Adress of Data Buffer */
+ __IO USB_HOST_PCKSIZE_Type PCKSIZE; /**< \brief Offset: 0x004 (R/W 32) HOST_DESC_BANK Host Bank, Packet Size */
+ __IO USB_HOST_EXTREG_Type EXTREG; /**< \brief Offset: 0x008 (R/W 16) HOST_DESC_BANK Host Bank, Extended */
+ __IO USB_HOST_STATUS_BK_Type STATUS_BK; /**< \brief Offset: 0x00A (R/W 8) HOST_DESC_BANK Host Bank, Status of Bank */
+ RoReg8 Reserved1[0x1];
+ __IO USB_HOST_CTRL_PIPE_Type CTRL_PIPE; /**< \brief Offset: 0x00C (R/W 16) HOST_DESC_BANK Host Bank, Host Control Pipe */
+ __IO USB_HOST_STATUS_PIPE_Type STATUS_PIPE; /**< \brief Offset: 0x00E (R/W 16) HOST_DESC_BANK Host Bank, Host Status Pipe */
+} UsbHostDescBank;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief UsbDeviceEndpoint hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO USB_DEVICE_EPCFG_Type EPCFG; /**< \brief Offset: 0x000 (R/W 8) DEVICE_ENDPOINT End Point Configuration */
+ RoReg8 Reserved1[0x3];
+ __O USB_DEVICE_EPSTATUSCLR_Type EPSTATUSCLR; /**< \brief Offset: 0x004 ( /W 8) DEVICE_ENDPOINT End Point Pipe Status Clear */
+ __O USB_DEVICE_EPSTATUSSET_Type EPSTATUSSET; /**< \brief Offset: 0x005 ( /W 8) DEVICE_ENDPOINT End Point Pipe Status Set */
+ __I USB_DEVICE_EPSTATUS_Type EPSTATUS; /**< \brief Offset: 0x006 (R/ 8) DEVICE_ENDPOINT End Point Pipe Status */
+ __IO USB_DEVICE_EPINTFLAG_Type EPINTFLAG; /**< \brief Offset: 0x007 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Flag */
+ __IO USB_DEVICE_EPINTENCLR_Type EPINTENCLR; /**< \brief Offset: 0x008 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Clear Flag */
+ __IO USB_DEVICE_EPINTENSET_Type EPINTENSET; /**< \brief Offset: 0x009 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Set Flag */
+ RoReg8 Reserved2[0x16];
+} UsbDeviceEndpoint;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief UsbHostPipe hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO USB_HOST_PCFG_Type PCFG; /**< \brief Offset: 0x000 (R/W 8) HOST_PIPE End Point Configuration */
+ RoReg8 Reserved1[0x2];
+ __IO USB_HOST_BINTERVAL_Type BINTERVAL; /**< \brief Offset: 0x003 (R/W 8) HOST_PIPE Bus Access Period of Pipe */
+ __O USB_HOST_PSTATUSCLR_Type PSTATUSCLR; /**< \brief Offset: 0x004 ( /W 8) HOST_PIPE End Point Pipe Status Clear */
+ __O USB_HOST_PSTATUSSET_Type PSTATUSSET; /**< \brief Offset: 0x005 ( /W 8) HOST_PIPE End Point Pipe Status Set */
+ __I USB_HOST_PSTATUS_Type PSTATUS; /**< \brief Offset: 0x006 (R/ 8) HOST_PIPE End Point Pipe Status */
+ __IO USB_HOST_PINTFLAG_Type PINTFLAG; /**< \brief Offset: 0x007 (R/W 8) HOST_PIPE Pipe Interrupt Flag */
+ __IO USB_HOST_PINTENCLR_Type PINTENCLR; /**< \brief Offset: 0x008 (R/W 8) HOST_PIPE Pipe Interrupt Flag Clear */
+ __IO USB_HOST_PINTENSET_Type PINTENSET; /**< \brief Offset: 0x009 (R/W 8) HOST_PIPE Pipe Interrupt Flag Set */
+ RoReg8 Reserved2[0x16];
+} UsbHostPipe;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief USB_DEVICE APB hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* USB is Device */
+ __IO USB_CTRLA_Type CTRLA; /**< \brief Offset: 0x000 (R/W 8) Control A */
+ RoReg8 Reserved1[0x1];
+ __I USB_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x002 (R/ 8) Synchronization Busy */
+ __IO USB_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x003 (R/W 8) USB Quality Of Service */
+ RoReg8 Reserved2[0x4];
+ __IO USB_DEVICE_CTRLB_Type CTRLB; /**< \brief Offset: 0x008 (R/W 16) DEVICE Control B */
+ __IO USB_DEVICE_DADD_Type DADD; /**< \brief Offset: 0x00A (R/W 8) DEVICE Device Address */
+ RoReg8 Reserved3[0x1];
+ __I USB_DEVICE_STATUS_Type STATUS; /**< \brief Offset: 0x00C (R/ 8) DEVICE Status */
+ __I USB_FSMSTATUS_Type FSMSTATUS; /**< \brief Offset: 0x00D (R/ 8) Finite State Machine Status */
+ RoReg8 Reserved4[0x2];
+ __I USB_DEVICE_FNUM_Type FNUM; /**< \brief Offset: 0x010 (R/ 16) DEVICE Device Frame Number */
+ RoReg8 Reserved5[0x2];
+ __IO USB_DEVICE_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x014 (R/W 16) DEVICE Device Interrupt Enable Clear */
+ RoReg8 Reserved6[0x2];
+ __IO USB_DEVICE_INTENSET_Type INTENSET; /**< \brief Offset: 0x018 (R/W 16) DEVICE Device Interrupt Enable Set */
+ RoReg8 Reserved7[0x2];
+ __IO USB_DEVICE_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x01C (R/W 16) DEVICE Device Interrupt Flag */
+ RoReg8 Reserved8[0x2];
+ __I USB_DEVICE_EPINTSMRY_Type EPINTSMRY; /**< \brief Offset: 0x020 (R/ 16) DEVICE End Point Interrupt Summary */
+ RoReg8 Reserved9[0x2];
+ __IO USB_DESCADD_Type DESCADD; /**< \brief Offset: 0x024 (R/W 32) Descriptor Address */
+ __IO USB_PADCAL_Type PADCAL; /**< \brief Offset: 0x028 (R/W 16) USB PAD Calibration */
+ RoReg8 Reserved10[0xD6];
+ UsbDeviceEndpoint DeviceEndpoint[8]; /**< \brief Offset: 0x100 UsbDeviceEndpoint groups [EPT_NUM] */
+} UsbDevice;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief USB_HOST hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* USB is Host */
+ __IO USB_CTRLA_Type CTRLA; /**< \brief Offset: 0x000 (R/W 8) Control A */
+ RoReg8 Reserved1[0x1];
+ __I USB_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x002 (R/ 8) Synchronization Busy */
+ __IO USB_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x003 (R/W 8) USB Quality Of Service */
+ RoReg8 Reserved2[0x4];
+ __IO USB_HOST_CTRLB_Type CTRLB; /**< \brief Offset: 0x008 (R/W 16) HOST Control B */
+ __IO USB_HOST_HSOFC_Type HSOFC; /**< \brief Offset: 0x00A (R/W 8) HOST Host Start Of Frame Control */
+ RoReg8 Reserved3[0x1];
+ __IO USB_HOST_STATUS_Type STATUS; /**< \brief Offset: 0x00C (R/W 8) HOST Status */
+ __I USB_FSMSTATUS_Type FSMSTATUS; /**< \brief Offset: 0x00D (R/ 8) Finite State Machine Status */
+ RoReg8 Reserved4[0x2];
+ __IO USB_HOST_FNUM_Type FNUM; /**< \brief Offset: 0x010 (R/W 16) HOST Host Frame Number */
+ __I USB_HOST_FLENHIGH_Type FLENHIGH; /**< \brief Offset: 0x012 (R/ 8) HOST Host Frame Length */
+ RoReg8 Reserved5[0x1];
+ __IO USB_HOST_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x014 (R/W 16) HOST Host Interrupt Enable Clear */
+ RoReg8 Reserved6[0x2];
+ __IO USB_HOST_INTENSET_Type INTENSET; /**< \brief Offset: 0x018 (R/W 16) HOST Host Interrupt Enable Set */
+ RoReg8 Reserved7[0x2];
+ __IO USB_HOST_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x01C (R/W 16) HOST Host Interrupt Flag */
+ RoReg8 Reserved8[0x2];
+ __I USB_HOST_PINTSMRY_Type PINTSMRY; /**< \brief Offset: 0x020 (R/ 16) HOST Pipe Interrupt Summary */
+ RoReg8 Reserved9[0x2];
+ __IO USB_DESCADD_Type DESCADD; /**< \brief Offset: 0x024 (R/W 32) Descriptor Address */
+ __IO USB_PADCAL_Type PADCAL; /**< \brief Offset: 0x028 (R/W 16) USB PAD Calibration */
+ RoReg8 Reserved10[0xD6];
+ UsbHostPipe HostPipe[8]; /**< \brief Offset: 0x100 UsbHostPipe groups [EPT_NUM*HOST_IMPLEMENTED] */
+} UsbHost;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief USB_DEVICE Descriptor SRAM registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* USB is Device */
+ UsbDeviceDescBank DeviceDescBank[2]; /**< \brief Offset: 0x000 UsbDeviceDescBank groups */
+} UsbDeviceDescriptor;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/** \brief USB_HOST Descriptor SRAM registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct { /* USB is Host */
+ UsbHostDescBank HostDescBank[2]; /**< \brief Offset: 0x000 UsbHostDescBank groups [2*HOST_IMPLEMENTED] */
+} UsbHostDescriptor;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define SECTION_USB_DESCRIPTOR
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ UsbDevice DEVICE; /**< \brief Offset: 0x000 USB is Device */
+ UsbHost HOST; /**< \brief Offset: 0x000 USB is Host */
+} Usb;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_USB_COMPONENT_ */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/component/wdt.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/component/wdt.h
new file mode 100644
index 0000000000000000000000000000000000000000..93c3f164a2fa8a2400a4a872179660fed75b90a7
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/component/wdt.h
@@ -0,0 +1,303 @@
+/**
+ * \file
+ *
+ * \brief Component description for WDT
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_WDT_COMPONENT_
+#define _SAMD21_WDT_COMPONENT_
+
+/* ========================================================================== */
+/** SOFTWARE API DEFINITION FOR WDT */
+/* ========================================================================== */
+/** \addtogroup SAMD21_WDT Watchdog Timer */
+/*@{*/
+
+#define WDT_U2203
+#define REV_WDT 0x200
+
+/* -------- WDT_CTRL : (WDT Offset: 0x0) (R/W 8) Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t :1; /*!< bit: 0 Reserved */
+ uint8_t ENABLE:1; /*!< bit: 1 Enable */
+ uint8_t WEN:1; /*!< bit: 2 Watchdog Timer Window Mode Enable */
+ uint8_t :4; /*!< bit: 3.. 6 Reserved */
+ uint8_t ALWAYSON:1; /*!< bit: 7 Always-On */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} WDT_CTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define WDT_CTRL_OFFSET 0x0 /**< \brief (WDT_CTRL offset) Control */
+#define WDT_CTRL_RESETVALUE 0x00ul /**< \brief (WDT_CTRL reset_value) Control */
+
+#define WDT_CTRL_ENABLE_Pos 1 /**< \brief (WDT_CTRL) Enable */
+#define WDT_CTRL_ENABLE (0x1ul << WDT_CTRL_ENABLE_Pos)
+#define WDT_CTRL_WEN_Pos 2 /**< \brief (WDT_CTRL) Watchdog Timer Window Mode Enable */
+#define WDT_CTRL_WEN (0x1ul << WDT_CTRL_WEN_Pos)
+#define WDT_CTRL_ALWAYSON_Pos 7 /**< \brief (WDT_CTRL) Always-On */
+#define WDT_CTRL_ALWAYSON (0x1ul << WDT_CTRL_ALWAYSON_Pos)
+#define WDT_CTRL_MASK 0x86ul /**< \brief (WDT_CTRL) MASK Register */
+
+/* -------- WDT_CONFIG : (WDT Offset: 0x1) (R/W 8) Configuration -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t PER:4; /*!< bit: 0.. 3 Time-Out Period */
+ uint8_t WINDOW:4; /*!< bit: 4.. 7 Window Mode Time-Out Period */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} WDT_CONFIG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define WDT_CONFIG_OFFSET 0x1 /**< \brief (WDT_CONFIG offset) Configuration */
+#define WDT_CONFIG_RESETVALUE 0xBBul /**< \brief (WDT_CONFIG reset_value) Configuration */
+
+#define WDT_CONFIG_PER_Pos 0 /**< \brief (WDT_CONFIG) Time-Out Period */
+#define WDT_CONFIG_PER_Msk (0xFul << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER(value) (WDT_CONFIG_PER_Msk & ((value) << WDT_CONFIG_PER_Pos))
+#define WDT_CONFIG_PER_8_Val 0x0ul /**< \brief (WDT_CONFIG) 8 clock cycles */
+#define WDT_CONFIG_PER_16_Val 0x1ul /**< \brief (WDT_CONFIG) 16 clock cycles */
+#define WDT_CONFIG_PER_32_Val 0x2ul /**< \brief (WDT_CONFIG) 32 clock cycles */
+#define WDT_CONFIG_PER_64_Val 0x3ul /**< \brief (WDT_CONFIG) 64 clock cycles */
+#define WDT_CONFIG_PER_128_Val 0x4ul /**< \brief (WDT_CONFIG) 128 clock cycles */
+#define WDT_CONFIG_PER_256_Val 0x5ul /**< \brief (WDT_CONFIG) 256 clock cycles */
+#define WDT_CONFIG_PER_512_Val 0x6ul /**< \brief (WDT_CONFIG) 512 clock cycles */
+#define WDT_CONFIG_PER_1K_Val 0x7ul /**< \brief (WDT_CONFIG) 1024 clock cycles */
+#define WDT_CONFIG_PER_2K_Val 0x8ul /**< \brief (WDT_CONFIG) 2048 clock cycles */
+#define WDT_CONFIG_PER_4K_Val 0x9ul /**< \brief (WDT_CONFIG) 4096 clock cycles */
+#define WDT_CONFIG_PER_8K_Val 0xAul /**< \brief (WDT_CONFIG) 8192 clock cycles */
+#define WDT_CONFIG_PER_16K_Val 0xBul /**< \brief (WDT_CONFIG) 16384 clock cycles */
+#define WDT_CONFIG_PER_8 (WDT_CONFIG_PER_8_Val << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_16 (WDT_CONFIG_PER_16_Val << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_32 (WDT_CONFIG_PER_32_Val << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_64 (WDT_CONFIG_PER_64_Val << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_128 (WDT_CONFIG_PER_128_Val << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_256 (WDT_CONFIG_PER_256_Val << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_512 (WDT_CONFIG_PER_512_Val << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_1K (WDT_CONFIG_PER_1K_Val << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_2K (WDT_CONFIG_PER_2K_Val << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_4K (WDT_CONFIG_PER_4K_Val << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_8K (WDT_CONFIG_PER_8K_Val << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_PER_16K (WDT_CONFIG_PER_16K_Val << WDT_CONFIG_PER_Pos)
+#define WDT_CONFIG_WINDOW_Pos 4 /**< \brief (WDT_CONFIG) Window Mode Time-Out Period */
+#define WDT_CONFIG_WINDOW_Msk (0xFul << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW(value) (WDT_CONFIG_WINDOW_Msk & ((value) << WDT_CONFIG_WINDOW_Pos))
+#define WDT_CONFIG_WINDOW_8_Val 0x0ul /**< \brief (WDT_CONFIG) 8 clock cycles */
+#define WDT_CONFIG_WINDOW_16_Val 0x1ul /**< \brief (WDT_CONFIG) 16 clock cycles */
+#define WDT_CONFIG_WINDOW_32_Val 0x2ul /**< \brief (WDT_CONFIG) 32 clock cycles */
+#define WDT_CONFIG_WINDOW_64_Val 0x3ul /**< \brief (WDT_CONFIG) 64 clock cycles */
+#define WDT_CONFIG_WINDOW_128_Val 0x4ul /**< \brief (WDT_CONFIG) 128 clock cycles */
+#define WDT_CONFIG_WINDOW_256_Val 0x5ul /**< \brief (WDT_CONFIG) 256 clock cycles */
+#define WDT_CONFIG_WINDOW_512_Val 0x6ul /**< \brief (WDT_CONFIG) 512 clock cycles */
+#define WDT_CONFIG_WINDOW_1K_Val 0x7ul /**< \brief (WDT_CONFIG) 1024 clock cycles */
+#define WDT_CONFIG_WINDOW_2K_Val 0x8ul /**< \brief (WDT_CONFIG) 2048 clock cycles */
+#define WDT_CONFIG_WINDOW_4K_Val 0x9ul /**< \brief (WDT_CONFIG) 4096 clock cycles */
+#define WDT_CONFIG_WINDOW_8K_Val 0xAul /**< \brief (WDT_CONFIG) 8192 clock cycles */
+#define WDT_CONFIG_WINDOW_16K_Val 0xBul /**< \brief (WDT_CONFIG) 16384 clock cycles */
+#define WDT_CONFIG_WINDOW_8 (WDT_CONFIG_WINDOW_8_Val << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_16 (WDT_CONFIG_WINDOW_16_Val << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_32 (WDT_CONFIG_WINDOW_32_Val << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_64 (WDT_CONFIG_WINDOW_64_Val << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_128 (WDT_CONFIG_WINDOW_128_Val << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_256 (WDT_CONFIG_WINDOW_256_Val << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_512 (WDT_CONFIG_WINDOW_512_Val << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_1K (WDT_CONFIG_WINDOW_1K_Val << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_2K (WDT_CONFIG_WINDOW_2K_Val << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_4K (WDT_CONFIG_WINDOW_4K_Val << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_8K (WDT_CONFIG_WINDOW_8K_Val << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_WINDOW_16K (WDT_CONFIG_WINDOW_16K_Val << WDT_CONFIG_WINDOW_Pos)
+#define WDT_CONFIG_MASK 0xFFul /**< \brief (WDT_CONFIG) MASK Register */
+
+/* -------- WDT_EWCTRL : (WDT Offset: 0x2) (R/W 8) Early Warning Interrupt Control -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t EWOFFSET:4; /*!< bit: 0.. 3 Early Warning Interrupt Time Offset */
+ uint8_t :4; /*!< bit: 4.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} WDT_EWCTRL_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define WDT_EWCTRL_OFFSET 0x2 /**< \brief (WDT_EWCTRL offset) Early Warning Interrupt Control */
+#define WDT_EWCTRL_RESETVALUE 0x0Bul /**< \brief (WDT_EWCTRL reset_value) Early Warning Interrupt Control */
+
+#define WDT_EWCTRL_EWOFFSET_Pos 0 /**< \brief (WDT_EWCTRL) Early Warning Interrupt Time Offset */
+#define WDT_EWCTRL_EWOFFSET_Msk (0xFul << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET(value) (WDT_EWCTRL_EWOFFSET_Msk & ((value) << WDT_EWCTRL_EWOFFSET_Pos))
+#define WDT_EWCTRL_EWOFFSET_8_Val 0x0ul /**< \brief (WDT_EWCTRL) 8 clock cycles */
+#define WDT_EWCTRL_EWOFFSET_16_Val 0x1ul /**< \brief (WDT_EWCTRL) 16 clock cycles */
+#define WDT_EWCTRL_EWOFFSET_32_Val 0x2ul /**< \brief (WDT_EWCTRL) 32 clock cycles */
+#define WDT_EWCTRL_EWOFFSET_64_Val 0x3ul /**< \brief (WDT_EWCTRL) 64 clock cycles */
+#define WDT_EWCTRL_EWOFFSET_128_Val 0x4ul /**< \brief (WDT_EWCTRL) 128 clock cycles */
+#define WDT_EWCTRL_EWOFFSET_256_Val 0x5ul /**< \brief (WDT_EWCTRL) 256 clock cycles */
+#define WDT_EWCTRL_EWOFFSET_512_Val 0x6ul /**< \brief (WDT_EWCTRL) 512 clock cycles */
+#define WDT_EWCTRL_EWOFFSET_1K_Val 0x7ul /**< \brief (WDT_EWCTRL) 1024 clock cycles */
+#define WDT_EWCTRL_EWOFFSET_2K_Val 0x8ul /**< \brief (WDT_EWCTRL) 2048 clock cycles */
+#define WDT_EWCTRL_EWOFFSET_4K_Val 0x9ul /**< \brief (WDT_EWCTRL) 4096 clock cycles */
+#define WDT_EWCTRL_EWOFFSET_8K_Val 0xAul /**< \brief (WDT_EWCTRL) 8192 clock cycles */
+#define WDT_EWCTRL_EWOFFSET_16K_Val 0xBul /**< \brief (WDT_EWCTRL) 16384 clock cycles */
+#define WDT_EWCTRL_EWOFFSET_8 (WDT_EWCTRL_EWOFFSET_8_Val << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_16 (WDT_EWCTRL_EWOFFSET_16_Val << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_32 (WDT_EWCTRL_EWOFFSET_32_Val << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_64 (WDT_EWCTRL_EWOFFSET_64_Val << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_128 (WDT_EWCTRL_EWOFFSET_128_Val << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_256 (WDT_EWCTRL_EWOFFSET_256_Val << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_512 (WDT_EWCTRL_EWOFFSET_512_Val << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_1K (WDT_EWCTRL_EWOFFSET_1K_Val << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_2K (WDT_EWCTRL_EWOFFSET_2K_Val << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_4K (WDT_EWCTRL_EWOFFSET_4K_Val << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_8K (WDT_EWCTRL_EWOFFSET_8K_Val << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_EWOFFSET_16K (WDT_EWCTRL_EWOFFSET_16K_Val << WDT_EWCTRL_EWOFFSET_Pos)
+#define WDT_EWCTRL_MASK 0x0Ful /**< \brief (WDT_EWCTRL) MASK Register */
+
+/* -------- WDT_INTENCLR : (WDT Offset: 0x4) (R/W 8) Interrupt Enable Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} WDT_INTENCLR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define WDT_INTENCLR_OFFSET 0x4 /**< \brief (WDT_INTENCLR offset) Interrupt Enable Clear */
+#define WDT_INTENCLR_RESETVALUE 0x00ul /**< \brief (WDT_INTENCLR reset_value) Interrupt Enable Clear */
+
+#define WDT_INTENCLR_EW_Pos 0 /**< \brief (WDT_INTENCLR) Early Warning Interrupt Enable */
+#define WDT_INTENCLR_EW (0x1ul << WDT_INTENCLR_EW_Pos)
+#define WDT_INTENCLR_MASK 0x01ul /**< \brief (WDT_INTENCLR) MASK Register */
+
+/* -------- WDT_INTENSET : (WDT Offset: 0x5) (R/W 8) Interrupt Enable Set -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */
+ uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} WDT_INTENSET_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define WDT_INTENSET_OFFSET 0x5 /**< \brief (WDT_INTENSET offset) Interrupt Enable Set */
+#define WDT_INTENSET_RESETVALUE 0x00ul /**< \brief (WDT_INTENSET reset_value) Interrupt Enable Set */
+
+#define WDT_INTENSET_EW_Pos 0 /**< \brief (WDT_INTENSET) Early Warning Interrupt Enable */
+#define WDT_INTENSET_EW (0x1ul << WDT_INTENSET_EW_Pos)
+#define WDT_INTENSET_MASK 0x01ul /**< \brief (WDT_INTENSET) MASK Register */
+
+/* -------- WDT_INTFLAG : (WDT Offset: 0x6) (R/W 8) Interrupt Flag Status and Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union { // __I to avoid read-modify-write on write-to-clear register
+ struct {
+ __I uint8_t EW:1; /*!< bit: 0 Early Warning */
+ __I uint8_t :7; /*!< bit: 1.. 7 Reserved */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} WDT_INTFLAG_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define WDT_INTFLAG_OFFSET 0x6 /**< \brief (WDT_INTFLAG offset) Interrupt Flag Status and Clear */
+#define WDT_INTFLAG_RESETVALUE 0x00ul /**< \brief (WDT_INTFLAG reset_value) Interrupt Flag Status and Clear */
+
+#define WDT_INTFLAG_EW_Pos 0 /**< \brief (WDT_INTFLAG) Early Warning */
+#define WDT_INTFLAG_EW (0x1ul << WDT_INTFLAG_EW_Pos)
+#define WDT_INTFLAG_MASK 0x01ul /**< \brief (WDT_INTFLAG) MASK Register */
+
+/* -------- WDT_STATUS : (WDT Offset: 0x7) (R/ 8) Status -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t :7; /*!< bit: 0.. 6 Reserved */
+ uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} WDT_STATUS_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define WDT_STATUS_OFFSET 0x7 /**< \brief (WDT_STATUS offset) Status */
+#define WDT_STATUS_RESETVALUE 0x00ul /**< \brief (WDT_STATUS reset_value) Status */
+
+#define WDT_STATUS_SYNCBUSY_Pos 7 /**< \brief (WDT_STATUS) Synchronization Busy */
+#define WDT_STATUS_SYNCBUSY (0x1ul << WDT_STATUS_SYNCBUSY_Pos)
+#define WDT_STATUS_MASK 0x80ul /**< \brief (WDT_STATUS) MASK Register */
+
+/* -------- WDT_CLEAR : (WDT Offset: 0x8) ( /W 8) Clear -------- */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef union {
+ struct {
+ uint8_t CLEAR:8; /*!< bit: 0.. 7 Watchdog Clear */
+ } bit; /*!< Structure used for bit access */
+ uint8_t reg; /*!< Type used for register access */
+} WDT_CLEAR_Type;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+#define WDT_CLEAR_OFFSET 0x8 /**< \brief (WDT_CLEAR offset) Clear */
+#define WDT_CLEAR_RESETVALUE 0x00ul /**< \brief (WDT_CLEAR reset_value) Clear */
+
+#define WDT_CLEAR_CLEAR_Pos 0 /**< \brief (WDT_CLEAR) Watchdog Clear */
+#define WDT_CLEAR_CLEAR_Msk (0xFFul << WDT_CLEAR_CLEAR_Pos)
+#define WDT_CLEAR_CLEAR(value) (WDT_CLEAR_CLEAR_Msk & ((value) << WDT_CLEAR_CLEAR_Pos))
+#define WDT_CLEAR_CLEAR_KEY_Val 0xA5ul /**< \brief (WDT_CLEAR) Clear Key */
+#define WDT_CLEAR_CLEAR_KEY (WDT_CLEAR_CLEAR_KEY_Val << WDT_CLEAR_CLEAR_Pos)
+#define WDT_CLEAR_MASK 0xFFul /**< \brief (WDT_CLEAR) MASK Register */
+
+/** \brief WDT hardware registers */
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+typedef struct {
+ __IO WDT_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */
+ __IO WDT_CONFIG_Type CONFIG; /**< \brief Offset: 0x1 (R/W 8) Configuration */
+ __IO WDT_EWCTRL_Type EWCTRL; /**< \brief Offset: 0x2 (R/W 8) Early Warning Interrupt Control */
+ RoReg8 Reserved1[0x1];
+ __IO WDT_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x4 (R/W 8) Interrupt Enable Clear */
+ __IO WDT_INTENSET_Type INTENSET; /**< \brief Offset: 0x5 (R/W 8) Interrupt Enable Set */
+ __IO WDT_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x6 (R/W 8) Interrupt Flag Status and Clear */
+ __I WDT_STATUS_Type STATUS; /**< \brief Offset: 0x7 (R/ 8) Status */
+ __O WDT_CLEAR_Type CLEAR; /**< \brief Offset: 0x8 ( /W 8) Clear */
+} Wdt;
+#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/*@}*/
+
+#endif /* _SAMD21_WDT_COMPONENT_ */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/ac.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/ac.h
new file mode 100644
index 0000000000000000000000000000000000000000..7aa9f58e82317bf3a9991aae008e743f8896dff1
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/ac.h
@@ -0,0 +1,87 @@
+/**
+ * \file
+ *
+ * \brief Instance description for AC
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_AC_INSTANCE_
+#define _SAMD21_AC_INSTANCE_
+
+/* ========== Register definition for AC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_AC_CTRLA (0x42004400U) /**< \brief (AC) Control A */
+#define REG_AC_CTRLB (0x42004401U) /**< \brief (AC) Control B */
+#define REG_AC_EVCTRL (0x42004402U) /**< \brief (AC) Event Control */
+#define REG_AC_INTENCLR (0x42004404U) /**< \brief (AC) Interrupt Enable Clear */
+#define REG_AC_INTENSET (0x42004405U) /**< \brief (AC) Interrupt Enable Set */
+#define REG_AC_INTFLAG (0x42004406U) /**< \brief (AC) Interrupt Flag Status and Clear */
+#define REG_AC_STATUSA (0x42004408U) /**< \brief (AC) Status A */
+#define REG_AC_STATUSB (0x42004409U) /**< \brief (AC) Status B */
+#define REG_AC_STATUSC (0x4200440AU) /**< \brief (AC) Status C */
+#define REG_AC_WINCTRL (0x4200440CU) /**< \brief (AC) Window Control */
+#define REG_AC_COMPCTRL0 (0x42004410U) /**< \brief (AC) Comparator Control 0 */
+#define REG_AC_COMPCTRL1 (0x42004414U) /**< \brief (AC) Comparator Control 1 */
+#define REG_AC_SCALER0 (0x42004420U) /**< \brief (AC) Scaler 0 */
+#define REG_AC_SCALER1 (0x42004421U) /**< \brief (AC) Scaler 1 */
+#else
+#define REG_AC_CTRLA (*(RwReg8 *)0x42004400U) /**< \brief (AC) Control A */
+#define REG_AC_CTRLB (*(WoReg8 *)0x42004401U) /**< \brief (AC) Control B */
+#define REG_AC_EVCTRL (*(RwReg16*)0x42004402U) /**< \brief (AC) Event Control */
+#define REG_AC_INTENCLR (*(RwReg8 *)0x42004404U) /**< \brief (AC) Interrupt Enable Clear */
+#define REG_AC_INTENSET (*(RwReg8 *)0x42004405U) /**< \brief (AC) Interrupt Enable Set */
+#define REG_AC_INTFLAG (*(RwReg8 *)0x42004406U) /**< \brief (AC) Interrupt Flag Status and Clear */
+#define REG_AC_STATUSA (*(RoReg8 *)0x42004408U) /**< \brief (AC) Status A */
+#define REG_AC_STATUSB (*(RoReg8 *)0x42004409U) /**< \brief (AC) Status B */
+#define REG_AC_STATUSC (*(RoReg8 *)0x4200440AU) /**< \brief (AC) Status C */
+#define REG_AC_WINCTRL (*(RwReg8 *)0x4200440CU) /**< \brief (AC) Window Control */
+#define REG_AC_COMPCTRL0 (*(RwReg *)0x42004410U) /**< \brief (AC) Comparator Control 0 */
+#define REG_AC_COMPCTRL1 (*(RwReg *)0x42004414U) /**< \brief (AC) Comparator Control 1 */
+#define REG_AC_SCALER0 (*(RwReg8 *)0x42004420U) /**< \brief (AC) Scaler 0 */
+#define REG_AC_SCALER1 (*(RwReg8 *)0x42004421U) /**< \brief (AC) Scaler 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for AC peripheral ========== */
+#define AC_CMP_NUM 2 // Number of comparators
+#define AC_GCLK_ID_ANA 32 // Index of Generic Clock for analog
+#define AC_GCLK_ID_DIG 31 // Index of Generic Clock for digital
+#define AC_NUM_CMP 2
+#define AC_PAIRS 1 // Number of pairs of comparators
+
+#endif /* _SAMD21_AC_INSTANCE_ */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/adc.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/adc.h
new file mode 100644
index 0000000000000000000000000000000000000000..af5ed823d6f5d145c40bb0c9d8115ca490c28e3b
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/adc.h
@@ -0,0 +1,99 @@
+/**
+ * \file
+ *
+ * \brief Instance description for ADC
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_ADC_INSTANCE_
+#define _SAMD21_ADC_INSTANCE_
+
+/* ========== Register definition for ADC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_ADC_CTRLA (0x42004000U) /**< \brief (ADC) Control A */
+#define REG_ADC_REFCTRL (0x42004001U) /**< \brief (ADC) Reference Control */
+#define REG_ADC_AVGCTRL (0x42004002U) /**< \brief (ADC) Average Control */
+#define REG_ADC_SAMPCTRL (0x42004003U) /**< \brief (ADC) Sampling Time Control */
+#define REG_ADC_CTRLB (0x42004004U) /**< \brief (ADC) Control B */
+#define REG_ADC_WINCTRL (0x42004008U) /**< \brief (ADC) Window Monitor Control */
+#define REG_ADC_SWTRIG (0x4200400CU) /**< \brief (ADC) Software Trigger */
+#define REG_ADC_INPUTCTRL (0x42004010U) /**< \brief (ADC) Input Control */
+#define REG_ADC_EVCTRL (0x42004014U) /**< \brief (ADC) Event Control */
+#define REG_ADC_INTENCLR (0x42004016U) /**< \brief (ADC) Interrupt Enable Clear */
+#define REG_ADC_INTENSET (0x42004017U) /**< \brief (ADC) Interrupt Enable Set */
+#define REG_ADC_INTFLAG (0x42004018U) /**< \brief (ADC) Interrupt Flag Status and Clear */
+#define REG_ADC_STATUS (0x42004019U) /**< \brief (ADC) Status */
+#define REG_ADC_RESULT (0x4200401AU) /**< \brief (ADC) Result */
+#define REG_ADC_WINLT (0x4200401CU) /**< \brief (ADC) Window Monitor Lower Threshold */
+#define REG_ADC_WINUT (0x42004020U) /**< \brief (ADC) Window Monitor Upper Threshold */
+#define REG_ADC_GAINCORR (0x42004024U) /**< \brief (ADC) Gain Correction */
+#define REG_ADC_OFFSETCORR (0x42004026U) /**< \brief (ADC) Offset Correction */
+#define REG_ADC_CALIB (0x42004028U) /**< \brief (ADC) Calibration */
+#define REG_ADC_DBGCTRL (0x4200402AU) /**< \brief (ADC) Debug Control */
+#else
+#define REG_ADC_CTRLA (*(RwReg8 *)0x42004000U) /**< \brief (ADC) Control A */
+#define REG_ADC_REFCTRL (*(RwReg8 *)0x42004001U) /**< \brief (ADC) Reference Control */
+#define REG_ADC_AVGCTRL (*(RwReg8 *)0x42004002U) /**< \brief (ADC) Average Control */
+#define REG_ADC_SAMPCTRL (*(RwReg8 *)0x42004003U) /**< \brief (ADC) Sampling Time Control */
+#define REG_ADC_CTRLB (*(RwReg16*)0x42004004U) /**< \brief (ADC) Control B */
+#define REG_ADC_WINCTRL (*(RwReg8 *)0x42004008U) /**< \brief (ADC) Window Monitor Control */
+#define REG_ADC_SWTRIG (*(RwReg8 *)0x4200400CU) /**< \brief (ADC) Software Trigger */
+#define REG_ADC_INPUTCTRL (*(RwReg *)0x42004010U) /**< \brief (ADC) Input Control */
+#define REG_ADC_EVCTRL (*(RwReg8 *)0x42004014U) /**< \brief (ADC) Event Control */
+#define REG_ADC_INTENCLR (*(RwReg8 *)0x42004016U) /**< \brief (ADC) Interrupt Enable Clear */
+#define REG_ADC_INTENSET (*(RwReg8 *)0x42004017U) /**< \brief (ADC) Interrupt Enable Set */
+#define REG_ADC_INTFLAG (*(RwReg8 *)0x42004018U) /**< \brief (ADC) Interrupt Flag Status and Clear */
+#define REG_ADC_STATUS (*(RoReg8 *)0x42004019U) /**< \brief (ADC) Status */
+#define REG_ADC_RESULT (*(RoReg16*)0x4200401AU) /**< \brief (ADC) Result */
+#define REG_ADC_WINLT (*(RwReg16*)0x4200401CU) /**< \brief (ADC) Window Monitor Lower Threshold */
+#define REG_ADC_WINUT (*(RwReg16*)0x42004020U) /**< \brief (ADC) Window Monitor Upper Threshold */
+#define REG_ADC_GAINCORR (*(RwReg16*)0x42004024U) /**< \brief (ADC) Gain Correction */
+#define REG_ADC_OFFSETCORR (*(RwReg16*)0x42004026U) /**< \brief (ADC) Offset Correction */
+#define REG_ADC_CALIB (*(RwReg16*)0x42004028U) /**< \brief (ADC) Calibration */
+#define REG_ADC_DBGCTRL (*(RwReg8 *)0x4200402AU) /**< \brief (ADC) Debug Control */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for ADC peripheral ========== */
+#define ADC_DMAC_ID_RESRDY 39 // Index of DMA RESRDY trigger
+#define ADC_EXTCHANNEL_MSB 19 // Number of external channels
+#define ADC_GCLK_ID 30 // Index of Generic Clock
+#define ADC_RESULT_BITS 16 // Size of RESULT.RESULT bitfield
+#define ADC_RESULT_MSB 15 // Size of Result
+
+#endif /* _SAMD21_ADC_INSTANCE_ */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/dac.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/dac.h
new file mode 100644
index 0000000000000000000000000000000000000000..930646c12e9cd2e867a8a8bdf3136fafbc06f0f8
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/dac.h
@@ -0,0 +1,74 @@
+/**
+ * \file
+ *
+ * \brief Instance description for DAC
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_DAC_INSTANCE_
+#define _SAMD21_DAC_INSTANCE_
+
+/* ========== Register definition for DAC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_DAC_CTRLA (0x42004800U) /**< \brief (DAC) Control A */
+#define REG_DAC_CTRLB (0x42004801U) /**< \brief (DAC) Control B */
+#define REG_DAC_EVCTRL (0x42004802U) /**< \brief (DAC) Event Control */
+#define REG_DAC_INTENCLR (0x42004804U) /**< \brief (DAC) Interrupt Enable Clear */
+#define REG_DAC_INTENSET (0x42004805U) /**< \brief (DAC) Interrupt Enable Set */
+#define REG_DAC_INTFLAG (0x42004806U) /**< \brief (DAC) Interrupt Flag Status and Clear */
+#define REG_DAC_STATUS (0x42004807U) /**< \brief (DAC) Status */
+#define REG_DAC_DATA (0x42004808U) /**< \brief (DAC) Data */
+#define REG_DAC_DATABUF (0x4200480CU) /**< \brief (DAC) Data Buffer */
+#else
+#define REG_DAC_CTRLA (*(RwReg8 *)0x42004800U) /**< \brief (DAC) Control A */
+#define REG_DAC_CTRLB (*(RwReg8 *)0x42004801U) /**< \brief (DAC) Control B */
+#define REG_DAC_EVCTRL (*(RwReg8 *)0x42004802U) /**< \brief (DAC) Event Control */
+#define REG_DAC_INTENCLR (*(RwReg8 *)0x42004804U) /**< \brief (DAC) Interrupt Enable Clear */
+#define REG_DAC_INTENSET (*(RwReg8 *)0x42004805U) /**< \brief (DAC) Interrupt Enable Set */
+#define REG_DAC_INTFLAG (*(RwReg8 *)0x42004806U) /**< \brief (DAC) Interrupt Flag Status and Clear */
+#define REG_DAC_STATUS (*(RoReg8 *)0x42004807U) /**< \brief (DAC) Status */
+#define REG_DAC_DATA (*(RwReg16*)0x42004808U) /**< \brief (DAC) Data */
+#define REG_DAC_DATABUF (*(RwReg16*)0x4200480CU) /**< \brief (DAC) Data Buffer */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for DAC peripheral ========== */
+#define DAC_DMAC_ID_EMPTY 40 // Index of DMAC EMPTY trigger
+#define DAC_GCLK_ID 33 // Index of Generic Clock
+
+#endif /* _SAMD21_DAC_INSTANCE_ */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/dmac.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/dmac.h
new file mode 100644
index 0000000000000000000000000000000000000000..68527b226b402d0a89214fcc84a99f037e02e1da
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/dmac.h
@@ -0,0 +1,109 @@
+/**
+ * \file
+ *
+ * \brief Instance description for DMAC
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_DMAC_INSTANCE_
+#define _SAMD21_DMAC_INSTANCE_
+
+/* ========== Register definition for DMAC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_DMAC_CTRL (0x41004800U) /**< \brief (DMAC) Control */
+#define REG_DMAC_CRCCTRL (0x41004802U) /**< \brief (DMAC) CRC Control */
+#define REG_DMAC_CRCDATAIN (0x41004804U) /**< \brief (DMAC) CRC Data Input */
+#define REG_DMAC_CRCCHKSUM (0x41004808U) /**< \brief (DMAC) CRC Checksum */
+#define REG_DMAC_CRCSTATUS (0x4100480CU) /**< \brief (DMAC) CRC Status */
+#define REG_DMAC_DBGCTRL (0x4100480DU) /**< \brief (DMAC) Debug Control */
+#define REG_DMAC_QOSCTRL (0x4100480EU) /**< \brief (DMAC) QOS Control */
+#define REG_DMAC_SWTRIGCTRL (0x41004810U) /**< \brief (DMAC) Software Trigger Control */
+#define REG_DMAC_PRICTRL0 (0x41004814U) /**< \brief (DMAC) Priority Control 0 */
+#define REG_DMAC_INTPEND (0x41004820U) /**< \brief (DMAC) Interrupt Pending */
+#define REG_DMAC_INTSTATUS (0x41004824U) /**< \brief (DMAC) Interrupt Status */
+#define REG_DMAC_BUSYCH (0x41004828U) /**< \brief (DMAC) Busy Channels */
+#define REG_DMAC_PENDCH (0x4100482CU) /**< \brief (DMAC) Pending Channels */
+#define REG_DMAC_ACTIVE (0x41004830U) /**< \brief (DMAC) Active Channel and Levels */
+#define REG_DMAC_BASEADDR (0x41004834U) /**< \brief (DMAC) Descriptor Memory Section Base Address */
+#define REG_DMAC_WRBADDR (0x41004838U) /**< \brief (DMAC) Write-Back Memory Section Base Address */
+#define REG_DMAC_CHID (0x4100483FU) /**< \brief (DMAC) Channel ID */
+#define REG_DMAC_CHCTRLA (0x41004840U) /**< \brief (DMAC) Channel Control A */
+#define REG_DMAC_CHCTRLB (0x41004844U) /**< \brief (DMAC) Channel Control B */
+#define REG_DMAC_CHINTENCLR (0x4100484CU) /**< \brief (DMAC) Channel Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET (0x4100484DU) /**< \brief (DMAC) Channel Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG (0x4100484EU) /**< \brief (DMAC) Channel Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS (0x4100484FU) /**< \brief (DMAC) Channel Status */
+#else
+#define REG_DMAC_CTRL (*(RwReg16*)0x41004800U) /**< \brief (DMAC) Control */
+#define REG_DMAC_CRCCTRL (*(RwReg16*)0x41004802U) /**< \brief (DMAC) CRC Control */
+#define REG_DMAC_CRCDATAIN (*(RwReg *)0x41004804U) /**< \brief (DMAC) CRC Data Input */
+#define REG_DMAC_CRCCHKSUM (*(RwReg *)0x41004808U) /**< \brief (DMAC) CRC Checksum */
+#define REG_DMAC_CRCSTATUS (*(RwReg8 *)0x4100480CU) /**< \brief (DMAC) CRC Status */
+#define REG_DMAC_DBGCTRL (*(RwReg8 *)0x4100480DU) /**< \brief (DMAC) Debug Control */
+#define REG_DMAC_QOSCTRL (*(RwReg8 *)0x4100480EU) /**< \brief (DMAC) QOS Control */
+#define REG_DMAC_SWTRIGCTRL (*(RwReg *)0x41004810U) /**< \brief (DMAC) Software Trigger Control */
+#define REG_DMAC_PRICTRL0 (*(RwReg *)0x41004814U) /**< \brief (DMAC) Priority Control 0 */
+#define REG_DMAC_INTPEND (*(RwReg16*)0x41004820U) /**< \brief (DMAC) Interrupt Pending */
+#define REG_DMAC_INTSTATUS (*(RoReg *)0x41004824U) /**< \brief (DMAC) Interrupt Status */
+#define REG_DMAC_BUSYCH (*(RoReg *)0x41004828U) /**< \brief (DMAC) Busy Channels */
+#define REG_DMAC_PENDCH (*(RoReg *)0x4100482CU) /**< \brief (DMAC) Pending Channels */
+#define REG_DMAC_ACTIVE (*(RoReg *)0x41004830U) /**< \brief (DMAC) Active Channel and Levels */
+#define REG_DMAC_BASEADDR (*(RwReg *)0x41004834U) /**< \brief (DMAC) Descriptor Memory Section Base Address */
+#define REG_DMAC_WRBADDR (*(RwReg *)0x41004838U) /**< \brief (DMAC) Write-Back Memory Section Base Address */
+#define REG_DMAC_CHID (*(RwReg8 *)0x4100483FU) /**< \brief (DMAC) Channel ID */
+#define REG_DMAC_CHCTRLA (*(RwReg8 *)0x41004840U) /**< \brief (DMAC) Channel Control A */
+#define REG_DMAC_CHCTRLB (*(RwReg *)0x41004844U) /**< \brief (DMAC) Channel Control B */
+#define REG_DMAC_CHINTENCLR (*(RwReg8 *)0x4100484CU) /**< \brief (DMAC) Channel Interrupt Enable Clear */
+#define REG_DMAC_CHINTENSET (*(RwReg8 *)0x4100484DU) /**< \brief (DMAC) Channel Interrupt Enable Set */
+#define REG_DMAC_CHINTFLAG (*(RwReg8 *)0x4100484EU) /**< \brief (DMAC) Channel Interrupt Flag Status and Clear */
+#define REG_DMAC_CHSTATUS (*(RoReg8 *)0x4100484FU) /**< \brief (DMAC) Channel Status */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for DMAC peripheral ========== */
+#define DMAC_CH_BITS 4 // Number of bits to select channel
+#define DMAC_CH_NUM 12 // Number of channels
+#define DMAC_CLK_AHB_ID 5 // AHB clock index
+#define DMAC_EVIN_NUM 4 // Number of input events
+#define DMAC_EVOUT_NUM 4 // Number of output events
+#define DMAC_LVL_BITS 2 // Number of bit to select level priority
+#define DMAC_LVL_NUM 4 // Enable priority level number
+#define DMAC_TRIG_BITS 6 // Number of bits to select trigger source
+#define DMAC_TRIG_NUM 45 // Number of peripheral triggers
+
+#endif /* _SAMD21_DMAC_INSTANCE_ */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/dsu.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/dsu.h
new file mode 100644
index 0000000000000000000000000000000000000000..8ca1088548af0a2193f521f9402d0be0ea0a66fc
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/dsu.h
@@ -0,0 +1,99 @@
+/**
+ * \file
+ *
+ * \brief Instance description for DSU
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_DSU_INSTANCE_
+#define _SAMD21_DSU_INSTANCE_
+
+/* ========== Register definition for DSU peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_DSU_CTRL (0x41002000U) /**< \brief (DSU) Control */
+#define REG_DSU_STATUSA (0x41002001U) /**< \brief (DSU) Status A */
+#define REG_DSU_STATUSB (0x41002002U) /**< \brief (DSU) Status B */
+#define REG_DSU_ADDR (0x41002004U) /**< \brief (DSU) Address */
+#define REG_DSU_LENGTH (0x41002008U) /**< \brief (DSU) Length */
+#define REG_DSU_DATA (0x4100200CU) /**< \brief (DSU) Data */
+#define REG_DSU_DCC0 (0x41002010U) /**< \brief (DSU) Debug Communication Channel 0 */
+#define REG_DSU_DCC1 (0x41002014U) /**< \brief (DSU) Debug Communication Channel 1 */
+#define REG_DSU_DID (0x41002018U) /**< \brief (DSU) Device Identification */
+#define REG_DSU_ENTRY0 (0x41003000U) /**< \brief (DSU) Coresight ROM Table Entry 0 */
+#define REG_DSU_ENTRY1 (0x41003004U) /**< \brief (DSU) Coresight ROM Table Entry 1 */
+#define REG_DSU_END (0x41003008U) /**< \brief (DSU) Coresight ROM Table End */
+#define REG_DSU_MEMTYPE (0x41003FCCU) /**< \brief (DSU) Coresight ROM Table Memory Type */
+#define REG_DSU_PID4 (0x41003FD0U) /**< \brief (DSU) Peripheral Identification 4 */
+#define REG_DSU_PID0 (0x41003FE0U) /**< \brief (DSU) Peripheral Identification 0 */
+#define REG_DSU_PID1 (0x41003FE4U) /**< \brief (DSU) Peripheral Identification 1 */
+#define REG_DSU_PID2 (0x41003FE8U) /**< \brief (DSU) Peripheral Identification 2 */
+#define REG_DSU_PID3 (0x41003FECU) /**< \brief (DSU) Peripheral Identification 3 */
+#define REG_DSU_CID0 (0x41003FF0U) /**< \brief (DSU) Component Identification 0 */
+#define REG_DSU_CID1 (0x41003FF4U) /**< \brief (DSU) Component Identification 1 */
+#define REG_DSU_CID2 (0x41003FF8U) /**< \brief (DSU) Component Identification 2 */
+#define REG_DSU_CID3 (0x41003FFCU) /**< \brief (DSU) Component Identification 3 */
+#else
+#define REG_DSU_CTRL (*(WoReg8 *)0x41002000U) /**< \brief (DSU) Control */
+#define REG_DSU_STATUSA (*(RwReg8 *)0x41002001U) /**< \brief (DSU) Status A */
+#define REG_DSU_STATUSB (*(RoReg8 *)0x41002002U) /**< \brief (DSU) Status B */
+#define REG_DSU_ADDR (*(RwReg *)0x41002004U) /**< \brief (DSU) Address */
+#define REG_DSU_LENGTH (*(RwReg *)0x41002008U) /**< \brief (DSU) Length */
+#define REG_DSU_DATA (*(RwReg *)0x4100200CU) /**< \brief (DSU) Data */
+#define REG_DSU_DCC0 (*(RwReg *)0x41002010U) /**< \brief (DSU) Debug Communication Channel 0 */
+#define REG_DSU_DCC1 (*(RwReg *)0x41002014U) /**< \brief (DSU) Debug Communication Channel 1 */
+#define REG_DSU_DID (*(RoReg *)0x41002018U) /**< \brief (DSU) Device Identification */
+#define REG_DSU_ENTRY0 (*(RoReg *)0x41003000U) /**< \brief (DSU) Coresight ROM Table Entry 0 */
+#define REG_DSU_ENTRY1 (*(RoReg *)0x41003004U) /**< \brief (DSU) Coresight ROM Table Entry 1 */
+#define REG_DSU_END (*(RoReg *)0x41003008U) /**< \brief (DSU) Coresight ROM Table End */
+#define REG_DSU_MEMTYPE (*(RoReg *)0x41003FCCU) /**< \brief (DSU) Coresight ROM Table Memory Type */
+#define REG_DSU_PID4 (*(RoReg *)0x41003FD0U) /**< \brief (DSU) Peripheral Identification 4 */
+#define REG_DSU_PID0 (*(RoReg *)0x41003FE0U) /**< \brief (DSU) Peripheral Identification 0 */
+#define REG_DSU_PID1 (*(RoReg *)0x41003FE4U) /**< \brief (DSU) Peripheral Identification 1 */
+#define REG_DSU_PID2 (*(RoReg *)0x41003FE8U) /**< \brief (DSU) Peripheral Identification 2 */
+#define REG_DSU_PID3 (*(RoReg *)0x41003FECU) /**< \brief (DSU) Peripheral Identification 3 */
+#define REG_DSU_CID0 (*(RoReg *)0x41003FF0U) /**< \brief (DSU) Component Identification 0 */
+#define REG_DSU_CID1 (*(RoReg *)0x41003FF4U) /**< \brief (DSU) Component Identification 1 */
+#define REG_DSU_CID2 (*(RoReg *)0x41003FF8U) /**< \brief (DSU) Component Identification 2 */
+#define REG_DSU_CID3 (*(RoReg *)0x41003FFCU) /**< \brief (DSU) Component Identification 3 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for DSU peripheral ========== */
+#define DSU_CLK_HSB_ID 3 // Index of AHB clock in PM.AHBMASK register
+
+#endif /* _SAMD21_DSU_INSTANCE_ */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/eic.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/eic.h
new file mode 100644
index 0000000000000000000000000000000000000000..c2423823155a43226975c1fbf3bc146a41fb0f88
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/eic.h
@@ -0,0 +1,78 @@
+/**
+ * \file
+ *
+ * \brief Instance description for EIC
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_EIC_INSTANCE_
+#define _SAMD21_EIC_INSTANCE_
+
+/* ========== Register definition for EIC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_EIC_CTRL (0x40001800U) /**< \brief (EIC) Control */
+#define REG_EIC_STATUS (0x40001801U) /**< \brief (EIC) Status */
+#define REG_EIC_NMICTRL (0x40001802U) /**< \brief (EIC) Non-Maskable Interrupt Control */
+#define REG_EIC_NMIFLAG (0x40001803U) /**< \brief (EIC) Non-Maskable Interrupt Flag Status and Clear */
+#define REG_EIC_EVCTRL (0x40001804U) /**< \brief (EIC) Event Control */
+#define REG_EIC_INTENCLR (0x40001808U) /**< \brief (EIC) Interrupt Enable Clear */
+#define REG_EIC_INTENSET (0x4000180CU) /**< \brief (EIC) Interrupt Enable Set */
+#define REG_EIC_INTFLAG (0x40001810U) /**< \brief (EIC) Interrupt Flag Status and Clear */
+#define REG_EIC_WAKEUP (0x40001814U) /**< \brief (EIC) Wake-Up Enable */
+#define REG_EIC_CONFIG0 (0x40001818U) /**< \brief (EIC) Configuration 0 */
+#define REG_EIC_CONFIG1 (0x4000181CU) /**< \brief (EIC) Configuration 1 */
+#else
+#define REG_EIC_CTRL (*(RwReg8 *)0x40001800U) /**< \brief (EIC) Control */
+#define REG_EIC_STATUS (*(RoReg8 *)0x40001801U) /**< \brief (EIC) Status */
+#define REG_EIC_NMICTRL (*(RwReg8 *)0x40001802U) /**< \brief (EIC) Non-Maskable Interrupt Control */
+#define REG_EIC_NMIFLAG (*(RwReg8 *)0x40001803U) /**< \brief (EIC) Non-Maskable Interrupt Flag Status and Clear */
+#define REG_EIC_EVCTRL (*(RwReg *)0x40001804U) /**< \brief (EIC) Event Control */
+#define REG_EIC_INTENCLR (*(RwReg *)0x40001808U) /**< \brief (EIC) Interrupt Enable Clear */
+#define REG_EIC_INTENSET (*(RwReg *)0x4000180CU) /**< \brief (EIC) Interrupt Enable Set */
+#define REG_EIC_INTFLAG (*(RwReg *)0x40001810U) /**< \brief (EIC) Interrupt Flag Status and Clear */
+#define REG_EIC_WAKEUP (*(RwReg *)0x40001814U) /**< \brief (EIC) Wake-Up Enable */
+#define REG_EIC_CONFIG0 (*(RwReg *)0x40001818U) /**< \brief (EIC) Configuration 0 */
+#define REG_EIC_CONFIG1 (*(RwReg *)0x4000181CU) /**< \brief (EIC) Configuration 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for EIC peripheral ========== */
+#define EIC_CONFIG_NUM 2 // Number of CONFIG registers
+#define EIC_GCLK_ID 5 // Index of Generic Clock
+
+#endif /* _SAMD21_EIC_INSTANCE_ */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/evsys.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/evsys.h
new file mode 100644
index 0000000000000000000000000000000000000000..c7a2d51b40a67379ed23c8d9d27821c07392c2bc
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/evsys.h
@@ -0,0 +1,197 @@
+/**
+ * \file
+ *
+ * \brief Instance description for EVSYS
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_EVSYS_INSTANCE_
+#define _SAMD21_EVSYS_INSTANCE_
+
+/* ========== Register definition for EVSYS peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_EVSYS_CTRL (0x42000400U) /**< \brief (EVSYS) Control */
+#define REG_EVSYS_CHANNEL (0x42000404U) /**< \brief (EVSYS) Channel */
+#define REG_EVSYS_USER (0x42000408U) /**< \brief (EVSYS) User Multiplexer */
+#define REG_EVSYS_CHSTATUS (0x4200040CU) /**< \brief (EVSYS) Channel Status */
+#define REG_EVSYS_INTENCLR (0x42000410U) /**< \brief (EVSYS) Interrupt Enable Clear */
+#define REG_EVSYS_INTENSET (0x42000414U) /**< \brief (EVSYS) Interrupt Enable Set */
+#define REG_EVSYS_INTFLAG (0x42000418U) /**< \brief (EVSYS) Interrupt Flag Status and Clear */
+#else
+#define REG_EVSYS_CTRL (*(WoReg8 *)0x42000400U) /**< \brief (EVSYS) Control */
+#define REG_EVSYS_CHANNEL (*(RwReg *)0x42000404U) /**< \brief (EVSYS) Channel */
+#define REG_EVSYS_USER (*(RwReg16*)0x42000408U) /**< \brief (EVSYS) User Multiplexer */
+#define REG_EVSYS_CHSTATUS (*(RoReg *)0x4200040CU) /**< \brief (EVSYS) Channel Status */
+#define REG_EVSYS_INTENCLR (*(RwReg *)0x42000410U) /**< \brief (EVSYS) Interrupt Enable Clear */
+#define REG_EVSYS_INTENSET (*(RwReg *)0x42000414U) /**< \brief (EVSYS) Interrupt Enable Set */
+#define REG_EVSYS_INTFLAG (*(RwReg *)0x42000418U) /**< \brief (EVSYS) Interrupt Flag Status and Clear */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for EVSYS peripheral ========== */
+#define EVSYS_CHANNELS 12 // Number of Channels
+#define EVSYS_CHANNELS_BITS 4 // Number of bits to select Channel
+#define EVSYS_CHANNELS_MSB 11 // Number of Channels - 1
+#define EVSYS_EXTEVT_NUM 0 // Number of External Event Generators
+#define EVSYS_GCLK_ID_0 7
+#define EVSYS_GCLK_ID_1 8
+#define EVSYS_GCLK_ID_2 9
+#define EVSYS_GCLK_ID_3 10
+#define EVSYS_GCLK_ID_4 11
+#define EVSYS_GCLK_ID_5 12
+#define EVSYS_GCLK_ID_6 13
+#define EVSYS_GCLK_ID_7 14
+#define EVSYS_GCLK_ID_8 15
+#define EVSYS_GCLK_ID_9 16
+#define EVSYS_GCLK_ID_10 17
+#define EVSYS_GCLK_ID_11 18
+#define EVSYS_GCLK_ID_LSB 7
+#define EVSYS_GCLK_ID_MSB 18
+#define EVSYS_GCLK_ID_SIZE 12
+#define EVSYS_GENERATORS 73 // Total Number of Event Generators
+#define EVSYS_GENERATORS_BITS 7 // Number of bits to select Event Generator
+#define EVSYS_USERS 29 // Total Number of Event Users
+#define EVSYS_USERS_BITS 5 // Number of bits to select Event User
+
+// GENERATORS
+#define EVSYS_ID_GEN_RTC_CMP_0 1
+#define EVSYS_ID_GEN_RTC_CMP_1 2
+#define EVSYS_ID_GEN_RTC_OVF 3
+#define EVSYS_ID_GEN_RTC_PER_0 4
+#define EVSYS_ID_GEN_RTC_PER_1 5
+#define EVSYS_ID_GEN_RTC_PER_2 6
+#define EVSYS_ID_GEN_RTC_PER_3 7
+#define EVSYS_ID_GEN_RTC_PER_4 8
+#define EVSYS_ID_GEN_RTC_PER_5 9
+#define EVSYS_ID_GEN_RTC_PER_6 10
+#define EVSYS_ID_GEN_RTC_PER_7 11
+#define EVSYS_ID_GEN_EIC_EXTINT_0 12
+#define EVSYS_ID_GEN_EIC_EXTINT_1 13
+#define EVSYS_ID_GEN_EIC_EXTINT_2 14
+#define EVSYS_ID_GEN_EIC_EXTINT_3 15
+#define EVSYS_ID_GEN_EIC_EXTINT_4 16
+#define EVSYS_ID_GEN_EIC_EXTINT_5 17
+#define EVSYS_ID_GEN_EIC_EXTINT_6 18
+#define EVSYS_ID_GEN_EIC_EXTINT_7 19
+#define EVSYS_ID_GEN_EIC_EXTINT_8 20
+#define EVSYS_ID_GEN_EIC_EXTINT_9 21
+#define EVSYS_ID_GEN_EIC_EXTINT_10 22
+#define EVSYS_ID_GEN_EIC_EXTINT_11 23
+#define EVSYS_ID_GEN_EIC_EXTINT_12 24
+#define EVSYS_ID_GEN_EIC_EXTINT_13 25
+#define EVSYS_ID_GEN_EIC_EXTINT_14 26
+#define EVSYS_ID_GEN_EIC_EXTINT_15 27
+#define EVSYS_ID_GEN_EIC_EXTINT_16 28
+#define EVSYS_ID_GEN_EIC_EXTINT_17 29
+#define EVSYS_ID_GEN_DMAC_CH_0 30
+#define EVSYS_ID_GEN_DMAC_CH_1 31
+#define EVSYS_ID_GEN_DMAC_CH_2 32
+#define EVSYS_ID_GEN_DMAC_CH_3 33
+#define EVSYS_ID_GEN_TCC0_OVF 34
+#define EVSYS_ID_GEN_TCC0_TRG 35
+#define EVSYS_ID_GEN_TCC0_CNT 36
+#define EVSYS_ID_GEN_TCC0_MCX_0 37
+#define EVSYS_ID_GEN_TCC0_MCX_1 38
+#define EVSYS_ID_GEN_TCC0_MCX_2 39
+#define EVSYS_ID_GEN_TCC0_MCX_3 40
+#define EVSYS_ID_GEN_TCC1_OVF 41
+#define EVSYS_ID_GEN_TCC1_TRG 42
+#define EVSYS_ID_GEN_TCC1_CNT 43
+#define EVSYS_ID_GEN_TCC1_MCX_0 44
+#define EVSYS_ID_GEN_TCC1_MCX_1 45
+#define EVSYS_ID_GEN_TCC2_OVF 46
+#define EVSYS_ID_GEN_TCC2_TRG 47
+#define EVSYS_ID_GEN_TCC2_CNT 48
+#define EVSYS_ID_GEN_TCC2_MCX_0 49
+#define EVSYS_ID_GEN_TCC2_MCX_1 50
+#define EVSYS_ID_GEN_TC3_OVF 51
+#define EVSYS_ID_GEN_TC3_MCX_0 52
+#define EVSYS_ID_GEN_TC3_MCX_1 53
+#define EVSYS_ID_GEN_TC4_OVF 54
+#define EVSYS_ID_GEN_TC4_MCX_0 55
+#define EVSYS_ID_GEN_TC4_MCX_1 56
+#define EVSYS_ID_GEN_TC5_OVF 57
+#define EVSYS_ID_GEN_TC5_MCX_0 58
+#define EVSYS_ID_GEN_TC5_MCX_1 59
+#define EVSYS_ID_GEN_TC6_OVF 60
+#define EVSYS_ID_GEN_TC6_MCX_0 61
+#define EVSYS_ID_GEN_TC6_MCX_1 62
+#define EVSYS_ID_GEN_TC7_OVF 63
+#define EVSYS_ID_GEN_TC7_MCX_0 64
+#define EVSYS_ID_GEN_TC7_MCX_1 65
+#define EVSYS_ID_GEN_ADC_RESRDY 66
+#define EVSYS_ID_GEN_ADC_WINMON 67
+#define EVSYS_ID_GEN_AC_COMP_0 68
+#define EVSYS_ID_GEN_AC_COMP_1 69
+#define EVSYS_ID_GEN_AC_WIN_0 70
+#define EVSYS_ID_GEN_DAC_EMPTY 71
+#define EVSYS_ID_GEN_PTC_EOC 72
+#define EVSYS_ID_GEN_PTC_WCOMP 73
+
+// USERS
+#define EVSYS_ID_USER_DMAC_CH_0 0
+#define EVSYS_ID_USER_DMAC_CH_1 1
+#define EVSYS_ID_USER_DMAC_CH_2 2
+#define EVSYS_ID_USER_DMAC_CH_3 3
+#define EVSYS_ID_USER_TCC0_EV_0 4
+#define EVSYS_ID_USER_TCC0_EV_1 5
+#define EVSYS_ID_USER_TCC0_MC_0 6
+#define EVSYS_ID_USER_TCC0_MC_1 7
+#define EVSYS_ID_USER_TCC0_MC_2 8
+#define EVSYS_ID_USER_TCC0_MC_3 9
+#define EVSYS_ID_USER_TCC1_EV_0 10
+#define EVSYS_ID_USER_TCC1_EV_1 11
+#define EVSYS_ID_USER_TCC1_MC_0 12
+#define EVSYS_ID_USER_TCC1_MC_1 13
+#define EVSYS_ID_USER_TCC2_EV_0 14
+#define EVSYS_ID_USER_TCC2_EV_1 15
+#define EVSYS_ID_USER_TCC2_MC_0 16
+#define EVSYS_ID_USER_TCC2_MC_1 17
+#define EVSYS_ID_USER_TC3_EVU 18
+#define EVSYS_ID_USER_TC4_EVU 19
+#define EVSYS_ID_USER_TC5_EVU 20
+#define EVSYS_ID_USER_TC6_EVU 21
+#define EVSYS_ID_USER_TC7_EVU 22
+#define EVSYS_ID_USER_ADC_START 23
+#define EVSYS_ID_USER_ADC_SYNC 24
+#define EVSYS_ID_USER_AC_SOC_0 25
+#define EVSYS_ID_USER_AC_SOC_1 26
+#define EVSYS_ID_USER_DAC_START 27
+#define EVSYS_ID_USER_PTC_STCONV 28
+
+#endif /* _SAMD21_EVSYS_INSTANCE_ */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/gclk.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/gclk.h
new file mode 100644
index 0000000000000000000000000000000000000000..01befb280e085e6d851e61a052f51d8f8095c268
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/gclk.h
@@ -0,0 +1,79 @@
+/**
+ * \file
+ *
+ * \brief Instance description for GCLK
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_GCLK_INSTANCE_
+#define _SAMD21_GCLK_INSTANCE_
+
+/* ========== Register definition for GCLK peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_GCLK_CTRL (0x40000C00U) /**< \brief (GCLK) Control */
+#define REG_GCLK_STATUS (0x40000C01U) /**< \brief (GCLK) Status */
+#define REG_GCLK_CLKCTRL (0x40000C02U) /**< \brief (GCLK) Generic Clock Control */
+#define REG_GCLK_GENCTRL (0x40000C04U) /**< \brief (GCLK) Generic Clock Generator Control */
+#define REG_GCLK_GENDIV (0x40000C08U) /**< \brief (GCLK) Generic Clock Generator Division */
+#else
+#define REG_GCLK_CTRL (*(RwReg8 *)0x40000C00U) /**< \brief (GCLK) Control */
+#define REG_GCLK_STATUS (*(RoReg8 *)0x40000C01U) /**< \brief (GCLK) Status */
+#define REG_GCLK_CLKCTRL (*(RwReg16*)0x40000C02U) /**< \brief (GCLK) Generic Clock Control */
+#define REG_GCLK_GENCTRL (*(RwReg *)0x40000C04U) /**< \brief (GCLK) Generic Clock Generator Control */
+#define REG_GCLK_GENDIV (*(RwReg *)0x40000C08U) /**< \brief (GCLK) Generic Clock Generator Division */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for GCLK peripheral ========== */
+#define GCLK_GENDIV_BITS 16
+#define GCLK_GEN_NUM 9 // Number of Generic Clock Generators
+#define GCLK_GEN_NUM_MSB 8 // Number of Generic Clock Generators - 1
+#define GCLK_GEN_SOURCE_NUM_MSB 8 // Number of Generic Clock Sources - 1
+#define GCLK_NUM 37 // Number of Generic Clock Users
+#define GCLK_SOURCE_DFLL48M 7
+#define GCLK_SOURCE_FDPLL 8
+#define GCLK_SOURCE_GCLKGEN1 2
+#define GCLK_SOURCE_GCLKIN 1
+#define GCLK_SOURCE_NUM 9 // Number of Generic Clock Sources
+#define GCLK_SOURCE_OSCULP32K 3
+#define GCLK_SOURCE_OSC8M 6
+#define GCLK_SOURCE_OSC32K 4
+#define GCLK_SOURCE_XOSC 0
+#define GCLK_SOURCE_XOSC32K 5
+
+#endif /* _SAMD21_GCLK_INSTANCE_ */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/i2s.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/i2s.h
new file mode 100644
index 0000000000000000000000000000000000000000..36ddb88706c7535b1f950b15b029ae7c26f05640
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/i2s.h
@@ -0,0 +1,94 @@
+/**
+ * \file
+ *
+ * \brief Instance description for I2S
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_I2S_INSTANCE_
+#define _SAMD21_I2S_INSTANCE_
+
+/* ========== Register definition for I2S peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_I2S_CTRLA (0x42005000U) /**< \brief (I2S) Control A */
+#define REG_I2S_CLKCTRL0 (0x42005004U) /**< \brief (I2S) Clock Unit 0 Control */
+#define REG_I2S_CLKCTRL1 (0x42005008U) /**< \brief (I2S) Clock Unit 1 Control */
+#define REG_I2S_INTENCLR (0x4200500CU) /**< \brief (I2S) Interrupt Enable Clear */
+#define REG_I2S_INTENSET (0x42005010U) /**< \brief (I2S) Interrupt Enable Set */
+#define REG_I2S_INTFLAG (0x42005014U) /**< \brief (I2S) Interrupt Flag Status and Clear */
+#define REG_I2S_SYNCBUSY (0x42005018U) /**< \brief (I2S) Synchronization Status */
+#define REG_I2S_SERCTRL0 (0x42005020U) /**< \brief (I2S) Serializer 0 Control */
+#define REG_I2S_SERCTRL1 (0x42005024U) /**< \brief (I2S) Serializer 1 Control */
+#define REG_I2S_DATA0 (0x42005030U) /**< \brief (I2S) Data 0 */
+#define REG_I2S_DATA1 (0x42005034U) /**< \brief (I2S) Data 1 */
+#else
+#define REG_I2S_CTRLA (*(RwReg8 *)0x42005000U) /**< \brief (I2S) Control A */
+#define REG_I2S_CLKCTRL0 (*(RwReg *)0x42005004U) /**< \brief (I2S) Clock Unit 0 Control */
+#define REG_I2S_CLKCTRL1 (*(RwReg *)0x42005008U) /**< \brief (I2S) Clock Unit 1 Control */
+#define REG_I2S_INTENCLR (*(RwReg16*)0x4200500CU) /**< \brief (I2S) Interrupt Enable Clear */
+#define REG_I2S_INTENSET (*(RwReg16*)0x42005010U) /**< \brief (I2S) Interrupt Enable Set */
+#define REG_I2S_INTFLAG (*(RwReg16*)0x42005014U) /**< \brief (I2S) Interrupt Flag Status and Clear */
+#define REG_I2S_SYNCBUSY (*(RoReg16*)0x42005018U) /**< \brief (I2S) Synchronization Status */
+#define REG_I2S_SERCTRL0 (*(RwReg *)0x42005020U) /**< \brief (I2S) Serializer 0 Control */
+#define REG_I2S_SERCTRL1 (*(RwReg *)0x42005024U) /**< \brief (I2S) Serializer 1 Control */
+#define REG_I2S_DATA0 (*(RwReg *)0x42005030U) /**< \brief (I2S) Data 0 */
+#define REG_I2S_DATA1 (*(RwReg *)0x42005034U) /**< \brief (I2S) Data 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for I2S peripheral ========== */
+#define I2S_CLK_NUM 2 // Number of clock units
+#define I2S_DMAC_ID_RX_0 41
+#define I2S_DMAC_ID_RX_1 42
+#define I2S_DMAC_ID_RX_LSB 41
+#define I2S_DMAC_ID_RX_MSB 42
+#define I2S_DMAC_ID_RX_SIZE 2
+#define I2S_DMAC_ID_TX_0 43
+#define I2S_DMAC_ID_TX_1 44
+#define I2S_DMAC_ID_TX_LSB 43
+#define I2S_DMAC_ID_TX_MSB 44
+#define I2S_DMAC_ID_TX_SIZE 2
+#define I2S_GCLK_ID_0 35
+#define I2S_GCLK_ID_1 36
+#define I2S_GCLK_ID_LSB 35
+#define I2S_GCLK_ID_MSB 36
+#define I2S_GCLK_ID_SIZE 2
+#define I2S_MAX_SLOTS 8 // Max number of data slots in frame
+#define I2S_SER_NUM 2 // Number of serializers
+
+#endif /* _SAMD21_I2S_INSTANCE_ */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/mtb.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/mtb.h
new file mode 100644
index 0000000000000000000000000000000000000000..ff9a0cfd76af110933574fe63d52f6db89b76738
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/mtb.h
@@ -0,0 +1,103 @@
+/**
+ * \file
+ *
+ * \brief Instance description for MTB
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_MTB_INSTANCE_
+#define _SAMD21_MTB_INSTANCE_
+
+/* ========== Register definition for MTB peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_MTB_POSITION (0x41006000U) /**< \brief (MTB) MTB Position */
+#define REG_MTB_MASTER (0x41006004U) /**< \brief (MTB) MTB Master */
+#define REG_MTB_FLOW (0x41006008U) /**< \brief (MTB) MTB Flow */
+#define REG_MTB_BASE (0x4100600CU) /**< \brief (MTB) MTB Base */
+#define REG_MTB_ITCTRL (0x41006F00U) /**< \brief (MTB) MTB Integration Mode Control */
+#define REG_MTB_CLAIMSET (0x41006FA0U) /**< \brief (MTB) MTB Claim Set */
+#define REG_MTB_CLAIMCLR (0x41006FA4U) /**< \brief (MTB) MTB Claim Clear */
+#define REG_MTB_LOCKACCESS (0x41006FB0U) /**< \brief (MTB) MTB Lock Access */
+#define REG_MTB_LOCKSTATUS (0x41006FB4U) /**< \brief (MTB) MTB Lock Status */
+#define REG_MTB_AUTHSTATUS (0x41006FB8U) /**< \brief (MTB) MTB Authentication Status */
+#define REG_MTB_DEVARCH (0x41006FBCU) /**< \brief (MTB) MTB Device Architecture */
+#define REG_MTB_DEVID (0x41006FC8U) /**< \brief (MTB) MTB Device Configuration */
+#define REG_MTB_DEVTYPE (0x41006FCCU) /**< \brief (MTB) MTB Device Type */
+#define REG_MTB_PID4 (0x41006FD0U) /**< \brief (MTB) CoreSight */
+#define REG_MTB_PID5 (0x41006FD4U) /**< \brief (MTB) CoreSight */
+#define REG_MTB_PID6 (0x41006FD8U) /**< \brief (MTB) CoreSight */
+#define REG_MTB_PID7 (0x41006FDCU) /**< \brief (MTB) CoreSight */
+#define REG_MTB_PID0 (0x41006FE0U) /**< \brief (MTB) CoreSight */
+#define REG_MTB_PID1 (0x41006FE4U) /**< \brief (MTB) CoreSight */
+#define REG_MTB_PID2 (0x41006FE8U) /**< \brief (MTB) CoreSight */
+#define REG_MTB_PID3 (0x41006FECU) /**< \brief (MTB) CoreSight */
+#define REG_MTB_CID0 (0x41006FF0U) /**< \brief (MTB) CoreSight */
+#define REG_MTB_CID1 (0x41006FF4U) /**< \brief (MTB) CoreSight */
+#define REG_MTB_CID2 (0x41006FF8U) /**< \brief (MTB) CoreSight */
+#define REG_MTB_CID3 (0x41006FFCU) /**< \brief (MTB) CoreSight */
+#else
+#define REG_MTB_POSITION (*(RwReg *)0x41006000U) /**< \brief (MTB) MTB Position */
+#define REG_MTB_MASTER (*(RwReg *)0x41006004U) /**< \brief (MTB) MTB Master */
+#define REG_MTB_FLOW (*(RwReg *)0x41006008U) /**< \brief (MTB) MTB Flow */
+#define REG_MTB_BASE (*(RoReg *)0x4100600CU) /**< \brief (MTB) MTB Base */
+#define REG_MTB_ITCTRL (*(RwReg *)0x41006F00U) /**< \brief (MTB) MTB Integration Mode Control */
+#define REG_MTB_CLAIMSET (*(RwReg *)0x41006FA0U) /**< \brief (MTB) MTB Claim Set */
+#define REG_MTB_CLAIMCLR (*(RwReg *)0x41006FA4U) /**< \brief (MTB) MTB Claim Clear */
+#define REG_MTB_LOCKACCESS (*(RwReg *)0x41006FB0U) /**< \brief (MTB) MTB Lock Access */
+#define REG_MTB_LOCKSTATUS (*(RoReg *)0x41006FB4U) /**< \brief (MTB) MTB Lock Status */
+#define REG_MTB_AUTHSTATUS (*(RoReg *)0x41006FB8U) /**< \brief (MTB) MTB Authentication Status */
+#define REG_MTB_DEVARCH (*(RoReg *)0x41006FBCU) /**< \brief (MTB) MTB Device Architecture */
+#define REG_MTB_DEVID (*(RoReg *)0x41006FC8U) /**< \brief (MTB) MTB Device Configuration */
+#define REG_MTB_DEVTYPE (*(RoReg *)0x41006FCCU) /**< \brief (MTB) MTB Device Type */
+#define REG_MTB_PID4 (*(RoReg *)0x41006FD0U) /**< \brief (MTB) CoreSight */
+#define REG_MTB_PID5 (*(RoReg *)0x41006FD4U) /**< \brief (MTB) CoreSight */
+#define REG_MTB_PID6 (*(RoReg *)0x41006FD8U) /**< \brief (MTB) CoreSight */
+#define REG_MTB_PID7 (*(RoReg *)0x41006FDCU) /**< \brief (MTB) CoreSight */
+#define REG_MTB_PID0 (*(RoReg *)0x41006FE0U) /**< \brief (MTB) CoreSight */
+#define REG_MTB_PID1 (*(RoReg *)0x41006FE4U) /**< \brief (MTB) CoreSight */
+#define REG_MTB_PID2 (*(RoReg *)0x41006FE8U) /**< \brief (MTB) CoreSight */
+#define REG_MTB_PID3 (*(RoReg *)0x41006FECU) /**< \brief (MTB) CoreSight */
+#define REG_MTB_CID0 (*(RoReg *)0x41006FF0U) /**< \brief (MTB) CoreSight */
+#define REG_MTB_CID1 (*(RoReg *)0x41006FF4U) /**< \brief (MTB) CoreSight */
+#define REG_MTB_CID2 (*(RoReg *)0x41006FF8U) /**< \brief (MTB) CoreSight */
+#define REG_MTB_CID3 (*(RoReg *)0x41006FFCU) /**< \brief (MTB) CoreSight */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+
+#endif /* _SAMD21_MTB_INSTANCE_ */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/nvmctrl.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/nvmctrl.h
new file mode 100644
index 0000000000000000000000000000000000000000..6005e484b1f0c94460e4e45d2d254c78fc234f3c
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/nvmctrl.h
@@ -0,0 +1,91 @@
+/**
+ * \file
+ *
+ * \brief Instance description for NVMCTRL
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_NVMCTRL_INSTANCE_
+#define _SAMD21_NVMCTRL_INSTANCE_
+
+/* ========== Register definition for NVMCTRL peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_NVMCTRL_CTRLA (0x41004000U) /**< \brief (NVMCTRL) Control A */
+#define REG_NVMCTRL_CTRLB (0x41004004U) /**< \brief (NVMCTRL) Control B */
+#define REG_NVMCTRL_PARAM (0x41004008U) /**< \brief (NVMCTRL) NVM Parameter */
+#define REG_NVMCTRL_INTENCLR (0x4100400CU) /**< \brief (NVMCTRL) Interrupt Enable Clear */
+#define REG_NVMCTRL_INTENSET (0x41004010U) /**< \brief (NVMCTRL) Interrupt Enable Set */
+#define REG_NVMCTRL_INTFLAG (0x41004014U) /**< \brief (NVMCTRL) Interrupt Flag Status and Clear */
+#define REG_NVMCTRL_STATUS (0x41004018U) /**< \brief (NVMCTRL) Status */
+#define REG_NVMCTRL_ADDR (0x4100401CU) /**< \brief (NVMCTRL) Address */
+#define REG_NVMCTRL_LOCK (0x41004020U) /**< \brief (NVMCTRL) Lock Section */
+#else
+#define REG_NVMCTRL_CTRLA (*(RwReg16*)0x41004000U) /**< \brief (NVMCTRL) Control A */
+#define REG_NVMCTRL_CTRLB (*(RwReg *)0x41004004U) /**< \brief (NVMCTRL) Control B */
+#define REG_NVMCTRL_PARAM (*(RwReg *)0x41004008U) /**< \brief (NVMCTRL) NVM Parameter */
+#define REG_NVMCTRL_INTENCLR (*(RwReg8 *)0x4100400CU) /**< \brief (NVMCTRL) Interrupt Enable Clear */
+#define REG_NVMCTRL_INTENSET (*(RwReg8 *)0x41004010U) /**< \brief (NVMCTRL) Interrupt Enable Set */
+#define REG_NVMCTRL_INTFLAG (*(RwReg8 *)0x41004014U) /**< \brief (NVMCTRL) Interrupt Flag Status and Clear */
+#define REG_NVMCTRL_STATUS (*(RwReg16*)0x41004018U) /**< \brief (NVMCTRL) Status */
+#define REG_NVMCTRL_ADDR (*(RwReg *)0x4100401CU) /**< \brief (NVMCTRL) Address */
+#define REG_NVMCTRL_LOCK (*(RwReg16*)0x41004020U) /**< \brief (NVMCTRL) Lock Section */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for NVMCTRL peripheral ========== */
+#define NVMCTRL_AUX0_ADDRESS 0x00804000
+#define NVMCTRL_AUX1_ADDRESS 0x00806000
+#define NVMCTRL_AUX2_ADDRESS 0x00808000
+#define NVMCTRL_AUX3_ADDRESS 0x0080A000
+#define NVMCTRL_CLK_AHB_ID 4 // Index of AHB Clock in PM.AHBMASK register
+#define NVMCTRL_FACTORY_WORD_IMPLEMENTED_MASK 0xC0000007FFFFFFFF
+#define NVMCTRL_FLASH_SIZE 262144
+#define NVMCTRL_LOCKBIT_ADDRESS 0x00802000
+#define NVMCTRL_PAGE_HW 32
+#define NVMCTRL_PAGE_SIZE 64
+#define NVMCTRL_PAGE_W 16
+#define NVMCTRL_PMSB 3
+#define NVMCTRL_PSZ_BITS 6
+#define NVMCTRL_ROW_PAGES 4
+#define NVMCTRL_ROW_SIZE 256
+#define NVMCTRL_TEMP_LOG_ADDRESS 0x00806030
+#define NVMCTRL_USER_PAGE_ADDRESS 0x00800000
+#define NVMCTRL_USER_PAGE_OFFSET 0x00800000
+#define NVMCTRL_USER_WORD_IMPLEMENTED_MASK 0xC01FFFFFFFFFFFFF
+
+#endif /* _SAMD21_NVMCTRL_INSTANCE_ */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/pac0.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/pac0.h
new file mode 100644
index 0000000000000000000000000000000000000000..7712d03813c3fa1cf2c65fcff9c5d22e6093ae31
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/pac0.h
@@ -0,0 +1,59 @@
+/**
+ * \file
+ *
+ * \brief Instance description for PAC0
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_PAC0_INSTANCE_
+#define _SAMD21_PAC0_INSTANCE_
+
+/* ========== Register definition for PAC0 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PAC0_WPCLR (0x40000000U) /**< \brief (PAC0) Write Protection Clear */
+#define REG_PAC0_WPSET (0x40000004U) /**< \brief (PAC0) Write Protection Set */
+#else
+#define REG_PAC0_WPCLR (*(RwReg *)0x40000000U) /**< \brief (PAC0) Write Protection Clear */
+#define REG_PAC0_WPSET (*(RwReg *)0x40000004U) /**< \brief (PAC0) Write Protection Set */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for PAC0 peripheral ========== */
+#define PAC0_WPROT_DEFAULT_VAL 0x00000000 // PAC protection mask at reset
+
+#endif /* _SAMD21_PAC0_INSTANCE_ */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/pac1.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/pac1.h
new file mode 100644
index 0000000000000000000000000000000000000000..74b02453cfc0045a650de9d6dfb5bb2504d427f8
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/pac1.h
@@ -0,0 +1,59 @@
+/**
+ * \file
+ *
+ * \brief Instance description for PAC1
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_PAC1_INSTANCE_
+#define _SAMD21_PAC1_INSTANCE_
+
+/* ========== Register definition for PAC1 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PAC1_WPCLR (0x41000000U) /**< \brief (PAC1) Write Protection Clear */
+#define REG_PAC1_WPSET (0x41000004U) /**< \brief (PAC1) Write Protection Set */
+#else
+#define REG_PAC1_WPCLR (*(RwReg *)0x41000000U) /**< \brief (PAC1) Write Protection Clear */
+#define REG_PAC1_WPSET (*(RwReg *)0x41000004U) /**< \brief (PAC1) Write Protection Set */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for PAC1 peripheral ========== */
+#define PAC1_WPROT_DEFAULT_VAL 0x00000002 // PAC protection mask at reset
+
+#endif /* _SAMD21_PAC1_INSTANCE_ */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/pac2.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/pac2.h
new file mode 100644
index 0000000000000000000000000000000000000000..57688e5ea5723c66daa67b6b1b47fb320f4883ba
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/pac2.h
@@ -0,0 +1,59 @@
+/**
+ * \file
+ *
+ * \brief Instance description for PAC2
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_PAC2_INSTANCE_
+#define _SAMD21_PAC2_INSTANCE_
+
+/* ========== Register definition for PAC2 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PAC2_WPCLR (0x42000000U) /**< \brief (PAC2) Write Protection Clear */
+#define REG_PAC2_WPSET (0x42000004U) /**< \brief (PAC2) Write Protection Set */
+#else
+#define REG_PAC2_WPCLR (*(RwReg *)0x42000000U) /**< \brief (PAC2) Write Protection Clear */
+#define REG_PAC2_WPSET (*(RwReg *)0x42000004U) /**< \brief (PAC2) Write Protection Set */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for PAC2 peripheral ========== */
+#define PAC2_WPROT_DEFAULT_VAL 0x00800000 // PAC protection mask at reset
+
+#endif /* _SAMD21_PAC2_INSTANCE_ */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/pm.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/pm.h
new file mode 100644
index 0000000000000000000000000000000000000000..77c30635a5aa6171d7ca8b4ef8b04c735d679a82
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/pm.h
@@ -0,0 +1,87 @@
+/**
+ * \file
+ *
+ * \brief Instance description for PM
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_PM_INSTANCE_
+#define _SAMD21_PM_INSTANCE_
+
+/* ========== Register definition for PM peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PM_CTRL (0x40000400U) /**< \brief (PM) Control */
+#define REG_PM_SLEEP (0x40000401U) /**< \brief (PM) Sleep Mode */
+#define REG_PM_CPUSEL (0x40000408U) /**< \brief (PM) CPU Clock Select */
+#define REG_PM_APBASEL (0x40000409U) /**< \brief (PM) APBA Clock Select */
+#define REG_PM_APBBSEL (0x4000040AU) /**< \brief (PM) APBB Clock Select */
+#define REG_PM_APBCSEL (0x4000040BU) /**< \brief (PM) APBC Clock Select */
+#define REG_PM_AHBMASK (0x40000414U) /**< \brief (PM) AHB Mask */
+#define REG_PM_APBAMASK (0x40000418U) /**< \brief (PM) APBA Mask */
+#define REG_PM_APBBMASK (0x4000041CU) /**< \brief (PM) APBB Mask */
+#define REG_PM_APBCMASK (0x40000420U) /**< \brief (PM) APBC Mask */
+#define REG_PM_INTENCLR (0x40000434U) /**< \brief (PM) Interrupt Enable Clear */
+#define REG_PM_INTENSET (0x40000435U) /**< \brief (PM) Interrupt Enable Set */
+#define REG_PM_INTFLAG (0x40000436U) /**< \brief (PM) Interrupt Flag Status and Clear */
+#define REG_PM_RCAUSE (0x40000438U) /**< \brief (PM) Reset Cause */
+#else
+#define REG_PM_CTRL (*(RwReg8 *)0x40000400U) /**< \brief (PM) Control */
+#define REG_PM_SLEEP (*(RwReg8 *)0x40000401U) /**< \brief (PM) Sleep Mode */
+#define REG_PM_CPUSEL (*(RwReg8 *)0x40000408U) /**< \brief (PM) CPU Clock Select */
+#define REG_PM_APBASEL (*(RwReg8 *)0x40000409U) /**< \brief (PM) APBA Clock Select */
+#define REG_PM_APBBSEL (*(RwReg8 *)0x4000040AU) /**< \brief (PM) APBB Clock Select */
+#define REG_PM_APBCSEL (*(RwReg8 *)0x4000040BU) /**< \brief (PM) APBC Clock Select */
+#define REG_PM_AHBMASK (*(RwReg *)0x40000414U) /**< \brief (PM) AHB Mask */
+#define REG_PM_APBAMASK (*(RwReg *)0x40000418U) /**< \brief (PM) APBA Mask */
+#define REG_PM_APBBMASK (*(RwReg *)0x4000041CU) /**< \brief (PM) APBB Mask */
+#define REG_PM_APBCMASK (*(RwReg *)0x40000420U) /**< \brief (PM) APBC Mask */
+#define REG_PM_INTENCLR (*(RwReg8 *)0x40000434U) /**< \brief (PM) Interrupt Enable Clear */
+#define REG_PM_INTENSET (*(RwReg8 *)0x40000435U) /**< \brief (PM) Interrupt Enable Set */
+#define REG_PM_INTFLAG (*(RwReg8 *)0x40000436U) /**< \brief (PM) Interrupt Flag Status and Clear */
+#define REG_PM_RCAUSE (*(RoReg8 *)0x40000438U) /**< \brief (PM) Reset Cause */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for PM peripheral ========== */
+#define PM_CTRL_MCSEL_DFLL48M 3
+#define PM_CTRL_MCSEL_GCLK 0
+#define PM_CTRL_MCSEL_OSC8M 1
+#define PM_CTRL_MCSEL_XOSC 2
+#define PM_PM_CLK_APB_NUM 2
+
+#endif /* _SAMD21_PM_INSTANCE_ */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/port.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/port.h
new file mode 100644
index 0000000000000000000000000000000000000000..6187be566f9addd9f7733b568e41eb69691923f2
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/port.h
@@ -0,0 +1,136 @@
+/**
+ * \file
+ *
+ * \brief Instance description for PORT
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_PORT_INSTANCE_
+#define _SAMD21_PORT_INSTANCE_
+
+/* ========== Register definition for PORT peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_PORT_DIR0 (0x41004400U) /**< \brief (PORT) Data Direction 0 */
+#define REG_PORT_DIRCLR0 (0x41004404U) /**< \brief (PORT) Data Direction Clear 0 */
+#define REG_PORT_DIRSET0 (0x41004408U) /**< \brief (PORT) Data Direction Set 0 */
+#define REG_PORT_DIRTGL0 (0x4100440CU) /**< \brief (PORT) Data Direction Toggle 0 */
+#define REG_PORT_OUT0 (0x41004410U) /**< \brief (PORT) Data Output Value 0 */
+#define REG_PORT_OUTCLR0 (0x41004414U) /**< \brief (PORT) Data Output Value Clear 0 */
+#define REG_PORT_OUTSET0 (0x41004418U) /**< \brief (PORT) Data Output Value Set 0 */
+#define REG_PORT_OUTTGL0 (0x4100441CU) /**< \brief (PORT) Data Output Value Toggle 0 */
+#define REG_PORT_IN0 (0x41004420U) /**< \brief (PORT) Data Input Value 0 */
+#define REG_PORT_CTRL0 (0x41004424U) /**< \brief (PORT) Control 0 */
+#define REG_PORT_WRCONFIG0 (0x41004428U) /**< \brief (PORT) Write Configuration 0 */
+#define REG_PORT_PMUX0 (0x41004430U) /**< \brief (PORT) Peripheral Multiplexing 0 */
+#define REG_PORT_PINCFG0 (0x41004440U) /**< \brief (PORT) Pin Configuration 0 */
+#define REG_PORT_DIR1 (0x41004480U) /**< \brief (PORT) Data Direction 1 */
+#define REG_PORT_DIRCLR1 (0x41004484U) /**< \brief (PORT) Data Direction Clear 1 */
+#define REG_PORT_DIRSET1 (0x41004488U) /**< \brief (PORT) Data Direction Set 1 */
+#define REG_PORT_DIRTGL1 (0x4100448CU) /**< \brief (PORT) Data Direction Toggle 1 */
+#define REG_PORT_OUT1 (0x41004490U) /**< \brief (PORT) Data Output Value 1 */
+#define REG_PORT_OUTCLR1 (0x41004494U) /**< \brief (PORT) Data Output Value Clear 1 */
+#define REG_PORT_OUTSET1 (0x41004498U) /**< \brief (PORT) Data Output Value Set 1 */
+#define REG_PORT_OUTTGL1 (0x4100449CU) /**< \brief (PORT) Data Output Value Toggle 1 */
+#define REG_PORT_IN1 (0x410044A0U) /**< \brief (PORT) Data Input Value 1 */
+#define REG_PORT_CTRL1 (0x410044A4U) /**< \brief (PORT) Control 1 */
+#define REG_PORT_WRCONFIG1 (0x410044A8U) /**< \brief (PORT) Write Configuration 1 */
+#define REG_PORT_PMUX1 (0x410044B0U) /**< \brief (PORT) Peripheral Multiplexing 1 */
+#define REG_PORT_PINCFG1 (0x410044C0U) /**< \brief (PORT) Pin Configuration 1 */
+#else
+#define REG_PORT_DIR0 (*(RwReg *)0x41004400U) /**< \brief (PORT) Data Direction 0 */
+#define REG_PORT_DIRCLR0 (*(RwReg *)0x41004404U) /**< \brief (PORT) Data Direction Clear 0 */
+#define REG_PORT_DIRSET0 (*(RwReg *)0x41004408U) /**< \brief (PORT) Data Direction Set 0 */
+#define REG_PORT_DIRTGL0 (*(RwReg *)0x4100440CU) /**< \brief (PORT) Data Direction Toggle 0 */
+#define REG_PORT_OUT0 (*(RwReg *)0x41004410U) /**< \brief (PORT) Data Output Value 0 */
+#define REG_PORT_OUTCLR0 (*(RwReg *)0x41004414U) /**< \brief (PORT) Data Output Value Clear 0 */
+#define REG_PORT_OUTSET0 (*(RwReg *)0x41004418U) /**< \brief (PORT) Data Output Value Set 0 */
+#define REG_PORT_OUTTGL0 (*(RwReg *)0x4100441CU) /**< \brief (PORT) Data Output Value Toggle 0 */
+#define REG_PORT_IN0 (*(RoReg *)0x41004420U) /**< \brief (PORT) Data Input Value 0 */
+#define REG_PORT_CTRL0 (*(RwReg *)0x41004424U) /**< \brief (PORT) Control 0 */
+#define REG_PORT_WRCONFIG0 (*(WoReg *)0x41004428U) /**< \brief (PORT) Write Configuration 0 */
+#define REG_PORT_PMUX0 (*(RwReg *)0x41004430U) /**< \brief (PORT) Peripheral Multiplexing 0 */
+#define REG_PORT_PINCFG0 (*(RwReg *)0x41004440U) /**< \brief (PORT) Pin Configuration 0 */
+#define REG_PORT_DIR1 (*(RwReg *)0x41004480U) /**< \brief (PORT) Data Direction 1 */
+#define REG_PORT_DIRCLR1 (*(RwReg *)0x41004484U) /**< \brief (PORT) Data Direction Clear 1 */
+#define REG_PORT_DIRSET1 (*(RwReg *)0x41004488U) /**< \brief (PORT) Data Direction Set 1 */
+#define REG_PORT_DIRTGL1 (*(RwReg *)0x4100448CU) /**< \brief (PORT) Data Direction Toggle 1 */
+#define REG_PORT_OUT1 (*(RwReg *)0x41004490U) /**< \brief (PORT) Data Output Value 1 */
+#define REG_PORT_OUTCLR1 (*(RwReg *)0x41004494U) /**< \brief (PORT) Data Output Value Clear 1 */
+#define REG_PORT_OUTSET1 (*(RwReg *)0x41004498U) /**< \brief (PORT) Data Output Value Set 1 */
+#define REG_PORT_OUTTGL1 (*(RwReg *)0x4100449CU) /**< \brief (PORT) Data Output Value Toggle 1 */
+#define REG_PORT_IN1 (*(RoReg *)0x410044A0U) /**< \brief (PORT) Data Input Value 1 */
+#define REG_PORT_CTRL1 (*(RwReg *)0x410044A4U) /**< \brief (PORT) Control 1 */
+#define REG_PORT_WRCONFIG1 (*(WoReg *)0x410044A8U) /**< \brief (PORT) Write Configuration 1 */
+#define REG_PORT_PMUX1 (*(RwReg *)0x410044B0U) /**< \brief (PORT) Peripheral Multiplexing 1 */
+#define REG_PORT_PINCFG1 (*(RwReg *)0x410044C0U) /**< \brief (PORT) Pin Configuration 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for PORT peripheral ========== */
+#define PORT_BITS 84 // Number of PORT pins
+#define PORT_DIR_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } // Default value for DIR of all pins
+#define PORT_DIR_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000FFFFF } // Implementation mask for DIR of all pins
+#define PORT_DRVSTR 1 // DRVSTR supported
+#define PORT_DRVSTR_DEFAULT_VAL { 0xD8FFFFFF, 0xC0C3FFFF, 0x000FFFFF } // Default value for DRVSTR of all pins
+#define PORT_DRVSTR_IMPLEMENTED { 0xD8FFFFFF, 0xC0C3FFFF, 0x000FFFFF } // Implementation mask for DRVSTR of all pins
+#define PORT_EVENT_IMPLEMENTED { 0x00000000, 0x00000000, 0x00000000 }
+#define PORT_INEN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } // Default value for INEN of all pins
+#define PORT_INEN_IMPLEMENTED { 0xD8FFFFFF, 0xC0C3FFFF, 0x000FFFFF } // Implementation mask for INEN of all pins
+#define PORT_ODRAIN 0 // ODRAIN supported
+#define PORT_ODRAIN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } // Default value for ODRAIN of all pins
+#define PORT_ODRAIN_IMPLEMENTED { 0x00000000, 0x00000000, 0x00000000 } // Implementation mask for ODRAIN of all pins
+#define PORT_OUT_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } // Default value for OUT of all pins
+#define PORT_OUT_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000FFFFF } // Implementation mask for OUT of all pins
+#define PORT_PIN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000FFFFF } // Implementation mask for all PORT pins
+#define PORT_PMUXBIT0_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } // Default value for PMUX[0] of all pins
+#define PORT_PMUXBIT0_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000D0000 } // Implementation mask for PMUX[0] of all pins
+#define PORT_PMUXBIT1_DEFAULT_VAL { 0x40000000, 0x00000000, 0x00000000 } // Default value for PMUX[1] of all pins
+#define PORT_PMUXBIT1_IMPLEMENTED { 0xDBFFFFF3, 0xC0C3FF0F, 0x00000000 } // Implementation mask for PMUX[1] of all pins
+#define PORT_PMUXBIT2_DEFAULT_VAL { 0x40000000, 0x00000000, 0x00000000 } // Default value for PMUX[2] of all pins
+#define PORT_PMUXBIT2_IMPLEMENTED { 0xDBFFFFF3, 0xC0C3FF0F, 0x000D0000 } // Implementation mask for PMUX[2] of all pins
+#define PORT_PMUXBIT3_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } // Default value for PMUX[3] of all pins
+#define PORT_PMUXBIT3_IMPLEMENTED { 0x00000000, 0x00000000, 0x00000000 } // Implementation mask for PMUX[3] of all pins
+#define PORT_PMUXEN_DEFAULT_VAL { 0x64000000, 0x3F3C0000, 0x00000000 } // Default value for PMUXEN of all pins
+#define PORT_PMUXEN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000F7FFE } // Implementation mask for PMUXEN of all pins
+#define PORT_PULLEN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } // Default value for PULLEN of all pins
+#define PORT_PULLEN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000FFFFF } // Implementation mask for PULLEN of all pins
+#define PORT_SLEWLIM 0 // SLEWLIM supported
+#define PORT_SLEWLIM_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } // Default value for SLEWLIM of all pins
+#define PORT_SLEWLIM_IMPLEMENTED { 0x00000000, 0x00000000, 0x00000000 } // Implementation mask for SLEWLIM of all pins
+
+#endif /* _SAMD21_PORT_INSTANCE_ */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/rtc.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/rtc.h
new file mode 100644
index 0000000000000000000000000000000000000000..3ebca633f7a8666c34f7af216ca0f6ff2f44b827
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/rtc.h
@@ -0,0 +1,117 @@
+/**
+ * \file
+ *
+ * \brief Instance description for RTC
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_RTC_INSTANCE_
+#define _SAMD21_RTC_INSTANCE_
+
+/* ========== Register definition for RTC peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_RTC_READREQ (0x40001402U) /**< \brief (RTC) Read Request */
+#define REG_RTC_STATUS (0x4000140AU) /**< \brief (RTC) Status */
+#define REG_RTC_DBGCTRL (0x4000140BU) /**< \brief (RTC) Debug Control */
+#define REG_RTC_FREQCORR (0x4000140CU) /**< \brief (RTC) Frequency Correction */
+#define REG_RTC_MODE0_CTRL (0x40001400U) /**< \brief (RTC) MODE0 Control */
+#define REG_RTC_MODE0_EVCTRL (0x40001404U) /**< \brief (RTC) MODE0 Event Control */
+#define REG_RTC_MODE0_INTENCLR (0x40001406U) /**< \brief (RTC) MODE0 Interrupt Enable Clear */
+#define REG_RTC_MODE0_INTENSET (0x40001407U) /**< \brief (RTC) MODE0 Interrupt Enable Set */
+#define REG_RTC_MODE0_INTFLAG (0x40001408U) /**< \brief (RTC) MODE0 Interrupt Flag Status and Clear */
+#define REG_RTC_MODE0_COUNT (0x40001410U) /**< \brief (RTC) MODE0 Counter Value */
+#define REG_RTC_MODE0_COMP0 (0x40001418U) /**< \brief (RTC) MODE0 Compare 0 Value */
+#define REG_RTC_MODE1_CTRL (0x40001400U) /**< \brief (RTC) MODE1 Control */
+#define REG_RTC_MODE1_EVCTRL (0x40001404U) /**< \brief (RTC) MODE1 Event Control */
+#define REG_RTC_MODE1_INTENCLR (0x40001406U) /**< \brief (RTC) MODE1 Interrupt Enable Clear */
+#define REG_RTC_MODE1_INTENSET (0x40001407U) /**< \brief (RTC) MODE1 Interrupt Enable Set */
+#define REG_RTC_MODE1_INTFLAG (0x40001408U) /**< \brief (RTC) MODE1 Interrupt Flag Status and Clear */
+#define REG_RTC_MODE1_COUNT (0x40001410U) /**< \brief (RTC) MODE1 Counter Value */
+#define REG_RTC_MODE1_PER (0x40001414U) /**< \brief (RTC) MODE1 Counter Period */
+#define REG_RTC_MODE1_COMP0 (0x40001418U) /**< \brief (RTC) MODE1 Compare 0 Value */
+#define REG_RTC_MODE1_COMP1 (0x4000141AU) /**< \brief (RTC) MODE1 Compare 1 Value */
+#define REG_RTC_MODE2_CTRL (0x40001400U) /**< \brief (RTC) MODE2 Control */
+#define REG_RTC_MODE2_EVCTRL (0x40001404U) /**< \brief (RTC) MODE2 Event Control */
+#define REG_RTC_MODE2_INTENCLR (0x40001406U) /**< \brief (RTC) MODE2 Interrupt Enable Clear */
+#define REG_RTC_MODE2_INTENSET (0x40001407U) /**< \brief (RTC) MODE2 Interrupt Enable Set */
+#define REG_RTC_MODE2_INTFLAG (0x40001408U) /**< \brief (RTC) MODE2 Interrupt Flag Status and Clear */
+#define REG_RTC_MODE2_CLOCK (0x40001410U) /**< \brief (RTC) MODE2 Clock Value */
+#define REG_RTC_MODE2_ALARM_ALARM0 (0x40001418U) /**< \brief (RTC) MODE2_ALARM Alarm 0 Value */
+#define REG_RTC_MODE2_ALARM_MASK0 (0x4000141CU) /**< \brief (RTC) MODE2_ALARM Alarm 0 Mask */
+#else
+#define REG_RTC_READREQ (*(RwReg16*)0x40001402U) /**< \brief (RTC) Read Request */
+#define REG_RTC_STATUS (*(RwReg8 *)0x4000140AU) /**< \brief (RTC) Status */
+#define REG_RTC_DBGCTRL (*(RwReg8 *)0x4000140BU) /**< \brief (RTC) Debug Control */
+#define REG_RTC_FREQCORR (*(RwReg8 *)0x4000140CU) /**< \brief (RTC) Frequency Correction */
+#define REG_RTC_MODE0_CTRL (*(RwReg16*)0x40001400U) /**< \brief (RTC) MODE0 Control */
+#define REG_RTC_MODE0_EVCTRL (*(RwReg16*)0x40001404U) /**< \brief (RTC) MODE0 Event Control */
+#define REG_RTC_MODE0_INTENCLR (*(RwReg8 *)0x40001406U) /**< \brief (RTC) MODE0 Interrupt Enable Clear */
+#define REG_RTC_MODE0_INTENSET (*(RwReg8 *)0x40001407U) /**< \brief (RTC) MODE0 Interrupt Enable Set */
+#define REG_RTC_MODE0_INTFLAG (*(RwReg8 *)0x40001408U) /**< \brief (RTC) MODE0 Interrupt Flag Status and Clear */
+#define REG_RTC_MODE0_COUNT (*(RwReg *)0x40001410U) /**< \brief (RTC) MODE0 Counter Value */
+#define REG_RTC_MODE0_COMP0 (*(RwReg *)0x40001418U) /**< \brief (RTC) MODE0 Compare 0 Value */
+#define REG_RTC_MODE1_CTRL (*(RwReg16*)0x40001400U) /**< \brief (RTC) MODE1 Control */
+#define REG_RTC_MODE1_EVCTRL (*(RwReg16*)0x40001404U) /**< \brief (RTC) MODE1 Event Control */
+#define REG_RTC_MODE1_INTENCLR (*(RwReg8 *)0x40001406U) /**< \brief (RTC) MODE1 Interrupt Enable Clear */
+#define REG_RTC_MODE1_INTENSET (*(RwReg8 *)0x40001407U) /**< \brief (RTC) MODE1 Interrupt Enable Set */
+#define REG_RTC_MODE1_INTFLAG (*(RwReg8 *)0x40001408U) /**< \brief (RTC) MODE1 Interrupt Flag Status and Clear */
+#define REG_RTC_MODE1_COUNT (*(RwReg16*)0x40001410U) /**< \brief (RTC) MODE1 Counter Value */
+#define REG_RTC_MODE1_PER (*(RwReg16*)0x40001414U) /**< \brief (RTC) MODE1 Counter Period */
+#define REG_RTC_MODE1_COMP0 (*(RwReg16*)0x40001418U) /**< \brief (RTC) MODE1 Compare 0 Value */
+#define REG_RTC_MODE1_COMP1 (*(RwReg16*)0x4000141AU) /**< \brief (RTC) MODE1 Compare 1 Value */
+#define REG_RTC_MODE2_CTRL (*(RwReg16*)0x40001400U) /**< \brief (RTC) MODE2 Control */
+#define REG_RTC_MODE2_EVCTRL (*(RwReg16*)0x40001404U) /**< \brief (RTC) MODE2 Event Control */
+#define REG_RTC_MODE2_INTENCLR (*(RwReg8 *)0x40001406U) /**< \brief (RTC) MODE2 Interrupt Enable Clear */
+#define REG_RTC_MODE2_INTENSET (*(RwReg8 *)0x40001407U) /**< \brief (RTC) MODE2 Interrupt Enable Set */
+#define REG_RTC_MODE2_INTFLAG (*(RwReg8 *)0x40001408U) /**< \brief (RTC) MODE2 Interrupt Flag Status and Clear */
+#define REG_RTC_MODE2_CLOCK (*(RwReg *)0x40001410U) /**< \brief (RTC) MODE2 Clock Value */
+#define REG_RTC_MODE2_ALARM_ALARM0 (*(RwReg *)0x40001418U) /**< \brief (RTC) MODE2_ALARM Alarm 0 Value */
+#define REG_RTC_MODE2_ALARM_MASK0 (*(RwReg *)0x4000141CU) /**< \brief (RTC) MODE2_ALARM Alarm 0 Mask */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for RTC peripheral ========== */
+#define RTC_ALARM_NUM 1 // Number of Alarms
+#define RTC_COMP16_NUM 2 // Number of 16-bit Comparators
+#define RTC_COMP32_NUM 1 // Number of 32-bit Comparators
+#define RTC_GCLK_ID 4 // Index of Generic Clock
+#define RTC_NUM_OF_ALARMS 1 // Number of Alarms (obsolete)
+#define RTC_NUM_OF_COMP16 2 // Number of 16-bit Comparators (obsolete)
+#define RTC_NUM_OF_COMP32 1 // Number of 32-bit Comparators (obsolete)
+
+#endif /* _SAMD21_RTC_INSTANCE_ */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/sbmatrix.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/sbmatrix.h
new file mode 100644
index 0000000000000000000000000000000000000000..fe1d333ef98e8014b64af18fa3d05a50c315a918
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/sbmatrix.h
@@ -0,0 +1,165 @@
+/**
+ * \file
+ *
+ * \brief Instance description for SBMATRIX
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_SBMATRIX_INSTANCE_
+#define _SAMD21_SBMATRIX_INSTANCE_
+
+/* ========== Register definition for SBMATRIX peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SBMATRIX_PRAS0 (0x41007080U) /**< \brief (SBMATRIX) Priority A for Slave 0 */
+#define REG_SBMATRIX_PRBS0 (0x41007084U) /**< \brief (SBMATRIX) Priority B for Slave 0 */
+#define REG_SBMATRIX_PRAS1 (0x41007088U) /**< \brief (SBMATRIX) Priority A for Slave 1 */
+#define REG_SBMATRIX_PRBS1 (0x4100708CU) /**< \brief (SBMATRIX) Priority B for Slave 1 */
+#define REG_SBMATRIX_PRAS2 (0x41007090U) /**< \brief (SBMATRIX) Priority A for Slave 2 */
+#define REG_SBMATRIX_PRBS2 (0x41007094U) /**< \brief (SBMATRIX) Priority B for Slave 2 */
+#define REG_SBMATRIX_PRAS3 (0x41007098U) /**< \brief (SBMATRIX) Priority A for Slave 3 */
+#define REG_SBMATRIX_PRBS3 (0x4100709CU) /**< \brief (SBMATRIX) Priority B for Slave 3 */
+#define REG_SBMATRIX_PRAS4 (0x410070A0U) /**< \brief (SBMATRIX) Priority A for Slave 4 */
+#define REG_SBMATRIX_PRBS4 (0x410070A4U) /**< \brief (SBMATRIX) Priority B for Slave 4 */
+#define REG_SBMATRIX_PRAS5 (0x410070A8U) /**< \brief (SBMATRIX) Priority A for Slave 5 */
+#define REG_SBMATRIX_PRBS5 (0x410070ACU) /**< \brief (SBMATRIX) Priority B for Slave 5 */
+#define REG_SBMATRIX_PRAS6 (0x410070B0U) /**< \brief (SBMATRIX) Priority A for Slave 6 */
+#define REG_SBMATRIX_PRBS6 (0x410070B4U) /**< \brief (SBMATRIX) Priority B for Slave 6 */
+#define REG_SBMATRIX_PRAS7 (0x410070B8U) /**< \brief (SBMATRIX) Priority A for Slave 7 */
+#define REG_SBMATRIX_PRBS7 (0x410070BCU) /**< \brief (SBMATRIX) Priority B for Slave 7 */
+#define REG_SBMATRIX_PRAS8 (0x410070C0U) /**< \brief (SBMATRIX) Priority A for Slave 8 */
+#define REG_SBMATRIX_PRBS8 (0x410070C4U) /**< \brief (SBMATRIX) Priority B for Slave 8 */
+#define REG_SBMATRIX_PRAS9 (0x410070C8U) /**< \brief (SBMATRIX) Priority A for Slave 9 */
+#define REG_SBMATRIX_PRBS9 (0x410070CCU) /**< \brief (SBMATRIX) Priority B for Slave 9 */
+#define REG_SBMATRIX_PRAS10 (0x410070D0U) /**< \brief (SBMATRIX) Priority A for Slave 10 */
+#define REG_SBMATRIX_PRBS10 (0x410070D4U) /**< \brief (SBMATRIX) Priority B for Slave 10 */
+#define REG_SBMATRIX_PRAS11 (0x410070D8U) /**< \brief (SBMATRIX) Priority A for Slave 11 */
+#define REG_SBMATRIX_PRBS11 (0x410070DCU) /**< \brief (SBMATRIX) Priority B for Slave 11 */
+#define REG_SBMATRIX_PRAS12 (0x410070E0U) /**< \brief (SBMATRIX) Priority A for Slave 12 */
+#define REG_SBMATRIX_PRBS12 (0x410070E4U) /**< \brief (SBMATRIX) Priority B for Slave 12 */
+#define REG_SBMATRIX_PRAS13 (0x410070E8U) /**< \brief (SBMATRIX) Priority A for Slave 13 */
+#define REG_SBMATRIX_PRBS13 (0x410070ECU) /**< \brief (SBMATRIX) Priority B for Slave 13 */
+#define REG_SBMATRIX_PRAS14 (0x410070F0U) /**< \brief (SBMATRIX) Priority A for Slave 14 */
+#define REG_SBMATRIX_PRBS14 (0x410070F4U) /**< \brief (SBMATRIX) Priority B for Slave 14 */
+#define REG_SBMATRIX_PRAS15 (0x410070F8U) /**< \brief (SBMATRIX) Priority A for Slave 15 */
+#define REG_SBMATRIX_PRBS15 (0x410070FCU) /**< \brief (SBMATRIX) Priority B for Slave 15 */
+#define REG_SBMATRIX_SFR0 (0x41007110U) /**< \brief (SBMATRIX) Special Function 0 */
+#define REG_SBMATRIX_SFR1 (0x41007114U) /**< \brief (SBMATRIX) Special Function 1 */
+#define REG_SBMATRIX_SFR2 (0x41007118U) /**< \brief (SBMATRIX) Special Function 2 */
+#define REG_SBMATRIX_SFR3 (0x4100711CU) /**< \brief (SBMATRIX) Special Function 3 */
+#define REG_SBMATRIX_SFR4 (0x41007120U) /**< \brief (SBMATRIX) Special Function 4 */
+#define REG_SBMATRIX_SFR5 (0x41007124U) /**< \brief (SBMATRIX) Special Function 5 */
+#define REG_SBMATRIX_SFR6 (0x41007128U) /**< \brief (SBMATRIX) Special Function 6 */
+#define REG_SBMATRIX_SFR7 (0x4100712CU) /**< \brief (SBMATRIX) Special Function 7 */
+#define REG_SBMATRIX_SFR8 (0x41007130U) /**< \brief (SBMATRIX) Special Function 8 */
+#define REG_SBMATRIX_SFR9 (0x41007134U) /**< \brief (SBMATRIX) Special Function 9 */
+#define REG_SBMATRIX_SFR10 (0x41007138U) /**< \brief (SBMATRIX) Special Function 10 */
+#define REG_SBMATRIX_SFR11 (0x4100713CU) /**< \brief (SBMATRIX) Special Function 11 */
+#define REG_SBMATRIX_SFR12 (0x41007140U) /**< \brief (SBMATRIX) Special Function 12 */
+#define REG_SBMATRIX_SFR13 (0x41007144U) /**< \brief (SBMATRIX) Special Function 13 */
+#define REG_SBMATRIX_SFR14 (0x41007148U) /**< \brief (SBMATRIX) Special Function 14 */
+#define REG_SBMATRIX_SFR15 (0x4100714CU) /**< \brief (SBMATRIX) Special Function 15 */
+#else
+#define REG_SBMATRIX_PRAS0 (*(RwReg *)0x41007080U) /**< \brief (SBMATRIX) Priority A for Slave 0 */
+#define REG_SBMATRIX_PRBS0 (*(RwReg *)0x41007084U) /**< \brief (SBMATRIX) Priority B for Slave 0 */
+#define REG_SBMATRIX_PRAS1 (*(RwReg *)0x41007088U) /**< \brief (SBMATRIX) Priority A for Slave 1 */
+#define REG_SBMATRIX_PRBS1 (*(RwReg *)0x4100708CU) /**< \brief (SBMATRIX) Priority B for Slave 1 */
+#define REG_SBMATRIX_PRAS2 (*(RwReg *)0x41007090U) /**< \brief (SBMATRIX) Priority A for Slave 2 */
+#define REG_SBMATRIX_PRBS2 (*(RwReg *)0x41007094U) /**< \brief (SBMATRIX) Priority B for Slave 2 */
+#define REG_SBMATRIX_PRAS3 (*(RwReg *)0x41007098U) /**< \brief (SBMATRIX) Priority A for Slave 3 */
+#define REG_SBMATRIX_PRBS3 (*(RwReg *)0x4100709CU) /**< \brief (SBMATRIX) Priority B for Slave 3 */
+#define REG_SBMATRIX_PRAS4 (*(RwReg *)0x410070A0U) /**< \brief (SBMATRIX) Priority A for Slave 4 */
+#define REG_SBMATRIX_PRBS4 (*(RwReg *)0x410070A4U) /**< \brief (SBMATRIX) Priority B for Slave 4 */
+#define REG_SBMATRIX_PRAS5 (*(RwReg *)0x410070A8U) /**< \brief (SBMATRIX) Priority A for Slave 5 */
+#define REG_SBMATRIX_PRBS5 (*(RwReg *)0x410070ACU) /**< \brief (SBMATRIX) Priority B for Slave 5 */
+#define REG_SBMATRIX_PRAS6 (*(RwReg *)0x410070B0U) /**< \brief (SBMATRIX) Priority A for Slave 6 */
+#define REG_SBMATRIX_PRBS6 (*(RwReg *)0x410070B4U) /**< \brief (SBMATRIX) Priority B for Slave 6 */
+#define REG_SBMATRIX_PRAS7 (*(RwReg *)0x410070B8U) /**< \brief (SBMATRIX) Priority A for Slave 7 */
+#define REG_SBMATRIX_PRBS7 (*(RwReg *)0x410070BCU) /**< \brief (SBMATRIX) Priority B for Slave 7 */
+#define REG_SBMATRIX_PRAS8 (*(RwReg *)0x410070C0U) /**< \brief (SBMATRIX) Priority A for Slave 8 */
+#define REG_SBMATRIX_PRBS8 (*(RwReg *)0x410070C4U) /**< \brief (SBMATRIX) Priority B for Slave 8 */
+#define REG_SBMATRIX_PRAS9 (*(RwReg *)0x410070C8U) /**< \brief (SBMATRIX) Priority A for Slave 9 */
+#define REG_SBMATRIX_PRBS9 (*(RwReg *)0x410070CCU) /**< \brief (SBMATRIX) Priority B for Slave 9 */
+#define REG_SBMATRIX_PRAS10 (*(RwReg *)0x410070D0U) /**< \brief (SBMATRIX) Priority A for Slave 10 */
+#define REG_SBMATRIX_PRBS10 (*(RwReg *)0x410070D4U) /**< \brief (SBMATRIX) Priority B for Slave 10 */
+#define REG_SBMATRIX_PRAS11 (*(RwReg *)0x410070D8U) /**< \brief (SBMATRIX) Priority A for Slave 11 */
+#define REG_SBMATRIX_PRBS11 (*(RwReg *)0x410070DCU) /**< \brief (SBMATRIX) Priority B for Slave 11 */
+#define REG_SBMATRIX_PRAS12 (*(RwReg *)0x410070E0U) /**< \brief (SBMATRIX) Priority A for Slave 12 */
+#define REG_SBMATRIX_PRBS12 (*(RwReg *)0x410070E4U) /**< \brief (SBMATRIX) Priority B for Slave 12 */
+#define REG_SBMATRIX_PRAS13 (*(RwReg *)0x410070E8U) /**< \brief (SBMATRIX) Priority A for Slave 13 */
+#define REG_SBMATRIX_PRBS13 (*(RwReg *)0x410070ECU) /**< \brief (SBMATRIX) Priority B for Slave 13 */
+#define REG_SBMATRIX_PRAS14 (*(RwReg *)0x410070F0U) /**< \brief (SBMATRIX) Priority A for Slave 14 */
+#define REG_SBMATRIX_PRBS14 (*(RwReg *)0x410070F4U) /**< \brief (SBMATRIX) Priority B for Slave 14 */
+#define REG_SBMATRIX_PRAS15 (*(RwReg *)0x410070F8U) /**< \brief (SBMATRIX) Priority A for Slave 15 */
+#define REG_SBMATRIX_PRBS15 (*(RwReg *)0x410070FCU) /**< \brief (SBMATRIX) Priority B for Slave 15 */
+#define REG_SBMATRIX_SFR0 (*(RwReg *)0x41007110U) /**< \brief (SBMATRIX) Special Function 0 */
+#define REG_SBMATRIX_SFR1 (*(RwReg *)0x41007114U) /**< \brief (SBMATRIX) Special Function 1 */
+#define REG_SBMATRIX_SFR2 (*(RwReg *)0x41007118U) /**< \brief (SBMATRIX) Special Function 2 */
+#define REG_SBMATRIX_SFR3 (*(RwReg *)0x4100711CU) /**< \brief (SBMATRIX) Special Function 3 */
+#define REG_SBMATRIX_SFR4 (*(RwReg *)0x41007120U) /**< \brief (SBMATRIX) Special Function 4 */
+#define REG_SBMATRIX_SFR5 (*(RwReg *)0x41007124U) /**< \brief (SBMATRIX) Special Function 5 */
+#define REG_SBMATRIX_SFR6 (*(RwReg *)0x41007128U) /**< \brief (SBMATRIX) Special Function 6 */
+#define REG_SBMATRIX_SFR7 (*(RwReg *)0x4100712CU) /**< \brief (SBMATRIX) Special Function 7 */
+#define REG_SBMATRIX_SFR8 (*(RwReg *)0x41007130U) /**< \brief (SBMATRIX) Special Function 8 */
+#define REG_SBMATRIX_SFR9 (*(RwReg *)0x41007134U) /**< \brief (SBMATRIX) Special Function 9 */
+#define REG_SBMATRIX_SFR10 (*(RwReg *)0x41007138U) /**< \brief (SBMATRIX) Special Function 10 */
+#define REG_SBMATRIX_SFR11 (*(RwReg *)0x4100713CU) /**< \brief (SBMATRIX) Special Function 11 */
+#define REG_SBMATRIX_SFR12 (*(RwReg *)0x41007140U) /**< \brief (SBMATRIX) Special Function 12 */
+#define REG_SBMATRIX_SFR13 (*(RwReg *)0x41007144U) /**< \brief (SBMATRIX) Special Function 13 */
+#define REG_SBMATRIX_SFR14 (*(RwReg *)0x41007148U) /**< \brief (SBMATRIX) Special Function 14 */
+#define REG_SBMATRIX_SFR15 (*(RwReg *)0x4100714CU) /**< \brief (SBMATRIX) Special Function 15 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for SBMATRIX peripheral ========== */
+#define SBMATRIX_DEFINED
+/* ========== Instance parameters for SBMATRIX ========== */
+#define SBMATRIX_SLAVE_FLASH 0
+#define SBMATRIX_SLAVE_HPB0 1
+#define SBMATRIX_SLAVE_HPB1 2
+#define SBMATRIX_SLAVE_HPB2 3
+#define SBMATRIX_SLAVE_HMCRAMC0 4
+#define SBMATRIX_SLAVE_HMCRAMC0_ALT0 5
+#define SBMATRIX_SLAVE_HMCRAMC0_ALT1 6
+#define SBMATRIX_SLAVE_NUM 7
+
+#define SBMATRIX_MASTER_CM0PLUS 0
+#define SBMATRIX_MASTER_DSU 1
+#define SBMATRIX_MASTER_DMAC 2
+#define SBMATRIX_MASTER_NUM 3
+
+#endif /* _SAMD21_SBMATRIX_INSTANCE_ */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/sercom0.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/sercom0.h
new file mode 100644
index 0000000000000000000000000000000000000000..70c048dbc292ec1cb882774c1f8a09adee39bfab
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/sercom0.h
@@ -0,0 +1,143 @@
+/**
+ * \file
+ *
+ * \brief Instance description for SERCOM0
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_SERCOM0_INSTANCE_
+#define _SAMD21_SERCOM0_INSTANCE_
+
+/* ========== Register definition for SERCOM0 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SERCOM0_I2CM_CTRLA (0x42000800U) /**< \brief (SERCOM0) I2CM Control A */
+#define REG_SERCOM0_I2CM_CTRLB (0x42000804U) /**< \brief (SERCOM0) I2CM Control B */
+#define REG_SERCOM0_I2CM_BAUD (0x4200080CU) /**< \brief (SERCOM0) I2CM Baud Rate */
+#define REG_SERCOM0_I2CM_INTENCLR (0x42000814U) /**< \brief (SERCOM0) I2CM Interrupt Enable Clear */
+#define REG_SERCOM0_I2CM_INTENSET (0x42000816U) /**< \brief (SERCOM0) I2CM Interrupt Enable Set */
+#define REG_SERCOM0_I2CM_INTFLAG (0x42000818U) /**< \brief (SERCOM0) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM0_I2CM_STATUS (0x4200081AU) /**< \brief (SERCOM0) I2CM Status */
+#define REG_SERCOM0_I2CM_SYNCBUSY (0x4200081CU) /**< \brief (SERCOM0) I2CM Syncbusy */
+#define REG_SERCOM0_I2CM_ADDR (0x42000824U) /**< \brief (SERCOM0) I2CM Address */
+#define REG_SERCOM0_I2CM_DATA (0x42000828U) /**< \brief (SERCOM0) I2CM Data */
+#define REG_SERCOM0_I2CM_DBGCTRL (0x42000830U) /**< \brief (SERCOM0) I2CM Debug Control */
+#define REG_SERCOM0_I2CS_CTRLA (0x42000800U) /**< \brief (SERCOM0) I2CS Control A */
+#define REG_SERCOM0_I2CS_CTRLB (0x42000804U) /**< \brief (SERCOM0) I2CS Control B */
+#define REG_SERCOM0_I2CS_INTENCLR (0x42000814U) /**< \brief (SERCOM0) I2CS Interrupt Enable Clear */
+#define REG_SERCOM0_I2CS_INTENSET (0x42000816U) /**< \brief (SERCOM0) I2CS Interrupt Enable Set */
+#define REG_SERCOM0_I2CS_INTFLAG (0x42000818U) /**< \brief (SERCOM0) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM0_I2CS_STATUS (0x4200081AU) /**< \brief (SERCOM0) I2CS Status */
+#define REG_SERCOM0_I2CS_SYNCBUSY (0x4200081CU) /**< \brief (SERCOM0) I2CS Syncbusy */
+#define REG_SERCOM0_I2CS_ADDR (0x42000824U) /**< \brief (SERCOM0) I2CS Address */
+#define REG_SERCOM0_I2CS_DATA (0x42000828U) /**< \brief (SERCOM0) I2CS Data */
+#define REG_SERCOM0_SPI_CTRLA (0x42000800U) /**< \brief (SERCOM0) SPI Control A */
+#define REG_SERCOM0_SPI_CTRLB (0x42000804U) /**< \brief (SERCOM0) SPI Control B */
+#define REG_SERCOM0_SPI_BAUD (0x4200080CU) /**< \brief (SERCOM0) SPI Baud Rate */
+#define REG_SERCOM0_SPI_INTENCLR (0x42000814U) /**< \brief (SERCOM0) SPI Interrupt Enable Clear */
+#define REG_SERCOM0_SPI_INTENSET (0x42000816U) /**< \brief (SERCOM0) SPI Interrupt Enable Set */
+#define REG_SERCOM0_SPI_INTFLAG (0x42000818U) /**< \brief (SERCOM0) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM0_SPI_STATUS (0x4200081AU) /**< \brief (SERCOM0) SPI Status */
+#define REG_SERCOM0_SPI_SYNCBUSY (0x4200081CU) /**< \brief (SERCOM0) SPI Syncbusy */
+#define REG_SERCOM0_SPI_ADDR (0x42000824U) /**< \brief (SERCOM0) SPI Address */
+#define REG_SERCOM0_SPI_DATA (0x42000828U) /**< \brief (SERCOM0) SPI Data */
+#define REG_SERCOM0_SPI_DBGCTRL (0x42000830U) /**< \brief (SERCOM0) SPI Debug Control */
+#define REG_SERCOM0_USART_CTRLA (0x42000800U) /**< \brief (SERCOM0) USART Control A */
+#define REG_SERCOM0_USART_CTRLB (0x42000804U) /**< \brief (SERCOM0) USART Control B */
+#define REG_SERCOM0_USART_BAUD (0x4200080CU) /**< \brief (SERCOM0) USART Baud Rate */
+#define REG_SERCOM0_USART_RXPL (0x4200080EU) /**< \brief (SERCOM0) USART Receive Pulse Length */
+#define REG_SERCOM0_USART_INTENCLR (0x42000814U) /**< \brief (SERCOM0) USART Interrupt Enable Clear */
+#define REG_SERCOM0_USART_INTENSET (0x42000816U) /**< \brief (SERCOM0) USART Interrupt Enable Set */
+#define REG_SERCOM0_USART_INTFLAG (0x42000818U) /**< \brief (SERCOM0) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM0_USART_STATUS (0x4200081AU) /**< \brief (SERCOM0) USART Status */
+#define REG_SERCOM0_USART_SYNCBUSY (0x4200081CU) /**< \brief (SERCOM0) USART Syncbusy */
+#define REG_SERCOM0_USART_DATA (0x42000828U) /**< \brief (SERCOM0) USART Data */
+#define REG_SERCOM0_USART_DBGCTRL (0x42000830U) /**< \brief (SERCOM0) USART Debug Control */
+#else
+#define REG_SERCOM0_I2CM_CTRLA (*(RwReg *)0x42000800U) /**< \brief (SERCOM0) I2CM Control A */
+#define REG_SERCOM0_I2CM_CTRLB (*(RwReg *)0x42000804U) /**< \brief (SERCOM0) I2CM Control B */
+#define REG_SERCOM0_I2CM_BAUD (*(RwReg *)0x4200080CU) /**< \brief (SERCOM0) I2CM Baud Rate */
+#define REG_SERCOM0_I2CM_INTENCLR (*(RwReg8 *)0x42000814U) /**< \brief (SERCOM0) I2CM Interrupt Enable Clear */
+#define REG_SERCOM0_I2CM_INTENSET (*(RwReg8 *)0x42000816U) /**< \brief (SERCOM0) I2CM Interrupt Enable Set */
+#define REG_SERCOM0_I2CM_INTFLAG (*(RwReg8 *)0x42000818U) /**< \brief (SERCOM0) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM0_I2CM_STATUS (*(RwReg16*)0x4200081AU) /**< \brief (SERCOM0) I2CM Status */
+#define REG_SERCOM0_I2CM_SYNCBUSY (*(RoReg *)0x4200081CU) /**< \brief (SERCOM0) I2CM Syncbusy */
+#define REG_SERCOM0_I2CM_ADDR (*(RwReg *)0x42000824U) /**< \brief (SERCOM0) I2CM Address */
+#define REG_SERCOM0_I2CM_DATA (*(RwReg8 *)0x42000828U) /**< \brief (SERCOM0) I2CM Data */
+#define REG_SERCOM0_I2CM_DBGCTRL (*(RwReg8 *)0x42000830U) /**< \brief (SERCOM0) I2CM Debug Control */
+#define REG_SERCOM0_I2CS_CTRLA (*(RwReg *)0x42000800U) /**< \brief (SERCOM0) I2CS Control A */
+#define REG_SERCOM0_I2CS_CTRLB (*(RwReg *)0x42000804U) /**< \brief (SERCOM0) I2CS Control B */
+#define REG_SERCOM0_I2CS_INTENCLR (*(RwReg8 *)0x42000814U) /**< \brief (SERCOM0) I2CS Interrupt Enable Clear */
+#define REG_SERCOM0_I2CS_INTENSET (*(RwReg8 *)0x42000816U) /**< \brief (SERCOM0) I2CS Interrupt Enable Set */
+#define REG_SERCOM0_I2CS_INTFLAG (*(RwReg8 *)0x42000818U) /**< \brief (SERCOM0) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM0_I2CS_STATUS (*(RwReg16*)0x4200081AU) /**< \brief (SERCOM0) I2CS Status */
+#define REG_SERCOM0_I2CS_SYNCBUSY (*(RoReg *)0x4200081CU) /**< \brief (SERCOM0) I2CS Syncbusy */
+#define REG_SERCOM0_I2CS_ADDR (*(RwReg *)0x42000824U) /**< \brief (SERCOM0) I2CS Address */
+#define REG_SERCOM0_I2CS_DATA (*(RwReg8 *)0x42000828U) /**< \brief (SERCOM0) I2CS Data */
+#define REG_SERCOM0_SPI_CTRLA (*(RwReg *)0x42000800U) /**< \brief (SERCOM0) SPI Control A */
+#define REG_SERCOM0_SPI_CTRLB (*(RwReg *)0x42000804U) /**< \brief (SERCOM0) SPI Control B */
+#define REG_SERCOM0_SPI_BAUD (*(RwReg8 *)0x4200080CU) /**< \brief (SERCOM0) SPI Baud Rate */
+#define REG_SERCOM0_SPI_INTENCLR (*(RwReg8 *)0x42000814U) /**< \brief (SERCOM0) SPI Interrupt Enable Clear */
+#define REG_SERCOM0_SPI_INTENSET (*(RwReg8 *)0x42000816U) /**< \brief (SERCOM0) SPI Interrupt Enable Set */
+#define REG_SERCOM0_SPI_INTFLAG (*(RwReg8 *)0x42000818U) /**< \brief (SERCOM0) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM0_SPI_STATUS (*(RwReg16*)0x4200081AU) /**< \brief (SERCOM0) SPI Status */
+#define REG_SERCOM0_SPI_SYNCBUSY (*(RoReg *)0x4200081CU) /**< \brief (SERCOM0) SPI Syncbusy */
+#define REG_SERCOM0_SPI_ADDR (*(RwReg *)0x42000824U) /**< \brief (SERCOM0) SPI Address */
+#define REG_SERCOM0_SPI_DATA (*(RwReg *)0x42000828U) /**< \brief (SERCOM0) SPI Data */
+#define REG_SERCOM0_SPI_DBGCTRL (*(RwReg8 *)0x42000830U) /**< \brief (SERCOM0) SPI Debug Control */
+#define REG_SERCOM0_USART_CTRLA (*(RwReg *)0x42000800U) /**< \brief (SERCOM0) USART Control A */
+#define REG_SERCOM0_USART_CTRLB (*(RwReg *)0x42000804U) /**< \brief (SERCOM0) USART Control B */
+#define REG_SERCOM0_USART_BAUD (*(RwReg16*)0x4200080CU) /**< \brief (SERCOM0) USART Baud Rate */
+#define REG_SERCOM0_USART_RXPL (*(RwReg8 *)0x4200080EU) /**< \brief (SERCOM0) USART Receive Pulse Length */
+#define REG_SERCOM0_USART_INTENCLR (*(RwReg8 *)0x42000814U) /**< \brief (SERCOM0) USART Interrupt Enable Clear */
+#define REG_SERCOM0_USART_INTENSET (*(RwReg8 *)0x42000816U) /**< \brief (SERCOM0) USART Interrupt Enable Set */
+#define REG_SERCOM0_USART_INTFLAG (*(RwReg8 *)0x42000818U) /**< \brief (SERCOM0) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM0_USART_STATUS (*(RwReg16*)0x4200081AU) /**< \brief (SERCOM0) USART Status */
+#define REG_SERCOM0_USART_SYNCBUSY (*(RoReg *)0x4200081CU) /**< \brief (SERCOM0) USART Syncbusy */
+#define REG_SERCOM0_USART_DATA (*(RwReg16*)0x42000828U) /**< \brief (SERCOM0) USART Data */
+#define REG_SERCOM0_USART_DBGCTRL (*(RwReg8 *)0x42000830U) /**< \brief (SERCOM0) USART Debug Control */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for SERCOM0 peripheral ========== */
+#define SERCOM0_DMAC_ID_RX 1 // Index of DMA RX trigger
+#define SERCOM0_DMAC_ID_TX 2 // Index of DMA TX trigger
+#define SERCOM0_GCLK_ID_CORE 20 // Index of Generic Clock for Core
+#define SERCOM0_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout
+#define SERCOM0_INT_MSB 6
+
+#endif /* _SAMD21_SERCOM0_INSTANCE_ */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/sercom1.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/sercom1.h
new file mode 100644
index 0000000000000000000000000000000000000000..35bd112c9223905f1cf91d55e9f4442d8c6f6d12
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/sercom1.h
@@ -0,0 +1,143 @@
+/**
+ * \file
+ *
+ * \brief Instance description for SERCOM1
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_SERCOM1_INSTANCE_
+#define _SAMD21_SERCOM1_INSTANCE_
+
+/* ========== Register definition for SERCOM1 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SERCOM1_I2CM_CTRLA (0x42000C00U) /**< \brief (SERCOM1) I2CM Control A */
+#define REG_SERCOM1_I2CM_CTRLB (0x42000C04U) /**< \brief (SERCOM1) I2CM Control B */
+#define REG_SERCOM1_I2CM_BAUD (0x42000C0CU) /**< \brief (SERCOM1) I2CM Baud Rate */
+#define REG_SERCOM1_I2CM_INTENCLR (0x42000C14U) /**< \brief (SERCOM1) I2CM Interrupt Enable Clear */
+#define REG_SERCOM1_I2CM_INTENSET (0x42000C16U) /**< \brief (SERCOM1) I2CM Interrupt Enable Set */
+#define REG_SERCOM1_I2CM_INTFLAG (0x42000C18U) /**< \brief (SERCOM1) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM1_I2CM_STATUS (0x42000C1AU) /**< \brief (SERCOM1) I2CM Status */
+#define REG_SERCOM1_I2CM_SYNCBUSY (0x42000C1CU) /**< \brief (SERCOM1) I2CM Syncbusy */
+#define REG_SERCOM1_I2CM_ADDR (0x42000C24U) /**< \brief (SERCOM1) I2CM Address */
+#define REG_SERCOM1_I2CM_DATA (0x42000C28U) /**< \brief (SERCOM1) I2CM Data */
+#define REG_SERCOM1_I2CM_DBGCTRL (0x42000C30U) /**< \brief (SERCOM1) I2CM Debug Control */
+#define REG_SERCOM1_I2CS_CTRLA (0x42000C00U) /**< \brief (SERCOM1) I2CS Control A */
+#define REG_SERCOM1_I2CS_CTRLB (0x42000C04U) /**< \brief (SERCOM1) I2CS Control B */
+#define REG_SERCOM1_I2CS_INTENCLR (0x42000C14U) /**< \brief (SERCOM1) I2CS Interrupt Enable Clear */
+#define REG_SERCOM1_I2CS_INTENSET (0x42000C16U) /**< \brief (SERCOM1) I2CS Interrupt Enable Set */
+#define REG_SERCOM1_I2CS_INTFLAG (0x42000C18U) /**< \brief (SERCOM1) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM1_I2CS_STATUS (0x42000C1AU) /**< \brief (SERCOM1) I2CS Status */
+#define REG_SERCOM1_I2CS_SYNCBUSY (0x42000C1CU) /**< \brief (SERCOM1) I2CS Syncbusy */
+#define REG_SERCOM1_I2CS_ADDR (0x42000C24U) /**< \brief (SERCOM1) I2CS Address */
+#define REG_SERCOM1_I2CS_DATA (0x42000C28U) /**< \brief (SERCOM1) I2CS Data */
+#define REG_SERCOM1_SPI_CTRLA (0x42000C00U) /**< \brief (SERCOM1) SPI Control A */
+#define REG_SERCOM1_SPI_CTRLB (0x42000C04U) /**< \brief (SERCOM1) SPI Control B */
+#define REG_SERCOM1_SPI_BAUD (0x42000C0CU) /**< \brief (SERCOM1) SPI Baud Rate */
+#define REG_SERCOM1_SPI_INTENCLR (0x42000C14U) /**< \brief (SERCOM1) SPI Interrupt Enable Clear */
+#define REG_SERCOM1_SPI_INTENSET (0x42000C16U) /**< \brief (SERCOM1) SPI Interrupt Enable Set */
+#define REG_SERCOM1_SPI_INTFLAG (0x42000C18U) /**< \brief (SERCOM1) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM1_SPI_STATUS (0x42000C1AU) /**< \brief (SERCOM1) SPI Status */
+#define REG_SERCOM1_SPI_SYNCBUSY (0x42000C1CU) /**< \brief (SERCOM1) SPI Syncbusy */
+#define REG_SERCOM1_SPI_ADDR (0x42000C24U) /**< \brief (SERCOM1) SPI Address */
+#define REG_SERCOM1_SPI_DATA (0x42000C28U) /**< \brief (SERCOM1) SPI Data */
+#define REG_SERCOM1_SPI_DBGCTRL (0x42000C30U) /**< \brief (SERCOM1) SPI Debug Control */
+#define REG_SERCOM1_USART_CTRLA (0x42000C00U) /**< \brief (SERCOM1) USART Control A */
+#define REG_SERCOM1_USART_CTRLB (0x42000C04U) /**< \brief (SERCOM1) USART Control B */
+#define REG_SERCOM1_USART_BAUD (0x42000C0CU) /**< \brief (SERCOM1) USART Baud Rate */
+#define REG_SERCOM1_USART_RXPL (0x42000C0EU) /**< \brief (SERCOM1) USART Receive Pulse Length */
+#define REG_SERCOM1_USART_INTENCLR (0x42000C14U) /**< \brief (SERCOM1) USART Interrupt Enable Clear */
+#define REG_SERCOM1_USART_INTENSET (0x42000C16U) /**< \brief (SERCOM1) USART Interrupt Enable Set */
+#define REG_SERCOM1_USART_INTFLAG (0x42000C18U) /**< \brief (SERCOM1) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM1_USART_STATUS (0x42000C1AU) /**< \brief (SERCOM1) USART Status */
+#define REG_SERCOM1_USART_SYNCBUSY (0x42000C1CU) /**< \brief (SERCOM1) USART Syncbusy */
+#define REG_SERCOM1_USART_DATA (0x42000C28U) /**< \brief (SERCOM1) USART Data */
+#define REG_SERCOM1_USART_DBGCTRL (0x42000C30U) /**< \brief (SERCOM1) USART Debug Control */
+#else
+#define REG_SERCOM1_I2CM_CTRLA (*(RwReg *)0x42000C00U) /**< \brief (SERCOM1) I2CM Control A */
+#define REG_SERCOM1_I2CM_CTRLB (*(RwReg *)0x42000C04U) /**< \brief (SERCOM1) I2CM Control B */
+#define REG_SERCOM1_I2CM_BAUD (*(RwReg *)0x42000C0CU) /**< \brief (SERCOM1) I2CM Baud Rate */
+#define REG_SERCOM1_I2CM_INTENCLR (*(RwReg8 *)0x42000C14U) /**< \brief (SERCOM1) I2CM Interrupt Enable Clear */
+#define REG_SERCOM1_I2CM_INTENSET (*(RwReg8 *)0x42000C16U) /**< \brief (SERCOM1) I2CM Interrupt Enable Set */
+#define REG_SERCOM1_I2CM_INTFLAG (*(RwReg8 *)0x42000C18U) /**< \brief (SERCOM1) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM1_I2CM_STATUS (*(RwReg16*)0x42000C1AU) /**< \brief (SERCOM1) I2CM Status */
+#define REG_SERCOM1_I2CM_SYNCBUSY (*(RoReg *)0x42000C1CU) /**< \brief (SERCOM1) I2CM Syncbusy */
+#define REG_SERCOM1_I2CM_ADDR (*(RwReg *)0x42000C24U) /**< \brief (SERCOM1) I2CM Address */
+#define REG_SERCOM1_I2CM_DATA (*(RwReg8 *)0x42000C28U) /**< \brief (SERCOM1) I2CM Data */
+#define REG_SERCOM1_I2CM_DBGCTRL (*(RwReg8 *)0x42000C30U) /**< \brief (SERCOM1) I2CM Debug Control */
+#define REG_SERCOM1_I2CS_CTRLA (*(RwReg *)0x42000C00U) /**< \brief (SERCOM1) I2CS Control A */
+#define REG_SERCOM1_I2CS_CTRLB (*(RwReg *)0x42000C04U) /**< \brief (SERCOM1) I2CS Control B */
+#define REG_SERCOM1_I2CS_INTENCLR (*(RwReg8 *)0x42000C14U) /**< \brief (SERCOM1) I2CS Interrupt Enable Clear */
+#define REG_SERCOM1_I2CS_INTENSET (*(RwReg8 *)0x42000C16U) /**< \brief (SERCOM1) I2CS Interrupt Enable Set */
+#define REG_SERCOM1_I2CS_INTFLAG (*(RwReg8 *)0x42000C18U) /**< \brief (SERCOM1) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM1_I2CS_STATUS (*(RwReg16*)0x42000C1AU) /**< \brief (SERCOM1) I2CS Status */
+#define REG_SERCOM1_I2CS_SYNCBUSY (*(RoReg *)0x42000C1CU) /**< \brief (SERCOM1) I2CS Syncbusy */
+#define REG_SERCOM1_I2CS_ADDR (*(RwReg *)0x42000C24U) /**< \brief (SERCOM1) I2CS Address */
+#define REG_SERCOM1_I2CS_DATA (*(RwReg8 *)0x42000C28U) /**< \brief (SERCOM1) I2CS Data */
+#define REG_SERCOM1_SPI_CTRLA (*(RwReg *)0x42000C00U) /**< \brief (SERCOM1) SPI Control A */
+#define REG_SERCOM1_SPI_CTRLB (*(RwReg *)0x42000C04U) /**< \brief (SERCOM1) SPI Control B */
+#define REG_SERCOM1_SPI_BAUD (*(RwReg8 *)0x42000C0CU) /**< \brief (SERCOM1) SPI Baud Rate */
+#define REG_SERCOM1_SPI_INTENCLR (*(RwReg8 *)0x42000C14U) /**< \brief (SERCOM1) SPI Interrupt Enable Clear */
+#define REG_SERCOM1_SPI_INTENSET (*(RwReg8 *)0x42000C16U) /**< \brief (SERCOM1) SPI Interrupt Enable Set */
+#define REG_SERCOM1_SPI_INTFLAG (*(RwReg8 *)0x42000C18U) /**< \brief (SERCOM1) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM1_SPI_STATUS (*(RwReg16*)0x42000C1AU) /**< \brief (SERCOM1) SPI Status */
+#define REG_SERCOM1_SPI_SYNCBUSY (*(RoReg *)0x42000C1CU) /**< \brief (SERCOM1) SPI Syncbusy */
+#define REG_SERCOM1_SPI_ADDR (*(RwReg *)0x42000C24U) /**< \brief (SERCOM1) SPI Address */
+#define REG_SERCOM1_SPI_DATA (*(RwReg *)0x42000C28U) /**< \brief (SERCOM1) SPI Data */
+#define REG_SERCOM1_SPI_DBGCTRL (*(RwReg8 *)0x42000C30U) /**< \brief (SERCOM1) SPI Debug Control */
+#define REG_SERCOM1_USART_CTRLA (*(RwReg *)0x42000C00U) /**< \brief (SERCOM1) USART Control A */
+#define REG_SERCOM1_USART_CTRLB (*(RwReg *)0x42000C04U) /**< \brief (SERCOM1) USART Control B */
+#define REG_SERCOM1_USART_BAUD (*(RwReg16*)0x42000C0CU) /**< \brief (SERCOM1) USART Baud Rate */
+#define REG_SERCOM1_USART_RXPL (*(RwReg8 *)0x42000C0EU) /**< \brief (SERCOM1) USART Receive Pulse Length */
+#define REG_SERCOM1_USART_INTENCLR (*(RwReg8 *)0x42000C14U) /**< \brief (SERCOM1) USART Interrupt Enable Clear */
+#define REG_SERCOM1_USART_INTENSET (*(RwReg8 *)0x42000C16U) /**< \brief (SERCOM1) USART Interrupt Enable Set */
+#define REG_SERCOM1_USART_INTFLAG (*(RwReg8 *)0x42000C18U) /**< \brief (SERCOM1) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM1_USART_STATUS (*(RwReg16*)0x42000C1AU) /**< \brief (SERCOM1) USART Status */
+#define REG_SERCOM1_USART_SYNCBUSY (*(RoReg *)0x42000C1CU) /**< \brief (SERCOM1) USART Syncbusy */
+#define REG_SERCOM1_USART_DATA (*(RwReg16*)0x42000C28U) /**< \brief (SERCOM1) USART Data */
+#define REG_SERCOM1_USART_DBGCTRL (*(RwReg8 *)0x42000C30U) /**< \brief (SERCOM1) USART Debug Control */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for SERCOM1 peripheral ========== */
+#define SERCOM1_DMAC_ID_RX 3 // Index of DMA RX trigger
+#define SERCOM1_DMAC_ID_TX 4 // Index of DMA TX trigger
+#define SERCOM1_GCLK_ID_CORE 21 // Index of Generic Clock for Core
+#define SERCOM1_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout
+#define SERCOM1_INT_MSB 6
+
+#endif /* _SAMD21_SERCOM1_INSTANCE_ */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/sercom2.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/sercom2.h
new file mode 100644
index 0000000000000000000000000000000000000000..08fc6b11b06015ceb3a0257186f531ce4713f9fe
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/sercom2.h
@@ -0,0 +1,143 @@
+/**
+ * \file
+ *
+ * \brief Instance description for SERCOM2
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_SERCOM2_INSTANCE_
+#define _SAMD21_SERCOM2_INSTANCE_
+
+/* ========== Register definition for SERCOM2 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SERCOM2_I2CM_CTRLA (0x42001000U) /**< \brief (SERCOM2) I2CM Control A */
+#define REG_SERCOM2_I2CM_CTRLB (0x42001004U) /**< \brief (SERCOM2) I2CM Control B */
+#define REG_SERCOM2_I2CM_BAUD (0x4200100CU) /**< \brief (SERCOM2) I2CM Baud Rate */
+#define REG_SERCOM2_I2CM_INTENCLR (0x42001014U) /**< \brief (SERCOM2) I2CM Interrupt Enable Clear */
+#define REG_SERCOM2_I2CM_INTENSET (0x42001016U) /**< \brief (SERCOM2) I2CM Interrupt Enable Set */
+#define REG_SERCOM2_I2CM_INTFLAG (0x42001018U) /**< \brief (SERCOM2) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM2_I2CM_STATUS (0x4200101AU) /**< \brief (SERCOM2) I2CM Status */
+#define REG_SERCOM2_I2CM_SYNCBUSY (0x4200101CU) /**< \brief (SERCOM2) I2CM Syncbusy */
+#define REG_SERCOM2_I2CM_ADDR (0x42001024U) /**< \brief (SERCOM2) I2CM Address */
+#define REG_SERCOM2_I2CM_DATA (0x42001028U) /**< \brief (SERCOM2) I2CM Data */
+#define REG_SERCOM2_I2CM_DBGCTRL (0x42001030U) /**< \brief (SERCOM2) I2CM Debug Control */
+#define REG_SERCOM2_I2CS_CTRLA (0x42001000U) /**< \brief (SERCOM2) I2CS Control A */
+#define REG_SERCOM2_I2CS_CTRLB (0x42001004U) /**< \brief (SERCOM2) I2CS Control B */
+#define REG_SERCOM2_I2CS_INTENCLR (0x42001014U) /**< \brief (SERCOM2) I2CS Interrupt Enable Clear */
+#define REG_SERCOM2_I2CS_INTENSET (0x42001016U) /**< \brief (SERCOM2) I2CS Interrupt Enable Set */
+#define REG_SERCOM2_I2CS_INTFLAG (0x42001018U) /**< \brief (SERCOM2) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM2_I2CS_STATUS (0x4200101AU) /**< \brief (SERCOM2) I2CS Status */
+#define REG_SERCOM2_I2CS_SYNCBUSY (0x4200101CU) /**< \brief (SERCOM2) I2CS Syncbusy */
+#define REG_SERCOM2_I2CS_ADDR (0x42001024U) /**< \brief (SERCOM2) I2CS Address */
+#define REG_SERCOM2_I2CS_DATA (0x42001028U) /**< \brief (SERCOM2) I2CS Data */
+#define REG_SERCOM2_SPI_CTRLA (0x42001000U) /**< \brief (SERCOM2) SPI Control A */
+#define REG_SERCOM2_SPI_CTRLB (0x42001004U) /**< \brief (SERCOM2) SPI Control B */
+#define REG_SERCOM2_SPI_BAUD (0x4200100CU) /**< \brief (SERCOM2) SPI Baud Rate */
+#define REG_SERCOM2_SPI_INTENCLR (0x42001014U) /**< \brief (SERCOM2) SPI Interrupt Enable Clear */
+#define REG_SERCOM2_SPI_INTENSET (0x42001016U) /**< \brief (SERCOM2) SPI Interrupt Enable Set */
+#define REG_SERCOM2_SPI_INTFLAG (0x42001018U) /**< \brief (SERCOM2) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM2_SPI_STATUS (0x4200101AU) /**< \brief (SERCOM2) SPI Status */
+#define REG_SERCOM2_SPI_SYNCBUSY (0x4200101CU) /**< \brief (SERCOM2) SPI Syncbusy */
+#define REG_SERCOM2_SPI_ADDR (0x42001024U) /**< \brief (SERCOM2) SPI Address */
+#define REG_SERCOM2_SPI_DATA (0x42001028U) /**< \brief (SERCOM2) SPI Data */
+#define REG_SERCOM2_SPI_DBGCTRL (0x42001030U) /**< \brief (SERCOM2) SPI Debug Control */
+#define REG_SERCOM2_USART_CTRLA (0x42001000U) /**< \brief (SERCOM2) USART Control A */
+#define REG_SERCOM2_USART_CTRLB (0x42001004U) /**< \brief (SERCOM2) USART Control B */
+#define REG_SERCOM2_USART_BAUD (0x4200100CU) /**< \brief (SERCOM2) USART Baud Rate */
+#define REG_SERCOM2_USART_RXPL (0x4200100EU) /**< \brief (SERCOM2) USART Receive Pulse Length */
+#define REG_SERCOM2_USART_INTENCLR (0x42001014U) /**< \brief (SERCOM2) USART Interrupt Enable Clear */
+#define REG_SERCOM2_USART_INTENSET (0x42001016U) /**< \brief (SERCOM2) USART Interrupt Enable Set */
+#define REG_SERCOM2_USART_INTFLAG (0x42001018U) /**< \brief (SERCOM2) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM2_USART_STATUS (0x4200101AU) /**< \brief (SERCOM2) USART Status */
+#define REG_SERCOM2_USART_SYNCBUSY (0x4200101CU) /**< \brief (SERCOM2) USART Syncbusy */
+#define REG_SERCOM2_USART_DATA (0x42001028U) /**< \brief (SERCOM2) USART Data */
+#define REG_SERCOM2_USART_DBGCTRL (0x42001030U) /**< \brief (SERCOM2) USART Debug Control */
+#else
+#define REG_SERCOM2_I2CM_CTRLA (*(RwReg *)0x42001000U) /**< \brief (SERCOM2) I2CM Control A */
+#define REG_SERCOM2_I2CM_CTRLB (*(RwReg *)0x42001004U) /**< \brief (SERCOM2) I2CM Control B */
+#define REG_SERCOM2_I2CM_BAUD (*(RwReg *)0x4200100CU) /**< \brief (SERCOM2) I2CM Baud Rate */
+#define REG_SERCOM2_I2CM_INTENCLR (*(RwReg8 *)0x42001014U) /**< \brief (SERCOM2) I2CM Interrupt Enable Clear */
+#define REG_SERCOM2_I2CM_INTENSET (*(RwReg8 *)0x42001016U) /**< \brief (SERCOM2) I2CM Interrupt Enable Set */
+#define REG_SERCOM2_I2CM_INTFLAG (*(RwReg8 *)0x42001018U) /**< \brief (SERCOM2) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM2_I2CM_STATUS (*(RwReg16*)0x4200101AU) /**< \brief (SERCOM2) I2CM Status */
+#define REG_SERCOM2_I2CM_SYNCBUSY (*(RoReg *)0x4200101CU) /**< \brief (SERCOM2) I2CM Syncbusy */
+#define REG_SERCOM2_I2CM_ADDR (*(RwReg *)0x42001024U) /**< \brief (SERCOM2) I2CM Address */
+#define REG_SERCOM2_I2CM_DATA (*(RwReg8 *)0x42001028U) /**< \brief (SERCOM2) I2CM Data */
+#define REG_SERCOM2_I2CM_DBGCTRL (*(RwReg8 *)0x42001030U) /**< \brief (SERCOM2) I2CM Debug Control */
+#define REG_SERCOM2_I2CS_CTRLA (*(RwReg *)0x42001000U) /**< \brief (SERCOM2) I2CS Control A */
+#define REG_SERCOM2_I2CS_CTRLB (*(RwReg *)0x42001004U) /**< \brief (SERCOM2) I2CS Control B */
+#define REG_SERCOM2_I2CS_INTENCLR (*(RwReg8 *)0x42001014U) /**< \brief (SERCOM2) I2CS Interrupt Enable Clear */
+#define REG_SERCOM2_I2CS_INTENSET (*(RwReg8 *)0x42001016U) /**< \brief (SERCOM2) I2CS Interrupt Enable Set */
+#define REG_SERCOM2_I2CS_INTFLAG (*(RwReg8 *)0x42001018U) /**< \brief (SERCOM2) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM2_I2CS_STATUS (*(RwReg16*)0x4200101AU) /**< \brief (SERCOM2) I2CS Status */
+#define REG_SERCOM2_I2CS_SYNCBUSY (*(RoReg *)0x4200101CU) /**< \brief (SERCOM2) I2CS Syncbusy */
+#define REG_SERCOM2_I2CS_ADDR (*(RwReg *)0x42001024U) /**< \brief (SERCOM2) I2CS Address */
+#define REG_SERCOM2_I2CS_DATA (*(RwReg8 *)0x42001028U) /**< \brief (SERCOM2) I2CS Data */
+#define REG_SERCOM2_SPI_CTRLA (*(RwReg *)0x42001000U) /**< \brief (SERCOM2) SPI Control A */
+#define REG_SERCOM2_SPI_CTRLB (*(RwReg *)0x42001004U) /**< \brief (SERCOM2) SPI Control B */
+#define REG_SERCOM2_SPI_BAUD (*(RwReg8 *)0x4200100CU) /**< \brief (SERCOM2) SPI Baud Rate */
+#define REG_SERCOM2_SPI_INTENCLR (*(RwReg8 *)0x42001014U) /**< \brief (SERCOM2) SPI Interrupt Enable Clear */
+#define REG_SERCOM2_SPI_INTENSET (*(RwReg8 *)0x42001016U) /**< \brief (SERCOM2) SPI Interrupt Enable Set */
+#define REG_SERCOM2_SPI_INTFLAG (*(RwReg8 *)0x42001018U) /**< \brief (SERCOM2) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM2_SPI_STATUS (*(RwReg16*)0x4200101AU) /**< \brief (SERCOM2) SPI Status */
+#define REG_SERCOM2_SPI_SYNCBUSY (*(RoReg *)0x4200101CU) /**< \brief (SERCOM2) SPI Syncbusy */
+#define REG_SERCOM2_SPI_ADDR (*(RwReg *)0x42001024U) /**< \brief (SERCOM2) SPI Address */
+#define REG_SERCOM2_SPI_DATA (*(RwReg *)0x42001028U) /**< \brief (SERCOM2) SPI Data */
+#define REG_SERCOM2_SPI_DBGCTRL (*(RwReg8 *)0x42001030U) /**< \brief (SERCOM2) SPI Debug Control */
+#define REG_SERCOM2_USART_CTRLA (*(RwReg *)0x42001000U) /**< \brief (SERCOM2) USART Control A */
+#define REG_SERCOM2_USART_CTRLB (*(RwReg *)0x42001004U) /**< \brief (SERCOM2) USART Control B */
+#define REG_SERCOM2_USART_BAUD (*(RwReg16*)0x4200100CU) /**< \brief (SERCOM2) USART Baud Rate */
+#define REG_SERCOM2_USART_RXPL (*(RwReg8 *)0x4200100EU) /**< \brief (SERCOM2) USART Receive Pulse Length */
+#define REG_SERCOM2_USART_INTENCLR (*(RwReg8 *)0x42001014U) /**< \brief (SERCOM2) USART Interrupt Enable Clear */
+#define REG_SERCOM2_USART_INTENSET (*(RwReg8 *)0x42001016U) /**< \brief (SERCOM2) USART Interrupt Enable Set */
+#define REG_SERCOM2_USART_INTFLAG (*(RwReg8 *)0x42001018U) /**< \brief (SERCOM2) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM2_USART_STATUS (*(RwReg16*)0x4200101AU) /**< \brief (SERCOM2) USART Status */
+#define REG_SERCOM2_USART_SYNCBUSY (*(RoReg *)0x4200101CU) /**< \brief (SERCOM2) USART Syncbusy */
+#define REG_SERCOM2_USART_DATA (*(RwReg16*)0x42001028U) /**< \brief (SERCOM2) USART Data */
+#define REG_SERCOM2_USART_DBGCTRL (*(RwReg8 *)0x42001030U) /**< \brief (SERCOM2) USART Debug Control */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for SERCOM2 peripheral ========== */
+#define SERCOM2_DMAC_ID_RX 5 // Index of DMA RX trigger
+#define SERCOM2_DMAC_ID_TX 6 // Index of DMA TX trigger
+#define SERCOM2_GCLK_ID_CORE 22 // Index of Generic Clock for Core
+#define SERCOM2_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout
+#define SERCOM2_INT_MSB 6
+
+#endif /* _SAMD21_SERCOM2_INSTANCE_ */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/sercom3.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/sercom3.h
new file mode 100644
index 0000000000000000000000000000000000000000..5b9e0b329374aff70d937539f89d0b6dcbfba58b
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/sercom3.h
@@ -0,0 +1,143 @@
+/**
+ * \file
+ *
+ * \brief Instance description for SERCOM3
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_SERCOM3_INSTANCE_
+#define _SAMD21_SERCOM3_INSTANCE_
+
+/* ========== Register definition for SERCOM3 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SERCOM3_I2CM_CTRLA (0x42001400U) /**< \brief (SERCOM3) I2CM Control A */
+#define REG_SERCOM3_I2CM_CTRLB (0x42001404U) /**< \brief (SERCOM3) I2CM Control B */
+#define REG_SERCOM3_I2CM_BAUD (0x4200140CU) /**< \brief (SERCOM3) I2CM Baud Rate */
+#define REG_SERCOM3_I2CM_INTENCLR (0x42001414U) /**< \brief (SERCOM3) I2CM Interrupt Enable Clear */
+#define REG_SERCOM3_I2CM_INTENSET (0x42001416U) /**< \brief (SERCOM3) I2CM Interrupt Enable Set */
+#define REG_SERCOM3_I2CM_INTFLAG (0x42001418U) /**< \brief (SERCOM3) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM3_I2CM_STATUS (0x4200141AU) /**< \brief (SERCOM3) I2CM Status */
+#define REG_SERCOM3_I2CM_SYNCBUSY (0x4200141CU) /**< \brief (SERCOM3) I2CM Syncbusy */
+#define REG_SERCOM3_I2CM_ADDR (0x42001424U) /**< \brief (SERCOM3) I2CM Address */
+#define REG_SERCOM3_I2CM_DATA (0x42001428U) /**< \brief (SERCOM3) I2CM Data */
+#define REG_SERCOM3_I2CM_DBGCTRL (0x42001430U) /**< \brief (SERCOM3) I2CM Debug Control */
+#define REG_SERCOM3_I2CS_CTRLA (0x42001400U) /**< \brief (SERCOM3) I2CS Control A */
+#define REG_SERCOM3_I2CS_CTRLB (0x42001404U) /**< \brief (SERCOM3) I2CS Control B */
+#define REG_SERCOM3_I2CS_INTENCLR (0x42001414U) /**< \brief (SERCOM3) I2CS Interrupt Enable Clear */
+#define REG_SERCOM3_I2CS_INTENSET (0x42001416U) /**< \brief (SERCOM3) I2CS Interrupt Enable Set */
+#define REG_SERCOM3_I2CS_INTFLAG (0x42001418U) /**< \brief (SERCOM3) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM3_I2CS_STATUS (0x4200141AU) /**< \brief (SERCOM3) I2CS Status */
+#define REG_SERCOM3_I2CS_SYNCBUSY (0x4200141CU) /**< \brief (SERCOM3) I2CS Syncbusy */
+#define REG_SERCOM3_I2CS_ADDR (0x42001424U) /**< \brief (SERCOM3) I2CS Address */
+#define REG_SERCOM3_I2CS_DATA (0x42001428U) /**< \brief (SERCOM3) I2CS Data */
+#define REG_SERCOM3_SPI_CTRLA (0x42001400U) /**< \brief (SERCOM3) SPI Control A */
+#define REG_SERCOM3_SPI_CTRLB (0x42001404U) /**< \brief (SERCOM3) SPI Control B */
+#define REG_SERCOM3_SPI_BAUD (0x4200140CU) /**< \brief (SERCOM3) SPI Baud Rate */
+#define REG_SERCOM3_SPI_INTENCLR (0x42001414U) /**< \brief (SERCOM3) SPI Interrupt Enable Clear */
+#define REG_SERCOM3_SPI_INTENSET (0x42001416U) /**< \brief (SERCOM3) SPI Interrupt Enable Set */
+#define REG_SERCOM3_SPI_INTFLAG (0x42001418U) /**< \brief (SERCOM3) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM3_SPI_STATUS (0x4200141AU) /**< \brief (SERCOM3) SPI Status */
+#define REG_SERCOM3_SPI_SYNCBUSY (0x4200141CU) /**< \brief (SERCOM3) SPI Syncbusy */
+#define REG_SERCOM3_SPI_ADDR (0x42001424U) /**< \brief (SERCOM3) SPI Address */
+#define REG_SERCOM3_SPI_DATA (0x42001428U) /**< \brief (SERCOM3) SPI Data */
+#define REG_SERCOM3_SPI_DBGCTRL (0x42001430U) /**< \brief (SERCOM3) SPI Debug Control */
+#define REG_SERCOM3_USART_CTRLA (0x42001400U) /**< \brief (SERCOM3) USART Control A */
+#define REG_SERCOM3_USART_CTRLB (0x42001404U) /**< \brief (SERCOM3) USART Control B */
+#define REG_SERCOM3_USART_BAUD (0x4200140CU) /**< \brief (SERCOM3) USART Baud Rate */
+#define REG_SERCOM3_USART_RXPL (0x4200140EU) /**< \brief (SERCOM3) USART Receive Pulse Length */
+#define REG_SERCOM3_USART_INTENCLR (0x42001414U) /**< \brief (SERCOM3) USART Interrupt Enable Clear */
+#define REG_SERCOM3_USART_INTENSET (0x42001416U) /**< \brief (SERCOM3) USART Interrupt Enable Set */
+#define REG_SERCOM3_USART_INTFLAG (0x42001418U) /**< \brief (SERCOM3) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM3_USART_STATUS (0x4200141AU) /**< \brief (SERCOM3) USART Status */
+#define REG_SERCOM3_USART_SYNCBUSY (0x4200141CU) /**< \brief (SERCOM3) USART Syncbusy */
+#define REG_SERCOM3_USART_DATA (0x42001428U) /**< \brief (SERCOM3) USART Data */
+#define REG_SERCOM3_USART_DBGCTRL (0x42001430U) /**< \brief (SERCOM3) USART Debug Control */
+#else
+#define REG_SERCOM3_I2CM_CTRLA (*(RwReg *)0x42001400U) /**< \brief (SERCOM3) I2CM Control A */
+#define REG_SERCOM3_I2CM_CTRLB (*(RwReg *)0x42001404U) /**< \brief (SERCOM3) I2CM Control B */
+#define REG_SERCOM3_I2CM_BAUD (*(RwReg *)0x4200140CU) /**< \brief (SERCOM3) I2CM Baud Rate */
+#define REG_SERCOM3_I2CM_INTENCLR (*(RwReg8 *)0x42001414U) /**< \brief (SERCOM3) I2CM Interrupt Enable Clear */
+#define REG_SERCOM3_I2CM_INTENSET (*(RwReg8 *)0x42001416U) /**< \brief (SERCOM3) I2CM Interrupt Enable Set */
+#define REG_SERCOM3_I2CM_INTFLAG (*(RwReg8 *)0x42001418U) /**< \brief (SERCOM3) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM3_I2CM_STATUS (*(RwReg16*)0x4200141AU) /**< \brief (SERCOM3) I2CM Status */
+#define REG_SERCOM3_I2CM_SYNCBUSY (*(RoReg *)0x4200141CU) /**< \brief (SERCOM3) I2CM Syncbusy */
+#define REG_SERCOM3_I2CM_ADDR (*(RwReg *)0x42001424U) /**< \brief (SERCOM3) I2CM Address */
+#define REG_SERCOM3_I2CM_DATA (*(RwReg8 *)0x42001428U) /**< \brief (SERCOM3) I2CM Data */
+#define REG_SERCOM3_I2CM_DBGCTRL (*(RwReg8 *)0x42001430U) /**< \brief (SERCOM3) I2CM Debug Control */
+#define REG_SERCOM3_I2CS_CTRLA (*(RwReg *)0x42001400U) /**< \brief (SERCOM3) I2CS Control A */
+#define REG_SERCOM3_I2CS_CTRLB (*(RwReg *)0x42001404U) /**< \brief (SERCOM3) I2CS Control B */
+#define REG_SERCOM3_I2CS_INTENCLR (*(RwReg8 *)0x42001414U) /**< \brief (SERCOM3) I2CS Interrupt Enable Clear */
+#define REG_SERCOM3_I2CS_INTENSET (*(RwReg8 *)0x42001416U) /**< \brief (SERCOM3) I2CS Interrupt Enable Set */
+#define REG_SERCOM3_I2CS_INTFLAG (*(RwReg8 *)0x42001418U) /**< \brief (SERCOM3) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM3_I2CS_STATUS (*(RwReg16*)0x4200141AU) /**< \brief (SERCOM3) I2CS Status */
+#define REG_SERCOM3_I2CS_SYNCBUSY (*(RoReg *)0x4200141CU) /**< \brief (SERCOM3) I2CS Syncbusy */
+#define REG_SERCOM3_I2CS_ADDR (*(RwReg *)0x42001424U) /**< \brief (SERCOM3) I2CS Address */
+#define REG_SERCOM3_I2CS_DATA (*(RwReg8 *)0x42001428U) /**< \brief (SERCOM3) I2CS Data */
+#define REG_SERCOM3_SPI_CTRLA (*(RwReg *)0x42001400U) /**< \brief (SERCOM3) SPI Control A */
+#define REG_SERCOM3_SPI_CTRLB (*(RwReg *)0x42001404U) /**< \brief (SERCOM3) SPI Control B */
+#define REG_SERCOM3_SPI_BAUD (*(RwReg8 *)0x4200140CU) /**< \brief (SERCOM3) SPI Baud Rate */
+#define REG_SERCOM3_SPI_INTENCLR (*(RwReg8 *)0x42001414U) /**< \brief (SERCOM3) SPI Interrupt Enable Clear */
+#define REG_SERCOM3_SPI_INTENSET (*(RwReg8 *)0x42001416U) /**< \brief (SERCOM3) SPI Interrupt Enable Set */
+#define REG_SERCOM3_SPI_INTFLAG (*(RwReg8 *)0x42001418U) /**< \brief (SERCOM3) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM3_SPI_STATUS (*(RwReg16*)0x4200141AU) /**< \brief (SERCOM3) SPI Status */
+#define REG_SERCOM3_SPI_SYNCBUSY (*(RoReg *)0x4200141CU) /**< \brief (SERCOM3) SPI Syncbusy */
+#define REG_SERCOM3_SPI_ADDR (*(RwReg *)0x42001424U) /**< \brief (SERCOM3) SPI Address */
+#define REG_SERCOM3_SPI_DATA (*(RwReg *)0x42001428U) /**< \brief (SERCOM3) SPI Data */
+#define REG_SERCOM3_SPI_DBGCTRL (*(RwReg8 *)0x42001430U) /**< \brief (SERCOM3) SPI Debug Control */
+#define REG_SERCOM3_USART_CTRLA (*(RwReg *)0x42001400U) /**< \brief (SERCOM3) USART Control A */
+#define REG_SERCOM3_USART_CTRLB (*(RwReg *)0x42001404U) /**< \brief (SERCOM3) USART Control B */
+#define REG_SERCOM3_USART_BAUD (*(RwReg16*)0x4200140CU) /**< \brief (SERCOM3) USART Baud Rate */
+#define REG_SERCOM3_USART_RXPL (*(RwReg8 *)0x4200140EU) /**< \brief (SERCOM3) USART Receive Pulse Length */
+#define REG_SERCOM3_USART_INTENCLR (*(RwReg8 *)0x42001414U) /**< \brief (SERCOM3) USART Interrupt Enable Clear */
+#define REG_SERCOM3_USART_INTENSET (*(RwReg8 *)0x42001416U) /**< \brief (SERCOM3) USART Interrupt Enable Set */
+#define REG_SERCOM3_USART_INTFLAG (*(RwReg8 *)0x42001418U) /**< \brief (SERCOM3) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM3_USART_STATUS (*(RwReg16*)0x4200141AU) /**< \brief (SERCOM3) USART Status */
+#define REG_SERCOM3_USART_SYNCBUSY (*(RoReg *)0x4200141CU) /**< \brief (SERCOM3) USART Syncbusy */
+#define REG_SERCOM3_USART_DATA (*(RwReg16*)0x42001428U) /**< \brief (SERCOM3) USART Data */
+#define REG_SERCOM3_USART_DBGCTRL (*(RwReg8 *)0x42001430U) /**< \brief (SERCOM3) USART Debug Control */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for SERCOM3 peripheral ========== */
+#define SERCOM3_DMAC_ID_RX 7 // Index of DMA RX trigger
+#define SERCOM3_DMAC_ID_TX 8 // Index of DMA TX trigger
+#define SERCOM3_GCLK_ID_CORE 23 // Index of Generic Clock for Core
+#define SERCOM3_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout
+#define SERCOM3_INT_MSB 6
+
+#endif /* _SAMD21_SERCOM3_INSTANCE_ */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/sercom4.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/sercom4.h
new file mode 100644
index 0000000000000000000000000000000000000000..77da7caec7e6a2414566021804451b53dd5f358e
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/sercom4.h
@@ -0,0 +1,143 @@
+/**
+ * \file
+ *
+ * \brief Instance description for SERCOM4
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_SERCOM4_INSTANCE_
+#define _SAMD21_SERCOM4_INSTANCE_
+
+/* ========== Register definition for SERCOM4 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SERCOM4_I2CM_CTRLA (0x42001800U) /**< \brief (SERCOM4) I2CM Control A */
+#define REG_SERCOM4_I2CM_CTRLB (0x42001804U) /**< \brief (SERCOM4) I2CM Control B */
+#define REG_SERCOM4_I2CM_BAUD (0x4200180CU) /**< \brief (SERCOM4) I2CM Baud Rate */
+#define REG_SERCOM4_I2CM_INTENCLR (0x42001814U) /**< \brief (SERCOM4) I2CM Interrupt Enable Clear */
+#define REG_SERCOM4_I2CM_INTENSET (0x42001816U) /**< \brief (SERCOM4) I2CM Interrupt Enable Set */
+#define REG_SERCOM4_I2CM_INTFLAG (0x42001818U) /**< \brief (SERCOM4) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM4_I2CM_STATUS (0x4200181AU) /**< \brief (SERCOM4) I2CM Status */
+#define REG_SERCOM4_I2CM_SYNCBUSY (0x4200181CU) /**< \brief (SERCOM4) I2CM Syncbusy */
+#define REG_SERCOM4_I2CM_ADDR (0x42001824U) /**< \brief (SERCOM4) I2CM Address */
+#define REG_SERCOM4_I2CM_DATA (0x42001828U) /**< \brief (SERCOM4) I2CM Data */
+#define REG_SERCOM4_I2CM_DBGCTRL (0x42001830U) /**< \brief (SERCOM4) I2CM Debug Control */
+#define REG_SERCOM4_I2CS_CTRLA (0x42001800U) /**< \brief (SERCOM4) I2CS Control A */
+#define REG_SERCOM4_I2CS_CTRLB (0x42001804U) /**< \brief (SERCOM4) I2CS Control B */
+#define REG_SERCOM4_I2CS_INTENCLR (0x42001814U) /**< \brief (SERCOM4) I2CS Interrupt Enable Clear */
+#define REG_SERCOM4_I2CS_INTENSET (0x42001816U) /**< \brief (SERCOM4) I2CS Interrupt Enable Set */
+#define REG_SERCOM4_I2CS_INTFLAG (0x42001818U) /**< \brief (SERCOM4) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM4_I2CS_STATUS (0x4200181AU) /**< \brief (SERCOM4) I2CS Status */
+#define REG_SERCOM4_I2CS_SYNCBUSY (0x4200181CU) /**< \brief (SERCOM4) I2CS Syncbusy */
+#define REG_SERCOM4_I2CS_ADDR (0x42001824U) /**< \brief (SERCOM4) I2CS Address */
+#define REG_SERCOM4_I2CS_DATA (0x42001828U) /**< \brief (SERCOM4) I2CS Data */
+#define REG_SERCOM4_SPI_CTRLA (0x42001800U) /**< \brief (SERCOM4) SPI Control A */
+#define REG_SERCOM4_SPI_CTRLB (0x42001804U) /**< \brief (SERCOM4) SPI Control B */
+#define REG_SERCOM4_SPI_BAUD (0x4200180CU) /**< \brief (SERCOM4) SPI Baud Rate */
+#define REG_SERCOM4_SPI_INTENCLR (0x42001814U) /**< \brief (SERCOM4) SPI Interrupt Enable Clear */
+#define REG_SERCOM4_SPI_INTENSET (0x42001816U) /**< \brief (SERCOM4) SPI Interrupt Enable Set */
+#define REG_SERCOM4_SPI_INTFLAG (0x42001818U) /**< \brief (SERCOM4) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM4_SPI_STATUS (0x4200181AU) /**< \brief (SERCOM4) SPI Status */
+#define REG_SERCOM4_SPI_SYNCBUSY (0x4200181CU) /**< \brief (SERCOM4) SPI Syncbusy */
+#define REG_SERCOM4_SPI_ADDR (0x42001824U) /**< \brief (SERCOM4) SPI Address */
+#define REG_SERCOM4_SPI_DATA (0x42001828U) /**< \brief (SERCOM4) SPI Data */
+#define REG_SERCOM4_SPI_DBGCTRL (0x42001830U) /**< \brief (SERCOM4) SPI Debug Control */
+#define REG_SERCOM4_USART_CTRLA (0x42001800U) /**< \brief (SERCOM4) USART Control A */
+#define REG_SERCOM4_USART_CTRLB (0x42001804U) /**< \brief (SERCOM4) USART Control B */
+#define REG_SERCOM4_USART_BAUD (0x4200180CU) /**< \brief (SERCOM4) USART Baud Rate */
+#define REG_SERCOM4_USART_RXPL (0x4200180EU) /**< \brief (SERCOM4) USART Receive Pulse Length */
+#define REG_SERCOM4_USART_INTENCLR (0x42001814U) /**< \brief (SERCOM4) USART Interrupt Enable Clear */
+#define REG_SERCOM4_USART_INTENSET (0x42001816U) /**< \brief (SERCOM4) USART Interrupt Enable Set */
+#define REG_SERCOM4_USART_INTFLAG (0x42001818U) /**< \brief (SERCOM4) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM4_USART_STATUS (0x4200181AU) /**< \brief (SERCOM4) USART Status */
+#define REG_SERCOM4_USART_SYNCBUSY (0x4200181CU) /**< \brief (SERCOM4) USART Syncbusy */
+#define REG_SERCOM4_USART_DATA (0x42001828U) /**< \brief (SERCOM4) USART Data */
+#define REG_SERCOM4_USART_DBGCTRL (0x42001830U) /**< \brief (SERCOM4) USART Debug Control */
+#else
+#define REG_SERCOM4_I2CM_CTRLA (*(RwReg *)0x42001800U) /**< \brief (SERCOM4) I2CM Control A */
+#define REG_SERCOM4_I2CM_CTRLB (*(RwReg *)0x42001804U) /**< \brief (SERCOM4) I2CM Control B */
+#define REG_SERCOM4_I2CM_BAUD (*(RwReg *)0x4200180CU) /**< \brief (SERCOM4) I2CM Baud Rate */
+#define REG_SERCOM4_I2CM_INTENCLR (*(RwReg8 *)0x42001814U) /**< \brief (SERCOM4) I2CM Interrupt Enable Clear */
+#define REG_SERCOM4_I2CM_INTENSET (*(RwReg8 *)0x42001816U) /**< \brief (SERCOM4) I2CM Interrupt Enable Set */
+#define REG_SERCOM4_I2CM_INTFLAG (*(RwReg8 *)0x42001818U) /**< \brief (SERCOM4) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM4_I2CM_STATUS (*(RwReg16*)0x4200181AU) /**< \brief (SERCOM4) I2CM Status */
+#define REG_SERCOM4_I2CM_SYNCBUSY (*(RoReg *)0x4200181CU) /**< \brief (SERCOM4) I2CM Syncbusy */
+#define REG_SERCOM4_I2CM_ADDR (*(RwReg *)0x42001824U) /**< \brief (SERCOM4) I2CM Address */
+#define REG_SERCOM4_I2CM_DATA (*(RwReg8 *)0x42001828U) /**< \brief (SERCOM4) I2CM Data */
+#define REG_SERCOM4_I2CM_DBGCTRL (*(RwReg8 *)0x42001830U) /**< \brief (SERCOM4) I2CM Debug Control */
+#define REG_SERCOM4_I2CS_CTRLA (*(RwReg *)0x42001800U) /**< \brief (SERCOM4) I2CS Control A */
+#define REG_SERCOM4_I2CS_CTRLB (*(RwReg *)0x42001804U) /**< \brief (SERCOM4) I2CS Control B */
+#define REG_SERCOM4_I2CS_INTENCLR (*(RwReg8 *)0x42001814U) /**< \brief (SERCOM4) I2CS Interrupt Enable Clear */
+#define REG_SERCOM4_I2CS_INTENSET (*(RwReg8 *)0x42001816U) /**< \brief (SERCOM4) I2CS Interrupt Enable Set */
+#define REG_SERCOM4_I2CS_INTFLAG (*(RwReg8 *)0x42001818U) /**< \brief (SERCOM4) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM4_I2CS_STATUS (*(RwReg16*)0x4200181AU) /**< \brief (SERCOM4) I2CS Status */
+#define REG_SERCOM4_I2CS_SYNCBUSY (*(RoReg *)0x4200181CU) /**< \brief (SERCOM4) I2CS Syncbusy */
+#define REG_SERCOM4_I2CS_ADDR (*(RwReg *)0x42001824U) /**< \brief (SERCOM4) I2CS Address */
+#define REG_SERCOM4_I2CS_DATA (*(RwReg8 *)0x42001828U) /**< \brief (SERCOM4) I2CS Data */
+#define REG_SERCOM4_SPI_CTRLA (*(RwReg *)0x42001800U) /**< \brief (SERCOM4) SPI Control A */
+#define REG_SERCOM4_SPI_CTRLB (*(RwReg *)0x42001804U) /**< \brief (SERCOM4) SPI Control B */
+#define REG_SERCOM4_SPI_BAUD (*(RwReg8 *)0x4200180CU) /**< \brief (SERCOM4) SPI Baud Rate */
+#define REG_SERCOM4_SPI_INTENCLR (*(RwReg8 *)0x42001814U) /**< \brief (SERCOM4) SPI Interrupt Enable Clear */
+#define REG_SERCOM4_SPI_INTENSET (*(RwReg8 *)0x42001816U) /**< \brief (SERCOM4) SPI Interrupt Enable Set */
+#define REG_SERCOM4_SPI_INTFLAG (*(RwReg8 *)0x42001818U) /**< \brief (SERCOM4) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM4_SPI_STATUS (*(RwReg16*)0x4200181AU) /**< \brief (SERCOM4) SPI Status */
+#define REG_SERCOM4_SPI_SYNCBUSY (*(RoReg *)0x4200181CU) /**< \brief (SERCOM4) SPI Syncbusy */
+#define REG_SERCOM4_SPI_ADDR (*(RwReg *)0x42001824U) /**< \brief (SERCOM4) SPI Address */
+#define REG_SERCOM4_SPI_DATA (*(RwReg *)0x42001828U) /**< \brief (SERCOM4) SPI Data */
+#define REG_SERCOM4_SPI_DBGCTRL (*(RwReg8 *)0x42001830U) /**< \brief (SERCOM4) SPI Debug Control */
+#define REG_SERCOM4_USART_CTRLA (*(RwReg *)0x42001800U) /**< \brief (SERCOM4) USART Control A */
+#define REG_SERCOM4_USART_CTRLB (*(RwReg *)0x42001804U) /**< \brief (SERCOM4) USART Control B */
+#define REG_SERCOM4_USART_BAUD (*(RwReg16*)0x4200180CU) /**< \brief (SERCOM4) USART Baud Rate */
+#define REG_SERCOM4_USART_RXPL (*(RwReg8 *)0x4200180EU) /**< \brief (SERCOM4) USART Receive Pulse Length */
+#define REG_SERCOM4_USART_INTENCLR (*(RwReg8 *)0x42001814U) /**< \brief (SERCOM4) USART Interrupt Enable Clear */
+#define REG_SERCOM4_USART_INTENSET (*(RwReg8 *)0x42001816U) /**< \brief (SERCOM4) USART Interrupt Enable Set */
+#define REG_SERCOM4_USART_INTFLAG (*(RwReg8 *)0x42001818U) /**< \brief (SERCOM4) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM4_USART_STATUS (*(RwReg16*)0x4200181AU) /**< \brief (SERCOM4) USART Status */
+#define REG_SERCOM4_USART_SYNCBUSY (*(RoReg *)0x4200181CU) /**< \brief (SERCOM4) USART Syncbusy */
+#define REG_SERCOM4_USART_DATA (*(RwReg16*)0x42001828U) /**< \brief (SERCOM4) USART Data */
+#define REG_SERCOM4_USART_DBGCTRL (*(RwReg8 *)0x42001830U) /**< \brief (SERCOM4) USART Debug Control */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for SERCOM4 peripheral ========== */
+#define SERCOM4_DMAC_ID_RX 9 // Index of DMA RX trigger
+#define SERCOM4_DMAC_ID_TX 10 // Index of DMA TX trigger
+#define SERCOM4_GCLK_ID_CORE 24 // Index of Generic Clock for Core
+#define SERCOM4_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout
+#define SERCOM4_INT_MSB 6
+
+#endif /* _SAMD21_SERCOM4_INSTANCE_ */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/sercom5.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/sercom5.h
new file mode 100644
index 0000000000000000000000000000000000000000..0baafd85c90512a0ddcb47f3fd8d16d1ffc9b71e
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/sercom5.h
@@ -0,0 +1,143 @@
+/**
+ * \file
+ *
+ * \brief Instance description for SERCOM5
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_SERCOM5_INSTANCE_
+#define _SAMD21_SERCOM5_INSTANCE_
+
+/* ========== Register definition for SERCOM5 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SERCOM5_I2CM_CTRLA (0x42001C00U) /**< \brief (SERCOM5) I2CM Control A */
+#define REG_SERCOM5_I2CM_CTRLB (0x42001C04U) /**< \brief (SERCOM5) I2CM Control B */
+#define REG_SERCOM5_I2CM_BAUD (0x42001C0CU) /**< \brief (SERCOM5) I2CM Baud Rate */
+#define REG_SERCOM5_I2CM_INTENCLR (0x42001C14U) /**< \brief (SERCOM5) I2CM Interrupt Enable Clear */
+#define REG_SERCOM5_I2CM_INTENSET (0x42001C16U) /**< \brief (SERCOM5) I2CM Interrupt Enable Set */
+#define REG_SERCOM5_I2CM_INTFLAG (0x42001C18U) /**< \brief (SERCOM5) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM5_I2CM_STATUS (0x42001C1AU) /**< \brief (SERCOM5) I2CM Status */
+#define REG_SERCOM5_I2CM_SYNCBUSY (0x42001C1CU) /**< \brief (SERCOM5) I2CM Syncbusy */
+#define REG_SERCOM5_I2CM_ADDR (0x42001C24U) /**< \brief (SERCOM5) I2CM Address */
+#define REG_SERCOM5_I2CM_DATA (0x42001C28U) /**< \brief (SERCOM5) I2CM Data */
+#define REG_SERCOM5_I2CM_DBGCTRL (0x42001C30U) /**< \brief (SERCOM5) I2CM Debug Control */
+#define REG_SERCOM5_I2CS_CTRLA (0x42001C00U) /**< \brief (SERCOM5) I2CS Control A */
+#define REG_SERCOM5_I2CS_CTRLB (0x42001C04U) /**< \brief (SERCOM5) I2CS Control B */
+#define REG_SERCOM5_I2CS_INTENCLR (0x42001C14U) /**< \brief (SERCOM5) I2CS Interrupt Enable Clear */
+#define REG_SERCOM5_I2CS_INTENSET (0x42001C16U) /**< \brief (SERCOM5) I2CS Interrupt Enable Set */
+#define REG_SERCOM5_I2CS_INTFLAG (0x42001C18U) /**< \brief (SERCOM5) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM5_I2CS_STATUS (0x42001C1AU) /**< \brief (SERCOM5) I2CS Status */
+#define REG_SERCOM5_I2CS_SYNCBUSY (0x42001C1CU) /**< \brief (SERCOM5) I2CS Syncbusy */
+#define REG_SERCOM5_I2CS_ADDR (0x42001C24U) /**< \brief (SERCOM5) I2CS Address */
+#define REG_SERCOM5_I2CS_DATA (0x42001C28U) /**< \brief (SERCOM5) I2CS Data */
+#define REG_SERCOM5_SPI_CTRLA (0x42001C00U) /**< \brief (SERCOM5) SPI Control A */
+#define REG_SERCOM5_SPI_CTRLB (0x42001C04U) /**< \brief (SERCOM5) SPI Control B */
+#define REG_SERCOM5_SPI_BAUD (0x42001C0CU) /**< \brief (SERCOM5) SPI Baud Rate */
+#define REG_SERCOM5_SPI_INTENCLR (0x42001C14U) /**< \brief (SERCOM5) SPI Interrupt Enable Clear */
+#define REG_SERCOM5_SPI_INTENSET (0x42001C16U) /**< \brief (SERCOM5) SPI Interrupt Enable Set */
+#define REG_SERCOM5_SPI_INTFLAG (0x42001C18U) /**< \brief (SERCOM5) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM5_SPI_STATUS (0x42001C1AU) /**< \brief (SERCOM5) SPI Status */
+#define REG_SERCOM5_SPI_SYNCBUSY (0x42001C1CU) /**< \brief (SERCOM5) SPI Syncbusy */
+#define REG_SERCOM5_SPI_ADDR (0x42001C24U) /**< \brief (SERCOM5) SPI Address */
+#define REG_SERCOM5_SPI_DATA (0x42001C28U) /**< \brief (SERCOM5) SPI Data */
+#define REG_SERCOM5_SPI_DBGCTRL (0x42001C30U) /**< \brief (SERCOM5) SPI Debug Control */
+#define REG_SERCOM5_USART_CTRLA (0x42001C00U) /**< \brief (SERCOM5) USART Control A */
+#define REG_SERCOM5_USART_CTRLB (0x42001C04U) /**< \brief (SERCOM5) USART Control B */
+#define REG_SERCOM5_USART_BAUD (0x42001C0CU) /**< \brief (SERCOM5) USART Baud Rate */
+#define REG_SERCOM5_USART_RXPL (0x42001C0EU) /**< \brief (SERCOM5) USART Receive Pulse Length */
+#define REG_SERCOM5_USART_INTENCLR (0x42001C14U) /**< \brief (SERCOM5) USART Interrupt Enable Clear */
+#define REG_SERCOM5_USART_INTENSET (0x42001C16U) /**< \brief (SERCOM5) USART Interrupt Enable Set */
+#define REG_SERCOM5_USART_INTFLAG (0x42001C18U) /**< \brief (SERCOM5) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM5_USART_STATUS (0x42001C1AU) /**< \brief (SERCOM5) USART Status */
+#define REG_SERCOM5_USART_SYNCBUSY (0x42001C1CU) /**< \brief (SERCOM5) USART Syncbusy */
+#define REG_SERCOM5_USART_DATA (0x42001C28U) /**< \brief (SERCOM5) USART Data */
+#define REG_SERCOM5_USART_DBGCTRL (0x42001C30U) /**< \brief (SERCOM5) USART Debug Control */
+#else
+#define REG_SERCOM5_I2CM_CTRLA (*(RwReg *)0x42001C00U) /**< \brief (SERCOM5) I2CM Control A */
+#define REG_SERCOM5_I2CM_CTRLB (*(RwReg *)0x42001C04U) /**< \brief (SERCOM5) I2CM Control B */
+#define REG_SERCOM5_I2CM_BAUD (*(RwReg *)0x42001C0CU) /**< \brief (SERCOM5) I2CM Baud Rate */
+#define REG_SERCOM5_I2CM_INTENCLR (*(RwReg8 *)0x42001C14U) /**< \brief (SERCOM5) I2CM Interrupt Enable Clear */
+#define REG_SERCOM5_I2CM_INTENSET (*(RwReg8 *)0x42001C16U) /**< \brief (SERCOM5) I2CM Interrupt Enable Set */
+#define REG_SERCOM5_I2CM_INTFLAG (*(RwReg8 *)0x42001C18U) /**< \brief (SERCOM5) I2CM Interrupt Flag Status and Clear */
+#define REG_SERCOM5_I2CM_STATUS (*(RwReg16*)0x42001C1AU) /**< \brief (SERCOM5) I2CM Status */
+#define REG_SERCOM5_I2CM_SYNCBUSY (*(RoReg *)0x42001C1CU) /**< \brief (SERCOM5) I2CM Syncbusy */
+#define REG_SERCOM5_I2CM_ADDR (*(RwReg *)0x42001C24U) /**< \brief (SERCOM5) I2CM Address */
+#define REG_SERCOM5_I2CM_DATA (*(RwReg8 *)0x42001C28U) /**< \brief (SERCOM5) I2CM Data */
+#define REG_SERCOM5_I2CM_DBGCTRL (*(RwReg8 *)0x42001C30U) /**< \brief (SERCOM5) I2CM Debug Control */
+#define REG_SERCOM5_I2CS_CTRLA (*(RwReg *)0x42001C00U) /**< \brief (SERCOM5) I2CS Control A */
+#define REG_SERCOM5_I2CS_CTRLB (*(RwReg *)0x42001C04U) /**< \brief (SERCOM5) I2CS Control B */
+#define REG_SERCOM5_I2CS_INTENCLR (*(RwReg8 *)0x42001C14U) /**< \brief (SERCOM5) I2CS Interrupt Enable Clear */
+#define REG_SERCOM5_I2CS_INTENSET (*(RwReg8 *)0x42001C16U) /**< \brief (SERCOM5) I2CS Interrupt Enable Set */
+#define REG_SERCOM5_I2CS_INTFLAG (*(RwReg8 *)0x42001C18U) /**< \brief (SERCOM5) I2CS Interrupt Flag Status and Clear */
+#define REG_SERCOM5_I2CS_STATUS (*(RwReg16*)0x42001C1AU) /**< \brief (SERCOM5) I2CS Status */
+#define REG_SERCOM5_I2CS_SYNCBUSY (*(RoReg *)0x42001C1CU) /**< \brief (SERCOM5) I2CS Syncbusy */
+#define REG_SERCOM5_I2CS_ADDR (*(RwReg *)0x42001C24U) /**< \brief (SERCOM5) I2CS Address */
+#define REG_SERCOM5_I2CS_DATA (*(RwReg8 *)0x42001C28U) /**< \brief (SERCOM5) I2CS Data */
+#define REG_SERCOM5_SPI_CTRLA (*(RwReg *)0x42001C00U) /**< \brief (SERCOM5) SPI Control A */
+#define REG_SERCOM5_SPI_CTRLB (*(RwReg *)0x42001C04U) /**< \brief (SERCOM5) SPI Control B */
+#define REG_SERCOM5_SPI_BAUD (*(RwReg8 *)0x42001C0CU) /**< \brief (SERCOM5) SPI Baud Rate */
+#define REG_SERCOM5_SPI_INTENCLR (*(RwReg8 *)0x42001C14U) /**< \brief (SERCOM5) SPI Interrupt Enable Clear */
+#define REG_SERCOM5_SPI_INTENSET (*(RwReg8 *)0x42001C16U) /**< \brief (SERCOM5) SPI Interrupt Enable Set */
+#define REG_SERCOM5_SPI_INTFLAG (*(RwReg8 *)0x42001C18U) /**< \brief (SERCOM5) SPI Interrupt Flag Status and Clear */
+#define REG_SERCOM5_SPI_STATUS (*(RwReg16*)0x42001C1AU) /**< \brief (SERCOM5) SPI Status */
+#define REG_SERCOM5_SPI_SYNCBUSY (*(RoReg *)0x42001C1CU) /**< \brief (SERCOM5) SPI Syncbusy */
+#define REG_SERCOM5_SPI_ADDR (*(RwReg *)0x42001C24U) /**< \brief (SERCOM5) SPI Address */
+#define REG_SERCOM5_SPI_DATA (*(RwReg *)0x42001C28U) /**< \brief (SERCOM5) SPI Data */
+#define REG_SERCOM5_SPI_DBGCTRL (*(RwReg8 *)0x42001C30U) /**< \brief (SERCOM5) SPI Debug Control */
+#define REG_SERCOM5_USART_CTRLA (*(RwReg *)0x42001C00U) /**< \brief (SERCOM5) USART Control A */
+#define REG_SERCOM5_USART_CTRLB (*(RwReg *)0x42001C04U) /**< \brief (SERCOM5) USART Control B */
+#define REG_SERCOM5_USART_BAUD (*(RwReg16*)0x42001C0CU) /**< \brief (SERCOM5) USART Baud Rate */
+#define REG_SERCOM5_USART_RXPL (*(RwReg8 *)0x42001C0EU) /**< \brief (SERCOM5) USART Receive Pulse Length */
+#define REG_SERCOM5_USART_INTENCLR (*(RwReg8 *)0x42001C14U) /**< \brief (SERCOM5) USART Interrupt Enable Clear */
+#define REG_SERCOM5_USART_INTENSET (*(RwReg8 *)0x42001C16U) /**< \brief (SERCOM5) USART Interrupt Enable Set */
+#define REG_SERCOM5_USART_INTFLAG (*(RwReg8 *)0x42001C18U) /**< \brief (SERCOM5) USART Interrupt Flag Status and Clear */
+#define REG_SERCOM5_USART_STATUS (*(RwReg16*)0x42001C1AU) /**< \brief (SERCOM5) USART Status */
+#define REG_SERCOM5_USART_SYNCBUSY (*(RoReg *)0x42001C1CU) /**< \brief (SERCOM5) USART Syncbusy */
+#define REG_SERCOM5_USART_DATA (*(RwReg16*)0x42001C28U) /**< \brief (SERCOM5) USART Data */
+#define REG_SERCOM5_USART_DBGCTRL (*(RwReg8 *)0x42001C30U) /**< \brief (SERCOM5) USART Debug Control */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for SERCOM5 peripheral ========== */
+#define SERCOM5_DMAC_ID_RX 11 // Index of DMA RX trigger
+#define SERCOM5_DMAC_ID_TX 12 // Index of DMA TX trigger
+#define SERCOM5_GCLK_ID_CORE 25 // Index of Generic Clock for Core
+#define SERCOM5_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout
+#define SERCOM5_INT_MSB 6
+
+#endif /* _SAMD21_SERCOM5_INSTANCE_ */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/sysctrl.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/sysctrl.h
new file mode 100644
index 0000000000000000000000000000000000000000..581aa5cbe318d5685b6db01facff5c73f6b96ac4
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/sysctrl.h
@@ -0,0 +1,120 @@
+/**
+ * \file
+ *
+ * \brief Instance description for SYSCTRL
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_SYSCTRL_INSTANCE_
+#define _SAMD21_SYSCTRL_INSTANCE_
+
+/* ========== Register definition for SYSCTRL peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_SYSCTRL_INTENCLR (0x40000800U) /**< \brief (SYSCTRL) Interrupt Enable Clear */
+#define REG_SYSCTRL_INTENSET (0x40000804U) /**< \brief (SYSCTRL) Interrupt Enable Set */
+#define REG_SYSCTRL_INTFLAG (0x40000808U) /**< \brief (SYSCTRL) Interrupt Flag Status and Clear */
+#define REG_SYSCTRL_PCLKSR (0x4000080CU) /**< \brief (SYSCTRL) Power and Clocks Status */
+#define REG_SYSCTRL_XOSC (0x40000810U) /**< \brief (SYSCTRL) External Multipurpose Crystal Oscillator (XOSC) Control */
+#define REG_SYSCTRL_XOSC32K (0x40000814U) /**< \brief (SYSCTRL) 32kHz External Crystal Oscillator (XOSC32K) Control */
+#define REG_SYSCTRL_OSC32K (0x40000818U) /**< \brief (SYSCTRL) 32kHz Internal Oscillator (OSC32K) Control */
+#define REG_SYSCTRL_OSCULP32K (0x4000081CU) /**< \brief (SYSCTRL) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
+#define REG_SYSCTRL_OSC8M (0x40000820U) /**< \brief (SYSCTRL) 8MHz Internal Oscillator (OSC8M) Control */
+#define REG_SYSCTRL_DFLLCTRL (0x40000824U) /**< \brief (SYSCTRL) DFLL48M Control */
+#define REG_SYSCTRL_DFLLVAL (0x40000828U) /**< \brief (SYSCTRL) DFLL48M Value */
+#define REG_SYSCTRL_DFLLMUL (0x4000082CU) /**< \brief (SYSCTRL) DFLL48M Multiplier */
+#define REG_SYSCTRL_DFLLSYNC (0x40000830U) /**< \brief (SYSCTRL) DFLL48M Synchronization */
+#define REG_SYSCTRL_BOD33 (0x40000834U) /**< \brief (SYSCTRL) 3.3V Brown-Out Detector (BOD33) Control */
+#define REG_SYSCTRL_VREG (0x4000083CU) /**< \brief (SYSCTRL) Voltage Regulator System (VREG) Control */
+#define REG_SYSCTRL_VREF (0x40000840U) /**< \brief (SYSCTRL) Voltage References System (VREF) Control */
+#define REG_SYSCTRL_DPLLCTRLA (0x40000844U) /**< \brief (SYSCTRL) DPLL Control A */
+#define REG_SYSCTRL_DPLLRATIO (0x40000848U) /**< \brief (SYSCTRL) DPLL Ratio Control */
+#define REG_SYSCTRL_DPLLCTRLB (0x4000084CU) /**< \brief (SYSCTRL) DPLL Control B */
+#define REG_SYSCTRL_DPLLSTATUS (0x40000850U) /**< \brief (SYSCTRL) DPLL Status */
+#else
+#define REG_SYSCTRL_INTENCLR (*(RwReg *)0x40000800U) /**< \brief (SYSCTRL) Interrupt Enable Clear */
+#define REG_SYSCTRL_INTENSET (*(RwReg *)0x40000804U) /**< \brief (SYSCTRL) Interrupt Enable Set */
+#define REG_SYSCTRL_INTFLAG (*(RwReg *)0x40000808U) /**< \brief (SYSCTRL) Interrupt Flag Status and Clear */
+#define REG_SYSCTRL_PCLKSR (*(RoReg *)0x4000080CU) /**< \brief (SYSCTRL) Power and Clocks Status */
+#define REG_SYSCTRL_XOSC (*(RwReg16*)0x40000810U) /**< \brief (SYSCTRL) External Multipurpose Crystal Oscillator (XOSC) Control */
+#define REG_SYSCTRL_XOSC32K (*(RwReg16*)0x40000814U) /**< \brief (SYSCTRL) 32kHz External Crystal Oscillator (XOSC32K) Control */
+#define REG_SYSCTRL_OSC32K (*(RwReg *)0x40000818U) /**< \brief (SYSCTRL) 32kHz Internal Oscillator (OSC32K) Control */
+#define REG_SYSCTRL_OSCULP32K (*(RwReg8 *)0x4000081CU) /**< \brief (SYSCTRL) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
+#define REG_SYSCTRL_OSC8M (*(RwReg *)0x40000820U) /**< \brief (SYSCTRL) 8MHz Internal Oscillator (OSC8M) Control */
+#define REG_SYSCTRL_DFLLCTRL (*(RwReg16*)0x40000824U) /**< \brief (SYSCTRL) DFLL48M Control */
+#define REG_SYSCTRL_DFLLVAL (*(RwReg *)0x40000828U) /**< \brief (SYSCTRL) DFLL48M Value */
+#define REG_SYSCTRL_DFLLMUL (*(RwReg *)0x4000082CU) /**< \brief (SYSCTRL) DFLL48M Multiplier */
+#define REG_SYSCTRL_DFLLSYNC (*(RwReg8 *)0x40000830U) /**< \brief (SYSCTRL) DFLL48M Synchronization */
+#define REG_SYSCTRL_BOD33 (*(RwReg *)0x40000834U) /**< \brief (SYSCTRL) 3.3V Brown-Out Detector (BOD33) Control */
+#define REG_SYSCTRL_VREG (*(RwReg16*)0x4000083CU) /**< \brief (SYSCTRL) Voltage Regulator System (VREG) Control */
+#define REG_SYSCTRL_VREF (*(RwReg *)0x40000840U) /**< \brief (SYSCTRL) Voltage References System (VREF) Control */
+#define REG_SYSCTRL_DPLLCTRLA (*(RwReg8 *)0x40000844U) /**< \brief (SYSCTRL) DPLL Control A */
+#define REG_SYSCTRL_DPLLRATIO (*(RwReg *)0x40000848U) /**< \brief (SYSCTRL) DPLL Ratio Control */
+#define REG_SYSCTRL_DPLLCTRLB (*(RwReg *)0x4000084CU) /**< \brief (SYSCTRL) DPLL Control B */
+#define REG_SYSCTRL_DPLLSTATUS (*(RoReg8 *)0x40000850U) /**< \brief (SYSCTRL) DPLL Status */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for SYSCTRL peripheral ========== */
+#define SYSCTRL_BGAP_CALIB_MSB 11
+#define SYSCTRL_BOD33_CALIB_MSB 5
+#define SYSCTRL_DFLL48M_COARSE_MSB 5
+#define SYSCTRL_DFLL48M_FINE_MSB 9
+#define SYSCTRL_GCLK_ID_DFLL48 0 // Index of Generic Clock for DFLL48
+#define SYSCTRL_GCLK_ID_FDPLL 1 // Index of Generic Clock for DPLL
+#define SYSCTRL_GCLK_ID_FDPLL32K 2 // Index of Generic Clock for DPLL 32K
+#define SYSCTRL_OSC32K_COARSE_CALIB_MSB 6
+#define SYSCTRL_POR33_ENTEST_MSB 1
+#define SYSCTRL_ULPVREF_DIVLEV_MSB 3
+#define SYSCTRL_ULPVREG_FORCEGAIN_MSB 1
+#define SYSCTRL_ULPVREG_RAMREFSEL_MSB 2
+#define SYSCTRL_VREF_CONTROL_MSB 48
+#define SYSCTRL_VREF_STATUS_MSB 7
+#define SYSCTRL_VREG_LEVEL_MSB 2
+#define SYSCTRL_BOD12_VERSION 0x111
+#define SYSCTRL_BOD33_VERSION 0x111
+#define SYSCTRL_DFLL48M_VERSION 0x301
+#define SYSCTRL_FDPLL_VERSION 0x111
+#define SYSCTRL_OSCULP32K_VERSION 0x111
+#define SYSCTRL_OSC8M_VERSION 0x120
+#define SYSCTRL_OSC32K_VERSION 0x1101
+#define SYSCTRL_VREF_VERSION 0x200
+#define SYSCTRL_VREG_VERSION 0x201
+#define SYSCTRL_XOSC_VERSION 0x1111
+#define SYSCTRL_XOSC32K_VERSION 0x1111
+
+#endif /* _SAMD21_SYSCTRL_INSTANCE_ */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/tc3.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/tc3.h
new file mode 100644
index 0000000000000000000000000000000000000000..73a3c86f97dddc8f65c5d1b8fc47030a901c9e5e
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/tc3.h
@@ -0,0 +1,111 @@
+/**
+ * \file
+ *
+ * \brief Instance description for TC3
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_TC3_INSTANCE_
+#define _SAMD21_TC3_INSTANCE_
+
+/* ========== Register definition for TC3 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TC3_CTRLA (0x42002C00U) /**< \brief (TC3) Control A */
+#define REG_TC3_READREQ (0x42002C02U) /**< \brief (TC3) Read Request */
+#define REG_TC3_CTRLBCLR (0x42002C04U) /**< \brief (TC3) Control B Clear */
+#define REG_TC3_CTRLBSET (0x42002C05U) /**< \brief (TC3) Control B Set */
+#define REG_TC3_CTRLC (0x42002C06U) /**< \brief (TC3) Control C */
+#define REG_TC3_DBGCTRL (0x42002C08U) /**< \brief (TC3) Debug Control */
+#define REG_TC3_EVCTRL (0x42002C0AU) /**< \brief (TC3) Event Control */
+#define REG_TC3_INTENCLR (0x42002C0CU) /**< \brief (TC3) Interrupt Enable Clear */
+#define REG_TC3_INTENSET (0x42002C0DU) /**< \brief (TC3) Interrupt Enable Set */
+#define REG_TC3_INTFLAG (0x42002C0EU) /**< \brief (TC3) Interrupt Flag Status and Clear */
+#define REG_TC3_STATUS (0x42002C0FU) /**< \brief (TC3) Status */
+#define REG_TC3_COUNT16_COUNT (0x42002C10U) /**< \brief (TC3) COUNT16 Counter Value */
+#define REG_TC3_COUNT16_CC0 (0x42002C18U) /**< \brief (TC3) COUNT16 Compare/Capture 0 */
+#define REG_TC3_COUNT16_CC1 (0x42002C1AU) /**< \brief (TC3) COUNT16 Compare/Capture 1 */
+#define REG_TC3_COUNT32_COUNT (0x42002C10U) /**< \brief (TC3) COUNT32 Counter Value */
+#define REG_TC3_COUNT32_CC0 (0x42002C18U) /**< \brief (TC3) COUNT32 Compare/Capture 0 */
+#define REG_TC3_COUNT32_CC1 (0x42002C1CU) /**< \brief (TC3) COUNT32 Compare/Capture 1 */
+#define REG_TC3_COUNT8_COUNT (0x42002C10U) /**< \brief (TC3) COUNT8 Counter Value */
+#define REG_TC3_COUNT8_PER (0x42002C14U) /**< \brief (TC3) COUNT8 Period Value */
+#define REG_TC3_COUNT8_CC0 (0x42002C18U) /**< \brief (TC3) COUNT8 Compare/Capture 0 */
+#define REG_TC3_COUNT8_CC1 (0x42002C19U) /**< \brief (TC3) COUNT8 Compare/Capture 1 */
+#else
+#define REG_TC3_CTRLA (*(RwReg16*)0x42002C00U) /**< \brief (TC3) Control A */
+#define REG_TC3_READREQ (*(RwReg16*)0x42002C02U) /**< \brief (TC3) Read Request */
+#define REG_TC3_CTRLBCLR (*(RwReg8 *)0x42002C04U) /**< \brief (TC3) Control B Clear */
+#define REG_TC3_CTRLBSET (*(RwReg8 *)0x42002C05U) /**< \brief (TC3) Control B Set */
+#define REG_TC3_CTRLC (*(RwReg8 *)0x42002C06U) /**< \brief (TC3) Control C */
+#define REG_TC3_DBGCTRL (*(RwReg8 *)0x42002C08U) /**< \brief (TC3) Debug Control */
+#define REG_TC3_EVCTRL (*(RwReg16*)0x42002C0AU) /**< \brief (TC3) Event Control */
+#define REG_TC3_INTENCLR (*(RwReg8 *)0x42002C0CU) /**< \brief (TC3) Interrupt Enable Clear */
+#define REG_TC3_INTENSET (*(RwReg8 *)0x42002C0DU) /**< \brief (TC3) Interrupt Enable Set */
+#define REG_TC3_INTFLAG (*(RwReg8 *)0x42002C0EU) /**< \brief (TC3) Interrupt Flag Status and Clear */
+#define REG_TC3_STATUS (*(RoReg8 *)0x42002C0FU) /**< \brief (TC3) Status */
+#define REG_TC3_COUNT16_COUNT (*(RwReg16*)0x42002C10U) /**< \brief (TC3) COUNT16 Counter Value */
+#define REG_TC3_COUNT16_CC0 (*(RwReg16*)0x42002C18U) /**< \brief (TC3) COUNT16 Compare/Capture 0 */
+#define REG_TC3_COUNT16_CC1 (*(RwReg16*)0x42002C1AU) /**< \brief (TC3) COUNT16 Compare/Capture 1 */
+#define REG_TC3_COUNT32_COUNT (*(RwReg *)0x42002C10U) /**< \brief (TC3) COUNT32 Counter Value */
+#define REG_TC3_COUNT32_CC0 (*(RwReg *)0x42002C18U) /**< \brief (TC3) COUNT32 Compare/Capture 0 */
+#define REG_TC3_COUNT32_CC1 (*(RwReg *)0x42002C1CU) /**< \brief (TC3) COUNT32 Compare/Capture 1 */
+#define REG_TC3_COUNT8_COUNT (*(RwReg8 *)0x42002C10U) /**< \brief (TC3) COUNT8 Counter Value */
+#define REG_TC3_COUNT8_PER (*(RwReg8 *)0x42002C14U) /**< \brief (TC3) COUNT8 Period Value */
+#define REG_TC3_COUNT8_CC0 (*(RwReg8 *)0x42002C18U) /**< \brief (TC3) COUNT8 Compare/Capture 0 */
+#define REG_TC3_COUNT8_CC1 (*(RwReg8 *)0x42002C19U) /**< \brief (TC3) COUNT8 Compare/Capture 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TC3 peripheral ========== */
+#define TC3_CC8_NUM 2 // Number of 8-bit Counters
+#define TC3_CC16_NUM 2 // Number of 16-bit Counters
+#define TC3_CC32_NUM 2 // Number of 32-bit Counters
+#define TC3_DITHERING_EXT 0 // Dithering feature implemented
+#define TC3_DMAC_ID_MC_0 25
+#define TC3_DMAC_ID_MC_1 26
+#define TC3_DMAC_ID_MC_LSB 25
+#define TC3_DMAC_ID_MC_MSB 26
+#define TC3_DMAC_ID_MC_SIZE 2
+#define TC3_DMAC_ID_OVF 24 // Indexes of DMA Overflow trigger
+#define TC3_GCLK_ID 27 // Index of Generic Clock
+#define TC3_MASTER 0
+#define TC3_OW_NUM 2 // Number of Output Waveforms
+#define TC3_PERIOD_EXT 0 // Period feature implemented
+#define TC3_SHADOW_EXT 0 // Shadow feature implemented
+
+#endif /* _SAMD21_TC3_INSTANCE_ */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/tc4.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/tc4.h
new file mode 100644
index 0000000000000000000000000000000000000000..f2a8fa3e57ffe411e3a35aa9395101a0c40b0785
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/tc4.h
@@ -0,0 +1,111 @@
+/**
+ * \file
+ *
+ * \brief Instance description for TC4
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_TC4_INSTANCE_
+#define _SAMD21_TC4_INSTANCE_
+
+/* ========== Register definition for TC4 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TC4_CTRLA (0x42003000U) /**< \brief (TC4) Control A */
+#define REG_TC4_READREQ (0x42003002U) /**< \brief (TC4) Read Request */
+#define REG_TC4_CTRLBCLR (0x42003004U) /**< \brief (TC4) Control B Clear */
+#define REG_TC4_CTRLBSET (0x42003005U) /**< \brief (TC4) Control B Set */
+#define REG_TC4_CTRLC (0x42003006U) /**< \brief (TC4) Control C */
+#define REG_TC4_DBGCTRL (0x42003008U) /**< \brief (TC4) Debug Control */
+#define REG_TC4_EVCTRL (0x4200300AU) /**< \brief (TC4) Event Control */
+#define REG_TC4_INTENCLR (0x4200300CU) /**< \brief (TC4) Interrupt Enable Clear */
+#define REG_TC4_INTENSET (0x4200300DU) /**< \brief (TC4) Interrupt Enable Set */
+#define REG_TC4_INTFLAG (0x4200300EU) /**< \brief (TC4) Interrupt Flag Status and Clear */
+#define REG_TC4_STATUS (0x4200300FU) /**< \brief (TC4) Status */
+#define REG_TC4_COUNT16_COUNT (0x42003010U) /**< \brief (TC4) COUNT16 Counter Value */
+#define REG_TC4_COUNT16_CC0 (0x42003018U) /**< \brief (TC4) COUNT16 Compare/Capture 0 */
+#define REG_TC4_COUNT16_CC1 (0x4200301AU) /**< \brief (TC4) COUNT16 Compare/Capture 1 */
+#define REG_TC4_COUNT32_COUNT (0x42003010U) /**< \brief (TC4) COUNT32 Counter Value */
+#define REG_TC4_COUNT32_CC0 (0x42003018U) /**< \brief (TC4) COUNT32 Compare/Capture 0 */
+#define REG_TC4_COUNT32_CC1 (0x4200301CU) /**< \brief (TC4) COUNT32 Compare/Capture 1 */
+#define REG_TC4_COUNT8_COUNT (0x42003010U) /**< \brief (TC4) COUNT8 Counter Value */
+#define REG_TC4_COUNT8_PER (0x42003014U) /**< \brief (TC4) COUNT8 Period Value */
+#define REG_TC4_COUNT8_CC0 (0x42003018U) /**< \brief (TC4) COUNT8 Compare/Capture 0 */
+#define REG_TC4_COUNT8_CC1 (0x42003019U) /**< \brief (TC4) COUNT8 Compare/Capture 1 */
+#else
+#define REG_TC4_CTRLA (*(RwReg16*)0x42003000U) /**< \brief (TC4) Control A */
+#define REG_TC4_READREQ (*(RwReg16*)0x42003002U) /**< \brief (TC4) Read Request */
+#define REG_TC4_CTRLBCLR (*(RwReg8 *)0x42003004U) /**< \brief (TC4) Control B Clear */
+#define REG_TC4_CTRLBSET (*(RwReg8 *)0x42003005U) /**< \brief (TC4) Control B Set */
+#define REG_TC4_CTRLC (*(RwReg8 *)0x42003006U) /**< \brief (TC4) Control C */
+#define REG_TC4_DBGCTRL (*(RwReg8 *)0x42003008U) /**< \brief (TC4) Debug Control */
+#define REG_TC4_EVCTRL (*(RwReg16*)0x4200300AU) /**< \brief (TC4) Event Control */
+#define REG_TC4_INTENCLR (*(RwReg8 *)0x4200300CU) /**< \brief (TC4) Interrupt Enable Clear */
+#define REG_TC4_INTENSET (*(RwReg8 *)0x4200300DU) /**< \brief (TC4) Interrupt Enable Set */
+#define REG_TC4_INTFLAG (*(RwReg8 *)0x4200300EU) /**< \brief (TC4) Interrupt Flag Status and Clear */
+#define REG_TC4_STATUS (*(RoReg8 *)0x4200300FU) /**< \brief (TC4) Status */
+#define REG_TC4_COUNT16_COUNT (*(RwReg16*)0x42003010U) /**< \brief (TC4) COUNT16 Counter Value */
+#define REG_TC4_COUNT16_CC0 (*(RwReg16*)0x42003018U) /**< \brief (TC4) COUNT16 Compare/Capture 0 */
+#define REG_TC4_COUNT16_CC1 (*(RwReg16*)0x4200301AU) /**< \brief (TC4) COUNT16 Compare/Capture 1 */
+#define REG_TC4_COUNT32_COUNT (*(RwReg *)0x42003010U) /**< \brief (TC4) COUNT32 Counter Value */
+#define REG_TC4_COUNT32_CC0 (*(RwReg *)0x42003018U) /**< \brief (TC4) COUNT32 Compare/Capture 0 */
+#define REG_TC4_COUNT32_CC1 (*(RwReg *)0x4200301CU) /**< \brief (TC4) COUNT32 Compare/Capture 1 */
+#define REG_TC4_COUNT8_COUNT (*(RwReg8 *)0x42003010U) /**< \brief (TC4) COUNT8 Counter Value */
+#define REG_TC4_COUNT8_PER (*(RwReg8 *)0x42003014U) /**< \brief (TC4) COUNT8 Period Value */
+#define REG_TC4_COUNT8_CC0 (*(RwReg8 *)0x42003018U) /**< \brief (TC4) COUNT8 Compare/Capture 0 */
+#define REG_TC4_COUNT8_CC1 (*(RwReg8 *)0x42003019U) /**< \brief (TC4) COUNT8 Compare/Capture 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TC4 peripheral ========== */
+#define TC4_CC8_NUM 2 // Number of 8-bit Counters
+#define TC4_CC16_NUM 2 // Number of 16-bit Counters
+#define TC4_CC32_NUM 2 // Number of 32-bit Counters
+#define TC4_DITHERING_EXT 0 // Dithering feature implemented
+#define TC4_DMAC_ID_MC_0 28
+#define TC4_DMAC_ID_MC_1 29
+#define TC4_DMAC_ID_MC_LSB 28
+#define TC4_DMAC_ID_MC_MSB 29
+#define TC4_DMAC_ID_MC_SIZE 2
+#define TC4_DMAC_ID_OVF 27 // Indexes of DMA Overflow trigger
+#define TC4_GCLK_ID 28 // Index of Generic Clock
+#define TC4_MASTER 1
+#define TC4_OW_NUM 2 // Number of Output Waveforms
+#define TC4_PERIOD_EXT 0 // Period feature implemented
+#define TC4_SHADOW_EXT 0 // Shadow feature implemented
+
+#endif /* _SAMD21_TC4_INSTANCE_ */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/tc5.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/tc5.h
new file mode 100644
index 0000000000000000000000000000000000000000..7b81c51331a75d3ceb03988a1dcf087f4c55fc9f
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/tc5.h
@@ -0,0 +1,111 @@
+/**
+ * \file
+ *
+ * \brief Instance description for TC5
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_TC5_INSTANCE_
+#define _SAMD21_TC5_INSTANCE_
+
+/* ========== Register definition for TC5 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TC5_CTRLA (0x42003400U) /**< \brief (TC5) Control A */
+#define REG_TC5_READREQ (0x42003402U) /**< \brief (TC5) Read Request */
+#define REG_TC5_CTRLBCLR (0x42003404U) /**< \brief (TC5) Control B Clear */
+#define REG_TC5_CTRLBSET (0x42003405U) /**< \brief (TC5) Control B Set */
+#define REG_TC5_CTRLC (0x42003406U) /**< \brief (TC5) Control C */
+#define REG_TC5_DBGCTRL (0x42003408U) /**< \brief (TC5) Debug Control */
+#define REG_TC5_EVCTRL (0x4200340AU) /**< \brief (TC5) Event Control */
+#define REG_TC5_INTENCLR (0x4200340CU) /**< \brief (TC5) Interrupt Enable Clear */
+#define REG_TC5_INTENSET (0x4200340DU) /**< \brief (TC5) Interrupt Enable Set */
+#define REG_TC5_INTFLAG (0x4200340EU) /**< \brief (TC5) Interrupt Flag Status and Clear */
+#define REG_TC5_STATUS (0x4200340FU) /**< \brief (TC5) Status */
+#define REG_TC5_COUNT16_COUNT (0x42003410U) /**< \brief (TC5) COUNT16 Counter Value */
+#define REG_TC5_COUNT16_CC0 (0x42003418U) /**< \brief (TC5) COUNT16 Compare/Capture 0 */
+#define REG_TC5_COUNT16_CC1 (0x4200341AU) /**< \brief (TC5) COUNT16 Compare/Capture 1 */
+#define REG_TC5_COUNT32_COUNT (0x42003410U) /**< \brief (TC5) COUNT32 Counter Value */
+#define REG_TC5_COUNT32_CC0 (0x42003418U) /**< \brief (TC5) COUNT32 Compare/Capture 0 */
+#define REG_TC5_COUNT32_CC1 (0x4200341CU) /**< \brief (TC5) COUNT32 Compare/Capture 1 */
+#define REG_TC5_COUNT8_COUNT (0x42003410U) /**< \brief (TC5) COUNT8 Counter Value */
+#define REG_TC5_COUNT8_PER (0x42003414U) /**< \brief (TC5) COUNT8 Period Value */
+#define REG_TC5_COUNT8_CC0 (0x42003418U) /**< \brief (TC5) COUNT8 Compare/Capture 0 */
+#define REG_TC5_COUNT8_CC1 (0x42003419U) /**< \brief (TC5) COUNT8 Compare/Capture 1 */
+#else
+#define REG_TC5_CTRLA (*(RwReg16*)0x42003400U) /**< \brief (TC5) Control A */
+#define REG_TC5_READREQ (*(RwReg16*)0x42003402U) /**< \brief (TC5) Read Request */
+#define REG_TC5_CTRLBCLR (*(RwReg8 *)0x42003404U) /**< \brief (TC5) Control B Clear */
+#define REG_TC5_CTRLBSET (*(RwReg8 *)0x42003405U) /**< \brief (TC5) Control B Set */
+#define REG_TC5_CTRLC (*(RwReg8 *)0x42003406U) /**< \brief (TC5) Control C */
+#define REG_TC5_DBGCTRL (*(RwReg8 *)0x42003408U) /**< \brief (TC5) Debug Control */
+#define REG_TC5_EVCTRL (*(RwReg16*)0x4200340AU) /**< \brief (TC5) Event Control */
+#define REG_TC5_INTENCLR (*(RwReg8 *)0x4200340CU) /**< \brief (TC5) Interrupt Enable Clear */
+#define REG_TC5_INTENSET (*(RwReg8 *)0x4200340DU) /**< \brief (TC5) Interrupt Enable Set */
+#define REG_TC5_INTFLAG (*(RwReg8 *)0x4200340EU) /**< \brief (TC5) Interrupt Flag Status and Clear */
+#define REG_TC5_STATUS (*(RoReg8 *)0x4200340FU) /**< \brief (TC5) Status */
+#define REG_TC5_COUNT16_COUNT (*(RwReg16*)0x42003410U) /**< \brief (TC5) COUNT16 Counter Value */
+#define REG_TC5_COUNT16_CC0 (*(RwReg16*)0x42003418U) /**< \brief (TC5) COUNT16 Compare/Capture 0 */
+#define REG_TC5_COUNT16_CC1 (*(RwReg16*)0x4200341AU) /**< \brief (TC5) COUNT16 Compare/Capture 1 */
+#define REG_TC5_COUNT32_COUNT (*(RwReg *)0x42003410U) /**< \brief (TC5) COUNT32 Counter Value */
+#define REG_TC5_COUNT32_CC0 (*(RwReg *)0x42003418U) /**< \brief (TC5) COUNT32 Compare/Capture 0 */
+#define REG_TC5_COUNT32_CC1 (*(RwReg *)0x4200341CU) /**< \brief (TC5) COUNT32 Compare/Capture 1 */
+#define REG_TC5_COUNT8_COUNT (*(RwReg8 *)0x42003410U) /**< \brief (TC5) COUNT8 Counter Value */
+#define REG_TC5_COUNT8_PER (*(RwReg8 *)0x42003414U) /**< \brief (TC5) COUNT8 Period Value */
+#define REG_TC5_COUNT8_CC0 (*(RwReg8 *)0x42003418U) /**< \brief (TC5) COUNT8 Compare/Capture 0 */
+#define REG_TC5_COUNT8_CC1 (*(RwReg8 *)0x42003419U) /**< \brief (TC5) COUNT8 Compare/Capture 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TC5 peripheral ========== */
+#define TC5_CC8_NUM 2 // Number of 8-bit Counters
+#define TC5_CC16_NUM 2 // Number of 16-bit Counters
+#define TC5_CC32_NUM 2 // Number of 32-bit Counters
+#define TC5_DITHERING_EXT 0 // Dithering feature implemented
+#define TC5_DMAC_ID_MC_0 31
+#define TC5_DMAC_ID_MC_1 32
+#define TC5_DMAC_ID_MC_LSB 31
+#define TC5_DMAC_ID_MC_MSB 32
+#define TC5_DMAC_ID_MC_SIZE 2
+#define TC5_DMAC_ID_OVF 30 // Indexes of DMA Overflow trigger
+#define TC5_GCLK_ID 28 // Index of Generic Clock
+#define TC5_MASTER 0
+#define TC5_OW_NUM 2 // Number of Output Waveforms
+#define TC5_PERIOD_EXT 0 // Period feature implemented
+#define TC5_SHADOW_EXT 0 // Shadow feature implemented
+
+#endif /* _SAMD21_TC5_INSTANCE_ */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/tc6.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/tc6.h
new file mode 100644
index 0000000000000000000000000000000000000000..1ab5812833bc54d0ddcf735a6caa49f639eeb063
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/tc6.h
@@ -0,0 +1,111 @@
+/**
+ * \file
+ *
+ * \brief Instance description for TC6
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_TC6_INSTANCE_
+#define _SAMD21_TC6_INSTANCE_
+
+/* ========== Register definition for TC6 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TC6_CTRLA (0x42003800U) /**< \brief (TC6) Control A */
+#define REG_TC6_READREQ (0x42003802U) /**< \brief (TC6) Read Request */
+#define REG_TC6_CTRLBCLR (0x42003804U) /**< \brief (TC6) Control B Clear */
+#define REG_TC6_CTRLBSET (0x42003805U) /**< \brief (TC6) Control B Set */
+#define REG_TC6_CTRLC (0x42003806U) /**< \brief (TC6) Control C */
+#define REG_TC6_DBGCTRL (0x42003808U) /**< \brief (TC6) Debug Control */
+#define REG_TC6_EVCTRL (0x4200380AU) /**< \brief (TC6) Event Control */
+#define REG_TC6_INTENCLR (0x4200380CU) /**< \brief (TC6) Interrupt Enable Clear */
+#define REG_TC6_INTENSET (0x4200380DU) /**< \brief (TC6) Interrupt Enable Set */
+#define REG_TC6_INTFLAG (0x4200380EU) /**< \brief (TC6) Interrupt Flag Status and Clear */
+#define REG_TC6_STATUS (0x4200380FU) /**< \brief (TC6) Status */
+#define REG_TC6_COUNT16_COUNT (0x42003810U) /**< \brief (TC6) COUNT16 Counter Value */
+#define REG_TC6_COUNT16_CC0 (0x42003818U) /**< \brief (TC6) COUNT16 Compare/Capture 0 */
+#define REG_TC6_COUNT16_CC1 (0x4200381AU) /**< \brief (TC6) COUNT16 Compare/Capture 1 */
+#define REG_TC6_COUNT32_COUNT (0x42003810U) /**< \brief (TC6) COUNT32 Counter Value */
+#define REG_TC6_COUNT32_CC0 (0x42003818U) /**< \brief (TC6) COUNT32 Compare/Capture 0 */
+#define REG_TC6_COUNT32_CC1 (0x4200381CU) /**< \brief (TC6) COUNT32 Compare/Capture 1 */
+#define REG_TC6_COUNT8_COUNT (0x42003810U) /**< \brief (TC6) COUNT8 Counter Value */
+#define REG_TC6_COUNT8_PER (0x42003814U) /**< \brief (TC6) COUNT8 Period Value */
+#define REG_TC6_COUNT8_CC0 (0x42003818U) /**< \brief (TC6) COUNT8 Compare/Capture 0 */
+#define REG_TC6_COUNT8_CC1 (0x42003819U) /**< \brief (TC6) COUNT8 Compare/Capture 1 */
+#else
+#define REG_TC6_CTRLA (*(RwReg16*)0x42003800U) /**< \brief (TC6) Control A */
+#define REG_TC6_READREQ (*(RwReg16*)0x42003802U) /**< \brief (TC6) Read Request */
+#define REG_TC6_CTRLBCLR (*(RwReg8 *)0x42003804U) /**< \brief (TC6) Control B Clear */
+#define REG_TC6_CTRLBSET (*(RwReg8 *)0x42003805U) /**< \brief (TC6) Control B Set */
+#define REG_TC6_CTRLC (*(RwReg8 *)0x42003806U) /**< \brief (TC6) Control C */
+#define REG_TC6_DBGCTRL (*(RwReg8 *)0x42003808U) /**< \brief (TC6) Debug Control */
+#define REG_TC6_EVCTRL (*(RwReg16*)0x4200380AU) /**< \brief (TC6) Event Control */
+#define REG_TC6_INTENCLR (*(RwReg8 *)0x4200380CU) /**< \brief (TC6) Interrupt Enable Clear */
+#define REG_TC6_INTENSET (*(RwReg8 *)0x4200380DU) /**< \brief (TC6) Interrupt Enable Set */
+#define REG_TC6_INTFLAG (*(RwReg8 *)0x4200380EU) /**< \brief (TC6) Interrupt Flag Status and Clear */
+#define REG_TC6_STATUS (*(RoReg8 *)0x4200380FU) /**< \brief (TC6) Status */
+#define REG_TC6_COUNT16_COUNT (*(RwReg16*)0x42003810U) /**< \brief (TC6) COUNT16 Counter Value */
+#define REG_TC6_COUNT16_CC0 (*(RwReg16*)0x42003818U) /**< \brief (TC6) COUNT16 Compare/Capture 0 */
+#define REG_TC6_COUNT16_CC1 (*(RwReg16*)0x4200381AU) /**< \brief (TC6) COUNT16 Compare/Capture 1 */
+#define REG_TC6_COUNT32_COUNT (*(RwReg *)0x42003810U) /**< \brief (TC6) COUNT32 Counter Value */
+#define REG_TC6_COUNT32_CC0 (*(RwReg *)0x42003818U) /**< \brief (TC6) COUNT32 Compare/Capture 0 */
+#define REG_TC6_COUNT32_CC1 (*(RwReg *)0x4200381CU) /**< \brief (TC6) COUNT32 Compare/Capture 1 */
+#define REG_TC6_COUNT8_COUNT (*(RwReg8 *)0x42003810U) /**< \brief (TC6) COUNT8 Counter Value */
+#define REG_TC6_COUNT8_PER (*(RwReg8 *)0x42003814U) /**< \brief (TC6) COUNT8 Period Value */
+#define REG_TC6_COUNT8_CC0 (*(RwReg8 *)0x42003818U) /**< \brief (TC6) COUNT8 Compare/Capture 0 */
+#define REG_TC6_COUNT8_CC1 (*(RwReg8 *)0x42003819U) /**< \brief (TC6) COUNT8 Compare/Capture 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TC6 peripheral ========== */
+#define TC6_CC8_NUM 2 // Number of 8-bit Counters
+#define TC6_CC16_NUM 2 // Number of 16-bit Counters
+#define TC6_CC32_NUM 2 // Number of 32-bit Counters
+#define TC6_DITHERING_EXT 0 // Dithering feature implemented
+#define TC6_DMAC_ID_MC_0 34
+#define TC6_DMAC_ID_MC_1 35
+#define TC6_DMAC_ID_MC_LSB 34
+#define TC6_DMAC_ID_MC_MSB 35
+#define TC6_DMAC_ID_MC_SIZE 2
+#define TC6_DMAC_ID_OVF 33 // Indexes of DMA Overflow trigger
+#define TC6_GCLK_ID 29 // Index of Generic Clock
+#define TC6_MASTER 1
+#define TC6_OW_NUM 2 // Number of Output Waveforms
+#define TC6_PERIOD_EXT 0 // Period feature implemented
+#define TC6_SHADOW_EXT 0 // Shadow feature implemented
+
+#endif /* _SAMD21_TC6_INSTANCE_ */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/tc7.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/tc7.h
new file mode 100644
index 0000000000000000000000000000000000000000..50928ae030b597bf10d79668bf91a63e9b6bd7bf
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/tc7.h
@@ -0,0 +1,111 @@
+/**
+ * \file
+ *
+ * \brief Instance description for TC7
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_TC7_INSTANCE_
+#define _SAMD21_TC7_INSTANCE_
+
+/* ========== Register definition for TC7 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TC7_CTRLA (0x42003C00U) /**< \brief (TC7) Control A */
+#define REG_TC7_READREQ (0x42003C02U) /**< \brief (TC7) Read Request */
+#define REG_TC7_CTRLBCLR (0x42003C04U) /**< \brief (TC7) Control B Clear */
+#define REG_TC7_CTRLBSET (0x42003C05U) /**< \brief (TC7) Control B Set */
+#define REG_TC7_CTRLC (0x42003C06U) /**< \brief (TC7) Control C */
+#define REG_TC7_DBGCTRL (0x42003C08U) /**< \brief (TC7) Debug Control */
+#define REG_TC7_EVCTRL (0x42003C0AU) /**< \brief (TC7) Event Control */
+#define REG_TC7_INTENCLR (0x42003C0CU) /**< \brief (TC7) Interrupt Enable Clear */
+#define REG_TC7_INTENSET (0x42003C0DU) /**< \brief (TC7) Interrupt Enable Set */
+#define REG_TC7_INTFLAG (0x42003C0EU) /**< \brief (TC7) Interrupt Flag Status and Clear */
+#define REG_TC7_STATUS (0x42003C0FU) /**< \brief (TC7) Status */
+#define REG_TC7_COUNT16_COUNT (0x42003C10U) /**< \brief (TC7) COUNT16 Counter Value */
+#define REG_TC7_COUNT16_CC0 (0x42003C18U) /**< \brief (TC7) COUNT16 Compare/Capture 0 */
+#define REG_TC7_COUNT16_CC1 (0x42003C1AU) /**< \brief (TC7) COUNT16 Compare/Capture 1 */
+#define REG_TC7_COUNT32_COUNT (0x42003C10U) /**< \brief (TC7) COUNT32 Counter Value */
+#define REG_TC7_COUNT32_CC0 (0x42003C18U) /**< \brief (TC7) COUNT32 Compare/Capture 0 */
+#define REG_TC7_COUNT32_CC1 (0x42003C1CU) /**< \brief (TC7) COUNT32 Compare/Capture 1 */
+#define REG_TC7_COUNT8_COUNT (0x42003C10U) /**< \brief (TC7) COUNT8 Counter Value */
+#define REG_TC7_COUNT8_PER (0x42003C14U) /**< \brief (TC7) COUNT8 Period Value */
+#define REG_TC7_COUNT8_CC0 (0x42003C18U) /**< \brief (TC7) COUNT8 Compare/Capture 0 */
+#define REG_TC7_COUNT8_CC1 (0x42003C19U) /**< \brief (TC7) COUNT8 Compare/Capture 1 */
+#else
+#define REG_TC7_CTRLA (*(RwReg16*)0x42003C00U) /**< \brief (TC7) Control A */
+#define REG_TC7_READREQ (*(RwReg16*)0x42003C02U) /**< \brief (TC7) Read Request */
+#define REG_TC7_CTRLBCLR (*(RwReg8 *)0x42003C04U) /**< \brief (TC7) Control B Clear */
+#define REG_TC7_CTRLBSET (*(RwReg8 *)0x42003C05U) /**< \brief (TC7) Control B Set */
+#define REG_TC7_CTRLC (*(RwReg8 *)0x42003C06U) /**< \brief (TC7) Control C */
+#define REG_TC7_DBGCTRL (*(RwReg8 *)0x42003C08U) /**< \brief (TC7) Debug Control */
+#define REG_TC7_EVCTRL (*(RwReg16*)0x42003C0AU) /**< \brief (TC7) Event Control */
+#define REG_TC7_INTENCLR (*(RwReg8 *)0x42003C0CU) /**< \brief (TC7) Interrupt Enable Clear */
+#define REG_TC7_INTENSET (*(RwReg8 *)0x42003C0DU) /**< \brief (TC7) Interrupt Enable Set */
+#define REG_TC7_INTFLAG (*(RwReg8 *)0x42003C0EU) /**< \brief (TC7) Interrupt Flag Status and Clear */
+#define REG_TC7_STATUS (*(RoReg8 *)0x42003C0FU) /**< \brief (TC7) Status */
+#define REG_TC7_COUNT16_COUNT (*(RwReg16*)0x42003C10U) /**< \brief (TC7) COUNT16 Counter Value */
+#define REG_TC7_COUNT16_CC0 (*(RwReg16*)0x42003C18U) /**< \brief (TC7) COUNT16 Compare/Capture 0 */
+#define REG_TC7_COUNT16_CC1 (*(RwReg16*)0x42003C1AU) /**< \brief (TC7) COUNT16 Compare/Capture 1 */
+#define REG_TC7_COUNT32_COUNT (*(RwReg *)0x42003C10U) /**< \brief (TC7) COUNT32 Counter Value */
+#define REG_TC7_COUNT32_CC0 (*(RwReg *)0x42003C18U) /**< \brief (TC7) COUNT32 Compare/Capture 0 */
+#define REG_TC7_COUNT32_CC1 (*(RwReg *)0x42003C1CU) /**< \brief (TC7) COUNT32 Compare/Capture 1 */
+#define REG_TC7_COUNT8_COUNT (*(RwReg8 *)0x42003C10U) /**< \brief (TC7) COUNT8 Counter Value */
+#define REG_TC7_COUNT8_PER (*(RwReg8 *)0x42003C14U) /**< \brief (TC7) COUNT8 Period Value */
+#define REG_TC7_COUNT8_CC0 (*(RwReg8 *)0x42003C18U) /**< \brief (TC7) COUNT8 Compare/Capture 0 */
+#define REG_TC7_COUNT8_CC1 (*(RwReg8 *)0x42003C19U) /**< \brief (TC7) COUNT8 Compare/Capture 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TC7 peripheral ========== */
+#define TC7_CC8_NUM 2 // Number of 8-bit Counters
+#define TC7_CC16_NUM 2 // Number of 16-bit Counters
+#define TC7_CC32_NUM 2 // Number of 32-bit Counters
+#define TC7_DITHERING_EXT 0 // Dithering feature implemented
+#define TC7_DMAC_ID_MC_0 37
+#define TC7_DMAC_ID_MC_1 38
+#define TC7_DMAC_ID_MC_LSB 37
+#define TC7_DMAC_ID_MC_MSB 38
+#define TC7_DMAC_ID_MC_SIZE 2
+#define TC7_DMAC_ID_OVF 36 // Indexes of DMA Overflow trigger
+#define TC7_GCLK_ID 29 // Index of Generic Clock
+#define TC7_MASTER 0
+#define TC7_OW_NUM 2 // Number of Output Waveforms
+#define TC7_PERIOD_EXT 0 // Period feature implemented
+#define TC7_SHADOW_EXT 0 // Shadow feature implemented
+
+#endif /* _SAMD21_TC7_INSTANCE_ */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/tcc0.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/tcc0.h
new file mode 100644
index 0000000000000000000000000000000000000000..4f507cbfbcd29df6cd8b8299ee8c70ba918567ad
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/tcc0.h
@@ -0,0 +1,131 @@
+/**
+ * \file
+ *
+ * \brief Instance description for TCC0
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_TCC0_INSTANCE_
+#define _SAMD21_TCC0_INSTANCE_
+
+/* ========== Register definition for TCC0 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TCC0_CTRLA (0x42002000U) /**< \brief (TCC0) Control A */
+#define REG_TCC0_CTRLBCLR (0x42002004U) /**< \brief (TCC0) Control B Clear */
+#define REG_TCC0_CTRLBSET (0x42002005U) /**< \brief (TCC0) Control B Set */
+#define REG_TCC0_SYNCBUSY (0x42002008U) /**< \brief (TCC0) Synchronization Busy */
+#define REG_TCC0_FCTRLA (0x4200200CU) /**< \brief (TCC0) Recoverable Fault A Configuration */
+#define REG_TCC0_FCTRLB (0x42002010U) /**< \brief (TCC0) Recoverable Fault B Configuration */
+#define REG_TCC0_WEXCTRL (0x42002014U) /**< \brief (TCC0) Waveform Extension Configuration */
+#define REG_TCC0_DRVCTRL (0x42002018U) /**< \brief (TCC0) Driver Control */
+#define REG_TCC0_DBGCTRL (0x4200201EU) /**< \brief (TCC0) Debug Control */
+#define REG_TCC0_EVCTRL (0x42002020U) /**< \brief (TCC0) Event Control */
+#define REG_TCC0_INTENCLR (0x42002024U) /**< \brief (TCC0) Interrupt Enable Clear */
+#define REG_TCC0_INTENSET (0x42002028U) /**< \brief (TCC0) Interrupt Enable Set */
+#define REG_TCC0_INTFLAG (0x4200202CU) /**< \brief (TCC0) Interrupt Flag Status and Clear */
+#define REG_TCC0_STATUS (0x42002030U) /**< \brief (TCC0) Status */
+#define REG_TCC0_COUNT (0x42002034U) /**< \brief (TCC0) Count */
+#define REG_TCC0_PATT (0x42002038U) /**< \brief (TCC0) Pattern */
+#define REG_TCC0_WAVE (0x4200203CU) /**< \brief (TCC0) Waveform Control */
+#define REG_TCC0_PER (0x42002040U) /**< \brief (TCC0) Period */
+#define REG_TCC0_CC0 (0x42002044U) /**< \brief (TCC0) Compare and Capture 0 */
+#define REG_TCC0_CC1 (0x42002048U) /**< \brief (TCC0) Compare and Capture 1 */
+#define REG_TCC0_CC2 (0x4200204CU) /**< \brief (TCC0) Compare and Capture 2 */
+#define REG_TCC0_CC3 (0x42002050U) /**< \brief (TCC0) Compare and Capture 3 */
+#define REG_TCC0_PATTB (0x42002064U) /**< \brief (TCC0) Pattern Buffer */
+#define REG_TCC0_WAVEB (0x42002068U) /**< \brief (TCC0) Waveform Control Buffer */
+#define REG_TCC0_PERB (0x4200206CU) /**< \brief (TCC0) Period Buffer */
+#define REG_TCC0_CCB0 (0x42002070U) /**< \brief (TCC0) Compare and Capture Buffer 0 */
+#define REG_TCC0_CCB1 (0x42002074U) /**< \brief (TCC0) Compare and Capture Buffer 1 */
+#define REG_TCC0_CCB2 (0x42002078U) /**< \brief (TCC0) Compare and Capture Buffer 2 */
+#define REG_TCC0_CCB3 (0x4200207CU) /**< \brief (TCC0) Compare and Capture Buffer 3 */
+#else
+#define REG_TCC0_CTRLA (*(RwReg *)0x42002000U) /**< \brief (TCC0) Control A */
+#define REG_TCC0_CTRLBCLR (*(RwReg8 *)0x42002004U) /**< \brief (TCC0) Control B Clear */
+#define REG_TCC0_CTRLBSET (*(RwReg8 *)0x42002005U) /**< \brief (TCC0) Control B Set */
+#define REG_TCC0_SYNCBUSY (*(RoReg *)0x42002008U) /**< \brief (TCC0) Synchronization Busy */
+#define REG_TCC0_FCTRLA (*(RwReg *)0x4200200CU) /**< \brief (TCC0) Recoverable Fault A Configuration */
+#define REG_TCC0_FCTRLB (*(RwReg *)0x42002010U) /**< \brief (TCC0) Recoverable Fault B Configuration */
+#define REG_TCC0_WEXCTRL (*(RwReg *)0x42002014U) /**< \brief (TCC0) Waveform Extension Configuration */
+#define REG_TCC0_DRVCTRL (*(RwReg *)0x42002018U) /**< \brief (TCC0) Driver Control */
+#define REG_TCC0_DBGCTRL (*(RwReg8 *)0x4200201EU) /**< \brief (TCC0) Debug Control */
+#define REG_TCC0_EVCTRL (*(RwReg *)0x42002020U) /**< \brief (TCC0) Event Control */
+#define REG_TCC0_INTENCLR (*(RwReg *)0x42002024U) /**< \brief (TCC0) Interrupt Enable Clear */
+#define REG_TCC0_INTENSET (*(RwReg *)0x42002028U) /**< \brief (TCC0) Interrupt Enable Set */
+#define REG_TCC0_INTFLAG (*(RwReg *)0x4200202CU) /**< \brief (TCC0) Interrupt Flag Status and Clear */
+#define REG_TCC0_STATUS (*(RwReg *)0x42002030U) /**< \brief (TCC0) Status */
+#define REG_TCC0_COUNT (*(RwReg *)0x42002034U) /**< \brief (TCC0) Count */
+#define REG_TCC0_PATT (*(RwReg16*)0x42002038U) /**< \brief (TCC0) Pattern */
+#define REG_TCC0_WAVE (*(RwReg *)0x4200203CU) /**< \brief (TCC0) Waveform Control */
+#define REG_TCC0_PER (*(RwReg *)0x42002040U) /**< \brief (TCC0) Period */
+#define REG_TCC0_CC0 (*(RwReg *)0x42002044U) /**< \brief (TCC0) Compare and Capture 0 */
+#define REG_TCC0_CC1 (*(RwReg *)0x42002048U) /**< \brief (TCC0) Compare and Capture 1 */
+#define REG_TCC0_CC2 (*(RwReg *)0x4200204CU) /**< \brief (TCC0) Compare and Capture 2 */
+#define REG_TCC0_CC3 (*(RwReg *)0x42002050U) /**< \brief (TCC0) Compare and Capture 3 */
+#define REG_TCC0_PATTB (*(RwReg16*)0x42002064U) /**< \brief (TCC0) Pattern Buffer */
+#define REG_TCC0_WAVEB (*(RwReg *)0x42002068U) /**< \brief (TCC0) Waveform Control Buffer */
+#define REG_TCC0_PERB (*(RwReg *)0x4200206CU) /**< \brief (TCC0) Period Buffer */
+#define REG_TCC0_CCB0 (*(RwReg *)0x42002070U) /**< \brief (TCC0) Compare and Capture Buffer 0 */
+#define REG_TCC0_CCB1 (*(RwReg *)0x42002074U) /**< \brief (TCC0) Compare and Capture Buffer 1 */
+#define REG_TCC0_CCB2 (*(RwReg *)0x42002078U) /**< \brief (TCC0) Compare and Capture Buffer 2 */
+#define REG_TCC0_CCB3 (*(RwReg *)0x4200207CU) /**< \brief (TCC0) Compare and Capture Buffer 3 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TCC0 peripheral ========== */
+#define TCC0_CC_NUM 4 // Number of Compare/Capture units
+#define TCC0_DITHERING 1 // Dithering feature implemented
+#define TCC0_DMAC_ID_MC_0 14
+#define TCC0_DMAC_ID_MC_1 15
+#define TCC0_DMAC_ID_MC_2 16
+#define TCC0_DMAC_ID_MC_3 17
+#define TCC0_DMAC_ID_MC_LSB 14
+#define TCC0_DMAC_ID_MC_MSB 17
+#define TCC0_DMAC_ID_MC_SIZE 4
+#define TCC0_DMAC_ID_OVF 13 // DMA overflow/underflow/retrigger trigger
+#define TCC0_DTI 1 // Dead-Time-Insertion feature implemented
+#define TCC0_EXT 31 // (@_DITHERING*16+@_PG*8+@_SWAP*4+@_DTI*2+@_OTMX*1)
+#define TCC0_GCLK_ID 26 // Index of Generic Clock
+#define TCC0_OTMX 1 // Output Matrix feature implemented
+#define TCC0_OW_NUM 8 // Number of Output Waveforms
+#define TCC0_PG 1 // Pattern Generation feature implemented
+#define TCC0_SIZE 24
+#define TCC0_SWAP 1 // DTI outputs swap feature implemented
+#define TCC0_TYPE 0 // TCC type 0 : NA, 1 : Master, 2 : Slave
+
+#endif /* _SAMD21_TCC0_INSTANCE_ */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/tcc1.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/tcc1.h
new file mode 100644
index 0000000000000000000000000000000000000000..72f08224e15961cb332e730f31755f58f957281c
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/tcc1.h
@@ -0,0 +1,119 @@
+/**
+ * \file
+ *
+ * \brief Instance description for TCC1
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_TCC1_INSTANCE_
+#define _SAMD21_TCC1_INSTANCE_
+
+/* ========== Register definition for TCC1 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TCC1_CTRLA (0x42002400U) /**< \brief (TCC1) Control A */
+#define REG_TCC1_CTRLBCLR (0x42002404U) /**< \brief (TCC1) Control B Clear */
+#define REG_TCC1_CTRLBSET (0x42002405U) /**< \brief (TCC1) Control B Set */
+#define REG_TCC1_SYNCBUSY (0x42002408U) /**< \brief (TCC1) Synchronization Busy */
+#define REG_TCC1_FCTRLA (0x4200240CU) /**< \brief (TCC1) Recoverable Fault A Configuration */
+#define REG_TCC1_FCTRLB (0x42002410U) /**< \brief (TCC1) Recoverable Fault B Configuration */
+#define REG_TCC1_DRVCTRL (0x42002418U) /**< \brief (TCC1) Driver Control */
+#define REG_TCC1_DBGCTRL (0x4200241EU) /**< \brief (TCC1) Debug Control */
+#define REG_TCC1_EVCTRL (0x42002420U) /**< \brief (TCC1) Event Control */
+#define REG_TCC1_INTENCLR (0x42002424U) /**< \brief (TCC1) Interrupt Enable Clear */
+#define REG_TCC1_INTENSET (0x42002428U) /**< \brief (TCC1) Interrupt Enable Set */
+#define REG_TCC1_INTFLAG (0x4200242CU) /**< \brief (TCC1) Interrupt Flag Status and Clear */
+#define REG_TCC1_STATUS (0x42002430U) /**< \brief (TCC1) Status */
+#define REG_TCC1_COUNT (0x42002434U) /**< \brief (TCC1) Count */
+#define REG_TCC1_PATT (0x42002438U) /**< \brief (TCC1) Pattern */
+#define REG_TCC1_WAVE (0x4200243CU) /**< \brief (TCC1) Waveform Control */
+#define REG_TCC1_PER (0x42002440U) /**< \brief (TCC1) Period */
+#define REG_TCC1_CC0 (0x42002444U) /**< \brief (TCC1) Compare and Capture 0 */
+#define REG_TCC1_CC1 (0x42002448U) /**< \brief (TCC1) Compare and Capture 1 */
+#define REG_TCC1_PATTB (0x42002464U) /**< \brief (TCC1) Pattern Buffer */
+#define REG_TCC1_WAVEB (0x42002468U) /**< \brief (TCC1) Waveform Control Buffer */
+#define REG_TCC1_PERB (0x4200246CU) /**< \brief (TCC1) Period Buffer */
+#define REG_TCC1_CCB0 (0x42002470U) /**< \brief (TCC1) Compare and Capture Buffer 0 */
+#define REG_TCC1_CCB1 (0x42002474U) /**< \brief (TCC1) Compare and Capture Buffer 1 */
+#else
+#define REG_TCC1_CTRLA (*(RwReg *)0x42002400U) /**< \brief (TCC1) Control A */
+#define REG_TCC1_CTRLBCLR (*(RwReg8 *)0x42002404U) /**< \brief (TCC1) Control B Clear */
+#define REG_TCC1_CTRLBSET (*(RwReg8 *)0x42002405U) /**< \brief (TCC1) Control B Set */
+#define REG_TCC1_SYNCBUSY (*(RoReg *)0x42002408U) /**< \brief (TCC1) Synchronization Busy */
+#define REG_TCC1_FCTRLA (*(RwReg *)0x4200240CU) /**< \brief (TCC1) Recoverable Fault A Configuration */
+#define REG_TCC1_FCTRLB (*(RwReg *)0x42002410U) /**< \brief (TCC1) Recoverable Fault B Configuration */
+#define REG_TCC1_DRVCTRL (*(RwReg *)0x42002418U) /**< \brief (TCC1) Driver Control */
+#define REG_TCC1_DBGCTRL (*(RwReg8 *)0x4200241EU) /**< \brief (TCC1) Debug Control */
+#define REG_TCC1_EVCTRL (*(RwReg *)0x42002420U) /**< \brief (TCC1) Event Control */
+#define REG_TCC1_INTENCLR (*(RwReg *)0x42002424U) /**< \brief (TCC1) Interrupt Enable Clear */
+#define REG_TCC1_INTENSET (*(RwReg *)0x42002428U) /**< \brief (TCC1) Interrupt Enable Set */
+#define REG_TCC1_INTFLAG (*(RwReg *)0x4200242CU) /**< \brief (TCC1) Interrupt Flag Status and Clear */
+#define REG_TCC1_STATUS (*(RwReg *)0x42002430U) /**< \brief (TCC1) Status */
+#define REG_TCC1_COUNT (*(RwReg *)0x42002434U) /**< \brief (TCC1) Count */
+#define REG_TCC1_PATT (*(RwReg16*)0x42002438U) /**< \brief (TCC1) Pattern */
+#define REG_TCC1_WAVE (*(RwReg *)0x4200243CU) /**< \brief (TCC1) Waveform Control */
+#define REG_TCC1_PER (*(RwReg *)0x42002440U) /**< \brief (TCC1) Period */
+#define REG_TCC1_CC0 (*(RwReg *)0x42002444U) /**< \brief (TCC1) Compare and Capture 0 */
+#define REG_TCC1_CC1 (*(RwReg *)0x42002448U) /**< \brief (TCC1) Compare and Capture 1 */
+#define REG_TCC1_PATTB (*(RwReg16*)0x42002464U) /**< \brief (TCC1) Pattern Buffer */
+#define REG_TCC1_WAVEB (*(RwReg *)0x42002468U) /**< \brief (TCC1) Waveform Control Buffer */
+#define REG_TCC1_PERB (*(RwReg *)0x4200246CU) /**< \brief (TCC1) Period Buffer */
+#define REG_TCC1_CCB0 (*(RwReg *)0x42002470U) /**< \brief (TCC1) Compare and Capture Buffer 0 */
+#define REG_TCC1_CCB1 (*(RwReg *)0x42002474U) /**< \brief (TCC1) Compare and Capture Buffer 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TCC1 peripheral ========== */
+#define TCC1_CC_NUM 2 // Number of Compare/Capture units
+#define TCC1_DITHERING 1 // Dithering feature implemented
+#define TCC1_DMAC_ID_MC_0 19
+#define TCC1_DMAC_ID_MC_1 20
+#define TCC1_DMAC_ID_MC_LSB 19
+#define TCC1_DMAC_ID_MC_MSB 20
+#define TCC1_DMAC_ID_MC_SIZE 2
+#define TCC1_DMAC_ID_OVF 18 // DMA overflow/underflow/retrigger trigger
+#define TCC1_DTI 0 // Dead-Time-Insertion feature implemented
+#define TCC1_EXT 24 // Coding of implemented extended features
+#define TCC1_GCLK_ID 26 // Index of Generic Clock
+#define TCC1_OTMX 0 // Output Matrix feature implemented
+#define TCC1_OW_NUM 4 // Number of Output Waveforms
+#define TCC1_PG 1 // Pattern Generation feature implemented
+#define TCC1_SIZE 24
+#define TCC1_SWAP 0 // DTI outputs swap feature implemented
+#define TCC1_TYPE 0 // TCC type 0 : NA, 1 : Master, 2 : Slave
+
+#endif /* _SAMD21_TCC1_INSTANCE_ */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/tcc2.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/tcc2.h
new file mode 100644
index 0000000000000000000000000000000000000000..c8112168a82b5bd352656c8b7eacf04ab8702c53
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/tcc2.h
@@ -0,0 +1,115 @@
+/**
+ * \file
+ *
+ * \brief Instance description for TCC2
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_TCC2_INSTANCE_
+#define _SAMD21_TCC2_INSTANCE_
+
+/* ========== Register definition for TCC2 peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_TCC2_CTRLA (0x42002800U) /**< \brief (TCC2) Control A */
+#define REG_TCC2_CTRLBCLR (0x42002804U) /**< \brief (TCC2) Control B Clear */
+#define REG_TCC2_CTRLBSET (0x42002805U) /**< \brief (TCC2) Control B Set */
+#define REG_TCC2_SYNCBUSY (0x42002808U) /**< \brief (TCC2) Synchronization Busy */
+#define REG_TCC2_FCTRLA (0x4200280CU) /**< \brief (TCC2) Recoverable Fault A Configuration */
+#define REG_TCC2_FCTRLB (0x42002810U) /**< \brief (TCC2) Recoverable Fault B Configuration */
+#define REG_TCC2_DRVCTRL (0x42002818U) /**< \brief (TCC2) Driver Control */
+#define REG_TCC2_DBGCTRL (0x4200281EU) /**< \brief (TCC2) Debug Control */
+#define REG_TCC2_EVCTRL (0x42002820U) /**< \brief (TCC2) Event Control */
+#define REG_TCC2_INTENCLR (0x42002824U) /**< \brief (TCC2) Interrupt Enable Clear */
+#define REG_TCC2_INTENSET (0x42002828U) /**< \brief (TCC2) Interrupt Enable Set */
+#define REG_TCC2_INTFLAG (0x4200282CU) /**< \brief (TCC2) Interrupt Flag Status and Clear */
+#define REG_TCC2_STATUS (0x42002830U) /**< \brief (TCC2) Status */
+#define REG_TCC2_COUNT (0x42002834U) /**< \brief (TCC2) Count */
+#define REG_TCC2_WAVE (0x4200283CU) /**< \brief (TCC2) Waveform Control */
+#define REG_TCC2_PER (0x42002840U) /**< \brief (TCC2) Period */
+#define REG_TCC2_CC0 (0x42002844U) /**< \brief (TCC2) Compare and Capture 0 */
+#define REG_TCC2_CC1 (0x42002848U) /**< \brief (TCC2) Compare and Capture 1 */
+#define REG_TCC2_WAVEB (0x42002868U) /**< \brief (TCC2) Waveform Control Buffer */
+#define REG_TCC2_PERB (0x4200286CU) /**< \brief (TCC2) Period Buffer */
+#define REG_TCC2_CCB0 (0x42002870U) /**< \brief (TCC2) Compare and Capture Buffer 0 */
+#define REG_TCC2_CCB1 (0x42002874U) /**< \brief (TCC2) Compare and Capture Buffer 1 */
+#else
+#define REG_TCC2_CTRLA (*(RwReg *)0x42002800U) /**< \brief (TCC2) Control A */
+#define REG_TCC2_CTRLBCLR (*(RwReg8 *)0x42002804U) /**< \brief (TCC2) Control B Clear */
+#define REG_TCC2_CTRLBSET (*(RwReg8 *)0x42002805U) /**< \brief (TCC2) Control B Set */
+#define REG_TCC2_SYNCBUSY (*(RoReg *)0x42002808U) /**< \brief (TCC2) Synchronization Busy */
+#define REG_TCC2_FCTRLA (*(RwReg *)0x4200280CU) /**< \brief (TCC2) Recoverable Fault A Configuration */
+#define REG_TCC2_FCTRLB (*(RwReg *)0x42002810U) /**< \brief (TCC2) Recoverable Fault B Configuration */
+#define REG_TCC2_DRVCTRL (*(RwReg *)0x42002818U) /**< \brief (TCC2) Driver Control */
+#define REG_TCC2_DBGCTRL (*(RwReg8 *)0x4200281EU) /**< \brief (TCC2) Debug Control */
+#define REG_TCC2_EVCTRL (*(RwReg *)0x42002820U) /**< \brief (TCC2) Event Control */
+#define REG_TCC2_INTENCLR (*(RwReg *)0x42002824U) /**< \brief (TCC2) Interrupt Enable Clear */
+#define REG_TCC2_INTENSET (*(RwReg *)0x42002828U) /**< \brief (TCC2) Interrupt Enable Set */
+#define REG_TCC2_INTFLAG (*(RwReg *)0x4200282CU) /**< \brief (TCC2) Interrupt Flag Status and Clear */
+#define REG_TCC2_STATUS (*(RwReg *)0x42002830U) /**< \brief (TCC2) Status */
+#define REG_TCC2_COUNT (*(RwReg *)0x42002834U) /**< \brief (TCC2) Count */
+#define REG_TCC2_WAVE (*(RwReg *)0x4200283CU) /**< \brief (TCC2) Waveform Control */
+#define REG_TCC2_PER (*(RwReg *)0x42002840U) /**< \brief (TCC2) Period */
+#define REG_TCC2_CC0 (*(RwReg *)0x42002844U) /**< \brief (TCC2) Compare and Capture 0 */
+#define REG_TCC2_CC1 (*(RwReg *)0x42002848U) /**< \brief (TCC2) Compare and Capture 1 */
+#define REG_TCC2_WAVEB (*(RwReg *)0x42002868U) /**< \brief (TCC2) Waveform Control Buffer */
+#define REG_TCC2_PERB (*(RwReg *)0x4200286CU) /**< \brief (TCC2) Period Buffer */
+#define REG_TCC2_CCB0 (*(RwReg *)0x42002870U) /**< \brief (TCC2) Compare and Capture Buffer 0 */
+#define REG_TCC2_CCB1 (*(RwReg *)0x42002874U) /**< \brief (TCC2) Compare and Capture Buffer 1 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for TCC2 peripheral ========== */
+#define TCC2_CC_NUM 2 // Number of Compare/Capture units
+#define TCC2_DITHERING 0 // Dithering feature implemented
+#define TCC2_DMAC_ID_MC_0 22
+#define TCC2_DMAC_ID_MC_1 23
+#define TCC2_DMAC_ID_MC_LSB 22
+#define TCC2_DMAC_ID_MC_MSB 23
+#define TCC2_DMAC_ID_MC_SIZE 2
+#define TCC2_DMAC_ID_OVF 21 // DMA overflow/underflow/retrigger trigger
+#define TCC2_DTI 0 // Dead-Time-Insertion feature implemented
+#define TCC2_EXT 0 // Coding of implemented extended features
+#define TCC2_GCLK_ID 27 // Index of Generic Clock
+#define TCC2_OTMX 0 // Output Matrix feature implemented
+#define TCC2_OW_NUM 2 // Number of Output Waveforms
+#define TCC2_PG 0 // Pattern Generation feature implemented
+#define TCC2_SIZE 16
+#define TCC2_SWAP 0 // DTI outputs swap feature implemented
+#define TCC2_TYPE 0 // TCC type 0 : NA, 1 : Master, 2 : Slave
+
+#endif /* _SAMD21_TCC2_INSTANCE_ */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/usb.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/usb.h
new file mode 100644
index 0000000000000000000000000000000000000000..787d2912b5f61d375c8fb95ef96485421a3efe0e
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/usb.h
@@ -0,0 +1,344 @@
+/**
+ * \file
+ *
+ * \brief Instance description for USB
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_USB_INSTANCE_
+#define _SAMD21_USB_INSTANCE_
+
+/* ========== Register definition for USB peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_USB_CTRLA (0x41005000U) /**< \brief (USB) Control A */
+#define REG_USB_SYNCBUSY (0x41005002U) /**< \brief (USB) Synchronization Busy */
+#define REG_USB_QOSCTRL (0x41005003U) /**< \brief (USB) USB Quality Of Service */
+#define REG_USB_FSMSTATUS (0x4100500DU) /**< \brief (USB) Finite State Machine Status */
+#define REG_USB_DESCADD (0x41005024U) /**< \brief (USB) Descriptor Address */
+#define REG_USB_PADCAL (0x41005028U) /**< \brief (USB) USB PAD Calibration */
+#define REG_USB_DEVICE_CTRLB (0x41005008U) /**< \brief (USB) DEVICE Control B */
+#define REG_USB_DEVICE_DADD (0x4100500AU) /**< \brief (USB) DEVICE Device Address */
+#define REG_USB_DEVICE_STATUS (0x4100500CU) /**< \brief (USB) DEVICE Status */
+#define REG_USB_DEVICE_FNUM (0x41005010U) /**< \brief (USB) DEVICE Device Frame Number */
+#define REG_USB_DEVICE_INTENCLR (0x41005014U) /**< \brief (USB) DEVICE Device Interrupt Enable Clear */
+#define REG_USB_DEVICE_INTENSET (0x41005018U) /**< \brief (USB) DEVICE Device Interrupt Enable Set */
+#define REG_USB_DEVICE_INTFLAG (0x4100501CU) /**< \brief (USB) DEVICE Device Interrupt Flag */
+#define REG_USB_DEVICE_EPINTSMRY (0x41005020U) /**< \brief (USB) DEVICE End Point Interrupt Summary */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG0 (0x41005100U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR0 (0x41005104U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET0 (0x41005105U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS0 (0x41005106U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG0 (0x41005107U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR0 (0x41005108U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET0 (0x41005109U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG1 (0x41005120U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR1 (0x41005124U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET1 (0x41005125U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS1 (0x41005126U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG1 (0x41005127U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR1 (0x41005128U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET1 (0x41005129U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG2 (0x41005140U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR2 (0x41005144U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET2 (0x41005145U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS2 (0x41005146U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG2 (0x41005147U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR2 (0x41005148U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET2 (0x41005149U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG3 (0x41005160U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR3 (0x41005164U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET3 (0x41005165U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS3 (0x41005166U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG3 (0x41005167U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR3 (0x41005168U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET3 (0x41005169U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG4 (0x41005180U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR4 (0x41005184U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET4 (0x41005185U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS4 (0x41005186U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG4 (0x41005187U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR4 (0x41005188U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET4 (0x41005189U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG5 (0x410051A0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR5 (0x410051A4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET5 (0x410051A5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS5 (0x410051A6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG5 (0x410051A7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR5 (0x410051A8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET5 (0x410051A9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG6 (0x410051C0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR6 (0x410051C4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET6 (0x410051C5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS6 (0x410051C6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG6 (0x410051C7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR6 (0x410051C8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET6 (0x410051C9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG7 (0x410051E0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR7 (0x410051E4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET7 (0x410051E5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS7 (0x410051E6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG7 (0x410051E7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR7 (0x410051E8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET7 (0x410051E9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 7 */
+#define REG_USB_HOST_CTRLB (0x41005008U) /**< \brief (USB) HOST Control B */
+#define REG_USB_HOST_HSOFC (0x4100500AU) /**< \brief (USB) HOST Host Start Of Frame Control */
+#define REG_USB_HOST_STATUS (0x4100500CU) /**< \brief (USB) HOST Status */
+#define REG_USB_HOST_FNUM (0x41005010U) /**< \brief (USB) HOST Host Frame Number */
+#define REG_USB_HOST_FLENHIGH (0x41005012U) /**< \brief (USB) HOST Host Frame Length */
+#define REG_USB_HOST_INTENCLR (0x41005014U) /**< \brief (USB) HOST Host Interrupt Enable Clear */
+#define REG_USB_HOST_INTENSET (0x41005018U) /**< \brief (USB) HOST Host Interrupt Enable Set */
+#define REG_USB_HOST_INTFLAG (0x4100501CU) /**< \brief (USB) HOST Host Interrupt Flag */
+#define REG_USB_HOST_PINTSMRY (0x41005020U) /**< \brief (USB) HOST Pipe Interrupt Summary */
+#define REG_USB_HOST_PIPE_PCFG0 (0x41005100U) /**< \brief (USB) HOST_PIPE End Point Configuration 0 */
+#define REG_USB_HOST_PIPE_BINTERVAL0 (0x41005103U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 0 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR0 (0x41005104U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 0 */
+#define REG_USB_HOST_PIPE_PSTATUSSET0 (0x41005105U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 0 */
+#define REG_USB_HOST_PIPE_PSTATUS0 (0x41005106U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 0 */
+#define REG_USB_HOST_PIPE_PINTFLAG0 (0x41005107U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 0 */
+#define REG_USB_HOST_PIPE_PINTENCLR0 (0x41005108U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 0 */
+#define REG_USB_HOST_PIPE_PINTENSET0 (0x41005109U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 0 */
+#define REG_USB_HOST_PIPE_PCFG1 (0x41005120U) /**< \brief (USB) HOST_PIPE End Point Configuration 1 */
+#define REG_USB_HOST_PIPE_BINTERVAL1 (0x41005123U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 1 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR1 (0x41005124U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 1 */
+#define REG_USB_HOST_PIPE_PSTATUSSET1 (0x41005125U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 1 */
+#define REG_USB_HOST_PIPE_PSTATUS1 (0x41005126U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 1 */
+#define REG_USB_HOST_PIPE_PINTFLAG1 (0x41005127U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 1 */
+#define REG_USB_HOST_PIPE_PINTENCLR1 (0x41005128U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 1 */
+#define REG_USB_HOST_PIPE_PINTENSET1 (0x41005129U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 1 */
+#define REG_USB_HOST_PIPE_PCFG2 (0x41005140U) /**< \brief (USB) HOST_PIPE End Point Configuration 2 */
+#define REG_USB_HOST_PIPE_BINTERVAL2 (0x41005143U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 2 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR2 (0x41005144U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 2 */
+#define REG_USB_HOST_PIPE_PSTATUSSET2 (0x41005145U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 2 */
+#define REG_USB_HOST_PIPE_PSTATUS2 (0x41005146U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 2 */
+#define REG_USB_HOST_PIPE_PINTFLAG2 (0x41005147U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 2 */
+#define REG_USB_HOST_PIPE_PINTENCLR2 (0x41005148U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 2 */
+#define REG_USB_HOST_PIPE_PINTENSET2 (0x41005149U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 2 */
+#define REG_USB_HOST_PIPE_PCFG3 (0x41005160U) /**< \brief (USB) HOST_PIPE End Point Configuration 3 */
+#define REG_USB_HOST_PIPE_BINTERVAL3 (0x41005163U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 3 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR3 (0x41005164U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 3 */
+#define REG_USB_HOST_PIPE_PSTATUSSET3 (0x41005165U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 3 */
+#define REG_USB_HOST_PIPE_PSTATUS3 (0x41005166U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 3 */
+#define REG_USB_HOST_PIPE_PINTFLAG3 (0x41005167U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 3 */
+#define REG_USB_HOST_PIPE_PINTENCLR3 (0x41005168U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 3 */
+#define REG_USB_HOST_PIPE_PINTENSET3 (0x41005169U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 3 */
+#define REG_USB_HOST_PIPE_PCFG4 (0x41005180U) /**< \brief (USB) HOST_PIPE End Point Configuration 4 */
+#define REG_USB_HOST_PIPE_BINTERVAL4 (0x41005183U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 4 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR4 (0x41005184U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 4 */
+#define REG_USB_HOST_PIPE_PSTATUSSET4 (0x41005185U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 4 */
+#define REG_USB_HOST_PIPE_PSTATUS4 (0x41005186U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 4 */
+#define REG_USB_HOST_PIPE_PINTFLAG4 (0x41005187U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 4 */
+#define REG_USB_HOST_PIPE_PINTENCLR4 (0x41005188U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 4 */
+#define REG_USB_HOST_PIPE_PINTENSET4 (0x41005189U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 4 */
+#define REG_USB_HOST_PIPE_PCFG5 (0x410051A0U) /**< \brief (USB) HOST_PIPE End Point Configuration 5 */
+#define REG_USB_HOST_PIPE_BINTERVAL5 (0x410051A3U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 5 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR5 (0x410051A4U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 5 */
+#define REG_USB_HOST_PIPE_PSTATUSSET5 (0x410051A5U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 5 */
+#define REG_USB_HOST_PIPE_PSTATUS5 (0x410051A6U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 5 */
+#define REG_USB_HOST_PIPE_PINTFLAG5 (0x410051A7U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 5 */
+#define REG_USB_HOST_PIPE_PINTENCLR5 (0x410051A8U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 5 */
+#define REG_USB_HOST_PIPE_PINTENSET5 (0x410051A9U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 5 */
+#define REG_USB_HOST_PIPE_PCFG6 (0x410051C0U) /**< \brief (USB) HOST_PIPE End Point Configuration 6 */
+#define REG_USB_HOST_PIPE_BINTERVAL6 (0x410051C3U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 6 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR6 (0x410051C4U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 6 */
+#define REG_USB_HOST_PIPE_PSTATUSSET6 (0x410051C5U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 6 */
+#define REG_USB_HOST_PIPE_PSTATUS6 (0x410051C6U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 6 */
+#define REG_USB_HOST_PIPE_PINTFLAG6 (0x410051C7U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 6 */
+#define REG_USB_HOST_PIPE_PINTENCLR6 (0x410051C8U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 6 */
+#define REG_USB_HOST_PIPE_PINTENSET6 (0x410051C9U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 6 */
+#define REG_USB_HOST_PIPE_PCFG7 (0x410051E0U) /**< \brief (USB) HOST_PIPE End Point Configuration 7 */
+#define REG_USB_HOST_PIPE_BINTERVAL7 (0x410051E3U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 7 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR7 (0x410051E4U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 7 */
+#define REG_USB_HOST_PIPE_PSTATUSSET7 (0x410051E5U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 7 */
+#define REG_USB_HOST_PIPE_PSTATUS7 (0x410051E6U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 7 */
+#define REG_USB_HOST_PIPE_PINTFLAG7 (0x410051E7U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 7 */
+#define REG_USB_HOST_PIPE_PINTENCLR7 (0x410051E8U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 7 */
+#define REG_USB_HOST_PIPE_PINTENSET7 (0x410051E9U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 7 */
+#else
+#define REG_USB_CTRLA (*(RwReg8 *)0x41005000U) /**< \brief (USB) Control A */
+#define REG_USB_SYNCBUSY (*(RoReg8 *)0x41005002U) /**< \brief (USB) Synchronization Busy */
+#define REG_USB_QOSCTRL (*(RwReg8 *)0x41005003U) /**< \brief (USB) USB Quality Of Service */
+#define REG_USB_FSMSTATUS (*(RoReg8 *)0x4100500DU) /**< \brief (USB) Finite State Machine Status */
+#define REG_USB_DESCADD (*(RwReg *)0x41005024U) /**< \brief (USB) Descriptor Address */
+#define REG_USB_PADCAL (*(RwReg16*)0x41005028U) /**< \brief (USB) USB PAD Calibration */
+#define REG_USB_DEVICE_CTRLB (*(RwReg16*)0x41005008U) /**< \brief (USB) DEVICE Control B */
+#define REG_USB_DEVICE_DADD (*(RwReg8 *)0x4100500AU) /**< \brief (USB) DEVICE Device Address */
+#define REG_USB_DEVICE_STATUS (*(RoReg8 *)0x4100500CU) /**< \brief (USB) DEVICE Status */
+#define REG_USB_DEVICE_FNUM (*(RoReg16*)0x41005010U) /**< \brief (USB) DEVICE Device Frame Number */
+#define REG_USB_DEVICE_INTENCLR (*(RwReg16*)0x41005014U) /**< \brief (USB) DEVICE Device Interrupt Enable Clear */
+#define REG_USB_DEVICE_INTENSET (*(RwReg16*)0x41005018U) /**< \brief (USB) DEVICE Device Interrupt Enable Set */
+#define REG_USB_DEVICE_INTFLAG (*(RwReg16*)0x4100501CU) /**< \brief (USB) DEVICE Device Interrupt Flag */
+#define REG_USB_DEVICE_EPINTSMRY (*(RoReg16*)0x41005020U) /**< \brief (USB) DEVICE End Point Interrupt Summary */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG0 (*(RwReg8 *)0x41005100U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR0 (*(WoReg8 *)0x41005104U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET0 (*(WoReg8 *)0x41005105U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS0 (*(RoReg8 *)0x41005106U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG0 (*(RwReg8 *)0x41005107U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR0 (*(RwReg8 *)0x41005108U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET0 (*(RwReg8 *)0x41005109U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 0 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG1 (*(RwReg8 *)0x41005120U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR1 (*(WoReg8 *)0x41005124U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET1 (*(WoReg8 *)0x41005125U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS1 (*(RoReg8 *)0x41005126U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG1 (*(RwReg8 *)0x41005127U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR1 (*(RwReg8 *)0x41005128U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET1 (*(RwReg8 *)0x41005129U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 1 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG2 (*(RwReg8 *)0x41005140U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR2 (*(WoReg8 *)0x41005144U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET2 (*(WoReg8 *)0x41005145U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS2 (*(RoReg8 *)0x41005146U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG2 (*(RwReg8 *)0x41005147U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR2 (*(RwReg8 *)0x41005148U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET2 (*(RwReg8 *)0x41005149U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 2 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG3 (*(RwReg8 *)0x41005160U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR3 (*(WoReg8 *)0x41005164U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET3 (*(WoReg8 *)0x41005165U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS3 (*(RoReg8 *)0x41005166U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG3 (*(RwReg8 *)0x41005167U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR3 (*(RwReg8 *)0x41005168U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET3 (*(RwReg8 *)0x41005169U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 3 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG4 (*(RwReg8 *)0x41005180U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR4 (*(WoReg8 *)0x41005184U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET4 (*(WoReg8 *)0x41005185U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS4 (*(RoReg8 *)0x41005186U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG4 (*(RwReg8 *)0x41005187U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR4 (*(RwReg8 *)0x41005188U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET4 (*(RwReg8 *)0x41005189U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 4 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG5 (*(RwReg8 *)0x410051A0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR5 (*(WoReg8 *)0x410051A4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET5 (*(WoReg8 *)0x410051A5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS5 (*(RoReg8 *)0x410051A6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG5 (*(RwReg8 *)0x410051A7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR5 (*(RwReg8 *)0x410051A8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET5 (*(RwReg8 *)0x410051A9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 5 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG6 (*(RwReg8 *)0x410051C0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR6 (*(WoReg8 *)0x410051C4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET6 (*(WoReg8 *)0x410051C5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS6 (*(RoReg8 *)0x410051C6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG6 (*(RwReg8 *)0x410051C7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR6 (*(RwReg8 *)0x410051C8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET6 (*(RwReg8 *)0x410051C9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 6 */
+#define REG_USB_DEVICE_ENDPOINT_EPCFG7 (*(RwReg8 *)0x410051E0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR7 (*(WoReg8 *)0x410051E4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET7 (*(WoReg8 *)0x410051E5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPSTATUS7 (*(RoReg8 *)0x410051E6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG7 (*(RwReg8 *)0x410051E7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR7 (*(RwReg8 *)0x410051E8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 7 */
+#define REG_USB_DEVICE_ENDPOINT_EPINTENSET7 (*(RwReg8 *)0x410051E9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 7 */
+#define REG_USB_HOST_CTRLB (*(RwReg16*)0x41005008U) /**< \brief (USB) HOST Control B */
+#define REG_USB_HOST_HSOFC (*(RwReg8 *)0x4100500AU) /**< \brief (USB) HOST Host Start Of Frame Control */
+#define REG_USB_HOST_STATUS (*(RwReg8 *)0x4100500CU) /**< \brief (USB) HOST Status */
+#define REG_USB_HOST_FNUM (*(RwReg16*)0x41005010U) /**< \brief (USB) HOST Host Frame Number */
+#define REG_USB_HOST_FLENHIGH (*(RoReg8 *)0x41005012U) /**< \brief (USB) HOST Host Frame Length */
+#define REG_USB_HOST_INTENCLR (*(RwReg16*)0x41005014U) /**< \brief (USB) HOST Host Interrupt Enable Clear */
+#define REG_USB_HOST_INTENSET (*(RwReg16*)0x41005018U) /**< \brief (USB) HOST Host Interrupt Enable Set */
+#define REG_USB_HOST_INTFLAG (*(RwReg16*)0x4100501CU) /**< \brief (USB) HOST Host Interrupt Flag */
+#define REG_USB_HOST_PINTSMRY (*(RoReg16*)0x41005020U) /**< \brief (USB) HOST Pipe Interrupt Summary */
+#define REG_USB_HOST_PIPE_PCFG0 (*(RwReg8 *)0x41005100U) /**< \brief (USB) HOST_PIPE End Point Configuration 0 */
+#define REG_USB_HOST_PIPE_BINTERVAL0 (*(RwReg8 *)0x41005103U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 0 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR0 (*(WoReg8 *)0x41005104U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 0 */
+#define REG_USB_HOST_PIPE_PSTATUSSET0 (*(WoReg8 *)0x41005105U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 0 */
+#define REG_USB_HOST_PIPE_PSTATUS0 (*(RoReg8 *)0x41005106U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 0 */
+#define REG_USB_HOST_PIPE_PINTFLAG0 (*(RwReg8 *)0x41005107U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 0 */
+#define REG_USB_HOST_PIPE_PINTENCLR0 (*(RwReg8 *)0x41005108U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 0 */
+#define REG_USB_HOST_PIPE_PINTENSET0 (*(RwReg8 *)0x41005109U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 0 */
+#define REG_USB_HOST_PIPE_PCFG1 (*(RwReg8 *)0x41005120U) /**< \brief (USB) HOST_PIPE End Point Configuration 1 */
+#define REG_USB_HOST_PIPE_BINTERVAL1 (*(RwReg8 *)0x41005123U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 1 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR1 (*(WoReg8 *)0x41005124U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 1 */
+#define REG_USB_HOST_PIPE_PSTATUSSET1 (*(WoReg8 *)0x41005125U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 1 */
+#define REG_USB_HOST_PIPE_PSTATUS1 (*(RoReg8 *)0x41005126U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 1 */
+#define REG_USB_HOST_PIPE_PINTFLAG1 (*(RwReg8 *)0x41005127U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 1 */
+#define REG_USB_HOST_PIPE_PINTENCLR1 (*(RwReg8 *)0x41005128U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 1 */
+#define REG_USB_HOST_PIPE_PINTENSET1 (*(RwReg8 *)0x41005129U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 1 */
+#define REG_USB_HOST_PIPE_PCFG2 (*(RwReg8 *)0x41005140U) /**< \brief (USB) HOST_PIPE End Point Configuration 2 */
+#define REG_USB_HOST_PIPE_BINTERVAL2 (*(RwReg8 *)0x41005143U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 2 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR2 (*(WoReg8 *)0x41005144U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 2 */
+#define REG_USB_HOST_PIPE_PSTATUSSET2 (*(WoReg8 *)0x41005145U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 2 */
+#define REG_USB_HOST_PIPE_PSTATUS2 (*(RoReg8 *)0x41005146U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 2 */
+#define REG_USB_HOST_PIPE_PINTFLAG2 (*(RwReg8 *)0x41005147U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 2 */
+#define REG_USB_HOST_PIPE_PINTENCLR2 (*(RwReg8 *)0x41005148U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 2 */
+#define REG_USB_HOST_PIPE_PINTENSET2 (*(RwReg8 *)0x41005149U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 2 */
+#define REG_USB_HOST_PIPE_PCFG3 (*(RwReg8 *)0x41005160U) /**< \brief (USB) HOST_PIPE End Point Configuration 3 */
+#define REG_USB_HOST_PIPE_BINTERVAL3 (*(RwReg8 *)0x41005163U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 3 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR3 (*(WoReg8 *)0x41005164U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 3 */
+#define REG_USB_HOST_PIPE_PSTATUSSET3 (*(WoReg8 *)0x41005165U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 3 */
+#define REG_USB_HOST_PIPE_PSTATUS3 (*(RoReg8 *)0x41005166U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 3 */
+#define REG_USB_HOST_PIPE_PINTFLAG3 (*(RwReg8 *)0x41005167U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 3 */
+#define REG_USB_HOST_PIPE_PINTENCLR3 (*(RwReg8 *)0x41005168U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 3 */
+#define REG_USB_HOST_PIPE_PINTENSET3 (*(RwReg8 *)0x41005169U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 3 */
+#define REG_USB_HOST_PIPE_PCFG4 (*(RwReg8 *)0x41005180U) /**< \brief (USB) HOST_PIPE End Point Configuration 4 */
+#define REG_USB_HOST_PIPE_BINTERVAL4 (*(RwReg8 *)0x41005183U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 4 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR4 (*(WoReg8 *)0x41005184U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 4 */
+#define REG_USB_HOST_PIPE_PSTATUSSET4 (*(WoReg8 *)0x41005185U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 4 */
+#define REG_USB_HOST_PIPE_PSTATUS4 (*(RoReg8 *)0x41005186U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 4 */
+#define REG_USB_HOST_PIPE_PINTFLAG4 (*(RwReg8 *)0x41005187U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 4 */
+#define REG_USB_HOST_PIPE_PINTENCLR4 (*(RwReg8 *)0x41005188U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 4 */
+#define REG_USB_HOST_PIPE_PINTENSET4 (*(RwReg8 *)0x41005189U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 4 */
+#define REG_USB_HOST_PIPE_PCFG5 (*(RwReg8 *)0x410051A0U) /**< \brief (USB) HOST_PIPE End Point Configuration 5 */
+#define REG_USB_HOST_PIPE_BINTERVAL5 (*(RwReg8 *)0x410051A3U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 5 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR5 (*(WoReg8 *)0x410051A4U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 5 */
+#define REG_USB_HOST_PIPE_PSTATUSSET5 (*(WoReg8 *)0x410051A5U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 5 */
+#define REG_USB_HOST_PIPE_PSTATUS5 (*(RoReg8 *)0x410051A6U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 5 */
+#define REG_USB_HOST_PIPE_PINTFLAG5 (*(RwReg8 *)0x410051A7U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 5 */
+#define REG_USB_HOST_PIPE_PINTENCLR5 (*(RwReg8 *)0x410051A8U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 5 */
+#define REG_USB_HOST_PIPE_PINTENSET5 (*(RwReg8 *)0x410051A9U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 5 */
+#define REG_USB_HOST_PIPE_PCFG6 (*(RwReg8 *)0x410051C0U) /**< \brief (USB) HOST_PIPE End Point Configuration 6 */
+#define REG_USB_HOST_PIPE_BINTERVAL6 (*(RwReg8 *)0x410051C3U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 6 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR6 (*(WoReg8 *)0x410051C4U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 6 */
+#define REG_USB_HOST_PIPE_PSTATUSSET6 (*(WoReg8 *)0x410051C5U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 6 */
+#define REG_USB_HOST_PIPE_PSTATUS6 (*(RoReg8 *)0x410051C6U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 6 */
+#define REG_USB_HOST_PIPE_PINTFLAG6 (*(RwReg8 *)0x410051C7U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 6 */
+#define REG_USB_HOST_PIPE_PINTENCLR6 (*(RwReg8 *)0x410051C8U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 6 */
+#define REG_USB_HOST_PIPE_PINTENSET6 (*(RwReg8 *)0x410051C9U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 6 */
+#define REG_USB_HOST_PIPE_PCFG7 (*(RwReg8 *)0x410051E0U) /**< \brief (USB) HOST_PIPE End Point Configuration 7 */
+#define REG_USB_HOST_PIPE_BINTERVAL7 (*(RwReg8 *)0x410051E3U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 7 */
+#define REG_USB_HOST_PIPE_PSTATUSCLR7 (*(WoReg8 *)0x410051E4U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 7 */
+#define REG_USB_HOST_PIPE_PSTATUSSET7 (*(WoReg8 *)0x410051E5U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 7 */
+#define REG_USB_HOST_PIPE_PSTATUS7 (*(RoReg8 *)0x410051E6U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 7 */
+#define REG_USB_HOST_PIPE_PINTFLAG7 (*(RwReg8 *)0x410051E7U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 7 */
+#define REG_USB_HOST_PIPE_PINTENCLR7 (*(RwReg8 *)0x410051E8U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 7 */
+#define REG_USB_HOST_PIPE_PINTENSET7 (*(RwReg8 *)0x410051E9U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 7 */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for USB peripheral ========== */
+#define USB_EPT_NBR 8 // Number of USB end points (obsolete)
+#define USB_EPT_NUM 8 // Number of USB end points
+#define USB_GCLK_ID 6 // Index of Generic Clock
+#define USB_PIPE_NUM 8 // Number of USB pipes
+
+#endif /* _SAMD21_USB_INSTANCE_ */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/wdt.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/wdt.h
new file mode 100644
index 0000000000000000000000000000000000000000..8a672601b594052f5a5fe0dcc834e1de7b0d29fa
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/instance/wdt.h
@@ -0,0 +1,71 @@
+/**
+ * \file
+ *
+ * \brief Instance description for WDT
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_WDT_INSTANCE_
+#define _SAMD21_WDT_INSTANCE_
+
+/* ========== Register definition for WDT peripheral ========== */
+#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#define REG_WDT_CTRL (0x40001000U) /**< \brief (WDT) Control */
+#define REG_WDT_CONFIG (0x40001001U) /**< \brief (WDT) Configuration */
+#define REG_WDT_EWCTRL (0x40001002U) /**< \brief (WDT) Early Warning Interrupt Control */
+#define REG_WDT_INTENCLR (0x40001004U) /**< \brief (WDT) Interrupt Enable Clear */
+#define REG_WDT_INTENSET (0x40001005U) /**< \brief (WDT) Interrupt Enable Set */
+#define REG_WDT_INTFLAG (0x40001006U) /**< \brief (WDT) Interrupt Flag Status and Clear */
+#define REG_WDT_STATUS (0x40001007U) /**< \brief (WDT) Status */
+#define REG_WDT_CLEAR (0x40001008U) /**< \brief (WDT) Clear */
+#else
+#define REG_WDT_CTRL (*(RwReg8 *)0x40001000U) /**< \brief (WDT) Control */
+#define REG_WDT_CONFIG (*(RwReg8 *)0x40001001U) /**< \brief (WDT) Configuration */
+#define REG_WDT_EWCTRL (*(RwReg8 *)0x40001002U) /**< \brief (WDT) Early Warning Interrupt Control */
+#define REG_WDT_INTENCLR (*(RwReg8 *)0x40001004U) /**< \brief (WDT) Interrupt Enable Clear */
+#define REG_WDT_INTENSET (*(RwReg8 *)0x40001005U) /**< \brief (WDT) Interrupt Enable Set */
+#define REG_WDT_INTFLAG (*(RwReg8 *)0x40001006U) /**< \brief (WDT) Interrupt Flag Status and Clear */
+#define REG_WDT_STATUS (*(RoReg8 *)0x40001007U) /**< \brief (WDT) Status */
+#define REG_WDT_CLEAR (*(WoReg8 *)0x40001008U) /**< \brief (WDT) Clear */
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+
+/* ========== Instance parameters for WDT peripheral ========== */
+#define WDT_GCLK_ID 3 // Index of Generic Clock
+
+#endif /* _SAMD21_WDT_INSTANCE_ */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/pio/samd21e15a.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/pio/samd21e15a.h
new file mode 100644
index 0000000000000000000000000000000000000000..09af18455b257f60b274908045c7ddbcec27b5ca
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/pio/samd21e15a.h
@@ -0,0 +1,641 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21E15A
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21E15A_PIO_
+#define _SAMD21E15A_PIO_
+
+#define PIN_PA00 0 /**< \brief Pin Number for PA00 */
+#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */
+#define PIN_PA01 1 /**< \brief Pin Number for PA01 */
+#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */
+#define PIN_PA02 2 /**< \brief Pin Number for PA02 */
+#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */
+#define PIN_PA03 3 /**< \brief Pin Number for PA03 */
+#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */
+#define PIN_PA04 4 /**< \brief Pin Number for PA04 */
+#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */
+#define PIN_PA05 5 /**< \brief Pin Number for PA05 */
+#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */
+#define PIN_PA06 6 /**< \brief Pin Number for PA06 */
+#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */
+#define PIN_PA07 7 /**< \brief Pin Number for PA07 */
+#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */
+#define PIN_PA08 8 /**< \brief Pin Number for PA08 */
+#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */
+#define PIN_PA09 9 /**< \brief Pin Number for PA09 */
+#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */
+#define PIN_PA10 10 /**< \brief Pin Number for PA10 */
+#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */
+#define PIN_PA11 11 /**< \brief Pin Number for PA11 */
+#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */
+#define PIN_PA14 14 /**< \brief Pin Number for PA14 */
+#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */
+#define PIN_PA15 15 /**< \brief Pin Number for PA15 */
+#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */
+#define PIN_PA16 16 /**< \brief Pin Number for PA16 */
+#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */
+#define PIN_PA17 17 /**< \brief Pin Number for PA17 */
+#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */
+#define PIN_PA18 18 /**< \brief Pin Number for PA18 */
+#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */
+#define PIN_PA19 19 /**< \brief Pin Number for PA19 */
+#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */
+#define PIN_PA22 22 /**< \brief Pin Number for PA22 */
+#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */
+#define PIN_PA23 23 /**< \brief Pin Number for PA23 */
+#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */
+#define PIN_PA24 24 /**< \brief Pin Number for PA24 */
+#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */
+#define PIN_PA25 25 /**< \brief Pin Number for PA25 */
+#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */
+#define PIN_PA27 27 /**< \brief Pin Number for PA27 */
+#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */
+#define PIN_PA28 28 /**< \brief Pin Number for PA28 */
+#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */
+#define PIN_PA30 30 /**< \brief Pin Number for PA30 */
+#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */
+#define PIN_PA31 31 /**< \brief Pin Number for PA31 */
+#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0 7L
+#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0 (1ul << 14)
+#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0 7L
+#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0 (1ul << 27)
+#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0 7L
+#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0 (1ul << 28)
+#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0 7L
+#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0 (1ul << 30)
+#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1 7L
+#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1 (1ul << 15)
+#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2 7L
+#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2 (1ul << 16)
+#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3 7L
+#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3 (1ul << 17)
+#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4 7L
+#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4 (1ul << 10)
+#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5 7L
+#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5 (1ul << 11)
+#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6 7L
+#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6 (1ul << 22)
+#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7 7L
+#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7 (1ul << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0 0L
+#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0 (1ul << 16)
+#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0 0L
+#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0 (1ul << 0)
+#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1 0L
+#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1 (1ul << 17)
+#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1 0L
+#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1 (1ul << 1)
+#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2 0L
+#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2 (1ul << 18)
+#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2 0L
+#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2 (1ul << 2)
+#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3 0L
+#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3 (1ul << 3)
+#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3 0L
+#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3 (1ul << 19)
+#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4 0L
+#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4 (1ul << 4)
+#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5 0L
+#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5 (1ul << 5)
+#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6 0L
+#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6 (1ul << 6)
+#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6 0L
+#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6 (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7 0L
+#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7 (1ul << 7)
+#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7 0L
+#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7 (1ul << 23)
+#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8 0L
+#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8 (1ul << 28)
+#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9 0L
+#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9 (1ul << 9)
+#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10 0L
+#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10 (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10 0L
+#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10 (1ul << 30)
+#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11 0L
+#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11 (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11 0L
+#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11 (1ul << 31)
+#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12 0L
+#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12 (1ul << 24)
+#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13 0L
+#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13 (1ul << 25)
+#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14 0L
+#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14 (1ul << 14)
+#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15 0L
+#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15 (1ul << 15)
+#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15 0L
+#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15 (1ul << 27)
+#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI 0L
+#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI (1ul << 8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM 6L
+#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM (1ul << 24)
+#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP 6L
+#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP (1ul << 25)
+#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ 6L
+#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0 3L
+#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4)
+#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0 2L
+#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8)
+#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1 3L
+#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5)
+#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1 2L
+#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9)
+#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2 3L
+#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6)
+#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2 2L
+#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3 3L
+#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7)
+#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3 2L
+#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0 2L
+#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16)
+#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0 3L
+#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0)
+#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1 2L
+#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17)
+#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1 3L
+#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1)
+#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2 3L
+#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2 2L
+#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3 3L
+#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3 2L
+#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0 3L
+#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8)
+#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1 3L
+#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9)
+#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2 3L
+#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2 2L
+#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3 3L
+#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3 2L
+#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0 3L
+#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0 2L
+#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1 3L
+#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1 2L
+#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2 3L
+#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18)
+#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2 2L
+#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3 3L
+#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19)
+#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3 2L
+#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0 4L
+#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0 (1ul << 4)
+#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0 4L
+#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0 (1ul << 8)
+#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1 4L
+#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1 (1ul << 5)
+#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1 4L
+#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1 (1ul << 9)
+#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2 5L
+#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2 (1ul << 10)
+#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2 5L
+#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2 (1ul << 18)
+#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3 5L
+#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3 (1ul << 11)
+#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3 5L
+#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3 (1ul << 19)
+#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4 5L
+#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4 (1ul << 14)
+#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4 5L
+#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4 (1ul << 22)
+#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5 5L
+#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5 (1ul << 15)
+#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5 5L
+#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5 (1ul << 23)
+#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6 5L
+#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6 (1ul << 16)
+#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7 5L
+#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7 (1ul << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0 4L
+#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0 (1ul << 6)
+#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0 4L
+#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0 (1ul << 10)
+#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0 4L
+#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0 (1ul << 30)
+#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1 4L
+#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1 (1ul << 7)
+#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1 4L
+#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1 (1ul << 11)
+#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1 4L
+#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1 (1ul << 31)
+#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2 5L
+#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2 (1ul << 8)
+#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2 5L
+#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2 (1ul << 24)
+#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3 5L
+#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3 (1ul << 9)
+#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3 5L
+#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3 (1ul << 25)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0 4L
+#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0 (1ul << 16)
+#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0 4L
+#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0 (1ul << 0)
+#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1 4L
+#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1 (1ul << 17)
+#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1 4L
+#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1 (1ul << 1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0 4L
+#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0 (1ul << 18)
+#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0 4L
+#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0 (1ul << 14)
+#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1 4L
+#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1 (1ul << 19)
+#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1 4L
+#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1 (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0 4L
+#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0 (1ul << 22)
+#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1 4L
+#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1 (1ul << 23)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0 4L
+#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0 (1ul << 24)
+#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1 4L
+#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1 (1ul << 25)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0 1L
+#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0 (1ul << 2)
+#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1 1L
+#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1 (1ul << 3)
+#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4 1L
+#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4 (1ul << 4)
+#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5 1L
+#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5 (1ul << 5)
+#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6 1L
+#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6 (1ul << 6)
+#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7 1L
+#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7 (1ul << 7)
+#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16 1L
+#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16 (1ul << 8)
+#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17 1L
+#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17 (1ul << 9)
+#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18 1L
+#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18 (1ul << 10)
+#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19 1L
+#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19 (1ul << 11)
+#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP 1L
+#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP (1ul << 4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0 1L
+#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0 (1ul << 4)
+#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1 1L
+#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1 (1ul << 5)
+#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2 1L
+#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2 (1ul << 6)
+#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3 1L
+#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3 (1ul << 7)
+#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0 7L
+#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0 (1ul << 18)
+#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1 7L
+#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1 (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT 1L
+#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT (1ul << 2)
+#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP 1L
+#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP (1ul << 3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0 11L /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0 6L
+#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0 (1ul << 11)
+#define PIN_PA09G_I2S_MCK0 9L /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0 6L
+#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0 (1ul << 9)
+#define PIN_PA10G_I2S_SCK0 10L /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0 6L
+#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0 (1ul << 10)
+#define PIN_PA07G_I2S_SD0 7L /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0 6L
+#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0 (1ul << 7)
+#define PIN_PA19G_I2S_SD0 19L /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0 6L
+#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0 (1ul << 19)
+#define PIN_PA08G_I2S_SD1 8L /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1 6L
+#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1 (1ul << 8)
+
+#endif /* _SAMD21E15A_PIO_ */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/pio/samd21e16a.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/pio/samd21e16a.h
new file mode 100644
index 0000000000000000000000000000000000000000..3018877b91e341130264862014133e8ce89512ad
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/pio/samd21e16a.h
@@ -0,0 +1,641 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21E16A
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21E16A_PIO_
+#define _SAMD21E16A_PIO_
+
+#define PIN_PA00 0 /**< \brief Pin Number for PA00 */
+#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */
+#define PIN_PA01 1 /**< \brief Pin Number for PA01 */
+#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */
+#define PIN_PA02 2 /**< \brief Pin Number for PA02 */
+#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */
+#define PIN_PA03 3 /**< \brief Pin Number for PA03 */
+#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */
+#define PIN_PA04 4 /**< \brief Pin Number for PA04 */
+#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */
+#define PIN_PA05 5 /**< \brief Pin Number for PA05 */
+#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */
+#define PIN_PA06 6 /**< \brief Pin Number for PA06 */
+#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */
+#define PIN_PA07 7 /**< \brief Pin Number for PA07 */
+#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */
+#define PIN_PA08 8 /**< \brief Pin Number for PA08 */
+#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */
+#define PIN_PA09 9 /**< \brief Pin Number for PA09 */
+#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */
+#define PIN_PA10 10 /**< \brief Pin Number for PA10 */
+#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */
+#define PIN_PA11 11 /**< \brief Pin Number for PA11 */
+#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */
+#define PIN_PA14 14 /**< \brief Pin Number for PA14 */
+#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */
+#define PIN_PA15 15 /**< \brief Pin Number for PA15 */
+#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */
+#define PIN_PA16 16 /**< \brief Pin Number for PA16 */
+#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */
+#define PIN_PA17 17 /**< \brief Pin Number for PA17 */
+#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */
+#define PIN_PA18 18 /**< \brief Pin Number for PA18 */
+#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */
+#define PIN_PA19 19 /**< \brief Pin Number for PA19 */
+#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */
+#define PIN_PA22 22 /**< \brief Pin Number for PA22 */
+#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */
+#define PIN_PA23 23 /**< \brief Pin Number for PA23 */
+#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */
+#define PIN_PA24 24 /**< \brief Pin Number for PA24 */
+#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */
+#define PIN_PA25 25 /**< \brief Pin Number for PA25 */
+#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */
+#define PIN_PA27 27 /**< \brief Pin Number for PA27 */
+#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */
+#define PIN_PA28 28 /**< \brief Pin Number for PA28 */
+#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */
+#define PIN_PA30 30 /**< \brief Pin Number for PA30 */
+#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */
+#define PIN_PA31 31 /**< \brief Pin Number for PA31 */
+#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0 7L
+#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0 (1ul << 14)
+#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0 7L
+#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0 (1ul << 27)
+#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0 7L
+#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0 (1ul << 28)
+#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0 7L
+#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0 (1ul << 30)
+#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1 7L
+#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1 (1ul << 15)
+#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2 7L
+#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2 (1ul << 16)
+#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3 7L
+#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3 (1ul << 17)
+#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4 7L
+#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4 (1ul << 10)
+#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5 7L
+#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5 (1ul << 11)
+#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6 7L
+#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6 (1ul << 22)
+#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7 7L
+#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7 (1ul << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0 0L
+#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0 (1ul << 16)
+#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0 0L
+#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0 (1ul << 0)
+#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1 0L
+#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1 (1ul << 17)
+#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1 0L
+#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1 (1ul << 1)
+#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2 0L
+#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2 (1ul << 18)
+#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2 0L
+#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2 (1ul << 2)
+#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3 0L
+#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3 (1ul << 3)
+#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3 0L
+#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3 (1ul << 19)
+#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4 0L
+#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4 (1ul << 4)
+#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5 0L
+#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5 (1ul << 5)
+#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6 0L
+#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6 (1ul << 6)
+#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6 0L
+#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6 (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7 0L
+#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7 (1ul << 7)
+#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7 0L
+#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7 (1ul << 23)
+#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8 0L
+#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8 (1ul << 28)
+#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9 0L
+#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9 (1ul << 9)
+#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10 0L
+#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10 (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10 0L
+#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10 (1ul << 30)
+#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11 0L
+#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11 (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11 0L
+#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11 (1ul << 31)
+#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12 0L
+#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12 (1ul << 24)
+#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13 0L
+#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13 (1ul << 25)
+#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14 0L
+#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14 (1ul << 14)
+#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15 0L
+#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15 (1ul << 15)
+#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15 0L
+#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15 (1ul << 27)
+#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI 0L
+#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI (1ul << 8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM 6L
+#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM (1ul << 24)
+#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP 6L
+#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP (1ul << 25)
+#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ 6L
+#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0 3L
+#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4)
+#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0 2L
+#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8)
+#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1 3L
+#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5)
+#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1 2L
+#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9)
+#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2 3L
+#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6)
+#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2 2L
+#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3 3L
+#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7)
+#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3 2L
+#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0 2L
+#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16)
+#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0 3L
+#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0)
+#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1 2L
+#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17)
+#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1 3L
+#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1)
+#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2 3L
+#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2 2L
+#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3 3L
+#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3 2L
+#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0 3L
+#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8)
+#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1 3L
+#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9)
+#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2 3L
+#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2 2L
+#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3 3L
+#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3 2L
+#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0 3L
+#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0 2L
+#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1 3L
+#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1 2L
+#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2 3L
+#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18)
+#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2 2L
+#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3 3L
+#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19)
+#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3 2L
+#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0 4L
+#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0 (1ul << 4)
+#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0 4L
+#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0 (1ul << 8)
+#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1 4L
+#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1 (1ul << 5)
+#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1 4L
+#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1 (1ul << 9)
+#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2 5L
+#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2 (1ul << 10)
+#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2 5L
+#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2 (1ul << 18)
+#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3 5L
+#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3 (1ul << 11)
+#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3 5L
+#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3 (1ul << 19)
+#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4 5L
+#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4 (1ul << 14)
+#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4 5L
+#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4 (1ul << 22)
+#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5 5L
+#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5 (1ul << 15)
+#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5 5L
+#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5 (1ul << 23)
+#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6 5L
+#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6 (1ul << 16)
+#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7 5L
+#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7 (1ul << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0 4L
+#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0 (1ul << 6)
+#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0 4L
+#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0 (1ul << 10)
+#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0 4L
+#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0 (1ul << 30)
+#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1 4L
+#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1 (1ul << 7)
+#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1 4L
+#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1 (1ul << 11)
+#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1 4L
+#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1 (1ul << 31)
+#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2 5L
+#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2 (1ul << 8)
+#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2 5L
+#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2 (1ul << 24)
+#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3 5L
+#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3 (1ul << 9)
+#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3 5L
+#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3 (1ul << 25)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0 4L
+#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0 (1ul << 16)
+#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0 4L
+#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0 (1ul << 0)
+#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1 4L
+#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1 (1ul << 17)
+#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1 4L
+#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1 (1ul << 1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0 4L
+#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0 (1ul << 18)
+#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0 4L
+#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0 (1ul << 14)
+#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1 4L
+#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1 (1ul << 19)
+#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1 4L
+#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1 (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0 4L
+#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0 (1ul << 22)
+#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1 4L
+#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1 (1ul << 23)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0 4L
+#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0 (1ul << 24)
+#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1 4L
+#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1 (1ul << 25)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0 1L
+#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0 (1ul << 2)
+#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1 1L
+#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1 (1ul << 3)
+#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4 1L
+#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4 (1ul << 4)
+#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5 1L
+#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5 (1ul << 5)
+#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6 1L
+#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6 (1ul << 6)
+#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7 1L
+#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7 (1ul << 7)
+#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16 1L
+#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16 (1ul << 8)
+#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17 1L
+#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17 (1ul << 9)
+#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18 1L
+#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18 (1ul << 10)
+#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19 1L
+#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19 (1ul << 11)
+#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP 1L
+#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP (1ul << 4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0 1L
+#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0 (1ul << 4)
+#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1 1L
+#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1 (1ul << 5)
+#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2 1L
+#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2 (1ul << 6)
+#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3 1L
+#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3 (1ul << 7)
+#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0 7L
+#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0 (1ul << 18)
+#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1 7L
+#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1 (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT 1L
+#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT (1ul << 2)
+#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP 1L
+#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP (1ul << 3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0 11L /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0 6L
+#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0 (1ul << 11)
+#define PIN_PA09G_I2S_MCK0 9L /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0 6L
+#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0 (1ul << 9)
+#define PIN_PA10G_I2S_SCK0 10L /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0 6L
+#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0 (1ul << 10)
+#define PIN_PA07G_I2S_SD0 7L /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0 6L
+#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0 (1ul << 7)
+#define PIN_PA19G_I2S_SD0 19L /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0 6L
+#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0 (1ul << 19)
+#define PIN_PA08G_I2S_SD1 8L /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1 6L
+#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1 (1ul << 8)
+
+#endif /* _SAMD21E16A_PIO_ */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/pio/samd21e17a.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/pio/samd21e17a.h
new file mode 100644
index 0000000000000000000000000000000000000000..9b4c31398dd6491410597838800d4e0abe50cfbd
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/pio/samd21e17a.h
@@ -0,0 +1,641 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21E17A
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21E17A_PIO_
+#define _SAMD21E17A_PIO_
+
+#define PIN_PA00 0 /**< \brief Pin Number for PA00 */
+#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */
+#define PIN_PA01 1 /**< \brief Pin Number for PA01 */
+#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */
+#define PIN_PA02 2 /**< \brief Pin Number for PA02 */
+#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */
+#define PIN_PA03 3 /**< \brief Pin Number for PA03 */
+#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */
+#define PIN_PA04 4 /**< \brief Pin Number for PA04 */
+#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */
+#define PIN_PA05 5 /**< \brief Pin Number for PA05 */
+#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */
+#define PIN_PA06 6 /**< \brief Pin Number for PA06 */
+#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */
+#define PIN_PA07 7 /**< \brief Pin Number for PA07 */
+#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */
+#define PIN_PA08 8 /**< \brief Pin Number for PA08 */
+#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */
+#define PIN_PA09 9 /**< \brief Pin Number for PA09 */
+#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */
+#define PIN_PA10 10 /**< \brief Pin Number for PA10 */
+#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */
+#define PIN_PA11 11 /**< \brief Pin Number for PA11 */
+#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */
+#define PIN_PA14 14 /**< \brief Pin Number for PA14 */
+#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */
+#define PIN_PA15 15 /**< \brief Pin Number for PA15 */
+#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */
+#define PIN_PA16 16 /**< \brief Pin Number for PA16 */
+#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */
+#define PIN_PA17 17 /**< \brief Pin Number for PA17 */
+#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */
+#define PIN_PA18 18 /**< \brief Pin Number for PA18 */
+#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */
+#define PIN_PA19 19 /**< \brief Pin Number for PA19 */
+#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */
+#define PIN_PA22 22 /**< \brief Pin Number for PA22 */
+#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */
+#define PIN_PA23 23 /**< \brief Pin Number for PA23 */
+#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */
+#define PIN_PA24 24 /**< \brief Pin Number for PA24 */
+#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */
+#define PIN_PA25 25 /**< \brief Pin Number for PA25 */
+#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */
+#define PIN_PA27 27 /**< \brief Pin Number for PA27 */
+#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */
+#define PIN_PA28 28 /**< \brief Pin Number for PA28 */
+#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */
+#define PIN_PA30 30 /**< \brief Pin Number for PA30 */
+#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */
+#define PIN_PA31 31 /**< \brief Pin Number for PA31 */
+#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0 7L
+#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0 (1ul << 14)
+#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0 7L
+#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0 (1ul << 27)
+#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0 7L
+#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0 (1ul << 28)
+#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0 7L
+#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0 (1ul << 30)
+#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1 7L
+#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1 (1ul << 15)
+#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2 7L
+#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2 (1ul << 16)
+#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3 7L
+#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3 (1ul << 17)
+#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4 7L
+#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4 (1ul << 10)
+#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5 7L
+#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5 (1ul << 11)
+#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6 7L
+#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6 (1ul << 22)
+#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7 7L
+#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7 (1ul << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0 0L
+#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0 (1ul << 16)
+#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0 0L
+#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0 (1ul << 0)
+#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1 0L
+#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1 (1ul << 17)
+#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1 0L
+#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1 (1ul << 1)
+#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2 0L
+#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2 (1ul << 18)
+#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2 0L
+#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2 (1ul << 2)
+#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3 0L
+#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3 (1ul << 3)
+#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3 0L
+#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3 (1ul << 19)
+#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4 0L
+#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4 (1ul << 4)
+#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5 0L
+#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5 (1ul << 5)
+#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6 0L
+#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6 (1ul << 6)
+#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6 0L
+#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6 (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7 0L
+#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7 (1ul << 7)
+#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7 0L
+#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7 (1ul << 23)
+#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8 0L
+#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8 (1ul << 28)
+#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9 0L
+#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9 (1ul << 9)
+#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10 0L
+#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10 (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10 0L
+#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10 (1ul << 30)
+#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11 0L
+#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11 (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11 0L
+#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11 (1ul << 31)
+#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12 0L
+#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12 (1ul << 24)
+#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13 0L
+#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13 (1ul << 25)
+#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14 0L
+#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14 (1ul << 14)
+#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15 0L
+#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15 (1ul << 15)
+#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15 0L
+#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15 (1ul << 27)
+#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI 0L
+#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI (1ul << 8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM 6L
+#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM (1ul << 24)
+#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP 6L
+#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP (1ul << 25)
+#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ 6L
+#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0 3L
+#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4)
+#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0 2L
+#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8)
+#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1 3L
+#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5)
+#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1 2L
+#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9)
+#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2 3L
+#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6)
+#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2 2L
+#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3 3L
+#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7)
+#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3 2L
+#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0 2L
+#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16)
+#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0 3L
+#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0)
+#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1 2L
+#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17)
+#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1 3L
+#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1)
+#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2 3L
+#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2 2L
+#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3 3L
+#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3 2L
+#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0 3L
+#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8)
+#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1 3L
+#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9)
+#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2 3L
+#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2 2L
+#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3 3L
+#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3 2L
+#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0 3L
+#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0 2L
+#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1 3L
+#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1 2L
+#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2 3L
+#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18)
+#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2 2L
+#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3 3L
+#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19)
+#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3 2L
+#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0 4L
+#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0 (1ul << 4)
+#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0 4L
+#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0 (1ul << 8)
+#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1 4L
+#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1 (1ul << 5)
+#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1 4L
+#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1 (1ul << 9)
+#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2 5L
+#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2 (1ul << 10)
+#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2 5L
+#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2 (1ul << 18)
+#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3 5L
+#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3 (1ul << 11)
+#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3 5L
+#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3 (1ul << 19)
+#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4 5L
+#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4 (1ul << 14)
+#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4 5L
+#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4 (1ul << 22)
+#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5 5L
+#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5 (1ul << 15)
+#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5 5L
+#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5 (1ul << 23)
+#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6 5L
+#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6 (1ul << 16)
+#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7 5L
+#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7 (1ul << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0 4L
+#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0 (1ul << 6)
+#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0 4L
+#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0 (1ul << 10)
+#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0 4L
+#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0 (1ul << 30)
+#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1 4L
+#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1 (1ul << 7)
+#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1 4L
+#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1 (1ul << 11)
+#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1 4L
+#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1 (1ul << 31)
+#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2 5L
+#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2 (1ul << 8)
+#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2 5L
+#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2 (1ul << 24)
+#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3 5L
+#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3 (1ul << 9)
+#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3 5L
+#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3 (1ul << 25)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0 4L
+#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0 (1ul << 16)
+#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0 4L
+#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0 (1ul << 0)
+#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1 4L
+#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1 (1ul << 17)
+#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1 4L
+#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1 (1ul << 1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0 4L
+#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0 (1ul << 18)
+#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0 4L
+#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0 (1ul << 14)
+#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1 4L
+#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1 (1ul << 19)
+#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1 4L
+#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1 (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0 4L
+#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0 (1ul << 22)
+#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1 4L
+#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1 (1ul << 23)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0 4L
+#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0 (1ul << 24)
+#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1 4L
+#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1 (1ul << 25)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0 1L
+#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0 (1ul << 2)
+#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1 1L
+#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1 (1ul << 3)
+#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4 1L
+#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4 (1ul << 4)
+#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5 1L
+#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5 (1ul << 5)
+#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6 1L
+#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6 (1ul << 6)
+#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7 1L
+#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7 (1ul << 7)
+#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16 1L
+#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16 (1ul << 8)
+#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17 1L
+#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17 (1ul << 9)
+#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18 1L
+#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18 (1ul << 10)
+#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19 1L
+#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19 (1ul << 11)
+#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP 1L
+#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP (1ul << 4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0 1L
+#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0 (1ul << 4)
+#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1 1L
+#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1 (1ul << 5)
+#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2 1L
+#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2 (1ul << 6)
+#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3 1L
+#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3 (1ul << 7)
+#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0 7L
+#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0 (1ul << 18)
+#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1 7L
+#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1 (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT 1L
+#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT (1ul << 2)
+#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP 1L
+#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP (1ul << 3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0 11L /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0 6L
+#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0 (1ul << 11)
+#define PIN_PA09G_I2S_MCK0 9L /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0 6L
+#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0 (1ul << 9)
+#define PIN_PA10G_I2S_SCK0 10L /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0 6L
+#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0 (1ul << 10)
+#define PIN_PA07G_I2S_SD0 7L /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0 6L
+#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0 (1ul << 7)
+#define PIN_PA19G_I2S_SD0 19L /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0 6L
+#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0 (1ul << 19)
+#define PIN_PA08G_I2S_SD1 8L /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1 6L
+#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1 (1ul << 8)
+
+#endif /* _SAMD21E17A_PIO_ */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/pio/samd21e18a.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/pio/samd21e18a.h
new file mode 100644
index 0000000000000000000000000000000000000000..3053aa028c1fe6e2dc52cf96e42f9cf438bcea6c
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/pio/samd21e18a.h
@@ -0,0 +1,641 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21E18A
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21E18A_PIO_
+#define _SAMD21E18A_PIO_
+
+#define PIN_PA00 0 /**< \brief Pin Number for PA00 */
+#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */
+#define PIN_PA01 1 /**< \brief Pin Number for PA01 */
+#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */
+#define PIN_PA02 2 /**< \brief Pin Number for PA02 */
+#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */
+#define PIN_PA03 3 /**< \brief Pin Number for PA03 */
+#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */
+#define PIN_PA04 4 /**< \brief Pin Number for PA04 */
+#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */
+#define PIN_PA05 5 /**< \brief Pin Number for PA05 */
+#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */
+#define PIN_PA06 6 /**< \brief Pin Number for PA06 */
+#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */
+#define PIN_PA07 7 /**< \brief Pin Number for PA07 */
+#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */
+#define PIN_PA08 8 /**< \brief Pin Number for PA08 */
+#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */
+#define PIN_PA09 9 /**< \brief Pin Number for PA09 */
+#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */
+#define PIN_PA10 10 /**< \brief Pin Number for PA10 */
+#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */
+#define PIN_PA11 11 /**< \brief Pin Number for PA11 */
+#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */
+#define PIN_PA14 14 /**< \brief Pin Number for PA14 */
+#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */
+#define PIN_PA15 15 /**< \brief Pin Number for PA15 */
+#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */
+#define PIN_PA16 16 /**< \brief Pin Number for PA16 */
+#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */
+#define PIN_PA17 17 /**< \brief Pin Number for PA17 */
+#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */
+#define PIN_PA18 18 /**< \brief Pin Number for PA18 */
+#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */
+#define PIN_PA19 19 /**< \brief Pin Number for PA19 */
+#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */
+#define PIN_PA22 22 /**< \brief Pin Number for PA22 */
+#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */
+#define PIN_PA23 23 /**< \brief Pin Number for PA23 */
+#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */
+#define PIN_PA24 24 /**< \brief Pin Number for PA24 */
+#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */
+#define PIN_PA25 25 /**< \brief Pin Number for PA25 */
+#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */
+#define PIN_PA27 27 /**< \brief Pin Number for PA27 */
+#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */
+#define PIN_PA28 28 /**< \brief Pin Number for PA28 */
+#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */
+#define PIN_PA30 30 /**< \brief Pin Number for PA30 */
+#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */
+#define PIN_PA31 31 /**< \brief Pin Number for PA31 */
+#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0 7L
+#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0 (1ul << 14)
+#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0 7L
+#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0 (1ul << 27)
+#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0 7L
+#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0 (1ul << 28)
+#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0 7L
+#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0 (1ul << 30)
+#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1 7L
+#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1 (1ul << 15)
+#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2 7L
+#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2 (1ul << 16)
+#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3 7L
+#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3 (1ul << 17)
+#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4 7L
+#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4 (1ul << 10)
+#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5 7L
+#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5 (1ul << 11)
+#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6 7L
+#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6 (1ul << 22)
+#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7 7L
+#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7 (1ul << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0 0L
+#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0 (1ul << 16)
+#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0 0L
+#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0 (1ul << 0)
+#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1 0L
+#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1 (1ul << 17)
+#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1 0L
+#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1 (1ul << 1)
+#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2 0L
+#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2 (1ul << 18)
+#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2 0L
+#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2 (1ul << 2)
+#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3 0L
+#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3 (1ul << 3)
+#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3 0L
+#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3 (1ul << 19)
+#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4 0L
+#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4 (1ul << 4)
+#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5 0L
+#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5 (1ul << 5)
+#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6 0L
+#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6 (1ul << 6)
+#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6 0L
+#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6 (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7 0L
+#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7 (1ul << 7)
+#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7 0L
+#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7 (1ul << 23)
+#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8 0L
+#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8 (1ul << 28)
+#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9 0L
+#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9 (1ul << 9)
+#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10 0L
+#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10 (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10 0L
+#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10 (1ul << 30)
+#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11 0L
+#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11 (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11 0L
+#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11 (1ul << 31)
+#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12 0L
+#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12 (1ul << 24)
+#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13 0L
+#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13 (1ul << 25)
+#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14 0L
+#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14 (1ul << 14)
+#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15 0L
+#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15 (1ul << 15)
+#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15 0L
+#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15 (1ul << 27)
+#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI 0L
+#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI (1ul << 8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM 6L
+#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM (1ul << 24)
+#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP 6L
+#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP (1ul << 25)
+#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ 6L
+#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0 3L
+#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4)
+#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0 2L
+#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8)
+#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1 3L
+#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5)
+#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1 2L
+#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9)
+#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2 3L
+#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6)
+#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2 2L
+#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3 3L
+#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7)
+#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3 2L
+#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0 2L
+#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16)
+#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0 3L
+#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0)
+#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1 2L
+#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17)
+#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1 3L
+#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1)
+#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2 3L
+#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2 2L
+#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3 3L
+#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3 2L
+#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0 3L
+#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8)
+#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1 3L
+#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9)
+#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2 3L
+#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2 2L
+#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3 3L
+#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3 2L
+#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0 3L
+#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0 2L
+#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1 3L
+#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1 2L
+#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2 3L
+#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18)
+#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2 2L
+#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3 3L
+#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19)
+#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3 2L
+#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0 4L
+#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0 (1ul << 4)
+#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0 4L
+#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0 (1ul << 8)
+#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1 4L
+#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1 (1ul << 5)
+#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1 4L
+#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1 (1ul << 9)
+#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2 5L
+#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2 (1ul << 10)
+#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2 5L
+#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2 (1ul << 18)
+#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3 5L
+#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3 (1ul << 11)
+#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3 5L
+#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3 (1ul << 19)
+#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4 5L
+#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4 (1ul << 14)
+#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4 5L
+#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4 (1ul << 22)
+#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5 5L
+#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5 (1ul << 15)
+#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5 5L
+#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5 (1ul << 23)
+#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6 5L
+#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6 (1ul << 16)
+#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7 5L
+#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7 (1ul << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0 4L
+#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0 (1ul << 6)
+#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0 4L
+#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0 (1ul << 10)
+#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0 4L
+#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0 (1ul << 30)
+#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1 4L
+#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1 (1ul << 7)
+#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1 4L
+#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1 (1ul << 11)
+#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1 4L
+#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1 (1ul << 31)
+#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2 5L
+#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2 (1ul << 8)
+#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2 5L
+#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2 (1ul << 24)
+#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3 5L
+#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3 (1ul << 9)
+#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3 5L
+#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3 (1ul << 25)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0 4L
+#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0 (1ul << 16)
+#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0 4L
+#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0 (1ul << 0)
+#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1 4L
+#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1 (1ul << 17)
+#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1 4L
+#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1 (1ul << 1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0 4L
+#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0 (1ul << 18)
+#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0 4L
+#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0 (1ul << 14)
+#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1 4L
+#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1 (1ul << 19)
+#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1 4L
+#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1 (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0 4L
+#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0 (1ul << 22)
+#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1 4L
+#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1 (1ul << 23)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0 4L
+#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0 (1ul << 24)
+#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1 4L
+#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1 (1ul << 25)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0 1L
+#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0 (1ul << 2)
+#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1 1L
+#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1 (1ul << 3)
+#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4 1L
+#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4 (1ul << 4)
+#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5 1L
+#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5 (1ul << 5)
+#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6 1L
+#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6 (1ul << 6)
+#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7 1L
+#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7 (1ul << 7)
+#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16 1L
+#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16 (1ul << 8)
+#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17 1L
+#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17 (1ul << 9)
+#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18 1L
+#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18 (1ul << 10)
+#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19 1L
+#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19 (1ul << 11)
+#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP 1L
+#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP (1ul << 4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0 1L
+#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0 (1ul << 4)
+#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1 1L
+#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1 (1ul << 5)
+#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2 1L
+#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2 (1ul << 6)
+#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3 1L
+#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3 (1ul << 7)
+#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0 7L
+#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0 (1ul << 18)
+#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1 7L
+#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1 (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT 1L
+#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT (1ul << 2)
+#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP 1L
+#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP (1ul << 3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0 11L /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0 6L
+#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0 (1ul << 11)
+#define PIN_PA09G_I2S_MCK0 9L /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0 6L
+#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0 (1ul << 9)
+#define PIN_PA10G_I2S_SCK0 10L /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0 6L
+#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0 (1ul << 10)
+#define PIN_PA07G_I2S_SD0 7L /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0 6L
+#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0 (1ul << 7)
+#define PIN_PA19G_I2S_SD0 19L /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0 6L
+#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0 (1ul << 19)
+#define PIN_PA08G_I2S_SD1 8L /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1 6L
+#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1 (1ul << 8)
+
+#endif /* _SAMD21E18A_PIO_ */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/pio/samd21g15a.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/pio/samd21g15a.h
new file mode 100644
index 0000000000000000000000000000000000000000..bac5e82c009b3a4306549db44fe28f4c6684797d
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/pio/samd21g15a.h
@@ -0,0 +1,915 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21G15A
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21G15A_PIO_
+#define _SAMD21G15A_PIO_
+
+#define PIN_PA00 0 /**< \brief Pin Number for PA00 */
+#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */
+#define PIN_PA01 1 /**< \brief Pin Number for PA01 */
+#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */
+#define PIN_PA02 2 /**< \brief Pin Number for PA02 */
+#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */
+#define PIN_PA03 3 /**< \brief Pin Number for PA03 */
+#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */
+#define PIN_PA04 4 /**< \brief Pin Number for PA04 */
+#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */
+#define PIN_PA05 5 /**< \brief Pin Number for PA05 */
+#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */
+#define PIN_PA06 6 /**< \brief Pin Number for PA06 */
+#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */
+#define PIN_PA07 7 /**< \brief Pin Number for PA07 */
+#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */
+#define PIN_PA08 8 /**< \brief Pin Number for PA08 */
+#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */
+#define PIN_PA09 9 /**< \brief Pin Number for PA09 */
+#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */
+#define PIN_PA10 10 /**< \brief Pin Number for PA10 */
+#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */
+#define PIN_PA11 11 /**< \brief Pin Number for PA11 */
+#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */
+#define PIN_PA12 12 /**< \brief Pin Number for PA12 */
+#define PORT_PA12 (1ul << 12) /**< \brief PORT Mask for PA12 */
+#define PIN_PA13 13 /**< \brief Pin Number for PA13 */
+#define PORT_PA13 (1ul << 13) /**< \brief PORT Mask for PA13 */
+#define PIN_PA14 14 /**< \brief Pin Number for PA14 */
+#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */
+#define PIN_PA15 15 /**< \brief Pin Number for PA15 */
+#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */
+#define PIN_PA16 16 /**< \brief Pin Number for PA16 */
+#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */
+#define PIN_PA17 17 /**< \brief Pin Number for PA17 */
+#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */
+#define PIN_PA18 18 /**< \brief Pin Number for PA18 */
+#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */
+#define PIN_PA19 19 /**< \brief Pin Number for PA19 */
+#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */
+#define PIN_PA20 20 /**< \brief Pin Number for PA20 */
+#define PORT_PA20 (1ul << 20) /**< \brief PORT Mask for PA20 */
+#define PIN_PA21 21 /**< \brief Pin Number for PA21 */
+#define PORT_PA21 (1ul << 21) /**< \brief PORT Mask for PA21 */
+#define PIN_PA22 22 /**< \brief Pin Number for PA22 */
+#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */
+#define PIN_PA23 23 /**< \brief Pin Number for PA23 */
+#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */
+#define PIN_PA24 24 /**< \brief Pin Number for PA24 */
+#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */
+#define PIN_PA25 25 /**< \brief Pin Number for PA25 */
+#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */
+#define PIN_PA27 27 /**< \brief Pin Number for PA27 */
+#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */
+#define PIN_PA28 28 /**< \brief Pin Number for PA28 */
+#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */
+#define PIN_PA30 30 /**< \brief Pin Number for PA30 */
+#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */
+#define PIN_PA31 31 /**< \brief Pin Number for PA31 */
+#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */
+#define PIN_PB02 34 /**< \brief Pin Number for PB02 */
+#define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */
+#define PIN_PB03 35 /**< \brief Pin Number for PB03 */
+#define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */
+#define PIN_PB08 40 /**< \brief Pin Number for PB08 */
+#define PORT_PB08 (1ul << 8) /**< \brief PORT Mask for PB08 */
+#define PIN_PB09 41 /**< \brief Pin Number for PB09 */
+#define PORT_PB09 (1ul << 9) /**< \brief PORT Mask for PB09 */
+#define PIN_PB10 42 /**< \brief Pin Number for PB10 */
+#define PORT_PB10 (1ul << 10) /**< \brief PORT Mask for PB10 */
+#define PIN_PB11 43 /**< \brief Pin Number for PB11 */
+#define PORT_PB11 (1ul << 11) /**< \brief PORT Mask for PB11 */
+#define PIN_PB22 54 /**< \brief Pin Number for PB22 */
+#define PORT_PB22 (1ul << 22) /**< \brief PORT Mask for PB22 */
+#define PIN_PB23 55 /**< \brief Pin Number for PB23 */
+#define PORT_PB23 (1ul << 23) /**< \brief PORT Mask for PB23 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PB22H_GCLK_IO0 54L /**< \brief GCLK signal: IO0 on PB22 mux H */
+#define MUX_PB22H_GCLK_IO0 7L
+#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
+#define PORT_PB22H_GCLK_IO0 (1ul << 22)
+#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0 7L
+#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0 (1ul << 14)
+#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0 7L
+#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0 (1ul << 27)
+#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0 7L
+#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0 (1ul << 28)
+#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0 7L
+#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0 (1ul << 30)
+#define PIN_PB23H_GCLK_IO1 55L /**< \brief GCLK signal: IO1 on PB23 mux H */
+#define MUX_PB23H_GCLK_IO1 7L
+#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
+#define PORT_PB23H_GCLK_IO1 (1ul << 23)
+#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1 7L
+#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1 (1ul << 15)
+#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2 7L
+#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2 (1ul << 16)
+#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3 7L
+#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3 (1ul << 17)
+#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4 7L
+#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4 (1ul << 10)
+#define PIN_PA20H_GCLK_IO4 20L /**< \brief GCLK signal: IO4 on PA20 mux H */
+#define MUX_PA20H_GCLK_IO4 7L
+#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
+#define PORT_PA20H_GCLK_IO4 (1ul << 20)
+#define PIN_PB10H_GCLK_IO4 42L /**< \brief GCLK signal: IO4 on PB10 mux H */
+#define MUX_PB10H_GCLK_IO4 7L
+#define PINMUX_PB10H_GCLK_IO4 ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
+#define PORT_PB10H_GCLK_IO4 (1ul << 10)
+#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5 7L
+#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5 (1ul << 11)
+#define PIN_PA21H_GCLK_IO5 21L /**< \brief GCLK signal: IO5 on PA21 mux H */
+#define MUX_PA21H_GCLK_IO5 7L
+#define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
+#define PORT_PA21H_GCLK_IO5 (1ul << 21)
+#define PIN_PB11H_GCLK_IO5 43L /**< \brief GCLK signal: IO5 on PB11 mux H */
+#define MUX_PB11H_GCLK_IO5 7L
+#define PINMUX_PB11H_GCLK_IO5 ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
+#define PORT_PB11H_GCLK_IO5 (1ul << 11)
+#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6 7L
+#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6 (1ul << 22)
+#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7 7L
+#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7 (1ul << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0 0L
+#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0 (1ul << 16)
+#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0 0L
+#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0 (1ul << 0)
+#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1 0L
+#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1 (1ul << 17)
+#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1 0L
+#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1 (1ul << 1)
+#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2 0L
+#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2 (1ul << 18)
+#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2 0L
+#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2 (1ul << 2)
+#define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2 0L
+#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2 (1ul << 2)
+#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3 0L
+#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3 (1ul << 3)
+#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3 0L
+#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3 (1ul << 19)
+#define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3 0L
+#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3 (1ul << 3)
+#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4 0L
+#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4 (1ul << 4)
+#define PIN_PA20A_EIC_EXTINT4 20L /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4 0L
+#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4 (1ul << 20)
+#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5 0L
+#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5 (1ul << 5)
+#define PIN_PA21A_EIC_EXTINT5 21L /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5 0L
+#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5 (1ul << 21)
+#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6 0L
+#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6 (1ul << 6)
+#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6 0L
+#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6 (1ul << 22)
+#define PIN_PB22A_EIC_EXTINT6 54L /**< \brief EIC signal: EXTINT6 on PB22 mux A */
+#define MUX_PB22A_EIC_EXTINT6 0L
+#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
+#define PORT_PB22A_EIC_EXTINT6 (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7 0L
+#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7 (1ul << 7)
+#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7 0L
+#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7 (1ul << 23)
+#define PIN_PB23A_EIC_EXTINT7 55L /**< \brief EIC signal: EXTINT7 on PB23 mux A */
+#define MUX_PB23A_EIC_EXTINT7 0L
+#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
+#define PORT_PB23A_EIC_EXTINT7 (1ul << 23)
+#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8 0L
+#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8 (1ul << 28)
+#define PIN_PB08A_EIC_EXTINT8 40L /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8 0L
+#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8 (1ul << 8)
+#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9 0L
+#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9 (1ul << 9)
+#define PIN_PB09A_EIC_EXTINT9 41L /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9 0L
+#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9 (1ul << 9)
+#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10 0L
+#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10 (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10 0L
+#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10 (1ul << 30)
+#define PIN_PB10A_EIC_EXTINT10 42L /**< \brief EIC signal: EXTINT10 on PB10 mux A */
+#define MUX_PB10A_EIC_EXTINT10 0L
+#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
+#define PORT_PB10A_EIC_EXTINT10 (1ul << 10)
+#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11 0L
+#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11 (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11 0L
+#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11 (1ul << 31)
+#define PIN_PB11A_EIC_EXTINT11 43L /**< \brief EIC signal: EXTINT11 on PB11 mux A */
+#define MUX_PB11A_EIC_EXTINT11 0L
+#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
+#define PORT_PB11A_EIC_EXTINT11 (1ul << 11)
+#define PIN_PA12A_EIC_EXTINT12 12L /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12 0L
+#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12 (1ul << 12)
+#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12 0L
+#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12 (1ul << 24)
+#define PIN_PA13A_EIC_EXTINT13 13L /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13 0L
+#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13 (1ul << 13)
+#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13 0L
+#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13 (1ul << 25)
+#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14 0L
+#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14 (1ul << 14)
+#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15 0L
+#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15 (1ul << 15)
+#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15 0L
+#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15 (1ul << 27)
+#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI 0L
+#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI (1ul << 8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM 6L
+#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM (1ul << 24)
+#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP 6L
+#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP (1ul << 25)
+#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ 6L
+#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0 3L
+#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4)
+#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0 2L
+#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8)
+#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1 3L
+#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5)
+#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1 2L
+#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9)
+#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2 3L
+#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6)
+#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2 2L
+#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3 3L
+#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7)
+#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3 2L
+#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0 2L
+#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16)
+#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0 3L
+#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0)
+#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1 2L
+#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17)
+#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1 3L
+#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1)
+#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2 3L
+#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2 2L
+#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3 3L
+#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3 2L
+#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0 3L
+#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8)
+#define PIN_PA12C_SERCOM2_PAD0 12L /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0 2L
+#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0 (1ul << 12)
+#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1 3L
+#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9)
+#define PIN_PA13C_SERCOM2_PAD1 13L /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1 2L
+#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1 (1ul << 13)
+#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2 3L
+#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2 2L
+#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3 3L
+#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3 2L
+#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0 3L
+#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0 2L
+#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1 3L
+#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1 2L
+#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2 3L
+#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18)
+#define PIN_PA20D_SERCOM3_PAD2 20L /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2 3L
+#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2 (1ul << 20)
+#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2 2L
+#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3 3L
+#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19)
+#define PIN_PA21D_SERCOM3_PAD3 21L /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3 3L
+#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3 (1ul << 21)
+#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3 2L
+#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA12D_SERCOM4_PAD0 12L /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD0 3L
+#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
+#define PORT_PA12D_SERCOM4_PAD0 (1ul << 12)
+#define PIN_PB08D_SERCOM4_PAD0 40L /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0 3L
+#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0 (1ul << 8)
+#define PIN_PA13D_SERCOM4_PAD1 13L /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD1 3L
+#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
+#define PORT_PA13D_SERCOM4_PAD1 (1ul << 13)
+#define PIN_PB09D_SERCOM4_PAD1 41L /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1 3L
+#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1 (1ul << 9)
+#define PIN_PA14D_SERCOM4_PAD2 14L /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2 3L
+#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2 (1ul << 14)
+#define PIN_PB10D_SERCOM4_PAD2 42L /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
+#define MUX_PB10D_SERCOM4_PAD2 3L
+#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
+#define PORT_PB10D_SERCOM4_PAD2 (1ul << 10)
+#define PIN_PA15D_SERCOM4_PAD3 15L /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3 3L
+#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3 (1ul << 15)
+#define PIN_PB11D_SERCOM4_PAD3 43L /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
+#define MUX_PB11D_SERCOM4_PAD3 3L
+#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
+#define PORT_PB11D_SERCOM4_PAD3 (1ul << 11)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PA22D_SERCOM5_PAD0 22L /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD0 3L
+#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
+#define PORT_PA22D_SERCOM5_PAD0 (1ul << 22)
+#define PIN_PB02D_SERCOM5_PAD0 34L /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0 3L
+#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0 (1ul << 2)
+#define PIN_PA23D_SERCOM5_PAD1 23L /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD1 3L
+#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
+#define PORT_PA23D_SERCOM5_PAD1 (1ul << 23)
+#define PIN_PB03D_SERCOM5_PAD1 35L /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1 3L
+#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1 (1ul << 3)
+#define PIN_PA24D_SERCOM5_PAD2 24L /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2 3L
+#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2 (1ul << 24)
+#define PIN_PB22D_SERCOM5_PAD2 54L /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
+#define MUX_PB22D_SERCOM5_PAD2 3L
+#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
+#define PORT_PB22D_SERCOM5_PAD2 (1ul << 22)
+#define PIN_PA20C_SERCOM5_PAD2 20L /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2 2L
+#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2 (1ul << 20)
+#define PIN_PA25D_SERCOM5_PAD3 25L /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3 3L
+#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3 (1ul << 25)
+#define PIN_PB23D_SERCOM5_PAD3 55L /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
+#define MUX_PB23D_SERCOM5_PAD3 3L
+#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
+#define PORT_PB23D_SERCOM5_PAD3 (1ul << 23)
+#define PIN_PA21C_SERCOM5_PAD3 21L /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3 2L
+#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3 (1ul << 21)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0 4L
+#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0 (1ul << 4)
+#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0 4L
+#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0 (1ul << 8)
+#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1 4L
+#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1 (1ul << 5)
+#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1 4L
+#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1 (1ul << 9)
+#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2 5L
+#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2 (1ul << 10)
+#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2 5L
+#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2 (1ul << 18)
+#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3 5L
+#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3 (1ul << 11)
+#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3 5L
+#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3 (1ul << 19)
+#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4 5L
+#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4 (1ul << 14)
+#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4 5L
+#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4 (1ul << 22)
+#define PIN_PB10F_TCC0_WO4 42L /**< \brief TCC0 signal: WO4 on PB10 mux F */
+#define MUX_PB10F_TCC0_WO4 5L
+#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
+#define PORT_PB10F_TCC0_WO4 (1ul << 10)
+#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5 5L
+#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5 (1ul << 15)
+#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5 5L
+#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5 (1ul << 23)
+#define PIN_PB11F_TCC0_WO5 43L /**< \brief TCC0 signal: WO5 on PB11 mux F */
+#define MUX_PB11F_TCC0_WO5 5L
+#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
+#define PORT_PB11F_TCC0_WO5 (1ul << 11)
+#define PIN_PA12F_TCC0_WO6 12L /**< \brief TCC0 signal: WO6 on PA12 mux F */
+#define MUX_PA12F_TCC0_WO6 5L
+#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
+#define PORT_PA12F_TCC0_WO6 (1ul << 12)
+#define PIN_PA20F_TCC0_WO6 20L /**< \brief TCC0 signal: WO6 on PA20 mux F */
+#define MUX_PA20F_TCC0_WO6 5L
+#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
+#define PORT_PA20F_TCC0_WO6 (1ul << 20)
+#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6 5L
+#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6 (1ul << 16)
+#define PIN_PA13F_TCC0_WO7 13L /**< \brief TCC0 signal: WO7 on PA13 mux F */
+#define MUX_PA13F_TCC0_WO7 5L
+#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
+#define PORT_PA13F_TCC0_WO7 (1ul << 13)
+#define PIN_PA21F_TCC0_WO7 21L /**< \brief TCC0 signal: WO7 on PA21 mux F */
+#define MUX_PA21F_TCC0_WO7 5L
+#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
+#define PORT_PA21F_TCC0_WO7 (1ul << 21)
+#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7 5L
+#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7 (1ul << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0 4L
+#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0 (1ul << 6)
+#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0 4L
+#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0 (1ul << 10)
+#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0 4L
+#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0 (1ul << 30)
+#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1 4L
+#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1 (1ul << 7)
+#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1 4L
+#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1 (1ul << 11)
+#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1 4L
+#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1 (1ul << 31)
+#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2 5L
+#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2 (1ul << 8)
+#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2 5L
+#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2 (1ul << 24)
+#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3 5L
+#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3 (1ul << 9)
+#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3 5L
+#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3 (1ul << 25)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA12E_TCC2_WO0 12L /**< \brief TCC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TCC2_WO0 4L
+#define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
+#define PORT_PA12E_TCC2_WO0 (1ul << 12)
+#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0 4L
+#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0 (1ul << 16)
+#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0 4L
+#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0 (1ul << 0)
+#define PIN_PA13E_TCC2_WO1 13L /**< \brief TCC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TCC2_WO1 4L
+#define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
+#define PORT_PA13E_TCC2_WO1 (1ul << 13)
+#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1 4L
+#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1 (1ul << 17)
+#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1 4L
+#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1 (1ul << 1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0 4L
+#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0 (1ul << 18)
+#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0 4L
+#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0 (1ul << 14)
+#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1 4L
+#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1 (1ul << 19)
+#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1 4L
+#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1 (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0 4L
+#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0 (1ul << 22)
+#define PIN_PB08E_TC4_WO0 40L /**< \brief TC4 signal: WO0 on PB08 mux E */
+#define MUX_PB08E_TC4_WO0 4L
+#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
+#define PORT_PB08E_TC4_WO0 (1ul << 8)
+#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1 4L
+#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1 (1ul << 23)
+#define PIN_PB09E_TC4_WO1 41L /**< \brief TC4 signal: WO1 on PB09 mux E */
+#define MUX_PB09E_TC4_WO1 4L
+#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
+#define PORT_PB09E_TC4_WO1 (1ul << 9)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0 4L
+#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0 (1ul << 24)
+#define PIN_PB10E_TC5_WO0 42L /**< \brief TC5 signal: WO0 on PB10 mux E */
+#define MUX_PB10E_TC5_WO0 4L
+#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
+#define PORT_PB10E_TC5_WO0 (1ul << 10)
+#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1 4L
+#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1 (1ul << 25)
+#define PIN_PB11E_TC5_WO1 43L /**< \brief TC5 signal: WO1 on PB11 mux E */
+#define MUX_PB11E_TC5_WO1 4L
+#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
+#define PORT_PB11E_TC5_WO1 (1ul << 11)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0 1L
+#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0 (1ul << 2)
+#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1 1L
+#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1 (1ul << 3)
+#define PIN_PB08B_ADC_AIN2 40L /**< \brief ADC signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC_AIN2 1L
+#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
+#define PORT_PB08B_ADC_AIN2 (1ul << 8)
+#define PIN_PB09B_ADC_AIN3 41L /**< \brief ADC signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC_AIN3 1L
+#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
+#define PORT_PB09B_ADC_AIN3 (1ul << 9)
+#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4 1L
+#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4 (1ul << 4)
+#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5 1L
+#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5 (1ul << 5)
+#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6 1L
+#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6 (1ul << 6)
+#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7 1L
+#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7 (1ul << 7)
+#define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */
+#define MUX_PB02B_ADC_AIN10 1L
+#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
+#define PORT_PB02B_ADC_AIN10 (1ul << 2)
+#define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */
+#define MUX_PB03B_ADC_AIN11 1L
+#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
+#define PORT_PB03B_ADC_AIN11 (1ul << 3)
+#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16 1L
+#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16 (1ul << 8)
+#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17 1L
+#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17 (1ul << 9)
+#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18 1L
+#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18 (1ul << 10)
+#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19 1L
+#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19 (1ul << 11)
+#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP 1L
+#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP (1ul << 4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0 1L
+#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0 (1ul << 4)
+#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1 1L
+#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1 (1ul << 5)
+#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2 1L
+#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2 (1ul << 6)
+#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3 1L
+#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3 (1ul << 7)
+#define PIN_PA12H_AC_CMP0 12L /**< \brief AC signal: CMP0 on PA12 mux H */
+#define MUX_PA12H_AC_CMP0 7L
+#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
+#define PORT_PA12H_AC_CMP0 (1ul << 12)
+#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0 7L
+#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0 (1ul << 18)
+#define PIN_PA13H_AC_CMP1 13L /**< \brief AC signal: CMP1 on PA13 mux H */
+#define MUX_PA13H_AC_CMP1 7L
+#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
+#define PORT_PA13H_AC_CMP1 (1ul << 13)
+#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1 7L
+#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1 (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT 1L
+#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT (1ul << 2)
+#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP 1L
+#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP (1ul << 3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0 11L /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0 6L
+#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0 (1ul << 11)
+#define PIN_PA21G_I2S_FS0 21L /**< \brief I2S signal: FS0 on PA21 mux G */
+#define MUX_PA21G_I2S_FS0 6L
+#define PINMUX_PA21G_I2S_FS0 ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
+#define PORT_PA21G_I2S_FS0 (1ul << 21)
+#define PIN_PA09G_I2S_MCK0 9L /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0 6L
+#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0 (1ul << 9)
+#define PIN_PB10G_I2S_MCK1 42L /**< \brief I2S signal: MCK1 on PB10 mux G */
+#define MUX_PB10G_I2S_MCK1 6L
+#define PINMUX_PB10G_I2S_MCK1 ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1)
+#define PORT_PB10G_I2S_MCK1 (1ul << 10)
+#define PIN_PA10G_I2S_SCK0 10L /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0 6L
+#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0 (1ul << 10)
+#define PIN_PA20G_I2S_SCK0 20L /**< \brief I2S signal: SCK0 on PA20 mux G */
+#define MUX_PA20G_I2S_SCK0 6L
+#define PINMUX_PA20G_I2S_SCK0 ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
+#define PORT_PA20G_I2S_SCK0 (1ul << 20)
+#define PIN_PB11G_I2S_SCK1 43L /**< \brief I2S signal: SCK1 on PB11 mux G */
+#define MUX_PB11G_I2S_SCK1 6L
+#define PINMUX_PB11G_I2S_SCK1 ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1)
+#define PORT_PB11G_I2S_SCK1 (1ul << 11)
+#define PIN_PA07G_I2S_SD0 7L /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0 6L
+#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0 (1ul << 7)
+#define PIN_PA19G_I2S_SD0 19L /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0 6L
+#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0 (1ul << 19)
+#define PIN_PA08G_I2S_SD1 8L /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1 6L
+#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1 (1ul << 8)
+
+#endif /* _SAMD21G15A_PIO_ */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/pio/samd21g16a.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/pio/samd21g16a.h
new file mode 100644
index 0000000000000000000000000000000000000000..09f2f0ef894577224d9d3d39c5af54abcc2bd091
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/pio/samd21g16a.h
@@ -0,0 +1,915 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21G16A
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21G16A_PIO_
+#define _SAMD21G16A_PIO_
+
+#define PIN_PA00 0 /**< \brief Pin Number for PA00 */
+#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */
+#define PIN_PA01 1 /**< \brief Pin Number for PA01 */
+#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */
+#define PIN_PA02 2 /**< \brief Pin Number for PA02 */
+#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */
+#define PIN_PA03 3 /**< \brief Pin Number for PA03 */
+#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */
+#define PIN_PA04 4 /**< \brief Pin Number for PA04 */
+#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */
+#define PIN_PA05 5 /**< \brief Pin Number for PA05 */
+#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */
+#define PIN_PA06 6 /**< \brief Pin Number for PA06 */
+#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */
+#define PIN_PA07 7 /**< \brief Pin Number for PA07 */
+#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */
+#define PIN_PA08 8 /**< \brief Pin Number for PA08 */
+#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */
+#define PIN_PA09 9 /**< \brief Pin Number for PA09 */
+#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */
+#define PIN_PA10 10 /**< \brief Pin Number for PA10 */
+#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */
+#define PIN_PA11 11 /**< \brief Pin Number for PA11 */
+#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */
+#define PIN_PA12 12 /**< \brief Pin Number for PA12 */
+#define PORT_PA12 (1ul << 12) /**< \brief PORT Mask for PA12 */
+#define PIN_PA13 13 /**< \brief Pin Number for PA13 */
+#define PORT_PA13 (1ul << 13) /**< \brief PORT Mask for PA13 */
+#define PIN_PA14 14 /**< \brief Pin Number for PA14 */
+#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */
+#define PIN_PA15 15 /**< \brief Pin Number for PA15 */
+#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */
+#define PIN_PA16 16 /**< \brief Pin Number for PA16 */
+#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */
+#define PIN_PA17 17 /**< \brief Pin Number for PA17 */
+#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */
+#define PIN_PA18 18 /**< \brief Pin Number for PA18 */
+#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */
+#define PIN_PA19 19 /**< \brief Pin Number for PA19 */
+#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */
+#define PIN_PA20 20 /**< \brief Pin Number for PA20 */
+#define PORT_PA20 (1ul << 20) /**< \brief PORT Mask for PA20 */
+#define PIN_PA21 21 /**< \brief Pin Number for PA21 */
+#define PORT_PA21 (1ul << 21) /**< \brief PORT Mask for PA21 */
+#define PIN_PA22 22 /**< \brief Pin Number for PA22 */
+#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */
+#define PIN_PA23 23 /**< \brief Pin Number for PA23 */
+#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */
+#define PIN_PA24 24 /**< \brief Pin Number for PA24 */
+#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */
+#define PIN_PA25 25 /**< \brief Pin Number for PA25 */
+#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */
+#define PIN_PA27 27 /**< \brief Pin Number for PA27 */
+#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */
+#define PIN_PA28 28 /**< \brief Pin Number for PA28 */
+#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */
+#define PIN_PA30 30 /**< \brief Pin Number for PA30 */
+#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */
+#define PIN_PA31 31 /**< \brief Pin Number for PA31 */
+#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */
+#define PIN_PB02 34 /**< \brief Pin Number for PB02 */
+#define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */
+#define PIN_PB03 35 /**< \brief Pin Number for PB03 */
+#define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */
+#define PIN_PB08 40 /**< \brief Pin Number for PB08 */
+#define PORT_PB08 (1ul << 8) /**< \brief PORT Mask for PB08 */
+#define PIN_PB09 41 /**< \brief Pin Number for PB09 */
+#define PORT_PB09 (1ul << 9) /**< \brief PORT Mask for PB09 */
+#define PIN_PB10 42 /**< \brief Pin Number for PB10 */
+#define PORT_PB10 (1ul << 10) /**< \brief PORT Mask for PB10 */
+#define PIN_PB11 43 /**< \brief Pin Number for PB11 */
+#define PORT_PB11 (1ul << 11) /**< \brief PORT Mask for PB11 */
+#define PIN_PB22 54 /**< \brief Pin Number for PB22 */
+#define PORT_PB22 (1ul << 22) /**< \brief PORT Mask for PB22 */
+#define PIN_PB23 55 /**< \brief Pin Number for PB23 */
+#define PORT_PB23 (1ul << 23) /**< \brief PORT Mask for PB23 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PB22H_GCLK_IO0 54L /**< \brief GCLK signal: IO0 on PB22 mux H */
+#define MUX_PB22H_GCLK_IO0 7L
+#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
+#define PORT_PB22H_GCLK_IO0 (1ul << 22)
+#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0 7L
+#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0 (1ul << 14)
+#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0 7L
+#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0 (1ul << 27)
+#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0 7L
+#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0 (1ul << 28)
+#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0 7L
+#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0 (1ul << 30)
+#define PIN_PB23H_GCLK_IO1 55L /**< \brief GCLK signal: IO1 on PB23 mux H */
+#define MUX_PB23H_GCLK_IO1 7L
+#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
+#define PORT_PB23H_GCLK_IO1 (1ul << 23)
+#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1 7L
+#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1 (1ul << 15)
+#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2 7L
+#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2 (1ul << 16)
+#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3 7L
+#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3 (1ul << 17)
+#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4 7L
+#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4 (1ul << 10)
+#define PIN_PA20H_GCLK_IO4 20L /**< \brief GCLK signal: IO4 on PA20 mux H */
+#define MUX_PA20H_GCLK_IO4 7L
+#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
+#define PORT_PA20H_GCLK_IO4 (1ul << 20)
+#define PIN_PB10H_GCLK_IO4 42L /**< \brief GCLK signal: IO4 on PB10 mux H */
+#define MUX_PB10H_GCLK_IO4 7L
+#define PINMUX_PB10H_GCLK_IO4 ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
+#define PORT_PB10H_GCLK_IO4 (1ul << 10)
+#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5 7L
+#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5 (1ul << 11)
+#define PIN_PA21H_GCLK_IO5 21L /**< \brief GCLK signal: IO5 on PA21 mux H */
+#define MUX_PA21H_GCLK_IO5 7L
+#define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
+#define PORT_PA21H_GCLK_IO5 (1ul << 21)
+#define PIN_PB11H_GCLK_IO5 43L /**< \brief GCLK signal: IO5 on PB11 mux H */
+#define MUX_PB11H_GCLK_IO5 7L
+#define PINMUX_PB11H_GCLK_IO5 ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
+#define PORT_PB11H_GCLK_IO5 (1ul << 11)
+#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6 7L
+#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6 (1ul << 22)
+#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7 7L
+#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7 (1ul << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0 0L
+#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0 (1ul << 16)
+#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0 0L
+#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0 (1ul << 0)
+#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1 0L
+#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1 (1ul << 17)
+#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1 0L
+#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1 (1ul << 1)
+#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2 0L
+#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2 (1ul << 18)
+#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2 0L
+#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2 (1ul << 2)
+#define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2 0L
+#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2 (1ul << 2)
+#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3 0L
+#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3 (1ul << 3)
+#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3 0L
+#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3 (1ul << 19)
+#define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3 0L
+#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3 (1ul << 3)
+#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4 0L
+#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4 (1ul << 4)
+#define PIN_PA20A_EIC_EXTINT4 20L /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4 0L
+#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4 (1ul << 20)
+#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5 0L
+#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5 (1ul << 5)
+#define PIN_PA21A_EIC_EXTINT5 21L /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5 0L
+#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5 (1ul << 21)
+#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6 0L
+#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6 (1ul << 6)
+#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6 0L
+#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6 (1ul << 22)
+#define PIN_PB22A_EIC_EXTINT6 54L /**< \brief EIC signal: EXTINT6 on PB22 mux A */
+#define MUX_PB22A_EIC_EXTINT6 0L
+#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
+#define PORT_PB22A_EIC_EXTINT6 (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7 0L
+#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7 (1ul << 7)
+#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7 0L
+#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7 (1ul << 23)
+#define PIN_PB23A_EIC_EXTINT7 55L /**< \brief EIC signal: EXTINT7 on PB23 mux A */
+#define MUX_PB23A_EIC_EXTINT7 0L
+#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
+#define PORT_PB23A_EIC_EXTINT7 (1ul << 23)
+#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8 0L
+#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8 (1ul << 28)
+#define PIN_PB08A_EIC_EXTINT8 40L /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8 0L
+#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8 (1ul << 8)
+#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9 0L
+#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9 (1ul << 9)
+#define PIN_PB09A_EIC_EXTINT9 41L /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9 0L
+#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9 (1ul << 9)
+#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10 0L
+#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10 (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10 0L
+#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10 (1ul << 30)
+#define PIN_PB10A_EIC_EXTINT10 42L /**< \brief EIC signal: EXTINT10 on PB10 mux A */
+#define MUX_PB10A_EIC_EXTINT10 0L
+#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
+#define PORT_PB10A_EIC_EXTINT10 (1ul << 10)
+#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11 0L
+#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11 (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11 0L
+#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11 (1ul << 31)
+#define PIN_PB11A_EIC_EXTINT11 43L /**< \brief EIC signal: EXTINT11 on PB11 mux A */
+#define MUX_PB11A_EIC_EXTINT11 0L
+#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
+#define PORT_PB11A_EIC_EXTINT11 (1ul << 11)
+#define PIN_PA12A_EIC_EXTINT12 12L /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12 0L
+#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12 (1ul << 12)
+#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12 0L
+#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12 (1ul << 24)
+#define PIN_PA13A_EIC_EXTINT13 13L /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13 0L
+#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13 (1ul << 13)
+#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13 0L
+#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13 (1ul << 25)
+#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14 0L
+#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14 (1ul << 14)
+#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15 0L
+#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15 (1ul << 15)
+#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15 0L
+#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15 (1ul << 27)
+#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI 0L
+#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI (1ul << 8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM 6L
+#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM (1ul << 24)
+#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP 6L
+#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP (1ul << 25)
+#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ 6L
+#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0 3L
+#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4)
+#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0 2L
+#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8)
+#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1 3L
+#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5)
+#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1 2L
+#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9)
+#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2 3L
+#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6)
+#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2 2L
+#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3 3L
+#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7)
+#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3 2L
+#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0 2L
+#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16)
+#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0 3L
+#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0)
+#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1 2L
+#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17)
+#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1 3L
+#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1)
+#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2 3L
+#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2 2L
+#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3 3L
+#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3 2L
+#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0 3L
+#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8)
+#define PIN_PA12C_SERCOM2_PAD0 12L /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0 2L
+#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0 (1ul << 12)
+#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1 3L
+#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9)
+#define PIN_PA13C_SERCOM2_PAD1 13L /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1 2L
+#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1 (1ul << 13)
+#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2 3L
+#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2 2L
+#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3 3L
+#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3 2L
+#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0 3L
+#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0 2L
+#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1 3L
+#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1 2L
+#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2 3L
+#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18)
+#define PIN_PA20D_SERCOM3_PAD2 20L /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2 3L
+#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2 (1ul << 20)
+#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2 2L
+#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3 3L
+#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19)
+#define PIN_PA21D_SERCOM3_PAD3 21L /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3 3L
+#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3 (1ul << 21)
+#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3 2L
+#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA12D_SERCOM4_PAD0 12L /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD0 3L
+#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
+#define PORT_PA12D_SERCOM4_PAD0 (1ul << 12)
+#define PIN_PB08D_SERCOM4_PAD0 40L /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0 3L
+#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0 (1ul << 8)
+#define PIN_PA13D_SERCOM4_PAD1 13L /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD1 3L
+#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
+#define PORT_PA13D_SERCOM4_PAD1 (1ul << 13)
+#define PIN_PB09D_SERCOM4_PAD1 41L /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1 3L
+#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1 (1ul << 9)
+#define PIN_PA14D_SERCOM4_PAD2 14L /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2 3L
+#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2 (1ul << 14)
+#define PIN_PB10D_SERCOM4_PAD2 42L /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
+#define MUX_PB10D_SERCOM4_PAD2 3L
+#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
+#define PORT_PB10D_SERCOM4_PAD2 (1ul << 10)
+#define PIN_PA15D_SERCOM4_PAD3 15L /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3 3L
+#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3 (1ul << 15)
+#define PIN_PB11D_SERCOM4_PAD3 43L /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
+#define MUX_PB11D_SERCOM4_PAD3 3L
+#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
+#define PORT_PB11D_SERCOM4_PAD3 (1ul << 11)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PA22D_SERCOM5_PAD0 22L /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD0 3L
+#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
+#define PORT_PA22D_SERCOM5_PAD0 (1ul << 22)
+#define PIN_PB02D_SERCOM5_PAD0 34L /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0 3L
+#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0 (1ul << 2)
+#define PIN_PA23D_SERCOM5_PAD1 23L /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD1 3L
+#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
+#define PORT_PA23D_SERCOM5_PAD1 (1ul << 23)
+#define PIN_PB03D_SERCOM5_PAD1 35L /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1 3L
+#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1 (1ul << 3)
+#define PIN_PA24D_SERCOM5_PAD2 24L /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2 3L
+#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2 (1ul << 24)
+#define PIN_PB22D_SERCOM5_PAD2 54L /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
+#define MUX_PB22D_SERCOM5_PAD2 3L
+#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
+#define PORT_PB22D_SERCOM5_PAD2 (1ul << 22)
+#define PIN_PA20C_SERCOM5_PAD2 20L /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2 2L
+#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2 (1ul << 20)
+#define PIN_PA25D_SERCOM5_PAD3 25L /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3 3L
+#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3 (1ul << 25)
+#define PIN_PB23D_SERCOM5_PAD3 55L /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
+#define MUX_PB23D_SERCOM5_PAD3 3L
+#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
+#define PORT_PB23D_SERCOM5_PAD3 (1ul << 23)
+#define PIN_PA21C_SERCOM5_PAD3 21L /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3 2L
+#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3 (1ul << 21)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0 4L
+#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0 (1ul << 4)
+#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0 4L
+#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0 (1ul << 8)
+#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1 4L
+#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1 (1ul << 5)
+#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1 4L
+#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1 (1ul << 9)
+#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2 5L
+#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2 (1ul << 10)
+#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2 5L
+#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2 (1ul << 18)
+#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3 5L
+#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3 (1ul << 11)
+#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3 5L
+#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3 (1ul << 19)
+#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4 5L
+#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4 (1ul << 14)
+#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4 5L
+#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4 (1ul << 22)
+#define PIN_PB10F_TCC0_WO4 42L /**< \brief TCC0 signal: WO4 on PB10 mux F */
+#define MUX_PB10F_TCC0_WO4 5L
+#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
+#define PORT_PB10F_TCC0_WO4 (1ul << 10)
+#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5 5L
+#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5 (1ul << 15)
+#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5 5L
+#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5 (1ul << 23)
+#define PIN_PB11F_TCC0_WO5 43L /**< \brief TCC0 signal: WO5 on PB11 mux F */
+#define MUX_PB11F_TCC0_WO5 5L
+#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
+#define PORT_PB11F_TCC0_WO5 (1ul << 11)
+#define PIN_PA12F_TCC0_WO6 12L /**< \brief TCC0 signal: WO6 on PA12 mux F */
+#define MUX_PA12F_TCC0_WO6 5L
+#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
+#define PORT_PA12F_TCC0_WO6 (1ul << 12)
+#define PIN_PA20F_TCC0_WO6 20L /**< \brief TCC0 signal: WO6 on PA20 mux F */
+#define MUX_PA20F_TCC0_WO6 5L
+#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
+#define PORT_PA20F_TCC0_WO6 (1ul << 20)
+#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6 5L
+#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6 (1ul << 16)
+#define PIN_PA13F_TCC0_WO7 13L /**< \brief TCC0 signal: WO7 on PA13 mux F */
+#define MUX_PA13F_TCC0_WO7 5L
+#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
+#define PORT_PA13F_TCC0_WO7 (1ul << 13)
+#define PIN_PA21F_TCC0_WO7 21L /**< \brief TCC0 signal: WO7 on PA21 mux F */
+#define MUX_PA21F_TCC0_WO7 5L
+#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
+#define PORT_PA21F_TCC0_WO7 (1ul << 21)
+#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7 5L
+#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7 (1ul << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0 4L
+#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0 (1ul << 6)
+#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0 4L
+#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0 (1ul << 10)
+#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0 4L
+#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0 (1ul << 30)
+#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1 4L
+#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1 (1ul << 7)
+#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1 4L
+#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1 (1ul << 11)
+#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1 4L
+#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1 (1ul << 31)
+#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2 5L
+#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2 (1ul << 8)
+#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2 5L
+#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2 (1ul << 24)
+#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3 5L
+#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3 (1ul << 9)
+#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3 5L
+#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3 (1ul << 25)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA12E_TCC2_WO0 12L /**< \brief TCC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TCC2_WO0 4L
+#define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
+#define PORT_PA12E_TCC2_WO0 (1ul << 12)
+#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0 4L
+#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0 (1ul << 16)
+#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0 4L
+#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0 (1ul << 0)
+#define PIN_PA13E_TCC2_WO1 13L /**< \brief TCC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TCC2_WO1 4L
+#define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
+#define PORT_PA13E_TCC2_WO1 (1ul << 13)
+#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1 4L
+#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1 (1ul << 17)
+#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1 4L
+#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1 (1ul << 1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0 4L
+#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0 (1ul << 18)
+#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0 4L
+#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0 (1ul << 14)
+#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1 4L
+#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1 (1ul << 19)
+#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1 4L
+#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1 (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0 4L
+#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0 (1ul << 22)
+#define PIN_PB08E_TC4_WO0 40L /**< \brief TC4 signal: WO0 on PB08 mux E */
+#define MUX_PB08E_TC4_WO0 4L
+#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
+#define PORT_PB08E_TC4_WO0 (1ul << 8)
+#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1 4L
+#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1 (1ul << 23)
+#define PIN_PB09E_TC4_WO1 41L /**< \brief TC4 signal: WO1 on PB09 mux E */
+#define MUX_PB09E_TC4_WO1 4L
+#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
+#define PORT_PB09E_TC4_WO1 (1ul << 9)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0 4L
+#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0 (1ul << 24)
+#define PIN_PB10E_TC5_WO0 42L /**< \brief TC5 signal: WO0 on PB10 mux E */
+#define MUX_PB10E_TC5_WO0 4L
+#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
+#define PORT_PB10E_TC5_WO0 (1ul << 10)
+#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1 4L
+#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1 (1ul << 25)
+#define PIN_PB11E_TC5_WO1 43L /**< \brief TC5 signal: WO1 on PB11 mux E */
+#define MUX_PB11E_TC5_WO1 4L
+#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
+#define PORT_PB11E_TC5_WO1 (1ul << 11)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0 1L
+#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0 (1ul << 2)
+#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1 1L
+#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1 (1ul << 3)
+#define PIN_PB08B_ADC_AIN2 40L /**< \brief ADC signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC_AIN2 1L
+#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
+#define PORT_PB08B_ADC_AIN2 (1ul << 8)
+#define PIN_PB09B_ADC_AIN3 41L /**< \brief ADC signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC_AIN3 1L
+#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
+#define PORT_PB09B_ADC_AIN3 (1ul << 9)
+#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4 1L
+#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4 (1ul << 4)
+#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5 1L
+#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5 (1ul << 5)
+#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6 1L
+#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6 (1ul << 6)
+#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7 1L
+#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7 (1ul << 7)
+#define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */
+#define MUX_PB02B_ADC_AIN10 1L
+#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
+#define PORT_PB02B_ADC_AIN10 (1ul << 2)
+#define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */
+#define MUX_PB03B_ADC_AIN11 1L
+#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
+#define PORT_PB03B_ADC_AIN11 (1ul << 3)
+#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16 1L
+#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16 (1ul << 8)
+#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17 1L
+#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17 (1ul << 9)
+#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18 1L
+#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18 (1ul << 10)
+#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19 1L
+#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19 (1ul << 11)
+#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP 1L
+#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP (1ul << 4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0 1L
+#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0 (1ul << 4)
+#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1 1L
+#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1 (1ul << 5)
+#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2 1L
+#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2 (1ul << 6)
+#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3 1L
+#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3 (1ul << 7)
+#define PIN_PA12H_AC_CMP0 12L /**< \brief AC signal: CMP0 on PA12 mux H */
+#define MUX_PA12H_AC_CMP0 7L
+#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
+#define PORT_PA12H_AC_CMP0 (1ul << 12)
+#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0 7L
+#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0 (1ul << 18)
+#define PIN_PA13H_AC_CMP1 13L /**< \brief AC signal: CMP1 on PA13 mux H */
+#define MUX_PA13H_AC_CMP1 7L
+#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
+#define PORT_PA13H_AC_CMP1 (1ul << 13)
+#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1 7L
+#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1 (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT 1L
+#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT (1ul << 2)
+#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP 1L
+#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP (1ul << 3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0 11L /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0 6L
+#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0 (1ul << 11)
+#define PIN_PA21G_I2S_FS0 21L /**< \brief I2S signal: FS0 on PA21 mux G */
+#define MUX_PA21G_I2S_FS0 6L
+#define PINMUX_PA21G_I2S_FS0 ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
+#define PORT_PA21G_I2S_FS0 (1ul << 21)
+#define PIN_PA09G_I2S_MCK0 9L /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0 6L
+#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0 (1ul << 9)
+#define PIN_PB10G_I2S_MCK1 42L /**< \brief I2S signal: MCK1 on PB10 mux G */
+#define MUX_PB10G_I2S_MCK1 6L
+#define PINMUX_PB10G_I2S_MCK1 ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1)
+#define PORT_PB10G_I2S_MCK1 (1ul << 10)
+#define PIN_PA10G_I2S_SCK0 10L /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0 6L
+#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0 (1ul << 10)
+#define PIN_PA20G_I2S_SCK0 20L /**< \brief I2S signal: SCK0 on PA20 mux G */
+#define MUX_PA20G_I2S_SCK0 6L
+#define PINMUX_PA20G_I2S_SCK0 ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
+#define PORT_PA20G_I2S_SCK0 (1ul << 20)
+#define PIN_PB11G_I2S_SCK1 43L /**< \brief I2S signal: SCK1 on PB11 mux G */
+#define MUX_PB11G_I2S_SCK1 6L
+#define PINMUX_PB11G_I2S_SCK1 ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1)
+#define PORT_PB11G_I2S_SCK1 (1ul << 11)
+#define PIN_PA07G_I2S_SD0 7L /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0 6L
+#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0 (1ul << 7)
+#define PIN_PA19G_I2S_SD0 19L /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0 6L
+#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0 (1ul << 19)
+#define PIN_PA08G_I2S_SD1 8L /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1 6L
+#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1 (1ul << 8)
+
+#endif /* _SAMD21G16A_PIO_ */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/pio/samd21g17a.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/pio/samd21g17a.h
new file mode 100644
index 0000000000000000000000000000000000000000..c73f2194e8c4f01d7db190377c74a676a7f54df1
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/pio/samd21g17a.h
@@ -0,0 +1,915 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21G17A
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21G17A_PIO_
+#define _SAMD21G17A_PIO_
+
+#define PIN_PA00 0 /**< \brief Pin Number for PA00 */
+#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */
+#define PIN_PA01 1 /**< \brief Pin Number for PA01 */
+#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */
+#define PIN_PA02 2 /**< \brief Pin Number for PA02 */
+#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */
+#define PIN_PA03 3 /**< \brief Pin Number for PA03 */
+#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */
+#define PIN_PA04 4 /**< \brief Pin Number for PA04 */
+#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */
+#define PIN_PA05 5 /**< \brief Pin Number for PA05 */
+#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */
+#define PIN_PA06 6 /**< \brief Pin Number for PA06 */
+#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */
+#define PIN_PA07 7 /**< \brief Pin Number for PA07 */
+#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */
+#define PIN_PA08 8 /**< \brief Pin Number for PA08 */
+#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */
+#define PIN_PA09 9 /**< \brief Pin Number for PA09 */
+#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */
+#define PIN_PA10 10 /**< \brief Pin Number for PA10 */
+#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */
+#define PIN_PA11 11 /**< \brief Pin Number for PA11 */
+#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */
+#define PIN_PA12 12 /**< \brief Pin Number for PA12 */
+#define PORT_PA12 (1ul << 12) /**< \brief PORT Mask for PA12 */
+#define PIN_PA13 13 /**< \brief Pin Number for PA13 */
+#define PORT_PA13 (1ul << 13) /**< \brief PORT Mask for PA13 */
+#define PIN_PA14 14 /**< \brief Pin Number for PA14 */
+#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */
+#define PIN_PA15 15 /**< \brief Pin Number for PA15 */
+#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */
+#define PIN_PA16 16 /**< \brief Pin Number for PA16 */
+#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */
+#define PIN_PA17 17 /**< \brief Pin Number for PA17 */
+#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */
+#define PIN_PA18 18 /**< \brief Pin Number for PA18 */
+#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */
+#define PIN_PA19 19 /**< \brief Pin Number for PA19 */
+#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */
+#define PIN_PA20 20 /**< \brief Pin Number for PA20 */
+#define PORT_PA20 (1ul << 20) /**< \brief PORT Mask for PA20 */
+#define PIN_PA21 21 /**< \brief Pin Number for PA21 */
+#define PORT_PA21 (1ul << 21) /**< \brief PORT Mask for PA21 */
+#define PIN_PA22 22 /**< \brief Pin Number for PA22 */
+#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */
+#define PIN_PA23 23 /**< \brief Pin Number for PA23 */
+#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */
+#define PIN_PA24 24 /**< \brief Pin Number for PA24 */
+#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */
+#define PIN_PA25 25 /**< \brief Pin Number for PA25 */
+#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */
+#define PIN_PA27 27 /**< \brief Pin Number for PA27 */
+#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */
+#define PIN_PA28 28 /**< \brief Pin Number for PA28 */
+#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */
+#define PIN_PA30 30 /**< \brief Pin Number for PA30 */
+#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */
+#define PIN_PA31 31 /**< \brief Pin Number for PA31 */
+#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */
+#define PIN_PB02 34 /**< \brief Pin Number for PB02 */
+#define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */
+#define PIN_PB03 35 /**< \brief Pin Number for PB03 */
+#define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */
+#define PIN_PB08 40 /**< \brief Pin Number for PB08 */
+#define PORT_PB08 (1ul << 8) /**< \brief PORT Mask for PB08 */
+#define PIN_PB09 41 /**< \brief Pin Number for PB09 */
+#define PORT_PB09 (1ul << 9) /**< \brief PORT Mask for PB09 */
+#define PIN_PB10 42 /**< \brief Pin Number for PB10 */
+#define PORT_PB10 (1ul << 10) /**< \brief PORT Mask for PB10 */
+#define PIN_PB11 43 /**< \brief Pin Number for PB11 */
+#define PORT_PB11 (1ul << 11) /**< \brief PORT Mask for PB11 */
+#define PIN_PB22 54 /**< \brief Pin Number for PB22 */
+#define PORT_PB22 (1ul << 22) /**< \brief PORT Mask for PB22 */
+#define PIN_PB23 55 /**< \brief Pin Number for PB23 */
+#define PORT_PB23 (1ul << 23) /**< \brief PORT Mask for PB23 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PB22H_GCLK_IO0 54L /**< \brief GCLK signal: IO0 on PB22 mux H */
+#define MUX_PB22H_GCLK_IO0 7L
+#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
+#define PORT_PB22H_GCLK_IO0 (1ul << 22)
+#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0 7L
+#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0 (1ul << 14)
+#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0 7L
+#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0 (1ul << 27)
+#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0 7L
+#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0 (1ul << 28)
+#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0 7L
+#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0 (1ul << 30)
+#define PIN_PB23H_GCLK_IO1 55L /**< \brief GCLK signal: IO1 on PB23 mux H */
+#define MUX_PB23H_GCLK_IO1 7L
+#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
+#define PORT_PB23H_GCLK_IO1 (1ul << 23)
+#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1 7L
+#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1 (1ul << 15)
+#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2 7L
+#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2 (1ul << 16)
+#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3 7L
+#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3 (1ul << 17)
+#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4 7L
+#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4 (1ul << 10)
+#define PIN_PA20H_GCLK_IO4 20L /**< \brief GCLK signal: IO4 on PA20 mux H */
+#define MUX_PA20H_GCLK_IO4 7L
+#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
+#define PORT_PA20H_GCLK_IO4 (1ul << 20)
+#define PIN_PB10H_GCLK_IO4 42L /**< \brief GCLK signal: IO4 on PB10 mux H */
+#define MUX_PB10H_GCLK_IO4 7L
+#define PINMUX_PB10H_GCLK_IO4 ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
+#define PORT_PB10H_GCLK_IO4 (1ul << 10)
+#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5 7L
+#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5 (1ul << 11)
+#define PIN_PA21H_GCLK_IO5 21L /**< \brief GCLK signal: IO5 on PA21 mux H */
+#define MUX_PA21H_GCLK_IO5 7L
+#define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
+#define PORT_PA21H_GCLK_IO5 (1ul << 21)
+#define PIN_PB11H_GCLK_IO5 43L /**< \brief GCLK signal: IO5 on PB11 mux H */
+#define MUX_PB11H_GCLK_IO5 7L
+#define PINMUX_PB11H_GCLK_IO5 ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
+#define PORT_PB11H_GCLK_IO5 (1ul << 11)
+#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6 7L
+#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6 (1ul << 22)
+#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7 7L
+#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7 (1ul << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0 0L
+#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0 (1ul << 16)
+#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0 0L
+#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0 (1ul << 0)
+#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1 0L
+#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1 (1ul << 17)
+#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1 0L
+#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1 (1ul << 1)
+#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2 0L
+#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2 (1ul << 18)
+#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2 0L
+#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2 (1ul << 2)
+#define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2 0L
+#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2 (1ul << 2)
+#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3 0L
+#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3 (1ul << 3)
+#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3 0L
+#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3 (1ul << 19)
+#define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3 0L
+#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3 (1ul << 3)
+#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4 0L
+#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4 (1ul << 4)
+#define PIN_PA20A_EIC_EXTINT4 20L /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4 0L
+#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4 (1ul << 20)
+#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5 0L
+#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5 (1ul << 5)
+#define PIN_PA21A_EIC_EXTINT5 21L /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5 0L
+#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5 (1ul << 21)
+#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6 0L
+#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6 (1ul << 6)
+#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6 0L
+#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6 (1ul << 22)
+#define PIN_PB22A_EIC_EXTINT6 54L /**< \brief EIC signal: EXTINT6 on PB22 mux A */
+#define MUX_PB22A_EIC_EXTINT6 0L
+#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
+#define PORT_PB22A_EIC_EXTINT6 (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7 0L
+#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7 (1ul << 7)
+#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7 0L
+#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7 (1ul << 23)
+#define PIN_PB23A_EIC_EXTINT7 55L /**< \brief EIC signal: EXTINT7 on PB23 mux A */
+#define MUX_PB23A_EIC_EXTINT7 0L
+#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
+#define PORT_PB23A_EIC_EXTINT7 (1ul << 23)
+#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8 0L
+#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8 (1ul << 28)
+#define PIN_PB08A_EIC_EXTINT8 40L /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8 0L
+#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8 (1ul << 8)
+#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9 0L
+#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9 (1ul << 9)
+#define PIN_PB09A_EIC_EXTINT9 41L /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9 0L
+#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9 (1ul << 9)
+#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10 0L
+#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10 (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10 0L
+#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10 (1ul << 30)
+#define PIN_PB10A_EIC_EXTINT10 42L /**< \brief EIC signal: EXTINT10 on PB10 mux A */
+#define MUX_PB10A_EIC_EXTINT10 0L
+#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
+#define PORT_PB10A_EIC_EXTINT10 (1ul << 10)
+#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11 0L
+#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11 (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11 0L
+#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11 (1ul << 31)
+#define PIN_PB11A_EIC_EXTINT11 43L /**< \brief EIC signal: EXTINT11 on PB11 mux A */
+#define MUX_PB11A_EIC_EXTINT11 0L
+#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
+#define PORT_PB11A_EIC_EXTINT11 (1ul << 11)
+#define PIN_PA12A_EIC_EXTINT12 12L /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12 0L
+#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12 (1ul << 12)
+#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12 0L
+#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12 (1ul << 24)
+#define PIN_PA13A_EIC_EXTINT13 13L /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13 0L
+#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13 (1ul << 13)
+#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13 0L
+#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13 (1ul << 25)
+#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14 0L
+#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14 (1ul << 14)
+#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15 0L
+#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15 (1ul << 15)
+#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15 0L
+#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15 (1ul << 27)
+#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI 0L
+#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI (1ul << 8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM 6L
+#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM (1ul << 24)
+#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP 6L
+#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP (1ul << 25)
+#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ 6L
+#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0 3L
+#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4)
+#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0 2L
+#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8)
+#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1 3L
+#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5)
+#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1 2L
+#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9)
+#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2 3L
+#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6)
+#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2 2L
+#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3 3L
+#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7)
+#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3 2L
+#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0 2L
+#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16)
+#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0 3L
+#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0)
+#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1 2L
+#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17)
+#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1 3L
+#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1)
+#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2 3L
+#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2 2L
+#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3 3L
+#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3 2L
+#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0 3L
+#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8)
+#define PIN_PA12C_SERCOM2_PAD0 12L /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0 2L
+#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0 (1ul << 12)
+#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1 3L
+#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9)
+#define PIN_PA13C_SERCOM2_PAD1 13L /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1 2L
+#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1 (1ul << 13)
+#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2 3L
+#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2 2L
+#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3 3L
+#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3 2L
+#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0 3L
+#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0 2L
+#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1 3L
+#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1 2L
+#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2 3L
+#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18)
+#define PIN_PA20D_SERCOM3_PAD2 20L /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2 3L
+#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2 (1ul << 20)
+#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2 2L
+#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3 3L
+#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19)
+#define PIN_PA21D_SERCOM3_PAD3 21L /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3 3L
+#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3 (1ul << 21)
+#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3 2L
+#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA12D_SERCOM4_PAD0 12L /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD0 3L
+#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
+#define PORT_PA12D_SERCOM4_PAD0 (1ul << 12)
+#define PIN_PB08D_SERCOM4_PAD0 40L /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0 3L
+#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0 (1ul << 8)
+#define PIN_PA13D_SERCOM4_PAD1 13L /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD1 3L
+#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
+#define PORT_PA13D_SERCOM4_PAD1 (1ul << 13)
+#define PIN_PB09D_SERCOM4_PAD1 41L /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1 3L
+#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1 (1ul << 9)
+#define PIN_PA14D_SERCOM4_PAD2 14L /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2 3L
+#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2 (1ul << 14)
+#define PIN_PB10D_SERCOM4_PAD2 42L /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
+#define MUX_PB10D_SERCOM4_PAD2 3L
+#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
+#define PORT_PB10D_SERCOM4_PAD2 (1ul << 10)
+#define PIN_PA15D_SERCOM4_PAD3 15L /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3 3L
+#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3 (1ul << 15)
+#define PIN_PB11D_SERCOM4_PAD3 43L /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
+#define MUX_PB11D_SERCOM4_PAD3 3L
+#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
+#define PORT_PB11D_SERCOM4_PAD3 (1ul << 11)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PA22D_SERCOM5_PAD0 22L /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD0 3L
+#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
+#define PORT_PA22D_SERCOM5_PAD0 (1ul << 22)
+#define PIN_PB02D_SERCOM5_PAD0 34L /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0 3L
+#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0 (1ul << 2)
+#define PIN_PA23D_SERCOM5_PAD1 23L /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD1 3L
+#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
+#define PORT_PA23D_SERCOM5_PAD1 (1ul << 23)
+#define PIN_PB03D_SERCOM5_PAD1 35L /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1 3L
+#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1 (1ul << 3)
+#define PIN_PA24D_SERCOM5_PAD2 24L /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2 3L
+#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2 (1ul << 24)
+#define PIN_PB22D_SERCOM5_PAD2 54L /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
+#define MUX_PB22D_SERCOM5_PAD2 3L
+#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
+#define PORT_PB22D_SERCOM5_PAD2 (1ul << 22)
+#define PIN_PA20C_SERCOM5_PAD2 20L /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2 2L
+#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2 (1ul << 20)
+#define PIN_PA25D_SERCOM5_PAD3 25L /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3 3L
+#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3 (1ul << 25)
+#define PIN_PB23D_SERCOM5_PAD3 55L /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
+#define MUX_PB23D_SERCOM5_PAD3 3L
+#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
+#define PORT_PB23D_SERCOM5_PAD3 (1ul << 23)
+#define PIN_PA21C_SERCOM5_PAD3 21L /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3 2L
+#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3 (1ul << 21)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0 4L
+#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0 (1ul << 4)
+#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0 4L
+#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0 (1ul << 8)
+#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1 4L
+#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1 (1ul << 5)
+#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1 4L
+#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1 (1ul << 9)
+#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2 5L
+#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2 (1ul << 10)
+#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2 5L
+#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2 (1ul << 18)
+#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3 5L
+#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3 (1ul << 11)
+#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3 5L
+#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3 (1ul << 19)
+#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4 5L
+#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4 (1ul << 14)
+#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4 5L
+#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4 (1ul << 22)
+#define PIN_PB10F_TCC0_WO4 42L /**< \brief TCC0 signal: WO4 on PB10 mux F */
+#define MUX_PB10F_TCC0_WO4 5L
+#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
+#define PORT_PB10F_TCC0_WO4 (1ul << 10)
+#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5 5L
+#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5 (1ul << 15)
+#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5 5L
+#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5 (1ul << 23)
+#define PIN_PB11F_TCC0_WO5 43L /**< \brief TCC0 signal: WO5 on PB11 mux F */
+#define MUX_PB11F_TCC0_WO5 5L
+#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
+#define PORT_PB11F_TCC0_WO5 (1ul << 11)
+#define PIN_PA12F_TCC0_WO6 12L /**< \brief TCC0 signal: WO6 on PA12 mux F */
+#define MUX_PA12F_TCC0_WO6 5L
+#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
+#define PORT_PA12F_TCC0_WO6 (1ul << 12)
+#define PIN_PA20F_TCC0_WO6 20L /**< \brief TCC0 signal: WO6 on PA20 mux F */
+#define MUX_PA20F_TCC0_WO6 5L
+#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
+#define PORT_PA20F_TCC0_WO6 (1ul << 20)
+#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6 5L
+#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6 (1ul << 16)
+#define PIN_PA13F_TCC0_WO7 13L /**< \brief TCC0 signal: WO7 on PA13 mux F */
+#define MUX_PA13F_TCC0_WO7 5L
+#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
+#define PORT_PA13F_TCC0_WO7 (1ul << 13)
+#define PIN_PA21F_TCC0_WO7 21L /**< \brief TCC0 signal: WO7 on PA21 mux F */
+#define MUX_PA21F_TCC0_WO7 5L
+#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
+#define PORT_PA21F_TCC0_WO7 (1ul << 21)
+#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7 5L
+#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7 (1ul << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0 4L
+#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0 (1ul << 6)
+#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0 4L
+#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0 (1ul << 10)
+#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0 4L
+#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0 (1ul << 30)
+#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1 4L
+#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1 (1ul << 7)
+#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1 4L
+#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1 (1ul << 11)
+#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1 4L
+#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1 (1ul << 31)
+#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2 5L
+#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2 (1ul << 8)
+#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2 5L
+#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2 (1ul << 24)
+#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3 5L
+#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3 (1ul << 9)
+#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3 5L
+#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3 (1ul << 25)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA12E_TCC2_WO0 12L /**< \brief TCC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TCC2_WO0 4L
+#define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
+#define PORT_PA12E_TCC2_WO0 (1ul << 12)
+#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0 4L
+#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0 (1ul << 16)
+#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0 4L
+#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0 (1ul << 0)
+#define PIN_PA13E_TCC2_WO1 13L /**< \brief TCC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TCC2_WO1 4L
+#define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
+#define PORT_PA13E_TCC2_WO1 (1ul << 13)
+#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1 4L
+#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1 (1ul << 17)
+#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1 4L
+#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1 (1ul << 1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0 4L
+#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0 (1ul << 18)
+#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0 4L
+#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0 (1ul << 14)
+#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1 4L
+#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1 (1ul << 19)
+#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1 4L
+#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1 (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0 4L
+#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0 (1ul << 22)
+#define PIN_PB08E_TC4_WO0 40L /**< \brief TC4 signal: WO0 on PB08 mux E */
+#define MUX_PB08E_TC4_WO0 4L
+#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
+#define PORT_PB08E_TC4_WO0 (1ul << 8)
+#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1 4L
+#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1 (1ul << 23)
+#define PIN_PB09E_TC4_WO1 41L /**< \brief TC4 signal: WO1 on PB09 mux E */
+#define MUX_PB09E_TC4_WO1 4L
+#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
+#define PORT_PB09E_TC4_WO1 (1ul << 9)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0 4L
+#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0 (1ul << 24)
+#define PIN_PB10E_TC5_WO0 42L /**< \brief TC5 signal: WO0 on PB10 mux E */
+#define MUX_PB10E_TC5_WO0 4L
+#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
+#define PORT_PB10E_TC5_WO0 (1ul << 10)
+#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1 4L
+#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1 (1ul << 25)
+#define PIN_PB11E_TC5_WO1 43L /**< \brief TC5 signal: WO1 on PB11 mux E */
+#define MUX_PB11E_TC5_WO1 4L
+#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
+#define PORT_PB11E_TC5_WO1 (1ul << 11)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0 1L
+#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0 (1ul << 2)
+#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1 1L
+#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1 (1ul << 3)
+#define PIN_PB08B_ADC_AIN2 40L /**< \brief ADC signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC_AIN2 1L
+#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
+#define PORT_PB08B_ADC_AIN2 (1ul << 8)
+#define PIN_PB09B_ADC_AIN3 41L /**< \brief ADC signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC_AIN3 1L
+#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
+#define PORT_PB09B_ADC_AIN3 (1ul << 9)
+#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4 1L
+#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4 (1ul << 4)
+#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5 1L
+#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5 (1ul << 5)
+#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6 1L
+#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6 (1ul << 6)
+#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7 1L
+#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7 (1ul << 7)
+#define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */
+#define MUX_PB02B_ADC_AIN10 1L
+#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
+#define PORT_PB02B_ADC_AIN10 (1ul << 2)
+#define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */
+#define MUX_PB03B_ADC_AIN11 1L
+#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
+#define PORT_PB03B_ADC_AIN11 (1ul << 3)
+#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16 1L
+#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16 (1ul << 8)
+#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17 1L
+#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17 (1ul << 9)
+#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18 1L
+#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18 (1ul << 10)
+#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19 1L
+#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19 (1ul << 11)
+#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP 1L
+#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP (1ul << 4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0 1L
+#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0 (1ul << 4)
+#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1 1L
+#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1 (1ul << 5)
+#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2 1L
+#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2 (1ul << 6)
+#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3 1L
+#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3 (1ul << 7)
+#define PIN_PA12H_AC_CMP0 12L /**< \brief AC signal: CMP0 on PA12 mux H */
+#define MUX_PA12H_AC_CMP0 7L
+#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
+#define PORT_PA12H_AC_CMP0 (1ul << 12)
+#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0 7L
+#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0 (1ul << 18)
+#define PIN_PA13H_AC_CMP1 13L /**< \brief AC signal: CMP1 on PA13 mux H */
+#define MUX_PA13H_AC_CMP1 7L
+#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
+#define PORT_PA13H_AC_CMP1 (1ul << 13)
+#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1 7L
+#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1 (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT 1L
+#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT (1ul << 2)
+#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP 1L
+#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP (1ul << 3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0 11L /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0 6L
+#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0 (1ul << 11)
+#define PIN_PA21G_I2S_FS0 21L /**< \brief I2S signal: FS0 on PA21 mux G */
+#define MUX_PA21G_I2S_FS0 6L
+#define PINMUX_PA21G_I2S_FS0 ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
+#define PORT_PA21G_I2S_FS0 (1ul << 21)
+#define PIN_PA09G_I2S_MCK0 9L /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0 6L
+#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0 (1ul << 9)
+#define PIN_PB10G_I2S_MCK1 42L /**< \brief I2S signal: MCK1 on PB10 mux G */
+#define MUX_PB10G_I2S_MCK1 6L
+#define PINMUX_PB10G_I2S_MCK1 ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1)
+#define PORT_PB10G_I2S_MCK1 (1ul << 10)
+#define PIN_PA10G_I2S_SCK0 10L /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0 6L
+#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0 (1ul << 10)
+#define PIN_PA20G_I2S_SCK0 20L /**< \brief I2S signal: SCK0 on PA20 mux G */
+#define MUX_PA20G_I2S_SCK0 6L
+#define PINMUX_PA20G_I2S_SCK0 ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
+#define PORT_PA20G_I2S_SCK0 (1ul << 20)
+#define PIN_PB11G_I2S_SCK1 43L /**< \brief I2S signal: SCK1 on PB11 mux G */
+#define MUX_PB11G_I2S_SCK1 6L
+#define PINMUX_PB11G_I2S_SCK1 ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1)
+#define PORT_PB11G_I2S_SCK1 (1ul << 11)
+#define PIN_PA07G_I2S_SD0 7L /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0 6L
+#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0 (1ul << 7)
+#define PIN_PA19G_I2S_SD0 19L /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0 6L
+#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0 (1ul << 19)
+#define PIN_PA08G_I2S_SD1 8L /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1 6L
+#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1 (1ul << 8)
+
+#endif /* _SAMD21G17A_PIO_ */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/pio/samd21g17au.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/pio/samd21g17au.h
new file mode 100644
index 0000000000000000000000000000000000000000..c245c493c64ca0c7cf02daebbb20594276647cd3
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/pio/samd21g17au.h
@@ -0,0 +1,863 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21G17AU
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21G17AU_PIO_
+#define _SAMD21G17AU_PIO_
+
+#define PIN_PA00 0 /**< \brief Pin Number for PA00 */
+#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */
+#define PIN_PA01 1 /**< \brief Pin Number for PA01 */
+#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */
+#define PIN_PA02 2 /**< \brief Pin Number for PA02 */
+#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */
+#define PIN_PA03 3 /**< \brief Pin Number for PA03 */
+#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */
+#define PIN_PA04 4 /**< \brief Pin Number for PA04 */
+#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */
+#define PIN_PA05 5 /**< \brief Pin Number for PA05 */
+#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */
+#define PIN_PA06 6 /**< \brief Pin Number for PA06 */
+#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */
+#define PIN_PA07 7 /**< \brief Pin Number for PA07 */
+#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */
+#define PIN_PA08 8 /**< \brief Pin Number for PA08 */
+#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */
+#define PIN_PA09 9 /**< \brief Pin Number for PA09 */
+#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */
+#define PIN_PA10 10 /**< \brief Pin Number for PA10 */
+#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */
+#define PIN_PA11 11 /**< \brief Pin Number for PA11 */
+#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */
+#define PIN_PA12 12 /**< \brief Pin Number for PA12 */
+#define PORT_PA12 (1ul << 12) /**< \brief PORT Mask for PA12 */
+#define PIN_PA13 13 /**< \brief Pin Number for PA13 */
+#define PORT_PA13 (1ul << 13) /**< \brief PORT Mask for PA13 */
+#define PIN_PA14 14 /**< \brief Pin Number for PA14 */
+#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */
+#define PIN_PA15 15 /**< \brief Pin Number for PA15 */
+#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */
+#define PIN_PA16 16 /**< \brief Pin Number for PA16 */
+#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */
+#define PIN_PA17 17 /**< \brief Pin Number for PA17 */
+#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */
+#define PIN_PA18 18 /**< \brief Pin Number for PA18 */
+#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */
+#define PIN_PA19 19 /**< \brief Pin Number for PA19 */
+#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */
+#define PIN_PA20 20 /**< \brief Pin Number for PA20 */
+#define PORT_PA20 (1ul << 20) /**< \brief PORT Mask for PA20 */
+#define PIN_PA21 21 /**< \brief Pin Number for PA21 */
+#define PORT_PA21 (1ul << 21) /**< \brief PORT Mask for PA21 */
+#define PIN_PA22 22 /**< \brief Pin Number for PA22 */
+#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */
+#define PIN_PA23 23 /**< \brief Pin Number for PA23 */
+#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */
+#define PIN_PA24 24 /**< \brief Pin Number for PA24 */
+#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */
+#define PIN_PA25 25 /**< \brief Pin Number for PA25 */
+#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */
+#define PIN_PA27 27 /**< \brief Pin Number for PA27 */
+#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */
+#define PIN_PA28 28 /**< \brief Pin Number for PA28 */
+#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */
+#define PIN_PA30 30 /**< \brief Pin Number for PA30 */
+#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */
+#define PIN_PA31 31 /**< \brief Pin Number for PA31 */
+#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */
+#define PIN_PB02 34 /**< \brief Pin Number for PB02 */
+#define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */
+#define PIN_PB03 35 /**< \brief Pin Number for PB03 */
+#define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */
+#define PIN_PB04 36 /**< \brief Pin Number for PB04 */
+#define PORT_PB04 (1ul << 4) /**< \brief PORT Mask for PB04 */
+#define PIN_PB08 40 /**< \brief Pin Number for PB08 */
+#define PORT_PB08 (1ul << 8) /**< \brief PORT Mask for PB08 */
+#define PIN_PB09 41 /**< \brief Pin Number for PB09 */
+#define PORT_PB09 (1ul << 9) /**< \brief PORT Mask for PB09 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0 7L
+#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0 (1ul << 14)
+#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0 7L
+#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0 (1ul << 27)
+#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0 7L
+#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0 (1ul << 28)
+#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0 7L
+#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0 (1ul << 30)
+#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1 7L
+#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1 (1ul << 15)
+#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2 7L
+#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2 (1ul << 16)
+#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3 7L
+#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3 (1ul << 17)
+#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4 7L
+#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4 (1ul << 10)
+#define PIN_PA20H_GCLK_IO4 20L /**< \brief GCLK signal: IO4 on PA20 mux H */
+#define MUX_PA20H_GCLK_IO4 7L
+#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
+#define PORT_PA20H_GCLK_IO4 (1ul << 20)
+#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5 7L
+#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5 (1ul << 11)
+#define PIN_PA21H_GCLK_IO5 21L /**< \brief GCLK signal: IO5 on PA21 mux H */
+#define MUX_PA21H_GCLK_IO5 7L
+#define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
+#define PORT_PA21H_GCLK_IO5 (1ul << 21)
+#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6 7L
+#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6 (1ul << 22)
+#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7 7L
+#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7 (1ul << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0 0L
+#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0 (1ul << 16)
+#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0 0L
+#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0 (1ul << 0)
+#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1 0L
+#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1 (1ul << 17)
+#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1 0L
+#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1 (1ul << 1)
+#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2 0L
+#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2 (1ul << 18)
+#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2 0L
+#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2 (1ul << 2)
+#define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2 0L
+#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2 (1ul << 2)
+#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3 0L
+#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3 (1ul << 3)
+#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3 0L
+#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3 (1ul << 19)
+#define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3 0L
+#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3 (1ul << 3)
+#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4 0L
+#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4 (1ul << 4)
+#define PIN_PA20A_EIC_EXTINT4 20L /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4 0L
+#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4 (1ul << 20)
+#define PIN_PB04A_EIC_EXTINT4 36L /**< \brief EIC signal: EXTINT4 on PB04 mux A */
+#define MUX_PB04A_EIC_EXTINT4 0L
+#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
+#define PORT_PB04A_EIC_EXTINT4 (1ul << 4)
+#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5 0L
+#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5 (1ul << 5)
+#define PIN_PA21A_EIC_EXTINT5 21L /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5 0L
+#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5 (1ul << 21)
+#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6 0L
+#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6 (1ul << 6)
+#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6 0L
+#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6 (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7 0L
+#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7 (1ul << 7)
+#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7 0L
+#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7 (1ul << 23)
+#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8 0L
+#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8 (1ul << 28)
+#define PIN_PB08A_EIC_EXTINT8 40L /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8 0L
+#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8 (1ul << 8)
+#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9 0L
+#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9 (1ul << 9)
+#define PIN_PB09A_EIC_EXTINT9 41L /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9 0L
+#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9 (1ul << 9)
+#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10 0L
+#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10 (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10 0L
+#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10 (1ul << 30)
+#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11 0L
+#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11 (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11 0L
+#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11 (1ul << 31)
+#define PIN_PA12A_EIC_EXTINT12 12L /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12 0L
+#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12 (1ul << 12)
+#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12 0L
+#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12 (1ul << 24)
+#define PIN_PA13A_EIC_EXTINT13 13L /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13 0L
+#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13 (1ul << 13)
+#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13 0L
+#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13 (1ul << 25)
+#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14 0L
+#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14 (1ul << 14)
+#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15 0L
+#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15 (1ul << 15)
+#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15 0L
+#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15 (1ul << 27)
+#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI 0L
+#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI (1ul << 8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM 6L
+#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM (1ul << 24)
+#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP 6L
+#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP (1ul << 25)
+#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ 6L
+#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0 3L
+#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4)
+#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0 2L
+#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8)
+#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1 3L
+#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5)
+#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1 2L
+#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9)
+#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2 3L
+#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6)
+#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2 2L
+#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3 3L
+#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7)
+#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3 2L
+#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0 2L
+#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16)
+#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0 3L
+#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0)
+#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1 2L
+#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17)
+#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1 3L
+#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1)
+#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2 3L
+#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2 2L
+#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3 3L
+#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3 2L
+#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0 3L
+#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8)
+#define PIN_PA12C_SERCOM2_PAD0 12L /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0 2L
+#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0 (1ul << 12)
+#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1 3L
+#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9)
+#define PIN_PA13C_SERCOM2_PAD1 13L /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1 2L
+#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1 (1ul << 13)
+#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2 3L
+#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2 2L
+#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3 3L
+#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3 2L
+#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0 3L
+#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0 2L
+#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1 3L
+#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1 2L
+#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2 3L
+#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18)
+#define PIN_PA20D_SERCOM3_PAD2 20L /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2 3L
+#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2 (1ul << 20)
+#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2 2L
+#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3 3L
+#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19)
+#define PIN_PA21D_SERCOM3_PAD3 21L /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3 3L
+#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3 (1ul << 21)
+#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3 2L
+#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA12D_SERCOM4_PAD0 12L /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD0 3L
+#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
+#define PORT_PA12D_SERCOM4_PAD0 (1ul << 12)
+#define PIN_PB08D_SERCOM4_PAD0 40L /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0 3L
+#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0 (1ul << 8)
+#define PIN_PA13D_SERCOM4_PAD1 13L /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD1 3L
+#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
+#define PORT_PA13D_SERCOM4_PAD1 (1ul << 13)
+#define PIN_PB09D_SERCOM4_PAD1 41L /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1 3L
+#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1 (1ul << 9)
+#define PIN_PA14D_SERCOM4_PAD2 14L /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2 3L
+#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2 (1ul << 14)
+#define PIN_PA15D_SERCOM4_PAD3 15L /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3 3L
+#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3 (1ul << 15)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PA22D_SERCOM5_PAD0 22L /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD0 3L
+#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
+#define PORT_PA22D_SERCOM5_PAD0 (1ul << 22)
+#define PIN_PB02D_SERCOM5_PAD0 34L /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0 3L
+#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0 (1ul << 2)
+#define PIN_PA23D_SERCOM5_PAD1 23L /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD1 3L
+#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
+#define PORT_PA23D_SERCOM5_PAD1 (1ul << 23)
+#define PIN_PB03D_SERCOM5_PAD1 35L /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1 3L
+#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1 (1ul << 3)
+#define PIN_PA24D_SERCOM5_PAD2 24L /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2 3L
+#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2 (1ul << 24)
+#define PIN_PA20C_SERCOM5_PAD2 20L /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2 2L
+#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2 (1ul << 20)
+#define PIN_PA25D_SERCOM5_PAD3 25L /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3 3L
+#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3 (1ul << 25)
+#define PIN_PA21C_SERCOM5_PAD3 21L /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3 2L
+#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3 (1ul << 21)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0 4L
+#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0 (1ul << 4)
+#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0 4L
+#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0 (1ul << 8)
+#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1 4L
+#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1 (1ul << 5)
+#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1 4L
+#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1 (1ul << 9)
+#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2 5L
+#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2 (1ul << 10)
+#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2 5L
+#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2 (1ul << 18)
+#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3 5L
+#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3 (1ul << 11)
+#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3 5L
+#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3 (1ul << 19)
+#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4 5L
+#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4 (1ul << 14)
+#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4 5L
+#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4 (1ul << 22)
+#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5 5L
+#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5 (1ul << 15)
+#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5 5L
+#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5 (1ul << 23)
+#define PIN_PA12F_TCC0_WO6 12L /**< \brief TCC0 signal: WO6 on PA12 mux F */
+#define MUX_PA12F_TCC0_WO6 5L
+#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
+#define PORT_PA12F_TCC0_WO6 (1ul << 12)
+#define PIN_PA20F_TCC0_WO6 20L /**< \brief TCC0 signal: WO6 on PA20 mux F */
+#define MUX_PA20F_TCC0_WO6 5L
+#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
+#define PORT_PA20F_TCC0_WO6 (1ul << 20)
+#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6 5L
+#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6 (1ul << 16)
+#define PIN_PA13F_TCC0_WO7 13L /**< \brief TCC0 signal: WO7 on PA13 mux F */
+#define MUX_PA13F_TCC0_WO7 5L
+#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
+#define PORT_PA13F_TCC0_WO7 (1ul << 13)
+#define PIN_PA21F_TCC0_WO7 21L /**< \brief TCC0 signal: WO7 on PA21 mux F */
+#define MUX_PA21F_TCC0_WO7 5L
+#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
+#define PORT_PA21F_TCC0_WO7 (1ul << 21)
+#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7 5L
+#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7 (1ul << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0 4L
+#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0 (1ul << 6)
+#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0 4L
+#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0 (1ul << 10)
+#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0 4L
+#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0 (1ul << 30)
+#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1 4L
+#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1 (1ul << 7)
+#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1 4L
+#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1 (1ul << 11)
+#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1 4L
+#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1 (1ul << 31)
+#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2 5L
+#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2 (1ul << 8)
+#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2 5L
+#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2 (1ul << 24)
+#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3 5L
+#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3 (1ul << 9)
+#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3 5L
+#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3 (1ul << 25)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA12E_TCC2_WO0 12L /**< \brief TCC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TCC2_WO0 4L
+#define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
+#define PORT_PA12E_TCC2_WO0 (1ul << 12)
+#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0 4L
+#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0 (1ul << 16)
+#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0 4L
+#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0 (1ul << 0)
+#define PIN_PA13E_TCC2_WO1 13L /**< \brief TCC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TCC2_WO1 4L
+#define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
+#define PORT_PA13E_TCC2_WO1 (1ul << 13)
+#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1 4L
+#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1 (1ul << 17)
+#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1 4L
+#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1 (1ul << 1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0 4L
+#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0 (1ul << 18)
+#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0 4L
+#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0 (1ul << 14)
+#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1 4L
+#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1 (1ul << 19)
+#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1 4L
+#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1 (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0 4L
+#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0 (1ul << 22)
+#define PIN_PB08E_TC4_WO0 40L /**< \brief TC4 signal: WO0 on PB08 mux E */
+#define MUX_PB08E_TC4_WO0 4L
+#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
+#define PORT_PB08E_TC4_WO0 (1ul << 8)
+#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1 4L
+#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1 (1ul << 23)
+#define PIN_PB09E_TC4_WO1 41L /**< \brief TC4 signal: WO1 on PB09 mux E */
+#define MUX_PB09E_TC4_WO1 4L
+#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
+#define PORT_PB09E_TC4_WO1 (1ul << 9)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0 4L
+#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0 (1ul << 24)
+#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1 4L
+#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1 (1ul << 25)
+/* ========== PORT definition for TC6 peripheral ========== */
+#define PIN_PB02E_TC6_WO0 34L /**< \brief TC6 signal: WO0 on PB02 mux E */
+#define MUX_PB02E_TC6_WO0 4L
+#define PINMUX_PB02E_TC6_WO0 ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0)
+#define PORT_PB02E_TC6_WO0 (1ul << 2)
+#define PIN_PB03E_TC6_WO1 35L /**< \brief TC6 signal: WO1 on PB03 mux E */
+#define MUX_PB03E_TC6_WO1 4L
+#define PINMUX_PB03E_TC6_WO1 ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1)
+#define PORT_PB03E_TC6_WO1 (1ul << 3)
+/* ========== PORT definition for TC7 peripheral ========== */
+#define PIN_PA20E_TC7_WO0 20L /**< \brief TC7 signal: WO0 on PA20 mux E */
+#define MUX_PA20E_TC7_WO0 4L
+#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0)
+#define PORT_PA20E_TC7_WO0 (1ul << 20)
+#define PIN_PA21E_TC7_WO1 21L /**< \brief TC7 signal: WO1 on PA21 mux E */
+#define MUX_PA21E_TC7_WO1 4L
+#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1)
+#define PORT_PA21E_TC7_WO1 (1ul << 21)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0 1L
+#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0 (1ul << 2)
+#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1 1L
+#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1 (1ul << 3)
+#define PIN_PB08B_ADC_AIN2 40L /**< \brief ADC signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC_AIN2 1L
+#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
+#define PORT_PB08B_ADC_AIN2 (1ul << 8)
+#define PIN_PB09B_ADC_AIN3 41L /**< \brief ADC signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC_AIN3 1L
+#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
+#define PORT_PB09B_ADC_AIN3 (1ul << 9)
+#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4 1L
+#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4 (1ul << 4)
+#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5 1L
+#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5 (1ul << 5)
+#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6 1L
+#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6 (1ul << 6)
+#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7 1L
+#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7 (1ul << 7)
+#define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */
+#define MUX_PB02B_ADC_AIN10 1L
+#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
+#define PORT_PB02B_ADC_AIN10 (1ul << 2)
+#define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */
+#define MUX_PB03B_ADC_AIN11 1L
+#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
+#define PORT_PB03B_ADC_AIN11 (1ul << 3)
+#define PIN_PB04B_ADC_AIN12 36L /**< \brief ADC signal: AIN12 on PB04 mux B */
+#define MUX_PB04B_ADC_AIN12 1L
+#define PINMUX_PB04B_ADC_AIN12 ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12)
+#define PORT_PB04B_ADC_AIN12 (1ul << 4)
+#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16 1L
+#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16 (1ul << 8)
+#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17 1L
+#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17 (1ul << 9)
+#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18 1L
+#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18 (1ul << 10)
+#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19 1L
+#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19 (1ul << 11)
+#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP 1L
+#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP (1ul << 4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0 1L
+#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0 (1ul << 4)
+#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1 1L
+#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1 (1ul << 5)
+#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2 1L
+#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2 (1ul << 6)
+#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3 1L
+#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3 (1ul << 7)
+#define PIN_PA12H_AC_CMP0 12L /**< \brief AC signal: CMP0 on PA12 mux H */
+#define MUX_PA12H_AC_CMP0 7L
+#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
+#define PORT_PA12H_AC_CMP0 (1ul << 12)
+#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0 7L
+#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0 (1ul << 18)
+#define PIN_PA13H_AC_CMP1 13L /**< \brief AC signal: CMP1 on PA13 mux H */
+#define MUX_PA13H_AC_CMP1 7L
+#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
+#define PORT_PA13H_AC_CMP1 (1ul << 13)
+#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1 7L
+#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1 (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT 1L
+#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT (1ul << 2)
+#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP 1L
+#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP (1ul << 3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0 11L /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0 6L
+#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0 (1ul << 11)
+#define PIN_PA21G_I2S_FS0 21L /**< \brief I2S signal: FS0 on PA21 mux G */
+#define MUX_PA21G_I2S_FS0 6L
+#define PINMUX_PA21G_I2S_FS0 ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
+#define PORT_PA21G_I2S_FS0 (1ul << 21)
+#define PIN_PA09G_I2S_MCK0 9L /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0 6L
+#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0 (1ul << 9)
+#define PIN_PA10G_I2S_SCK0 10L /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0 6L
+#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0 (1ul << 10)
+#define PIN_PA20G_I2S_SCK0 20L /**< \brief I2S signal: SCK0 on PA20 mux G */
+#define MUX_PA20G_I2S_SCK0 6L
+#define PINMUX_PA20G_I2S_SCK0 ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
+#define PORT_PA20G_I2S_SCK0 (1ul << 20)
+#define PIN_PA07G_I2S_SD0 7L /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0 6L
+#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0 (1ul << 7)
+#define PIN_PA19G_I2S_SD0 19L /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0 6L
+#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0 (1ul << 19)
+#define PIN_PA08G_I2S_SD1 8L /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1 6L
+#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1 (1ul << 8)
+
+#endif /* _SAMD21G17AU_PIO_ */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/pio/samd21g18a.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/pio/samd21g18a.h
new file mode 100644
index 0000000000000000000000000000000000000000..31eaf97ef0bbd0ac28ec3704caa886b6fccfc92f
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/pio/samd21g18a.h
@@ -0,0 +1,915 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21G18A
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21G18A_PIO_
+#define _SAMD21G18A_PIO_
+
+#define PIN_PA00 0 /**< \brief Pin Number for PA00 */
+#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */
+#define PIN_PA01 1 /**< \brief Pin Number for PA01 */
+#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */
+#define PIN_PA02 2 /**< \brief Pin Number for PA02 */
+#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */
+#define PIN_PA03 3 /**< \brief Pin Number for PA03 */
+#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */
+#define PIN_PA04 4 /**< \brief Pin Number for PA04 */
+#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */
+#define PIN_PA05 5 /**< \brief Pin Number for PA05 */
+#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */
+#define PIN_PA06 6 /**< \brief Pin Number for PA06 */
+#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */
+#define PIN_PA07 7 /**< \brief Pin Number for PA07 */
+#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */
+#define PIN_PA08 8 /**< \brief Pin Number for PA08 */
+#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */
+#define PIN_PA09 9 /**< \brief Pin Number for PA09 */
+#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */
+#define PIN_PA10 10 /**< \brief Pin Number for PA10 */
+#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */
+#define PIN_PA11 11 /**< \brief Pin Number for PA11 */
+#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */
+#define PIN_PA12 12 /**< \brief Pin Number for PA12 */
+#define PORT_PA12 (1ul << 12) /**< \brief PORT Mask for PA12 */
+#define PIN_PA13 13 /**< \brief Pin Number for PA13 */
+#define PORT_PA13 (1ul << 13) /**< \brief PORT Mask for PA13 */
+#define PIN_PA14 14 /**< \brief Pin Number for PA14 */
+#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */
+#define PIN_PA15 15 /**< \brief Pin Number for PA15 */
+#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */
+#define PIN_PA16 16 /**< \brief Pin Number for PA16 */
+#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */
+#define PIN_PA17 17 /**< \brief Pin Number for PA17 */
+#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */
+#define PIN_PA18 18 /**< \brief Pin Number for PA18 */
+#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */
+#define PIN_PA19 19 /**< \brief Pin Number for PA19 */
+#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */
+#define PIN_PA20 20 /**< \brief Pin Number for PA20 */
+#define PORT_PA20 (1ul << 20) /**< \brief PORT Mask for PA20 */
+#define PIN_PA21 21 /**< \brief Pin Number for PA21 */
+#define PORT_PA21 (1ul << 21) /**< \brief PORT Mask for PA21 */
+#define PIN_PA22 22 /**< \brief Pin Number for PA22 */
+#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */
+#define PIN_PA23 23 /**< \brief Pin Number for PA23 */
+#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */
+#define PIN_PA24 24 /**< \brief Pin Number for PA24 */
+#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */
+#define PIN_PA25 25 /**< \brief Pin Number for PA25 */
+#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */
+#define PIN_PA27 27 /**< \brief Pin Number for PA27 */
+#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */
+#define PIN_PA28 28 /**< \brief Pin Number for PA28 */
+#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */
+#define PIN_PA30 30 /**< \brief Pin Number for PA30 */
+#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */
+#define PIN_PA31 31 /**< \brief Pin Number for PA31 */
+#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */
+#define PIN_PB02 34 /**< \brief Pin Number for PB02 */
+#define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */
+#define PIN_PB03 35 /**< \brief Pin Number for PB03 */
+#define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */
+#define PIN_PB08 40 /**< \brief Pin Number for PB08 */
+#define PORT_PB08 (1ul << 8) /**< \brief PORT Mask for PB08 */
+#define PIN_PB09 41 /**< \brief Pin Number for PB09 */
+#define PORT_PB09 (1ul << 9) /**< \brief PORT Mask for PB09 */
+#define PIN_PB10 42 /**< \brief Pin Number for PB10 */
+#define PORT_PB10 (1ul << 10) /**< \brief PORT Mask for PB10 */
+#define PIN_PB11 43 /**< \brief Pin Number for PB11 */
+#define PORT_PB11 (1ul << 11) /**< \brief PORT Mask for PB11 */
+#define PIN_PB22 54 /**< \brief Pin Number for PB22 */
+#define PORT_PB22 (1ul << 22) /**< \brief PORT Mask for PB22 */
+#define PIN_PB23 55 /**< \brief Pin Number for PB23 */
+#define PORT_PB23 (1ul << 23) /**< \brief PORT Mask for PB23 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PB22H_GCLK_IO0 54L /**< \brief GCLK signal: IO0 on PB22 mux H */
+#define MUX_PB22H_GCLK_IO0 7L
+#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
+#define PORT_PB22H_GCLK_IO0 (1ul << 22)
+#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0 7L
+#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0 (1ul << 14)
+#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0 7L
+#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0 (1ul << 27)
+#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0 7L
+#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0 (1ul << 28)
+#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0 7L
+#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0 (1ul << 30)
+#define PIN_PB23H_GCLK_IO1 55L /**< \brief GCLK signal: IO1 on PB23 mux H */
+#define MUX_PB23H_GCLK_IO1 7L
+#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
+#define PORT_PB23H_GCLK_IO1 (1ul << 23)
+#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1 7L
+#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1 (1ul << 15)
+#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2 7L
+#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2 (1ul << 16)
+#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3 7L
+#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3 (1ul << 17)
+#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4 7L
+#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4 (1ul << 10)
+#define PIN_PA20H_GCLK_IO4 20L /**< \brief GCLK signal: IO4 on PA20 mux H */
+#define MUX_PA20H_GCLK_IO4 7L
+#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
+#define PORT_PA20H_GCLK_IO4 (1ul << 20)
+#define PIN_PB10H_GCLK_IO4 42L /**< \brief GCLK signal: IO4 on PB10 mux H */
+#define MUX_PB10H_GCLK_IO4 7L
+#define PINMUX_PB10H_GCLK_IO4 ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
+#define PORT_PB10H_GCLK_IO4 (1ul << 10)
+#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5 7L
+#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5 (1ul << 11)
+#define PIN_PA21H_GCLK_IO5 21L /**< \brief GCLK signal: IO5 on PA21 mux H */
+#define MUX_PA21H_GCLK_IO5 7L
+#define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
+#define PORT_PA21H_GCLK_IO5 (1ul << 21)
+#define PIN_PB11H_GCLK_IO5 43L /**< \brief GCLK signal: IO5 on PB11 mux H */
+#define MUX_PB11H_GCLK_IO5 7L
+#define PINMUX_PB11H_GCLK_IO5 ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
+#define PORT_PB11H_GCLK_IO5 (1ul << 11)
+#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6 7L
+#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6 (1ul << 22)
+#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7 7L
+#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7 (1ul << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0 0L
+#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0 (1ul << 16)
+#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0 0L
+#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0 (1ul << 0)
+#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1 0L
+#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1 (1ul << 17)
+#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1 0L
+#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1 (1ul << 1)
+#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2 0L
+#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2 (1ul << 18)
+#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2 0L
+#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2 (1ul << 2)
+#define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2 0L
+#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2 (1ul << 2)
+#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3 0L
+#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3 (1ul << 3)
+#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3 0L
+#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3 (1ul << 19)
+#define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3 0L
+#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3 (1ul << 3)
+#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4 0L
+#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4 (1ul << 4)
+#define PIN_PA20A_EIC_EXTINT4 20L /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4 0L
+#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4 (1ul << 20)
+#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5 0L
+#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5 (1ul << 5)
+#define PIN_PA21A_EIC_EXTINT5 21L /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5 0L
+#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5 (1ul << 21)
+#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6 0L
+#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6 (1ul << 6)
+#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6 0L
+#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6 (1ul << 22)
+#define PIN_PB22A_EIC_EXTINT6 54L /**< \brief EIC signal: EXTINT6 on PB22 mux A */
+#define MUX_PB22A_EIC_EXTINT6 0L
+#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
+#define PORT_PB22A_EIC_EXTINT6 (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7 0L
+#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7 (1ul << 7)
+#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7 0L
+#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7 (1ul << 23)
+#define PIN_PB23A_EIC_EXTINT7 55L /**< \brief EIC signal: EXTINT7 on PB23 mux A */
+#define MUX_PB23A_EIC_EXTINT7 0L
+#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
+#define PORT_PB23A_EIC_EXTINT7 (1ul << 23)
+#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8 0L
+#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8 (1ul << 28)
+#define PIN_PB08A_EIC_EXTINT8 40L /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8 0L
+#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8 (1ul << 8)
+#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9 0L
+#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9 (1ul << 9)
+#define PIN_PB09A_EIC_EXTINT9 41L /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9 0L
+#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9 (1ul << 9)
+#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10 0L
+#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10 (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10 0L
+#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10 (1ul << 30)
+#define PIN_PB10A_EIC_EXTINT10 42L /**< \brief EIC signal: EXTINT10 on PB10 mux A */
+#define MUX_PB10A_EIC_EXTINT10 0L
+#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
+#define PORT_PB10A_EIC_EXTINT10 (1ul << 10)
+#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11 0L
+#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11 (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11 0L
+#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11 (1ul << 31)
+#define PIN_PB11A_EIC_EXTINT11 43L /**< \brief EIC signal: EXTINT11 on PB11 mux A */
+#define MUX_PB11A_EIC_EXTINT11 0L
+#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
+#define PORT_PB11A_EIC_EXTINT11 (1ul << 11)
+#define PIN_PA12A_EIC_EXTINT12 12L /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12 0L
+#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12 (1ul << 12)
+#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12 0L
+#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12 (1ul << 24)
+#define PIN_PA13A_EIC_EXTINT13 13L /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13 0L
+#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13 (1ul << 13)
+#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13 0L
+#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13 (1ul << 25)
+#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14 0L
+#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14 (1ul << 14)
+#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15 0L
+#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15 (1ul << 15)
+#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15 0L
+#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15 (1ul << 27)
+#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI 0L
+#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI (1ul << 8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM 6L
+#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM (1ul << 24)
+#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP 6L
+#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP (1ul << 25)
+#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ 6L
+#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0 3L
+#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4)
+#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0 2L
+#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8)
+#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1 3L
+#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5)
+#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1 2L
+#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9)
+#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2 3L
+#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6)
+#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2 2L
+#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3 3L
+#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7)
+#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3 2L
+#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0 2L
+#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16)
+#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0 3L
+#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0)
+#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1 2L
+#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17)
+#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1 3L
+#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1)
+#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2 3L
+#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2 2L
+#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3 3L
+#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3 2L
+#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0 3L
+#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8)
+#define PIN_PA12C_SERCOM2_PAD0 12L /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0 2L
+#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0 (1ul << 12)
+#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1 3L
+#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9)
+#define PIN_PA13C_SERCOM2_PAD1 13L /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1 2L
+#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1 (1ul << 13)
+#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2 3L
+#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2 2L
+#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3 3L
+#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3 2L
+#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0 3L
+#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0 2L
+#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1 3L
+#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1 2L
+#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2 3L
+#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18)
+#define PIN_PA20D_SERCOM3_PAD2 20L /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2 3L
+#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2 (1ul << 20)
+#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2 2L
+#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3 3L
+#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19)
+#define PIN_PA21D_SERCOM3_PAD3 21L /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3 3L
+#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3 (1ul << 21)
+#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3 2L
+#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA12D_SERCOM4_PAD0 12L /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD0 3L
+#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
+#define PORT_PA12D_SERCOM4_PAD0 (1ul << 12)
+#define PIN_PB08D_SERCOM4_PAD0 40L /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0 3L
+#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0 (1ul << 8)
+#define PIN_PA13D_SERCOM4_PAD1 13L /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD1 3L
+#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
+#define PORT_PA13D_SERCOM4_PAD1 (1ul << 13)
+#define PIN_PB09D_SERCOM4_PAD1 41L /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1 3L
+#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1 (1ul << 9)
+#define PIN_PA14D_SERCOM4_PAD2 14L /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2 3L
+#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2 (1ul << 14)
+#define PIN_PB10D_SERCOM4_PAD2 42L /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
+#define MUX_PB10D_SERCOM4_PAD2 3L
+#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
+#define PORT_PB10D_SERCOM4_PAD2 (1ul << 10)
+#define PIN_PA15D_SERCOM4_PAD3 15L /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3 3L
+#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3 (1ul << 15)
+#define PIN_PB11D_SERCOM4_PAD3 43L /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
+#define MUX_PB11D_SERCOM4_PAD3 3L
+#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
+#define PORT_PB11D_SERCOM4_PAD3 (1ul << 11)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PA22D_SERCOM5_PAD0 22L /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD0 3L
+#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
+#define PORT_PA22D_SERCOM5_PAD0 (1ul << 22)
+#define PIN_PB02D_SERCOM5_PAD0 34L /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0 3L
+#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0 (1ul << 2)
+#define PIN_PA23D_SERCOM5_PAD1 23L /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD1 3L
+#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
+#define PORT_PA23D_SERCOM5_PAD1 (1ul << 23)
+#define PIN_PB03D_SERCOM5_PAD1 35L /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1 3L
+#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1 (1ul << 3)
+#define PIN_PA24D_SERCOM5_PAD2 24L /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2 3L
+#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2 (1ul << 24)
+#define PIN_PB22D_SERCOM5_PAD2 54L /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
+#define MUX_PB22D_SERCOM5_PAD2 3L
+#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
+#define PORT_PB22D_SERCOM5_PAD2 (1ul << 22)
+#define PIN_PA20C_SERCOM5_PAD2 20L /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2 2L
+#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2 (1ul << 20)
+#define PIN_PA25D_SERCOM5_PAD3 25L /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3 3L
+#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3 (1ul << 25)
+#define PIN_PB23D_SERCOM5_PAD3 55L /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
+#define MUX_PB23D_SERCOM5_PAD3 3L
+#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
+#define PORT_PB23D_SERCOM5_PAD3 (1ul << 23)
+#define PIN_PA21C_SERCOM5_PAD3 21L /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3 2L
+#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3 (1ul << 21)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0 4L
+#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0 (1ul << 4)
+#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0 4L
+#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0 (1ul << 8)
+#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1 4L
+#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1 (1ul << 5)
+#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1 4L
+#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1 (1ul << 9)
+#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2 5L
+#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2 (1ul << 10)
+#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2 5L
+#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2 (1ul << 18)
+#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3 5L
+#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3 (1ul << 11)
+#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3 5L
+#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3 (1ul << 19)
+#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4 5L
+#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4 (1ul << 14)
+#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4 5L
+#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4 (1ul << 22)
+#define PIN_PB10F_TCC0_WO4 42L /**< \brief TCC0 signal: WO4 on PB10 mux F */
+#define MUX_PB10F_TCC0_WO4 5L
+#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
+#define PORT_PB10F_TCC0_WO4 (1ul << 10)
+#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5 5L
+#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5 (1ul << 15)
+#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5 5L
+#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5 (1ul << 23)
+#define PIN_PB11F_TCC0_WO5 43L /**< \brief TCC0 signal: WO5 on PB11 mux F */
+#define MUX_PB11F_TCC0_WO5 5L
+#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
+#define PORT_PB11F_TCC0_WO5 (1ul << 11)
+#define PIN_PA12F_TCC0_WO6 12L /**< \brief TCC0 signal: WO6 on PA12 mux F */
+#define MUX_PA12F_TCC0_WO6 5L
+#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
+#define PORT_PA12F_TCC0_WO6 (1ul << 12)
+#define PIN_PA20F_TCC0_WO6 20L /**< \brief TCC0 signal: WO6 on PA20 mux F */
+#define MUX_PA20F_TCC0_WO6 5L
+#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
+#define PORT_PA20F_TCC0_WO6 (1ul << 20)
+#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6 5L
+#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6 (1ul << 16)
+#define PIN_PA13F_TCC0_WO7 13L /**< \brief TCC0 signal: WO7 on PA13 mux F */
+#define MUX_PA13F_TCC0_WO7 5L
+#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
+#define PORT_PA13F_TCC0_WO7 (1ul << 13)
+#define PIN_PA21F_TCC0_WO7 21L /**< \brief TCC0 signal: WO7 on PA21 mux F */
+#define MUX_PA21F_TCC0_WO7 5L
+#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
+#define PORT_PA21F_TCC0_WO7 (1ul << 21)
+#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7 5L
+#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7 (1ul << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0 4L
+#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0 (1ul << 6)
+#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0 4L
+#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0 (1ul << 10)
+#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0 4L
+#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0 (1ul << 30)
+#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1 4L
+#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1 (1ul << 7)
+#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1 4L
+#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1 (1ul << 11)
+#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1 4L
+#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1 (1ul << 31)
+#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2 5L
+#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2 (1ul << 8)
+#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2 5L
+#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2 (1ul << 24)
+#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3 5L
+#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3 (1ul << 9)
+#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3 5L
+#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3 (1ul << 25)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA12E_TCC2_WO0 12L /**< \brief TCC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TCC2_WO0 4L
+#define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
+#define PORT_PA12E_TCC2_WO0 (1ul << 12)
+#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0 4L
+#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0 (1ul << 16)
+#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0 4L
+#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0 (1ul << 0)
+#define PIN_PA13E_TCC2_WO1 13L /**< \brief TCC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TCC2_WO1 4L
+#define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
+#define PORT_PA13E_TCC2_WO1 (1ul << 13)
+#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1 4L
+#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1 (1ul << 17)
+#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1 4L
+#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1 (1ul << 1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0 4L
+#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0 (1ul << 18)
+#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0 4L
+#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0 (1ul << 14)
+#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1 4L
+#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1 (1ul << 19)
+#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1 4L
+#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1 (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0 4L
+#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0 (1ul << 22)
+#define PIN_PB08E_TC4_WO0 40L /**< \brief TC4 signal: WO0 on PB08 mux E */
+#define MUX_PB08E_TC4_WO0 4L
+#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
+#define PORT_PB08E_TC4_WO0 (1ul << 8)
+#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1 4L
+#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1 (1ul << 23)
+#define PIN_PB09E_TC4_WO1 41L /**< \brief TC4 signal: WO1 on PB09 mux E */
+#define MUX_PB09E_TC4_WO1 4L
+#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
+#define PORT_PB09E_TC4_WO1 (1ul << 9)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0 4L
+#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0 (1ul << 24)
+#define PIN_PB10E_TC5_WO0 42L /**< \brief TC5 signal: WO0 on PB10 mux E */
+#define MUX_PB10E_TC5_WO0 4L
+#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
+#define PORT_PB10E_TC5_WO0 (1ul << 10)
+#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1 4L
+#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1 (1ul << 25)
+#define PIN_PB11E_TC5_WO1 43L /**< \brief TC5 signal: WO1 on PB11 mux E */
+#define MUX_PB11E_TC5_WO1 4L
+#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
+#define PORT_PB11E_TC5_WO1 (1ul << 11)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0 1L
+#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0 (1ul << 2)
+#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1 1L
+#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1 (1ul << 3)
+#define PIN_PB08B_ADC_AIN2 40L /**< \brief ADC signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC_AIN2 1L
+#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
+#define PORT_PB08B_ADC_AIN2 (1ul << 8)
+#define PIN_PB09B_ADC_AIN3 41L /**< \brief ADC signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC_AIN3 1L
+#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
+#define PORT_PB09B_ADC_AIN3 (1ul << 9)
+#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4 1L
+#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4 (1ul << 4)
+#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5 1L
+#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5 (1ul << 5)
+#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6 1L
+#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6 (1ul << 6)
+#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7 1L
+#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7 (1ul << 7)
+#define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */
+#define MUX_PB02B_ADC_AIN10 1L
+#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
+#define PORT_PB02B_ADC_AIN10 (1ul << 2)
+#define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */
+#define MUX_PB03B_ADC_AIN11 1L
+#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
+#define PORT_PB03B_ADC_AIN11 (1ul << 3)
+#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16 1L
+#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16 (1ul << 8)
+#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17 1L
+#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17 (1ul << 9)
+#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18 1L
+#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18 (1ul << 10)
+#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19 1L
+#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19 (1ul << 11)
+#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP 1L
+#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP (1ul << 4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0 1L
+#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0 (1ul << 4)
+#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1 1L
+#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1 (1ul << 5)
+#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2 1L
+#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2 (1ul << 6)
+#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3 1L
+#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3 (1ul << 7)
+#define PIN_PA12H_AC_CMP0 12L /**< \brief AC signal: CMP0 on PA12 mux H */
+#define MUX_PA12H_AC_CMP0 7L
+#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
+#define PORT_PA12H_AC_CMP0 (1ul << 12)
+#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0 7L
+#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0 (1ul << 18)
+#define PIN_PA13H_AC_CMP1 13L /**< \brief AC signal: CMP1 on PA13 mux H */
+#define MUX_PA13H_AC_CMP1 7L
+#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
+#define PORT_PA13H_AC_CMP1 (1ul << 13)
+#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1 7L
+#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1 (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT 1L
+#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT (1ul << 2)
+#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP 1L
+#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP (1ul << 3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0 11L /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0 6L
+#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0 (1ul << 11)
+#define PIN_PA21G_I2S_FS0 21L /**< \brief I2S signal: FS0 on PA21 mux G */
+#define MUX_PA21G_I2S_FS0 6L
+#define PINMUX_PA21G_I2S_FS0 ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
+#define PORT_PA21G_I2S_FS0 (1ul << 21)
+#define PIN_PA09G_I2S_MCK0 9L /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0 6L
+#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0 (1ul << 9)
+#define PIN_PB10G_I2S_MCK1 42L /**< \brief I2S signal: MCK1 on PB10 mux G */
+#define MUX_PB10G_I2S_MCK1 6L
+#define PINMUX_PB10G_I2S_MCK1 ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1)
+#define PORT_PB10G_I2S_MCK1 (1ul << 10)
+#define PIN_PA10G_I2S_SCK0 10L /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0 6L
+#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0 (1ul << 10)
+#define PIN_PA20G_I2S_SCK0 20L /**< \brief I2S signal: SCK0 on PA20 mux G */
+#define MUX_PA20G_I2S_SCK0 6L
+#define PINMUX_PA20G_I2S_SCK0 ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
+#define PORT_PA20G_I2S_SCK0 (1ul << 20)
+#define PIN_PB11G_I2S_SCK1 43L /**< \brief I2S signal: SCK1 on PB11 mux G */
+#define MUX_PB11G_I2S_SCK1 6L
+#define PINMUX_PB11G_I2S_SCK1 ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1)
+#define PORT_PB11G_I2S_SCK1 (1ul << 11)
+#define PIN_PA07G_I2S_SD0 7L /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0 6L
+#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0 (1ul << 7)
+#define PIN_PA19G_I2S_SD0 19L /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0 6L
+#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0 (1ul << 19)
+#define PIN_PA08G_I2S_SD1 8L /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1 6L
+#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1 (1ul << 8)
+
+#endif /* _SAMD21G18A_PIO_ */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/pio/samd21g18au.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/pio/samd21g18au.h
new file mode 100644
index 0000000000000000000000000000000000000000..cb4d9cd5020409ef150daecd52e07f592f0ae54a
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/pio/samd21g18au.h
@@ -0,0 +1,863 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21G18AU
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21G18AU_PIO_
+#define _SAMD21G18AU_PIO_
+
+#define PIN_PA00 0 /**< \brief Pin Number for PA00 */
+#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */
+#define PIN_PA01 1 /**< \brief Pin Number for PA01 */
+#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */
+#define PIN_PA02 2 /**< \brief Pin Number for PA02 */
+#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */
+#define PIN_PA03 3 /**< \brief Pin Number for PA03 */
+#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */
+#define PIN_PA04 4 /**< \brief Pin Number for PA04 */
+#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */
+#define PIN_PA05 5 /**< \brief Pin Number for PA05 */
+#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */
+#define PIN_PA06 6 /**< \brief Pin Number for PA06 */
+#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */
+#define PIN_PA07 7 /**< \brief Pin Number for PA07 */
+#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */
+#define PIN_PA08 8 /**< \brief Pin Number for PA08 */
+#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */
+#define PIN_PA09 9 /**< \brief Pin Number for PA09 */
+#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */
+#define PIN_PA10 10 /**< \brief Pin Number for PA10 */
+#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */
+#define PIN_PA11 11 /**< \brief Pin Number for PA11 */
+#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */
+#define PIN_PA12 12 /**< \brief Pin Number for PA12 */
+#define PORT_PA12 (1ul << 12) /**< \brief PORT Mask for PA12 */
+#define PIN_PA13 13 /**< \brief Pin Number for PA13 */
+#define PORT_PA13 (1ul << 13) /**< \brief PORT Mask for PA13 */
+#define PIN_PA14 14 /**< \brief Pin Number for PA14 */
+#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */
+#define PIN_PA15 15 /**< \brief Pin Number for PA15 */
+#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */
+#define PIN_PA16 16 /**< \brief Pin Number for PA16 */
+#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */
+#define PIN_PA17 17 /**< \brief Pin Number for PA17 */
+#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */
+#define PIN_PA18 18 /**< \brief Pin Number for PA18 */
+#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */
+#define PIN_PA19 19 /**< \brief Pin Number for PA19 */
+#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */
+#define PIN_PA20 20 /**< \brief Pin Number for PA20 */
+#define PORT_PA20 (1ul << 20) /**< \brief PORT Mask for PA20 */
+#define PIN_PA21 21 /**< \brief Pin Number for PA21 */
+#define PORT_PA21 (1ul << 21) /**< \brief PORT Mask for PA21 */
+#define PIN_PA22 22 /**< \brief Pin Number for PA22 */
+#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */
+#define PIN_PA23 23 /**< \brief Pin Number for PA23 */
+#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */
+#define PIN_PA24 24 /**< \brief Pin Number for PA24 */
+#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */
+#define PIN_PA25 25 /**< \brief Pin Number for PA25 */
+#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */
+#define PIN_PA27 27 /**< \brief Pin Number for PA27 */
+#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */
+#define PIN_PA28 28 /**< \brief Pin Number for PA28 */
+#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */
+#define PIN_PA30 30 /**< \brief Pin Number for PA30 */
+#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */
+#define PIN_PA31 31 /**< \brief Pin Number for PA31 */
+#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */
+#define PIN_PB02 34 /**< \brief Pin Number for PB02 */
+#define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */
+#define PIN_PB03 35 /**< \brief Pin Number for PB03 */
+#define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */
+#define PIN_PB04 36 /**< \brief Pin Number for PB04 */
+#define PORT_PB04 (1ul << 4) /**< \brief PORT Mask for PB04 */
+#define PIN_PB08 40 /**< \brief Pin Number for PB08 */
+#define PORT_PB08 (1ul << 8) /**< \brief PORT Mask for PB08 */
+#define PIN_PB09 41 /**< \brief Pin Number for PB09 */
+#define PORT_PB09 (1ul << 9) /**< \brief PORT Mask for PB09 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0 7L
+#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0 (1ul << 14)
+#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0 7L
+#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0 (1ul << 27)
+#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0 7L
+#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0 (1ul << 28)
+#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0 7L
+#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0 (1ul << 30)
+#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1 7L
+#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1 (1ul << 15)
+#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2 7L
+#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2 (1ul << 16)
+#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3 7L
+#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3 (1ul << 17)
+#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4 7L
+#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4 (1ul << 10)
+#define PIN_PA20H_GCLK_IO4 20L /**< \brief GCLK signal: IO4 on PA20 mux H */
+#define MUX_PA20H_GCLK_IO4 7L
+#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
+#define PORT_PA20H_GCLK_IO4 (1ul << 20)
+#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5 7L
+#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5 (1ul << 11)
+#define PIN_PA21H_GCLK_IO5 21L /**< \brief GCLK signal: IO5 on PA21 mux H */
+#define MUX_PA21H_GCLK_IO5 7L
+#define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
+#define PORT_PA21H_GCLK_IO5 (1ul << 21)
+#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6 7L
+#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6 (1ul << 22)
+#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7 7L
+#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7 (1ul << 23)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0 0L
+#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0 (1ul << 16)
+#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0 0L
+#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0 (1ul << 0)
+#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1 0L
+#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1 (1ul << 17)
+#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1 0L
+#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1 (1ul << 1)
+#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2 0L
+#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2 (1ul << 18)
+#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2 0L
+#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2 (1ul << 2)
+#define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2 0L
+#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2 (1ul << 2)
+#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3 0L
+#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3 (1ul << 3)
+#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3 0L
+#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3 (1ul << 19)
+#define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3 0L
+#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3 (1ul << 3)
+#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4 0L
+#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4 (1ul << 4)
+#define PIN_PA20A_EIC_EXTINT4 20L /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4 0L
+#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4 (1ul << 20)
+#define PIN_PB04A_EIC_EXTINT4 36L /**< \brief EIC signal: EXTINT4 on PB04 mux A */
+#define MUX_PB04A_EIC_EXTINT4 0L
+#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
+#define PORT_PB04A_EIC_EXTINT4 (1ul << 4)
+#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5 0L
+#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5 (1ul << 5)
+#define PIN_PA21A_EIC_EXTINT5 21L /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5 0L
+#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5 (1ul << 21)
+#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6 0L
+#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6 (1ul << 6)
+#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6 0L
+#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6 (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7 0L
+#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7 (1ul << 7)
+#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7 0L
+#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7 (1ul << 23)
+#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8 0L
+#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8 (1ul << 28)
+#define PIN_PB08A_EIC_EXTINT8 40L /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8 0L
+#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8 (1ul << 8)
+#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9 0L
+#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9 (1ul << 9)
+#define PIN_PB09A_EIC_EXTINT9 41L /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9 0L
+#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9 (1ul << 9)
+#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10 0L
+#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10 (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10 0L
+#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10 (1ul << 30)
+#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11 0L
+#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11 (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11 0L
+#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11 (1ul << 31)
+#define PIN_PA12A_EIC_EXTINT12 12L /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12 0L
+#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12 (1ul << 12)
+#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12 0L
+#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12 (1ul << 24)
+#define PIN_PA13A_EIC_EXTINT13 13L /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13 0L
+#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13 (1ul << 13)
+#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13 0L
+#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13 (1ul << 25)
+#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14 0L
+#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14 (1ul << 14)
+#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15 0L
+#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15 (1ul << 15)
+#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15 0L
+#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15 (1ul << 27)
+#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI 0L
+#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI (1ul << 8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM 6L
+#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM (1ul << 24)
+#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP 6L
+#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP (1ul << 25)
+#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ 6L
+#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0 3L
+#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4)
+#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0 2L
+#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8)
+#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1 3L
+#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5)
+#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1 2L
+#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9)
+#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2 3L
+#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6)
+#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2 2L
+#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3 3L
+#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7)
+#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3 2L
+#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0 2L
+#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16)
+#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0 3L
+#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0)
+#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1 2L
+#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17)
+#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1 3L
+#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1)
+#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2 3L
+#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2 2L
+#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3 3L
+#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3 2L
+#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0 3L
+#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8)
+#define PIN_PA12C_SERCOM2_PAD0 12L /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0 2L
+#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0 (1ul << 12)
+#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1 3L
+#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9)
+#define PIN_PA13C_SERCOM2_PAD1 13L /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1 2L
+#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1 (1ul << 13)
+#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2 3L
+#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2 2L
+#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3 3L
+#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3 2L
+#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0 3L
+#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0 2L
+#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1 3L
+#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1 2L
+#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2 3L
+#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18)
+#define PIN_PA20D_SERCOM3_PAD2 20L /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2 3L
+#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2 (1ul << 20)
+#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2 2L
+#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3 3L
+#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19)
+#define PIN_PA21D_SERCOM3_PAD3 21L /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3 3L
+#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3 (1ul << 21)
+#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3 2L
+#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA12D_SERCOM4_PAD0 12L /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD0 3L
+#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
+#define PORT_PA12D_SERCOM4_PAD0 (1ul << 12)
+#define PIN_PB08D_SERCOM4_PAD0 40L /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0 3L
+#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0 (1ul << 8)
+#define PIN_PA13D_SERCOM4_PAD1 13L /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD1 3L
+#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
+#define PORT_PA13D_SERCOM4_PAD1 (1ul << 13)
+#define PIN_PB09D_SERCOM4_PAD1 41L /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1 3L
+#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1 (1ul << 9)
+#define PIN_PA14D_SERCOM4_PAD2 14L /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2 3L
+#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2 (1ul << 14)
+#define PIN_PA15D_SERCOM4_PAD3 15L /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3 3L
+#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3 (1ul << 15)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PA22D_SERCOM5_PAD0 22L /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD0 3L
+#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
+#define PORT_PA22D_SERCOM5_PAD0 (1ul << 22)
+#define PIN_PB02D_SERCOM5_PAD0 34L /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0 3L
+#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0 (1ul << 2)
+#define PIN_PA23D_SERCOM5_PAD1 23L /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD1 3L
+#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
+#define PORT_PA23D_SERCOM5_PAD1 (1ul << 23)
+#define PIN_PB03D_SERCOM5_PAD1 35L /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1 3L
+#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1 (1ul << 3)
+#define PIN_PA24D_SERCOM5_PAD2 24L /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2 3L
+#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2 (1ul << 24)
+#define PIN_PA20C_SERCOM5_PAD2 20L /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2 2L
+#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2 (1ul << 20)
+#define PIN_PA25D_SERCOM5_PAD3 25L /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3 3L
+#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3 (1ul << 25)
+#define PIN_PA21C_SERCOM5_PAD3 21L /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3 2L
+#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3 (1ul << 21)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0 4L
+#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0 (1ul << 4)
+#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0 4L
+#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0 (1ul << 8)
+#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1 4L
+#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1 (1ul << 5)
+#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1 4L
+#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1 (1ul << 9)
+#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2 5L
+#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2 (1ul << 10)
+#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2 5L
+#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2 (1ul << 18)
+#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3 5L
+#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3 (1ul << 11)
+#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3 5L
+#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3 (1ul << 19)
+#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4 5L
+#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4 (1ul << 14)
+#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4 5L
+#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4 (1ul << 22)
+#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5 5L
+#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5 (1ul << 15)
+#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5 5L
+#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5 (1ul << 23)
+#define PIN_PA12F_TCC0_WO6 12L /**< \brief TCC0 signal: WO6 on PA12 mux F */
+#define MUX_PA12F_TCC0_WO6 5L
+#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
+#define PORT_PA12F_TCC0_WO6 (1ul << 12)
+#define PIN_PA20F_TCC0_WO6 20L /**< \brief TCC0 signal: WO6 on PA20 mux F */
+#define MUX_PA20F_TCC0_WO6 5L
+#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
+#define PORT_PA20F_TCC0_WO6 (1ul << 20)
+#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6 5L
+#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6 (1ul << 16)
+#define PIN_PA13F_TCC0_WO7 13L /**< \brief TCC0 signal: WO7 on PA13 mux F */
+#define MUX_PA13F_TCC0_WO7 5L
+#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
+#define PORT_PA13F_TCC0_WO7 (1ul << 13)
+#define PIN_PA21F_TCC0_WO7 21L /**< \brief TCC0 signal: WO7 on PA21 mux F */
+#define MUX_PA21F_TCC0_WO7 5L
+#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
+#define PORT_PA21F_TCC0_WO7 (1ul << 21)
+#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7 5L
+#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7 (1ul << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0 4L
+#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0 (1ul << 6)
+#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0 4L
+#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0 (1ul << 10)
+#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0 4L
+#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0 (1ul << 30)
+#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1 4L
+#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1 (1ul << 7)
+#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1 4L
+#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1 (1ul << 11)
+#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1 4L
+#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1 (1ul << 31)
+#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2 5L
+#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2 (1ul << 8)
+#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2 5L
+#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2 (1ul << 24)
+#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3 5L
+#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3 (1ul << 9)
+#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3 5L
+#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3 (1ul << 25)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA12E_TCC2_WO0 12L /**< \brief TCC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TCC2_WO0 4L
+#define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
+#define PORT_PA12E_TCC2_WO0 (1ul << 12)
+#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0 4L
+#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0 (1ul << 16)
+#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0 4L
+#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0 (1ul << 0)
+#define PIN_PA13E_TCC2_WO1 13L /**< \brief TCC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TCC2_WO1 4L
+#define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
+#define PORT_PA13E_TCC2_WO1 (1ul << 13)
+#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1 4L
+#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1 (1ul << 17)
+#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1 4L
+#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1 (1ul << 1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0 4L
+#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0 (1ul << 18)
+#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0 4L
+#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0 (1ul << 14)
+#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1 4L
+#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1 (1ul << 19)
+#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1 4L
+#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1 (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0 4L
+#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0 (1ul << 22)
+#define PIN_PB08E_TC4_WO0 40L /**< \brief TC4 signal: WO0 on PB08 mux E */
+#define MUX_PB08E_TC4_WO0 4L
+#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
+#define PORT_PB08E_TC4_WO0 (1ul << 8)
+#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1 4L
+#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1 (1ul << 23)
+#define PIN_PB09E_TC4_WO1 41L /**< \brief TC4 signal: WO1 on PB09 mux E */
+#define MUX_PB09E_TC4_WO1 4L
+#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
+#define PORT_PB09E_TC4_WO1 (1ul << 9)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0 4L
+#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0 (1ul << 24)
+#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1 4L
+#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1 (1ul << 25)
+/* ========== PORT definition for TC6 peripheral ========== */
+#define PIN_PB02E_TC6_WO0 34L /**< \brief TC6 signal: WO0 on PB02 mux E */
+#define MUX_PB02E_TC6_WO0 4L
+#define PINMUX_PB02E_TC6_WO0 ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0)
+#define PORT_PB02E_TC6_WO0 (1ul << 2)
+#define PIN_PB03E_TC6_WO1 35L /**< \brief TC6 signal: WO1 on PB03 mux E */
+#define MUX_PB03E_TC6_WO1 4L
+#define PINMUX_PB03E_TC6_WO1 ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1)
+#define PORT_PB03E_TC6_WO1 (1ul << 3)
+/* ========== PORT definition for TC7 peripheral ========== */
+#define PIN_PA20E_TC7_WO0 20L /**< \brief TC7 signal: WO0 on PA20 mux E */
+#define MUX_PA20E_TC7_WO0 4L
+#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0)
+#define PORT_PA20E_TC7_WO0 (1ul << 20)
+#define PIN_PA21E_TC7_WO1 21L /**< \brief TC7 signal: WO1 on PA21 mux E */
+#define MUX_PA21E_TC7_WO1 4L
+#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1)
+#define PORT_PA21E_TC7_WO1 (1ul << 21)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0 1L
+#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0 (1ul << 2)
+#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1 1L
+#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1 (1ul << 3)
+#define PIN_PB08B_ADC_AIN2 40L /**< \brief ADC signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC_AIN2 1L
+#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
+#define PORT_PB08B_ADC_AIN2 (1ul << 8)
+#define PIN_PB09B_ADC_AIN3 41L /**< \brief ADC signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC_AIN3 1L
+#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
+#define PORT_PB09B_ADC_AIN3 (1ul << 9)
+#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4 1L
+#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4 (1ul << 4)
+#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5 1L
+#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5 (1ul << 5)
+#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6 1L
+#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6 (1ul << 6)
+#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7 1L
+#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7 (1ul << 7)
+#define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */
+#define MUX_PB02B_ADC_AIN10 1L
+#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
+#define PORT_PB02B_ADC_AIN10 (1ul << 2)
+#define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */
+#define MUX_PB03B_ADC_AIN11 1L
+#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
+#define PORT_PB03B_ADC_AIN11 (1ul << 3)
+#define PIN_PB04B_ADC_AIN12 36L /**< \brief ADC signal: AIN12 on PB04 mux B */
+#define MUX_PB04B_ADC_AIN12 1L
+#define PINMUX_PB04B_ADC_AIN12 ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12)
+#define PORT_PB04B_ADC_AIN12 (1ul << 4)
+#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16 1L
+#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16 (1ul << 8)
+#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17 1L
+#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17 (1ul << 9)
+#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18 1L
+#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18 (1ul << 10)
+#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19 1L
+#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19 (1ul << 11)
+#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP 1L
+#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP (1ul << 4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0 1L
+#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0 (1ul << 4)
+#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1 1L
+#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1 (1ul << 5)
+#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2 1L
+#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2 (1ul << 6)
+#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3 1L
+#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3 (1ul << 7)
+#define PIN_PA12H_AC_CMP0 12L /**< \brief AC signal: CMP0 on PA12 mux H */
+#define MUX_PA12H_AC_CMP0 7L
+#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
+#define PORT_PA12H_AC_CMP0 (1ul << 12)
+#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0 7L
+#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0 (1ul << 18)
+#define PIN_PA13H_AC_CMP1 13L /**< \brief AC signal: CMP1 on PA13 mux H */
+#define MUX_PA13H_AC_CMP1 7L
+#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
+#define PORT_PA13H_AC_CMP1 (1ul << 13)
+#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1 7L
+#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1 (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT 1L
+#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT (1ul << 2)
+#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP 1L
+#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP (1ul << 3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0 11L /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0 6L
+#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0 (1ul << 11)
+#define PIN_PA21G_I2S_FS0 21L /**< \brief I2S signal: FS0 on PA21 mux G */
+#define MUX_PA21G_I2S_FS0 6L
+#define PINMUX_PA21G_I2S_FS0 ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
+#define PORT_PA21G_I2S_FS0 (1ul << 21)
+#define PIN_PA09G_I2S_MCK0 9L /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0 6L
+#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0 (1ul << 9)
+#define PIN_PA10G_I2S_SCK0 10L /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0 6L
+#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0 (1ul << 10)
+#define PIN_PA20G_I2S_SCK0 20L /**< \brief I2S signal: SCK0 on PA20 mux G */
+#define MUX_PA20G_I2S_SCK0 6L
+#define PINMUX_PA20G_I2S_SCK0 ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
+#define PORT_PA20G_I2S_SCK0 (1ul << 20)
+#define PIN_PA07G_I2S_SD0 7L /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0 6L
+#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0 (1ul << 7)
+#define PIN_PA19G_I2S_SD0 19L /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0 6L
+#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0 (1ul << 19)
+#define PIN_PA08G_I2S_SD1 8L /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1 6L
+#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1 (1ul << 8)
+
+#endif /* _SAMD21G18AU_PIO_ */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/pio/samd21j15a.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/pio/samd21j15a.h
new file mode 100644
index 0000000000000000000000000000000000000000..c2d9c81d0fc06a0f1012d2e100fb4f009f47b6df
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/pio/samd21j15a.h
@@ -0,0 +1,1189 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21J15A
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21J15A_PIO_
+#define _SAMD21J15A_PIO_
+
+#define PIN_PA00 0 /**< \brief Pin Number for PA00 */
+#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */
+#define PIN_PA01 1 /**< \brief Pin Number for PA01 */
+#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */
+#define PIN_PA02 2 /**< \brief Pin Number for PA02 */
+#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */
+#define PIN_PA03 3 /**< \brief Pin Number for PA03 */
+#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */
+#define PIN_PA04 4 /**< \brief Pin Number for PA04 */
+#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */
+#define PIN_PA05 5 /**< \brief Pin Number for PA05 */
+#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */
+#define PIN_PA06 6 /**< \brief Pin Number for PA06 */
+#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */
+#define PIN_PA07 7 /**< \brief Pin Number for PA07 */
+#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */
+#define PIN_PA08 8 /**< \brief Pin Number for PA08 */
+#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */
+#define PIN_PA09 9 /**< \brief Pin Number for PA09 */
+#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */
+#define PIN_PA10 10 /**< \brief Pin Number for PA10 */
+#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */
+#define PIN_PA11 11 /**< \brief Pin Number for PA11 */
+#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */
+#define PIN_PA12 12 /**< \brief Pin Number for PA12 */
+#define PORT_PA12 (1ul << 12) /**< \brief PORT Mask for PA12 */
+#define PIN_PA13 13 /**< \brief Pin Number for PA13 */
+#define PORT_PA13 (1ul << 13) /**< \brief PORT Mask for PA13 */
+#define PIN_PA14 14 /**< \brief Pin Number for PA14 */
+#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */
+#define PIN_PA15 15 /**< \brief Pin Number for PA15 */
+#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */
+#define PIN_PA16 16 /**< \brief Pin Number for PA16 */
+#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */
+#define PIN_PA17 17 /**< \brief Pin Number for PA17 */
+#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */
+#define PIN_PA18 18 /**< \brief Pin Number for PA18 */
+#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */
+#define PIN_PA19 19 /**< \brief Pin Number for PA19 */
+#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */
+#define PIN_PA20 20 /**< \brief Pin Number for PA20 */
+#define PORT_PA20 (1ul << 20) /**< \brief PORT Mask for PA20 */
+#define PIN_PA21 21 /**< \brief Pin Number for PA21 */
+#define PORT_PA21 (1ul << 21) /**< \brief PORT Mask for PA21 */
+#define PIN_PA22 22 /**< \brief Pin Number for PA22 */
+#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */
+#define PIN_PA23 23 /**< \brief Pin Number for PA23 */
+#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */
+#define PIN_PA24 24 /**< \brief Pin Number for PA24 */
+#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */
+#define PIN_PA25 25 /**< \brief Pin Number for PA25 */
+#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */
+#define PIN_PA27 27 /**< \brief Pin Number for PA27 */
+#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */
+#define PIN_PA28 28 /**< \brief Pin Number for PA28 */
+#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */
+#define PIN_PA30 30 /**< \brief Pin Number for PA30 */
+#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */
+#define PIN_PA31 31 /**< \brief Pin Number for PA31 */
+#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */
+#define PIN_PB00 32 /**< \brief Pin Number for PB00 */
+#define PORT_PB00 (1ul << 0) /**< \brief PORT Mask for PB00 */
+#define PIN_PB01 33 /**< \brief Pin Number for PB01 */
+#define PORT_PB01 (1ul << 1) /**< \brief PORT Mask for PB01 */
+#define PIN_PB02 34 /**< \brief Pin Number for PB02 */
+#define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */
+#define PIN_PB03 35 /**< \brief Pin Number for PB03 */
+#define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */
+#define PIN_PB04 36 /**< \brief Pin Number for PB04 */
+#define PORT_PB04 (1ul << 4) /**< \brief PORT Mask for PB04 */
+#define PIN_PB05 37 /**< \brief Pin Number for PB05 */
+#define PORT_PB05 (1ul << 5) /**< \brief PORT Mask for PB05 */
+#define PIN_PB06 38 /**< \brief Pin Number for PB06 */
+#define PORT_PB06 (1ul << 6) /**< \brief PORT Mask for PB06 */
+#define PIN_PB07 39 /**< \brief Pin Number for PB07 */
+#define PORT_PB07 (1ul << 7) /**< \brief PORT Mask for PB07 */
+#define PIN_PB08 40 /**< \brief Pin Number for PB08 */
+#define PORT_PB08 (1ul << 8) /**< \brief PORT Mask for PB08 */
+#define PIN_PB09 41 /**< \brief Pin Number for PB09 */
+#define PORT_PB09 (1ul << 9) /**< \brief PORT Mask for PB09 */
+#define PIN_PB10 42 /**< \brief Pin Number for PB10 */
+#define PORT_PB10 (1ul << 10) /**< \brief PORT Mask for PB10 */
+#define PIN_PB11 43 /**< \brief Pin Number for PB11 */
+#define PORT_PB11 (1ul << 11) /**< \brief PORT Mask for PB11 */
+#define PIN_PB12 44 /**< \brief Pin Number for PB12 */
+#define PORT_PB12 (1ul << 12) /**< \brief PORT Mask for PB12 */
+#define PIN_PB13 45 /**< \brief Pin Number for PB13 */
+#define PORT_PB13 (1ul << 13) /**< \brief PORT Mask for PB13 */
+#define PIN_PB14 46 /**< \brief Pin Number for PB14 */
+#define PORT_PB14 (1ul << 14) /**< \brief PORT Mask for PB14 */
+#define PIN_PB15 47 /**< \brief Pin Number for PB15 */
+#define PORT_PB15 (1ul << 15) /**< \brief PORT Mask for PB15 */
+#define PIN_PB16 48 /**< \brief Pin Number for PB16 */
+#define PORT_PB16 (1ul << 16) /**< \brief PORT Mask for PB16 */
+#define PIN_PB17 49 /**< \brief Pin Number for PB17 */
+#define PORT_PB17 (1ul << 17) /**< \brief PORT Mask for PB17 */
+#define PIN_PB22 54 /**< \brief Pin Number for PB22 */
+#define PORT_PB22 (1ul << 22) /**< \brief PORT Mask for PB22 */
+#define PIN_PB23 55 /**< \brief Pin Number for PB23 */
+#define PORT_PB23 (1ul << 23) /**< \brief PORT Mask for PB23 */
+#define PIN_PB30 62 /**< \brief Pin Number for PB30 */
+#define PORT_PB30 (1ul << 30) /**< \brief PORT Mask for PB30 */
+#define PIN_PB31 63 /**< \brief Pin Number for PB31 */
+#define PORT_PB31 (1ul << 31) /**< \brief PORT Mask for PB31 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PB14H_GCLK_IO0 46L /**< \brief GCLK signal: IO0 on PB14 mux H */
+#define MUX_PB14H_GCLK_IO0 7L
+#define PINMUX_PB14H_GCLK_IO0 ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0)
+#define PORT_PB14H_GCLK_IO0 (1ul << 14)
+#define PIN_PB22H_GCLK_IO0 54L /**< \brief GCLK signal: IO0 on PB22 mux H */
+#define MUX_PB22H_GCLK_IO0 7L
+#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
+#define PORT_PB22H_GCLK_IO0 (1ul << 22)
+#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0 7L
+#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0 (1ul << 14)
+#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0 7L
+#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0 (1ul << 27)
+#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0 7L
+#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0 (1ul << 28)
+#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0 7L
+#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0 (1ul << 30)
+#define PIN_PB15H_GCLK_IO1 47L /**< \brief GCLK signal: IO1 on PB15 mux H */
+#define MUX_PB15H_GCLK_IO1 7L
+#define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1)
+#define PORT_PB15H_GCLK_IO1 (1ul << 15)
+#define PIN_PB23H_GCLK_IO1 55L /**< \brief GCLK signal: IO1 on PB23 mux H */
+#define MUX_PB23H_GCLK_IO1 7L
+#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
+#define PORT_PB23H_GCLK_IO1 (1ul << 23)
+#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1 7L
+#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1 (1ul << 15)
+#define PIN_PB16H_GCLK_IO2 48L /**< \brief GCLK signal: IO2 on PB16 mux H */
+#define MUX_PB16H_GCLK_IO2 7L
+#define PINMUX_PB16H_GCLK_IO2 ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2)
+#define PORT_PB16H_GCLK_IO2 (1ul << 16)
+#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2 7L
+#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2 (1ul << 16)
+#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3 7L
+#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3 (1ul << 17)
+#define PIN_PB17H_GCLK_IO3 49L /**< \brief GCLK signal: IO3 on PB17 mux H */
+#define MUX_PB17H_GCLK_IO3 7L
+#define PINMUX_PB17H_GCLK_IO3 ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3)
+#define PORT_PB17H_GCLK_IO3 (1ul << 17)
+#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4 7L
+#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4 (1ul << 10)
+#define PIN_PA20H_GCLK_IO4 20L /**< \brief GCLK signal: IO4 on PA20 mux H */
+#define MUX_PA20H_GCLK_IO4 7L
+#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
+#define PORT_PA20H_GCLK_IO4 (1ul << 20)
+#define PIN_PB10H_GCLK_IO4 42L /**< \brief GCLK signal: IO4 on PB10 mux H */
+#define MUX_PB10H_GCLK_IO4 7L
+#define PINMUX_PB10H_GCLK_IO4 ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
+#define PORT_PB10H_GCLK_IO4 (1ul << 10)
+#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5 7L
+#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5 (1ul << 11)
+#define PIN_PA21H_GCLK_IO5 21L /**< \brief GCLK signal: IO5 on PA21 mux H */
+#define MUX_PA21H_GCLK_IO5 7L
+#define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
+#define PORT_PA21H_GCLK_IO5 (1ul << 21)
+#define PIN_PB11H_GCLK_IO5 43L /**< \brief GCLK signal: IO5 on PB11 mux H */
+#define MUX_PB11H_GCLK_IO5 7L
+#define PINMUX_PB11H_GCLK_IO5 ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
+#define PORT_PB11H_GCLK_IO5 (1ul << 11)
+#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6 7L
+#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6 (1ul << 22)
+#define PIN_PB12H_GCLK_IO6 44L /**< \brief GCLK signal: IO6 on PB12 mux H */
+#define MUX_PB12H_GCLK_IO6 7L
+#define PINMUX_PB12H_GCLK_IO6 ((PIN_PB12H_GCLK_IO6 << 16) | MUX_PB12H_GCLK_IO6)
+#define PORT_PB12H_GCLK_IO6 (1ul << 12)
+#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7 7L
+#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7 (1ul << 23)
+#define PIN_PB13H_GCLK_IO7 45L /**< \brief GCLK signal: IO7 on PB13 mux H */
+#define MUX_PB13H_GCLK_IO7 7L
+#define PINMUX_PB13H_GCLK_IO7 ((PIN_PB13H_GCLK_IO7 << 16) | MUX_PB13H_GCLK_IO7)
+#define PORT_PB13H_GCLK_IO7 (1ul << 13)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0 0L
+#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0 (1ul << 16)
+#define PIN_PB00A_EIC_EXTINT0 32L /**< \brief EIC signal: EXTINT0 on PB00 mux A */
+#define MUX_PB00A_EIC_EXTINT0 0L
+#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0)
+#define PORT_PB00A_EIC_EXTINT0 (1ul << 0)
+#define PIN_PB16A_EIC_EXTINT0 48L /**< \brief EIC signal: EXTINT0 on PB16 mux A */
+#define MUX_PB16A_EIC_EXTINT0 0L
+#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0)
+#define PORT_PB16A_EIC_EXTINT0 (1ul << 16)
+#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0 0L
+#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0 (1ul << 0)
+#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1 0L
+#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1 (1ul << 17)
+#define PIN_PB01A_EIC_EXTINT1 33L /**< \brief EIC signal: EXTINT1 on PB01 mux A */
+#define MUX_PB01A_EIC_EXTINT1 0L
+#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1)
+#define PORT_PB01A_EIC_EXTINT1 (1ul << 1)
+#define PIN_PB17A_EIC_EXTINT1 49L /**< \brief EIC signal: EXTINT1 on PB17 mux A */
+#define MUX_PB17A_EIC_EXTINT1 0L
+#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1)
+#define PORT_PB17A_EIC_EXTINT1 (1ul << 17)
+#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1 0L
+#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1 (1ul << 1)
+#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2 0L
+#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2 (1ul << 18)
+#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2 0L
+#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2 (1ul << 2)
+#define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2 0L
+#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2 (1ul << 2)
+#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3 0L
+#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3 (1ul << 3)
+#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3 0L
+#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3 (1ul << 19)
+#define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3 0L
+#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3 (1ul << 3)
+#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4 0L
+#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4 (1ul << 4)
+#define PIN_PA20A_EIC_EXTINT4 20L /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4 0L
+#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4 (1ul << 20)
+#define PIN_PB04A_EIC_EXTINT4 36L /**< \brief EIC signal: EXTINT4 on PB04 mux A */
+#define MUX_PB04A_EIC_EXTINT4 0L
+#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
+#define PORT_PB04A_EIC_EXTINT4 (1ul << 4)
+#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5 0L
+#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5 (1ul << 5)
+#define PIN_PA21A_EIC_EXTINT5 21L /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5 0L
+#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5 (1ul << 21)
+#define PIN_PB05A_EIC_EXTINT5 37L /**< \brief EIC signal: EXTINT5 on PB05 mux A */
+#define MUX_PB05A_EIC_EXTINT5 0L
+#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5)
+#define PORT_PB05A_EIC_EXTINT5 (1ul << 5)
+#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6 0L
+#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6 (1ul << 6)
+#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6 0L
+#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6 (1ul << 22)
+#define PIN_PB06A_EIC_EXTINT6 38L /**< \brief EIC signal: EXTINT6 on PB06 mux A */
+#define MUX_PB06A_EIC_EXTINT6 0L
+#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6)
+#define PORT_PB06A_EIC_EXTINT6 (1ul << 6)
+#define PIN_PB22A_EIC_EXTINT6 54L /**< \brief EIC signal: EXTINT6 on PB22 mux A */
+#define MUX_PB22A_EIC_EXTINT6 0L
+#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
+#define PORT_PB22A_EIC_EXTINT6 (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7 0L
+#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7 (1ul << 7)
+#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7 0L
+#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7 (1ul << 23)
+#define PIN_PB07A_EIC_EXTINT7 39L /**< \brief EIC signal: EXTINT7 on PB07 mux A */
+#define MUX_PB07A_EIC_EXTINT7 0L
+#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7)
+#define PORT_PB07A_EIC_EXTINT7 (1ul << 7)
+#define PIN_PB23A_EIC_EXTINT7 55L /**< \brief EIC signal: EXTINT7 on PB23 mux A */
+#define MUX_PB23A_EIC_EXTINT7 0L
+#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
+#define PORT_PB23A_EIC_EXTINT7 (1ul << 23)
+#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8 0L
+#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8 (1ul << 28)
+#define PIN_PB08A_EIC_EXTINT8 40L /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8 0L
+#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8 (1ul << 8)
+#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9 0L
+#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9 (1ul << 9)
+#define PIN_PB09A_EIC_EXTINT9 41L /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9 0L
+#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9 (1ul << 9)
+#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10 0L
+#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10 (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10 0L
+#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10 (1ul << 30)
+#define PIN_PB10A_EIC_EXTINT10 42L /**< \brief EIC signal: EXTINT10 on PB10 mux A */
+#define MUX_PB10A_EIC_EXTINT10 0L
+#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
+#define PORT_PB10A_EIC_EXTINT10 (1ul << 10)
+#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11 0L
+#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11 (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11 0L
+#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11 (1ul << 31)
+#define PIN_PB11A_EIC_EXTINT11 43L /**< \brief EIC signal: EXTINT11 on PB11 mux A */
+#define MUX_PB11A_EIC_EXTINT11 0L
+#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
+#define PORT_PB11A_EIC_EXTINT11 (1ul << 11)
+#define PIN_PA12A_EIC_EXTINT12 12L /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12 0L
+#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12 (1ul << 12)
+#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12 0L
+#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12 (1ul << 24)
+#define PIN_PB12A_EIC_EXTINT12 44L /**< \brief EIC signal: EXTINT12 on PB12 mux A */
+#define MUX_PB12A_EIC_EXTINT12 0L
+#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12)
+#define PORT_PB12A_EIC_EXTINT12 (1ul << 12)
+#define PIN_PA13A_EIC_EXTINT13 13L /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13 0L
+#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13 (1ul << 13)
+#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13 0L
+#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13 (1ul << 25)
+#define PIN_PB13A_EIC_EXTINT13 45L /**< \brief EIC signal: EXTINT13 on PB13 mux A */
+#define MUX_PB13A_EIC_EXTINT13 0L
+#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13)
+#define PORT_PB13A_EIC_EXTINT13 (1ul << 13)
+#define PIN_PB14A_EIC_EXTINT14 46L /**< \brief EIC signal: EXTINT14 on PB14 mux A */
+#define MUX_PB14A_EIC_EXTINT14 0L
+#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14)
+#define PORT_PB14A_EIC_EXTINT14 (1ul << 14)
+#define PIN_PB30A_EIC_EXTINT14 62L /**< \brief EIC signal: EXTINT14 on PB30 mux A */
+#define MUX_PB30A_EIC_EXTINT14 0L
+#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14)
+#define PORT_PB30A_EIC_EXTINT14 (1ul << 30)
+#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14 0L
+#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14 (1ul << 14)
+#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15 0L
+#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15 (1ul << 15)
+#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15 0L
+#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15 (1ul << 27)
+#define PIN_PB15A_EIC_EXTINT15 47L /**< \brief EIC signal: EXTINT15 on PB15 mux A */
+#define MUX_PB15A_EIC_EXTINT15 0L
+#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15)
+#define PORT_PB15A_EIC_EXTINT15 (1ul << 15)
+#define PIN_PB31A_EIC_EXTINT15 63L /**< \brief EIC signal: EXTINT15 on PB31 mux A */
+#define MUX_PB31A_EIC_EXTINT15 0L
+#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15)
+#define PORT_PB31A_EIC_EXTINT15 (1ul << 31)
+#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI 0L
+#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI (1ul << 8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM 6L
+#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM (1ul << 24)
+#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP 6L
+#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP (1ul << 25)
+#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ 6L
+#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0 3L
+#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4)
+#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0 2L
+#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8)
+#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1 3L
+#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5)
+#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1 2L
+#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9)
+#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2 3L
+#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6)
+#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2 2L
+#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3 3L
+#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7)
+#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3 2L
+#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0 2L
+#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16)
+#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0 3L
+#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0)
+#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1 2L
+#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17)
+#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1 3L
+#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1)
+#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2 3L
+#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2 2L
+#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3 3L
+#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3 2L
+#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0 3L
+#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8)
+#define PIN_PA12C_SERCOM2_PAD0 12L /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0 2L
+#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0 (1ul << 12)
+#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1 3L
+#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9)
+#define PIN_PA13C_SERCOM2_PAD1 13L /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1 2L
+#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1 (1ul << 13)
+#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2 3L
+#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2 2L
+#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3 3L
+#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3 2L
+#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0 3L
+#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0 2L
+#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1 3L
+#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1 2L
+#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2 3L
+#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18)
+#define PIN_PA20D_SERCOM3_PAD2 20L /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2 3L
+#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2 (1ul << 20)
+#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2 2L
+#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3 3L
+#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19)
+#define PIN_PA21D_SERCOM3_PAD3 21L /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3 3L
+#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3 (1ul << 21)
+#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3 2L
+#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA12D_SERCOM4_PAD0 12L /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD0 3L
+#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
+#define PORT_PA12D_SERCOM4_PAD0 (1ul << 12)
+#define PIN_PB08D_SERCOM4_PAD0 40L /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0 3L
+#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0 (1ul << 8)
+#define PIN_PB12C_SERCOM4_PAD0 44L /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */
+#define MUX_PB12C_SERCOM4_PAD0 2L
+#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0)
+#define PORT_PB12C_SERCOM4_PAD0 (1ul << 12)
+#define PIN_PA13D_SERCOM4_PAD1 13L /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD1 3L
+#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
+#define PORT_PA13D_SERCOM4_PAD1 (1ul << 13)
+#define PIN_PB09D_SERCOM4_PAD1 41L /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1 3L
+#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1 (1ul << 9)
+#define PIN_PB13C_SERCOM4_PAD1 45L /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */
+#define MUX_PB13C_SERCOM4_PAD1 2L
+#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1)
+#define PORT_PB13C_SERCOM4_PAD1 (1ul << 13)
+#define PIN_PA14D_SERCOM4_PAD2 14L /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2 3L
+#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2 (1ul << 14)
+#define PIN_PB10D_SERCOM4_PAD2 42L /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
+#define MUX_PB10D_SERCOM4_PAD2 3L
+#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
+#define PORT_PB10D_SERCOM4_PAD2 (1ul << 10)
+#define PIN_PB14C_SERCOM4_PAD2 46L /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */
+#define MUX_PB14C_SERCOM4_PAD2 2L
+#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2)
+#define PORT_PB14C_SERCOM4_PAD2 (1ul << 14)
+#define PIN_PA15D_SERCOM4_PAD3 15L /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3 3L
+#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3 (1ul << 15)
+#define PIN_PB11D_SERCOM4_PAD3 43L /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
+#define MUX_PB11D_SERCOM4_PAD3 3L
+#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
+#define PORT_PB11D_SERCOM4_PAD3 (1ul << 11)
+#define PIN_PB15C_SERCOM4_PAD3 47L /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */
+#define MUX_PB15C_SERCOM4_PAD3 2L
+#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3)
+#define PORT_PB15C_SERCOM4_PAD3 (1ul << 15)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PB16C_SERCOM5_PAD0 48L /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */
+#define MUX_PB16C_SERCOM5_PAD0 2L
+#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0)
+#define PORT_PB16C_SERCOM5_PAD0 (1ul << 16)
+#define PIN_PA22D_SERCOM5_PAD0 22L /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD0 3L
+#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
+#define PORT_PA22D_SERCOM5_PAD0 (1ul << 22)
+#define PIN_PB02D_SERCOM5_PAD0 34L /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0 3L
+#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0 (1ul << 2)
+#define PIN_PB30D_SERCOM5_PAD0 62L /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */
+#define MUX_PB30D_SERCOM5_PAD0 3L
+#define PINMUX_PB30D_SERCOM5_PAD0 ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0)
+#define PORT_PB30D_SERCOM5_PAD0 (1ul << 30)
+#define PIN_PB17C_SERCOM5_PAD1 49L /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */
+#define MUX_PB17C_SERCOM5_PAD1 2L
+#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1)
+#define PORT_PB17C_SERCOM5_PAD1 (1ul << 17)
+#define PIN_PA23D_SERCOM5_PAD1 23L /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD1 3L
+#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
+#define PORT_PA23D_SERCOM5_PAD1 (1ul << 23)
+#define PIN_PB03D_SERCOM5_PAD1 35L /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1 3L
+#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1 (1ul << 3)
+#define PIN_PB31D_SERCOM5_PAD1 63L /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */
+#define MUX_PB31D_SERCOM5_PAD1 3L
+#define PINMUX_PB31D_SERCOM5_PAD1 ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1)
+#define PORT_PB31D_SERCOM5_PAD1 (1ul << 31)
+#define PIN_PA24D_SERCOM5_PAD2 24L /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2 3L
+#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2 (1ul << 24)
+#define PIN_PB00D_SERCOM5_PAD2 32L /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */
+#define MUX_PB00D_SERCOM5_PAD2 3L
+#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2)
+#define PORT_PB00D_SERCOM5_PAD2 (1ul << 0)
+#define PIN_PB22D_SERCOM5_PAD2 54L /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
+#define MUX_PB22D_SERCOM5_PAD2 3L
+#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
+#define PORT_PB22D_SERCOM5_PAD2 (1ul << 22)
+#define PIN_PA20C_SERCOM5_PAD2 20L /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2 2L
+#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2 (1ul << 20)
+#define PIN_PA25D_SERCOM5_PAD3 25L /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3 3L
+#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3 (1ul << 25)
+#define PIN_PB01D_SERCOM5_PAD3 33L /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */
+#define MUX_PB01D_SERCOM5_PAD3 3L
+#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3)
+#define PORT_PB01D_SERCOM5_PAD3 (1ul << 1)
+#define PIN_PB23D_SERCOM5_PAD3 55L /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
+#define MUX_PB23D_SERCOM5_PAD3 3L
+#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
+#define PORT_PB23D_SERCOM5_PAD3 (1ul << 23)
+#define PIN_PA21C_SERCOM5_PAD3 21L /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3 2L
+#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3 (1ul << 21)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0 4L
+#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0 (1ul << 4)
+#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0 4L
+#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0 (1ul << 8)
+#define PIN_PB30E_TCC0_WO0 62L /**< \brief TCC0 signal: WO0 on PB30 mux E */
+#define MUX_PB30E_TCC0_WO0 4L
+#define PINMUX_PB30E_TCC0_WO0 ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0)
+#define PORT_PB30E_TCC0_WO0 (1ul << 30)
+#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1 4L
+#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1 (1ul << 5)
+#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1 4L
+#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1 (1ul << 9)
+#define PIN_PB31E_TCC0_WO1 63L /**< \brief TCC0 signal: WO1 on PB31 mux E */
+#define MUX_PB31E_TCC0_WO1 4L
+#define PINMUX_PB31E_TCC0_WO1 ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1)
+#define PORT_PB31E_TCC0_WO1 (1ul << 31)
+#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2 5L
+#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2 (1ul << 10)
+#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2 5L
+#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2 (1ul << 18)
+#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3 5L
+#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3 (1ul << 11)
+#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3 5L
+#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3 (1ul << 19)
+#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4 5L
+#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4 (1ul << 14)
+#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4 5L
+#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4 (1ul << 22)
+#define PIN_PB10F_TCC0_WO4 42L /**< \brief TCC0 signal: WO4 on PB10 mux F */
+#define MUX_PB10F_TCC0_WO4 5L
+#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
+#define PORT_PB10F_TCC0_WO4 (1ul << 10)
+#define PIN_PB16F_TCC0_WO4 48L /**< \brief TCC0 signal: WO4 on PB16 mux F */
+#define MUX_PB16F_TCC0_WO4 5L
+#define PINMUX_PB16F_TCC0_WO4 ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4)
+#define PORT_PB16F_TCC0_WO4 (1ul << 16)
+#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5 5L
+#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5 (1ul << 15)
+#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5 5L
+#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5 (1ul << 23)
+#define PIN_PB11F_TCC0_WO5 43L /**< \brief TCC0 signal: WO5 on PB11 mux F */
+#define MUX_PB11F_TCC0_WO5 5L
+#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
+#define PORT_PB11F_TCC0_WO5 (1ul << 11)
+#define PIN_PB17F_TCC0_WO5 49L /**< \brief TCC0 signal: WO5 on PB17 mux F */
+#define MUX_PB17F_TCC0_WO5 5L
+#define PINMUX_PB17F_TCC0_WO5 ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5)
+#define PORT_PB17F_TCC0_WO5 (1ul << 17)
+#define PIN_PA12F_TCC0_WO6 12L /**< \brief TCC0 signal: WO6 on PA12 mux F */
+#define MUX_PA12F_TCC0_WO6 5L
+#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
+#define PORT_PA12F_TCC0_WO6 (1ul << 12)
+#define PIN_PA20F_TCC0_WO6 20L /**< \brief TCC0 signal: WO6 on PA20 mux F */
+#define MUX_PA20F_TCC0_WO6 5L
+#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
+#define PORT_PA20F_TCC0_WO6 (1ul << 20)
+#define PIN_PB12F_TCC0_WO6 44L /**< \brief TCC0 signal: WO6 on PB12 mux F */
+#define MUX_PB12F_TCC0_WO6 5L
+#define PINMUX_PB12F_TCC0_WO6 ((PIN_PB12F_TCC0_WO6 << 16) | MUX_PB12F_TCC0_WO6)
+#define PORT_PB12F_TCC0_WO6 (1ul << 12)
+#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6 5L
+#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6 (1ul << 16)
+#define PIN_PA13F_TCC0_WO7 13L /**< \brief TCC0 signal: WO7 on PA13 mux F */
+#define MUX_PA13F_TCC0_WO7 5L
+#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
+#define PORT_PA13F_TCC0_WO7 (1ul << 13)
+#define PIN_PA21F_TCC0_WO7 21L /**< \brief TCC0 signal: WO7 on PA21 mux F */
+#define MUX_PA21F_TCC0_WO7 5L
+#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
+#define PORT_PA21F_TCC0_WO7 (1ul << 21)
+#define PIN_PB13F_TCC0_WO7 45L /**< \brief TCC0 signal: WO7 on PB13 mux F */
+#define MUX_PB13F_TCC0_WO7 5L
+#define PINMUX_PB13F_TCC0_WO7 ((PIN_PB13F_TCC0_WO7 << 16) | MUX_PB13F_TCC0_WO7)
+#define PORT_PB13F_TCC0_WO7 (1ul << 13)
+#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7 5L
+#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7 (1ul << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0 4L
+#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0 (1ul << 6)
+#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0 4L
+#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0 (1ul << 10)
+#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0 4L
+#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0 (1ul << 30)
+#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1 4L
+#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1 (1ul << 7)
+#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1 4L
+#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1 (1ul << 11)
+#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1 4L
+#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1 (1ul << 31)
+#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2 5L
+#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2 (1ul << 8)
+#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2 5L
+#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2 (1ul << 24)
+#define PIN_PB30F_TCC1_WO2 62L /**< \brief TCC1 signal: WO2 on PB30 mux F */
+#define MUX_PB30F_TCC1_WO2 5L
+#define PINMUX_PB30F_TCC1_WO2 ((PIN_PB30F_TCC1_WO2 << 16) | MUX_PB30F_TCC1_WO2)
+#define PORT_PB30F_TCC1_WO2 (1ul << 30)
+#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3 5L
+#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3 (1ul << 9)
+#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3 5L
+#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3 (1ul << 25)
+#define PIN_PB31F_TCC1_WO3 63L /**< \brief TCC1 signal: WO3 on PB31 mux F */
+#define MUX_PB31F_TCC1_WO3 5L
+#define PINMUX_PB31F_TCC1_WO3 ((PIN_PB31F_TCC1_WO3 << 16) | MUX_PB31F_TCC1_WO3)
+#define PORT_PB31F_TCC1_WO3 (1ul << 31)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA12E_TCC2_WO0 12L /**< \brief TCC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TCC2_WO0 4L
+#define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
+#define PORT_PA12E_TCC2_WO0 (1ul << 12)
+#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0 4L
+#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0 (1ul << 16)
+#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0 4L
+#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0 (1ul << 0)
+#define PIN_PA13E_TCC2_WO1 13L /**< \brief TCC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TCC2_WO1 4L
+#define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
+#define PORT_PA13E_TCC2_WO1 (1ul << 13)
+#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1 4L
+#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1 (1ul << 17)
+#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1 4L
+#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1 (1ul << 1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0 4L
+#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0 (1ul << 18)
+#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0 4L
+#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0 (1ul << 14)
+#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1 4L
+#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1 (1ul << 19)
+#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1 4L
+#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1 (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0 4L
+#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0 (1ul << 22)
+#define PIN_PB08E_TC4_WO0 40L /**< \brief TC4 signal: WO0 on PB08 mux E */
+#define MUX_PB08E_TC4_WO0 4L
+#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
+#define PORT_PB08E_TC4_WO0 (1ul << 8)
+#define PIN_PB12E_TC4_WO0 44L /**< \brief TC4 signal: WO0 on PB12 mux E */
+#define MUX_PB12E_TC4_WO0 4L
+#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0)
+#define PORT_PB12E_TC4_WO0 (1ul << 12)
+#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1 4L
+#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1 (1ul << 23)
+#define PIN_PB09E_TC4_WO1 41L /**< \brief TC4 signal: WO1 on PB09 mux E */
+#define MUX_PB09E_TC4_WO1 4L
+#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
+#define PORT_PB09E_TC4_WO1 (1ul << 9)
+#define PIN_PB13E_TC4_WO1 45L /**< \brief TC4 signal: WO1 on PB13 mux E */
+#define MUX_PB13E_TC4_WO1 4L
+#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1)
+#define PORT_PB13E_TC4_WO1 (1ul << 13)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0 4L
+#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0 (1ul << 24)
+#define PIN_PB10E_TC5_WO0 42L /**< \brief TC5 signal: WO0 on PB10 mux E */
+#define MUX_PB10E_TC5_WO0 4L
+#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
+#define PORT_PB10E_TC5_WO0 (1ul << 10)
+#define PIN_PB14E_TC5_WO0 46L /**< \brief TC5 signal: WO0 on PB14 mux E */
+#define MUX_PB14E_TC5_WO0 4L
+#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0)
+#define PORT_PB14E_TC5_WO0 (1ul << 14)
+#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1 4L
+#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1 (1ul << 25)
+#define PIN_PB11E_TC5_WO1 43L /**< \brief TC5 signal: WO1 on PB11 mux E */
+#define MUX_PB11E_TC5_WO1 4L
+#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
+#define PORT_PB11E_TC5_WO1 (1ul << 11)
+#define PIN_PB15E_TC5_WO1 47L /**< \brief TC5 signal: WO1 on PB15 mux E */
+#define MUX_PB15E_TC5_WO1 4L
+#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1)
+#define PORT_PB15E_TC5_WO1 (1ul << 15)
+/* ========== PORT definition for TC6 peripheral ========== */
+#define PIN_PB02E_TC6_WO0 34L /**< \brief TC6 signal: WO0 on PB02 mux E */
+#define MUX_PB02E_TC6_WO0 4L
+#define PINMUX_PB02E_TC6_WO0 ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0)
+#define PORT_PB02E_TC6_WO0 (1ul << 2)
+#define PIN_PB16E_TC6_WO0 48L /**< \brief TC6 signal: WO0 on PB16 mux E */
+#define MUX_PB16E_TC6_WO0 4L
+#define PINMUX_PB16E_TC6_WO0 ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0)
+#define PORT_PB16E_TC6_WO0 (1ul << 16)
+#define PIN_PB03E_TC6_WO1 35L /**< \brief TC6 signal: WO1 on PB03 mux E */
+#define MUX_PB03E_TC6_WO1 4L
+#define PINMUX_PB03E_TC6_WO1 ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1)
+#define PORT_PB03E_TC6_WO1 (1ul << 3)
+#define PIN_PB17E_TC6_WO1 49L /**< \brief TC6 signal: WO1 on PB17 mux E */
+#define MUX_PB17E_TC6_WO1 4L
+#define PINMUX_PB17E_TC6_WO1 ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1)
+#define PORT_PB17E_TC6_WO1 (1ul << 17)
+/* ========== PORT definition for TC7 peripheral ========== */
+#define PIN_PA20E_TC7_WO0 20L /**< \brief TC7 signal: WO0 on PA20 mux E */
+#define MUX_PA20E_TC7_WO0 4L
+#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0)
+#define PORT_PA20E_TC7_WO0 (1ul << 20)
+#define PIN_PB00E_TC7_WO0 32L /**< \brief TC7 signal: WO0 on PB00 mux E */
+#define MUX_PB00E_TC7_WO0 4L
+#define PINMUX_PB00E_TC7_WO0 ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0)
+#define PORT_PB00E_TC7_WO0 (1ul << 0)
+#define PIN_PB22E_TC7_WO0 54L /**< \brief TC7 signal: WO0 on PB22 mux E */
+#define MUX_PB22E_TC7_WO0 4L
+#define PINMUX_PB22E_TC7_WO0 ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0)
+#define PORT_PB22E_TC7_WO0 (1ul << 22)
+#define PIN_PA21E_TC7_WO1 21L /**< \brief TC7 signal: WO1 on PA21 mux E */
+#define MUX_PA21E_TC7_WO1 4L
+#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1)
+#define PORT_PA21E_TC7_WO1 (1ul << 21)
+#define PIN_PB01E_TC7_WO1 33L /**< \brief TC7 signal: WO1 on PB01 mux E */
+#define MUX_PB01E_TC7_WO1 4L
+#define PINMUX_PB01E_TC7_WO1 ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1)
+#define PORT_PB01E_TC7_WO1 (1ul << 1)
+#define PIN_PB23E_TC7_WO1 55L /**< \brief TC7 signal: WO1 on PB23 mux E */
+#define MUX_PB23E_TC7_WO1 4L
+#define PINMUX_PB23E_TC7_WO1 ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1)
+#define PORT_PB23E_TC7_WO1 (1ul << 23)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0 1L
+#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0 (1ul << 2)
+#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1 1L
+#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1 (1ul << 3)
+#define PIN_PB08B_ADC_AIN2 40L /**< \brief ADC signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC_AIN2 1L
+#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
+#define PORT_PB08B_ADC_AIN2 (1ul << 8)
+#define PIN_PB09B_ADC_AIN3 41L /**< \brief ADC signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC_AIN3 1L
+#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
+#define PORT_PB09B_ADC_AIN3 (1ul << 9)
+#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4 1L
+#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4 (1ul << 4)
+#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5 1L
+#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5 (1ul << 5)
+#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6 1L
+#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6 (1ul << 6)
+#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7 1L
+#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7 (1ul << 7)
+#define PIN_PB00B_ADC_AIN8 32L /**< \brief ADC signal: AIN8 on PB00 mux B */
+#define MUX_PB00B_ADC_AIN8 1L
+#define PINMUX_PB00B_ADC_AIN8 ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8)
+#define PORT_PB00B_ADC_AIN8 (1ul << 0)
+#define PIN_PB01B_ADC_AIN9 33L /**< \brief ADC signal: AIN9 on PB01 mux B */
+#define MUX_PB01B_ADC_AIN9 1L
+#define PINMUX_PB01B_ADC_AIN9 ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9)
+#define PORT_PB01B_ADC_AIN9 (1ul << 1)
+#define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */
+#define MUX_PB02B_ADC_AIN10 1L
+#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
+#define PORT_PB02B_ADC_AIN10 (1ul << 2)
+#define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */
+#define MUX_PB03B_ADC_AIN11 1L
+#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
+#define PORT_PB03B_ADC_AIN11 (1ul << 3)
+#define PIN_PB04B_ADC_AIN12 36L /**< \brief ADC signal: AIN12 on PB04 mux B */
+#define MUX_PB04B_ADC_AIN12 1L
+#define PINMUX_PB04B_ADC_AIN12 ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12)
+#define PORT_PB04B_ADC_AIN12 (1ul << 4)
+#define PIN_PB05B_ADC_AIN13 37L /**< \brief ADC signal: AIN13 on PB05 mux B */
+#define MUX_PB05B_ADC_AIN13 1L
+#define PINMUX_PB05B_ADC_AIN13 ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13)
+#define PORT_PB05B_ADC_AIN13 (1ul << 5)
+#define PIN_PB06B_ADC_AIN14 38L /**< \brief ADC signal: AIN14 on PB06 mux B */
+#define MUX_PB06B_ADC_AIN14 1L
+#define PINMUX_PB06B_ADC_AIN14 ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14)
+#define PORT_PB06B_ADC_AIN14 (1ul << 6)
+#define PIN_PB07B_ADC_AIN15 39L /**< \brief ADC signal: AIN15 on PB07 mux B */
+#define MUX_PB07B_ADC_AIN15 1L
+#define PINMUX_PB07B_ADC_AIN15 ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15)
+#define PORT_PB07B_ADC_AIN15 (1ul << 7)
+#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16 1L
+#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16 (1ul << 8)
+#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17 1L
+#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17 (1ul << 9)
+#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18 1L
+#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18 (1ul << 10)
+#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19 1L
+#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19 (1ul << 11)
+#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP 1L
+#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP (1ul << 4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0 1L
+#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0 (1ul << 4)
+#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1 1L
+#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1 (1ul << 5)
+#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2 1L
+#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2 (1ul << 6)
+#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3 1L
+#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3 (1ul << 7)
+#define PIN_PA12H_AC_CMP0 12L /**< \brief AC signal: CMP0 on PA12 mux H */
+#define MUX_PA12H_AC_CMP0 7L
+#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
+#define PORT_PA12H_AC_CMP0 (1ul << 12)
+#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0 7L
+#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0 (1ul << 18)
+#define PIN_PA13H_AC_CMP1 13L /**< \brief AC signal: CMP1 on PA13 mux H */
+#define MUX_PA13H_AC_CMP1 7L
+#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
+#define PORT_PA13H_AC_CMP1 (1ul << 13)
+#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1 7L
+#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1 (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT 1L
+#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT (1ul << 2)
+#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP 1L
+#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP (1ul << 3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0 11L /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0 6L
+#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0 (1ul << 11)
+#define PIN_PA21G_I2S_FS0 21L /**< \brief I2S signal: FS0 on PA21 mux G */
+#define MUX_PA21G_I2S_FS0 6L
+#define PINMUX_PA21G_I2S_FS0 ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
+#define PORT_PA21G_I2S_FS0 (1ul << 21)
+#define PIN_PB12G_I2S_FS1 44L /**< \brief I2S signal: FS1 on PB12 mux G */
+#define MUX_PB12G_I2S_FS1 6L
+#define PINMUX_PB12G_I2S_FS1 ((PIN_PB12G_I2S_FS1 << 16) | MUX_PB12G_I2S_FS1)
+#define PORT_PB12G_I2S_FS1 (1ul << 12)
+#define PIN_PA09G_I2S_MCK0 9L /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0 6L
+#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0 (1ul << 9)
+#define PIN_PB17G_I2S_MCK0 49L /**< \brief I2S signal: MCK0 on PB17 mux G */
+#define MUX_PB17G_I2S_MCK0 6L
+#define PINMUX_PB17G_I2S_MCK0 ((PIN_PB17G_I2S_MCK0 << 16) | MUX_PB17G_I2S_MCK0)
+#define PORT_PB17G_I2S_MCK0 (1ul << 17)
+#define PIN_PB10G_I2S_MCK1 42L /**< \brief I2S signal: MCK1 on PB10 mux G */
+#define MUX_PB10G_I2S_MCK1 6L
+#define PINMUX_PB10G_I2S_MCK1 ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1)
+#define PORT_PB10G_I2S_MCK1 (1ul << 10)
+#define PIN_PA10G_I2S_SCK0 10L /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0 6L
+#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0 (1ul << 10)
+#define PIN_PA20G_I2S_SCK0 20L /**< \brief I2S signal: SCK0 on PA20 mux G */
+#define MUX_PA20G_I2S_SCK0 6L
+#define PINMUX_PA20G_I2S_SCK0 ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
+#define PORT_PA20G_I2S_SCK0 (1ul << 20)
+#define PIN_PB11G_I2S_SCK1 43L /**< \brief I2S signal: SCK1 on PB11 mux G */
+#define MUX_PB11G_I2S_SCK1 6L
+#define PINMUX_PB11G_I2S_SCK1 ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1)
+#define PORT_PB11G_I2S_SCK1 (1ul << 11)
+#define PIN_PA07G_I2S_SD0 7L /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0 6L
+#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0 (1ul << 7)
+#define PIN_PA19G_I2S_SD0 19L /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0 6L
+#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0 (1ul << 19)
+#define PIN_PA08G_I2S_SD1 8L /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1 6L
+#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1 (1ul << 8)
+#define PIN_PB16G_I2S_SD1 48L /**< \brief I2S signal: SD1 on PB16 mux G */
+#define MUX_PB16G_I2S_SD1 6L
+#define PINMUX_PB16G_I2S_SD1 ((PIN_PB16G_I2S_SD1 << 16) | MUX_PB16G_I2S_SD1)
+#define PORT_PB16G_I2S_SD1 (1ul << 16)
+
+#endif /* _SAMD21J15A_PIO_ */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/pio/samd21j16a.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/pio/samd21j16a.h
new file mode 100644
index 0000000000000000000000000000000000000000..adf530ea5b766ea3aec5b34702924ec7278f1362
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/pio/samd21j16a.h
@@ -0,0 +1,1189 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21J16A
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21J16A_PIO_
+#define _SAMD21J16A_PIO_
+
+#define PIN_PA00 0 /**< \brief Pin Number for PA00 */
+#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */
+#define PIN_PA01 1 /**< \brief Pin Number for PA01 */
+#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */
+#define PIN_PA02 2 /**< \brief Pin Number for PA02 */
+#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */
+#define PIN_PA03 3 /**< \brief Pin Number for PA03 */
+#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */
+#define PIN_PA04 4 /**< \brief Pin Number for PA04 */
+#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */
+#define PIN_PA05 5 /**< \brief Pin Number for PA05 */
+#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */
+#define PIN_PA06 6 /**< \brief Pin Number for PA06 */
+#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */
+#define PIN_PA07 7 /**< \brief Pin Number for PA07 */
+#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */
+#define PIN_PA08 8 /**< \brief Pin Number for PA08 */
+#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */
+#define PIN_PA09 9 /**< \brief Pin Number for PA09 */
+#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */
+#define PIN_PA10 10 /**< \brief Pin Number for PA10 */
+#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */
+#define PIN_PA11 11 /**< \brief Pin Number for PA11 */
+#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */
+#define PIN_PA12 12 /**< \brief Pin Number for PA12 */
+#define PORT_PA12 (1ul << 12) /**< \brief PORT Mask for PA12 */
+#define PIN_PA13 13 /**< \brief Pin Number for PA13 */
+#define PORT_PA13 (1ul << 13) /**< \brief PORT Mask for PA13 */
+#define PIN_PA14 14 /**< \brief Pin Number for PA14 */
+#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */
+#define PIN_PA15 15 /**< \brief Pin Number for PA15 */
+#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */
+#define PIN_PA16 16 /**< \brief Pin Number for PA16 */
+#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */
+#define PIN_PA17 17 /**< \brief Pin Number for PA17 */
+#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */
+#define PIN_PA18 18 /**< \brief Pin Number for PA18 */
+#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */
+#define PIN_PA19 19 /**< \brief Pin Number for PA19 */
+#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */
+#define PIN_PA20 20 /**< \brief Pin Number for PA20 */
+#define PORT_PA20 (1ul << 20) /**< \brief PORT Mask for PA20 */
+#define PIN_PA21 21 /**< \brief Pin Number for PA21 */
+#define PORT_PA21 (1ul << 21) /**< \brief PORT Mask for PA21 */
+#define PIN_PA22 22 /**< \brief Pin Number for PA22 */
+#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */
+#define PIN_PA23 23 /**< \brief Pin Number for PA23 */
+#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */
+#define PIN_PA24 24 /**< \brief Pin Number for PA24 */
+#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */
+#define PIN_PA25 25 /**< \brief Pin Number for PA25 */
+#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */
+#define PIN_PA27 27 /**< \brief Pin Number for PA27 */
+#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */
+#define PIN_PA28 28 /**< \brief Pin Number for PA28 */
+#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */
+#define PIN_PA30 30 /**< \brief Pin Number for PA30 */
+#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */
+#define PIN_PA31 31 /**< \brief Pin Number for PA31 */
+#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */
+#define PIN_PB00 32 /**< \brief Pin Number for PB00 */
+#define PORT_PB00 (1ul << 0) /**< \brief PORT Mask for PB00 */
+#define PIN_PB01 33 /**< \brief Pin Number for PB01 */
+#define PORT_PB01 (1ul << 1) /**< \brief PORT Mask for PB01 */
+#define PIN_PB02 34 /**< \brief Pin Number for PB02 */
+#define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */
+#define PIN_PB03 35 /**< \brief Pin Number for PB03 */
+#define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */
+#define PIN_PB04 36 /**< \brief Pin Number for PB04 */
+#define PORT_PB04 (1ul << 4) /**< \brief PORT Mask for PB04 */
+#define PIN_PB05 37 /**< \brief Pin Number for PB05 */
+#define PORT_PB05 (1ul << 5) /**< \brief PORT Mask for PB05 */
+#define PIN_PB06 38 /**< \brief Pin Number for PB06 */
+#define PORT_PB06 (1ul << 6) /**< \brief PORT Mask for PB06 */
+#define PIN_PB07 39 /**< \brief Pin Number for PB07 */
+#define PORT_PB07 (1ul << 7) /**< \brief PORT Mask for PB07 */
+#define PIN_PB08 40 /**< \brief Pin Number for PB08 */
+#define PORT_PB08 (1ul << 8) /**< \brief PORT Mask for PB08 */
+#define PIN_PB09 41 /**< \brief Pin Number for PB09 */
+#define PORT_PB09 (1ul << 9) /**< \brief PORT Mask for PB09 */
+#define PIN_PB10 42 /**< \brief Pin Number for PB10 */
+#define PORT_PB10 (1ul << 10) /**< \brief PORT Mask for PB10 */
+#define PIN_PB11 43 /**< \brief Pin Number for PB11 */
+#define PORT_PB11 (1ul << 11) /**< \brief PORT Mask for PB11 */
+#define PIN_PB12 44 /**< \brief Pin Number for PB12 */
+#define PORT_PB12 (1ul << 12) /**< \brief PORT Mask for PB12 */
+#define PIN_PB13 45 /**< \brief Pin Number for PB13 */
+#define PORT_PB13 (1ul << 13) /**< \brief PORT Mask for PB13 */
+#define PIN_PB14 46 /**< \brief Pin Number for PB14 */
+#define PORT_PB14 (1ul << 14) /**< \brief PORT Mask for PB14 */
+#define PIN_PB15 47 /**< \brief Pin Number for PB15 */
+#define PORT_PB15 (1ul << 15) /**< \brief PORT Mask for PB15 */
+#define PIN_PB16 48 /**< \brief Pin Number for PB16 */
+#define PORT_PB16 (1ul << 16) /**< \brief PORT Mask for PB16 */
+#define PIN_PB17 49 /**< \brief Pin Number for PB17 */
+#define PORT_PB17 (1ul << 17) /**< \brief PORT Mask for PB17 */
+#define PIN_PB22 54 /**< \brief Pin Number for PB22 */
+#define PORT_PB22 (1ul << 22) /**< \brief PORT Mask for PB22 */
+#define PIN_PB23 55 /**< \brief Pin Number for PB23 */
+#define PORT_PB23 (1ul << 23) /**< \brief PORT Mask for PB23 */
+#define PIN_PB30 62 /**< \brief Pin Number for PB30 */
+#define PORT_PB30 (1ul << 30) /**< \brief PORT Mask for PB30 */
+#define PIN_PB31 63 /**< \brief Pin Number for PB31 */
+#define PORT_PB31 (1ul << 31) /**< \brief PORT Mask for PB31 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PB14H_GCLK_IO0 46L /**< \brief GCLK signal: IO0 on PB14 mux H */
+#define MUX_PB14H_GCLK_IO0 7L
+#define PINMUX_PB14H_GCLK_IO0 ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0)
+#define PORT_PB14H_GCLK_IO0 (1ul << 14)
+#define PIN_PB22H_GCLK_IO0 54L /**< \brief GCLK signal: IO0 on PB22 mux H */
+#define MUX_PB22H_GCLK_IO0 7L
+#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
+#define PORT_PB22H_GCLK_IO0 (1ul << 22)
+#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0 7L
+#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0 (1ul << 14)
+#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0 7L
+#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0 (1ul << 27)
+#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0 7L
+#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0 (1ul << 28)
+#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0 7L
+#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0 (1ul << 30)
+#define PIN_PB15H_GCLK_IO1 47L /**< \brief GCLK signal: IO1 on PB15 mux H */
+#define MUX_PB15H_GCLK_IO1 7L
+#define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1)
+#define PORT_PB15H_GCLK_IO1 (1ul << 15)
+#define PIN_PB23H_GCLK_IO1 55L /**< \brief GCLK signal: IO1 on PB23 mux H */
+#define MUX_PB23H_GCLK_IO1 7L
+#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
+#define PORT_PB23H_GCLK_IO1 (1ul << 23)
+#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1 7L
+#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1 (1ul << 15)
+#define PIN_PB16H_GCLK_IO2 48L /**< \brief GCLK signal: IO2 on PB16 mux H */
+#define MUX_PB16H_GCLK_IO2 7L
+#define PINMUX_PB16H_GCLK_IO2 ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2)
+#define PORT_PB16H_GCLK_IO2 (1ul << 16)
+#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2 7L
+#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2 (1ul << 16)
+#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3 7L
+#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3 (1ul << 17)
+#define PIN_PB17H_GCLK_IO3 49L /**< \brief GCLK signal: IO3 on PB17 mux H */
+#define MUX_PB17H_GCLK_IO3 7L
+#define PINMUX_PB17H_GCLK_IO3 ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3)
+#define PORT_PB17H_GCLK_IO3 (1ul << 17)
+#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4 7L
+#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4 (1ul << 10)
+#define PIN_PA20H_GCLK_IO4 20L /**< \brief GCLK signal: IO4 on PA20 mux H */
+#define MUX_PA20H_GCLK_IO4 7L
+#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
+#define PORT_PA20H_GCLK_IO4 (1ul << 20)
+#define PIN_PB10H_GCLK_IO4 42L /**< \brief GCLK signal: IO4 on PB10 mux H */
+#define MUX_PB10H_GCLK_IO4 7L
+#define PINMUX_PB10H_GCLK_IO4 ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
+#define PORT_PB10H_GCLK_IO4 (1ul << 10)
+#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5 7L
+#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5 (1ul << 11)
+#define PIN_PA21H_GCLK_IO5 21L /**< \brief GCLK signal: IO5 on PA21 mux H */
+#define MUX_PA21H_GCLK_IO5 7L
+#define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
+#define PORT_PA21H_GCLK_IO5 (1ul << 21)
+#define PIN_PB11H_GCLK_IO5 43L /**< \brief GCLK signal: IO5 on PB11 mux H */
+#define MUX_PB11H_GCLK_IO5 7L
+#define PINMUX_PB11H_GCLK_IO5 ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
+#define PORT_PB11H_GCLK_IO5 (1ul << 11)
+#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6 7L
+#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6 (1ul << 22)
+#define PIN_PB12H_GCLK_IO6 44L /**< \brief GCLK signal: IO6 on PB12 mux H */
+#define MUX_PB12H_GCLK_IO6 7L
+#define PINMUX_PB12H_GCLK_IO6 ((PIN_PB12H_GCLK_IO6 << 16) | MUX_PB12H_GCLK_IO6)
+#define PORT_PB12H_GCLK_IO6 (1ul << 12)
+#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7 7L
+#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7 (1ul << 23)
+#define PIN_PB13H_GCLK_IO7 45L /**< \brief GCLK signal: IO7 on PB13 mux H */
+#define MUX_PB13H_GCLK_IO7 7L
+#define PINMUX_PB13H_GCLK_IO7 ((PIN_PB13H_GCLK_IO7 << 16) | MUX_PB13H_GCLK_IO7)
+#define PORT_PB13H_GCLK_IO7 (1ul << 13)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0 0L
+#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0 (1ul << 16)
+#define PIN_PB00A_EIC_EXTINT0 32L /**< \brief EIC signal: EXTINT0 on PB00 mux A */
+#define MUX_PB00A_EIC_EXTINT0 0L
+#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0)
+#define PORT_PB00A_EIC_EXTINT0 (1ul << 0)
+#define PIN_PB16A_EIC_EXTINT0 48L /**< \brief EIC signal: EXTINT0 on PB16 mux A */
+#define MUX_PB16A_EIC_EXTINT0 0L
+#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0)
+#define PORT_PB16A_EIC_EXTINT0 (1ul << 16)
+#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0 0L
+#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0 (1ul << 0)
+#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1 0L
+#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1 (1ul << 17)
+#define PIN_PB01A_EIC_EXTINT1 33L /**< \brief EIC signal: EXTINT1 on PB01 mux A */
+#define MUX_PB01A_EIC_EXTINT1 0L
+#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1)
+#define PORT_PB01A_EIC_EXTINT1 (1ul << 1)
+#define PIN_PB17A_EIC_EXTINT1 49L /**< \brief EIC signal: EXTINT1 on PB17 mux A */
+#define MUX_PB17A_EIC_EXTINT1 0L
+#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1)
+#define PORT_PB17A_EIC_EXTINT1 (1ul << 17)
+#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1 0L
+#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1 (1ul << 1)
+#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2 0L
+#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2 (1ul << 18)
+#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2 0L
+#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2 (1ul << 2)
+#define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2 0L
+#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2 (1ul << 2)
+#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3 0L
+#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3 (1ul << 3)
+#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3 0L
+#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3 (1ul << 19)
+#define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3 0L
+#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3 (1ul << 3)
+#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4 0L
+#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4 (1ul << 4)
+#define PIN_PA20A_EIC_EXTINT4 20L /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4 0L
+#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4 (1ul << 20)
+#define PIN_PB04A_EIC_EXTINT4 36L /**< \brief EIC signal: EXTINT4 on PB04 mux A */
+#define MUX_PB04A_EIC_EXTINT4 0L
+#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
+#define PORT_PB04A_EIC_EXTINT4 (1ul << 4)
+#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5 0L
+#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5 (1ul << 5)
+#define PIN_PA21A_EIC_EXTINT5 21L /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5 0L
+#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5 (1ul << 21)
+#define PIN_PB05A_EIC_EXTINT5 37L /**< \brief EIC signal: EXTINT5 on PB05 mux A */
+#define MUX_PB05A_EIC_EXTINT5 0L
+#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5)
+#define PORT_PB05A_EIC_EXTINT5 (1ul << 5)
+#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6 0L
+#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6 (1ul << 6)
+#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6 0L
+#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6 (1ul << 22)
+#define PIN_PB06A_EIC_EXTINT6 38L /**< \brief EIC signal: EXTINT6 on PB06 mux A */
+#define MUX_PB06A_EIC_EXTINT6 0L
+#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6)
+#define PORT_PB06A_EIC_EXTINT6 (1ul << 6)
+#define PIN_PB22A_EIC_EXTINT6 54L /**< \brief EIC signal: EXTINT6 on PB22 mux A */
+#define MUX_PB22A_EIC_EXTINT6 0L
+#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
+#define PORT_PB22A_EIC_EXTINT6 (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7 0L
+#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7 (1ul << 7)
+#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7 0L
+#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7 (1ul << 23)
+#define PIN_PB07A_EIC_EXTINT7 39L /**< \brief EIC signal: EXTINT7 on PB07 mux A */
+#define MUX_PB07A_EIC_EXTINT7 0L
+#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7)
+#define PORT_PB07A_EIC_EXTINT7 (1ul << 7)
+#define PIN_PB23A_EIC_EXTINT7 55L /**< \brief EIC signal: EXTINT7 on PB23 mux A */
+#define MUX_PB23A_EIC_EXTINT7 0L
+#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
+#define PORT_PB23A_EIC_EXTINT7 (1ul << 23)
+#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8 0L
+#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8 (1ul << 28)
+#define PIN_PB08A_EIC_EXTINT8 40L /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8 0L
+#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8 (1ul << 8)
+#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9 0L
+#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9 (1ul << 9)
+#define PIN_PB09A_EIC_EXTINT9 41L /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9 0L
+#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9 (1ul << 9)
+#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10 0L
+#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10 (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10 0L
+#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10 (1ul << 30)
+#define PIN_PB10A_EIC_EXTINT10 42L /**< \brief EIC signal: EXTINT10 on PB10 mux A */
+#define MUX_PB10A_EIC_EXTINT10 0L
+#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
+#define PORT_PB10A_EIC_EXTINT10 (1ul << 10)
+#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11 0L
+#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11 (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11 0L
+#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11 (1ul << 31)
+#define PIN_PB11A_EIC_EXTINT11 43L /**< \brief EIC signal: EXTINT11 on PB11 mux A */
+#define MUX_PB11A_EIC_EXTINT11 0L
+#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
+#define PORT_PB11A_EIC_EXTINT11 (1ul << 11)
+#define PIN_PA12A_EIC_EXTINT12 12L /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12 0L
+#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12 (1ul << 12)
+#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12 0L
+#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12 (1ul << 24)
+#define PIN_PB12A_EIC_EXTINT12 44L /**< \brief EIC signal: EXTINT12 on PB12 mux A */
+#define MUX_PB12A_EIC_EXTINT12 0L
+#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12)
+#define PORT_PB12A_EIC_EXTINT12 (1ul << 12)
+#define PIN_PA13A_EIC_EXTINT13 13L /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13 0L
+#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13 (1ul << 13)
+#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13 0L
+#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13 (1ul << 25)
+#define PIN_PB13A_EIC_EXTINT13 45L /**< \brief EIC signal: EXTINT13 on PB13 mux A */
+#define MUX_PB13A_EIC_EXTINT13 0L
+#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13)
+#define PORT_PB13A_EIC_EXTINT13 (1ul << 13)
+#define PIN_PB14A_EIC_EXTINT14 46L /**< \brief EIC signal: EXTINT14 on PB14 mux A */
+#define MUX_PB14A_EIC_EXTINT14 0L
+#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14)
+#define PORT_PB14A_EIC_EXTINT14 (1ul << 14)
+#define PIN_PB30A_EIC_EXTINT14 62L /**< \brief EIC signal: EXTINT14 on PB30 mux A */
+#define MUX_PB30A_EIC_EXTINT14 0L
+#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14)
+#define PORT_PB30A_EIC_EXTINT14 (1ul << 30)
+#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14 0L
+#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14 (1ul << 14)
+#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15 0L
+#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15 (1ul << 15)
+#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15 0L
+#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15 (1ul << 27)
+#define PIN_PB15A_EIC_EXTINT15 47L /**< \brief EIC signal: EXTINT15 on PB15 mux A */
+#define MUX_PB15A_EIC_EXTINT15 0L
+#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15)
+#define PORT_PB15A_EIC_EXTINT15 (1ul << 15)
+#define PIN_PB31A_EIC_EXTINT15 63L /**< \brief EIC signal: EXTINT15 on PB31 mux A */
+#define MUX_PB31A_EIC_EXTINT15 0L
+#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15)
+#define PORT_PB31A_EIC_EXTINT15 (1ul << 31)
+#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI 0L
+#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI (1ul << 8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM 6L
+#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM (1ul << 24)
+#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP 6L
+#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP (1ul << 25)
+#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ 6L
+#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0 3L
+#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4)
+#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0 2L
+#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8)
+#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1 3L
+#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5)
+#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1 2L
+#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9)
+#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2 3L
+#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6)
+#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2 2L
+#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3 3L
+#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7)
+#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3 2L
+#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0 2L
+#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16)
+#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0 3L
+#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0)
+#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1 2L
+#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17)
+#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1 3L
+#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1)
+#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2 3L
+#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2 2L
+#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3 3L
+#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3 2L
+#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0 3L
+#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8)
+#define PIN_PA12C_SERCOM2_PAD0 12L /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0 2L
+#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0 (1ul << 12)
+#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1 3L
+#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9)
+#define PIN_PA13C_SERCOM2_PAD1 13L /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1 2L
+#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1 (1ul << 13)
+#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2 3L
+#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2 2L
+#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3 3L
+#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3 2L
+#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0 3L
+#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0 2L
+#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1 3L
+#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1 2L
+#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2 3L
+#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18)
+#define PIN_PA20D_SERCOM3_PAD2 20L /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2 3L
+#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2 (1ul << 20)
+#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2 2L
+#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3 3L
+#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19)
+#define PIN_PA21D_SERCOM3_PAD3 21L /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3 3L
+#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3 (1ul << 21)
+#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3 2L
+#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA12D_SERCOM4_PAD0 12L /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD0 3L
+#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
+#define PORT_PA12D_SERCOM4_PAD0 (1ul << 12)
+#define PIN_PB08D_SERCOM4_PAD0 40L /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0 3L
+#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0 (1ul << 8)
+#define PIN_PB12C_SERCOM4_PAD0 44L /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */
+#define MUX_PB12C_SERCOM4_PAD0 2L
+#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0)
+#define PORT_PB12C_SERCOM4_PAD0 (1ul << 12)
+#define PIN_PA13D_SERCOM4_PAD1 13L /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD1 3L
+#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
+#define PORT_PA13D_SERCOM4_PAD1 (1ul << 13)
+#define PIN_PB09D_SERCOM4_PAD1 41L /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1 3L
+#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1 (1ul << 9)
+#define PIN_PB13C_SERCOM4_PAD1 45L /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */
+#define MUX_PB13C_SERCOM4_PAD1 2L
+#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1)
+#define PORT_PB13C_SERCOM4_PAD1 (1ul << 13)
+#define PIN_PA14D_SERCOM4_PAD2 14L /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2 3L
+#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2 (1ul << 14)
+#define PIN_PB10D_SERCOM4_PAD2 42L /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
+#define MUX_PB10D_SERCOM4_PAD2 3L
+#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
+#define PORT_PB10D_SERCOM4_PAD2 (1ul << 10)
+#define PIN_PB14C_SERCOM4_PAD2 46L /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */
+#define MUX_PB14C_SERCOM4_PAD2 2L
+#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2)
+#define PORT_PB14C_SERCOM4_PAD2 (1ul << 14)
+#define PIN_PA15D_SERCOM4_PAD3 15L /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3 3L
+#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3 (1ul << 15)
+#define PIN_PB11D_SERCOM4_PAD3 43L /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
+#define MUX_PB11D_SERCOM4_PAD3 3L
+#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
+#define PORT_PB11D_SERCOM4_PAD3 (1ul << 11)
+#define PIN_PB15C_SERCOM4_PAD3 47L /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */
+#define MUX_PB15C_SERCOM4_PAD3 2L
+#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3)
+#define PORT_PB15C_SERCOM4_PAD3 (1ul << 15)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PB16C_SERCOM5_PAD0 48L /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */
+#define MUX_PB16C_SERCOM5_PAD0 2L
+#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0)
+#define PORT_PB16C_SERCOM5_PAD0 (1ul << 16)
+#define PIN_PA22D_SERCOM5_PAD0 22L /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD0 3L
+#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
+#define PORT_PA22D_SERCOM5_PAD0 (1ul << 22)
+#define PIN_PB02D_SERCOM5_PAD0 34L /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0 3L
+#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0 (1ul << 2)
+#define PIN_PB30D_SERCOM5_PAD0 62L /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */
+#define MUX_PB30D_SERCOM5_PAD0 3L
+#define PINMUX_PB30D_SERCOM5_PAD0 ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0)
+#define PORT_PB30D_SERCOM5_PAD0 (1ul << 30)
+#define PIN_PB17C_SERCOM5_PAD1 49L /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */
+#define MUX_PB17C_SERCOM5_PAD1 2L
+#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1)
+#define PORT_PB17C_SERCOM5_PAD1 (1ul << 17)
+#define PIN_PA23D_SERCOM5_PAD1 23L /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD1 3L
+#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
+#define PORT_PA23D_SERCOM5_PAD1 (1ul << 23)
+#define PIN_PB03D_SERCOM5_PAD1 35L /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1 3L
+#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1 (1ul << 3)
+#define PIN_PB31D_SERCOM5_PAD1 63L /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */
+#define MUX_PB31D_SERCOM5_PAD1 3L
+#define PINMUX_PB31D_SERCOM5_PAD1 ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1)
+#define PORT_PB31D_SERCOM5_PAD1 (1ul << 31)
+#define PIN_PA24D_SERCOM5_PAD2 24L /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2 3L
+#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2 (1ul << 24)
+#define PIN_PB00D_SERCOM5_PAD2 32L /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */
+#define MUX_PB00D_SERCOM5_PAD2 3L
+#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2)
+#define PORT_PB00D_SERCOM5_PAD2 (1ul << 0)
+#define PIN_PB22D_SERCOM5_PAD2 54L /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
+#define MUX_PB22D_SERCOM5_PAD2 3L
+#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
+#define PORT_PB22D_SERCOM5_PAD2 (1ul << 22)
+#define PIN_PA20C_SERCOM5_PAD2 20L /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2 2L
+#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2 (1ul << 20)
+#define PIN_PA25D_SERCOM5_PAD3 25L /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3 3L
+#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3 (1ul << 25)
+#define PIN_PB01D_SERCOM5_PAD3 33L /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */
+#define MUX_PB01D_SERCOM5_PAD3 3L
+#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3)
+#define PORT_PB01D_SERCOM5_PAD3 (1ul << 1)
+#define PIN_PB23D_SERCOM5_PAD3 55L /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
+#define MUX_PB23D_SERCOM5_PAD3 3L
+#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
+#define PORT_PB23D_SERCOM5_PAD3 (1ul << 23)
+#define PIN_PA21C_SERCOM5_PAD3 21L /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3 2L
+#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3 (1ul << 21)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0 4L
+#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0 (1ul << 4)
+#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0 4L
+#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0 (1ul << 8)
+#define PIN_PB30E_TCC0_WO0 62L /**< \brief TCC0 signal: WO0 on PB30 mux E */
+#define MUX_PB30E_TCC0_WO0 4L
+#define PINMUX_PB30E_TCC0_WO0 ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0)
+#define PORT_PB30E_TCC0_WO0 (1ul << 30)
+#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1 4L
+#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1 (1ul << 5)
+#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1 4L
+#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1 (1ul << 9)
+#define PIN_PB31E_TCC0_WO1 63L /**< \brief TCC0 signal: WO1 on PB31 mux E */
+#define MUX_PB31E_TCC0_WO1 4L
+#define PINMUX_PB31E_TCC0_WO1 ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1)
+#define PORT_PB31E_TCC0_WO1 (1ul << 31)
+#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2 5L
+#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2 (1ul << 10)
+#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2 5L
+#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2 (1ul << 18)
+#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3 5L
+#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3 (1ul << 11)
+#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3 5L
+#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3 (1ul << 19)
+#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4 5L
+#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4 (1ul << 14)
+#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4 5L
+#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4 (1ul << 22)
+#define PIN_PB10F_TCC0_WO4 42L /**< \brief TCC0 signal: WO4 on PB10 mux F */
+#define MUX_PB10F_TCC0_WO4 5L
+#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
+#define PORT_PB10F_TCC0_WO4 (1ul << 10)
+#define PIN_PB16F_TCC0_WO4 48L /**< \brief TCC0 signal: WO4 on PB16 mux F */
+#define MUX_PB16F_TCC0_WO4 5L
+#define PINMUX_PB16F_TCC0_WO4 ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4)
+#define PORT_PB16F_TCC0_WO4 (1ul << 16)
+#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5 5L
+#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5 (1ul << 15)
+#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5 5L
+#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5 (1ul << 23)
+#define PIN_PB11F_TCC0_WO5 43L /**< \brief TCC0 signal: WO5 on PB11 mux F */
+#define MUX_PB11F_TCC0_WO5 5L
+#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
+#define PORT_PB11F_TCC0_WO5 (1ul << 11)
+#define PIN_PB17F_TCC0_WO5 49L /**< \brief TCC0 signal: WO5 on PB17 mux F */
+#define MUX_PB17F_TCC0_WO5 5L
+#define PINMUX_PB17F_TCC0_WO5 ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5)
+#define PORT_PB17F_TCC0_WO5 (1ul << 17)
+#define PIN_PA12F_TCC0_WO6 12L /**< \brief TCC0 signal: WO6 on PA12 mux F */
+#define MUX_PA12F_TCC0_WO6 5L
+#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
+#define PORT_PA12F_TCC0_WO6 (1ul << 12)
+#define PIN_PA20F_TCC0_WO6 20L /**< \brief TCC0 signal: WO6 on PA20 mux F */
+#define MUX_PA20F_TCC0_WO6 5L
+#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
+#define PORT_PA20F_TCC0_WO6 (1ul << 20)
+#define PIN_PB12F_TCC0_WO6 44L /**< \brief TCC0 signal: WO6 on PB12 mux F */
+#define MUX_PB12F_TCC0_WO6 5L
+#define PINMUX_PB12F_TCC0_WO6 ((PIN_PB12F_TCC0_WO6 << 16) | MUX_PB12F_TCC0_WO6)
+#define PORT_PB12F_TCC0_WO6 (1ul << 12)
+#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6 5L
+#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6 (1ul << 16)
+#define PIN_PA13F_TCC0_WO7 13L /**< \brief TCC0 signal: WO7 on PA13 mux F */
+#define MUX_PA13F_TCC0_WO7 5L
+#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
+#define PORT_PA13F_TCC0_WO7 (1ul << 13)
+#define PIN_PA21F_TCC0_WO7 21L /**< \brief TCC0 signal: WO7 on PA21 mux F */
+#define MUX_PA21F_TCC0_WO7 5L
+#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
+#define PORT_PA21F_TCC0_WO7 (1ul << 21)
+#define PIN_PB13F_TCC0_WO7 45L /**< \brief TCC0 signal: WO7 on PB13 mux F */
+#define MUX_PB13F_TCC0_WO7 5L
+#define PINMUX_PB13F_TCC0_WO7 ((PIN_PB13F_TCC0_WO7 << 16) | MUX_PB13F_TCC0_WO7)
+#define PORT_PB13F_TCC0_WO7 (1ul << 13)
+#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7 5L
+#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7 (1ul << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0 4L
+#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0 (1ul << 6)
+#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0 4L
+#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0 (1ul << 10)
+#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0 4L
+#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0 (1ul << 30)
+#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1 4L
+#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1 (1ul << 7)
+#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1 4L
+#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1 (1ul << 11)
+#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1 4L
+#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1 (1ul << 31)
+#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2 5L
+#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2 (1ul << 8)
+#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2 5L
+#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2 (1ul << 24)
+#define PIN_PB30F_TCC1_WO2 62L /**< \brief TCC1 signal: WO2 on PB30 mux F */
+#define MUX_PB30F_TCC1_WO2 5L
+#define PINMUX_PB30F_TCC1_WO2 ((PIN_PB30F_TCC1_WO2 << 16) | MUX_PB30F_TCC1_WO2)
+#define PORT_PB30F_TCC1_WO2 (1ul << 30)
+#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3 5L
+#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3 (1ul << 9)
+#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3 5L
+#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3 (1ul << 25)
+#define PIN_PB31F_TCC1_WO3 63L /**< \brief TCC1 signal: WO3 on PB31 mux F */
+#define MUX_PB31F_TCC1_WO3 5L
+#define PINMUX_PB31F_TCC1_WO3 ((PIN_PB31F_TCC1_WO3 << 16) | MUX_PB31F_TCC1_WO3)
+#define PORT_PB31F_TCC1_WO3 (1ul << 31)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA12E_TCC2_WO0 12L /**< \brief TCC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TCC2_WO0 4L
+#define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
+#define PORT_PA12E_TCC2_WO0 (1ul << 12)
+#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0 4L
+#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0 (1ul << 16)
+#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0 4L
+#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0 (1ul << 0)
+#define PIN_PA13E_TCC2_WO1 13L /**< \brief TCC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TCC2_WO1 4L
+#define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
+#define PORT_PA13E_TCC2_WO1 (1ul << 13)
+#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1 4L
+#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1 (1ul << 17)
+#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1 4L
+#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1 (1ul << 1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0 4L
+#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0 (1ul << 18)
+#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0 4L
+#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0 (1ul << 14)
+#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1 4L
+#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1 (1ul << 19)
+#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1 4L
+#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1 (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0 4L
+#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0 (1ul << 22)
+#define PIN_PB08E_TC4_WO0 40L /**< \brief TC4 signal: WO0 on PB08 mux E */
+#define MUX_PB08E_TC4_WO0 4L
+#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
+#define PORT_PB08E_TC4_WO0 (1ul << 8)
+#define PIN_PB12E_TC4_WO0 44L /**< \brief TC4 signal: WO0 on PB12 mux E */
+#define MUX_PB12E_TC4_WO0 4L
+#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0)
+#define PORT_PB12E_TC4_WO0 (1ul << 12)
+#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1 4L
+#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1 (1ul << 23)
+#define PIN_PB09E_TC4_WO1 41L /**< \brief TC4 signal: WO1 on PB09 mux E */
+#define MUX_PB09E_TC4_WO1 4L
+#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
+#define PORT_PB09E_TC4_WO1 (1ul << 9)
+#define PIN_PB13E_TC4_WO1 45L /**< \brief TC4 signal: WO1 on PB13 mux E */
+#define MUX_PB13E_TC4_WO1 4L
+#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1)
+#define PORT_PB13E_TC4_WO1 (1ul << 13)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0 4L
+#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0 (1ul << 24)
+#define PIN_PB10E_TC5_WO0 42L /**< \brief TC5 signal: WO0 on PB10 mux E */
+#define MUX_PB10E_TC5_WO0 4L
+#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
+#define PORT_PB10E_TC5_WO0 (1ul << 10)
+#define PIN_PB14E_TC5_WO0 46L /**< \brief TC5 signal: WO0 on PB14 mux E */
+#define MUX_PB14E_TC5_WO0 4L
+#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0)
+#define PORT_PB14E_TC5_WO0 (1ul << 14)
+#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1 4L
+#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1 (1ul << 25)
+#define PIN_PB11E_TC5_WO1 43L /**< \brief TC5 signal: WO1 on PB11 mux E */
+#define MUX_PB11E_TC5_WO1 4L
+#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
+#define PORT_PB11E_TC5_WO1 (1ul << 11)
+#define PIN_PB15E_TC5_WO1 47L /**< \brief TC5 signal: WO1 on PB15 mux E */
+#define MUX_PB15E_TC5_WO1 4L
+#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1)
+#define PORT_PB15E_TC5_WO1 (1ul << 15)
+/* ========== PORT definition for TC6 peripheral ========== */
+#define PIN_PB02E_TC6_WO0 34L /**< \brief TC6 signal: WO0 on PB02 mux E */
+#define MUX_PB02E_TC6_WO0 4L
+#define PINMUX_PB02E_TC6_WO0 ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0)
+#define PORT_PB02E_TC6_WO0 (1ul << 2)
+#define PIN_PB16E_TC6_WO0 48L /**< \brief TC6 signal: WO0 on PB16 mux E */
+#define MUX_PB16E_TC6_WO0 4L
+#define PINMUX_PB16E_TC6_WO0 ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0)
+#define PORT_PB16E_TC6_WO0 (1ul << 16)
+#define PIN_PB03E_TC6_WO1 35L /**< \brief TC6 signal: WO1 on PB03 mux E */
+#define MUX_PB03E_TC6_WO1 4L
+#define PINMUX_PB03E_TC6_WO1 ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1)
+#define PORT_PB03E_TC6_WO1 (1ul << 3)
+#define PIN_PB17E_TC6_WO1 49L /**< \brief TC6 signal: WO1 on PB17 mux E */
+#define MUX_PB17E_TC6_WO1 4L
+#define PINMUX_PB17E_TC6_WO1 ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1)
+#define PORT_PB17E_TC6_WO1 (1ul << 17)
+/* ========== PORT definition for TC7 peripheral ========== */
+#define PIN_PA20E_TC7_WO0 20L /**< \brief TC7 signal: WO0 on PA20 mux E */
+#define MUX_PA20E_TC7_WO0 4L
+#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0)
+#define PORT_PA20E_TC7_WO0 (1ul << 20)
+#define PIN_PB00E_TC7_WO0 32L /**< \brief TC7 signal: WO0 on PB00 mux E */
+#define MUX_PB00E_TC7_WO0 4L
+#define PINMUX_PB00E_TC7_WO0 ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0)
+#define PORT_PB00E_TC7_WO0 (1ul << 0)
+#define PIN_PB22E_TC7_WO0 54L /**< \brief TC7 signal: WO0 on PB22 mux E */
+#define MUX_PB22E_TC7_WO0 4L
+#define PINMUX_PB22E_TC7_WO0 ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0)
+#define PORT_PB22E_TC7_WO0 (1ul << 22)
+#define PIN_PA21E_TC7_WO1 21L /**< \brief TC7 signal: WO1 on PA21 mux E */
+#define MUX_PA21E_TC7_WO1 4L
+#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1)
+#define PORT_PA21E_TC7_WO1 (1ul << 21)
+#define PIN_PB01E_TC7_WO1 33L /**< \brief TC7 signal: WO1 on PB01 mux E */
+#define MUX_PB01E_TC7_WO1 4L
+#define PINMUX_PB01E_TC7_WO1 ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1)
+#define PORT_PB01E_TC7_WO1 (1ul << 1)
+#define PIN_PB23E_TC7_WO1 55L /**< \brief TC7 signal: WO1 on PB23 mux E */
+#define MUX_PB23E_TC7_WO1 4L
+#define PINMUX_PB23E_TC7_WO1 ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1)
+#define PORT_PB23E_TC7_WO1 (1ul << 23)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0 1L
+#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0 (1ul << 2)
+#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1 1L
+#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1 (1ul << 3)
+#define PIN_PB08B_ADC_AIN2 40L /**< \brief ADC signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC_AIN2 1L
+#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
+#define PORT_PB08B_ADC_AIN2 (1ul << 8)
+#define PIN_PB09B_ADC_AIN3 41L /**< \brief ADC signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC_AIN3 1L
+#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
+#define PORT_PB09B_ADC_AIN3 (1ul << 9)
+#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4 1L
+#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4 (1ul << 4)
+#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5 1L
+#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5 (1ul << 5)
+#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6 1L
+#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6 (1ul << 6)
+#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7 1L
+#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7 (1ul << 7)
+#define PIN_PB00B_ADC_AIN8 32L /**< \brief ADC signal: AIN8 on PB00 mux B */
+#define MUX_PB00B_ADC_AIN8 1L
+#define PINMUX_PB00B_ADC_AIN8 ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8)
+#define PORT_PB00B_ADC_AIN8 (1ul << 0)
+#define PIN_PB01B_ADC_AIN9 33L /**< \brief ADC signal: AIN9 on PB01 mux B */
+#define MUX_PB01B_ADC_AIN9 1L
+#define PINMUX_PB01B_ADC_AIN9 ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9)
+#define PORT_PB01B_ADC_AIN9 (1ul << 1)
+#define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */
+#define MUX_PB02B_ADC_AIN10 1L
+#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
+#define PORT_PB02B_ADC_AIN10 (1ul << 2)
+#define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */
+#define MUX_PB03B_ADC_AIN11 1L
+#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
+#define PORT_PB03B_ADC_AIN11 (1ul << 3)
+#define PIN_PB04B_ADC_AIN12 36L /**< \brief ADC signal: AIN12 on PB04 mux B */
+#define MUX_PB04B_ADC_AIN12 1L
+#define PINMUX_PB04B_ADC_AIN12 ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12)
+#define PORT_PB04B_ADC_AIN12 (1ul << 4)
+#define PIN_PB05B_ADC_AIN13 37L /**< \brief ADC signal: AIN13 on PB05 mux B */
+#define MUX_PB05B_ADC_AIN13 1L
+#define PINMUX_PB05B_ADC_AIN13 ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13)
+#define PORT_PB05B_ADC_AIN13 (1ul << 5)
+#define PIN_PB06B_ADC_AIN14 38L /**< \brief ADC signal: AIN14 on PB06 mux B */
+#define MUX_PB06B_ADC_AIN14 1L
+#define PINMUX_PB06B_ADC_AIN14 ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14)
+#define PORT_PB06B_ADC_AIN14 (1ul << 6)
+#define PIN_PB07B_ADC_AIN15 39L /**< \brief ADC signal: AIN15 on PB07 mux B */
+#define MUX_PB07B_ADC_AIN15 1L
+#define PINMUX_PB07B_ADC_AIN15 ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15)
+#define PORT_PB07B_ADC_AIN15 (1ul << 7)
+#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16 1L
+#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16 (1ul << 8)
+#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17 1L
+#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17 (1ul << 9)
+#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18 1L
+#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18 (1ul << 10)
+#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19 1L
+#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19 (1ul << 11)
+#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP 1L
+#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP (1ul << 4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0 1L
+#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0 (1ul << 4)
+#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1 1L
+#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1 (1ul << 5)
+#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2 1L
+#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2 (1ul << 6)
+#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3 1L
+#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3 (1ul << 7)
+#define PIN_PA12H_AC_CMP0 12L /**< \brief AC signal: CMP0 on PA12 mux H */
+#define MUX_PA12H_AC_CMP0 7L
+#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
+#define PORT_PA12H_AC_CMP0 (1ul << 12)
+#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0 7L
+#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0 (1ul << 18)
+#define PIN_PA13H_AC_CMP1 13L /**< \brief AC signal: CMP1 on PA13 mux H */
+#define MUX_PA13H_AC_CMP1 7L
+#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
+#define PORT_PA13H_AC_CMP1 (1ul << 13)
+#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1 7L
+#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1 (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT 1L
+#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT (1ul << 2)
+#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP 1L
+#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP (1ul << 3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0 11L /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0 6L
+#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0 (1ul << 11)
+#define PIN_PA21G_I2S_FS0 21L /**< \brief I2S signal: FS0 on PA21 mux G */
+#define MUX_PA21G_I2S_FS0 6L
+#define PINMUX_PA21G_I2S_FS0 ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
+#define PORT_PA21G_I2S_FS0 (1ul << 21)
+#define PIN_PB12G_I2S_FS1 44L /**< \brief I2S signal: FS1 on PB12 mux G */
+#define MUX_PB12G_I2S_FS1 6L
+#define PINMUX_PB12G_I2S_FS1 ((PIN_PB12G_I2S_FS1 << 16) | MUX_PB12G_I2S_FS1)
+#define PORT_PB12G_I2S_FS1 (1ul << 12)
+#define PIN_PA09G_I2S_MCK0 9L /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0 6L
+#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0 (1ul << 9)
+#define PIN_PB17G_I2S_MCK0 49L /**< \brief I2S signal: MCK0 on PB17 mux G */
+#define MUX_PB17G_I2S_MCK0 6L
+#define PINMUX_PB17G_I2S_MCK0 ((PIN_PB17G_I2S_MCK0 << 16) | MUX_PB17G_I2S_MCK0)
+#define PORT_PB17G_I2S_MCK0 (1ul << 17)
+#define PIN_PB10G_I2S_MCK1 42L /**< \brief I2S signal: MCK1 on PB10 mux G */
+#define MUX_PB10G_I2S_MCK1 6L
+#define PINMUX_PB10G_I2S_MCK1 ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1)
+#define PORT_PB10G_I2S_MCK1 (1ul << 10)
+#define PIN_PA10G_I2S_SCK0 10L /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0 6L
+#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0 (1ul << 10)
+#define PIN_PA20G_I2S_SCK0 20L /**< \brief I2S signal: SCK0 on PA20 mux G */
+#define MUX_PA20G_I2S_SCK0 6L
+#define PINMUX_PA20G_I2S_SCK0 ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
+#define PORT_PA20G_I2S_SCK0 (1ul << 20)
+#define PIN_PB11G_I2S_SCK1 43L /**< \brief I2S signal: SCK1 on PB11 mux G */
+#define MUX_PB11G_I2S_SCK1 6L
+#define PINMUX_PB11G_I2S_SCK1 ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1)
+#define PORT_PB11G_I2S_SCK1 (1ul << 11)
+#define PIN_PA07G_I2S_SD0 7L /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0 6L
+#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0 (1ul << 7)
+#define PIN_PA19G_I2S_SD0 19L /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0 6L
+#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0 (1ul << 19)
+#define PIN_PA08G_I2S_SD1 8L /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1 6L
+#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1 (1ul << 8)
+#define PIN_PB16G_I2S_SD1 48L /**< \brief I2S signal: SD1 on PB16 mux G */
+#define MUX_PB16G_I2S_SD1 6L
+#define PINMUX_PB16G_I2S_SD1 ((PIN_PB16G_I2S_SD1 << 16) | MUX_PB16G_I2S_SD1)
+#define PORT_PB16G_I2S_SD1 (1ul << 16)
+
+#endif /* _SAMD21J16A_PIO_ */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/pio/samd21j17a.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/pio/samd21j17a.h
new file mode 100644
index 0000000000000000000000000000000000000000..979447f481050d4174c5d9aa244ab6d0a736f0ef
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/pio/samd21j17a.h
@@ -0,0 +1,1189 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21J17A
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21J17A_PIO_
+#define _SAMD21J17A_PIO_
+
+#define PIN_PA00 0 /**< \brief Pin Number for PA00 */
+#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */
+#define PIN_PA01 1 /**< \brief Pin Number for PA01 */
+#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */
+#define PIN_PA02 2 /**< \brief Pin Number for PA02 */
+#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */
+#define PIN_PA03 3 /**< \brief Pin Number for PA03 */
+#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */
+#define PIN_PA04 4 /**< \brief Pin Number for PA04 */
+#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */
+#define PIN_PA05 5 /**< \brief Pin Number for PA05 */
+#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */
+#define PIN_PA06 6 /**< \brief Pin Number for PA06 */
+#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */
+#define PIN_PA07 7 /**< \brief Pin Number for PA07 */
+#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */
+#define PIN_PA08 8 /**< \brief Pin Number for PA08 */
+#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */
+#define PIN_PA09 9 /**< \brief Pin Number for PA09 */
+#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */
+#define PIN_PA10 10 /**< \brief Pin Number for PA10 */
+#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */
+#define PIN_PA11 11 /**< \brief Pin Number for PA11 */
+#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */
+#define PIN_PA12 12 /**< \brief Pin Number for PA12 */
+#define PORT_PA12 (1ul << 12) /**< \brief PORT Mask for PA12 */
+#define PIN_PA13 13 /**< \brief Pin Number for PA13 */
+#define PORT_PA13 (1ul << 13) /**< \brief PORT Mask for PA13 */
+#define PIN_PA14 14 /**< \brief Pin Number for PA14 */
+#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */
+#define PIN_PA15 15 /**< \brief Pin Number for PA15 */
+#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */
+#define PIN_PA16 16 /**< \brief Pin Number for PA16 */
+#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */
+#define PIN_PA17 17 /**< \brief Pin Number for PA17 */
+#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */
+#define PIN_PA18 18 /**< \brief Pin Number for PA18 */
+#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */
+#define PIN_PA19 19 /**< \brief Pin Number for PA19 */
+#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */
+#define PIN_PA20 20 /**< \brief Pin Number for PA20 */
+#define PORT_PA20 (1ul << 20) /**< \brief PORT Mask for PA20 */
+#define PIN_PA21 21 /**< \brief Pin Number for PA21 */
+#define PORT_PA21 (1ul << 21) /**< \brief PORT Mask for PA21 */
+#define PIN_PA22 22 /**< \brief Pin Number for PA22 */
+#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */
+#define PIN_PA23 23 /**< \brief Pin Number for PA23 */
+#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */
+#define PIN_PA24 24 /**< \brief Pin Number for PA24 */
+#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */
+#define PIN_PA25 25 /**< \brief Pin Number for PA25 */
+#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */
+#define PIN_PA27 27 /**< \brief Pin Number for PA27 */
+#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */
+#define PIN_PA28 28 /**< \brief Pin Number for PA28 */
+#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */
+#define PIN_PA30 30 /**< \brief Pin Number for PA30 */
+#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */
+#define PIN_PA31 31 /**< \brief Pin Number for PA31 */
+#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */
+#define PIN_PB00 32 /**< \brief Pin Number for PB00 */
+#define PORT_PB00 (1ul << 0) /**< \brief PORT Mask for PB00 */
+#define PIN_PB01 33 /**< \brief Pin Number for PB01 */
+#define PORT_PB01 (1ul << 1) /**< \brief PORT Mask for PB01 */
+#define PIN_PB02 34 /**< \brief Pin Number for PB02 */
+#define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */
+#define PIN_PB03 35 /**< \brief Pin Number for PB03 */
+#define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */
+#define PIN_PB04 36 /**< \brief Pin Number for PB04 */
+#define PORT_PB04 (1ul << 4) /**< \brief PORT Mask for PB04 */
+#define PIN_PB05 37 /**< \brief Pin Number for PB05 */
+#define PORT_PB05 (1ul << 5) /**< \brief PORT Mask for PB05 */
+#define PIN_PB06 38 /**< \brief Pin Number for PB06 */
+#define PORT_PB06 (1ul << 6) /**< \brief PORT Mask for PB06 */
+#define PIN_PB07 39 /**< \brief Pin Number for PB07 */
+#define PORT_PB07 (1ul << 7) /**< \brief PORT Mask for PB07 */
+#define PIN_PB08 40 /**< \brief Pin Number for PB08 */
+#define PORT_PB08 (1ul << 8) /**< \brief PORT Mask for PB08 */
+#define PIN_PB09 41 /**< \brief Pin Number for PB09 */
+#define PORT_PB09 (1ul << 9) /**< \brief PORT Mask for PB09 */
+#define PIN_PB10 42 /**< \brief Pin Number for PB10 */
+#define PORT_PB10 (1ul << 10) /**< \brief PORT Mask for PB10 */
+#define PIN_PB11 43 /**< \brief Pin Number for PB11 */
+#define PORT_PB11 (1ul << 11) /**< \brief PORT Mask for PB11 */
+#define PIN_PB12 44 /**< \brief Pin Number for PB12 */
+#define PORT_PB12 (1ul << 12) /**< \brief PORT Mask for PB12 */
+#define PIN_PB13 45 /**< \brief Pin Number for PB13 */
+#define PORT_PB13 (1ul << 13) /**< \brief PORT Mask for PB13 */
+#define PIN_PB14 46 /**< \brief Pin Number for PB14 */
+#define PORT_PB14 (1ul << 14) /**< \brief PORT Mask for PB14 */
+#define PIN_PB15 47 /**< \brief Pin Number for PB15 */
+#define PORT_PB15 (1ul << 15) /**< \brief PORT Mask for PB15 */
+#define PIN_PB16 48 /**< \brief Pin Number for PB16 */
+#define PORT_PB16 (1ul << 16) /**< \brief PORT Mask for PB16 */
+#define PIN_PB17 49 /**< \brief Pin Number for PB17 */
+#define PORT_PB17 (1ul << 17) /**< \brief PORT Mask for PB17 */
+#define PIN_PB22 54 /**< \brief Pin Number for PB22 */
+#define PORT_PB22 (1ul << 22) /**< \brief PORT Mask for PB22 */
+#define PIN_PB23 55 /**< \brief Pin Number for PB23 */
+#define PORT_PB23 (1ul << 23) /**< \brief PORT Mask for PB23 */
+#define PIN_PB30 62 /**< \brief Pin Number for PB30 */
+#define PORT_PB30 (1ul << 30) /**< \brief PORT Mask for PB30 */
+#define PIN_PB31 63 /**< \brief Pin Number for PB31 */
+#define PORT_PB31 (1ul << 31) /**< \brief PORT Mask for PB31 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PB14H_GCLK_IO0 46L /**< \brief GCLK signal: IO0 on PB14 mux H */
+#define MUX_PB14H_GCLK_IO0 7L
+#define PINMUX_PB14H_GCLK_IO0 ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0)
+#define PORT_PB14H_GCLK_IO0 (1ul << 14)
+#define PIN_PB22H_GCLK_IO0 54L /**< \brief GCLK signal: IO0 on PB22 mux H */
+#define MUX_PB22H_GCLK_IO0 7L
+#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
+#define PORT_PB22H_GCLK_IO0 (1ul << 22)
+#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0 7L
+#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0 (1ul << 14)
+#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0 7L
+#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0 (1ul << 27)
+#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0 7L
+#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0 (1ul << 28)
+#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0 7L
+#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0 (1ul << 30)
+#define PIN_PB15H_GCLK_IO1 47L /**< \brief GCLK signal: IO1 on PB15 mux H */
+#define MUX_PB15H_GCLK_IO1 7L
+#define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1)
+#define PORT_PB15H_GCLK_IO1 (1ul << 15)
+#define PIN_PB23H_GCLK_IO1 55L /**< \brief GCLK signal: IO1 on PB23 mux H */
+#define MUX_PB23H_GCLK_IO1 7L
+#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
+#define PORT_PB23H_GCLK_IO1 (1ul << 23)
+#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1 7L
+#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1 (1ul << 15)
+#define PIN_PB16H_GCLK_IO2 48L /**< \brief GCLK signal: IO2 on PB16 mux H */
+#define MUX_PB16H_GCLK_IO2 7L
+#define PINMUX_PB16H_GCLK_IO2 ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2)
+#define PORT_PB16H_GCLK_IO2 (1ul << 16)
+#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2 7L
+#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2 (1ul << 16)
+#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3 7L
+#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3 (1ul << 17)
+#define PIN_PB17H_GCLK_IO3 49L /**< \brief GCLK signal: IO3 on PB17 mux H */
+#define MUX_PB17H_GCLK_IO3 7L
+#define PINMUX_PB17H_GCLK_IO3 ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3)
+#define PORT_PB17H_GCLK_IO3 (1ul << 17)
+#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4 7L
+#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4 (1ul << 10)
+#define PIN_PA20H_GCLK_IO4 20L /**< \brief GCLK signal: IO4 on PA20 mux H */
+#define MUX_PA20H_GCLK_IO4 7L
+#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
+#define PORT_PA20H_GCLK_IO4 (1ul << 20)
+#define PIN_PB10H_GCLK_IO4 42L /**< \brief GCLK signal: IO4 on PB10 mux H */
+#define MUX_PB10H_GCLK_IO4 7L
+#define PINMUX_PB10H_GCLK_IO4 ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
+#define PORT_PB10H_GCLK_IO4 (1ul << 10)
+#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5 7L
+#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5 (1ul << 11)
+#define PIN_PA21H_GCLK_IO5 21L /**< \brief GCLK signal: IO5 on PA21 mux H */
+#define MUX_PA21H_GCLK_IO5 7L
+#define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
+#define PORT_PA21H_GCLK_IO5 (1ul << 21)
+#define PIN_PB11H_GCLK_IO5 43L /**< \brief GCLK signal: IO5 on PB11 mux H */
+#define MUX_PB11H_GCLK_IO5 7L
+#define PINMUX_PB11H_GCLK_IO5 ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
+#define PORT_PB11H_GCLK_IO5 (1ul << 11)
+#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6 7L
+#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6 (1ul << 22)
+#define PIN_PB12H_GCLK_IO6 44L /**< \brief GCLK signal: IO6 on PB12 mux H */
+#define MUX_PB12H_GCLK_IO6 7L
+#define PINMUX_PB12H_GCLK_IO6 ((PIN_PB12H_GCLK_IO6 << 16) | MUX_PB12H_GCLK_IO6)
+#define PORT_PB12H_GCLK_IO6 (1ul << 12)
+#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7 7L
+#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7 (1ul << 23)
+#define PIN_PB13H_GCLK_IO7 45L /**< \brief GCLK signal: IO7 on PB13 mux H */
+#define MUX_PB13H_GCLK_IO7 7L
+#define PINMUX_PB13H_GCLK_IO7 ((PIN_PB13H_GCLK_IO7 << 16) | MUX_PB13H_GCLK_IO7)
+#define PORT_PB13H_GCLK_IO7 (1ul << 13)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0 0L
+#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0 (1ul << 16)
+#define PIN_PB00A_EIC_EXTINT0 32L /**< \brief EIC signal: EXTINT0 on PB00 mux A */
+#define MUX_PB00A_EIC_EXTINT0 0L
+#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0)
+#define PORT_PB00A_EIC_EXTINT0 (1ul << 0)
+#define PIN_PB16A_EIC_EXTINT0 48L /**< \brief EIC signal: EXTINT0 on PB16 mux A */
+#define MUX_PB16A_EIC_EXTINT0 0L
+#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0)
+#define PORT_PB16A_EIC_EXTINT0 (1ul << 16)
+#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0 0L
+#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0 (1ul << 0)
+#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1 0L
+#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1 (1ul << 17)
+#define PIN_PB01A_EIC_EXTINT1 33L /**< \brief EIC signal: EXTINT1 on PB01 mux A */
+#define MUX_PB01A_EIC_EXTINT1 0L
+#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1)
+#define PORT_PB01A_EIC_EXTINT1 (1ul << 1)
+#define PIN_PB17A_EIC_EXTINT1 49L /**< \brief EIC signal: EXTINT1 on PB17 mux A */
+#define MUX_PB17A_EIC_EXTINT1 0L
+#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1)
+#define PORT_PB17A_EIC_EXTINT1 (1ul << 17)
+#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1 0L
+#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1 (1ul << 1)
+#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2 0L
+#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2 (1ul << 18)
+#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2 0L
+#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2 (1ul << 2)
+#define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2 0L
+#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2 (1ul << 2)
+#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3 0L
+#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3 (1ul << 3)
+#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3 0L
+#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3 (1ul << 19)
+#define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3 0L
+#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3 (1ul << 3)
+#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4 0L
+#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4 (1ul << 4)
+#define PIN_PA20A_EIC_EXTINT4 20L /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4 0L
+#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4 (1ul << 20)
+#define PIN_PB04A_EIC_EXTINT4 36L /**< \brief EIC signal: EXTINT4 on PB04 mux A */
+#define MUX_PB04A_EIC_EXTINT4 0L
+#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
+#define PORT_PB04A_EIC_EXTINT4 (1ul << 4)
+#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5 0L
+#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5 (1ul << 5)
+#define PIN_PA21A_EIC_EXTINT5 21L /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5 0L
+#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5 (1ul << 21)
+#define PIN_PB05A_EIC_EXTINT5 37L /**< \brief EIC signal: EXTINT5 on PB05 mux A */
+#define MUX_PB05A_EIC_EXTINT5 0L
+#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5)
+#define PORT_PB05A_EIC_EXTINT5 (1ul << 5)
+#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6 0L
+#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6 (1ul << 6)
+#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6 0L
+#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6 (1ul << 22)
+#define PIN_PB06A_EIC_EXTINT6 38L /**< \brief EIC signal: EXTINT6 on PB06 mux A */
+#define MUX_PB06A_EIC_EXTINT6 0L
+#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6)
+#define PORT_PB06A_EIC_EXTINT6 (1ul << 6)
+#define PIN_PB22A_EIC_EXTINT6 54L /**< \brief EIC signal: EXTINT6 on PB22 mux A */
+#define MUX_PB22A_EIC_EXTINT6 0L
+#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
+#define PORT_PB22A_EIC_EXTINT6 (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7 0L
+#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7 (1ul << 7)
+#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7 0L
+#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7 (1ul << 23)
+#define PIN_PB07A_EIC_EXTINT7 39L /**< \brief EIC signal: EXTINT7 on PB07 mux A */
+#define MUX_PB07A_EIC_EXTINT7 0L
+#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7)
+#define PORT_PB07A_EIC_EXTINT7 (1ul << 7)
+#define PIN_PB23A_EIC_EXTINT7 55L /**< \brief EIC signal: EXTINT7 on PB23 mux A */
+#define MUX_PB23A_EIC_EXTINT7 0L
+#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
+#define PORT_PB23A_EIC_EXTINT7 (1ul << 23)
+#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8 0L
+#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8 (1ul << 28)
+#define PIN_PB08A_EIC_EXTINT8 40L /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8 0L
+#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8 (1ul << 8)
+#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9 0L
+#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9 (1ul << 9)
+#define PIN_PB09A_EIC_EXTINT9 41L /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9 0L
+#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9 (1ul << 9)
+#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10 0L
+#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10 (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10 0L
+#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10 (1ul << 30)
+#define PIN_PB10A_EIC_EXTINT10 42L /**< \brief EIC signal: EXTINT10 on PB10 mux A */
+#define MUX_PB10A_EIC_EXTINT10 0L
+#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
+#define PORT_PB10A_EIC_EXTINT10 (1ul << 10)
+#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11 0L
+#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11 (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11 0L
+#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11 (1ul << 31)
+#define PIN_PB11A_EIC_EXTINT11 43L /**< \brief EIC signal: EXTINT11 on PB11 mux A */
+#define MUX_PB11A_EIC_EXTINT11 0L
+#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
+#define PORT_PB11A_EIC_EXTINT11 (1ul << 11)
+#define PIN_PA12A_EIC_EXTINT12 12L /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12 0L
+#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12 (1ul << 12)
+#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12 0L
+#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12 (1ul << 24)
+#define PIN_PB12A_EIC_EXTINT12 44L /**< \brief EIC signal: EXTINT12 on PB12 mux A */
+#define MUX_PB12A_EIC_EXTINT12 0L
+#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12)
+#define PORT_PB12A_EIC_EXTINT12 (1ul << 12)
+#define PIN_PA13A_EIC_EXTINT13 13L /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13 0L
+#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13 (1ul << 13)
+#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13 0L
+#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13 (1ul << 25)
+#define PIN_PB13A_EIC_EXTINT13 45L /**< \brief EIC signal: EXTINT13 on PB13 mux A */
+#define MUX_PB13A_EIC_EXTINT13 0L
+#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13)
+#define PORT_PB13A_EIC_EXTINT13 (1ul << 13)
+#define PIN_PB14A_EIC_EXTINT14 46L /**< \brief EIC signal: EXTINT14 on PB14 mux A */
+#define MUX_PB14A_EIC_EXTINT14 0L
+#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14)
+#define PORT_PB14A_EIC_EXTINT14 (1ul << 14)
+#define PIN_PB30A_EIC_EXTINT14 62L /**< \brief EIC signal: EXTINT14 on PB30 mux A */
+#define MUX_PB30A_EIC_EXTINT14 0L
+#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14)
+#define PORT_PB30A_EIC_EXTINT14 (1ul << 30)
+#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14 0L
+#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14 (1ul << 14)
+#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15 0L
+#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15 (1ul << 15)
+#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15 0L
+#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15 (1ul << 27)
+#define PIN_PB15A_EIC_EXTINT15 47L /**< \brief EIC signal: EXTINT15 on PB15 mux A */
+#define MUX_PB15A_EIC_EXTINT15 0L
+#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15)
+#define PORT_PB15A_EIC_EXTINT15 (1ul << 15)
+#define PIN_PB31A_EIC_EXTINT15 63L /**< \brief EIC signal: EXTINT15 on PB31 mux A */
+#define MUX_PB31A_EIC_EXTINT15 0L
+#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15)
+#define PORT_PB31A_EIC_EXTINT15 (1ul << 31)
+#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI 0L
+#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI (1ul << 8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM 6L
+#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM (1ul << 24)
+#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP 6L
+#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP (1ul << 25)
+#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ 6L
+#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0 3L
+#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4)
+#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0 2L
+#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8)
+#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1 3L
+#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5)
+#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1 2L
+#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9)
+#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2 3L
+#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6)
+#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2 2L
+#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3 3L
+#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7)
+#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3 2L
+#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0 2L
+#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16)
+#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0 3L
+#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0)
+#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1 2L
+#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17)
+#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1 3L
+#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1)
+#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2 3L
+#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2 2L
+#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3 3L
+#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3 2L
+#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0 3L
+#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8)
+#define PIN_PA12C_SERCOM2_PAD0 12L /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0 2L
+#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0 (1ul << 12)
+#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1 3L
+#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9)
+#define PIN_PA13C_SERCOM2_PAD1 13L /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1 2L
+#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1 (1ul << 13)
+#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2 3L
+#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2 2L
+#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3 3L
+#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3 2L
+#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0 3L
+#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0 2L
+#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1 3L
+#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1 2L
+#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2 3L
+#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18)
+#define PIN_PA20D_SERCOM3_PAD2 20L /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2 3L
+#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2 (1ul << 20)
+#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2 2L
+#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3 3L
+#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19)
+#define PIN_PA21D_SERCOM3_PAD3 21L /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3 3L
+#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3 (1ul << 21)
+#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3 2L
+#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA12D_SERCOM4_PAD0 12L /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD0 3L
+#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
+#define PORT_PA12D_SERCOM4_PAD0 (1ul << 12)
+#define PIN_PB08D_SERCOM4_PAD0 40L /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0 3L
+#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0 (1ul << 8)
+#define PIN_PB12C_SERCOM4_PAD0 44L /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */
+#define MUX_PB12C_SERCOM4_PAD0 2L
+#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0)
+#define PORT_PB12C_SERCOM4_PAD0 (1ul << 12)
+#define PIN_PA13D_SERCOM4_PAD1 13L /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD1 3L
+#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
+#define PORT_PA13D_SERCOM4_PAD1 (1ul << 13)
+#define PIN_PB09D_SERCOM4_PAD1 41L /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1 3L
+#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1 (1ul << 9)
+#define PIN_PB13C_SERCOM4_PAD1 45L /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */
+#define MUX_PB13C_SERCOM4_PAD1 2L
+#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1)
+#define PORT_PB13C_SERCOM4_PAD1 (1ul << 13)
+#define PIN_PA14D_SERCOM4_PAD2 14L /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2 3L
+#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2 (1ul << 14)
+#define PIN_PB10D_SERCOM4_PAD2 42L /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
+#define MUX_PB10D_SERCOM4_PAD2 3L
+#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
+#define PORT_PB10D_SERCOM4_PAD2 (1ul << 10)
+#define PIN_PB14C_SERCOM4_PAD2 46L /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */
+#define MUX_PB14C_SERCOM4_PAD2 2L
+#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2)
+#define PORT_PB14C_SERCOM4_PAD2 (1ul << 14)
+#define PIN_PA15D_SERCOM4_PAD3 15L /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3 3L
+#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3 (1ul << 15)
+#define PIN_PB11D_SERCOM4_PAD3 43L /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
+#define MUX_PB11D_SERCOM4_PAD3 3L
+#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
+#define PORT_PB11D_SERCOM4_PAD3 (1ul << 11)
+#define PIN_PB15C_SERCOM4_PAD3 47L /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */
+#define MUX_PB15C_SERCOM4_PAD3 2L
+#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3)
+#define PORT_PB15C_SERCOM4_PAD3 (1ul << 15)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PB16C_SERCOM5_PAD0 48L /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */
+#define MUX_PB16C_SERCOM5_PAD0 2L
+#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0)
+#define PORT_PB16C_SERCOM5_PAD0 (1ul << 16)
+#define PIN_PA22D_SERCOM5_PAD0 22L /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD0 3L
+#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
+#define PORT_PA22D_SERCOM5_PAD0 (1ul << 22)
+#define PIN_PB02D_SERCOM5_PAD0 34L /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0 3L
+#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0 (1ul << 2)
+#define PIN_PB30D_SERCOM5_PAD0 62L /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */
+#define MUX_PB30D_SERCOM5_PAD0 3L
+#define PINMUX_PB30D_SERCOM5_PAD0 ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0)
+#define PORT_PB30D_SERCOM5_PAD0 (1ul << 30)
+#define PIN_PB17C_SERCOM5_PAD1 49L /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */
+#define MUX_PB17C_SERCOM5_PAD1 2L
+#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1)
+#define PORT_PB17C_SERCOM5_PAD1 (1ul << 17)
+#define PIN_PA23D_SERCOM5_PAD1 23L /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD1 3L
+#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
+#define PORT_PA23D_SERCOM5_PAD1 (1ul << 23)
+#define PIN_PB03D_SERCOM5_PAD1 35L /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1 3L
+#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1 (1ul << 3)
+#define PIN_PB31D_SERCOM5_PAD1 63L /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */
+#define MUX_PB31D_SERCOM5_PAD1 3L
+#define PINMUX_PB31D_SERCOM5_PAD1 ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1)
+#define PORT_PB31D_SERCOM5_PAD1 (1ul << 31)
+#define PIN_PA24D_SERCOM5_PAD2 24L /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2 3L
+#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2 (1ul << 24)
+#define PIN_PB00D_SERCOM5_PAD2 32L /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */
+#define MUX_PB00D_SERCOM5_PAD2 3L
+#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2)
+#define PORT_PB00D_SERCOM5_PAD2 (1ul << 0)
+#define PIN_PB22D_SERCOM5_PAD2 54L /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
+#define MUX_PB22D_SERCOM5_PAD2 3L
+#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
+#define PORT_PB22D_SERCOM5_PAD2 (1ul << 22)
+#define PIN_PA20C_SERCOM5_PAD2 20L /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2 2L
+#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2 (1ul << 20)
+#define PIN_PA25D_SERCOM5_PAD3 25L /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3 3L
+#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3 (1ul << 25)
+#define PIN_PB01D_SERCOM5_PAD3 33L /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */
+#define MUX_PB01D_SERCOM5_PAD3 3L
+#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3)
+#define PORT_PB01D_SERCOM5_PAD3 (1ul << 1)
+#define PIN_PB23D_SERCOM5_PAD3 55L /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
+#define MUX_PB23D_SERCOM5_PAD3 3L
+#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
+#define PORT_PB23D_SERCOM5_PAD3 (1ul << 23)
+#define PIN_PA21C_SERCOM5_PAD3 21L /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3 2L
+#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3 (1ul << 21)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0 4L
+#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0 (1ul << 4)
+#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0 4L
+#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0 (1ul << 8)
+#define PIN_PB30E_TCC0_WO0 62L /**< \brief TCC0 signal: WO0 on PB30 mux E */
+#define MUX_PB30E_TCC0_WO0 4L
+#define PINMUX_PB30E_TCC0_WO0 ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0)
+#define PORT_PB30E_TCC0_WO0 (1ul << 30)
+#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1 4L
+#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1 (1ul << 5)
+#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1 4L
+#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1 (1ul << 9)
+#define PIN_PB31E_TCC0_WO1 63L /**< \brief TCC0 signal: WO1 on PB31 mux E */
+#define MUX_PB31E_TCC0_WO1 4L
+#define PINMUX_PB31E_TCC0_WO1 ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1)
+#define PORT_PB31E_TCC0_WO1 (1ul << 31)
+#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2 5L
+#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2 (1ul << 10)
+#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2 5L
+#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2 (1ul << 18)
+#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3 5L
+#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3 (1ul << 11)
+#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3 5L
+#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3 (1ul << 19)
+#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4 5L
+#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4 (1ul << 14)
+#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4 5L
+#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4 (1ul << 22)
+#define PIN_PB10F_TCC0_WO4 42L /**< \brief TCC0 signal: WO4 on PB10 mux F */
+#define MUX_PB10F_TCC0_WO4 5L
+#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
+#define PORT_PB10F_TCC0_WO4 (1ul << 10)
+#define PIN_PB16F_TCC0_WO4 48L /**< \brief TCC0 signal: WO4 on PB16 mux F */
+#define MUX_PB16F_TCC0_WO4 5L
+#define PINMUX_PB16F_TCC0_WO4 ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4)
+#define PORT_PB16F_TCC0_WO4 (1ul << 16)
+#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5 5L
+#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5 (1ul << 15)
+#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5 5L
+#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5 (1ul << 23)
+#define PIN_PB11F_TCC0_WO5 43L /**< \brief TCC0 signal: WO5 on PB11 mux F */
+#define MUX_PB11F_TCC0_WO5 5L
+#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
+#define PORT_PB11F_TCC0_WO5 (1ul << 11)
+#define PIN_PB17F_TCC0_WO5 49L /**< \brief TCC0 signal: WO5 on PB17 mux F */
+#define MUX_PB17F_TCC0_WO5 5L
+#define PINMUX_PB17F_TCC0_WO5 ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5)
+#define PORT_PB17F_TCC0_WO5 (1ul << 17)
+#define PIN_PA12F_TCC0_WO6 12L /**< \brief TCC0 signal: WO6 on PA12 mux F */
+#define MUX_PA12F_TCC0_WO6 5L
+#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
+#define PORT_PA12F_TCC0_WO6 (1ul << 12)
+#define PIN_PA20F_TCC0_WO6 20L /**< \brief TCC0 signal: WO6 on PA20 mux F */
+#define MUX_PA20F_TCC0_WO6 5L
+#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
+#define PORT_PA20F_TCC0_WO6 (1ul << 20)
+#define PIN_PB12F_TCC0_WO6 44L /**< \brief TCC0 signal: WO6 on PB12 mux F */
+#define MUX_PB12F_TCC0_WO6 5L
+#define PINMUX_PB12F_TCC0_WO6 ((PIN_PB12F_TCC0_WO6 << 16) | MUX_PB12F_TCC0_WO6)
+#define PORT_PB12F_TCC0_WO6 (1ul << 12)
+#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6 5L
+#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6 (1ul << 16)
+#define PIN_PA13F_TCC0_WO7 13L /**< \brief TCC0 signal: WO7 on PA13 mux F */
+#define MUX_PA13F_TCC0_WO7 5L
+#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
+#define PORT_PA13F_TCC0_WO7 (1ul << 13)
+#define PIN_PA21F_TCC0_WO7 21L /**< \brief TCC0 signal: WO7 on PA21 mux F */
+#define MUX_PA21F_TCC0_WO7 5L
+#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
+#define PORT_PA21F_TCC0_WO7 (1ul << 21)
+#define PIN_PB13F_TCC0_WO7 45L /**< \brief TCC0 signal: WO7 on PB13 mux F */
+#define MUX_PB13F_TCC0_WO7 5L
+#define PINMUX_PB13F_TCC0_WO7 ((PIN_PB13F_TCC0_WO7 << 16) | MUX_PB13F_TCC0_WO7)
+#define PORT_PB13F_TCC0_WO7 (1ul << 13)
+#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7 5L
+#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7 (1ul << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0 4L
+#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0 (1ul << 6)
+#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0 4L
+#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0 (1ul << 10)
+#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0 4L
+#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0 (1ul << 30)
+#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1 4L
+#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1 (1ul << 7)
+#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1 4L
+#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1 (1ul << 11)
+#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1 4L
+#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1 (1ul << 31)
+#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2 5L
+#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2 (1ul << 8)
+#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2 5L
+#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2 (1ul << 24)
+#define PIN_PB30F_TCC1_WO2 62L /**< \brief TCC1 signal: WO2 on PB30 mux F */
+#define MUX_PB30F_TCC1_WO2 5L
+#define PINMUX_PB30F_TCC1_WO2 ((PIN_PB30F_TCC1_WO2 << 16) | MUX_PB30F_TCC1_WO2)
+#define PORT_PB30F_TCC1_WO2 (1ul << 30)
+#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3 5L
+#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3 (1ul << 9)
+#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3 5L
+#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3 (1ul << 25)
+#define PIN_PB31F_TCC1_WO3 63L /**< \brief TCC1 signal: WO3 on PB31 mux F */
+#define MUX_PB31F_TCC1_WO3 5L
+#define PINMUX_PB31F_TCC1_WO3 ((PIN_PB31F_TCC1_WO3 << 16) | MUX_PB31F_TCC1_WO3)
+#define PORT_PB31F_TCC1_WO3 (1ul << 31)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA12E_TCC2_WO0 12L /**< \brief TCC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TCC2_WO0 4L
+#define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
+#define PORT_PA12E_TCC2_WO0 (1ul << 12)
+#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0 4L
+#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0 (1ul << 16)
+#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0 4L
+#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0 (1ul << 0)
+#define PIN_PA13E_TCC2_WO1 13L /**< \brief TCC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TCC2_WO1 4L
+#define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
+#define PORT_PA13E_TCC2_WO1 (1ul << 13)
+#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1 4L
+#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1 (1ul << 17)
+#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1 4L
+#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1 (1ul << 1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0 4L
+#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0 (1ul << 18)
+#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0 4L
+#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0 (1ul << 14)
+#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1 4L
+#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1 (1ul << 19)
+#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1 4L
+#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1 (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0 4L
+#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0 (1ul << 22)
+#define PIN_PB08E_TC4_WO0 40L /**< \brief TC4 signal: WO0 on PB08 mux E */
+#define MUX_PB08E_TC4_WO0 4L
+#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
+#define PORT_PB08E_TC4_WO0 (1ul << 8)
+#define PIN_PB12E_TC4_WO0 44L /**< \brief TC4 signal: WO0 on PB12 mux E */
+#define MUX_PB12E_TC4_WO0 4L
+#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0)
+#define PORT_PB12E_TC4_WO0 (1ul << 12)
+#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1 4L
+#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1 (1ul << 23)
+#define PIN_PB09E_TC4_WO1 41L /**< \brief TC4 signal: WO1 on PB09 mux E */
+#define MUX_PB09E_TC4_WO1 4L
+#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
+#define PORT_PB09E_TC4_WO1 (1ul << 9)
+#define PIN_PB13E_TC4_WO1 45L /**< \brief TC4 signal: WO1 on PB13 mux E */
+#define MUX_PB13E_TC4_WO1 4L
+#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1)
+#define PORT_PB13E_TC4_WO1 (1ul << 13)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0 4L
+#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0 (1ul << 24)
+#define PIN_PB10E_TC5_WO0 42L /**< \brief TC5 signal: WO0 on PB10 mux E */
+#define MUX_PB10E_TC5_WO0 4L
+#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
+#define PORT_PB10E_TC5_WO0 (1ul << 10)
+#define PIN_PB14E_TC5_WO0 46L /**< \brief TC5 signal: WO0 on PB14 mux E */
+#define MUX_PB14E_TC5_WO0 4L
+#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0)
+#define PORT_PB14E_TC5_WO0 (1ul << 14)
+#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1 4L
+#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1 (1ul << 25)
+#define PIN_PB11E_TC5_WO1 43L /**< \brief TC5 signal: WO1 on PB11 mux E */
+#define MUX_PB11E_TC5_WO1 4L
+#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
+#define PORT_PB11E_TC5_WO1 (1ul << 11)
+#define PIN_PB15E_TC5_WO1 47L /**< \brief TC5 signal: WO1 on PB15 mux E */
+#define MUX_PB15E_TC5_WO1 4L
+#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1)
+#define PORT_PB15E_TC5_WO1 (1ul << 15)
+/* ========== PORT definition for TC6 peripheral ========== */
+#define PIN_PB02E_TC6_WO0 34L /**< \brief TC6 signal: WO0 on PB02 mux E */
+#define MUX_PB02E_TC6_WO0 4L
+#define PINMUX_PB02E_TC6_WO0 ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0)
+#define PORT_PB02E_TC6_WO0 (1ul << 2)
+#define PIN_PB16E_TC6_WO0 48L /**< \brief TC6 signal: WO0 on PB16 mux E */
+#define MUX_PB16E_TC6_WO0 4L
+#define PINMUX_PB16E_TC6_WO0 ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0)
+#define PORT_PB16E_TC6_WO0 (1ul << 16)
+#define PIN_PB03E_TC6_WO1 35L /**< \brief TC6 signal: WO1 on PB03 mux E */
+#define MUX_PB03E_TC6_WO1 4L
+#define PINMUX_PB03E_TC6_WO1 ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1)
+#define PORT_PB03E_TC6_WO1 (1ul << 3)
+#define PIN_PB17E_TC6_WO1 49L /**< \brief TC6 signal: WO1 on PB17 mux E */
+#define MUX_PB17E_TC6_WO1 4L
+#define PINMUX_PB17E_TC6_WO1 ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1)
+#define PORT_PB17E_TC6_WO1 (1ul << 17)
+/* ========== PORT definition for TC7 peripheral ========== */
+#define PIN_PA20E_TC7_WO0 20L /**< \brief TC7 signal: WO0 on PA20 mux E */
+#define MUX_PA20E_TC7_WO0 4L
+#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0)
+#define PORT_PA20E_TC7_WO0 (1ul << 20)
+#define PIN_PB00E_TC7_WO0 32L /**< \brief TC7 signal: WO0 on PB00 mux E */
+#define MUX_PB00E_TC7_WO0 4L
+#define PINMUX_PB00E_TC7_WO0 ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0)
+#define PORT_PB00E_TC7_WO0 (1ul << 0)
+#define PIN_PB22E_TC7_WO0 54L /**< \brief TC7 signal: WO0 on PB22 mux E */
+#define MUX_PB22E_TC7_WO0 4L
+#define PINMUX_PB22E_TC7_WO0 ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0)
+#define PORT_PB22E_TC7_WO0 (1ul << 22)
+#define PIN_PA21E_TC7_WO1 21L /**< \brief TC7 signal: WO1 on PA21 mux E */
+#define MUX_PA21E_TC7_WO1 4L
+#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1)
+#define PORT_PA21E_TC7_WO1 (1ul << 21)
+#define PIN_PB01E_TC7_WO1 33L /**< \brief TC7 signal: WO1 on PB01 mux E */
+#define MUX_PB01E_TC7_WO1 4L
+#define PINMUX_PB01E_TC7_WO1 ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1)
+#define PORT_PB01E_TC7_WO1 (1ul << 1)
+#define PIN_PB23E_TC7_WO1 55L /**< \brief TC7 signal: WO1 on PB23 mux E */
+#define MUX_PB23E_TC7_WO1 4L
+#define PINMUX_PB23E_TC7_WO1 ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1)
+#define PORT_PB23E_TC7_WO1 (1ul << 23)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0 1L
+#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0 (1ul << 2)
+#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1 1L
+#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1 (1ul << 3)
+#define PIN_PB08B_ADC_AIN2 40L /**< \brief ADC signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC_AIN2 1L
+#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
+#define PORT_PB08B_ADC_AIN2 (1ul << 8)
+#define PIN_PB09B_ADC_AIN3 41L /**< \brief ADC signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC_AIN3 1L
+#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
+#define PORT_PB09B_ADC_AIN3 (1ul << 9)
+#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4 1L
+#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4 (1ul << 4)
+#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5 1L
+#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5 (1ul << 5)
+#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6 1L
+#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6 (1ul << 6)
+#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7 1L
+#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7 (1ul << 7)
+#define PIN_PB00B_ADC_AIN8 32L /**< \brief ADC signal: AIN8 on PB00 mux B */
+#define MUX_PB00B_ADC_AIN8 1L
+#define PINMUX_PB00B_ADC_AIN8 ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8)
+#define PORT_PB00B_ADC_AIN8 (1ul << 0)
+#define PIN_PB01B_ADC_AIN9 33L /**< \brief ADC signal: AIN9 on PB01 mux B */
+#define MUX_PB01B_ADC_AIN9 1L
+#define PINMUX_PB01B_ADC_AIN9 ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9)
+#define PORT_PB01B_ADC_AIN9 (1ul << 1)
+#define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */
+#define MUX_PB02B_ADC_AIN10 1L
+#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
+#define PORT_PB02B_ADC_AIN10 (1ul << 2)
+#define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */
+#define MUX_PB03B_ADC_AIN11 1L
+#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
+#define PORT_PB03B_ADC_AIN11 (1ul << 3)
+#define PIN_PB04B_ADC_AIN12 36L /**< \brief ADC signal: AIN12 on PB04 mux B */
+#define MUX_PB04B_ADC_AIN12 1L
+#define PINMUX_PB04B_ADC_AIN12 ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12)
+#define PORT_PB04B_ADC_AIN12 (1ul << 4)
+#define PIN_PB05B_ADC_AIN13 37L /**< \brief ADC signal: AIN13 on PB05 mux B */
+#define MUX_PB05B_ADC_AIN13 1L
+#define PINMUX_PB05B_ADC_AIN13 ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13)
+#define PORT_PB05B_ADC_AIN13 (1ul << 5)
+#define PIN_PB06B_ADC_AIN14 38L /**< \brief ADC signal: AIN14 on PB06 mux B */
+#define MUX_PB06B_ADC_AIN14 1L
+#define PINMUX_PB06B_ADC_AIN14 ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14)
+#define PORT_PB06B_ADC_AIN14 (1ul << 6)
+#define PIN_PB07B_ADC_AIN15 39L /**< \brief ADC signal: AIN15 on PB07 mux B */
+#define MUX_PB07B_ADC_AIN15 1L
+#define PINMUX_PB07B_ADC_AIN15 ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15)
+#define PORT_PB07B_ADC_AIN15 (1ul << 7)
+#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16 1L
+#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16 (1ul << 8)
+#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17 1L
+#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17 (1ul << 9)
+#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18 1L
+#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18 (1ul << 10)
+#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19 1L
+#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19 (1ul << 11)
+#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP 1L
+#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP (1ul << 4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0 1L
+#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0 (1ul << 4)
+#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1 1L
+#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1 (1ul << 5)
+#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2 1L
+#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2 (1ul << 6)
+#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3 1L
+#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3 (1ul << 7)
+#define PIN_PA12H_AC_CMP0 12L /**< \brief AC signal: CMP0 on PA12 mux H */
+#define MUX_PA12H_AC_CMP0 7L
+#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
+#define PORT_PA12H_AC_CMP0 (1ul << 12)
+#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0 7L
+#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0 (1ul << 18)
+#define PIN_PA13H_AC_CMP1 13L /**< \brief AC signal: CMP1 on PA13 mux H */
+#define MUX_PA13H_AC_CMP1 7L
+#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
+#define PORT_PA13H_AC_CMP1 (1ul << 13)
+#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1 7L
+#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1 (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT 1L
+#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT (1ul << 2)
+#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP 1L
+#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP (1ul << 3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0 11L /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0 6L
+#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0 (1ul << 11)
+#define PIN_PA21G_I2S_FS0 21L /**< \brief I2S signal: FS0 on PA21 mux G */
+#define MUX_PA21G_I2S_FS0 6L
+#define PINMUX_PA21G_I2S_FS0 ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
+#define PORT_PA21G_I2S_FS0 (1ul << 21)
+#define PIN_PB12G_I2S_FS1 44L /**< \brief I2S signal: FS1 on PB12 mux G */
+#define MUX_PB12G_I2S_FS1 6L
+#define PINMUX_PB12G_I2S_FS1 ((PIN_PB12G_I2S_FS1 << 16) | MUX_PB12G_I2S_FS1)
+#define PORT_PB12G_I2S_FS1 (1ul << 12)
+#define PIN_PA09G_I2S_MCK0 9L /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0 6L
+#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0 (1ul << 9)
+#define PIN_PB17G_I2S_MCK0 49L /**< \brief I2S signal: MCK0 on PB17 mux G */
+#define MUX_PB17G_I2S_MCK0 6L
+#define PINMUX_PB17G_I2S_MCK0 ((PIN_PB17G_I2S_MCK0 << 16) | MUX_PB17G_I2S_MCK0)
+#define PORT_PB17G_I2S_MCK0 (1ul << 17)
+#define PIN_PB10G_I2S_MCK1 42L /**< \brief I2S signal: MCK1 on PB10 mux G */
+#define MUX_PB10G_I2S_MCK1 6L
+#define PINMUX_PB10G_I2S_MCK1 ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1)
+#define PORT_PB10G_I2S_MCK1 (1ul << 10)
+#define PIN_PA10G_I2S_SCK0 10L /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0 6L
+#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0 (1ul << 10)
+#define PIN_PA20G_I2S_SCK0 20L /**< \brief I2S signal: SCK0 on PA20 mux G */
+#define MUX_PA20G_I2S_SCK0 6L
+#define PINMUX_PA20G_I2S_SCK0 ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
+#define PORT_PA20G_I2S_SCK0 (1ul << 20)
+#define PIN_PB11G_I2S_SCK1 43L /**< \brief I2S signal: SCK1 on PB11 mux G */
+#define MUX_PB11G_I2S_SCK1 6L
+#define PINMUX_PB11G_I2S_SCK1 ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1)
+#define PORT_PB11G_I2S_SCK1 (1ul << 11)
+#define PIN_PA07G_I2S_SD0 7L /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0 6L
+#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0 (1ul << 7)
+#define PIN_PA19G_I2S_SD0 19L /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0 6L
+#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0 (1ul << 19)
+#define PIN_PA08G_I2S_SD1 8L /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1 6L
+#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1 (1ul << 8)
+#define PIN_PB16G_I2S_SD1 48L /**< \brief I2S signal: SD1 on PB16 mux G */
+#define MUX_PB16G_I2S_SD1 6L
+#define PINMUX_PB16G_I2S_SD1 ((PIN_PB16G_I2S_SD1 << 16) | MUX_PB16G_I2S_SD1)
+#define PORT_PB16G_I2S_SD1 (1ul << 16)
+
+#endif /* _SAMD21J17A_PIO_ */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/pio/samd21j18a.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/pio/samd21j18a.h
new file mode 100644
index 0000000000000000000000000000000000000000..d8ee3deec8f30420c02b6396672feb98f31c860b
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/pio/samd21j18a.h
@@ -0,0 +1,1189 @@
+/**
+ * \file
+ *
+ * \brief Peripheral I/O description for SAMD21J18A
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21J18A_PIO_
+#define _SAMD21J18A_PIO_
+
+#define PIN_PA00 0 /**< \brief Pin Number for PA00 */
+#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */
+#define PIN_PA01 1 /**< \brief Pin Number for PA01 */
+#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */
+#define PIN_PA02 2 /**< \brief Pin Number for PA02 */
+#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */
+#define PIN_PA03 3 /**< \brief Pin Number for PA03 */
+#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */
+#define PIN_PA04 4 /**< \brief Pin Number for PA04 */
+#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */
+#define PIN_PA05 5 /**< \brief Pin Number for PA05 */
+#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */
+#define PIN_PA06 6 /**< \brief Pin Number for PA06 */
+#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */
+#define PIN_PA07 7 /**< \brief Pin Number for PA07 */
+#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */
+#define PIN_PA08 8 /**< \brief Pin Number for PA08 */
+#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */
+#define PIN_PA09 9 /**< \brief Pin Number for PA09 */
+#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */
+#define PIN_PA10 10 /**< \brief Pin Number for PA10 */
+#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */
+#define PIN_PA11 11 /**< \brief Pin Number for PA11 */
+#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */
+#define PIN_PA12 12 /**< \brief Pin Number for PA12 */
+#define PORT_PA12 (1ul << 12) /**< \brief PORT Mask for PA12 */
+#define PIN_PA13 13 /**< \brief Pin Number for PA13 */
+#define PORT_PA13 (1ul << 13) /**< \brief PORT Mask for PA13 */
+#define PIN_PA14 14 /**< \brief Pin Number for PA14 */
+#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */
+#define PIN_PA15 15 /**< \brief Pin Number for PA15 */
+#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */
+#define PIN_PA16 16 /**< \brief Pin Number for PA16 */
+#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */
+#define PIN_PA17 17 /**< \brief Pin Number for PA17 */
+#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */
+#define PIN_PA18 18 /**< \brief Pin Number for PA18 */
+#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */
+#define PIN_PA19 19 /**< \brief Pin Number for PA19 */
+#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */
+#define PIN_PA20 20 /**< \brief Pin Number for PA20 */
+#define PORT_PA20 (1ul << 20) /**< \brief PORT Mask for PA20 */
+#define PIN_PA21 21 /**< \brief Pin Number for PA21 */
+#define PORT_PA21 (1ul << 21) /**< \brief PORT Mask for PA21 */
+#define PIN_PA22 22 /**< \brief Pin Number for PA22 */
+#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */
+#define PIN_PA23 23 /**< \brief Pin Number for PA23 */
+#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */
+#define PIN_PA24 24 /**< \brief Pin Number for PA24 */
+#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */
+#define PIN_PA25 25 /**< \brief Pin Number for PA25 */
+#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */
+#define PIN_PA27 27 /**< \brief Pin Number for PA27 */
+#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */
+#define PIN_PA28 28 /**< \brief Pin Number for PA28 */
+#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */
+#define PIN_PA30 30 /**< \brief Pin Number for PA30 */
+#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */
+#define PIN_PA31 31 /**< \brief Pin Number for PA31 */
+#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */
+#define PIN_PB00 32 /**< \brief Pin Number for PB00 */
+#define PORT_PB00 (1ul << 0) /**< \brief PORT Mask for PB00 */
+#define PIN_PB01 33 /**< \brief Pin Number for PB01 */
+#define PORT_PB01 (1ul << 1) /**< \brief PORT Mask for PB01 */
+#define PIN_PB02 34 /**< \brief Pin Number for PB02 */
+#define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */
+#define PIN_PB03 35 /**< \brief Pin Number for PB03 */
+#define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */
+#define PIN_PB04 36 /**< \brief Pin Number for PB04 */
+#define PORT_PB04 (1ul << 4) /**< \brief PORT Mask for PB04 */
+#define PIN_PB05 37 /**< \brief Pin Number for PB05 */
+#define PORT_PB05 (1ul << 5) /**< \brief PORT Mask for PB05 */
+#define PIN_PB06 38 /**< \brief Pin Number for PB06 */
+#define PORT_PB06 (1ul << 6) /**< \brief PORT Mask for PB06 */
+#define PIN_PB07 39 /**< \brief Pin Number for PB07 */
+#define PORT_PB07 (1ul << 7) /**< \brief PORT Mask for PB07 */
+#define PIN_PB08 40 /**< \brief Pin Number for PB08 */
+#define PORT_PB08 (1ul << 8) /**< \brief PORT Mask for PB08 */
+#define PIN_PB09 41 /**< \brief Pin Number for PB09 */
+#define PORT_PB09 (1ul << 9) /**< \brief PORT Mask for PB09 */
+#define PIN_PB10 42 /**< \brief Pin Number for PB10 */
+#define PORT_PB10 (1ul << 10) /**< \brief PORT Mask for PB10 */
+#define PIN_PB11 43 /**< \brief Pin Number for PB11 */
+#define PORT_PB11 (1ul << 11) /**< \brief PORT Mask for PB11 */
+#define PIN_PB12 44 /**< \brief Pin Number for PB12 */
+#define PORT_PB12 (1ul << 12) /**< \brief PORT Mask for PB12 */
+#define PIN_PB13 45 /**< \brief Pin Number for PB13 */
+#define PORT_PB13 (1ul << 13) /**< \brief PORT Mask for PB13 */
+#define PIN_PB14 46 /**< \brief Pin Number for PB14 */
+#define PORT_PB14 (1ul << 14) /**< \brief PORT Mask for PB14 */
+#define PIN_PB15 47 /**< \brief Pin Number for PB15 */
+#define PORT_PB15 (1ul << 15) /**< \brief PORT Mask for PB15 */
+#define PIN_PB16 48 /**< \brief Pin Number for PB16 */
+#define PORT_PB16 (1ul << 16) /**< \brief PORT Mask for PB16 */
+#define PIN_PB17 49 /**< \brief Pin Number for PB17 */
+#define PORT_PB17 (1ul << 17) /**< \brief PORT Mask for PB17 */
+#define PIN_PB22 54 /**< \brief Pin Number for PB22 */
+#define PORT_PB22 (1ul << 22) /**< \brief PORT Mask for PB22 */
+#define PIN_PB23 55 /**< \brief Pin Number for PB23 */
+#define PORT_PB23 (1ul << 23) /**< \brief PORT Mask for PB23 */
+#define PIN_PB30 62 /**< \brief Pin Number for PB30 */
+#define PORT_PB30 (1ul << 30) /**< \brief PORT Mask for PB30 */
+#define PIN_PB31 63 /**< \brief Pin Number for PB31 */
+#define PORT_PB31 (1ul << 31) /**< \brief PORT Mask for PB31 */
+/* ========== PORT definition for GCLK peripheral ========== */
+#define PIN_PB14H_GCLK_IO0 46L /**< \brief GCLK signal: IO0 on PB14 mux H */
+#define MUX_PB14H_GCLK_IO0 7L
+#define PINMUX_PB14H_GCLK_IO0 ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0)
+#define PORT_PB14H_GCLK_IO0 (1ul << 14)
+#define PIN_PB22H_GCLK_IO0 54L /**< \brief GCLK signal: IO0 on PB22 mux H */
+#define MUX_PB22H_GCLK_IO0 7L
+#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0)
+#define PORT_PB22H_GCLK_IO0 (1ul << 22)
+#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */
+#define MUX_PA14H_GCLK_IO0 7L
+#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
+#define PORT_PA14H_GCLK_IO0 (1ul << 14)
+#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */
+#define MUX_PA27H_GCLK_IO0 7L
+#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
+#define PORT_PA27H_GCLK_IO0 (1ul << 27)
+#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */
+#define MUX_PA28H_GCLK_IO0 7L
+#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
+#define PORT_PA28H_GCLK_IO0 (1ul << 28)
+#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */
+#define MUX_PA30H_GCLK_IO0 7L
+#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
+#define PORT_PA30H_GCLK_IO0 (1ul << 30)
+#define PIN_PB15H_GCLK_IO1 47L /**< \brief GCLK signal: IO1 on PB15 mux H */
+#define MUX_PB15H_GCLK_IO1 7L
+#define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1)
+#define PORT_PB15H_GCLK_IO1 (1ul << 15)
+#define PIN_PB23H_GCLK_IO1 55L /**< \brief GCLK signal: IO1 on PB23 mux H */
+#define MUX_PB23H_GCLK_IO1 7L
+#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1)
+#define PORT_PB23H_GCLK_IO1 (1ul << 23)
+#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */
+#define MUX_PA15H_GCLK_IO1 7L
+#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
+#define PORT_PA15H_GCLK_IO1 (1ul << 15)
+#define PIN_PB16H_GCLK_IO2 48L /**< \brief GCLK signal: IO2 on PB16 mux H */
+#define MUX_PB16H_GCLK_IO2 7L
+#define PINMUX_PB16H_GCLK_IO2 ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2)
+#define PORT_PB16H_GCLK_IO2 (1ul << 16)
+#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */
+#define MUX_PA16H_GCLK_IO2 7L
+#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
+#define PORT_PA16H_GCLK_IO2 (1ul << 16)
+#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */
+#define MUX_PA17H_GCLK_IO3 7L
+#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
+#define PORT_PA17H_GCLK_IO3 (1ul << 17)
+#define PIN_PB17H_GCLK_IO3 49L /**< \brief GCLK signal: IO3 on PB17 mux H */
+#define MUX_PB17H_GCLK_IO3 7L
+#define PINMUX_PB17H_GCLK_IO3 ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3)
+#define PORT_PB17H_GCLK_IO3 (1ul << 17)
+#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */
+#define MUX_PA10H_GCLK_IO4 7L
+#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
+#define PORT_PA10H_GCLK_IO4 (1ul << 10)
+#define PIN_PA20H_GCLK_IO4 20L /**< \brief GCLK signal: IO4 on PA20 mux H */
+#define MUX_PA20H_GCLK_IO4 7L
+#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4)
+#define PORT_PA20H_GCLK_IO4 (1ul << 20)
+#define PIN_PB10H_GCLK_IO4 42L /**< \brief GCLK signal: IO4 on PB10 mux H */
+#define MUX_PB10H_GCLK_IO4 7L
+#define PINMUX_PB10H_GCLK_IO4 ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4)
+#define PORT_PB10H_GCLK_IO4 (1ul << 10)
+#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */
+#define MUX_PA11H_GCLK_IO5 7L
+#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
+#define PORT_PA11H_GCLK_IO5 (1ul << 11)
+#define PIN_PA21H_GCLK_IO5 21L /**< \brief GCLK signal: IO5 on PA21 mux H */
+#define MUX_PA21H_GCLK_IO5 7L
+#define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5)
+#define PORT_PA21H_GCLK_IO5 (1ul << 21)
+#define PIN_PB11H_GCLK_IO5 43L /**< \brief GCLK signal: IO5 on PB11 mux H */
+#define MUX_PB11H_GCLK_IO5 7L
+#define PINMUX_PB11H_GCLK_IO5 ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5)
+#define PORT_PB11H_GCLK_IO5 (1ul << 11)
+#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */
+#define MUX_PA22H_GCLK_IO6 7L
+#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
+#define PORT_PA22H_GCLK_IO6 (1ul << 22)
+#define PIN_PB12H_GCLK_IO6 44L /**< \brief GCLK signal: IO6 on PB12 mux H */
+#define MUX_PB12H_GCLK_IO6 7L
+#define PINMUX_PB12H_GCLK_IO6 ((PIN_PB12H_GCLK_IO6 << 16) | MUX_PB12H_GCLK_IO6)
+#define PORT_PB12H_GCLK_IO6 (1ul << 12)
+#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */
+#define MUX_PA23H_GCLK_IO7 7L
+#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
+#define PORT_PA23H_GCLK_IO7 (1ul << 23)
+#define PIN_PB13H_GCLK_IO7 45L /**< \brief GCLK signal: IO7 on PB13 mux H */
+#define MUX_PB13H_GCLK_IO7 7L
+#define PINMUX_PB13H_GCLK_IO7 ((PIN_PB13H_GCLK_IO7 << 16) | MUX_PB13H_GCLK_IO7)
+#define PORT_PB13H_GCLK_IO7 (1ul << 13)
+/* ========== PORT definition for EIC peripheral ========== */
+#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */
+#define MUX_PA16A_EIC_EXTINT0 0L
+#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
+#define PORT_PA16A_EIC_EXTINT0 (1ul << 16)
+#define PIN_PB00A_EIC_EXTINT0 32L /**< \brief EIC signal: EXTINT0 on PB00 mux A */
+#define MUX_PB00A_EIC_EXTINT0 0L
+#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0)
+#define PORT_PB00A_EIC_EXTINT0 (1ul << 0)
+#define PIN_PB16A_EIC_EXTINT0 48L /**< \brief EIC signal: EXTINT0 on PB16 mux A */
+#define MUX_PB16A_EIC_EXTINT0 0L
+#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0)
+#define PORT_PB16A_EIC_EXTINT0 (1ul << 16)
+#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */
+#define MUX_PA00A_EIC_EXTINT0 0L
+#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
+#define PORT_PA00A_EIC_EXTINT0 (1ul << 0)
+#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */
+#define MUX_PA17A_EIC_EXTINT1 0L
+#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
+#define PORT_PA17A_EIC_EXTINT1 (1ul << 17)
+#define PIN_PB01A_EIC_EXTINT1 33L /**< \brief EIC signal: EXTINT1 on PB01 mux A */
+#define MUX_PB01A_EIC_EXTINT1 0L
+#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1)
+#define PORT_PB01A_EIC_EXTINT1 (1ul << 1)
+#define PIN_PB17A_EIC_EXTINT1 49L /**< \brief EIC signal: EXTINT1 on PB17 mux A */
+#define MUX_PB17A_EIC_EXTINT1 0L
+#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1)
+#define PORT_PB17A_EIC_EXTINT1 (1ul << 17)
+#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */
+#define MUX_PA01A_EIC_EXTINT1 0L
+#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
+#define PORT_PA01A_EIC_EXTINT1 (1ul << 1)
+#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */
+#define MUX_PA18A_EIC_EXTINT2 0L
+#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
+#define PORT_PA18A_EIC_EXTINT2 (1ul << 18)
+#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */
+#define MUX_PA02A_EIC_EXTINT2 0L
+#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
+#define PORT_PA02A_EIC_EXTINT2 (1ul << 2)
+#define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */
+#define MUX_PB02A_EIC_EXTINT2 0L
+#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
+#define PORT_PB02A_EIC_EXTINT2 (1ul << 2)
+#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */
+#define MUX_PA03A_EIC_EXTINT3 0L
+#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
+#define PORT_PA03A_EIC_EXTINT3 (1ul << 3)
+#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */
+#define MUX_PA19A_EIC_EXTINT3 0L
+#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
+#define PORT_PA19A_EIC_EXTINT3 (1ul << 19)
+#define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */
+#define MUX_PB03A_EIC_EXTINT3 0L
+#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
+#define PORT_PB03A_EIC_EXTINT3 (1ul << 3)
+#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */
+#define MUX_PA04A_EIC_EXTINT4 0L
+#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
+#define PORT_PA04A_EIC_EXTINT4 (1ul << 4)
+#define PIN_PA20A_EIC_EXTINT4 20L /**< \brief EIC signal: EXTINT4 on PA20 mux A */
+#define MUX_PA20A_EIC_EXTINT4 0L
+#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
+#define PORT_PA20A_EIC_EXTINT4 (1ul << 20)
+#define PIN_PB04A_EIC_EXTINT4 36L /**< \brief EIC signal: EXTINT4 on PB04 mux A */
+#define MUX_PB04A_EIC_EXTINT4 0L
+#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
+#define PORT_PB04A_EIC_EXTINT4 (1ul << 4)
+#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */
+#define MUX_PA05A_EIC_EXTINT5 0L
+#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
+#define PORT_PA05A_EIC_EXTINT5 (1ul << 5)
+#define PIN_PA21A_EIC_EXTINT5 21L /**< \brief EIC signal: EXTINT5 on PA21 mux A */
+#define MUX_PA21A_EIC_EXTINT5 0L
+#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
+#define PORT_PA21A_EIC_EXTINT5 (1ul << 21)
+#define PIN_PB05A_EIC_EXTINT5 37L /**< \brief EIC signal: EXTINT5 on PB05 mux A */
+#define MUX_PB05A_EIC_EXTINT5 0L
+#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5)
+#define PORT_PB05A_EIC_EXTINT5 (1ul << 5)
+#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */
+#define MUX_PA06A_EIC_EXTINT6 0L
+#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
+#define PORT_PA06A_EIC_EXTINT6 (1ul << 6)
+#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */
+#define MUX_PA22A_EIC_EXTINT6 0L
+#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
+#define PORT_PA22A_EIC_EXTINT6 (1ul << 22)
+#define PIN_PB06A_EIC_EXTINT6 38L /**< \brief EIC signal: EXTINT6 on PB06 mux A */
+#define MUX_PB06A_EIC_EXTINT6 0L
+#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6)
+#define PORT_PB06A_EIC_EXTINT6 (1ul << 6)
+#define PIN_PB22A_EIC_EXTINT6 54L /**< \brief EIC signal: EXTINT6 on PB22 mux A */
+#define MUX_PB22A_EIC_EXTINT6 0L
+#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
+#define PORT_PB22A_EIC_EXTINT6 (1ul << 22)
+#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */
+#define MUX_PA07A_EIC_EXTINT7 0L
+#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
+#define PORT_PA07A_EIC_EXTINT7 (1ul << 7)
+#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */
+#define MUX_PA23A_EIC_EXTINT7 0L
+#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
+#define PORT_PA23A_EIC_EXTINT7 (1ul << 23)
+#define PIN_PB07A_EIC_EXTINT7 39L /**< \brief EIC signal: EXTINT7 on PB07 mux A */
+#define MUX_PB07A_EIC_EXTINT7 0L
+#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7)
+#define PORT_PB07A_EIC_EXTINT7 (1ul << 7)
+#define PIN_PB23A_EIC_EXTINT7 55L /**< \brief EIC signal: EXTINT7 on PB23 mux A */
+#define MUX_PB23A_EIC_EXTINT7 0L
+#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
+#define PORT_PB23A_EIC_EXTINT7 (1ul << 23)
+#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */
+#define MUX_PA28A_EIC_EXTINT8 0L
+#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
+#define PORT_PA28A_EIC_EXTINT8 (1ul << 28)
+#define PIN_PB08A_EIC_EXTINT8 40L /**< \brief EIC signal: EXTINT8 on PB08 mux A */
+#define MUX_PB08A_EIC_EXTINT8 0L
+#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
+#define PORT_PB08A_EIC_EXTINT8 (1ul << 8)
+#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */
+#define MUX_PA09A_EIC_EXTINT9 0L
+#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
+#define PORT_PA09A_EIC_EXTINT9 (1ul << 9)
+#define PIN_PB09A_EIC_EXTINT9 41L /**< \brief EIC signal: EXTINT9 on PB09 mux A */
+#define MUX_PB09A_EIC_EXTINT9 0L
+#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
+#define PORT_PB09A_EIC_EXTINT9 (1ul << 9)
+#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */
+#define MUX_PA10A_EIC_EXTINT10 0L
+#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
+#define PORT_PA10A_EIC_EXTINT10 (1ul << 10)
+#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */
+#define MUX_PA30A_EIC_EXTINT10 0L
+#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
+#define PORT_PA30A_EIC_EXTINT10 (1ul << 30)
+#define PIN_PB10A_EIC_EXTINT10 42L /**< \brief EIC signal: EXTINT10 on PB10 mux A */
+#define MUX_PB10A_EIC_EXTINT10 0L
+#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
+#define PORT_PB10A_EIC_EXTINT10 (1ul << 10)
+#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */
+#define MUX_PA11A_EIC_EXTINT11 0L
+#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
+#define PORT_PA11A_EIC_EXTINT11 (1ul << 11)
+#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */
+#define MUX_PA31A_EIC_EXTINT11 0L
+#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
+#define PORT_PA31A_EIC_EXTINT11 (1ul << 31)
+#define PIN_PB11A_EIC_EXTINT11 43L /**< \brief EIC signal: EXTINT11 on PB11 mux A */
+#define MUX_PB11A_EIC_EXTINT11 0L
+#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
+#define PORT_PB11A_EIC_EXTINT11 (1ul << 11)
+#define PIN_PA12A_EIC_EXTINT12 12L /**< \brief EIC signal: EXTINT12 on PA12 mux A */
+#define MUX_PA12A_EIC_EXTINT12 0L
+#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
+#define PORT_PA12A_EIC_EXTINT12 (1ul << 12)
+#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */
+#define MUX_PA24A_EIC_EXTINT12 0L
+#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
+#define PORT_PA24A_EIC_EXTINT12 (1ul << 24)
+#define PIN_PB12A_EIC_EXTINT12 44L /**< \brief EIC signal: EXTINT12 on PB12 mux A */
+#define MUX_PB12A_EIC_EXTINT12 0L
+#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12)
+#define PORT_PB12A_EIC_EXTINT12 (1ul << 12)
+#define PIN_PA13A_EIC_EXTINT13 13L /**< \brief EIC signal: EXTINT13 on PA13 mux A */
+#define MUX_PA13A_EIC_EXTINT13 0L
+#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
+#define PORT_PA13A_EIC_EXTINT13 (1ul << 13)
+#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */
+#define MUX_PA25A_EIC_EXTINT13 0L
+#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
+#define PORT_PA25A_EIC_EXTINT13 (1ul << 25)
+#define PIN_PB13A_EIC_EXTINT13 45L /**< \brief EIC signal: EXTINT13 on PB13 mux A */
+#define MUX_PB13A_EIC_EXTINT13 0L
+#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13)
+#define PORT_PB13A_EIC_EXTINT13 (1ul << 13)
+#define PIN_PB14A_EIC_EXTINT14 46L /**< \brief EIC signal: EXTINT14 on PB14 mux A */
+#define MUX_PB14A_EIC_EXTINT14 0L
+#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14)
+#define PORT_PB14A_EIC_EXTINT14 (1ul << 14)
+#define PIN_PB30A_EIC_EXTINT14 62L /**< \brief EIC signal: EXTINT14 on PB30 mux A */
+#define MUX_PB30A_EIC_EXTINT14 0L
+#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14)
+#define PORT_PB30A_EIC_EXTINT14 (1ul << 30)
+#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */
+#define MUX_PA14A_EIC_EXTINT14 0L
+#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
+#define PORT_PA14A_EIC_EXTINT14 (1ul << 14)
+#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */
+#define MUX_PA15A_EIC_EXTINT15 0L
+#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
+#define PORT_PA15A_EIC_EXTINT15 (1ul << 15)
+#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */
+#define MUX_PA27A_EIC_EXTINT15 0L
+#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
+#define PORT_PA27A_EIC_EXTINT15 (1ul << 27)
+#define PIN_PB15A_EIC_EXTINT15 47L /**< \brief EIC signal: EXTINT15 on PB15 mux A */
+#define MUX_PB15A_EIC_EXTINT15 0L
+#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15)
+#define PORT_PB15A_EIC_EXTINT15 (1ul << 15)
+#define PIN_PB31A_EIC_EXTINT15 63L /**< \brief EIC signal: EXTINT15 on PB31 mux A */
+#define MUX_PB31A_EIC_EXTINT15 0L
+#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15)
+#define PORT_PB31A_EIC_EXTINT15 (1ul << 31)
+#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */
+#define MUX_PA08A_EIC_NMI 0L
+#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
+#define PORT_PA08A_EIC_NMI (1ul << 8)
+/* ========== PORT definition for USB peripheral ========== */
+#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */
+#define MUX_PA24G_USB_DM 6L
+#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM)
+#define PORT_PA24G_USB_DM (1ul << 24)
+#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */
+#define MUX_PA25G_USB_DP 6L
+#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP)
+#define PORT_PA25G_USB_DP (1ul << 25)
+#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */
+#define MUX_PA23G_USB_SOF_1KHZ 6L
+#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ)
+#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23)
+/* ========== PORT definition for SERCOM0 peripheral ========== */
+#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
+#define MUX_PA04D_SERCOM0_PAD0 3L
+#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
+#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4)
+#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
+#define MUX_PA08C_SERCOM0_PAD0 2L
+#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
+#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8)
+#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
+#define MUX_PA05D_SERCOM0_PAD1 3L
+#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
+#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5)
+#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
+#define MUX_PA09C_SERCOM0_PAD1 2L
+#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
+#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9)
+#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
+#define MUX_PA06D_SERCOM0_PAD2 3L
+#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
+#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6)
+#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
+#define MUX_PA10C_SERCOM0_PAD2 2L
+#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
+#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10)
+#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
+#define MUX_PA07D_SERCOM0_PAD3 3L
+#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
+#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7)
+#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
+#define MUX_PA11C_SERCOM0_PAD3 2L
+#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
+#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11)
+/* ========== PORT definition for SERCOM1 peripheral ========== */
+#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
+#define MUX_PA16C_SERCOM1_PAD0 2L
+#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
+#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16)
+#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
+#define MUX_PA00D_SERCOM1_PAD0 3L
+#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
+#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0)
+#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
+#define MUX_PA17C_SERCOM1_PAD1 2L
+#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
+#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17)
+#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
+#define MUX_PA01D_SERCOM1_PAD1 3L
+#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
+#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1)
+#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
+#define MUX_PA30D_SERCOM1_PAD2 3L
+#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
+#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30)
+#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
+#define MUX_PA18C_SERCOM1_PAD2 2L
+#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
+#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18)
+#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
+#define MUX_PA31D_SERCOM1_PAD3 3L
+#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
+#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31)
+#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
+#define MUX_PA19C_SERCOM1_PAD3 2L
+#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
+#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19)
+/* ========== PORT definition for SERCOM2 peripheral ========== */
+#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
+#define MUX_PA08D_SERCOM2_PAD0 3L
+#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
+#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8)
+#define PIN_PA12C_SERCOM2_PAD0 12L /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */
+#define MUX_PA12C_SERCOM2_PAD0 2L
+#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
+#define PORT_PA12C_SERCOM2_PAD0 (1ul << 12)
+#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
+#define MUX_PA09D_SERCOM2_PAD1 3L
+#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
+#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9)
+#define PIN_PA13C_SERCOM2_PAD1 13L /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */
+#define MUX_PA13C_SERCOM2_PAD1 2L
+#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
+#define PORT_PA13C_SERCOM2_PAD1 (1ul << 13)
+#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
+#define MUX_PA10D_SERCOM2_PAD2 3L
+#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
+#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10)
+#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
+#define MUX_PA14C_SERCOM2_PAD2 2L
+#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
+#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14)
+#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
+#define MUX_PA11D_SERCOM2_PAD3 3L
+#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
+#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11)
+#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
+#define MUX_PA15C_SERCOM2_PAD3 2L
+#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
+#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15)
+/* ========== PORT definition for SERCOM3 peripheral ========== */
+#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
+#define MUX_PA16D_SERCOM3_PAD0 3L
+#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
+#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16)
+#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
+#define MUX_PA22C_SERCOM3_PAD0 2L
+#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
+#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22)
+#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
+#define MUX_PA17D_SERCOM3_PAD1 3L
+#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
+#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17)
+#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
+#define MUX_PA23C_SERCOM3_PAD1 2L
+#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
+#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23)
+#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
+#define MUX_PA18D_SERCOM3_PAD2 3L
+#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
+#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18)
+#define PIN_PA20D_SERCOM3_PAD2 20L /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */
+#define MUX_PA20D_SERCOM3_PAD2 3L
+#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
+#define PORT_PA20D_SERCOM3_PAD2 (1ul << 20)
+#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
+#define MUX_PA24C_SERCOM3_PAD2 2L
+#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
+#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24)
+#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
+#define MUX_PA19D_SERCOM3_PAD3 3L
+#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
+#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19)
+#define PIN_PA21D_SERCOM3_PAD3 21L /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */
+#define MUX_PA21D_SERCOM3_PAD3 3L
+#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
+#define PORT_PA21D_SERCOM3_PAD3 (1ul << 21)
+#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
+#define MUX_PA25C_SERCOM3_PAD3 2L
+#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
+#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25)
+/* ========== PORT definition for SERCOM4 peripheral ========== */
+#define PIN_PA12D_SERCOM4_PAD0 12L /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */
+#define MUX_PA12D_SERCOM4_PAD0 3L
+#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0)
+#define PORT_PA12D_SERCOM4_PAD0 (1ul << 12)
+#define PIN_PB08D_SERCOM4_PAD0 40L /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */
+#define MUX_PB08D_SERCOM4_PAD0 3L
+#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
+#define PORT_PB08D_SERCOM4_PAD0 (1ul << 8)
+#define PIN_PB12C_SERCOM4_PAD0 44L /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */
+#define MUX_PB12C_SERCOM4_PAD0 2L
+#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0)
+#define PORT_PB12C_SERCOM4_PAD0 (1ul << 12)
+#define PIN_PA13D_SERCOM4_PAD1 13L /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */
+#define MUX_PA13D_SERCOM4_PAD1 3L
+#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1)
+#define PORT_PA13D_SERCOM4_PAD1 (1ul << 13)
+#define PIN_PB09D_SERCOM4_PAD1 41L /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */
+#define MUX_PB09D_SERCOM4_PAD1 3L
+#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
+#define PORT_PB09D_SERCOM4_PAD1 (1ul << 9)
+#define PIN_PB13C_SERCOM4_PAD1 45L /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */
+#define MUX_PB13C_SERCOM4_PAD1 2L
+#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1)
+#define PORT_PB13C_SERCOM4_PAD1 (1ul << 13)
+#define PIN_PA14D_SERCOM4_PAD2 14L /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */
+#define MUX_PA14D_SERCOM4_PAD2 3L
+#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
+#define PORT_PA14D_SERCOM4_PAD2 (1ul << 14)
+#define PIN_PB10D_SERCOM4_PAD2 42L /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */
+#define MUX_PB10D_SERCOM4_PAD2 3L
+#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
+#define PORT_PB10D_SERCOM4_PAD2 (1ul << 10)
+#define PIN_PB14C_SERCOM4_PAD2 46L /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */
+#define MUX_PB14C_SERCOM4_PAD2 2L
+#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2)
+#define PORT_PB14C_SERCOM4_PAD2 (1ul << 14)
+#define PIN_PA15D_SERCOM4_PAD3 15L /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */
+#define MUX_PA15D_SERCOM4_PAD3 3L
+#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
+#define PORT_PA15D_SERCOM4_PAD3 (1ul << 15)
+#define PIN_PB11D_SERCOM4_PAD3 43L /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */
+#define MUX_PB11D_SERCOM4_PAD3 3L
+#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
+#define PORT_PB11D_SERCOM4_PAD3 (1ul << 11)
+#define PIN_PB15C_SERCOM4_PAD3 47L /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */
+#define MUX_PB15C_SERCOM4_PAD3 2L
+#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3)
+#define PORT_PB15C_SERCOM4_PAD3 (1ul << 15)
+/* ========== PORT definition for SERCOM5 peripheral ========== */
+#define PIN_PB16C_SERCOM5_PAD0 48L /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */
+#define MUX_PB16C_SERCOM5_PAD0 2L
+#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0)
+#define PORT_PB16C_SERCOM5_PAD0 (1ul << 16)
+#define PIN_PA22D_SERCOM5_PAD0 22L /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */
+#define MUX_PA22D_SERCOM5_PAD0 3L
+#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0)
+#define PORT_PA22D_SERCOM5_PAD0 (1ul << 22)
+#define PIN_PB02D_SERCOM5_PAD0 34L /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */
+#define MUX_PB02D_SERCOM5_PAD0 3L
+#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
+#define PORT_PB02D_SERCOM5_PAD0 (1ul << 2)
+#define PIN_PB30D_SERCOM5_PAD0 62L /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */
+#define MUX_PB30D_SERCOM5_PAD0 3L
+#define PINMUX_PB30D_SERCOM5_PAD0 ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0)
+#define PORT_PB30D_SERCOM5_PAD0 (1ul << 30)
+#define PIN_PB17C_SERCOM5_PAD1 49L /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */
+#define MUX_PB17C_SERCOM5_PAD1 2L
+#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1)
+#define PORT_PB17C_SERCOM5_PAD1 (1ul << 17)
+#define PIN_PA23D_SERCOM5_PAD1 23L /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */
+#define MUX_PA23D_SERCOM5_PAD1 3L
+#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1)
+#define PORT_PA23D_SERCOM5_PAD1 (1ul << 23)
+#define PIN_PB03D_SERCOM5_PAD1 35L /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */
+#define MUX_PB03D_SERCOM5_PAD1 3L
+#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
+#define PORT_PB03D_SERCOM5_PAD1 (1ul << 3)
+#define PIN_PB31D_SERCOM5_PAD1 63L /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */
+#define MUX_PB31D_SERCOM5_PAD1 3L
+#define PINMUX_PB31D_SERCOM5_PAD1 ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1)
+#define PORT_PB31D_SERCOM5_PAD1 (1ul << 31)
+#define PIN_PA24D_SERCOM5_PAD2 24L /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */
+#define MUX_PA24D_SERCOM5_PAD2 3L
+#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
+#define PORT_PA24D_SERCOM5_PAD2 (1ul << 24)
+#define PIN_PB00D_SERCOM5_PAD2 32L /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */
+#define MUX_PB00D_SERCOM5_PAD2 3L
+#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2)
+#define PORT_PB00D_SERCOM5_PAD2 (1ul << 0)
+#define PIN_PB22D_SERCOM5_PAD2 54L /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */
+#define MUX_PB22D_SERCOM5_PAD2 3L
+#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
+#define PORT_PB22D_SERCOM5_PAD2 (1ul << 22)
+#define PIN_PA20C_SERCOM5_PAD2 20L /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */
+#define MUX_PA20C_SERCOM5_PAD2 2L
+#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
+#define PORT_PA20C_SERCOM5_PAD2 (1ul << 20)
+#define PIN_PA25D_SERCOM5_PAD3 25L /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */
+#define MUX_PA25D_SERCOM5_PAD3 3L
+#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
+#define PORT_PA25D_SERCOM5_PAD3 (1ul << 25)
+#define PIN_PB01D_SERCOM5_PAD3 33L /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */
+#define MUX_PB01D_SERCOM5_PAD3 3L
+#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3)
+#define PORT_PB01D_SERCOM5_PAD3 (1ul << 1)
+#define PIN_PB23D_SERCOM5_PAD3 55L /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */
+#define MUX_PB23D_SERCOM5_PAD3 3L
+#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
+#define PORT_PB23D_SERCOM5_PAD3 (1ul << 23)
+#define PIN_PA21C_SERCOM5_PAD3 21L /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */
+#define MUX_PA21C_SERCOM5_PAD3 2L
+#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
+#define PORT_PA21C_SERCOM5_PAD3 (1ul << 21)
+/* ========== PORT definition for TCC0 peripheral ========== */
+#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */
+#define MUX_PA04E_TCC0_WO0 4L
+#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
+#define PORT_PA04E_TCC0_WO0 (1ul << 4)
+#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */
+#define MUX_PA08E_TCC0_WO0 4L
+#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
+#define PORT_PA08E_TCC0_WO0 (1ul << 8)
+#define PIN_PB30E_TCC0_WO0 62L /**< \brief TCC0 signal: WO0 on PB30 mux E */
+#define MUX_PB30E_TCC0_WO0 4L
+#define PINMUX_PB30E_TCC0_WO0 ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0)
+#define PORT_PB30E_TCC0_WO0 (1ul << 30)
+#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */
+#define MUX_PA05E_TCC0_WO1 4L
+#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
+#define PORT_PA05E_TCC0_WO1 (1ul << 5)
+#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */
+#define MUX_PA09E_TCC0_WO1 4L
+#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
+#define PORT_PA09E_TCC0_WO1 (1ul << 9)
+#define PIN_PB31E_TCC0_WO1 63L /**< \brief TCC0 signal: WO1 on PB31 mux E */
+#define MUX_PB31E_TCC0_WO1 4L
+#define PINMUX_PB31E_TCC0_WO1 ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1)
+#define PORT_PB31E_TCC0_WO1 (1ul << 31)
+#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */
+#define MUX_PA10F_TCC0_WO2 5L
+#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
+#define PORT_PA10F_TCC0_WO2 (1ul << 10)
+#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */
+#define MUX_PA18F_TCC0_WO2 5L
+#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
+#define PORT_PA18F_TCC0_WO2 (1ul << 18)
+#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */
+#define MUX_PA11F_TCC0_WO3 5L
+#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
+#define PORT_PA11F_TCC0_WO3 (1ul << 11)
+#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */
+#define MUX_PA19F_TCC0_WO3 5L
+#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
+#define PORT_PA19F_TCC0_WO3 (1ul << 19)
+#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */
+#define MUX_PA14F_TCC0_WO4 5L
+#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
+#define PORT_PA14F_TCC0_WO4 (1ul << 14)
+#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */
+#define MUX_PA22F_TCC0_WO4 5L
+#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
+#define PORT_PA22F_TCC0_WO4 (1ul << 22)
+#define PIN_PB10F_TCC0_WO4 42L /**< \brief TCC0 signal: WO4 on PB10 mux F */
+#define MUX_PB10F_TCC0_WO4 5L
+#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
+#define PORT_PB10F_TCC0_WO4 (1ul << 10)
+#define PIN_PB16F_TCC0_WO4 48L /**< \brief TCC0 signal: WO4 on PB16 mux F */
+#define MUX_PB16F_TCC0_WO4 5L
+#define PINMUX_PB16F_TCC0_WO4 ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4)
+#define PORT_PB16F_TCC0_WO4 (1ul << 16)
+#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */
+#define MUX_PA15F_TCC0_WO5 5L
+#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
+#define PORT_PA15F_TCC0_WO5 (1ul << 15)
+#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */
+#define MUX_PA23F_TCC0_WO5 5L
+#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
+#define PORT_PA23F_TCC0_WO5 (1ul << 23)
+#define PIN_PB11F_TCC0_WO5 43L /**< \brief TCC0 signal: WO5 on PB11 mux F */
+#define MUX_PB11F_TCC0_WO5 5L
+#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
+#define PORT_PB11F_TCC0_WO5 (1ul << 11)
+#define PIN_PB17F_TCC0_WO5 49L /**< \brief TCC0 signal: WO5 on PB17 mux F */
+#define MUX_PB17F_TCC0_WO5 5L
+#define PINMUX_PB17F_TCC0_WO5 ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5)
+#define PORT_PB17F_TCC0_WO5 (1ul << 17)
+#define PIN_PA12F_TCC0_WO6 12L /**< \brief TCC0 signal: WO6 on PA12 mux F */
+#define MUX_PA12F_TCC0_WO6 5L
+#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
+#define PORT_PA12F_TCC0_WO6 (1ul << 12)
+#define PIN_PA20F_TCC0_WO6 20L /**< \brief TCC0 signal: WO6 on PA20 mux F */
+#define MUX_PA20F_TCC0_WO6 5L
+#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6)
+#define PORT_PA20F_TCC0_WO6 (1ul << 20)
+#define PIN_PB12F_TCC0_WO6 44L /**< \brief TCC0 signal: WO6 on PB12 mux F */
+#define MUX_PB12F_TCC0_WO6 5L
+#define PINMUX_PB12F_TCC0_WO6 ((PIN_PB12F_TCC0_WO6 << 16) | MUX_PB12F_TCC0_WO6)
+#define PORT_PB12F_TCC0_WO6 (1ul << 12)
+#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */
+#define MUX_PA16F_TCC0_WO6 5L
+#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
+#define PORT_PA16F_TCC0_WO6 (1ul << 16)
+#define PIN_PA13F_TCC0_WO7 13L /**< \brief TCC0 signal: WO7 on PA13 mux F */
+#define MUX_PA13F_TCC0_WO7 5L
+#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
+#define PORT_PA13F_TCC0_WO7 (1ul << 13)
+#define PIN_PA21F_TCC0_WO7 21L /**< \brief TCC0 signal: WO7 on PA21 mux F */
+#define MUX_PA21F_TCC0_WO7 5L
+#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7)
+#define PORT_PA21F_TCC0_WO7 (1ul << 21)
+#define PIN_PB13F_TCC0_WO7 45L /**< \brief TCC0 signal: WO7 on PB13 mux F */
+#define MUX_PB13F_TCC0_WO7 5L
+#define PINMUX_PB13F_TCC0_WO7 ((PIN_PB13F_TCC0_WO7 << 16) | MUX_PB13F_TCC0_WO7)
+#define PORT_PB13F_TCC0_WO7 (1ul << 13)
+#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */
+#define MUX_PA17F_TCC0_WO7 5L
+#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
+#define PORT_PA17F_TCC0_WO7 (1ul << 17)
+/* ========== PORT definition for TCC1 peripheral ========== */
+#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */
+#define MUX_PA06E_TCC1_WO0 4L
+#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
+#define PORT_PA06E_TCC1_WO0 (1ul << 6)
+#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */
+#define MUX_PA10E_TCC1_WO0 4L
+#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
+#define PORT_PA10E_TCC1_WO0 (1ul << 10)
+#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */
+#define MUX_PA30E_TCC1_WO0 4L
+#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
+#define PORT_PA30E_TCC1_WO0 (1ul << 30)
+#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */
+#define MUX_PA07E_TCC1_WO1 4L
+#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
+#define PORT_PA07E_TCC1_WO1 (1ul << 7)
+#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */
+#define MUX_PA11E_TCC1_WO1 4L
+#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
+#define PORT_PA11E_TCC1_WO1 (1ul << 11)
+#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */
+#define MUX_PA31E_TCC1_WO1 4L
+#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
+#define PORT_PA31E_TCC1_WO1 (1ul << 31)
+#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */
+#define MUX_PA08F_TCC1_WO2 5L
+#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
+#define PORT_PA08F_TCC1_WO2 (1ul << 8)
+#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */
+#define MUX_PA24F_TCC1_WO2 5L
+#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
+#define PORT_PA24F_TCC1_WO2 (1ul << 24)
+#define PIN_PB30F_TCC1_WO2 62L /**< \brief TCC1 signal: WO2 on PB30 mux F */
+#define MUX_PB30F_TCC1_WO2 5L
+#define PINMUX_PB30F_TCC1_WO2 ((PIN_PB30F_TCC1_WO2 << 16) | MUX_PB30F_TCC1_WO2)
+#define PORT_PB30F_TCC1_WO2 (1ul << 30)
+#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */
+#define MUX_PA09F_TCC1_WO3 5L
+#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
+#define PORT_PA09F_TCC1_WO3 (1ul << 9)
+#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */
+#define MUX_PA25F_TCC1_WO3 5L
+#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
+#define PORT_PA25F_TCC1_WO3 (1ul << 25)
+#define PIN_PB31F_TCC1_WO3 63L /**< \brief TCC1 signal: WO3 on PB31 mux F */
+#define MUX_PB31F_TCC1_WO3 5L
+#define PINMUX_PB31F_TCC1_WO3 ((PIN_PB31F_TCC1_WO3 << 16) | MUX_PB31F_TCC1_WO3)
+#define PORT_PB31F_TCC1_WO3 (1ul << 31)
+/* ========== PORT definition for TCC2 peripheral ========== */
+#define PIN_PA12E_TCC2_WO0 12L /**< \brief TCC2 signal: WO0 on PA12 mux E */
+#define MUX_PA12E_TCC2_WO0 4L
+#define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0)
+#define PORT_PA12E_TCC2_WO0 (1ul << 12)
+#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */
+#define MUX_PA16E_TCC2_WO0 4L
+#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
+#define PORT_PA16E_TCC2_WO0 (1ul << 16)
+#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */
+#define MUX_PA00E_TCC2_WO0 4L
+#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
+#define PORT_PA00E_TCC2_WO0 (1ul << 0)
+#define PIN_PA13E_TCC2_WO1 13L /**< \brief TCC2 signal: WO1 on PA13 mux E */
+#define MUX_PA13E_TCC2_WO1 4L
+#define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1)
+#define PORT_PA13E_TCC2_WO1 (1ul << 13)
+#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */
+#define MUX_PA17E_TCC2_WO1 4L
+#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
+#define PORT_PA17E_TCC2_WO1 (1ul << 17)
+#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */
+#define MUX_PA01E_TCC2_WO1 4L
+#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
+#define PORT_PA01E_TCC2_WO1 (1ul << 1)
+/* ========== PORT definition for TC3 peripheral ========== */
+#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */
+#define MUX_PA18E_TC3_WO0 4L
+#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
+#define PORT_PA18E_TC3_WO0 (1ul << 18)
+#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */
+#define MUX_PA14E_TC3_WO0 4L
+#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
+#define PORT_PA14E_TC3_WO0 (1ul << 14)
+#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */
+#define MUX_PA19E_TC3_WO1 4L
+#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
+#define PORT_PA19E_TC3_WO1 (1ul << 19)
+#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */
+#define MUX_PA15E_TC3_WO1 4L
+#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
+#define PORT_PA15E_TC3_WO1 (1ul << 15)
+/* ========== PORT definition for TC4 peripheral ========== */
+#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */
+#define MUX_PA22E_TC4_WO0 4L
+#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
+#define PORT_PA22E_TC4_WO0 (1ul << 22)
+#define PIN_PB08E_TC4_WO0 40L /**< \brief TC4 signal: WO0 on PB08 mux E */
+#define MUX_PB08E_TC4_WO0 4L
+#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
+#define PORT_PB08E_TC4_WO0 (1ul << 8)
+#define PIN_PB12E_TC4_WO0 44L /**< \brief TC4 signal: WO0 on PB12 mux E */
+#define MUX_PB12E_TC4_WO0 4L
+#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0)
+#define PORT_PB12E_TC4_WO0 (1ul << 12)
+#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */
+#define MUX_PA23E_TC4_WO1 4L
+#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
+#define PORT_PA23E_TC4_WO1 (1ul << 23)
+#define PIN_PB09E_TC4_WO1 41L /**< \brief TC4 signal: WO1 on PB09 mux E */
+#define MUX_PB09E_TC4_WO1 4L
+#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
+#define PORT_PB09E_TC4_WO1 (1ul << 9)
+#define PIN_PB13E_TC4_WO1 45L /**< \brief TC4 signal: WO1 on PB13 mux E */
+#define MUX_PB13E_TC4_WO1 4L
+#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1)
+#define PORT_PB13E_TC4_WO1 (1ul << 13)
+/* ========== PORT definition for TC5 peripheral ========== */
+#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */
+#define MUX_PA24E_TC5_WO0 4L
+#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
+#define PORT_PA24E_TC5_WO0 (1ul << 24)
+#define PIN_PB10E_TC5_WO0 42L /**< \brief TC5 signal: WO0 on PB10 mux E */
+#define MUX_PB10E_TC5_WO0 4L
+#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
+#define PORT_PB10E_TC5_WO0 (1ul << 10)
+#define PIN_PB14E_TC5_WO0 46L /**< \brief TC5 signal: WO0 on PB14 mux E */
+#define MUX_PB14E_TC5_WO0 4L
+#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0)
+#define PORT_PB14E_TC5_WO0 (1ul << 14)
+#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */
+#define MUX_PA25E_TC5_WO1 4L
+#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
+#define PORT_PA25E_TC5_WO1 (1ul << 25)
+#define PIN_PB11E_TC5_WO1 43L /**< \brief TC5 signal: WO1 on PB11 mux E */
+#define MUX_PB11E_TC5_WO1 4L
+#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
+#define PORT_PB11E_TC5_WO1 (1ul << 11)
+#define PIN_PB15E_TC5_WO1 47L /**< \brief TC5 signal: WO1 on PB15 mux E */
+#define MUX_PB15E_TC5_WO1 4L
+#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1)
+#define PORT_PB15E_TC5_WO1 (1ul << 15)
+/* ========== PORT definition for TC6 peripheral ========== */
+#define PIN_PB02E_TC6_WO0 34L /**< \brief TC6 signal: WO0 on PB02 mux E */
+#define MUX_PB02E_TC6_WO0 4L
+#define PINMUX_PB02E_TC6_WO0 ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0)
+#define PORT_PB02E_TC6_WO0 (1ul << 2)
+#define PIN_PB16E_TC6_WO0 48L /**< \brief TC6 signal: WO0 on PB16 mux E */
+#define MUX_PB16E_TC6_WO0 4L
+#define PINMUX_PB16E_TC6_WO0 ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0)
+#define PORT_PB16E_TC6_WO0 (1ul << 16)
+#define PIN_PB03E_TC6_WO1 35L /**< \brief TC6 signal: WO1 on PB03 mux E */
+#define MUX_PB03E_TC6_WO1 4L
+#define PINMUX_PB03E_TC6_WO1 ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1)
+#define PORT_PB03E_TC6_WO1 (1ul << 3)
+#define PIN_PB17E_TC6_WO1 49L /**< \brief TC6 signal: WO1 on PB17 mux E */
+#define MUX_PB17E_TC6_WO1 4L
+#define PINMUX_PB17E_TC6_WO1 ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1)
+#define PORT_PB17E_TC6_WO1 (1ul << 17)
+/* ========== PORT definition for TC7 peripheral ========== */
+#define PIN_PA20E_TC7_WO0 20L /**< \brief TC7 signal: WO0 on PA20 mux E */
+#define MUX_PA20E_TC7_WO0 4L
+#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0)
+#define PORT_PA20E_TC7_WO0 (1ul << 20)
+#define PIN_PB00E_TC7_WO0 32L /**< \brief TC7 signal: WO0 on PB00 mux E */
+#define MUX_PB00E_TC7_WO0 4L
+#define PINMUX_PB00E_TC7_WO0 ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0)
+#define PORT_PB00E_TC7_WO0 (1ul << 0)
+#define PIN_PB22E_TC7_WO0 54L /**< \brief TC7 signal: WO0 on PB22 mux E */
+#define MUX_PB22E_TC7_WO0 4L
+#define PINMUX_PB22E_TC7_WO0 ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0)
+#define PORT_PB22E_TC7_WO0 (1ul << 22)
+#define PIN_PA21E_TC7_WO1 21L /**< \brief TC7 signal: WO1 on PA21 mux E */
+#define MUX_PA21E_TC7_WO1 4L
+#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1)
+#define PORT_PA21E_TC7_WO1 (1ul << 21)
+#define PIN_PB01E_TC7_WO1 33L /**< \brief TC7 signal: WO1 on PB01 mux E */
+#define MUX_PB01E_TC7_WO1 4L
+#define PINMUX_PB01E_TC7_WO1 ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1)
+#define PORT_PB01E_TC7_WO1 (1ul << 1)
+#define PIN_PB23E_TC7_WO1 55L /**< \brief TC7 signal: WO1 on PB23 mux E */
+#define MUX_PB23E_TC7_WO1 4L
+#define PINMUX_PB23E_TC7_WO1 ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1)
+#define PORT_PB23E_TC7_WO1 (1ul << 23)
+/* ========== PORT definition for ADC peripheral ========== */
+#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */
+#define MUX_PA02B_ADC_AIN0 1L
+#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0)
+#define PORT_PA02B_ADC_AIN0 (1ul << 2)
+#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */
+#define MUX_PA03B_ADC_AIN1 1L
+#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1)
+#define PORT_PA03B_ADC_AIN1 (1ul << 3)
+#define PIN_PB08B_ADC_AIN2 40L /**< \brief ADC signal: AIN2 on PB08 mux B */
+#define MUX_PB08B_ADC_AIN2 1L
+#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2)
+#define PORT_PB08B_ADC_AIN2 (1ul << 8)
+#define PIN_PB09B_ADC_AIN3 41L /**< \brief ADC signal: AIN3 on PB09 mux B */
+#define MUX_PB09B_ADC_AIN3 1L
+#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3)
+#define PORT_PB09B_ADC_AIN3 (1ul << 9)
+#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */
+#define MUX_PA04B_ADC_AIN4 1L
+#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4)
+#define PORT_PA04B_ADC_AIN4 (1ul << 4)
+#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */
+#define MUX_PA05B_ADC_AIN5 1L
+#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5)
+#define PORT_PA05B_ADC_AIN5 (1ul << 5)
+#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */
+#define MUX_PA06B_ADC_AIN6 1L
+#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6)
+#define PORT_PA06B_ADC_AIN6 (1ul << 6)
+#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */
+#define MUX_PA07B_ADC_AIN7 1L
+#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7)
+#define PORT_PA07B_ADC_AIN7 (1ul << 7)
+#define PIN_PB00B_ADC_AIN8 32L /**< \brief ADC signal: AIN8 on PB00 mux B */
+#define MUX_PB00B_ADC_AIN8 1L
+#define PINMUX_PB00B_ADC_AIN8 ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8)
+#define PORT_PB00B_ADC_AIN8 (1ul << 0)
+#define PIN_PB01B_ADC_AIN9 33L /**< \brief ADC signal: AIN9 on PB01 mux B */
+#define MUX_PB01B_ADC_AIN9 1L
+#define PINMUX_PB01B_ADC_AIN9 ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9)
+#define PORT_PB01B_ADC_AIN9 (1ul << 1)
+#define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */
+#define MUX_PB02B_ADC_AIN10 1L
+#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10)
+#define PORT_PB02B_ADC_AIN10 (1ul << 2)
+#define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */
+#define MUX_PB03B_ADC_AIN11 1L
+#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11)
+#define PORT_PB03B_ADC_AIN11 (1ul << 3)
+#define PIN_PB04B_ADC_AIN12 36L /**< \brief ADC signal: AIN12 on PB04 mux B */
+#define MUX_PB04B_ADC_AIN12 1L
+#define PINMUX_PB04B_ADC_AIN12 ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12)
+#define PORT_PB04B_ADC_AIN12 (1ul << 4)
+#define PIN_PB05B_ADC_AIN13 37L /**< \brief ADC signal: AIN13 on PB05 mux B */
+#define MUX_PB05B_ADC_AIN13 1L
+#define PINMUX_PB05B_ADC_AIN13 ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13)
+#define PORT_PB05B_ADC_AIN13 (1ul << 5)
+#define PIN_PB06B_ADC_AIN14 38L /**< \brief ADC signal: AIN14 on PB06 mux B */
+#define MUX_PB06B_ADC_AIN14 1L
+#define PINMUX_PB06B_ADC_AIN14 ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14)
+#define PORT_PB06B_ADC_AIN14 (1ul << 6)
+#define PIN_PB07B_ADC_AIN15 39L /**< \brief ADC signal: AIN15 on PB07 mux B */
+#define MUX_PB07B_ADC_AIN15 1L
+#define PINMUX_PB07B_ADC_AIN15 ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15)
+#define PORT_PB07B_ADC_AIN15 (1ul << 7)
+#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */
+#define MUX_PA08B_ADC_AIN16 1L
+#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16)
+#define PORT_PA08B_ADC_AIN16 (1ul << 8)
+#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */
+#define MUX_PA09B_ADC_AIN17 1L
+#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17)
+#define PORT_PA09B_ADC_AIN17 (1ul << 9)
+#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */
+#define MUX_PA10B_ADC_AIN18 1L
+#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18)
+#define PORT_PA10B_ADC_AIN18 (1ul << 10)
+#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */
+#define MUX_PA11B_ADC_AIN19 1L
+#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19)
+#define PORT_PA11B_ADC_AIN19 (1ul << 11)
+#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */
+#define MUX_PA04B_ADC_VREFP 1L
+#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP)
+#define PORT_PA04B_ADC_VREFP (1ul << 4)
+/* ========== PORT definition for AC peripheral ========== */
+#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */
+#define MUX_PA04B_AC_AIN0 1L
+#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
+#define PORT_PA04B_AC_AIN0 (1ul << 4)
+#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */
+#define MUX_PA05B_AC_AIN1 1L
+#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
+#define PORT_PA05B_AC_AIN1 (1ul << 5)
+#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */
+#define MUX_PA06B_AC_AIN2 1L
+#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
+#define PORT_PA06B_AC_AIN2 (1ul << 6)
+#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */
+#define MUX_PA07B_AC_AIN3 1L
+#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
+#define PORT_PA07B_AC_AIN3 (1ul << 7)
+#define PIN_PA12H_AC_CMP0 12L /**< \brief AC signal: CMP0 on PA12 mux H */
+#define MUX_PA12H_AC_CMP0 7L
+#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0)
+#define PORT_PA12H_AC_CMP0 (1ul << 12)
+#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */
+#define MUX_PA18H_AC_CMP0 7L
+#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
+#define PORT_PA18H_AC_CMP0 (1ul << 18)
+#define PIN_PA13H_AC_CMP1 13L /**< \brief AC signal: CMP1 on PA13 mux H */
+#define MUX_PA13H_AC_CMP1 7L
+#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1)
+#define PORT_PA13H_AC_CMP1 (1ul << 13)
+#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */
+#define MUX_PA19H_AC_CMP1 7L
+#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
+#define PORT_PA19H_AC_CMP1 (1ul << 19)
+/* ========== PORT definition for DAC peripheral ========== */
+#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */
+#define MUX_PA02B_DAC_VOUT 1L
+#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
+#define PORT_PA02B_DAC_VOUT (1ul << 2)
+#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */
+#define MUX_PA03B_DAC_VREFP 1L
+#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
+#define PORT_PA03B_DAC_VREFP (1ul << 3)
+/* ========== PORT definition for I2S peripheral ========== */
+#define PIN_PA11G_I2S_FS0 11L /**< \brief I2S signal: FS0 on PA11 mux G */
+#define MUX_PA11G_I2S_FS0 6L
+#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0)
+#define PORT_PA11G_I2S_FS0 (1ul << 11)
+#define PIN_PA21G_I2S_FS0 21L /**< \brief I2S signal: FS0 on PA21 mux G */
+#define MUX_PA21G_I2S_FS0 6L
+#define PINMUX_PA21G_I2S_FS0 ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0)
+#define PORT_PA21G_I2S_FS0 (1ul << 21)
+#define PIN_PB12G_I2S_FS1 44L /**< \brief I2S signal: FS1 on PB12 mux G */
+#define MUX_PB12G_I2S_FS1 6L
+#define PINMUX_PB12G_I2S_FS1 ((PIN_PB12G_I2S_FS1 << 16) | MUX_PB12G_I2S_FS1)
+#define PORT_PB12G_I2S_FS1 (1ul << 12)
+#define PIN_PA09G_I2S_MCK0 9L /**< \brief I2S signal: MCK0 on PA09 mux G */
+#define MUX_PA09G_I2S_MCK0 6L
+#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0)
+#define PORT_PA09G_I2S_MCK0 (1ul << 9)
+#define PIN_PB17G_I2S_MCK0 49L /**< \brief I2S signal: MCK0 on PB17 mux G */
+#define MUX_PB17G_I2S_MCK0 6L
+#define PINMUX_PB17G_I2S_MCK0 ((PIN_PB17G_I2S_MCK0 << 16) | MUX_PB17G_I2S_MCK0)
+#define PORT_PB17G_I2S_MCK0 (1ul << 17)
+#define PIN_PB10G_I2S_MCK1 42L /**< \brief I2S signal: MCK1 on PB10 mux G */
+#define MUX_PB10G_I2S_MCK1 6L
+#define PINMUX_PB10G_I2S_MCK1 ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1)
+#define PORT_PB10G_I2S_MCK1 (1ul << 10)
+#define PIN_PA10G_I2S_SCK0 10L /**< \brief I2S signal: SCK0 on PA10 mux G */
+#define MUX_PA10G_I2S_SCK0 6L
+#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0)
+#define PORT_PA10G_I2S_SCK0 (1ul << 10)
+#define PIN_PA20G_I2S_SCK0 20L /**< \brief I2S signal: SCK0 on PA20 mux G */
+#define MUX_PA20G_I2S_SCK0 6L
+#define PINMUX_PA20G_I2S_SCK0 ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0)
+#define PORT_PA20G_I2S_SCK0 (1ul << 20)
+#define PIN_PB11G_I2S_SCK1 43L /**< \brief I2S signal: SCK1 on PB11 mux G */
+#define MUX_PB11G_I2S_SCK1 6L
+#define PINMUX_PB11G_I2S_SCK1 ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1)
+#define PORT_PB11G_I2S_SCK1 (1ul << 11)
+#define PIN_PA07G_I2S_SD0 7L /**< \brief I2S signal: SD0 on PA07 mux G */
+#define MUX_PA07G_I2S_SD0 6L
+#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0)
+#define PORT_PA07G_I2S_SD0 (1ul << 7)
+#define PIN_PA19G_I2S_SD0 19L /**< \brief I2S signal: SD0 on PA19 mux G */
+#define MUX_PA19G_I2S_SD0 6L
+#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0)
+#define PORT_PA19G_I2S_SD0 (1ul << 19)
+#define PIN_PA08G_I2S_SD1 8L /**< \brief I2S signal: SD1 on PA08 mux G */
+#define MUX_PA08G_I2S_SD1 6L
+#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1)
+#define PORT_PA08G_I2S_SD1 (1ul << 8)
+#define PIN_PB16G_I2S_SD1 48L /**< \brief I2S signal: SD1 on PB16 mux G */
+#define MUX_PB16G_I2S_SD1 6L
+#define PINMUX_PB16G_I2S_SD1 ((PIN_PB16G_I2S_SD1 << 16) | MUX_PB16G_I2S_SD1)
+#define PORT_PB16G_I2S_SD1 (1ul << 16)
+
+#endif /* _SAMD21J18A_PIO_ */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/samd21.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/samd21.h
new file mode 100644
index 0000000000000000000000000000000000000000..2d94c3f451ebfc6e273ab5f0ad48750d8e04fa96
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/samd21.h
@@ -0,0 +1,90 @@
+/**
+ * \file
+ *
+ * \brief Top header file for SAMD21
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21_
+#define _SAMD21_
+
+/**
+ * \defgroup SAMD21_definitions SAMD21 Device Definitions
+ * \brief SAMD21 CMSIS Definitions.
+ */
+
+#if defined(__SAMD21E15A__) || defined(__ATSAMD21E15A__)
+ #include "samd21e15a.h"
+#elif defined(__SAMD21E16A__) || defined(__ATSAMD21E16A__)
+ #include "samd21e16a.h"
+#elif defined(__SAMD21E17A__) || defined(__ATSAMD21E17A__)
+ #include "samd21e17a.h"
+#elif defined(__SAMD21E18A__) || defined(__ATSAMD21E18A__)
+ #include "samd21e18a.h"
+#elif defined(__SAMD21G15A__) || defined(__ATSAMD21G15A__)
+ #include "samd21g15a.h"
+#elif defined(__SAMD21G16A__) || defined(__ATSAMD21G16A__)
+ #include "samd21g16a.h"
+#elif defined(__SAMD21G17A__) || defined(__ATSAMD21G17A__)
+ #include "samd21g17a.h"
+#elif defined(__SAMD21G17AU__) || defined(__ATSAMD21G17AU__)
+ #include "samd21g17au.h"
+#elif defined(__SAMD21G18A__) || defined(__ATSAMD21G18A__)
+ #include "samd21g18a.h"
+#elif defined(__SAMD21G18AU__) || defined(__ATSAMD21G18AU__)
+ #include "samd21g18au.h"
+#elif defined(__SAMD21J15A__) || defined(__ATSAMD21J15A__)
+ #include "samd21j15a.h"
+#elif defined(__SAMD21J16A__) || defined(__ATSAMD21J16A__)
+ #include "samd21j16a.h"
+#elif defined(__SAMD21J16AC__) || defined(__ATSAMD21J16AC__)
+ #include "samd21j16ac.h"
+#elif defined(__SAMD21J17A__) || defined(__ATSAMD21J17A__)
+ #include "samd21j17a.h"
+#elif defined(__SAMD21J17AC__) || defined(__ATSAMD21J17AC__)
+ #include "samd21j17ac.h"
+#elif defined(__SAMD21J18A__) || defined(__ATSAMD21J18A__)
+ #include "samd21j18a.h"
+#elif defined(__SAMD21J18AC__) || defined(__ATSAMD21J18AC__)
+ #include "samd21j18ac.h"
+#else
+ #error Library does not support the specified device.
+#endif
+
+#endif /* _SAMD21_ */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/samd21e15a.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/samd21e15a.h
new file mode 100644
index 0000000000000000000000000000000000000000..e934d3614a84afddfca7fa16dbee28454d36b530
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/samd21e15a.h
@@ -0,0 +1,557 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21E15A
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21E15A_
+#define _SAMD21E15A_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21E15A_definitions SAMD21E15A definitions
+ * This file defines all structures and symbols for SAMD21E15A:
+ * - registers and bitfields
+ * - peripheral base address
+ * - peripheral ID
+ * - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#else
+typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
+typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/** CMSIS DEFINITIONS FOR SAMD21E15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E15A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21E15A-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21E15A Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21E15A System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21E15A Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21E15A Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21E15A External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21E15A Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21E15A Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21E15A Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21E15A Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21E15A Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21E15A Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21E15A Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21E15A Serial Communication Interface 3 (SERCOM3) */
+ TCC0_IRQn = 15, /**< 15 SAMD21E15A Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21E15A Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21E15A Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21E15A Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21E15A Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21E15A Basic Timer Counter 5 (TC5) */
+ ADC_IRQn = 23, /**< 23 SAMD21E15A Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21E15A Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21E15A Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21E15A Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21E15A Inter-IC Sound Interface (I2S) */
+
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnReserved13;
+ void* pfnReserved14;
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnReserved21;
+ void* pfnReserved22;
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+ void* pfnReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler ( void );
+void NMI_Handler ( void );
+void HardFault_Handler ( void );
+void SVC_Handler ( void );
+void PendSV_Handler ( void );
+void SysTick_Handler ( void );
+
+/* Peripherals handlers */
+void PM_Handler ( void );
+void SYSCTRL_Handler ( void );
+void WDT_Handler ( void );
+void RTC_Handler ( void );
+void EIC_Handler ( void );
+void NVMCTRL_Handler ( void );
+void DMAC_Handler ( void );
+void USB_Handler ( void );
+void EVSYS_Handler ( void );
+void SERCOM0_Handler ( void );
+void SERCOM1_Handler ( void );
+void SERCOM2_Handler ( void );
+void SERCOM3_Handler ( void );
+void TCC0_Handler ( void );
+void TCC1_Handler ( void );
+void TCC2_Handler ( void );
+void TC3_Handler ( void );
+void TC4_Handler ( void );
+void TC5_Handler ( void );
+void ADC_Handler ( void );
+void AC_Handler ( void );
+void DAC_Handler ( void );
+void PTC_Handler ( void );
+void I2S_Handler ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN 1
+#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 0 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT 1 /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E15A_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** REGISTERS ACCESS DEFINITIONS FOR SAMD21E15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E15A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** PERIPHERAL ID DEFINITIONS FOR SAMD21E15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E15A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM 1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT 35 /**< \brief Port Module (PORT) */
+#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC 81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/** BASE ADDRESS DEFINITIONS FOR SAMD21E15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E15A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define ADC (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S (0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0 (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1 (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2 (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0 (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4 (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5 (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TCC0 (0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1 (0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2 (0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define USB (0x41005000UL) /**< \brief (USB) APB Base Address */
+#define WDT (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
+#define AC_INSTS { AC } /**< \brief (AC) Instances List */
+
+#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */
+#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */
+
+#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */
+#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */
+
+#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
+
+#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
+#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */
+
+#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
+#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */
+
+#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */
+
+#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */
+
+#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */
+#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */
+
+#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
+#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
+
+#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */
+#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */
+
+#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
+#define PM_INSTS { PM } /**< \brief (PM) Instances List */
+
+#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
+#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID 34
+#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */
+#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */
+
+#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
+#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */
+
+#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */
+
+#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */
+#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */
+
+#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */
+#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
+
+#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */
+#define USB_INSTS { USB } /**< \brief (USB) Instances List */
+
+#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
+#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/** PORT DEFINITIONS FOR SAMD21E15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E15A_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21e15a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** MEMORY MAPPING DEFINITIONS FOR SAMD21E15A */
+/* ************************************************************************** */
+
+#define FLASH_SIZE 0x8000UL /* 32 kB */
+#define FLASH_PAGE_SIZE 64
+#define FLASH_NB_OF_PAGES 512
+#define FLASH_USER_PAGE_SIZE 64
+#define HMCRAMC0_SIZE 0x1000UL /* 4 kB */
+
+#define FLASH_ADDR (0x00000000u) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR (0x20000000u) /**< HMCRAMC0 base address */
+#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */
+#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */
+#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */
+#define PPB_ADDR (0xE0000000u) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE 0x1001000DUL
+#define EIC_EXTINT_NUM 16
+#define PORT_GROUPS 1
+
+/* ************************************************************************** */
+/** ELECTRICAL DEFINITIONS FOR SAMD21E15A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21E15A_H */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/samd21e16a.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/samd21e16a.h
new file mode 100644
index 0000000000000000000000000000000000000000..2291854563f1087fea930287c9f3c7f48c5b36b9
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/samd21e16a.h
@@ -0,0 +1,557 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21E16A
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21E16A_
+#define _SAMD21E16A_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21E16A_definitions SAMD21E16A definitions
+ * This file defines all structures and symbols for SAMD21E16A:
+ * - registers and bitfields
+ * - peripheral base address
+ * - peripheral ID
+ * - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#else
+typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
+typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/** CMSIS DEFINITIONS FOR SAMD21E16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E16A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21E16A-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21E16A Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21E16A System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21E16A Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21E16A Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21E16A External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21E16A Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21E16A Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21E16A Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21E16A Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21E16A Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21E16A Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21E16A Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21E16A Serial Communication Interface 3 (SERCOM3) */
+ TCC0_IRQn = 15, /**< 15 SAMD21E16A Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21E16A Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21E16A Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21E16A Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21E16A Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21E16A Basic Timer Counter 5 (TC5) */
+ ADC_IRQn = 23, /**< 23 SAMD21E16A Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21E16A Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21E16A Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21E16A Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21E16A Inter-IC Sound Interface (I2S) */
+
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnReserved13;
+ void* pfnReserved14;
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnReserved21;
+ void* pfnReserved22;
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+ void* pfnReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler ( void );
+void NMI_Handler ( void );
+void HardFault_Handler ( void );
+void SVC_Handler ( void );
+void PendSV_Handler ( void );
+void SysTick_Handler ( void );
+
+/* Peripherals handlers */
+void PM_Handler ( void );
+void SYSCTRL_Handler ( void );
+void WDT_Handler ( void );
+void RTC_Handler ( void );
+void EIC_Handler ( void );
+void NVMCTRL_Handler ( void );
+void DMAC_Handler ( void );
+void USB_Handler ( void );
+void EVSYS_Handler ( void );
+void SERCOM0_Handler ( void );
+void SERCOM1_Handler ( void );
+void SERCOM2_Handler ( void );
+void SERCOM3_Handler ( void );
+void TCC0_Handler ( void );
+void TCC1_Handler ( void );
+void TCC2_Handler ( void );
+void TC3_Handler ( void );
+void TC4_Handler ( void );
+void TC5_Handler ( void );
+void ADC_Handler ( void );
+void AC_Handler ( void );
+void DAC_Handler ( void );
+void PTC_Handler ( void );
+void I2S_Handler ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN 1
+#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 0 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT 1 /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E16A_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** REGISTERS ACCESS DEFINITIONS FOR SAMD21E16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E16A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** PERIPHERAL ID DEFINITIONS FOR SAMD21E16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E16A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM 1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT 35 /**< \brief Port Module (PORT) */
+#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC 81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/** BASE ADDRESS DEFINITIONS FOR SAMD21E16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E16A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define ADC (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S (0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0 (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1 (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2 (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0 (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4 (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5 (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TCC0 (0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1 (0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2 (0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define USB (0x41005000UL) /**< \brief (USB) APB Base Address */
+#define WDT (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
+#define AC_INSTS { AC } /**< \brief (AC) Instances List */
+
+#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */
+#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */
+
+#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */
+#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */
+
+#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
+
+#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
+#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */
+
+#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
+#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */
+
+#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */
+
+#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */
+
+#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */
+#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */
+
+#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
+#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
+
+#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */
+#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */
+
+#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
+#define PM_INSTS { PM } /**< \brief (PM) Instances List */
+
+#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
+#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID 34
+#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */
+#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */
+
+#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
+#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */
+
+#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */
+
+#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */
+#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */
+
+#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */
+#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
+
+#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */
+#define USB_INSTS { USB } /**< \brief (USB) Instances List */
+
+#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
+#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/** PORT DEFINITIONS FOR SAMD21E16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E16A_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21e16a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** MEMORY MAPPING DEFINITIONS FOR SAMD21E16A */
+/* ************************************************************************** */
+
+#define FLASH_SIZE 0x10000UL /* 64 kB */
+#define FLASH_PAGE_SIZE 64
+#define FLASH_NB_OF_PAGES 1024
+#define FLASH_USER_PAGE_SIZE 64
+#define HMCRAMC0_SIZE 0x2000UL /* 8 kB */
+
+#define FLASH_ADDR (0x00000000u) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR (0x20000000u) /**< HMCRAMC0 base address */
+#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */
+#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */
+#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */
+#define PPB_ADDR (0xE0000000u) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE 0x1001000CUL
+#define EIC_EXTINT_NUM 16
+#define PORT_GROUPS 1
+
+/* ************************************************************************** */
+/** ELECTRICAL DEFINITIONS FOR SAMD21E16A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21E16A_H */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/samd21e17a.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/samd21e17a.h
new file mode 100644
index 0000000000000000000000000000000000000000..590d6c08eee445fdd4e748ff3cecb5fc0b36721c
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/samd21e17a.h
@@ -0,0 +1,557 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21E17A
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21E17A_
+#define _SAMD21E17A_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21E17A_definitions SAMD21E17A definitions
+ * This file defines all structures and symbols for SAMD21E17A:
+ * - registers and bitfields
+ * - peripheral base address
+ * - peripheral ID
+ * - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#else
+typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
+typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/** CMSIS DEFINITIONS FOR SAMD21E17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E17A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21E17A-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21E17A Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21E17A System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21E17A Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21E17A Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21E17A External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21E17A Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21E17A Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21E17A Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21E17A Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21E17A Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21E17A Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21E17A Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21E17A Serial Communication Interface 3 (SERCOM3) */
+ TCC0_IRQn = 15, /**< 15 SAMD21E17A Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21E17A Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21E17A Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21E17A Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21E17A Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21E17A Basic Timer Counter 5 (TC5) */
+ ADC_IRQn = 23, /**< 23 SAMD21E17A Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21E17A Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21E17A Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21E17A Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21E17A Inter-IC Sound Interface (I2S) */
+
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnReserved13;
+ void* pfnReserved14;
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnReserved21;
+ void* pfnReserved22;
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+ void* pfnReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler ( void );
+void NMI_Handler ( void );
+void HardFault_Handler ( void );
+void SVC_Handler ( void );
+void PendSV_Handler ( void );
+void SysTick_Handler ( void );
+
+/* Peripherals handlers */
+void PM_Handler ( void );
+void SYSCTRL_Handler ( void );
+void WDT_Handler ( void );
+void RTC_Handler ( void );
+void EIC_Handler ( void );
+void NVMCTRL_Handler ( void );
+void DMAC_Handler ( void );
+void USB_Handler ( void );
+void EVSYS_Handler ( void );
+void SERCOM0_Handler ( void );
+void SERCOM1_Handler ( void );
+void SERCOM2_Handler ( void );
+void SERCOM3_Handler ( void );
+void TCC0_Handler ( void );
+void TCC1_Handler ( void );
+void TCC2_Handler ( void );
+void TC3_Handler ( void );
+void TC4_Handler ( void );
+void TC5_Handler ( void );
+void ADC_Handler ( void );
+void AC_Handler ( void );
+void DAC_Handler ( void );
+void PTC_Handler ( void );
+void I2S_Handler ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN 1
+#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 0 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT 1 /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E17A_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** REGISTERS ACCESS DEFINITIONS FOR SAMD21E17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E17A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** PERIPHERAL ID DEFINITIONS FOR SAMD21E17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E17A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM 1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT 35 /**< \brief Port Module (PORT) */
+#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC 81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/** BASE ADDRESS DEFINITIONS FOR SAMD21E17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E17A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define ADC (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S (0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0 (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1 (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2 (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0 (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4 (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5 (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TCC0 (0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1 (0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2 (0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define USB (0x41005000UL) /**< \brief (USB) APB Base Address */
+#define WDT (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
+#define AC_INSTS { AC } /**< \brief (AC) Instances List */
+
+#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */
+#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */
+
+#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */
+#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */
+
+#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
+
+#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
+#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */
+
+#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
+#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */
+
+#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */
+
+#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */
+
+#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */
+#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */
+
+#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
+#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
+
+#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */
+#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */
+
+#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
+#define PM_INSTS { PM } /**< \brief (PM) Instances List */
+
+#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
+#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID 34
+#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */
+#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */
+
+#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
+#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */
+
+#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */
+
+#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */
+#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */
+
+#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */
+#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
+
+#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */
+#define USB_INSTS { USB } /**< \brief (USB) Instances List */
+
+#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
+#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/** PORT DEFINITIONS FOR SAMD21E17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E17A_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21e17a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** MEMORY MAPPING DEFINITIONS FOR SAMD21E17A */
+/* ************************************************************************** */
+
+#define FLASH_SIZE 0x20000UL /* 128 kB */
+#define FLASH_PAGE_SIZE 64
+#define FLASH_NB_OF_PAGES 2048
+#define FLASH_USER_PAGE_SIZE 64
+#define HMCRAMC0_SIZE 0x4000UL /* 16 kB */
+
+#define FLASH_ADDR (0x00000000u) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR (0x20000000u) /**< HMCRAMC0 base address */
+#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */
+#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */
+#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */
+#define PPB_ADDR (0xE0000000u) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE 0x1001000BUL
+#define EIC_EXTINT_NUM 16
+#define PORT_GROUPS 1
+
+/* ************************************************************************** */
+/** ELECTRICAL DEFINITIONS FOR SAMD21E17A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21E17A_H */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/samd21e18a.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/samd21e18a.h
new file mode 100644
index 0000000000000000000000000000000000000000..79e262ac7ddc68fc449c758508c2002eb3bd1dc1
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/samd21e18a.h
@@ -0,0 +1,557 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21E18A
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21E18A_
+#define _SAMD21E18A_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21E18A_definitions SAMD21E18A definitions
+ * This file defines all structures and symbols for SAMD21E18A:
+ * - registers and bitfields
+ * - peripheral base address
+ * - peripheral ID
+ * - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#else
+typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
+typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/** CMSIS DEFINITIONS FOR SAMD21E18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E18A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21E18A-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21E18A Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21E18A System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21E18A Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21E18A Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21E18A External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21E18A Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21E18A Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21E18A Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21E18A Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21E18A Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21E18A Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21E18A Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21E18A Serial Communication Interface 3 (SERCOM3) */
+ TCC0_IRQn = 15, /**< 15 SAMD21E18A Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21E18A Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21E18A Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21E18A Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21E18A Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21E18A Basic Timer Counter 5 (TC5) */
+ ADC_IRQn = 23, /**< 23 SAMD21E18A Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21E18A Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21E18A Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21E18A Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21E18A Inter-IC Sound Interface (I2S) */
+
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnReserved13;
+ void* pfnReserved14;
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnReserved21;
+ void* pfnReserved22;
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+ void* pfnReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler ( void );
+void NMI_Handler ( void );
+void HardFault_Handler ( void );
+void SVC_Handler ( void );
+void PendSV_Handler ( void );
+void SysTick_Handler ( void );
+
+/* Peripherals handlers */
+void PM_Handler ( void );
+void SYSCTRL_Handler ( void );
+void WDT_Handler ( void );
+void RTC_Handler ( void );
+void EIC_Handler ( void );
+void NVMCTRL_Handler ( void );
+void DMAC_Handler ( void );
+void USB_Handler ( void );
+void EVSYS_Handler ( void );
+void SERCOM0_Handler ( void );
+void SERCOM1_Handler ( void );
+void SERCOM2_Handler ( void );
+void SERCOM3_Handler ( void );
+void TCC0_Handler ( void );
+void TCC1_Handler ( void );
+void TCC2_Handler ( void );
+void TC3_Handler ( void );
+void TC4_Handler ( void );
+void TC5_Handler ( void );
+void ADC_Handler ( void );
+void AC_Handler ( void );
+void DAC_Handler ( void );
+void PTC_Handler ( void );
+void I2S_Handler ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN 1
+#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 0 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT 1 /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E18A_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** REGISTERS ACCESS DEFINITIONS FOR SAMD21E18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E18A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** PERIPHERAL ID DEFINITIONS FOR SAMD21E18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E18A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM 1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT 35 /**< \brief Port Module (PORT) */
+#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC 81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/** BASE ADDRESS DEFINITIONS FOR SAMD21E18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E18A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define ADC (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S (0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0 (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1 (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2 (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0 (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4 (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5 (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TCC0 (0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1 (0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2 (0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define USB (0x41005000UL) /**< \brief (USB) APB Base Address */
+#define WDT (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
+#define AC_INSTS { AC } /**< \brief (AC) Instances List */
+
+#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */
+#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */
+
+#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */
+#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */
+
+#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
+
+#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
+#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */
+
+#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
+#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */
+
+#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */
+
+#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */
+
+#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */
+#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */
+
+#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
+#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
+
+#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */
+#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */
+
+#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
+#define PM_INSTS { PM } /**< \brief (PM) Instances List */
+
+#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
+#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID 34
+#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */
+#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */
+
+#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
+#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */
+
+#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */
+
+#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */
+#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */
+
+#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */
+#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
+
+#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */
+#define USB_INSTS { USB } /**< \brief (USB) Instances List */
+
+#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
+#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/** PORT DEFINITIONS FOR SAMD21E18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21E18A_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21e18a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** MEMORY MAPPING DEFINITIONS FOR SAMD21E18A */
+/* ************************************************************************** */
+
+#define FLASH_SIZE 0x40000UL /* 256 kB */
+#define FLASH_PAGE_SIZE 64
+#define FLASH_NB_OF_PAGES 4096
+#define FLASH_USER_PAGE_SIZE 64
+#define HMCRAMC0_SIZE 0x8000UL /* 32 kB */
+
+#define FLASH_ADDR (0x00000000u) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR (0x20000000u) /**< HMCRAMC0 base address */
+#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */
+#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */
+#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */
+#define PPB_ADDR (0xE0000000u) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE 0x1001000AUL
+#define EIC_EXTINT_NUM 16
+#define PORT_GROUPS 1
+
+/* ************************************************************************** */
+/** ELECTRICAL DEFINITIONS FOR SAMD21E18A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21E18A_H */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/samd21g15a.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/samd21g15a.h
new file mode 100644
index 0000000000000000000000000000000000000000..cb0a2b6d717c4dc5fe0bdfb0bacdf0536e342c21
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/samd21g15a.h
@@ -0,0 +1,569 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21G15A
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21G15A_
+#define _SAMD21G15A_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21G15A_definitions SAMD21G15A definitions
+ * This file defines all structures and symbols for SAMD21G15A:
+ * - registers and bitfields
+ * - peripheral base address
+ * - peripheral ID
+ * - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#else
+typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
+typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/** CMSIS DEFINITIONS FOR SAMD21G15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G15A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21G15A-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21G15A Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21G15A System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21G15A Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21G15A Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21G15A External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21G15A Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21G15A Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21G15A Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21G15A Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21G15A Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21G15A Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21G15A Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21G15A Serial Communication Interface 3 (SERCOM3) */
+ SERCOM4_IRQn = 13, /**< 13 SAMD21G15A Serial Communication Interface 4 (SERCOM4) */
+ SERCOM5_IRQn = 14, /**< 14 SAMD21G15A Serial Communication Interface 5 (SERCOM5) */
+ TCC0_IRQn = 15, /**< 15 SAMD21G15A Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21G15A Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21G15A Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21G15A Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21G15A Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21G15A Basic Timer Counter 5 (TC5) */
+ ADC_IRQn = 23, /**< 23 SAMD21G15A Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21G15A Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21G15A Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21G15A Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21G15A Inter-IC Sound Interface (I2S) */
+
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
+ void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnReserved21;
+ void* pfnReserved22;
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+ void* pfnReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler ( void );
+void NMI_Handler ( void );
+void HardFault_Handler ( void );
+void SVC_Handler ( void );
+void PendSV_Handler ( void );
+void SysTick_Handler ( void );
+
+/* Peripherals handlers */
+void PM_Handler ( void );
+void SYSCTRL_Handler ( void );
+void WDT_Handler ( void );
+void RTC_Handler ( void );
+void EIC_Handler ( void );
+void NVMCTRL_Handler ( void );
+void DMAC_Handler ( void );
+void USB_Handler ( void );
+void EVSYS_Handler ( void );
+void SERCOM0_Handler ( void );
+void SERCOM1_Handler ( void );
+void SERCOM2_Handler ( void );
+void SERCOM3_Handler ( void );
+void SERCOM4_Handler ( void );
+void SERCOM5_Handler ( void );
+void TCC0_Handler ( void );
+void TCC1_Handler ( void );
+void TCC2_Handler ( void );
+void TC3_Handler ( void );
+void TC4_Handler ( void );
+void TC5_Handler ( void );
+void ADC_Handler ( void );
+void AC_Handler ( void );
+void DAC_Handler ( void );
+void PTC_Handler ( void );
+void I2S_Handler ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN 1
+#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 0 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT 1 /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G15A_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** REGISTERS ACCESS DEFINITIONS FOR SAMD21G15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G15A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** PERIPHERAL ID DEFINITIONS FOR SAMD21G15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G15A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM 1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT 35 /**< \brief Port Module (PORT) */
+#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC 81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/** BASE ADDRESS DEFINITIONS FOR SAMD21G15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G15A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define ADC (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S (0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0 (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1 (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2 (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0 (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4 (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5 (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4 (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5 (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TCC0 (0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1 (0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2 (0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define USB (0x41005000UL) /**< \brief (USB) APB Base Address */
+#define WDT (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
+#define AC_INSTS { AC } /**< \brief (AC) Instances List */
+
+#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */
+#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */
+
+#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */
+#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */
+
+#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
+
+#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
+#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */
+
+#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
+#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */
+
+#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */
+
+#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */
+
+#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */
+#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */
+
+#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
+#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
+
+#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */
+#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */
+
+#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
+#define PM_INSTS { PM } /**< \brief (PM) Instances List */
+
+#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
+#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID 34
+#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */
+#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */
+
+#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
+#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */
+
+#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */
+
+#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */
+#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */
+
+#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */
+#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
+
+#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */
+#define USB_INSTS { USB } /**< \brief (USB) Instances List */
+
+#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
+#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/** PORT DEFINITIONS FOR SAMD21G15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G15A_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21g15a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** MEMORY MAPPING DEFINITIONS FOR SAMD21G15A */
+/* ************************************************************************** */
+
+#define FLASH_SIZE 0x8000UL /* 32 kB */
+#define FLASH_PAGE_SIZE 64
+#define FLASH_NB_OF_PAGES 512
+#define FLASH_USER_PAGE_SIZE 64
+#define HMCRAMC0_SIZE 0x1000UL /* 4 kB */
+
+#define FLASH_ADDR (0x00000000u) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR (0x20000000u) /**< HMCRAMC0 base address */
+#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */
+#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */
+#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */
+#define PPB_ADDR (0xE0000000u) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE 0x10010008UL
+#define EIC_EXTINT_NUM 16
+#define PORT_GROUPS 2
+
+/* ************************************************************************** */
+/** ELECTRICAL DEFINITIONS FOR SAMD21G15A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21G15A_H */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/samd21g16a.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/samd21g16a.h
new file mode 100644
index 0000000000000000000000000000000000000000..9e9f3588cf93ad29a7d17d8e6d14b68b1bfb5469
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/samd21g16a.h
@@ -0,0 +1,569 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21G16A
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21G16A_
+#define _SAMD21G16A_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21G16A_definitions SAMD21G16A definitions
+ * This file defines all structures and symbols for SAMD21G16A:
+ * - registers and bitfields
+ * - peripheral base address
+ * - peripheral ID
+ * - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#else
+typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
+typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/** CMSIS DEFINITIONS FOR SAMD21G16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G16A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21G16A-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21G16A Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21G16A System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21G16A Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21G16A Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21G16A External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21G16A Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21G16A Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21G16A Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21G16A Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21G16A Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21G16A Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21G16A Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21G16A Serial Communication Interface 3 (SERCOM3) */
+ SERCOM4_IRQn = 13, /**< 13 SAMD21G16A Serial Communication Interface 4 (SERCOM4) */
+ SERCOM5_IRQn = 14, /**< 14 SAMD21G16A Serial Communication Interface 5 (SERCOM5) */
+ TCC0_IRQn = 15, /**< 15 SAMD21G16A Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21G16A Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21G16A Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21G16A Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21G16A Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21G16A Basic Timer Counter 5 (TC5) */
+ ADC_IRQn = 23, /**< 23 SAMD21G16A Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21G16A Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21G16A Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21G16A Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21G16A Inter-IC Sound Interface (I2S) */
+
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
+ void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnReserved21;
+ void* pfnReserved22;
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+ void* pfnReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler ( void );
+void NMI_Handler ( void );
+void HardFault_Handler ( void );
+void SVC_Handler ( void );
+void PendSV_Handler ( void );
+void SysTick_Handler ( void );
+
+/* Peripherals handlers */
+void PM_Handler ( void );
+void SYSCTRL_Handler ( void );
+void WDT_Handler ( void );
+void RTC_Handler ( void );
+void EIC_Handler ( void );
+void NVMCTRL_Handler ( void );
+void DMAC_Handler ( void );
+void USB_Handler ( void );
+void EVSYS_Handler ( void );
+void SERCOM0_Handler ( void );
+void SERCOM1_Handler ( void );
+void SERCOM2_Handler ( void );
+void SERCOM3_Handler ( void );
+void SERCOM4_Handler ( void );
+void SERCOM5_Handler ( void );
+void TCC0_Handler ( void );
+void TCC1_Handler ( void );
+void TCC2_Handler ( void );
+void TC3_Handler ( void );
+void TC4_Handler ( void );
+void TC5_Handler ( void );
+void ADC_Handler ( void );
+void AC_Handler ( void );
+void DAC_Handler ( void );
+void PTC_Handler ( void );
+void I2S_Handler ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN 1
+#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 0 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT 1 /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G16A_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** REGISTERS ACCESS DEFINITIONS FOR SAMD21G16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G16A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** PERIPHERAL ID DEFINITIONS FOR SAMD21G16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G16A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM 1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT 35 /**< \brief Port Module (PORT) */
+#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC 81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/** BASE ADDRESS DEFINITIONS FOR SAMD21G16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G16A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define ADC (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S (0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0 (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1 (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2 (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0 (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4 (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5 (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4 (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5 (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TCC0 (0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1 (0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2 (0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define USB (0x41005000UL) /**< \brief (USB) APB Base Address */
+#define WDT (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
+#define AC_INSTS { AC } /**< \brief (AC) Instances List */
+
+#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */
+#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */
+
+#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */
+#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */
+
+#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
+
+#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
+#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */
+
+#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
+#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */
+
+#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */
+
+#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */
+
+#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */
+#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */
+
+#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
+#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
+
+#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */
+#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */
+
+#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
+#define PM_INSTS { PM } /**< \brief (PM) Instances List */
+
+#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
+#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID 34
+#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */
+#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */
+
+#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
+#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */
+
+#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */
+
+#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */
+#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */
+
+#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */
+#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
+
+#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */
+#define USB_INSTS { USB } /**< \brief (USB) Instances List */
+
+#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
+#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/** PORT DEFINITIONS FOR SAMD21G16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G16A_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21g16a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** MEMORY MAPPING DEFINITIONS FOR SAMD21G16A */
+/* ************************************************************************** */
+
+#define FLASH_SIZE 0x10000UL /* 64 kB */
+#define FLASH_PAGE_SIZE 64
+#define FLASH_NB_OF_PAGES 1024
+#define FLASH_USER_PAGE_SIZE 64
+#define HMCRAMC0_SIZE 0x2000UL /* 8 kB */
+
+#define FLASH_ADDR (0x00000000u) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR (0x20000000u) /**< HMCRAMC0 base address */
+#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */
+#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */
+#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */
+#define PPB_ADDR (0xE0000000u) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE 0x10010007UL
+#define EIC_EXTINT_NUM 16
+#define PORT_GROUPS 2
+
+/* ************************************************************************** */
+/** ELECTRICAL DEFINITIONS FOR SAMD21G16A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21G16A_H */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/samd21g17a.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/samd21g17a.h
new file mode 100644
index 0000000000000000000000000000000000000000..a49d473cabfe81d6904acd69409f6e1815157a28
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/samd21g17a.h
@@ -0,0 +1,569 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21G17A
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21G17A_
+#define _SAMD21G17A_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21G17A_definitions SAMD21G17A definitions
+ * This file defines all structures and symbols for SAMD21G17A:
+ * - registers and bitfields
+ * - peripheral base address
+ * - peripheral ID
+ * - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#else
+typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
+typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/** CMSIS DEFINITIONS FOR SAMD21G17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G17A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21G17A-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21G17A Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21G17A System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21G17A Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21G17A Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21G17A External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21G17A Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21G17A Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21G17A Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21G17A Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21G17A Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21G17A Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21G17A Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21G17A Serial Communication Interface 3 (SERCOM3) */
+ SERCOM4_IRQn = 13, /**< 13 SAMD21G17A Serial Communication Interface 4 (SERCOM4) */
+ SERCOM5_IRQn = 14, /**< 14 SAMD21G17A Serial Communication Interface 5 (SERCOM5) */
+ TCC0_IRQn = 15, /**< 15 SAMD21G17A Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21G17A Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21G17A Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21G17A Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21G17A Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21G17A Basic Timer Counter 5 (TC5) */
+ ADC_IRQn = 23, /**< 23 SAMD21G17A Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21G17A Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21G17A Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21G17A Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21G17A Inter-IC Sound Interface (I2S) */
+
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
+ void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnReserved21;
+ void* pfnReserved22;
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+ void* pfnReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler ( void );
+void NMI_Handler ( void );
+void HardFault_Handler ( void );
+void SVC_Handler ( void );
+void PendSV_Handler ( void );
+void SysTick_Handler ( void );
+
+/* Peripherals handlers */
+void PM_Handler ( void );
+void SYSCTRL_Handler ( void );
+void WDT_Handler ( void );
+void RTC_Handler ( void );
+void EIC_Handler ( void );
+void NVMCTRL_Handler ( void );
+void DMAC_Handler ( void );
+void USB_Handler ( void );
+void EVSYS_Handler ( void );
+void SERCOM0_Handler ( void );
+void SERCOM1_Handler ( void );
+void SERCOM2_Handler ( void );
+void SERCOM3_Handler ( void );
+void SERCOM4_Handler ( void );
+void SERCOM5_Handler ( void );
+void TCC0_Handler ( void );
+void TCC1_Handler ( void );
+void TCC2_Handler ( void );
+void TC3_Handler ( void );
+void TC4_Handler ( void );
+void TC5_Handler ( void );
+void ADC_Handler ( void );
+void AC_Handler ( void );
+void DAC_Handler ( void );
+void PTC_Handler ( void );
+void I2S_Handler ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN 1
+#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 0 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT 1 /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G17A_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** REGISTERS ACCESS DEFINITIONS FOR SAMD21G17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G17A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** PERIPHERAL ID DEFINITIONS FOR SAMD21G17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G17A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM 1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT 35 /**< \brief Port Module (PORT) */
+#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC 81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/** BASE ADDRESS DEFINITIONS FOR SAMD21G17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G17A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define ADC (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S (0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0 (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1 (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2 (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0 (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4 (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5 (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4 (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5 (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TCC0 (0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1 (0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2 (0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define USB (0x41005000UL) /**< \brief (USB) APB Base Address */
+#define WDT (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
+#define AC_INSTS { AC } /**< \brief (AC) Instances List */
+
+#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */
+#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */
+
+#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */
+#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */
+
+#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
+
+#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
+#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */
+
+#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
+#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */
+
+#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */
+
+#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */
+
+#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */
+#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */
+
+#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
+#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
+
+#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */
+#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */
+
+#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
+#define PM_INSTS { PM } /**< \brief (PM) Instances List */
+
+#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
+#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID 34
+#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */
+#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */
+
+#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
+#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */
+
+#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */
+
+#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */
+#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */
+
+#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */
+#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
+
+#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */
+#define USB_INSTS { USB } /**< \brief (USB) Instances List */
+
+#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
+#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/** PORT DEFINITIONS FOR SAMD21G17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G17A_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21g17a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** MEMORY MAPPING DEFINITIONS FOR SAMD21G17A */
+/* ************************************************************************** */
+
+#define FLASH_SIZE 0x20000UL /* 128 kB */
+#define FLASH_PAGE_SIZE 64
+#define FLASH_NB_OF_PAGES 2048
+#define FLASH_USER_PAGE_SIZE 64
+#define HMCRAMC0_SIZE 0x4000UL /* 16 kB */
+
+#define FLASH_ADDR (0x00000000u) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR (0x20000000u) /**< HMCRAMC0 base address */
+#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */
+#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */
+#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */
+#define PPB_ADDR (0xE0000000u) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE 0x10010006UL
+#define EIC_EXTINT_NUM 16
+#define PORT_GROUPS 2
+
+/* ************************************************************************** */
+/** ELECTRICAL DEFINITIONS FOR SAMD21G17A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21G17A_H */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/samd21g17au.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/samd21g17au.h
new file mode 100644
index 0000000000000000000000000000000000000000..59d150e59b4861b0b6bfdcc0ffff3d7e2faf72d8
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/samd21g17au.h
@@ -0,0 +1,581 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21G17AU
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21G17AU_
+#define _SAMD21G17AU_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21G17AU_definitions SAMD21G17AU definitions
+ * This file defines all structures and symbols for SAMD21G17AU:
+ * - registers and bitfields
+ * - peripheral base address
+ * - peripheral ID
+ * - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#else
+typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
+typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/** CMSIS DEFINITIONS FOR SAMD21G17AU */
+/* ************************************************************************** */
+/** \defgroup SAMD21G17AU_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21G17AU-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21G17AU Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21G17AU System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21G17AU Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21G17AU Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21G17AU External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21G17AU Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21G17AU Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21G17AU Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21G17AU Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21G17AU Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21G17AU Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21G17AU Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21G17AU Serial Communication Interface 3 (SERCOM3) */
+ SERCOM4_IRQn = 13, /**< 13 SAMD21G17AU Serial Communication Interface 4 (SERCOM4) */
+ SERCOM5_IRQn = 14, /**< 14 SAMD21G17AU Serial Communication Interface 5 (SERCOM5) */
+ TCC0_IRQn = 15, /**< 15 SAMD21G17AU Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21G17AU Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21G17AU Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21G17AU Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21G17AU Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21G17AU Basic Timer Counter 5 (TC5) */
+ TC6_IRQn = 21, /**< 21 SAMD21G17AU Basic Timer Counter 6 (TC6) */
+ TC7_IRQn = 22, /**< 22 SAMD21G17AU Basic Timer Counter 7 (TC7) */
+ ADC_IRQn = 23, /**< 23 SAMD21G17AU Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21G17AU Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21G17AU Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21G17AU Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21G17AU Inter-IC Sound Interface (I2S) */
+
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
+ void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
+ void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+ void* pfnReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler ( void );
+void NMI_Handler ( void );
+void HardFault_Handler ( void );
+void SVC_Handler ( void );
+void PendSV_Handler ( void );
+void SysTick_Handler ( void );
+
+/* Peripherals handlers */
+void PM_Handler ( void );
+void SYSCTRL_Handler ( void );
+void WDT_Handler ( void );
+void RTC_Handler ( void );
+void EIC_Handler ( void );
+void NVMCTRL_Handler ( void );
+void DMAC_Handler ( void );
+void USB_Handler ( void );
+void EVSYS_Handler ( void );
+void SERCOM0_Handler ( void );
+void SERCOM1_Handler ( void );
+void SERCOM2_Handler ( void );
+void SERCOM3_Handler ( void );
+void SERCOM4_Handler ( void );
+void SERCOM5_Handler ( void );
+void TCC0_Handler ( void );
+void TCC1_Handler ( void );
+void TCC2_Handler ( void );
+void TC3_Handler ( void );
+void TC4_Handler ( void );
+void TC5_Handler ( void );
+void TC6_Handler ( void );
+void TC7_Handler ( void );
+void ADC_Handler ( void );
+void AC_Handler ( void );
+void DAC_Handler ( void );
+void PTC_Handler ( void );
+void I2S_Handler ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN 1
+#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 0 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT 1 /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G17AU */
+/* ************************************************************************** */
+/** \defgroup SAMD21G17AU_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** REGISTERS ACCESS DEFINITIONS FOR SAMD21G17AU */
+/* ************************************************************************** */
+/** \defgroup SAMD21G17AU_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tc6.h"
+#include "instance/tc7.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** PERIPHERAL ID DEFINITIONS FOR SAMD21G17AU */
+/* ************************************************************************** */
+/** \defgroup SAMD21G17AU_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM 1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT 35 /**< \brief Port Module (PORT) */
+#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_TC6 78 /**< \brief Basic Timer Counter 6 (TC6) */
+#define ID_TC7 79 /**< \brief Basic Timer Counter 7 (TC7) */
+#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC 81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/** BASE ADDRESS DEFINITIONS FOR SAMD21G17AU */
+/* ************************************************************************** */
+/** \defgroup SAMD21G17AU_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define ADC (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S (0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0 (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1 (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2 (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0 (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4 (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5 (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4 (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5 (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC6 (0x42003800UL) /**< \brief (TC6) APB Base Address */
+#define TC7 (0x42003C00UL) /**< \brief (TC7) APB Base Address */
+#define TCC0 (0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1 (0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2 (0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define USB (0x41005000UL) /**< \brief (USB) APB Base Address */
+#define WDT (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
+#define AC_INSTS { AC } /**< \brief (AC) Instances List */
+
+#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */
+#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */
+
+#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */
+#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */
+
+#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
+
+#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
+#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */
+
+#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
+#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */
+
+#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */
+
+#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */
+
+#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */
+#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */
+
+#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
+#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
+
+#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */
+#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */
+
+#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
+#define PM_INSTS { PM } /**< \brief (PM) Instances List */
+
+#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
+#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID 34
+#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */
+#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */
+
+#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
+#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */
+
+#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */
+
+#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC6 ((Tc *)0x42003800UL) /**< \brief (TC6) APB Base Address */
+#define TC7 ((Tc *)0x42003C00UL) /**< \brief (TC7) APB Base Address */
+#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */
+#define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */
+
+#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */
+#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
+
+#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */
+#define USB_INSTS { USB } /**< \brief (USB) Instances List */
+
+#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
+#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/** PORT DEFINITIONS FOR SAMD21G17AU */
+/* ************************************************************************** */
+/** \defgroup SAMD21G17AU_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21g17au.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** MEMORY MAPPING DEFINITIONS FOR SAMD21G17AU */
+/* ************************************************************************** */
+
+#define FLASH_SIZE 0x20000UL /* 128 kB */
+#define FLASH_PAGE_SIZE 64
+#define FLASH_NB_OF_PAGES 2048
+#define FLASH_USER_PAGE_SIZE 64
+#define HMCRAMC0_SIZE 0x4000UL /* 16 kB */
+
+#define FLASH_ADDR (0x00000000u) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR (0x20000000u) /**< HMCRAMC0 base address */
+#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */
+#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */
+#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */
+#define PPB_ADDR (0xE0000000u) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE 0x10010010UL
+#define EIC_EXTINT_NUM 16
+#define PORT_GROUPS 2
+
+/* ************************************************************************** */
+/** ELECTRICAL DEFINITIONS FOR SAMD21G17AU */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21G17AU_H */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/samd21g18a.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/samd21g18a.h
new file mode 100644
index 0000000000000000000000000000000000000000..9017d23c063e009dbc9861b1b1102cafcb51b3d5
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/samd21g18a.h
@@ -0,0 +1,569 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21G18A
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21G18A_
+#define _SAMD21G18A_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21G18A_definitions SAMD21G18A definitions
+ * This file defines all structures and symbols for SAMD21G18A:
+ * - registers and bitfields
+ * - peripheral base address
+ * - peripheral ID
+ * - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#else
+typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
+typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/** CMSIS DEFINITIONS FOR SAMD21G18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G18A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21G18A-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21G18A Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21G18A System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21G18A Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21G18A Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21G18A External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21G18A Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21G18A Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21G18A Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21G18A Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21G18A Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21G18A Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21G18A Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21G18A Serial Communication Interface 3 (SERCOM3) */
+ SERCOM4_IRQn = 13, /**< 13 SAMD21G18A Serial Communication Interface 4 (SERCOM4) */
+ SERCOM5_IRQn = 14, /**< 14 SAMD21G18A Serial Communication Interface 5 (SERCOM5) */
+ TCC0_IRQn = 15, /**< 15 SAMD21G18A Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21G18A Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21G18A Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21G18A Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21G18A Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21G18A Basic Timer Counter 5 (TC5) */
+ ADC_IRQn = 23, /**< 23 SAMD21G18A Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21G18A Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21G18A Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21G18A Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21G18A Inter-IC Sound Interface (I2S) */
+
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
+ void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnReserved21;
+ void* pfnReserved22;
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+ void* pfnReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler ( void );
+void NMI_Handler ( void );
+void HardFault_Handler ( void );
+void SVC_Handler ( void );
+void PendSV_Handler ( void );
+void SysTick_Handler ( void );
+
+/* Peripherals handlers */
+void PM_Handler ( void );
+void SYSCTRL_Handler ( void );
+void WDT_Handler ( void );
+void RTC_Handler ( void );
+void EIC_Handler ( void );
+void NVMCTRL_Handler ( void );
+void DMAC_Handler ( void );
+void USB_Handler ( void );
+void EVSYS_Handler ( void );
+void SERCOM0_Handler ( void );
+void SERCOM1_Handler ( void );
+void SERCOM2_Handler ( void );
+void SERCOM3_Handler ( void );
+void SERCOM4_Handler ( void );
+void SERCOM5_Handler ( void );
+void TCC0_Handler ( void );
+void TCC1_Handler ( void );
+void TCC2_Handler ( void );
+void TC3_Handler ( void );
+void TC4_Handler ( void );
+void TC5_Handler ( void );
+void ADC_Handler ( void );
+void AC_Handler ( void );
+void DAC_Handler ( void );
+void PTC_Handler ( void );
+void I2S_Handler ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN 1
+#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 0 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT 1 /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G18A_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** REGISTERS ACCESS DEFINITIONS FOR SAMD21G18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G18A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** PERIPHERAL ID DEFINITIONS FOR SAMD21G18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G18A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM 1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT 35 /**< \brief Port Module (PORT) */
+#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC 81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/** BASE ADDRESS DEFINITIONS FOR SAMD21G18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G18A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define ADC (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S (0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0 (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1 (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2 (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0 (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4 (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5 (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4 (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5 (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TCC0 (0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1 (0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2 (0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define USB (0x41005000UL) /**< \brief (USB) APB Base Address */
+#define WDT (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
+#define AC_INSTS { AC } /**< \brief (AC) Instances List */
+
+#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */
+#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */
+
+#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */
+#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */
+
+#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
+
+#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
+#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */
+
+#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
+#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */
+
+#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */
+
+#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */
+
+#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */
+#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */
+
+#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
+#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
+
+#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */
+#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */
+
+#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
+#define PM_INSTS { PM } /**< \brief (PM) Instances List */
+
+#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
+#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID 34
+#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */
+#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */
+
+#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
+#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */
+
+#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */
+
+#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */
+#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */
+
+#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */
+#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
+
+#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */
+#define USB_INSTS { USB } /**< \brief (USB) Instances List */
+
+#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
+#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/** PORT DEFINITIONS FOR SAMD21G18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21G18A_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21g18a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** MEMORY MAPPING DEFINITIONS FOR SAMD21G18A */
+/* ************************************************************************** */
+
+#define FLASH_SIZE 0x40000UL /* 256 kB */
+#define FLASH_PAGE_SIZE 64
+#define FLASH_NB_OF_PAGES 4096
+#define FLASH_USER_PAGE_SIZE 64
+#define HMCRAMC0_SIZE 0x8000UL /* 32 kB */
+
+#define FLASH_ADDR (0x00000000u) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR (0x20000000u) /**< HMCRAMC0 base address */
+#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */
+#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */
+#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */
+#define PPB_ADDR (0xE0000000u) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE 0x10010005UL
+#define EIC_EXTINT_NUM 16
+#define PORT_GROUPS 2
+
+/* ************************************************************************** */
+/** ELECTRICAL DEFINITIONS FOR SAMD21G18A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21G18A_H */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/samd21g18au.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/samd21g18au.h
new file mode 100644
index 0000000000000000000000000000000000000000..1e6769b8579f6fc0278c3a5367709c847ca0754e
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/samd21g18au.h
@@ -0,0 +1,581 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21G18AU
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21G18AU_
+#define _SAMD21G18AU_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21G18AU_definitions SAMD21G18AU definitions
+ * This file defines all structures and symbols for SAMD21G18AU:
+ * - registers and bitfields
+ * - peripheral base address
+ * - peripheral ID
+ * - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#else
+typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
+typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/** CMSIS DEFINITIONS FOR SAMD21G18AU */
+/* ************************************************************************** */
+/** \defgroup SAMD21G18AU_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21G18AU-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21G18AU Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21G18AU System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21G18AU Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21G18AU Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21G18AU External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21G18AU Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21G18AU Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21G18AU Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21G18AU Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21G18AU Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21G18AU Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21G18AU Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21G18AU Serial Communication Interface 3 (SERCOM3) */
+ SERCOM4_IRQn = 13, /**< 13 SAMD21G18AU Serial Communication Interface 4 (SERCOM4) */
+ SERCOM5_IRQn = 14, /**< 14 SAMD21G18AU Serial Communication Interface 5 (SERCOM5) */
+ TCC0_IRQn = 15, /**< 15 SAMD21G18AU Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21G18AU Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21G18AU Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21G18AU Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21G18AU Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21G18AU Basic Timer Counter 5 (TC5) */
+ TC6_IRQn = 21, /**< 21 SAMD21G18AU Basic Timer Counter 6 (TC6) */
+ TC7_IRQn = 22, /**< 22 SAMD21G18AU Basic Timer Counter 7 (TC7) */
+ ADC_IRQn = 23, /**< 23 SAMD21G18AU Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21G18AU Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21G18AU Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21G18AU Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21G18AU Inter-IC Sound Interface (I2S) */
+
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
+ void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
+ void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+ void* pfnReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler ( void );
+void NMI_Handler ( void );
+void HardFault_Handler ( void );
+void SVC_Handler ( void );
+void PendSV_Handler ( void );
+void SysTick_Handler ( void );
+
+/* Peripherals handlers */
+void PM_Handler ( void );
+void SYSCTRL_Handler ( void );
+void WDT_Handler ( void );
+void RTC_Handler ( void );
+void EIC_Handler ( void );
+void NVMCTRL_Handler ( void );
+void DMAC_Handler ( void );
+void USB_Handler ( void );
+void EVSYS_Handler ( void );
+void SERCOM0_Handler ( void );
+void SERCOM1_Handler ( void );
+void SERCOM2_Handler ( void );
+void SERCOM3_Handler ( void );
+void SERCOM4_Handler ( void );
+void SERCOM5_Handler ( void );
+void TCC0_Handler ( void );
+void TCC1_Handler ( void );
+void TCC2_Handler ( void );
+void TC3_Handler ( void );
+void TC4_Handler ( void );
+void TC5_Handler ( void );
+void TC6_Handler ( void );
+void TC7_Handler ( void );
+void ADC_Handler ( void );
+void AC_Handler ( void );
+void DAC_Handler ( void );
+void PTC_Handler ( void );
+void I2S_Handler ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN 1
+#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 0 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT 1 /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G18AU */
+/* ************************************************************************** */
+/** \defgroup SAMD21G18AU_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** REGISTERS ACCESS DEFINITIONS FOR SAMD21G18AU */
+/* ************************************************************************** */
+/** \defgroup SAMD21G18AU_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tc6.h"
+#include "instance/tc7.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** PERIPHERAL ID DEFINITIONS FOR SAMD21G18AU */
+/* ************************************************************************** */
+/** \defgroup SAMD21G18AU_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM 1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT 35 /**< \brief Port Module (PORT) */
+#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_TC6 78 /**< \brief Basic Timer Counter 6 (TC6) */
+#define ID_TC7 79 /**< \brief Basic Timer Counter 7 (TC7) */
+#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC 81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/** BASE ADDRESS DEFINITIONS FOR SAMD21G18AU */
+/* ************************************************************************** */
+/** \defgroup SAMD21G18AU_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define ADC (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S (0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0 (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1 (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2 (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0 (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4 (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5 (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4 (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5 (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC6 (0x42003800UL) /**< \brief (TC6) APB Base Address */
+#define TC7 (0x42003C00UL) /**< \brief (TC7) APB Base Address */
+#define TCC0 (0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1 (0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2 (0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define USB (0x41005000UL) /**< \brief (USB) APB Base Address */
+#define WDT (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
+#define AC_INSTS { AC } /**< \brief (AC) Instances List */
+
+#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */
+#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */
+
+#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */
+#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */
+
+#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
+
+#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
+#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */
+
+#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
+#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */
+
+#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */
+
+#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */
+
+#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */
+#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */
+
+#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
+#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
+
+#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */
+#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */
+
+#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
+#define PM_INSTS { PM } /**< \brief (PM) Instances List */
+
+#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
+#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID 34
+#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */
+#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */
+
+#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
+#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */
+
+#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */
+
+#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC6 ((Tc *)0x42003800UL) /**< \brief (TC6) APB Base Address */
+#define TC7 ((Tc *)0x42003C00UL) /**< \brief (TC7) APB Base Address */
+#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */
+#define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */
+
+#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */
+#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
+
+#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */
+#define USB_INSTS { USB } /**< \brief (USB) Instances List */
+
+#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
+#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/** PORT DEFINITIONS FOR SAMD21G18AU */
+/* ************************************************************************** */
+/** \defgroup SAMD21G18AU_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21g18au.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** MEMORY MAPPING DEFINITIONS FOR SAMD21G18AU */
+/* ************************************************************************** */
+
+#define FLASH_SIZE 0x40000UL /* 256 kB */
+#define FLASH_PAGE_SIZE 64
+#define FLASH_NB_OF_PAGES 4096
+#define FLASH_USER_PAGE_SIZE 64
+#define HMCRAMC0_SIZE 0x8000UL /* 32 kB */
+
+#define FLASH_ADDR (0x00000000u) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR (0x20000000u) /**< HMCRAMC0 base address */
+#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */
+#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */
+#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */
+#define PPB_ADDR (0xE0000000u) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE 0x1001000FUL
+#define EIC_EXTINT_NUM 16
+#define PORT_GROUPS 2
+
+/* ************************************************************************** */
+/** ELECTRICAL DEFINITIONS FOR SAMD21G18AU */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21G18AU_H */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/samd21j15a.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/samd21j15a.h
new file mode 100644
index 0000000000000000000000000000000000000000..5d2ed5059a0c2665a51865a6131bc8f0fbe6afdd
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/samd21j15a.h
@@ -0,0 +1,581 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21J15A
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21J15A_
+#define _SAMD21J15A_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21J15A_definitions SAMD21J15A definitions
+ * This file defines all structures and symbols for SAMD21J15A:
+ * - registers and bitfields
+ * - peripheral base address
+ * - peripheral ID
+ * - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#else
+typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
+typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/** CMSIS DEFINITIONS FOR SAMD21J15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J15A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21J15A-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21J15A Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21J15A System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21J15A Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21J15A Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21J15A External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21J15A Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21J15A Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21J15A Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21J15A Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21J15A Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21J15A Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21J15A Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21J15A Serial Communication Interface 3 (SERCOM3) */
+ SERCOM4_IRQn = 13, /**< 13 SAMD21J15A Serial Communication Interface 4 (SERCOM4) */
+ SERCOM5_IRQn = 14, /**< 14 SAMD21J15A Serial Communication Interface 5 (SERCOM5) */
+ TCC0_IRQn = 15, /**< 15 SAMD21J15A Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21J15A Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21J15A Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21J15A Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21J15A Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21J15A Basic Timer Counter 5 (TC5) */
+ TC6_IRQn = 21, /**< 21 SAMD21J15A Basic Timer Counter 6 (TC6) */
+ TC7_IRQn = 22, /**< 22 SAMD21J15A Basic Timer Counter 7 (TC7) */
+ ADC_IRQn = 23, /**< 23 SAMD21J15A Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21J15A Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21J15A Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21J15A Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21J15A Inter-IC Sound Interface (I2S) */
+
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
+ void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
+ void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+ void* pfnReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler ( void );
+void NMI_Handler ( void );
+void HardFault_Handler ( void );
+void SVC_Handler ( void );
+void PendSV_Handler ( void );
+void SysTick_Handler ( void );
+
+/* Peripherals handlers */
+void PM_Handler ( void );
+void SYSCTRL_Handler ( void );
+void WDT_Handler ( void );
+void RTC_Handler ( void );
+void EIC_Handler ( void );
+void NVMCTRL_Handler ( void );
+void DMAC_Handler ( void );
+void USB_Handler ( void );
+void EVSYS_Handler ( void );
+void SERCOM0_Handler ( void );
+void SERCOM1_Handler ( void );
+void SERCOM2_Handler ( void );
+void SERCOM3_Handler ( void );
+void SERCOM4_Handler ( void );
+void SERCOM5_Handler ( void );
+void TCC0_Handler ( void );
+void TCC1_Handler ( void );
+void TCC2_Handler ( void );
+void TC3_Handler ( void );
+void TC4_Handler ( void );
+void TC5_Handler ( void );
+void TC6_Handler ( void );
+void TC7_Handler ( void );
+void ADC_Handler ( void );
+void AC_Handler ( void );
+void DAC_Handler ( void );
+void PTC_Handler ( void );
+void I2S_Handler ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN 1
+#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 0 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT 1 /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21J15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J15A_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** REGISTERS ACCESS DEFINITIONS FOR SAMD21J15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J15A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tc6.h"
+#include "instance/tc7.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** PERIPHERAL ID DEFINITIONS FOR SAMD21J15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J15A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM 1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT 35 /**< \brief Port Module (PORT) */
+#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_TC6 78 /**< \brief Basic Timer Counter 6 (TC6) */
+#define ID_TC7 79 /**< \brief Basic Timer Counter 7 (TC7) */
+#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC 81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/** BASE ADDRESS DEFINITIONS FOR SAMD21J15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J15A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define ADC (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S (0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0 (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1 (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2 (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0 (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4 (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5 (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4 (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5 (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC6 (0x42003800UL) /**< \brief (TC6) APB Base Address */
+#define TC7 (0x42003C00UL) /**< \brief (TC7) APB Base Address */
+#define TCC0 (0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1 (0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2 (0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define USB (0x41005000UL) /**< \brief (USB) APB Base Address */
+#define WDT (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
+#define AC_INSTS { AC } /**< \brief (AC) Instances List */
+
+#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */
+#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */
+
+#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */
+#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */
+
+#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
+
+#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
+#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */
+
+#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
+#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */
+
+#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */
+
+#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */
+
+#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */
+#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */
+
+#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
+#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
+
+#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */
+#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */
+
+#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
+#define PM_INSTS { PM } /**< \brief (PM) Instances List */
+
+#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
+#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID 34
+#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */
+#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */
+
+#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
+#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */
+
+#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */
+
+#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC6 ((Tc *)0x42003800UL) /**< \brief (TC6) APB Base Address */
+#define TC7 ((Tc *)0x42003C00UL) /**< \brief (TC7) APB Base Address */
+#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */
+#define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */
+
+#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */
+#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
+
+#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */
+#define USB_INSTS { USB } /**< \brief (USB) Instances List */
+
+#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
+#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/** PORT DEFINITIONS FOR SAMD21J15A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J15A_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21j15a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** MEMORY MAPPING DEFINITIONS FOR SAMD21J15A */
+/* ************************************************************************** */
+
+#define FLASH_SIZE 0x8000UL /* 32 kB */
+#define FLASH_PAGE_SIZE 64
+#define FLASH_NB_OF_PAGES 512
+#define FLASH_USER_PAGE_SIZE 64
+#define HMCRAMC0_SIZE 0x1000UL /* 4 kB */
+
+#define FLASH_ADDR (0x00000000u) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR (0x20000000u) /**< HMCRAMC0 base address */
+#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */
+#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */
+#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */
+#define PPB_ADDR (0xE0000000u) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE 0x10010003UL
+#define EIC_EXTINT_NUM 16
+#define PORT_GROUPS 2
+
+/* ************************************************************************** */
+/** ELECTRICAL DEFINITIONS FOR SAMD21J15A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21J15A_H */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/samd21j16a.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/samd21j16a.h
new file mode 100644
index 0000000000000000000000000000000000000000..b48a389469e5151e3be7b3601cb97364fcee50e4
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/samd21j16a.h
@@ -0,0 +1,581 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21J16A
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21J16A_
+#define _SAMD21J16A_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21J16A_definitions SAMD21J16A definitions
+ * This file defines all structures and symbols for SAMD21J16A:
+ * - registers and bitfields
+ * - peripheral base address
+ * - peripheral ID
+ * - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#else
+typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
+typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/** CMSIS DEFINITIONS FOR SAMD21J16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J16A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21J16A-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21J16A Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21J16A System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21J16A Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21J16A Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21J16A External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21J16A Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21J16A Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21J16A Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21J16A Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21J16A Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21J16A Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21J16A Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21J16A Serial Communication Interface 3 (SERCOM3) */
+ SERCOM4_IRQn = 13, /**< 13 SAMD21J16A Serial Communication Interface 4 (SERCOM4) */
+ SERCOM5_IRQn = 14, /**< 14 SAMD21J16A Serial Communication Interface 5 (SERCOM5) */
+ TCC0_IRQn = 15, /**< 15 SAMD21J16A Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21J16A Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21J16A Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21J16A Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21J16A Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21J16A Basic Timer Counter 5 (TC5) */
+ TC6_IRQn = 21, /**< 21 SAMD21J16A Basic Timer Counter 6 (TC6) */
+ TC7_IRQn = 22, /**< 22 SAMD21J16A Basic Timer Counter 7 (TC7) */
+ ADC_IRQn = 23, /**< 23 SAMD21J16A Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21J16A Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21J16A Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21J16A Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21J16A Inter-IC Sound Interface (I2S) */
+
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
+ void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
+ void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+ void* pfnReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler ( void );
+void NMI_Handler ( void );
+void HardFault_Handler ( void );
+void SVC_Handler ( void );
+void PendSV_Handler ( void );
+void SysTick_Handler ( void );
+
+/* Peripherals handlers */
+void PM_Handler ( void );
+void SYSCTRL_Handler ( void );
+void WDT_Handler ( void );
+void RTC_Handler ( void );
+void EIC_Handler ( void );
+void NVMCTRL_Handler ( void );
+void DMAC_Handler ( void );
+void USB_Handler ( void );
+void EVSYS_Handler ( void );
+void SERCOM0_Handler ( void );
+void SERCOM1_Handler ( void );
+void SERCOM2_Handler ( void );
+void SERCOM3_Handler ( void );
+void SERCOM4_Handler ( void );
+void SERCOM5_Handler ( void );
+void TCC0_Handler ( void );
+void TCC1_Handler ( void );
+void TCC2_Handler ( void );
+void TC3_Handler ( void );
+void TC4_Handler ( void );
+void TC5_Handler ( void );
+void TC6_Handler ( void );
+void TC7_Handler ( void );
+void ADC_Handler ( void );
+void AC_Handler ( void );
+void DAC_Handler ( void );
+void PTC_Handler ( void );
+void I2S_Handler ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN 1
+#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 0 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT 1 /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21J16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J16A_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** REGISTERS ACCESS DEFINITIONS FOR SAMD21J16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J16A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tc6.h"
+#include "instance/tc7.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** PERIPHERAL ID DEFINITIONS FOR SAMD21J16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J16A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM 1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT 35 /**< \brief Port Module (PORT) */
+#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_TC6 78 /**< \brief Basic Timer Counter 6 (TC6) */
+#define ID_TC7 79 /**< \brief Basic Timer Counter 7 (TC7) */
+#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC 81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/** BASE ADDRESS DEFINITIONS FOR SAMD21J16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J16A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define ADC (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S (0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0 (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1 (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2 (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0 (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4 (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5 (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4 (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5 (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC6 (0x42003800UL) /**< \brief (TC6) APB Base Address */
+#define TC7 (0x42003C00UL) /**< \brief (TC7) APB Base Address */
+#define TCC0 (0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1 (0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2 (0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define USB (0x41005000UL) /**< \brief (USB) APB Base Address */
+#define WDT (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
+#define AC_INSTS { AC } /**< \brief (AC) Instances List */
+
+#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */
+#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */
+
+#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */
+#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */
+
+#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
+
+#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
+#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */
+
+#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
+#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */
+
+#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */
+
+#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */
+
+#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */
+#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */
+
+#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
+#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
+
+#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */
+#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */
+
+#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
+#define PM_INSTS { PM } /**< \brief (PM) Instances List */
+
+#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
+#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID 34
+#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */
+#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */
+
+#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
+#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */
+
+#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */
+
+#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC6 ((Tc *)0x42003800UL) /**< \brief (TC6) APB Base Address */
+#define TC7 ((Tc *)0x42003C00UL) /**< \brief (TC7) APB Base Address */
+#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */
+#define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */
+
+#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */
+#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
+
+#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */
+#define USB_INSTS { USB } /**< \brief (USB) Instances List */
+
+#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
+#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/** PORT DEFINITIONS FOR SAMD21J16A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J16A_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21j16a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** MEMORY MAPPING DEFINITIONS FOR SAMD21J16A */
+/* ************************************************************************** */
+
+#define FLASH_SIZE 0x10000UL /* 64 kB */
+#define FLASH_PAGE_SIZE 64
+#define FLASH_NB_OF_PAGES 1024
+#define FLASH_USER_PAGE_SIZE 64
+#define HMCRAMC0_SIZE 0x2000UL /* 8 kB */
+
+#define FLASH_ADDR (0x00000000u) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR (0x20000000u) /**< HMCRAMC0 base address */
+#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */
+#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */
+#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */
+#define PPB_ADDR (0xE0000000u) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE 0x10010002UL
+#define EIC_EXTINT_NUM 16
+#define PORT_GROUPS 2
+
+/* ************************************************************************** */
+/** ELECTRICAL DEFINITIONS FOR SAMD21J16A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21J16A_H */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/samd21j17a.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/samd21j17a.h
new file mode 100644
index 0000000000000000000000000000000000000000..e39ff1f25d9e36d97b6804e3b768fb1dc156d4be
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/samd21j17a.h
@@ -0,0 +1,581 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21J17A
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21J17A_
+#define _SAMD21J17A_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21J17A_definitions SAMD21J17A definitions
+ * This file defines all structures and symbols for SAMD21J17A:
+ * - registers and bitfields
+ * - peripheral base address
+ * - peripheral ID
+ * - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#else
+typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
+typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/** CMSIS DEFINITIONS FOR SAMD21J17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J17A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21J17A-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21J17A Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21J17A System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21J17A Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21J17A Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21J17A External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21J17A Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21J17A Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21J17A Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21J17A Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21J17A Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21J17A Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21J17A Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21J17A Serial Communication Interface 3 (SERCOM3) */
+ SERCOM4_IRQn = 13, /**< 13 SAMD21J17A Serial Communication Interface 4 (SERCOM4) */
+ SERCOM5_IRQn = 14, /**< 14 SAMD21J17A Serial Communication Interface 5 (SERCOM5) */
+ TCC0_IRQn = 15, /**< 15 SAMD21J17A Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21J17A Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21J17A Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21J17A Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21J17A Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21J17A Basic Timer Counter 5 (TC5) */
+ TC6_IRQn = 21, /**< 21 SAMD21J17A Basic Timer Counter 6 (TC6) */
+ TC7_IRQn = 22, /**< 22 SAMD21J17A Basic Timer Counter 7 (TC7) */
+ ADC_IRQn = 23, /**< 23 SAMD21J17A Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21J17A Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21J17A Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21J17A Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21J17A Inter-IC Sound Interface (I2S) */
+
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
+ void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
+ void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+ void* pfnReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler ( void );
+void NMI_Handler ( void );
+void HardFault_Handler ( void );
+void SVC_Handler ( void );
+void PendSV_Handler ( void );
+void SysTick_Handler ( void );
+
+/* Peripherals handlers */
+void PM_Handler ( void );
+void SYSCTRL_Handler ( void );
+void WDT_Handler ( void );
+void RTC_Handler ( void );
+void EIC_Handler ( void );
+void NVMCTRL_Handler ( void );
+void DMAC_Handler ( void );
+void USB_Handler ( void );
+void EVSYS_Handler ( void );
+void SERCOM0_Handler ( void );
+void SERCOM1_Handler ( void );
+void SERCOM2_Handler ( void );
+void SERCOM3_Handler ( void );
+void SERCOM4_Handler ( void );
+void SERCOM5_Handler ( void );
+void TCC0_Handler ( void );
+void TCC1_Handler ( void );
+void TCC2_Handler ( void );
+void TC3_Handler ( void );
+void TC4_Handler ( void );
+void TC5_Handler ( void );
+void TC6_Handler ( void );
+void TC7_Handler ( void );
+void ADC_Handler ( void );
+void AC_Handler ( void );
+void DAC_Handler ( void );
+void PTC_Handler ( void );
+void I2S_Handler ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN 1
+#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 0 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT 1 /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21J17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J17A_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** REGISTERS ACCESS DEFINITIONS FOR SAMD21J17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J17A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tc6.h"
+#include "instance/tc7.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** PERIPHERAL ID DEFINITIONS FOR SAMD21J17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J17A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM 1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT 35 /**< \brief Port Module (PORT) */
+#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_TC6 78 /**< \brief Basic Timer Counter 6 (TC6) */
+#define ID_TC7 79 /**< \brief Basic Timer Counter 7 (TC7) */
+#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC 81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/** BASE ADDRESS DEFINITIONS FOR SAMD21J17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J17A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define ADC (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S (0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0 (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1 (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2 (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0 (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4 (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5 (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4 (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5 (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC6 (0x42003800UL) /**< \brief (TC6) APB Base Address */
+#define TC7 (0x42003C00UL) /**< \brief (TC7) APB Base Address */
+#define TCC0 (0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1 (0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2 (0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define USB (0x41005000UL) /**< \brief (USB) APB Base Address */
+#define WDT (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
+#define AC_INSTS { AC } /**< \brief (AC) Instances List */
+
+#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */
+#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */
+
+#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */
+#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */
+
+#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
+
+#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
+#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */
+
+#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
+#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */
+
+#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */
+
+#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */
+
+#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */
+#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */
+
+#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
+#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
+
+#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */
+#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */
+
+#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
+#define PM_INSTS { PM } /**< \brief (PM) Instances List */
+
+#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
+#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID 34
+#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */
+#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */
+
+#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
+#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */
+
+#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */
+
+#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC6 ((Tc *)0x42003800UL) /**< \brief (TC6) APB Base Address */
+#define TC7 ((Tc *)0x42003C00UL) /**< \brief (TC7) APB Base Address */
+#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */
+#define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */
+
+#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */
+#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
+
+#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */
+#define USB_INSTS { USB } /**< \brief (USB) Instances List */
+
+#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
+#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/** PORT DEFINITIONS FOR SAMD21J17A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J17A_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21j17a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** MEMORY MAPPING DEFINITIONS FOR SAMD21J17A */
+/* ************************************************************************** */
+
+#define FLASH_SIZE 0x20000UL /* 128 kB */
+#define FLASH_PAGE_SIZE 64
+#define FLASH_NB_OF_PAGES 2048
+#define FLASH_USER_PAGE_SIZE 64
+#define HMCRAMC0_SIZE 0x4000UL /* 16 kB */
+
+#define FLASH_ADDR (0x00000000u) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR (0x20000000u) /**< HMCRAMC0 base address */
+#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */
+#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */
+#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */
+#define PPB_ADDR (0xE0000000u) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE 0x10010001UL
+#define EIC_EXTINT_NUM 16
+#define PORT_GROUPS 2
+
+/* ************************************************************************** */
+/** ELECTRICAL DEFINITIONS FOR SAMD21J17A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21J17A_H */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/samd21j18a.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/samd21j18a.h
new file mode 100644
index 0000000000000000000000000000000000000000..368c00d013c3e1d967f7fd25d1f3c6ab1038e19b
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/samd21j18a.h
@@ -0,0 +1,581 @@
+/**
+ * \file
+ *
+ * \brief Header file for SAMD21J18A
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SAMD21J18A_
+#define _SAMD21J18A_
+
+/**
+ * \ingroup SAMD21_definitions
+ * \addtogroup SAMD21J18A_definitions SAMD21J18A definitions
+ * This file defines all structures and symbols for SAMD21J18A:
+ * - registers and bitfields
+ * - peripheral base address
+ * - peripheral ID
+ * - PIO definitions
+*/
+/*@{*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
+#include <stdint.h>
+#ifndef __cplusplus
+typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#else
+typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
+typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
+typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
+#endif
+typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
+typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
+typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
+typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
+typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
+#define CAST(type, value) ((type *)(value))
+#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
+#else
+#define CAST(type, value) (value)
+#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
+#endif
+
+/* ************************************************************************** */
+/** CMSIS DEFINITIONS FOR SAMD21J18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J18A_cmsis CMSIS Definitions */
+/*@{*/
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+ /****** Cortex-M0+ Processor Exceptions Numbers ******************************/
+ NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
+ PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
+ /****** SAMD21J18A-specific Interrupt Numbers ***********************/
+ PM_IRQn = 0, /**< 0 SAMD21J18A Power Manager (PM) */
+ SYSCTRL_IRQn = 1, /**< 1 SAMD21J18A System Control (SYSCTRL) */
+ WDT_IRQn = 2, /**< 2 SAMD21J18A Watchdog Timer (WDT) */
+ RTC_IRQn = 3, /**< 3 SAMD21J18A Real-Time Counter (RTC) */
+ EIC_IRQn = 4, /**< 4 SAMD21J18A External Interrupt Controller (EIC) */
+ NVMCTRL_IRQn = 5, /**< 5 SAMD21J18A Non-Volatile Memory Controller (NVMCTRL) */
+ DMAC_IRQn = 6, /**< 6 SAMD21J18A Direct Memory Access Controller (DMAC) */
+ USB_IRQn = 7, /**< 7 SAMD21J18A Universal Serial Bus (USB) */
+ EVSYS_IRQn = 8, /**< 8 SAMD21J18A Event System Interface (EVSYS) */
+ SERCOM0_IRQn = 9, /**< 9 SAMD21J18A Serial Communication Interface 0 (SERCOM0) */
+ SERCOM1_IRQn = 10, /**< 10 SAMD21J18A Serial Communication Interface 1 (SERCOM1) */
+ SERCOM2_IRQn = 11, /**< 11 SAMD21J18A Serial Communication Interface 2 (SERCOM2) */
+ SERCOM3_IRQn = 12, /**< 12 SAMD21J18A Serial Communication Interface 3 (SERCOM3) */
+ SERCOM4_IRQn = 13, /**< 13 SAMD21J18A Serial Communication Interface 4 (SERCOM4) */
+ SERCOM5_IRQn = 14, /**< 14 SAMD21J18A Serial Communication Interface 5 (SERCOM5) */
+ TCC0_IRQn = 15, /**< 15 SAMD21J18A Timer Counter Control 0 (TCC0) */
+ TCC1_IRQn = 16, /**< 16 SAMD21J18A Timer Counter Control 1 (TCC1) */
+ TCC2_IRQn = 17, /**< 17 SAMD21J18A Timer Counter Control 2 (TCC2) */
+ TC3_IRQn = 18, /**< 18 SAMD21J18A Basic Timer Counter 3 (TC3) */
+ TC4_IRQn = 19, /**< 19 SAMD21J18A Basic Timer Counter 4 (TC4) */
+ TC5_IRQn = 20, /**< 20 SAMD21J18A Basic Timer Counter 5 (TC5) */
+ TC6_IRQn = 21, /**< 21 SAMD21J18A Basic Timer Counter 6 (TC6) */
+ TC7_IRQn = 22, /**< 22 SAMD21J18A Basic Timer Counter 7 (TC7) */
+ ADC_IRQn = 23, /**< 23 SAMD21J18A Analog Digital Converter (ADC) */
+ AC_IRQn = 24, /**< 24 SAMD21J18A Analog Comparators (AC) */
+ DAC_IRQn = 25, /**< 25 SAMD21J18A Digital Analog Converter (DAC) */
+ PTC_IRQn = 26, /**< 26 SAMD21J18A Peripheral Touch Controller (PTC) */
+ I2S_IRQn = 27, /**< 27 SAMD21J18A Inter-IC Sound Interface (I2S) */
+
+ PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
+} IRQn_Type;
+
+typedef struct _DeviceVectors
+{
+ /* Stack pointer */
+ void* pvStack;
+
+ /* Cortex-M handlers */
+ void* pfnReset_Handler;
+ void* pfnNMI_Handler;
+ void* pfnHardFault_Handler;
+ void* pfnReservedM12;
+ void* pfnReservedM11;
+ void* pfnReservedM10;
+ void* pfnReservedM9;
+ void* pfnReservedM8;
+ void* pfnReservedM7;
+ void* pfnReservedM6;
+ void* pfnSVC_Handler;
+ void* pfnReservedM4;
+ void* pfnReservedM3;
+ void* pfnPendSV_Handler;
+ void* pfnSysTick_Handler;
+
+ /* Peripheral handlers */
+ void* pfnPM_Handler; /* 0 Power Manager */
+ void* pfnSYSCTRL_Handler; /* 1 System Control */
+ void* pfnWDT_Handler; /* 2 Watchdog Timer */
+ void* pfnRTC_Handler; /* 3 Real-Time Counter */
+ void* pfnEIC_Handler; /* 4 External Interrupt Controller */
+ void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
+ void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
+ void* pfnUSB_Handler; /* 7 Universal Serial Bus */
+ void* pfnEVSYS_Handler; /* 8 Event System Interface */
+ void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
+ void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
+ void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
+ void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
+ void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
+ void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
+ void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
+ void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
+ void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
+ void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
+ void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
+ void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
+ void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
+ void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
+ void* pfnADC_Handler; /* 23 Analog Digital Converter */
+ void* pfnAC_Handler; /* 24 Analog Comparators */
+ void* pfnDAC_Handler; /* 25 Digital Analog Converter */
+ void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
+ void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
+ void* pfnReserved28;
+} DeviceVectors;
+
+/* Cortex-M0+ processor handlers */
+void Reset_Handler ( void );
+void NMI_Handler ( void );
+void HardFault_Handler ( void );
+void SVC_Handler ( void );
+void PendSV_Handler ( void );
+void SysTick_Handler ( void );
+
+/* Peripherals handlers */
+void PM_Handler ( void );
+void SYSCTRL_Handler ( void );
+void WDT_Handler ( void );
+void RTC_Handler ( void );
+void EIC_Handler ( void );
+void NVMCTRL_Handler ( void );
+void DMAC_Handler ( void );
+void USB_Handler ( void );
+void EVSYS_Handler ( void );
+void SERCOM0_Handler ( void );
+void SERCOM1_Handler ( void );
+void SERCOM2_Handler ( void );
+void SERCOM3_Handler ( void );
+void SERCOM4_Handler ( void );
+void SERCOM5_Handler ( void );
+void TCC0_Handler ( void );
+void TCC1_Handler ( void );
+void TCC2_Handler ( void );
+void TC3_Handler ( void );
+void TC4_Handler ( void );
+void TC5_Handler ( void );
+void TC6_Handler ( void );
+void TC7_Handler ( void );
+void ADC_Handler ( void );
+void AC_Handler ( void );
+void DAC_Handler ( void );
+void PTC_Handler ( void );
+void I2S_Handler ( void );
+
+/*
+ * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
+ */
+
+#define LITTLE_ENDIAN 1
+#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 0 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
+#define __VTOR_PRESENT 1 /*!< VTOR present or not */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/**
+ * \brief CMSIS includes
+ */
+
+#include <core_cm0plus.h>
+#if !defined DONT_USE_CMSIS_INIT
+#include "system_samd21.h"
+#endif /* DONT_USE_CMSIS_INIT */
+
+/*@}*/
+
+/* ************************************************************************** */
+/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21J18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J18A_api Peripheral Software API */
+/*@{*/
+
+#include "component/ac.h"
+#include "component/adc.h"
+#include "component/dac.h"
+#include "component/dmac.h"
+#include "component/dsu.h"
+#include "component/eic.h"
+#include "component/evsys.h"
+#include "component/gclk.h"
+#include "component/hmatrixb.h"
+#include "component/i2s.h"
+#include "component/mtb.h"
+#include "component/nvmctrl.h"
+#include "component/pac.h"
+#include "component/pm.h"
+#include "component/port.h"
+#include "component/rtc.h"
+#include "component/sercom.h"
+#include "component/sysctrl.h"
+#include "component/tc.h"
+#include "component/tcc.h"
+#include "component/usb.h"
+#include "component/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** REGISTERS ACCESS DEFINITIONS FOR SAMD21J18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J18A_reg Registers Access Definitions */
+/*@{*/
+
+#include "instance/ac.h"
+#include "instance/adc.h"
+#include "instance/dac.h"
+#include "instance/dmac.h"
+#include "instance/dsu.h"
+#include "instance/eic.h"
+#include "instance/evsys.h"
+#include "instance/gclk.h"
+#include "instance/sbmatrix.h"
+#include "instance/i2s.h"
+#include "instance/mtb.h"
+#include "instance/nvmctrl.h"
+#include "instance/pac0.h"
+#include "instance/pac1.h"
+#include "instance/pac2.h"
+#include "instance/pm.h"
+#include "instance/port.h"
+#include "instance/rtc.h"
+#include "instance/sercom0.h"
+#include "instance/sercom1.h"
+#include "instance/sercom2.h"
+#include "instance/sercom3.h"
+#include "instance/sercom4.h"
+#include "instance/sercom5.h"
+#include "instance/sysctrl.h"
+#include "instance/tc3.h"
+#include "instance/tc4.h"
+#include "instance/tc5.h"
+#include "instance/tc6.h"
+#include "instance/tc7.h"
+#include "instance/tcc0.h"
+#include "instance/tcc1.h"
+#include "instance/tcc2.h"
+#include "instance/usb.h"
+#include "instance/wdt.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** PERIPHERAL ID DEFINITIONS FOR SAMD21J18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J18A_id Peripheral Ids Definitions */
+/*@{*/
+
+// Peripheral instances on HPB0 bridge
+#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */
+#define ID_PM 1 /**< \brief Power Manager (PM) */
+#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */
+#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */
+#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */
+#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */
+#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */
+
+// Peripheral instances on HPB1 bridge
+#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */
+#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */
+#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
+#define ID_PORT 35 /**< \brief Port Module (PORT) */
+#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */
+#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */
+#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
+#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */
+
+// Peripheral instances on HPB2 bridge
+#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */
+#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */
+#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
+#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */
+#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */
+#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */
+#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */
+#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */
+#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */
+#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */
+#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */
+#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */
+#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */
+#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */
+#define ID_TC6 78 /**< \brief Basic Timer Counter 6 (TC6) */
+#define ID_TC7 79 /**< \brief Basic Timer Counter 7 (TC7) */
+#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */
+#define ID_AC 81 /**< \brief Analog Comparators (AC) */
+#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */
+#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
+#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */
+
+#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */
+/*@}*/
+
+/* ************************************************************************** */
+/** BASE ADDRESS DEFINITIONS FOR SAMD21J18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J18A_base Peripheral Base Address Definitions */
+/*@{*/
+
+#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
+#define AC (0x42004400UL) /**< \brief (AC) APB Base Address */
+#define ADC (0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define DAC (0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define EIC (0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EVSYS (0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define GCLK (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define I2S (0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define PAC0 (0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1 (0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2 (0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PORT (0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define RTC (0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define SERCOM0 (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4 (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5 (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4 (0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5 (0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC6 (0x42003800UL) /**< \brief (TC6) APB Base Address */
+#define TC7 (0x42003C00UL) /**< \brief (TC7) APB Base Address */
+#define TCC0 (0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1 (0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2 (0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define USB (0x41005000UL) /**< \brief (USB) APB Base Address */
+#define WDT (0x40001000UL) /**< \brief (WDT) APB Base Address */
+#else
+#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */
+#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
+#define AC_INSTS { AC } /**< \brief (AC) Instances List */
+
+#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */
+#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */
+#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */
+
+#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */
+#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */
+#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */
+
+#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */
+#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */
+#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
+
+#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */
+#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
+#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */
+
+#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */
+#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
+#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */
+
+#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */
+#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
+#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */
+
+#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */
+#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
+#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
+
+#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
+#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */
+#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */
+
+#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */
+#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */
+#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */
+
+#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */
+#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
+#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
+
+#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
+#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
+#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
+#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */
+#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */
+#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */
+#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
+#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
+#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
+#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */
+
+#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */
+#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */
+#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */
+#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */
+#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */
+
+#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */
+#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
+#define PM_INSTS { PM } /**< \brief (PM) Instances List */
+
+#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */
+#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
+#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
+#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */
+
+#define PTC_GCLK_ID 34
+#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */
+#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */
+
+#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */
+#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
+#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */
+
+#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */
+#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */
+#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */
+#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */
+#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */
+#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */
+#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */
+#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
+
+#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */
+#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */
+#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */
+
+#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */
+#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */
+#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */
+#define TC6 ((Tc *)0x42003800UL) /**< \brief (TC6) APB Base Address */
+#define TC7 ((Tc *)0x42003C00UL) /**< \brief (TC7) APB Base Address */
+#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */
+#define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */
+
+#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */
+#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */
+#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */
+#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */
+#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
+
+#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */
+#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */
+#define USB_INSTS { USB } /**< \brief (USB) Instances List */
+
+#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */
+#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
+#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */
+
+#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
+/*@}*/
+
+/* ************************************************************************** */
+/** PORT DEFINITIONS FOR SAMD21J18A */
+/* ************************************************************************** */
+/** \defgroup SAMD21J18A_port PORT Definitions */
+/*@{*/
+
+#include "pio/samd21j18a.h"
+/*@}*/
+
+/* ************************************************************************** */
+/** MEMORY MAPPING DEFINITIONS FOR SAMD21J18A */
+/* ************************************************************************** */
+
+#define FLASH_SIZE 0x40000UL /* 256 kB */
+#define FLASH_PAGE_SIZE 64
+#define FLASH_NB_OF_PAGES 4096
+#define FLASH_USER_PAGE_SIZE 64
+#define HMCRAMC0_SIZE 0x8000UL /* 32 kB */
+
+#define FLASH_ADDR (0x00000000u) /**< FLASH base address */
+#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */
+#define HMCRAMC0_ADDR (0x20000000u) /**< HMCRAMC0 base address */
+#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */
+#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */
+#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */
+#define PPB_ADDR (0xE0000000u) /**< PPB base address */
+
+#define DSU_DID_RESETVALUE 0x10010000UL
+#define EIC_EXTINT_NUM 16
+#define PORT_GROUPS 2
+
+/* ************************************************************************** */
+/** ELECTRICAL DEFINITIONS FOR SAMD21J18A */
+/* ************************************************************************** */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/
+
+#endif /* SAMD21J18A_H */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/system_samd21.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/system_samd21.h
new file mode 100644
index 0000000000000000000000000000000000000000..47b3ea35c9f8eccd487f1c60dd321ab527f718ba
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/include/system_samd21.h
@@ -0,0 +1,62 @@
+/**
+ * \file
+ *
+ * \brief Low-level initialization functions called upon chip startup
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _SYSTEM_SAMD21_H_INCLUDED_
+#define _SYSTEM_SAMD21_H_INCLUDED_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+void SystemInit(void);
+void SystemCoreClockUpdate(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_SAMD21_H_INCLUDED */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21e15a_flash.ld b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21e15a_flash.ld
new file mode 100644
index 0000000000000000000000000000000000000000..f2a0727d495120a8c906489cedd56f8a06a7ee16
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21e15a_flash.ld
@@ -0,0 +1,157 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21E15A
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+ rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00008000
+ ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00001000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x400;
+
+/* Section Definitions */
+SECTIONS
+{
+ .text :
+ {
+ . = ALIGN(4);
+ _sfixed = .;
+ KEEP(*(.vectors .vectors.*))
+ *(.text .text.* .gnu.linkonce.t.*)
+ *(.glue_7t) *(.glue_7)
+ *(.rodata .rodata* .gnu.linkonce.r.*)
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+ /* Support C constructors, and C destructors in both user code
+ and the C library. This also provides support for C++ code. */
+ . = ALIGN(4);
+ KEEP(*(.init))
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ . = ALIGN(4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(4);
+ KEEP(*(.fini))
+
+ . = ALIGN(4);
+ __fini_array_start = .;
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ __fini_array_end = .;
+
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+
+ . = ALIGN(4);
+ _efixed = .; /* End of text section */
+ } > rom
+
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ PROVIDE_HIDDEN (__exidx_start = .);
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > rom
+ PROVIDE_HIDDEN (__exidx_end = .);
+
+ . = ALIGN(4);
+ _etext = .;
+
+ .relocate : AT (_etext)
+ {
+ . = ALIGN(4);
+ _srelocate = .;
+ *(.ramfunc .ramfunc.*);
+ *(.data .data.*);
+ . = ALIGN(4);
+ _erelocate = .;
+ } > ram
+
+ /* .bss section which is used for uninitialized data */
+ .bss (NOLOAD) :
+ {
+ . = ALIGN(4);
+ _sbss = . ;
+ _szero = .;
+ *(.bss .bss.*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = . ;
+ _ezero = .;
+ } > ram
+
+ /* stack section */
+ .stack (NOLOAD):
+ {
+ . = ALIGN(8);
+ _sstack = .;
+ . = . + STACK_SIZE;
+ . = ALIGN(8);
+ _estack = .;
+ } > ram
+
+ . = ALIGN(4);
+ _end = . ;
+}
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21e15a_sram.ld b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21e15a_sram.ld
new file mode 100644
index 0000000000000000000000000000000000000000..38ab271df428c5d4cad2395bf6cf4580add8d86e
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21e15a_sram.ld
@@ -0,0 +1,156 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21E15A
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+ ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00001000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x400;
+
+/* Section Definitions */
+SECTIONS
+{
+ .text :
+ {
+ . = ALIGN(4);
+ _sfixed = .;
+ KEEP(*(.vectors .vectors.*))
+ *(.text .text.* .gnu.linkonce.t.*)
+ *(.glue_7t) *(.glue_7)
+ *(.rodata .rodata* .gnu.linkonce.r.*)
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+ /* Support C constructors, and C destructors in both user code
+ and the C library. This also provides support for C++ code. */
+ . = ALIGN(4);
+ KEEP(*(.init))
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ . = ALIGN(4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(4);
+ KEEP(*(.fini))
+
+ . = ALIGN(4);
+ __fini_array_start = .;
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ __fini_array_end = .;
+
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+
+ . = ALIGN(4);
+ _efixed = .; /* End of text section */
+ } > ram
+
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ PROVIDE_HIDDEN (__exidx_start = .);
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > ram
+ PROVIDE_HIDDEN (__exidx_end = .);
+
+ . = ALIGN(4);
+ _etext = .;
+
+ .relocate : AT (_etext)
+ {
+ . = ALIGN(4);
+ _srelocate = .;
+ *(.ramfunc .ramfunc.*);
+ *(.data .data.*);
+ . = ALIGN(4);
+ _erelocate = .;
+ } > ram
+
+ /* .bss section which is used for uninitialized data */
+ .bss (NOLOAD) :
+ {
+ . = ALIGN(4);
+ _sbss = . ;
+ _szero = .;
+ *(.bss .bss.*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = . ;
+ _ezero = .;
+ } > ram
+
+ /* stack section */
+ .stack (NOLOAD):
+ {
+ . = ALIGN(8);
+ _sstack = .;
+ . = . + STACK_SIZE;
+ . = ALIGN(8);
+ _estack = .;
+ } > ram
+
+ . = ALIGN(4);
+ _end = . ;
+}
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21e15b_flash.ld b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21e15b_flash.ld
new file mode 100644
index 0000000000000000000000000000000000000000..433647a8c352e58641eeb189af16ad7fdb500296
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21e15b_flash.ld
@@ -0,0 +1,157 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21E15B
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+ rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00008000
+ ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00001000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x400;
+
+/* Section Definitions */
+SECTIONS
+{
+ .text :
+ {
+ . = ALIGN(4);
+ _sfixed = .;
+ KEEP(*(.vectors .vectors.*))
+ *(.text .text.* .gnu.linkonce.t.*)
+ *(.glue_7t) *(.glue_7)
+ *(.rodata .rodata* .gnu.linkonce.r.*)
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+ /* Support C constructors, and C destructors in both user code
+ and the C library. This also provides support for C++ code. */
+ . = ALIGN(4);
+ KEEP(*(.init))
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ . = ALIGN(4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(4);
+ KEEP(*(.fini))
+
+ . = ALIGN(4);
+ __fini_array_start = .;
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ __fini_array_end = .;
+
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+
+ . = ALIGN(4);
+ _efixed = .; /* End of text section */
+ } > rom
+
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ PROVIDE_HIDDEN (__exidx_start = .);
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > rom
+ PROVIDE_HIDDEN (__exidx_end = .);
+
+ . = ALIGN(4);
+ _etext = .;
+
+ .relocate : AT (_etext)
+ {
+ . = ALIGN(4);
+ _srelocate = .;
+ *(.ramfunc .ramfunc.*);
+ *(.data .data.*);
+ . = ALIGN(4);
+ _erelocate = .;
+ } > ram
+
+ /* .bss section which is used for uninitialized data */
+ .bss (NOLOAD) :
+ {
+ . = ALIGN(4);
+ _sbss = . ;
+ _szero = .;
+ *(.bss .bss.*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = . ;
+ _ezero = .;
+ } > ram
+
+ /* stack section */
+ .stack (NOLOAD):
+ {
+ . = ALIGN(8);
+ _sstack = .;
+ . = . + STACK_SIZE;
+ . = ALIGN(8);
+ _estack = .;
+ } > ram
+
+ . = ALIGN(4);
+ _end = . ;
+}
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21e15b_sram.ld b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21e15b_sram.ld
new file mode 100644
index 0000000000000000000000000000000000000000..64443ec29bc4c1b4252c6687fe586d3bb8df3c9a
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21e15b_sram.ld
@@ -0,0 +1,156 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21E15B
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+ ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00001000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x400;
+
+/* Section Definitions */
+SECTIONS
+{
+ .text :
+ {
+ . = ALIGN(4);
+ _sfixed = .;
+ KEEP(*(.vectors .vectors.*))
+ *(.text .text.* .gnu.linkonce.t.*)
+ *(.glue_7t) *(.glue_7)
+ *(.rodata .rodata* .gnu.linkonce.r.*)
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+ /* Support C constructors, and C destructors in both user code
+ and the C library. This also provides support for C++ code. */
+ . = ALIGN(4);
+ KEEP(*(.init))
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ . = ALIGN(4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(4);
+ KEEP(*(.fini))
+
+ . = ALIGN(4);
+ __fini_array_start = .;
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ __fini_array_end = .;
+
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+
+ . = ALIGN(4);
+ _efixed = .; /* End of text section */
+ } > ram
+
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ PROVIDE_HIDDEN (__exidx_start = .);
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > ram
+ PROVIDE_HIDDEN (__exidx_end = .);
+
+ . = ALIGN(4);
+ _etext = .;
+
+ .relocate : AT (_etext)
+ {
+ . = ALIGN(4);
+ _srelocate = .;
+ *(.ramfunc .ramfunc.*);
+ *(.data .data.*);
+ . = ALIGN(4);
+ _erelocate = .;
+ } > ram
+
+ /* .bss section which is used for uninitialized data */
+ .bss (NOLOAD) :
+ {
+ . = ALIGN(4);
+ _sbss = . ;
+ _szero = .;
+ *(.bss .bss.*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = . ;
+ _ezero = .;
+ } > ram
+
+ /* stack section */
+ .stack (NOLOAD):
+ {
+ . = ALIGN(8);
+ _sstack = .;
+ . = . + STACK_SIZE;
+ . = ALIGN(8);
+ _estack = .;
+ } > ram
+
+ . = ALIGN(4);
+ _end = . ;
+}
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21e15bu_flash.ld b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21e15bu_flash.ld
new file mode 100644
index 0000000000000000000000000000000000000000..0684c0d191386e77a5ea1465e4e2109cd1846652
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21e15bu_flash.ld
@@ -0,0 +1,157 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21E15BU
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+ rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00008000
+ ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00001000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x400;
+
+/* Section Definitions */
+SECTIONS
+{
+ .text :
+ {
+ . = ALIGN(4);
+ _sfixed = .;
+ KEEP(*(.vectors .vectors.*))
+ *(.text .text.* .gnu.linkonce.t.*)
+ *(.glue_7t) *(.glue_7)
+ *(.rodata .rodata* .gnu.linkonce.r.*)
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+ /* Support C constructors, and C destructors in both user code
+ and the C library. This also provides support for C++ code. */
+ . = ALIGN(4);
+ KEEP(*(.init))
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ . = ALIGN(4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(4);
+ KEEP(*(.fini))
+
+ . = ALIGN(4);
+ __fini_array_start = .;
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ __fini_array_end = .;
+
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+
+ . = ALIGN(4);
+ _efixed = .; /* End of text section */
+ } > rom
+
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ PROVIDE_HIDDEN (__exidx_start = .);
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > rom
+ PROVIDE_HIDDEN (__exidx_end = .);
+
+ . = ALIGN(4);
+ _etext = .;
+
+ .relocate : AT (_etext)
+ {
+ . = ALIGN(4);
+ _srelocate = .;
+ *(.ramfunc .ramfunc.*);
+ *(.data .data.*);
+ . = ALIGN(4);
+ _erelocate = .;
+ } > ram
+
+ /* .bss section which is used for uninitialized data */
+ .bss (NOLOAD) :
+ {
+ . = ALIGN(4);
+ _sbss = . ;
+ _szero = .;
+ *(.bss .bss.*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = . ;
+ _ezero = .;
+ } > ram
+
+ /* stack section */
+ .stack (NOLOAD):
+ {
+ . = ALIGN(8);
+ _sstack = .;
+ . = . + STACK_SIZE;
+ . = ALIGN(8);
+ _estack = .;
+ } > ram
+
+ . = ALIGN(4);
+ _end = . ;
+}
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21e15bu_sram.ld b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21e15bu_sram.ld
new file mode 100644
index 0000000000000000000000000000000000000000..4d2305d3a48f856c96e80d7ca3b133a0dd703ab1
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21e15bu_sram.ld
@@ -0,0 +1,156 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21E15BU
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+ ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00001000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x400;
+
+/* Section Definitions */
+SECTIONS
+{
+ .text :
+ {
+ . = ALIGN(4);
+ _sfixed = .;
+ KEEP(*(.vectors .vectors.*))
+ *(.text .text.* .gnu.linkonce.t.*)
+ *(.glue_7t) *(.glue_7)
+ *(.rodata .rodata* .gnu.linkonce.r.*)
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+ /* Support C constructors, and C destructors in both user code
+ and the C library. This also provides support for C++ code. */
+ . = ALIGN(4);
+ KEEP(*(.init))
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ . = ALIGN(4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(4);
+ KEEP(*(.fini))
+
+ . = ALIGN(4);
+ __fini_array_start = .;
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ __fini_array_end = .;
+
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+
+ . = ALIGN(4);
+ _efixed = .; /* End of text section */
+ } > ram
+
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ PROVIDE_HIDDEN (__exidx_start = .);
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > ram
+ PROVIDE_HIDDEN (__exidx_end = .);
+
+ . = ALIGN(4);
+ _etext = .;
+
+ .relocate : AT (_etext)
+ {
+ . = ALIGN(4);
+ _srelocate = .;
+ *(.ramfunc .ramfunc.*);
+ *(.data .data.*);
+ . = ALIGN(4);
+ _erelocate = .;
+ } > ram
+
+ /* .bss section which is used for uninitialized data */
+ .bss (NOLOAD) :
+ {
+ . = ALIGN(4);
+ _sbss = . ;
+ _szero = .;
+ *(.bss .bss.*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = . ;
+ _ezero = .;
+ } > ram
+
+ /* stack section */
+ .stack (NOLOAD):
+ {
+ . = ALIGN(8);
+ _sstack = .;
+ . = . + STACK_SIZE;
+ . = ALIGN(8);
+ _estack = .;
+ } > ram
+
+ . = ALIGN(4);
+ _end = . ;
+}
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21e15l_flash.ld b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21e15l_flash.ld
new file mode 100644
index 0000000000000000000000000000000000000000..81c73c07243119dfc4cabb6e0d4ce9d4f11cfe68
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21e15l_flash.ld
@@ -0,0 +1,157 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21E15L
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+ rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00008000
+ ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00001000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x400;
+
+/* Section Definitions */
+SECTIONS
+{
+ .text :
+ {
+ . = ALIGN(4);
+ _sfixed = .;
+ KEEP(*(.vectors .vectors.*))
+ *(.text .text.* .gnu.linkonce.t.*)
+ *(.glue_7t) *(.glue_7)
+ *(.rodata .rodata* .gnu.linkonce.r.*)
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+ /* Support C constructors, and C destructors in both user code
+ and the C library. This also provides support for C++ code. */
+ . = ALIGN(4);
+ KEEP(*(.init))
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ . = ALIGN(4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(4);
+ KEEP(*(.fini))
+
+ . = ALIGN(4);
+ __fini_array_start = .;
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ __fini_array_end = .;
+
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+
+ . = ALIGN(4);
+ _efixed = .; /* End of text section */
+ } > rom
+
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ PROVIDE_HIDDEN (__exidx_start = .);
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > rom
+ PROVIDE_HIDDEN (__exidx_end = .);
+
+ . = ALIGN(4);
+ _etext = .;
+
+ .relocate : AT (_etext)
+ {
+ . = ALIGN(4);
+ _srelocate = .;
+ *(.ramfunc .ramfunc.*);
+ *(.data .data.*);
+ . = ALIGN(4);
+ _erelocate = .;
+ } > ram
+
+ /* .bss section which is used for uninitialized data */
+ .bss (NOLOAD) :
+ {
+ . = ALIGN(4);
+ _sbss = . ;
+ _szero = .;
+ *(.bss .bss.*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = . ;
+ _ezero = .;
+ } > ram
+
+ /* stack section */
+ .stack (NOLOAD):
+ {
+ . = ALIGN(8);
+ _sstack = .;
+ . = . + STACK_SIZE;
+ . = ALIGN(8);
+ _estack = .;
+ } > ram
+
+ . = ALIGN(4);
+ _end = . ;
+}
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21e15l_sram.ld b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21e15l_sram.ld
new file mode 100644
index 0000000000000000000000000000000000000000..6cf9c7378671fc77bad95cb459cd9b58092964c7
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21e15l_sram.ld
@@ -0,0 +1,156 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21E15L
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+ ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00001000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x400;
+
+/* Section Definitions */
+SECTIONS
+{
+ .text :
+ {
+ . = ALIGN(4);
+ _sfixed = .;
+ KEEP(*(.vectors .vectors.*))
+ *(.text .text.* .gnu.linkonce.t.*)
+ *(.glue_7t) *(.glue_7)
+ *(.rodata .rodata* .gnu.linkonce.r.*)
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+ /* Support C constructors, and C destructors in both user code
+ and the C library. This also provides support for C++ code. */
+ . = ALIGN(4);
+ KEEP(*(.init))
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ . = ALIGN(4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(4);
+ KEEP(*(.fini))
+
+ . = ALIGN(4);
+ __fini_array_start = .;
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ __fini_array_end = .;
+
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+
+ . = ALIGN(4);
+ _efixed = .; /* End of text section */
+ } > ram
+
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ PROVIDE_HIDDEN (__exidx_start = .);
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > ram
+ PROVIDE_HIDDEN (__exidx_end = .);
+
+ . = ALIGN(4);
+ _etext = .;
+
+ .relocate : AT (_etext)
+ {
+ . = ALIGN(4);
+ _srelocate = .;
+ *(.ramfunc .ramfunc.*);
+ *(.data .data.*);
+ . = ALIGN(4);
+ _erelocate = .;
+ } > ram
+
+ /* .bss section which is used for uninitialized data */
+ .bss (NOLOAD) :
+ {
+ . = ALIGN(4);
+ _sbss = . ;
+ _szero = .;
+ *(.bss .bss.*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = . ;
+ _ezero = .;
+ } > ram
+
+ /* stack section */
+ .stack (NOLOAD):
+ {
+ . = ALIGN(8);
+ _sstack = .;
+ . = . + STACK_SIZE;
+ . = ALIGN(8);
+ _estack = .;
+ } > ram
+
+ . = ALIGN(4);
+ _end = . ;
+}
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21e16a_flash.ld b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21e16a_flash.ld
new file mode 100644
index 0000000000000000000000000000000000000000..059e7dab920e5e5eb02b673b1563b0e0e71fbece
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21e16a_flash.ld
@@ -0,0 +1,157 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21E16A
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+ rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00010000
+ ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00002000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x800;
+
+/* Section Definitions */
+SECTIONS
+{
+ .text :
+ {
+ . = ALIGN(4);
+ _sfixed = .;
+ KEEP(*(.vectors .vectors.*))
+ *(.text .text.* .gnu.linkonce.t.*)
+ *(.glue_7t) *(.glue_7)
+ *(.rodata .rodata* .gnu.linkonce.r.*)
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+ /* Support C constructors, and C destructors in both user code
+ and the C library. This also provides support for C++ code. */
+ . = ALIGN(4);
+ KEEP(*(.init))
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ . = ALIGN(4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(4);
+ KEEP(*(.fini))
+
+ . = ALIGN(4);
+ __fini_array_start = .;
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ __fini_array_end = .;
+
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+
+ . = ALIGN(4);
+ _efixed = .; /* End of text section */
+ } > rom
+
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ PROVIDE_HIDDEN (__exidx_start = .);
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > rom
+ PROVIDE_HIDDEN (__exidx_end = .);
+
+ . = ALIGN(4);
+ _etext = .;
+
+ .relocate : AT (_etext)
+ {
+ . = ALIGN(4);
+ _srelocate = .;
+ *(.ramfunc .ramfunc.*);
+ *(.data .data.*);
+ . = ALIGN(4);
+ _erelocate = .;
+ } > ram
+
+ /* .bss section which is used for uninitialized data */
+ .bss (NOLOAD) :
+ {
+ . = ALIGN(4);
+ _sbss = . ;
+ _szero = .;
+ *(.bss .bss.*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = . ;
+ _ezero = .;
+ } > ram
+
+ /* stack section */
+ .stack (NOLOAD):
+ {
+ . = ALIGN(8);
+ _sstack = .;
+ . = . + STACK_SIZE;
+ . = ALIGN(8);
+ _estack = .;
+ } > ram
+
+ . = ALIGN(4);
+ _end = . ;
+}
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21e16a_sram.ld b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21e16a_sram.ld
new file mode 100644
index 0000000000000000000000000000000000000000..0dd94eb1326839e7db83125f43206d5208725809
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21e16a_sram.ld
@@ -0,0 +1,156 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21E16A
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+ ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00002000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x800;
+
+/* Section Definitions */
+SECTIONS
+{
+ .text :
+ {
+ . = ALIGN(4);
+ _sfixed = .;
+ KEEP(*(.vectors .vectors.*))
+ *(.text .text.* .gnu.linkonce.t.*)
+ *(.glue_7t) *(.glue_7)
+ *(.rodata .rodata* .gnu.linkonce.r.*)
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+ /* Support C constructors, and C destructors in both user code
+ and the C library. This also provides support for C++ code. */
+ . = ALIGN(4);
+ KEEP(*(.init))
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ . = ALIGN(4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(4);
+ KEEP(*(.fini))
+
+ . = ALIGN(4);
+ __fini_array_start = .;
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ __fini_array_end = .;
+
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+
+ . = ALIGN(4);
+ _efixed = .; /* End of text section */
+ } > ram
+
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ PROVIDE_HIDDEN (__exidx_start = .);
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > ram
+ PROVIDE_HIDDEN (__exidx_end = .);
+
+ . = ALIGN(4);
+ _etext = .;
+
+ .relocate : AT (_etext)
+ {
+ . = ALIGN(4);
+ _srelocate = .;
+ *(.ramfunc .ramfunc.*);
+ *(.data .data.*);
+ . = ALIGN(4);
+ _erelocate = .;
+ } > ram
+
+ /* .bss section which is used for uninitialized data */
+ .bss (NOLOAD) :
+ {
+ . = ALIGN(4);
+ _sbss = . ;
+ _szero = .;
+ *(.bss .bss.*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = . ;
+ _ezero = .;
+ } > ram
+
+ /* stack section */
+ .stack (NOLOAD):
+ {
+ . = ALIGN(8);
+ _sstack = .;
+ . = . + STACK_SIZE;
+ . = ALIGN(8);
+ _estack = .;
+ } > ram
+
+ . = ALIGN(4);
+ _end = . ;
+}
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21e16b_flash.ld b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21e16b_flash.ld
new file mode 100644
index 0000000000000000000000000000000000000000..95e7e81bbac36e8ad88ffa0c2261eb17af966775
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21e16b_flash.ld
@@ -0,0 +1,157 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21E16B
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+ rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00010000
+ ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00002000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x800;
+
+/* Section Definitions */
+SECTIONS
+{
+ .text :
+ {
+ . = ALIGN(4);
+ _sfixed = .;
+ KEEP(*(.vectors .vectors.*))
+ *(.text .text.* .gnu.linkonce.t.*)
+ *(.glue_7t) *(.glue_7)
+ *(.rodata .rodata* .gnu.linkonce.r.*)
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+ /* Support C constructors, and C destructors in both user code
+ and the C library. This also provides support for C++ code. */
+ . = ALIGN(4);
+ KEEP(*(.init))
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ . = ALIGN(4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(4);
+ KEEP(*(.fini))
+
+ . = ALIGN(4);
+ __fini_array_start = .;
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ __fini_array_end = .;
+
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+
+ . = ALIGN(4);
+ _efixed = .; /* End of text section */
+ } > rom
+
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ PROVIDE_HIDDEN (__exidx_start = .);
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > rom
+ PROVIDE_HIDDEN (__exidx_end = .);
+
+ . = ALIGN(4);
+ _etext = .;
+
+ .relocate : AT (_etext)
+ {
+ . = ALIGN(4);
+ _srelocate = .;
+ *(.ramfunc .ramfunc.*);
+ *(.data .data.*);
+ . = ALIGN(4);
+ _erelocate = .;
+ } > ram
+
+ /* .bss section which is used for uninitialized data */
+ .bss (NOLOAD) :
+ {
+ . = ALIGN(4);
+ _sbss = . ;
+ _szero = .;
+ *(.bss .bss.*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = . ;
+ _ezero = .;
+ } > ram
+
+ /* stack section */
+ .stack (NOLOAD):
+ {
+ . = ALIGN(8);
+ _sstack = .;
+ . = . + STACK_SIZE;
+ . = ALIGN(8);
+ _estack = .;
+ } > ram
+
+ . = ALIGN(4);
+ _end = . ;
+}
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21e16b_sram.ld b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21e16b_sram.ld
new file mode 100644
index 0000000000000000000000000000000000000000..c500b3cbf2c91bc6c0a3aa1555bcc445541e5988
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21e16b_sram.ld
@@ -0,0 +1,156 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21E16B
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+ ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00002000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x800;
+
+/* Section Definitions */
+SECTIONS
+{
+ .text :
+ {
+ . = ALIGN(4);
+ _sfixed = .;
+ KEEP(*(.vectors .vectors.*))
+ *(.text .text.* .gnu.linkonce.t.*)
+ *(.glue_7t) *(.glue_7)
+ *(.rodata .rodata* .gnu.linkonce.r.*)
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+ /* Support C constructors, and C destructors in both user code
+ and the C library. This also provides support for C++ code. */
+ . = ALIGN(4);
+ KEEP(*(.init))
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ . = ALIGN(4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(4);
+ KEEP(*(.fini))
+
+ . = ALIGN(4);
+ __fini_array_start = .;
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ __fini_array_end = .;
+
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+
+ . = ALIGN(4);
+ _efixed = .; /* End of text section */
+ } > ram
+
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ PROVIDE_HIDDEN (__exidx_start = .);
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > ram
+ PROVIDE_HIDDEN (__exidx_end = .);
+
+ . = ALIGN(4);
+ _etext = .;
+
+ .relocate : AT (_etext)
+ {
+ . = ALIGN(4);
+ _srelocate = .;
+ *(.ramfunc .ramfunc.*);
+ *(.data .data.*);
+ . = ALIGN(4);
+ _erelocate = .;
+ } > ram
+
+ /* .bss section which is used for uninitialized data */
+ .bss (NOLOAD) :
+ {
+ . = ALIGN(4);
+ _sbss = . ;
+ _szero = .;
+ *(.bss .bss.*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = . ;
+ _ezero = .;
+ } > ram
+
+ /* stack section */
+ .stack (NOLOAD):
+ {
+ . = ALIGN(8);
+ _sstack = .;
+ . = . + STACK_SIZE;
+ . = ALIGN(8);
+ _estack = .;
+ } > ram
+
+ . = ALIGN(4);
+ _end = . ;
+}
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21e16bu_flash.ld b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21e16bu_flash.ld
new file mode 100644
index 0000000000000000000000000000000000000000..20cad4f3629efe7565cee3bc459b1479f3e1c43f
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21e16bu_flash.ld
@@ -0,0 +1,157 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21E16BU
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+ rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00010000
+ ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00002000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x800;
+
+/* Section Definitions */
+SECTIONS
+{
+ .text :
+ {
+ . = ALIGN(4);
+ _sfixed = .;
+ KEEP(*(.vectors .vectors.*))
+ *(.text .text.* .gnu.linkonce.t.*)
+ *(.glue_7t) *(.glue_7)
+ *(.rodata .rodata* .gnu.linkonce.r.*)
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+ /* Support C constructors, and C destructors in both user code
+ and the C library. This also provides support for C++ code. */
+ . = ALIGN(4);
+ KEEP(*(.init))
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ . = ALIGN(4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(4);
+ KEEP(*(.fini))
+
+ . = ALIGN(4);
+ __fini_array_start = .;
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ __fini_array_end = .;
+
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+
+ . = ALIGN(4);
+ _efixed = .; /* End of text section */
+ } > rom
+
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ PROVIDE_HIDDEN (__exidx_start = .);
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > rom
+ PROVIDE_HIDDEN (__exidx_end = .);
+
+ . = ALIGN(4);
+ _etext = .;
+
+ .relocate : AT (_etext)
+ {
+ . = ALIGN(4);
+ _srelocate = .;
+ *(.ramfunc .ramfunc.*);
+ *(.data .data.*);
+ . = ALIGN(4);
+ _erelocate = .;
+ } > ram
+
+ /* .bss section which is used for uninitialized data */
+ .bss (NOLOAD) :
+ {
+ . = ALIGN(4);
+ _sbss = . ;
+ _szero = .;
+ *(.bss .bss.*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = . ;
+ _ezero = .;
+ } > ram
+
+ /* stack section */
+ .stack (NOLOAD):
+ {
+ . = ALIGN(8);
+ _sstack = .;
+ . = . + STACK_SIZE;
+ . = ALIGN(8);
+ _estack = .;
+ } > ram
+
+ . = ALIGN(4);
+ _end = . ;
+}
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21e16bu_sram.ld b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21e16bu_sram.ld
new file mode 100644
index 0000000000000000000000000000000000000000..f129d2ea71779a35df59dcc24e3d43703a0c95b9
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21e16bu_sram.ld
@@ -0,0 +1,156 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21E16BU
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+ ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00002000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x800;
+
+/* Section Definitions */
+SECTIONS
+{
+ .text :
+ {
+ . = ALIGN(4);
+ _sfixed = .;
+ KEEP(*(.vectors .vectors.*))
+ *(.text .text.* .gnu.linkonce.t.*)
+ *(.glue_7t) *(.glue_7)
+ *(.rodata .rodata* .gnu.linkonce.r.*)
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+ /* Support C constructors, and C destructors in both user code
+ and the C library. This also provides support for C++ code. */
+ . = ALIGN(4);
+ KEEP(*(.init))
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ . = ALIGN(4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(4);
+ KEEP(*(.fini))
+
+ . = ALIGN(4);
+ __fini_array_start = .;
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ __fini_array_end = .;
+
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+
+ . = ALIGN(4);
+ _efixed = .; /* End of text section */
+ } > ram
+
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ PROVIDE_HIDDEN (__exidx_start = .);
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > ram
+ PROVIDE_HIDDEN (__exidx_end = .);
+
+ . = ALIGN(4);
+ _etext = .;
+
+ .relocate : AT (_etext)
+ {
+ . = ALIGN(4);
+ _srelocate = .;
+ *(.ramfunc .ramfunc.*);
+ *(.data .data.*);
+ . = ALIGN(4);
+ _erelocate = .;
+ } > ram
+
+ /* .bss section which is used for uninitialized data */
+ .bss (NOLOAD) :
+ {
+ . = ALIGN(4);
+ _sbss = . ;
+ _szero = .;
+ *(.bss .bss.*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = . ;
+ _ezero = .;
+ } > ram
+
+ /* stack section */
+ .stack (NOLOAD):
+ {
+ . = ALIGN(8);
+ _sstack = .;
+ . = . + STACK_SIZE;
+ . = ALIGN(8);
+ _estack = .;
+ } > ram
+
+ . = ALIGN(4);
+ _end = . ;
+}
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21e16l_flash.ld b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21e16l_flash.ld
new file mode 100644
index 0000000000000000000000000000000000000000..a106a88e41264dd95867f0370d31e4d2aebb74ba
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21e16l_flash.ld
@@ -0,0 +1,157 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21E16L
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+ rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00010000
+ ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00002000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x800;
+
+/* Section Definitions */
+SECTIONS
+{
+ .text :
+ {
+ . = ALIGN(4);
+ _sfixed = .;
+ KEEP(*(.vectors .vectors.*))
+ *(.text .text.* .gnu.linkonce.t.*)
+ *(.glue_7t) *(.glue_7)
+ *(.rodata .rodata* .gnu.linkonce.r.*)
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+ /* Support C constructors, and C destructors in both user code
+ and the C library. This also provides support for C++ code. */
+ . = ALIGN(4);
+ KEEP(*(.init))
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ . = ALIGN(4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(4);
+ KEEP(*(.fini))
+
+ . = ALIGN(4);
+ __fini_array_start = .;
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ __fini_array_end = .;
+
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+
+ . = ALIGN(4);
+ _efixed = .; /* End of text section */
+ } > rom
+
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ PROVIDE_HIDDEN (__exidx_start = .);
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > rom
+ PROVIDE_HIDDEN (__exidx_end = .);
+
+ . = ALIGN(4);
+ _etext = .;
+
+ .relocate : AT (_etext)
+ {
+ . = ALIGN(4);
+ _srelocate = .;
+ *(.ramfunc .ramfunc.*);
+ *(.data .data.*);
+ . = ALIGN(4);
+ _erelocate = .;
+ } > ram
+
+ /* .bss section which is used for uninitialized data */
+ .bss (NOLOAD) :
+ {
+ . = ALIGN(4);
+ _sbss = . ;
+ _szero = .;
+ *(.bss .bss.*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = . ;
+ _ezero = .;
+ } > ram
+
+ /* stack section */
+ .stack (NOLOAD):
+ {
+ . = ALIGN(8);
+ _sstack = .;
+ . = . + STACK_SIZE;
+ . = ALIGN(8);
+ _estack = .;
+ } > ram
+
+ . = ALIGN(4);
+ _end = . ;
+}
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21e16l_sram.ld b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21e16l_sram.ld
new file mode 100644
index 0000000000000000000000000000000000000000..b2b5fe6606b9694e560914d9d4cd85e5e5029a5d
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21e16l_sram.ld
@@ -0,0 +1,156 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21E16L
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+ ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00002000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x800;
+
+/* Section Definitions */
+SECTIONS
+{
+ .text :
+ {
+ . = ALIGN(4);
+ _sfixed = .;
+ KEEP(*(.vectors .vectors.*))
+ *(.text .text.* .gnu.linkonce.t.*)
+ *(.glue_7t) *(.glue_7)
+ *(.rodata .rodata* .gnu.linkonce.r.*)
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+ /* Support C constructors, and C destructors in both user code
+ and the C library. This also provides support for C++ code. */
+ . = ALIGN(4);
+ KEEP(*(.init))
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ . = ALIGN(4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(4);
+ KEEP(*(.fini))
+
+ . = ALIGN(4);
+ __fini_array_start = .;
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ __fini_array_end = .;
+
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+
+ . = ALIGN(4);
+ _efixed = .; /* End of text section */
+ } > ram
+
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ PROVIDE_HIDDEN (__exidx_start = .);
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > ram
+ PROVIDE_HIDDEN (__exidx_end = .);
+
+ . = ALIGN(4);
+ _etext = .;
+
+ .relocate : AT (_etext)
+ {
+ . = ALIGN(4);
+ _srelocate = .;
+ *(.ramfunc .ramfunc.*);
+ *(.data .data.*);
+ . = ALIGN(4);
+ _erelocate = .;
+ } > ram
+
+ /* .bss section which is used for uninitialized data */
+ .bss (NOLOAD) :
+ {
+ . = ALIGN(4);
+ _sbss = . ;
+ _szero = .;
+ *(.bss .bss.*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = . ;
+ _ezero = .;
+ } > ram
+
+ /* stack section */
+ .stack (NOLOAD):
+ {
+ . = ALIGN(8);
+ _sstack = .;
+ . = . + STACK_SIZE;
+ . = ALIGN(8);
+ _estack = .;
+ } > ram
+
+ . = ALIGN(4);
+ _end = . ;
+}
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21e17a_flash.ld b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21e17a_flash.ld
new file mode 100644
index 0000000000000000000000000000000000000000..ad9be9c1ecd7a907ec2fcfd9166a533e954a1f19
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21e17a_flash.ld
@@ -0,0 +1,157 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21E17A
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+ rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00020000
+ ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00004000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x1000;
+
+/* Section Definitions */
+SECTIONS
+{
+ .text :
+ {
+ . = ALIGN(4);
+ _sfixed = .;
+ KEEP(*(.vectors .vectors.*))
+ *(.text .text.* .gnu.linkonce.t.*)
+ *(.glue_7t) *(.glue_7)
+ *(.rodata .rodata* .gnu.linkonce.r.*)
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+ /* Support C constructors, and C destructors in both user code
+ and the C library. This also provides support for C++ code. */
+ . = ALIGN(4);
+ KEEP(*(.init))
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ . = ALIGN(4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(4);
+ KEEP(*(.fini))
+
+ . = ALIGN(4);
+ __fini_array_start = .;
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ __fini_array_end = .;
+
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+
+ . = ALIGN(4);
+ _efixed = .; /* End of text section */
+ } > rom
+
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ PROVIDE_HIDDEN (__exidx_start = .);
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > rom
+ PROVIDE_HIDDEN (__exidx_end = .);
+
+ . = ALIGN(4);
+ _etext = .;
+
+ .relocate : AT (_etext)
+ {
+ . = ALIGN(4);
+ _srelocate = .;
+ *(.ramfunc .ramfunc.*);
+ *(.data .data.*);
+ . = ALIGN(4);
+ _erelocate = .;
+ } > ram
+
+ /* .bss section which is used for uninitialized data */
+ .bss (NOLOAD) :
+ {
+ . = ALIGN(4);
+ _sbss = . ;
+ _szero = .;
+ *(.bss .bss.*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = . ;
+ _ezero = .;
+ } > ram
+
+ /* stack section */
+ .stack (NOLOAD):
+ {
+ . = ALIGN(8);
+ _sstack = .;
+ . = . + STACK_SIZE;
+ . = ALIGN(8);
+ _estack = .;
+ } > ram
+
+ . = ALIGN(4);
+ _end = . ;
+}
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21e17a_sram.ld b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21e17a_sram.ld
new file mode 100644
index 0000000000000000000000000000000000000000..5d93278e4c7e5b6852183225dda0a6a5550762d0
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21e17a_sram.ld
@@ -0,0 +1,156 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21E17A
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+ ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00004000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x1000;
+
+/* Section Definitions */
+SECTIONS
+{
+ .text :
+ {
+ . = ALIGN(4);
+ _sfixed = .;
+ KEEP(*(.vectors .vectors.*))
+ *(.text .text.* .gnu.linkonce.t.*)
+ *(.glue_7t) *(.glue_7)
+ *(.rodata .rodata* .gnu.linkonce.r.*)
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+ /* Support C constructors, and C destructors in both user code
+ and the C library. This also provides support for C++ code. */
+ . = ALIGN(4);
+ KEEP(*(.init))
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ . = ALIGN(4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(4);
+ KEEP(*(.fini))
+
+ . = ALIGN(4);
+ __fini_array_start = .;
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ __fini_array_end = .;
+
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+
+ . = ALIGN(4);
+ _efixed = .; /* End of text section */
+ } > ram
+
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ PROVIDE_HIDDEN (__exidx_start = .);
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > ram
+ PROVIDE_HIDDEN (__exidx_end = .);
+
+ . = ALIGN(4);
+ _etext = .;
+
+ .relocate : AT (_etext)
+ {
+ . = ALIGN(4);
+ _srelocate = .;
+ *(.ramfunc .ramfunc.*);
+ *(.data .data.*);
+ . = ALIGN(4);
+ _erelocate = .;
+ } > ram
+
+ /* .bss section which is used for uninitialized data */
+ .bss (NOLOAD) :
+ {
+ . = ALIGN(4);
+ _sbss = . ;
+ _szero = .;
+ *(.bss .bss.*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = . ;
+ _ezero = .;
+ } > ram
+
+ /* stack section */
+ .stack (NOLOAD):
+ {
+ . = ALIGN(8);
+ _sstack = .;
+ . = . + STACK_SIZE;
+ . = ALIGN(8);
+ _estack = .;
+ } > ram
+
+ . = ALIGN(4);
+ _end = . ;
+}
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21e18a_flash.ld b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21e18a_flash.ld
new file mode 100644
index 0000000000000000000000000000000000000000..ed118114eb600193db448a53d11b3e6c5da12b86
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21e18a_flash.ld
@@ -0,0 +1,157 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21E18A
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+ rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000
+ ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
+
+/* Section Definitions */
+SECTIONS
+{
+ .text :
+ {
+ . = ALIGN(4);
+ _sfixed = .;
+ KEEP(*(.vectors .vectors.*))
+ *(.text .text.* .gnu.linkonce.t.*)
+ *(.glue_7t) *(.glue_7)
+ *(.rodata .rodata* .gnu.linkonce.r.*)
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+ /* Support C constructors, and C destructors in both user code
+ and the C library. This also provides support for C++ code. */
+ . = ALIGN(4);
+ KEEP(*(.init))
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ . = ALIGN(4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(4);
+ KEEP(*(.fini))
+
+ . = ALIGN(4);
+ __fini_array_start = .;
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ __fini_array_end = .;
+
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+
+ . = ALIGN(4);
+ _efixed = .; /* End of text section */
+ } > rom
+
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ PROVIDE_HIDDEN (__exidx_start = .);
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > rom
+ PROVIDE_HIDDEN (__exidx_end = .);
+
+ . = ALIGN(4);
+ _etext = .;
+
+ .relocate : AT (_etext)
+ {
+ . = ALIGN(4);
+ _srelocate = .;
+ *(.ramfunc .ramfunc.*);
+ *(.data .data.*);
+ . = ALIGN(4);
+ _erelocate = .;
+ } > ram
+
+ /* .bss section which is used for uninitialized data */
+ .bss (NOLOAD) :
+ {
+ . = ALIGN(4);
+ _sbss = . ;
+ _szero = .;
+ *(.bss .bss.*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = . ;
+ _ezero = .;
+ } > ram
+
+ /* stack section */
+ .stack (NOLOAD):
+ {
+ . = ALIGN(8);
+ _sstack = .;
+ . = . + STACK_SIZE;
+ . = ALIGN(8);
+ _estack = .;
+ } > ram
+
+ . = ALIGN(4);
+ _end = . ;
+}
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21e18a_sram.ld b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21e18a_sram.ld
new file mode 100644
index 0000000000000000000000000000000000000000..27702eb24eaa50b48532069916968a17931e0562
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21e18a_sram.ld
@@ -0,0 +1,156 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21E18A
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+ ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
+
+/* Section Definitions */
+SECTIONS
+{
+ .text :
+ {
+ . = ALIGN(4);
+ _sfixed = .;
+ KEEP(*(.vectors .vectors.*))
+ *(.text .text.* .gnu.linkonce.t.*)
+ *(.glue_7t) *(.glue_7)
+ *(.rodata .rodata* .gnu.linkonce.r.*)
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+ /* Support C constructors, and C destructors in both user code
+ and the C library. This also provides support for C++ code. */
+ . = ALIGN(4);
+ KEEP(*(.init))
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ . = ALIGN(4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(4);
+ KEEP(*(.fini))
+
+ . = ALIGN(4);
+ __fini_array_start = .;
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ __fini_array_end = .;
+
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+
+ . = ALIGN(4);
+ _efixed = .; /* End of text section */
+ } > ram
+
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ PROVIDE_HIDDEN (__exidx_start = .);
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > ram
+ PROVIDE_HIDDEN (__exidx_end = .);
+
+ . = ALIGN(4);
+ _etext = .;
+
+ .relocate : AT (_etext)
+ {
+ . = ALIGN(4);
+ _srelocate = .;
+ *(.ramfunc .ramfunc.*);
+ *(.data .data.*);
+ . = ALIGN(4);
+ _erelocate = .;
+ } > ram
+
+ /* .bss section which is used for uninitialized data */
+ .bss (NOLOAD) :
+ {
+ . = ALIGN(4);
+ _sbss = . ;
+ _szero = .;
+ *(.bss .bss.*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = . ;
+ _ezero = .;
+ } > ram
+
+ /* stack section */
+ .stack (NOLOAD):
+ {
+ . = ALIGN(8);
+ _sstack = .;
+ . = . + STACK_SIZE;
+ . = ALIGN(8);
+ _estack = .;
+ } > ram
+
+ . = ALIGN(4);
+ _end = . ;
+}
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21g15a_flash.ld b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21g15a_flash.ld
new file mode 100644
index 0000000000000000000000000000000000000000..a635d7408165ac03df565073c5520be5821d9eae
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21g15a_flash.ld
@@ -0,0 +1,157 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21G15A
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+ rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00008000
+ ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00001000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x400;
+
+/* Section Definitions */
+SECTIONS
+{
+ .text :
+ {
+ . = ALIGN(4);
+ _sfixed = .;
+ KEEP(*(.vectors .vectors.*))
+ *(.text .text.* .gnu.linkonce.t.*)
+ *(.glue_7t) *(.glue_7)
+ *(.rodata .rodata* .gnu.linkonce.r.*)
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+ /* Support C constructors, and C destructors in both user code
+ and the C library. This also provides support for C++ code. */
+ . = ALIGN(4);
+ KEEP(*(.init))
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ . = ALIGN(4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(4);
+ KEEP(*(.fini))
+
+ . = ALIGN(4);
+ __fini_array_start = .;
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ __fini_array_end = .;
+
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+
+ . = ALIGN(4);
+ _efixed = .; /* End of text section */
+ } > rom
+
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ PROVIDE_HIDDEN (__exidx_start = .);
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > rom
+ PROVIDE_HIDDEN (__exidx_end = .);
+
+ . = ALIGN(4);
+ _etext = .;
+
+ .relocate : AT (_etext)
+ {
+ . = ALIGN(4);
+ _srelocate = .;
+ *(.ramfunc .ramfunc.*);
+ *(.data .data.*);
+ . = ALIGN(4);
+ _erelocate = .;
+ } > ram
+
+ /* .bss section which is used for uninitialized data */
+ .bss (NOLOAD) :
+ {
+ . = ALIGN(4);
+ _sbss = . ;
+ _szero = .;
+ *(.bss .bss.*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = . ;
+ _ezero = .;
+ } > ram
+
+ /* stack section */
+ .stack (NOLOAD):
+ {
+ . = ALIGN(8);
+ _sstack = .;
+ . = . + STACK_SIZE;
+ . = ALIGN(8);
+ _estack = .;
+ } > ram
+
+ . = ALIGN(4);
+ _end = . ;
+}
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21g15a_sram.ld b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21g15a_sram.ld
new file mode 100644
index 0000000000000000000000000000000000000000..bc337068bfa3326b29815bc4bef0535f999c2225
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21g15a_sram.ld
@@ -0,0 +1,156 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21G15A
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+ ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00001000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x400;
+
+/* Section Definitions */
+SECTIONS
+{
+ .text :
+ {
+ . = ALIGN(4);
+ _sfixed = .;
+ KEEP(*(.vectors .vectors.*))
+ *(.text .text.* .gnu.linkonce.t.*)
+ *(.glue_7t) *(.glue_7)
+ *(.rodata .rodata* .gnu.linkonce.r.*)
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+ /* Support C constructors, and C destructors in both user code
+ and the C library. This also provides support for C++ code. */
+ . = ALIGN(4);
+ KEEP(*(.init))
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ . = ALIGN(4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(4);
+ KEEP(*(.fini))
+
+ . = ALIGN(4);
+ __fini_array_start = .;
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ __fini_array_end = .;
+
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+
+ . = ALIGN(4);
+ _efixed = .; /* End of text section */
+ } > ram
+
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ PROVIDE_HIDDEN (__exidx_start = .);
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > ram
+ PROVIDE_HIDDEN (__exidx_end = .);
+
+ . = ALIGN(4);
+ _etext = .;
+
+ .relocate : AT (_etext)
+ {
+ . = ALIGN(4);
+ _srelocate = .;
+ *(.ramfunc .ramfunc.*);
+ *(.data .data.*);
+ . = ALIGN(4);
+ _erelocate = .;
+ } > ram
+
+ /* .bss section which is used for uninitialized data */
+ .bss (NOLOAD) :
+ {
+ . = ALIGN(4);
+ _sbss = . ;
+ _szero = .;
+ *(.bss .bss.*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = . ;
+ _ezero = .;
+ } > ram
+
+ /* stack section */
+ .stack (NOLOAD):
+ {
+ . = ALIGN(8);
+ _sstack = .;
+ . = . + STACK_SIZE;
+ . = ALIGN(8);
+ _estack = .;
+ } > ram
+
+ . = ALIGN(4);
+ _end = . ;
+}
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21g15b_flash.ld b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21g15b_flash.ld
new file mode 100644
index 0000000000000000000000000000000000000000..788582e781f259f1cbdd068be73c10424cb6f2b4
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21g15b_flash.ld
@@ -0,0 +1,157 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21G15B
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+ rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00008000
+ ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00001000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x400;
+
+/* Section Definitions */
+SECTIONS
+{
+ .text :
+ {
+ . = ALIGN(4);
+ _sfixed = .;
+ KEEP(*(.vectors .vectors.*))
+ *(.text .text.* .gnu.linkonce.t.*)
+ *(.glue_7t) *(.glue_7)
+ *(.rodata .rodata* .gnu.linkonce.r.*)
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+ /* Support C constructors, and C destructors in both user code
+ and the C library. This also provides support for C++ code. */
+ . = ALIGN(4);
+ KEEP(*(.init))
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ . = ALIGN(4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(4);
+ KEEP(*(.fini))
+
+ . = ALIGN(4);
+ __fini_array_start = .;
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ __fini_array_end = .;
+
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+
+ . = ALIGN(4);
+ _efixed = .; /* End of text section */
+ } > rom
+
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ PROVIDE_HIDDEN (__exidx_start = .);
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > rom
+ PROVIDE_HIDDEN (__exidx_end = .);
+
+ . = ALIGN(4);
+ _etext = .;
+
+ .relocate : AT (_etext)
+ {
+ . = ALIGN(4);
+ _srelocate = .;
+ *(.ramfunc .ramfunc.*);
+ *(.data .data.*);
+ . = ALIGN(4);
+ _erelocate = .;
+ } > ram
+
+ /* .bss section which is used for uninitialized data */
+ .bss (NOLOAD) :
+ {
+ . = ALIGN(4);
+ _sbss = . ;
+ _szero = .;
+ *(.bss .bss.*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = . ;
+ _ezero = .;
+ } > ram
+
+ /* stack section */
+ .stack (NOLOAD):
+ {
+ . = ALIGN(8);
+ _sstack = .;
+ . = . + STACK_SIZE;
+ . = ALIGN(8);
+ _estack = .;
+ } > ram
+
+ . = ALIGN(4);
+ _end = . ;
+}
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21g15b_sram.ld b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21g15b_sram.ld
new file mode 100644
index 0000000000000000000000000000000000000000..3c52b0410edde91aa3ea4989523b70b38d956089
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21g15b_sram.ld
@@ -0,0 +1,156 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21G15B
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+ ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00001000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x400;
+
+/* Section Definitions */
+SECTIONS
+{
+ .text :
+ {
+ . = ALIGN(4);
+ _sfixed = .;
+ KEEP(*(.vectors .vectors.*))
+ *(.text .text.* .gnu.linkonce.t.*)
+ *(.glue_7t) *(.glue_7)
+ *(.rodata .rodata* .gnu.linkonce.r.*)
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+ /* Support C constructors, and C destructors in both user code
+ and the C library. This also provides support for C++ code. */
+ . = ALIGN(4);
+ KEEP(*(.init))
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ . = ALIGN(4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(4);
+ KEEP(*(.fini))
+
+ . = ALIGN(4);
+ __fini_array_start = .;
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ __fini_array_end = .;
+
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+
+ . = ALIGN(4);
+ _efixed = .; /* End of text section */
+ } > ram
+
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ PROVIDE_HIDDEN (__exidx_start = .);
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > ram
+ PROVIDE_HIDDEN (__exidx_end = .);
+
+ . = ALIGN(4);
+ _etext = .;
+
+ .relocate : AT (_etext)
+ {
+ . = ALIGN(4);
+ _srelocate = .;
+ *(.ramfunc .ramfunc.*);
+ *(.data .data.*);
+ . = ALIGN(4);
+ _erelocate = .;
+ } > ram
+
+ /* .bss section which is used for uninitialized data */
+ .bss (NOLOAD) :
+ {
+ . = ALIGN(4);
+ _sbss = . ;
+ _szero = .;
+ *(.bss .bss.*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = . ;
+ _ezero = .;
+ } > ram
+
+ /* stack section */
+ .stack (NOLOAD):
+ {
+ . = ALIGN(8);
+ _sstack = .;
+ . = . + STACK_SIZE;
+ . = ALIGN(8);
+ _estack = .;
+ } > ram
+
+ . = ALIGN(4);
+ _end = . ;
+}
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21g16a_flash.ld b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21g16a_flash.ld
new file mode 100644
index 0000000000000000000000000000000000000000..cf7af9eee5d99dbbb5aef0e2954a9500b46db4eb
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21g16a_flash.ld
@@ -0,0 +1,157 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21G16A
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+ rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00010000
+ ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00002000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x800;
+
+/* Section Definitions */
+SECTIONS
+{
+ .text :
+ {
+ . = ALIGN(4);
+ _sfixed = .;
+ KEEP(*(.vectors .vectors.*))
+ *(.text .text.* .gnu.linkonce.t.*)
+ *(.glue_7t) *(.glue_7)
+ *(.rodata .rodata* .gnu.linkonce.r.*)
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+ /* Support C constructors, and C destructors in both user code
+ and the C library. This also provides support for C++ code. */
+ . = ALIGN(4);
+ KEEP(*(.init))
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ . = ALIGN(4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(4);
+ KEEP(*(.fini))
+
+ . = ALIGN(4);
+ __fini_array_start = .;
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ __fini_array_end = .;
+
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+
+ . = ALIGN(4);
+ _efixed = .; /* End of text section */
+ } > rom
+
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ PROVIDE_HIDDEN (__exidx_start = .);
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > rom
+ PROVIDE_HIDDEN (__exidx_end = .);
+
+ . = ALIGN(4);
+ _etext = .;
+
+ .relocate : AT (_etext)
+ {
+ . = ALIGN(4);
+ _srelocate = .;
+ *(.ramfunc .ramfunc.*);
+ *(.data .data.*);
+ . = ALIGN(4);
+ _erelocate = .;
+ } > ram
+
+ /* .bss section which is used for uninitialized data */
+ .bss (NOLOAD) :
+ {
+ . = ALIGN(4);
+ _sbss = . ;
+ _szero = .;
+ *(.bss .bss.*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = . ;
+ _ezero = .;
+ } > ram
+
+ /* stack section */
+ .stack (NOLOAD):
+ {
+ . = ALIGN(8);
+ _sstack = .;
+ . = . + STACK_SIZE;
+ . = ALIGN(8);
+ _estack = .;
+ } > ram
+
+ . = ALIGN(4);
+ _end = . ;
+}
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21g16a_sram.ld b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21g16a_sram.ld
new file mode 100644
index 0000000000000000000000000000000000000000..fe0912fdf15e8ba6b2c81fcc9a19d51d369d113c
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21g16a_sram.ld
@@ -0,0 +1,156 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21G16A
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+ ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00002000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x800;
+
+/* Section Definitions */
+SECTIONS
+{
+ .text :
+ {
+ . = ALIGN(4);
+ _sfixed = .;
+ KEEP(*(.vectors .vectors.*))
+ *(.text .text.* .gnu.linkonce.t.*)
+ *(.glue_7t) *(.glue_7)
+ *(.rodata .rodata* .gnu.linkonce.r.*)
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+ /* Support C constructors, and C destructors in both user code
+ and the C library. This also provides support for C++ code. */
+ . = ALIGN(4);
+ KEEP(*(.init))
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ . = ALIGN(4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(4);
+ KEEP(*(.fini))
+
+ . = ALIGN(4);
+ __fini_array_start = .;
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ __fini_array_end = .;
+
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+
+ . = ALIGN(4);
+ _efixed = .; /* End of text section */
+ } > ram
+
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ PROVIDE_HIDDEN (__exidx_start = .);
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > ram
+ PROVIDE_HIDDEN (__exidx_end = .);
+
+ . = ALIGN(4);
+ _etext = .;
+
+ .relocate : AT (_etext)
+ {
+ . = ALIGN(4);
+ _srelocate = .;
+ *(.ramfunc .ramfunc.*);
+ *(.data .data.*);
+ . = ALIGN(4);
+ _erelocate = .;
+ } > ram
+
+ /* .bss section which is used for uninitialized data */
+ .bss (NOLOAD) :
+ {
+ . = ALIGN(4);
+ _sbss = . ;
+ _szero = .;
+ *(.bss .bss.*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = . ;
+ _ezero = .;
+ } > ram
+
+ /* stack section */
+ .stack (NOLOAD):
+ {
+ . = ALIGN(8);
+ _sstack = .;
+ . = . + STACK_SIZE;
+ . = ALIGN(8);
+ _estack = .;
+ } > ram
+
+ . = ALIGN(4);
+ _end = . ;
+}
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21g16b_flash.ld b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21g16b_flash.ld
new file mode 100644
index 0000000000000000000000000000000000000000..d2e6dc228741c817ca1a8c94c38a78c3e33cbab0
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21g16b_flash.ld
@@ -0,0 +1,157 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21G16B
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+ rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00010000
+ ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00002000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x800;
+
+/* Section Definitions */
+SECTIONS
+{
+ .text :
+ {
+ . = ALIGN(4);
+ _sfixed = .;
+ KEEP(*(.vectors .vectors.*))
+ *(.text .text.* .gnu.linkonce.t.*)
+ *(.glue_7t) *(.glue_7)
+ *(.rodata .rodata* .gnu.linkonce.r.*)
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+ /* Support C constructors, and C destructors in both user code
+ and the C library. This also provides support for C++ code. */
+ . = ALIGN(4);
+ KEEP(*(.init))
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ . = ALIGN(4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(4);
+ KEEP(*(.fini))
+
+ . = ALIGN(4);
+ __fini_array_start = .;
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ __fini_array_end = .;
+
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+
+ . = ALIGN(4);
+ _efixed = .; /* End of text section */
+ } > rom
+
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ PROVIDE_HIDDEN (__exidx_start = .);
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > rom
+ PROVIDE_HIDDEN (__exidx_end = .);
+
+ . = ALIGN(4);
+ _etext = .;
+
+ .relocate : AT (_etext)
+ {
+ . = ALIGN(4);
+ _srelocate = .;
+ *(.ramfunc .ramfunc.*);
+ *(.data .data.*);
+ . = ALIGN(4);
+ _erelocate = .;
+ } > ram
+
+ /* .bss section which is used for uninitialized data */
+ .bss (NOLOAD) :
+ {
+ . = ALIGN(4);
+ _sbss = . ;
+ _szero = .;
+ *(.bss .bss.*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = . ;
+ _ezero = .;
+ } > ram
+
+ /* stack section */
+ .stack (NOLOAD):
+ {
+ . = ALIGN(8);
+ _sstack = .;
+ . = . + STACK_SIZE;
+ . = ALIGN(8);
+ _estack = .;
+ } > ram
+
+ . = ALIGN(4);
+ _end = . ;
+}
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21g16b_sram.ld b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21g16b_sram.ld
new file mode 100644
index 0000000000000000000000000000000000000000..cff172eb9647c3bf672183565f7ae056cd7d2055
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21g16b_sram.ld
@@ -0,0 +1,156 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21G16B
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+ ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00002000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x800;
+
+/* Section Definitions */
+SECTIONS
+{
+ .text :
+ {
+ . = ALIGN(4);
+ _sfixed = .;
+ KEEP(*(.vectors .vectors.*))
+ *(.text .text.* .gnu.linkonce.t.*)
+ *(.glue_7t) *(.glue_7)
+ *(.rodata .rodata* .gnu.linkonce.r.*)
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+ /* Support C constructors, and C destructors in both user code
+ and the C library. This also provides support for C++ code. */
+ . = ALIGN(4);
+ KEEP(*(.init))
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ . = ALIGN(4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(4);
+ KEEP(*(.fini))
+
+ . = ALIGN(4);
+ __fini_array_start = .;
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ __fini_array_end = .;
+
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+
+ . = ALIGN(4);
+ _efixed = .; /* End of text section */
+ } > ram
+
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ PROVIDE_HIDDEN (__exidx_start = .);
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > ram
+ PROVIDE_HIDDEN (__exidx_end = .);
+
+ . = ALIGN(4);
+ _etext = .;
+
+ .relocate : AT (_etext)
+ {
+ . = ALIGN(4);
+ _srelocate = .;
+ *(.ramfunc .ramfunc.*);
+ *(.data .data.*);
+ . = ALIGN(4);
+ _erelocate = .;
+ } > ram
+
+ /* .bss section which is used for uninitialized data */
+ .bss (NOLOAD) :
+ {
+ . = ALIGN(4);
+ _sbss = . ;
+ _szero = .;
+ *(.bss .bss.*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = . ;
+ _ezero = .;
+ } > ram
+
+ /* stack section */
+ .stack (NOLOAD):
+ {
+ . = ALIGN(8);
+ _sstack = .;
+ . = . + STACK_SIZE;
+ . = ALIGN(8);
+ _estack = .;
+ } > ram
+
+ . = ALIGN(4);
+ _end = . ;
+}
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21g17a_flash.ld b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21g17a_flash.ld
new file mode 100644
index 0000000000000000000000000000000000000000..9be36dda493f70ea72a3dc847b73d8422b029e65
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21g17a_flash.ld
@@ -0,0 +1,157 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21G17A
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+ rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00020000
+ ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00004000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x1000;
+
+/* Section Definitions */
+SECTIONS
+{
+ .text :
+ {
+ . = ALIGN(4);
+ _sfixed = .;
+ KEEP(*(.vectors .vectors.*))
+ *(.text .text.* .gnu.linkonce.t.*)
+ *(.glue_7t) *(.glue_7)
+ *(.rodata .rodata* .gnu.linkonce.r.*)
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+ /* Support C constructors, and C destructors in both user code
+ and the C library. This also provides support for C++ code. */
+ . = ALIGN(4);
+ KEEP(*(.init))
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ . = ALIGN(4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(4);
+ KEEP(*(.fini))
+
+ . = ALIGN(4);
+ __fini_array_start = .;
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ __fini_array_end = .;
+
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+
+ . = ALIGN(4);
+ _efixed = .; /* End of text section */
+ } > rom
+
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ PROVIDE_HIDDEN (__exidx_start = .);
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > rom
+ PROVIDE_HIDDEN (__exidx_end = .);
+
+ . = ALIGN(4);
+ _etext = .;
+
+ .relocate : AT (_etext)
+ {
+ . = ALIGN(4);
+ _srelocate = .;
+ *(.ramfunc .ramfunc.*);
+ *(.data .data.*);
+ . = ALIGN(4);
+ _erelocate = .;
+ } > ram
+
+ /* .bss section which is used for uninitialized data */
+ .bss (NOLOAD) :
+ {
+ . = ALIGN(4);
+ _sbss = . ;
+ _szero = .;
+ *(.bss .bss.*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = . ;
+ _ezero = .;
+ } > ram
+
+ /* stack section */
+ .stack (NOLOAD):
+ {
+ . = ALIGN(8);
+ _sstack = .;
+ . = . + STACK_SIZE;
+ . = ALIGN(8);
+ _estack = .;
+ } > ram
+
+ . = ALIGN(4);
+ _end = . ;
+}
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21g17a_sram.ld b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21g17a_sram.ld
new file mode 100644
index 0000000000000000000000000000000000000000..6ff7eb9e7c49d26f8fb9e1ec0edc8c09f61082e0
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21g17a_sram.ld
@@ -0,0 +1,156 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21G17A
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+ ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00004000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x1000;
+
+/* Section Definitions */
+SECTIONS
+{
+ .text :
+ {
+ . = ALIGN(4);
+ _sfixed = .;
+ KEEP(*(.vectors .vectors.*))
+ *(.text .text.* .gnu.linkonce.t.*)
+ *(.glue_7t) *(.glue_7)
+ *(.rodata .rodata* .gnu.linkonce.r.*)
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+ /* Support C constructors, and C destructors in both user code
+ and the C library. This also provides support for C++ code. */
+ . = ALIGN(4);
+ KEEP(*(.init))
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ . = ALIGN(4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(4);
+ KEEP(*(.fini))
+
+ . = ALIGN(4);
+ __fini_array_start = .;
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ __fini_array_end = .;
+
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+
+ . = ALIGN(4);
+ _efixed = .; /* End of text section */
+ } > ram
+
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ PROVIDE_HIDDEN (__exidx_start = .);
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > ram
+ PROVIDE_HIDDEN (__exidx_end = .);
+
+ . = ALIGN(4);
+ _etext = .;
+
+ .relocate : AT (_etext)
+ {
+ . = ALIGN(4);
+ _srelocate = .;
+ *(.ramfunc .ramfunc.*);
+ *(.data .data.*);
+ . = ALIGN(4);
+ _erelocate = .;
+ } > ram
+
+ /* .bss section which is used for uninitialized data */
+ .bss (NOLOAD) :
+ {
+ . = ALIGN(4);
+ _sbss = . ;
+ _szero = .;
+ *(.bss .bss.*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = . ;
+ _ezero = .;
+ } > ram
+
+ /* stack section */
+ .stack (NOLOAD):
+ {
+ . = ALIGN(8);
+ _sstack = .;
+ . = . + STACK_SIZE;
+ . = ALIGN(8);
+ _estack = .;
+ } > ram
+
+ . = ALIGN(4);
+ _end = . ;
+}
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21g17au_flash.ld b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21g17au_flash.ld
new file mode 100644
index 0000000000000000000000000000000000000000..446635f7e5b4b826c992949295795ba74dfb8d62
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21g17au_flash.ld
@@ -0,0 +1,157 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21G17AU
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+ rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00020000
+ ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00004000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x1000;
+
+/* Section Definitions */
+SECTIONS
+{
+ .text :
+ {
+ . = ALIGN(4);
+ _sfixed = .;
+ KEEP(*(.vectors .vectors.*))
+ *(.text .text.* .gnu.linkonce.t.*)
+ *(.glue_7t) *(.glue_7)
+ *(.rodata .rodata* .gnu.linkonce.r.*)
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+ /* Support C constructors, and C destructors in both user code
+ and the C library. This also provides support for C++ code. */
+ . = ALIGN(4);
+ KEEP(*(.init))
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ . = ALIGN(4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(4);
+ KEEP(*(.fini))
+
+ . = ALIGN(4);
+ __fini_array_start = .;
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ __fini_array_end = .;
+
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+
+ . = ALIGN(4);
+ _efixed = .; /* End of text section */
+ } > rom
+
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ PROVIDE_HIDDEN (__exidx_start = .);
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > rom
+ PROVIDE_HIDDEN (__exidx_end = .);
+
+ . = ALIGN(4);
+ _etext = .;
+
+ .relocate : AT (_etext)
+ {
+ . = ALIGN(4);
+ _srelocate = .;
+ *(.ramfunc .ramfunc.*);
+ *(.data .data.*);
+ . = ALIGN(4);
+ _erelocate = .;
+ } > ram
+
+ /* .bss section which is used for uninitialized data */
+ .bss (NOLOAD) :
+ {
+ . = ALIGN(4);
+ _sbss = . ;
+ _szero = .;
+ *(.bss .bss.*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = . ;
+ _ezero = .;
+ } > ram
+
+ /* stack section */
+ .stack (NOLOAD):
+ {
+ . = ALIGN(8);
+ _sstack = .;
+ . = . + STACK_SIZE;
+ . = ALIGN(8);
+ _estack = .;
+ } > ram
+
+ . = ALIGN(4);
+ _end = . ;
+}
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21g17au_sram.ld b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21g17au_sram.ld
new file mode 100644
index 0000000000000000000000000000000000000000..19be3614d56fcc25021db0d8f77cb50e03b8dd5c
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21g17au_sram.ld
@@ -0,0 +1,156 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21G17AU
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+ ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00004000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x1000;
+
+/* Section Definitions */
+SECTIONS
+{
+ .text :
+ {
+ . = ALIGN(4);
+ _sfixed = .;
+ KEEP(*(.vectors .vectors.*))
+ *(.text .text.* .gnu.linkonce.t.*)
+ *(.glue_7t) *(.glue_7)
+ *(.rodata .rodata* .gnu.linkonce.r.*)
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+ /* Support C constructors, and C destructors in both user code
+ and the C library. This also provides support for C++ code. */
+ . = ALIGN(4);
+ KEEP(*(.init))
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ . = ALIGN(4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(4);
+ KEEP(*(.fini))
+
+ . = ALIGN(4);
+ __fini_array_start = .;
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ __fini_array_end = .;
+
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+
+ . = ALIGN(4);
+ _efixed = .; /* End of text section */
+ } > ram
+
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ PROVIDE_HIDDEN (__exidx_start = .);
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > ram
+ PROVIDE_HIDDEN (__exidx_end = .);
+
+ . = ALIGN(4);
+ _etext = .;
+
+ .relocate : AT (_etext)
+ {
+ . = ALIGN(4);
+ _srelocate = .;
+ *(.ramfunc .ramfunc.*);
+ *(.data .data.*);
+ . = ALIGN(4);
+ _erelocate = .;
+ } > ram
+
+ /* .bss section which is used for uninitialized data */
+ .bss (NOLOAD) :
+ {
+ . = ALIGN(4);
+ _sbss = . ;
+ _szero = .;
+ *(.bss .bss.*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = . ;
+ _ezero = .;
+ } > ram
+
+ /* stack section */
+ .stack (NOLOAD):
+ {
+ . = ALIGN(8);
+ _sstack = .;
+ . = . + STACK_SIZE;
+ . = ALIGN(8);
+ _estack = .;
+ } > ram
+
+ . = ALIGN(4);
+ _end = . ;
+}
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21g18a_flash.ld b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21g18a_flash.ld
new file mode 100644
index 0000000000000000000000000000000000000000..6c753a87c6ec2129219564b855c40b4da25cf1d7
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21g18a_flash.ld
@@ -0,0 +1,157 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21G18A
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+ rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000
+ ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
+
+/* Section Definitions */
+SECTIONS
+{
+ .text :
+ {
+ . = ALIGN(4);
+ _sfixed = .;
+ KEEP(*(.vectors .vectors.*))
+ *(.text .text.* .gnu.linkonce.t.*)
+ *(.glue_7t) *(.glue_7)
+ *(.rodata .rodata* .gnu.linkonce.r.*)
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+ /* Support C constructors, and C destructors in both user code
+ and the C library. This also provides support for C++ code. */
+ . = ALIGN(4);
+ KEEP(*(.init))
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ . = ALIGN(4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(4);
+ KEEP(*(.fini))
+
+ . = ALIGN(4);
+ __fini_array_start = .;
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ __fini_array_end = .;
+
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+
+ . = ALIGN(4);
+ _efixed = .; /* End of text section */
+ } > rom
+
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ PROVIDE_HIDDEN (__exidx_start = .);
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > rom
+ PROVIDE_HIDDEN (__exidx_end = .);
+
+ . = ALIGN(4);
+ _etext = .;
+
+ .relocate : AT (_etext)
+ {
+ . = ALIGN(4);
+ _srelocate = .;
+ *(.ramfunc .ramfunc.*);
+ *(.data .data.*);
+ . = ALIGN(4);
+ _erelocate = .;
+ } > ram
+
+ /* .bss section which is used for uninitialized data */
+ .bss (NOLOAD) :
+ {
+ . = ALIGN(4);
+ _sbss = . ;
+ _szero = .;
+ *(.bss .bss.*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = . ;
+ _ezero = .;
+ } > ram
+
+ /* stack section */
+ .stack (NOLOAD):
+ {
+ . = ALIGN(8);
+ _sstack = .;
+ . = . + STACK_SIZE;
+ . = ALIGN(8);
+ _estack = .;
+ } > ram
+
+ . = ALIGN(4);
+ _end = . ;
+}
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21g18a_sram.ld b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21g18a_sram.ld
new file mode 100644
index 0000000000000000000000000000000000000000..00ee6356571a8f1fa37e8db742c16223cff9d27e
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21g18a_sram.ld
@@ -0,0 +1,156 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21G18A
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+ ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
+
+/* Section Definitions */
+SECTIONS
+{
+ .text :
+ {
+ . = ALIGN(4);
+ _sfixed = .;
+ KEEP(*(.vectors .vectors.*))
+ *(.text .text.* .gnu.linkonce.t.*)
+ *(.glue_7t) *(.glue_7)
+ *(.rodata .rodata* .gnu.linkonce.r.*)
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+ /* Support C constructors, and C destructors in both user code
+ and the C library. This also provides support for C++ code. */
+ . = ALIGN(4);
+ KEEP(*(.init))
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ . = ALIGN(4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(4);
+ KEEP(*(.fini))
+
+ . = ALIGN(4);
+ __fini_array_start = .;
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ __fini_array_end = .;
+
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+
+ . = ALIGN(4);
+ _efixed = .; /* End of text section */
+ } > ram
+
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ PROVIDE_HIDDEN (__exidx_start = .);
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > ram
+ PROVIDE_HIDDEN (__exidx_end = .);
+
+ . = ALIGN(4);
+ _etext = .;
+
+ .relocate : AT (_etext)
+ {
+ . = ALIGN(4);
+ _srelocate = .;
+ *(.ramfunc .ramfunc.*);
+ *(.data .data.*);
+ . = ALIGN(4);
+ _erelocate = .;
+ } > ram
+
+ /* .bss section which is used for uninitialized data */
+ .bss (NOLOAD) :
+ {
+ . = ALIGN(4);
+ _sbss = . ;
+ _szero = .;
+ *(.bss .bss.*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = . ;
+ _ezero = .;
+ } > ram
+
+ /* stack section */
+ .stack (NOLOAD):
+ {
+ . = ALIGN(8);
+ _sstack = .;
+ . = . + STACK_SIZE;
+ . = ALIGN(8);
+ _estack = .;
+ } > ram
+
+ . = ALIGN(4);
+ _end = . ;
+}
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21g18au_flash.ld b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21g18au_flash.ld
new file mode 100644
index 0000000000000000000000000000000000000000..ad5966bd09ce0933b76a30a1e7ce18835eee1936
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21g18au_flash.ld
@@ -0,0 +1,157 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21G18AU
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+ rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000
+ ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
+
+/* Section Definitions */
+SECTIONS
+{
+ .text :
+ {
+ . = ALIGN(4);
+ _sfixed = .;
+ KEEP(*(.vectors .vectors.*))
+ *(.text .text.* .gnu.linkonce.t.*)
+ *(.glue_7t) *(.glue_7)
+ *(.rodata .rodata* .gnu.linkonce.r.*)
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+ /* Support C constructors, and C destructors in both user code
+ and the C library. This also provides support for C++ code. */
+ . = ALIGN(4);
+ KEEP(*(.init))
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ . = ALIGN(4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(4);
+ KEEP(*(.fini))
+
+ . = ALIGN(4);
+ __fini_array_start = .;
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ __fini_array_end = .;
+
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+
+ . = ALIGN(4);
+ _efixed = .; /* End of text section */
+ } > rom
+
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ PROVIDE_HIDDEN (__exidx_start = .);
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > rom
+ PROVIDE_HIDDEN (__exidx_end = .);
+
+ . = ALIGN(4);
+ _etext = .;
+
+ .relocate : AT (_etext)
+ {
+ . = ALIGN(4);
+ _srelocate = .;
+ *(.ramfunc .ramfunc.*);
+ *(.data .data.*);
+ . = ALIGN(4);
+ _erelocate = .;
+ } > ram
+
+ /* .bss section which is used for uninitialized data */
+ .bss (NOLOAD) :
+ {
+ . = ALIGN(4);
+ _sbss = . ;
+ _szero = .;
+ *(.bss .bss.*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = . ;
+ _ezero = .;
+ } > ram
+
+ /* stack section */
+ .stack (NOLOAD):
+ {
+ . = ALIGN(8);
+ _sstack = .;
+ . = . + STACK_SIZE;
+ . = ALIGN(8);
+ _estack = .;
+ } > ram
+
+ . = ALIGN(4);
+ _end = . ;
+}
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21g18au_sram.ld b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21g18au_sram.ld
new file mode 100644
index 0000000000000000000000000000000000000000..03959a01e0f9b2d8561c9b9d9ba733fef8ceb022
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21g18au_sram.ld
@@ -0,0 +1,156 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21G18AU
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+ ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
+
+/* Section Definitions */
+SECTIONS
+{
+ .text :
+ {
+ . = ALIGN(4);
+ _sfixed = .;
+ KEEP(*(.vectors .vectors.*))
+ *(.text .text.* .gnu.linkonce.t.*)
+ *(.glue_7t) *(.glue_7)
+ *(.rodata .rodata* .gnu.linkonce.r.*)
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+ /* Support C constructors, and C destructors in both user code
+ and the C library. This also provides support for C++ code. */
+ . = ALIGN(4);
+ KEEP(*(.init))
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ . = ALIGN(4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(4);
+ KEEP(*(.fini))
+
+ . = ALIGN(4);
+ __fini_array_start = .;
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ __fini_array_end = .;
+
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+
+ . = ALIGN(4);
+ _efixed = .; /* End of text section */
+ } > ram
+
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ PROVIDE_HIDDEN (__exidx_start = .);
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > ram
+ PROVIDE_HIDDEN (__exidx_end = .);
+
+ . = ALIGN(4);
+ _etext = .;
+
+ .relocate : AT (_etext)
+ {
+ . = ALIGN(4);
+ _srelocate = .;
+ *(.ramfunc .ramfunc.*);
+ *(.data .data.*);
+ . = ALIGN(4);
+ _erelocate = .;
+ } > ram
+
+ /* .bss section which is used for uninitialized data */
+ .bss (NOLOAD) :
+ {
+ . = ALIGN(4);
+ _sbss = . ;
+ _szero = .;
+ *(.bss .bss.*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = . ;
+ _ezero = .;
+ } > ram
+
+ /* stack section */
+ .stack (NOLOAD):
+ {
+ . = ALIGN(8);
+ _sstack = .;
+ . = . + STACK_SIZE;
+ . = ALIGN(8);
+ _estack = .;
+ } > ram
+
+ . = ALIGN(4);
+ _end = . ;
+}
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21j15a_flash.ld b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21j15a_flash.ld
new file mode 100644
index 0000000000000000000000000000000000000000..762c5c50d5531c26b1ebdea53b4bf5e1d0e6f54d
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21j15a_flash.ld
@@ -0,0 +1,157 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21J15A
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+ rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00008000
+ ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00001000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x400;
+
+/* Section Definitions */
+SECTIONS
+{
+ .text :
+ {
+ . = ALIGN(4);
+ _sfixed = .;
+ KEEP(*(.vectors .vectors.*))
+ *(.text .text.* .gnu.linkonce.t.*)
+ *(.glue_7t) *(.glue_7)
+ *(.rodata .rodata* .gnu.linkonce.r.*)
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+ /* Support C constructors, and C destructors in both user code
+ and the C library. This also provides support for C++ code. */
+ . = ALIGN(4);
+ KEEP(*(.init))
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ . = ALIGN(4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(4);
+ KEEP(*(.fini))
+
+ . = ALIGN(4);
+ __fini_array_start = .;
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ __fini_array_end = .;
+
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+
+ . = ALIGN(4);
+ _efixed = .; /* End of text section */
+ } > rom
+
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ PROVIDE_HIDDEN (__exidx_start = .);
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > rom
+ PROVIDE_HIDDEN (__exidx_end = .);
+
+ . = ALIGN(4);
+ _etext = .;
+
+ .relocate : AT (_etext)
+ {
+ . = ALIGN(4);
+ _srelocate = .;
+ *(.ramfunc .ramfunc.*);
+ *(.data .data.*);
+ . = ALIGN(4);
+ _erelocate = .;
+ } > ram
+
+ /* .bss section which is used for uninitialized data */
+ .bss (NOLOAD) :
+ {
+ . = ALIGN(4);
+ _sbss = . ;
+ _szero = .;
+ *(.bss .bss.*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = . ;
+ _ezero = .;
+ } > ram
+
+ /* stack section */
+ .stack (NOLOAD):
+ {
+ . = ALIGN(8);
+ _sstack = .;
+ . = . + STACK_SIZE;
+ . = ALIGN(8);
+ _estack = .;
+ } > ram
+
+ . = ALIGN(4);
+ _end = . ;
+}
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21j15a_sram.ld b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21j15a_sram.ld
new file mode 100644
index 0000000000000000000000000000000000000000..2b1a86281c3f30c1a614873ea5e2622c4c7a53f1
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21j15a_sram.ld
@@ -0,0 +1,156 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21J15A
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+ ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00001000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x400;
+
+/* Section Definitions */
+SECTIONS
+{
+ .text :
+ {
+ . = ALIGN(4);
+ _sfixed = .;
+ KEEP(*(.vectors .vectors.*))
+ *(.text .text.* .gnu.linkonce.t.*)
+ *(.glue_7t) *(.glue_7)
+ *(.rodata .rodata* .gnu.linkonce.r.*)
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+ /* Support C constructors, and C destructors in both user code
+ and the C library. This also provides support for C++ code. */
+ . = ALIGN(4);
+ KEEP(*(.init))
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ . = ALIGN(4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(4);
+ KEEP(*(.fini))
+
+ . = ALIGN(4);
+ __fini_array_start = .;
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ __fini_array_end = .;
+
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+
+ . = ALIGN(4);
+ _efixed = .; /* End of text section */
+ } > ram
+
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ PROVIDE_HIDDEN (__exidx_start = .);
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > ram
+ PROVIDE_HIDDEN (__exidx_end = .);
+
+ . = ALIGN(4);
+ _etext = .;
+
+ .relocate : AT (_etext)
+ {
+ . = ALIGN(4);
+ _srelocate = .;
+ *(.ramfunc .ramfunc.*);
+ *(.data .data.*);
+ . = ALIGN(4);
+ _erelocate = .;
+ } > ram
+
+ /* .bss section which is used for uninitialized data */
+ .bss (NOLOAD) :
+ {
+ . = ALIGN(4);
+ _sbss = . ;
+ _szero = .;
+ *(.bss .bss.*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = . ;
+ _ezero = .;
+ } > ram
+
+ /* stack section */
+ .stack (NOLOAD):
+ {
+ . = ALIGN(8);
+ _sstack = .;
+ . = . + STACK_SIZE;
+ . = ALIGN(8);
+ _estack = .;
+ } > ram
+
+ . = ALIGN(4);
+ _end = . ;
+}
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21j15b_flash.ld b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21j15b_flash.ld
new file mode 100644
index 0000000000000000000000000000000000000000..1515dd6bd92f6c400bd07c1fb9f3917910525f08
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21j15b_flash.ld
@@ -0,0 +1,157 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21J15B
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+ rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00008000
+ ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00001000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x400;
+
+/* Section Definitions */
+SECTIONS
+{
+ .text :
+ {
+ . = ALIGN(4);
+ _sfixed = .;
+ KEEP(*(.vectors .vectors.*))
+ *(.text .text.* .gnu.linkonce.t.*)
+ *(.glue_7t) *(.glue_7)
+ *(.rodata .rodata* .gnu.linkonce.r.*)
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+ /* Support C constructors, and C destructors in both user code
+ and the C library. This also provides support for C++ code. */
+ . = ALIGN(4);
+ KEEP(*(.init))
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ . = ALIGN(4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(4);
+ KEEP(*(.fini))
+
+ . = ALIGN(4);
+ __fini_array_start = .;
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ __fini_array_end = .;
+
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+
+ . = ALIGN(4);
+ _efixed = .; /* End of text section */
+ } > rom
+
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ PROVIDE_HIDDEN (__exidx_start = .);
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > rom
+ PROVIDE_HIDDEN (__exidx_end = .);
+
+ . = ALIGN(4);
+ _etext = .;
+
+ .relocate : AT (_etext)
+ {
+ . = ALIGN(4);
+ _srelocate = .;
+ *(.ramfunc .ramfunc.*);
+ *(.data .data.*);
+ . = ALIGN(4);
+ _erelocate = .;
+ } > ram
+
+ /* .bss section which is used for uninitialized data */
+ .bss (NOLOAD) :
+ {
+ . = ALIGN(4);
+ _sbss = . ;
+ _szero = .;
+ *(.bss .bss.*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = . ;
+ _ezero = .;
+ } > ram
+
+ /* stack section */
+ .stack (NOLOAD):
+ {
+ . = ALIGN(8);
+ _sstack = .;
+ . = . + STACK_SIZE;
+ . = ALIGN(8);
+ _estack = .;
+ } > ram
+
+ . = ALIGN(4);
+ _end = . ;
+}
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21j15b_sram.ld b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21j15b_sram.ld
new file mode 100644
index 0000000000000000000000000000000000000000..dac8b0996d54ec3fa254abe0b0934f1abf90b508
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21j15b_sram.ld
@@ -0,0 +1,156 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21J15B
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+ ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00001000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x400;
+
+/* Section Definitions */
+SECTIONS
+{
+ .text :
+ {
+ . = ALIGN(4);
+ _sfixed = .;
+ KEEP(*(.vectors .vectors.*))
+ *(.text .text.* .gnu.linkonce.t.*)
+ *(.glue_7t) *(.glue_7)
+ *(.rodata .rodata* .gnu.linkonce.r.*)
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+ /* Support C constructors, and C destructors in both user code
+ and the C library. This also provides support for C++ code. */
+ . = ALIGN(4);
+ KEEP(*(.init))
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ . = ALIGN(4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(4);
+ KEEP(*(.fini))
+
+ . = ALIGN(4);
+ __fini_array_start = .;
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ __fini_array_end = .;
+
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+
+ . = ALIGN(4);
+ _efixed = .; /* End of text section */
+ } > ram
+
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ PROVIDE_HIDDEN (__exidx_start = .);
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > ram
+ PROVIDE_HIDDEN (__exidx_end = .);
+
+ . = ALIGN(4);
+ _etext = .;
+
+ .relocate : AT (_etext)
+ {
+ . = ALIGN(4);
+ _srelocate = .;
+ *(.ramfunc .ramfunc.*);
+ *(.data .data.*);
+ . = ALIGN(4);
+ _erelocate = .;
+ } > ram
+
+ /* .bss section which is used for uninitialized data */
+ .bss (NOLOAD) :
+ {
+ . = ALIGN(4);
+ _sbss = . ;
+ _szero = .;
+ *(.bss .bss.*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = . ;
+ _ezero = .;
+ } > ram
+
+ /* stack section */
+ .stack (NOLOAD):
+ {
+ . = ALIGN(8);
+ _sstack = .;
+ . = . + STACK_SIZE;
+ . = ALIGN(8);
+ _estack = .;
+ } > ram
+
+ . = ALIGN(4);
+ _end = . ;
+}
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21j16a_flash.ld b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21j16a_flash.ld
new file mode 100644
index 0000000000000000000000000000000000000000..05aef488956cc61d5ed204081dea61c585a1a893
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21j16a_flash.ld
@@ -0,0 +1,157 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21J16A
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+ rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00010000
+ ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00002000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x800;
+
+/* Section Definitions */
+SECTIONS
+{
+ .text :
+ {
+ . = ALIGN(4);
+ _sfixed = .;
+ KEEP(*(.vectors .vectors.*))
+ *(.text .text.* .gnu.linkonce.t.*)
+ *(.glue_7t) *(.glue_7)
+ *(.rodata .rodata* .gnu.linkonce.r.*)
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+ /* Support C constructors, and C destructors in both user code
+ and the C library. This also provides support for C++ code. */
+ . = ALIGN(4);
+ KEEP(*(.init))
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ . = ALIGN(4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(4);
+ KEEP(*(.fini))
+
+ . = ALIGN(4);
+ __fini_array_start = .;
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ __fini_array_end = .;
+
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+
+ . = ALIGN(4);
+ _efixed = .; /* End of text section */
+ } > rom
+
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ PROVIDE_HIDDEN (__exidx_start = .);
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > rom
+ PROVIDE_HIDDEN (__exidx_end = .);
+
+ . = ALIGN(4);
+ _etext = .;
+
+ .relocate : AT (_etext)
+ {
+ . = ALIGN(4);
+ _srelocate = .;
+ *(.ramfunc .ramfunc.*);
+ *(.data .data.*);
+ . = ALIGN(4);
+ _erelocate = .;
+ } > ram
+
+ /* .bss section which is used for uninitialized data */
+ .bss (NOLOAD) :
+ {
+ . = ALIGN(4);
+ _sbss = . ;
+ _szero = .;
+ *(.bss .bss.*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = . ;
+ _ezero = .;
+ } > ram
+
+ /* stack section */
+ .stack (NOLOAD):
+ {
+ . = ALIGN(8);
+ _sstack = .;
+ . = . + STACK_SIZE;
+ . = ALIGN(8);
+ _estack = .;
+ } > ram
+
+ . = ALIGN(4);
+ _end = . ;
+}
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21j16a_sram.ld b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21j16a_sram.ld
new file mode 100644
index 0000000000000000000000000000000000000000..d245d9ce033ce15d1cd9aed5ba5ae0aa657d03ee
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21j16a_sram.ld
@@ -0,0 +1,156 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21J16A
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+ ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00002000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x800;
+
+/* Section Definitions */
+SECTIONS
+{
+ .text :
+ {
+ . = ALIGN(4);
+ _sfixed = .;
+ KEEP(*(.vectors .vectors.*))
+ *(.text .text.* .gnu.linkonce.t.*)
+ *(.glue_7t) *(.glue_7)
+ *(.rodata .rodata* .gnu.linkonce.r.*)
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+ /* Support C constructors, and C destructors in both user code
+ and the C library. This also provides support for C++ code. */
+ . = ALIGN(4);
+ KEEP(*(.init))
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ . = ALIGN(4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(4);
+ KEEP(*(.fini))
+
+ . = ALIGN(4);
+ __fini_array_start = .;
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ __fini_array_end = .;
+
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+
+ . = ALIGN(4);
+ _efixed = .; /* End of text section */
+ } > ram
+
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ PROVIDE_HIDDEN (__exidx_start = .);
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > ram
+ PROVIDE_HIDDEN (__exidx_end = .);
+
+ . = ALIGN(4);
+ _etext = .;
+
+ .relocate : AT (_etext)
+ {
+ . = ALIGN(4);
+ _srelocate = .;
+ *(.ramfunc .ramfunc.*);
+ *(.data .data.*);
+ . = ALIGN(4);
+ _erelocate = .;
+ } > ram
+
+ /* .bss section which is used for uninitialized data */
+ .bss (NOLOAD) :
+ {
+ . = ALIGN(4);
+ _sbss = . ;
+ _szero = .;
+ *(.bss .bss.*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = . ;
+ _ezero = .;
+ } > ram
+
+ /* stack section */
+ .stack (NOLOAD):
+ {
+ . = ALIGN(8);
+ _sstack = .;
+ . = . + STACK_SIZE;
+ . = ALIGN(8);
+ _estack = .;
+ } > ram
+
+ . = ALIGN(4);
+ _end = . ;
+}
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21j16b_flash.ld b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21j16b_flash.ld
new file mode 100644
index 0000000000000000000000000000000000000000..95b3ace3aff52fc1935575a6b56e205283fe02e0
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21j16b_flash.ld
@@ -0,0 +1,157 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21J16B
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+ rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00010000
+ ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00002000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x800;
+
+/* Section Definitions */
+SECTIONS
+{
+ .text :
+ {
+ . = ALIGN(4);
+ _sfixed = .;
+ KEEP(*(.vectors .vectors.*))
+ *(.text .text.* .gnu.linkonce.t.*)
+ *(.glue_7t) *(.glue_7)
+ *(.rodata .rodata* .gnu.linkonce.r.*)
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+ /* Support C constructors, and C destructors in both user code
+ and the C library. This also provides support for C++ code. */
+ . = ALIGN(4);
+ KEEP(*(.init))
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ . = ALIGN(4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(4);
+ KEEP(*(.fini))
+
+ . = ALIGN(4);
+ __fini_array_start = .;
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ __fini_array_end = .;
+
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+
+ . = ALIGN(4);
+ _efixed = .; /* End of text section */
+ } > rom
+
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ PROVIDE_HIDDEN (__exidx_start = .);
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > rom
+ PROVIDE_HIDDEN (__exidx_end = .);
+
+ . = ALIGN(4);
+ _etext = .;
+
+ .relocate : AT (_etext)
+ {
+ . = ALIGN(4);
+ _srelocate = .;
+ *(.ramfunc .ramfunc.*);
+ *(.data .data.*);
+ . = ALIGN(4);
+ _erelocate = .;
+ } > ram
+
+ /* .bss section which is used for uninitialized data */
+ .bss (NOLOAD) :
+ {
+ . = ALIGN(4);
+ _sbss = . ;
+ _szero = .;
+ *(.bss .bss.*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = . ;
+ _ezero = .;
+ } > ram
+
+ /* stack section */
+ .stack (NOLOAD):
+ {
+ . = ALIGN(8);
+ _sstack = .;
+ . = . + STACK_SIZE;
+ . = ALIGN(8);
+ _estack = .;
+ } > ram
+
+ . = ALIGN(4);
+ _end = . ;
+}
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21j16b_sram.ld b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21j16b_sram.ld
new file mode 100644
index 0000000000000000000000000000000000000000..7ea27fd32f7d62eac03f761216dfbb0796a7824a
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21j16b_sram.ld
@@ -0,0 +1,156 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21J16B
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+ ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00002000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x800;
+
+/* Section Definitions */
+SECTIONS
+{
+ .text :
+ {
+ . = ALIGN(4);
+ _sfixed = .;
+ KEEP(*(.vectors .vectors.*))
+ *(.text .text.* .gnu.linkonce.t.*)
+ *(.glue_7t) *(.glue_7)
+ *(.rodata .rodata* .gnu.linkonce.r.*)
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+ /* Support C constructors, and C destructors in both user code
+ and the C library. This also provides support for C++ code. */
+ . = ALIGN(4);
+ KEEP(*(.init))
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ . = ALIGN(4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(4);
+ KEEP(*(.fini))
+
+ . = ALIGN(4);
+ __fini_array_start = .;
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ __fini_array_end = .;
+
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+
+ . = ALIGN(4);
+ _efixed = .; /* End of text section */
+ } > ram
+
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ PROVIDE_HIDDEN (__exidx_start = .);
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > ram
+ PROVIDE_HIDDEN (__exidx_end = .);
+
+ . = ALIGN(4);
+ _etext = .;
+
+ .relocate : AT (_etext)
+ {
+ . = ALIGN(4);
+ _srelocate = .;
+ *(.ramfunc .ramfunc.*);
+ *(.data .data.*);
+ . = ALIGN(4);
+ _erelocate = .;
+ } > ram
+
+ /* .bss section which is used for uninitialized data */
+ .bss (NOLOAD) :
+ {
+ . = ALIGN(4);
+ _sbss = . ;
+ _szero = .;
+ *(.bss .bss.*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = . ;
+ _ezero = .;
+ } > ram
+
+ /* stack section */
+ .stack (NOLOAD):
+ {
+ . = ALIGN(8);
+ _sstack = .;
+ . = . + STACK_SIZE;
+ . = ALIGN(8);
+ _estack = .;
+ } > ram
+
+ . = ALIGN(4);
+ _end = . ;
+}
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21j17a_flash.ld b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21j17a_flash.ld
new file mode 100644
index 0000000000000000000000000000000000000000..145d10ad3d4efe428640de955d7687de9d5b7620
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21j17a_flash.ld
@@ -0,0 +1,157 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21J17A
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+ rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00020000
+ ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00004000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x1000;
+
+/* Section Definitions */
+SECTIONS
+{
+ .text :
+ {
+ . = ALIGN(4);
+ _sfixed = .;
+ KEEP(*(.vectors .vectors.*))
+ *(.text .text.* .gnu.linkonce.t.*)
+ *(.glue_7t) *(.glue_7)
+ *(.rodata .rodata* .gnu.linkonce.r.*)
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+ /* Support C constructors, and C destructors in both user code
+ and the C library. This also provides support for C++ code. */
+ . = ALIGN(4);
+ KEEP(*(.init))
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ . = ALIGN(4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(4);
+ KEEP(*(.fini))
+
+ . = ALIGN(4);
+ __fini_array_start = .;
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ __fini_array_end = .;
+
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+
+ . = ALIGN(4);
+ _efixed = .; /* End of text section */
+ } > rom
+
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ PROVIDE_HIDDEN (__exidx_start = .);
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > rom
+ PROVIDE_HIDDEN (__exidx_end = .);
+
+ . = ALIGN(4);
+ _etext = .;
+
+ .relocate : AT (_etext)
+ {
+ . = ALIGN(4);
+ _srelocate = .;
+ *(.ramfunc .ramfunc.*);
+ *(.data .data.*);
+ . = ALIGN(4);
+ _erelocate = .;
+ } > ram
+
+ /* .bss section which is used for uninitialized data */
+ .bss (NOLOAD) :
+ {
+ . = ALIGN(4);
+ _sbss = . ;
+ _szero = .;
+ *(.bss .bss.*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = . ;
+ _ezero = .;
+ } > ram
+
+ /* stack section */
+ .stack (NOLOAD):
+ {
+ . = ALIGN(8);
+ _sstack = .;
+ . = . + STACK_SIZE;
+ . = ALIGN(8);
+ _estack = .;
+ } > ram
+
+ . = ALIGN(4);
+ _end = . ;
+}
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21j17a_sram.ld b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21j17a_sram.ld
new file mode 100644
index 0000000000000000000000000000000000000000..20c194f904dc8bfaf5177174265e1bbc27da89cd
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21j17a_sram.ld
@@ -0,0 +1,156 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21J17A
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+ ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00004000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x1000;
+
+/* Section Definitions */
+SECTIONS
+{
+ .text :
+ {
+ . = ALIGN(4);
+ _sfixed = .;
+ KEEP(*(.vectors .vectors.*))
+ *(.text .text.* .gnu.linkonce.t.*)
+ *(.glue_7t) *(.glue_7)
+ *(.rodata .rodata* .gnu.linkonce.r.*)
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+ /* Support C constructors, and C destructors in both user code
+ and the C library. This also provides support for C++ code. */
+ . = ALIGN(4);
+ KEEP(*(.init))
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ . = ALIGN(4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(4);
+ KEEP(*(.fini))
+
+ . = ALIGN(4);
+ __fini_array_start = .;
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ __fini_array_end = .;
+
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+
+ . = ALIGN(4);
+ _efixed = .; /* End of text section */
+ } > ram
+
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ PROVIDE_HIDDEN (__exidx_start = .);
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > ram
+ PROVIDE_HIDDEN (__exidx_end = .);
+
+ . = ALIGN(4);
+ _etext = .;
+
+ .relocate : AT (_etext)
+ {
+ . = ALIGN(4);
+ _srelocate = .;
+ *(.ramfunc .ramfunc.*);
+ *(.data .data.*);
+ . = ALIGN(4);
+ _erelocate = .;
+ } > ram
+
+ /* .bss section which is used for uninitialized data */
+ .bss (NOLOAD) :
+ {
+ . = ALIGN(4);
+ _sbss = . ;
+ _szero = .;
+ *(.bss .bss.*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = . ;
+ _ezero = .;
+ } > ram
+
+ /* stack section */
+ .stack (NOLOAD):
+ {
+ . = ALIGN(8);
+ _sstack = .;
+ . = . + STACK_SIZE;
+ . = ALIGN(8);
+ _estack = .;
+ } > ram
+
+ . = ALIGN(4);
+ _end = . ;
+}
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21j18a_flash.ld b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21j18a_flash.ld
new file mode 100644
index 0000000000000000000000000000000000000000..17934fb90231767edefed24008975566d67bcf6f
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21j18a_flash.ld
@@ -0,0 +1,157 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal FLASH on the SAMD21J18A
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+ rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000
+ ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
+
+/* Section Definitions */
+SECTIONS
+{
+ .text :
+ {
+ . = ALIGN(4);
+ _sfixed = .;
+ KEEP(*(.vectors .vectors.*))
+ *(.text .text.* .gnu.linkonce.t.*)
+ *(.glue_7t) *(.glue_7)
+ *(.rodata .rodata* .gnu.linkonce.r.*)
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+ /* Support C constructors, and C destructors in both user code
+ and the C library. This also provides support for C++ code. */
+ . = ALIGN(4);
+ KEEP(*(.init))
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ . = ALIGN(4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(4);
+ KEEP(*(.fini))
+
+ . = ALIGN(4);
+ __fini_array_start = .;
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ __fini_array_end = .;
+
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+
+ . = ALIGN(4);
+ _efixed = .; /* End of text section */
+ } > rom
+
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ PROVIDE_HIDDEN (__exidx_start = .);
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > rom
+ PROVIDE_HIDDEN (__exidx_end = .);
+
+ . = ALIGN(4);
+ _etext = .;
+
+ .relocate : AT (_etext)
+ {
+ . = ALIGN(4);
+ _srelocate = .;
+ *(.ramfunc .ramfunc.*);
+ *(.data .data.*);
+ . = ALIGN(4);
+ _erelocate = .;
+ } > ram
+
+ /* .bss section which is used for uninitialized data */
+ .bss (NOLOAD) :
+ {
+ . = ALIGN(4);
+ _sbss = . ;
+ _szero = .;
+ *(.bss .bss.*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = . ;
+ _ezero = .;
+ } > ram
+
+ /* stack section */
+ .stack (NOLOAD):
+ {
+ . = ALIGN(8);
+ _sstack = .;
+ . = . + STACK_SIZE;
+ . = ALIGN(8);
+ _estack = .;
+ } > ram
+
+ . = ALIGN(4);
+ _end = . ;
+}
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21j18a_sram.ld b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21j18a_sram.ld
new file mode 100644
index 0000000000000000000000000000000000000000..97c50c47e2d25ac89cb401fd5decc3a9710a10c6
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/samd21j18a_sram.ld
@@ -0,0 +1,156 @@
+/**
+ * \file
+ *
+ * \brief Linker script for running in internal SRAM on the SAMD21J18A
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY
+{
+ ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
+}
+
+/* The stack size used by the application. NOTE: you need to adjust according to your application. */
+STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
+
+/* Section Definitions */
+SECTIONS
+{
+ .text :
+ {
+ . = ALIGN(4);
+ _sfixed = .;
+ KEEP(*(.vectors .vectors.*))
+ *(.text .text.* .gnu.linkonce.t.*)
+ *(.glue_7t) *(.glue_7)
+ *(.rodata .rodata* .gnu.linkonce.r.*)
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+ /* Support C constructors, and C destructors in both user code
+ and the C library. This also provides support for C++ code. */
+ . = ALIGN(4);
+ KEEP(*(.init))
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ . = ALIGN(4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(4);
+ KEEP(*(.fini))
+
+ . = ALIGN(4);
+ __fini_array_start = .;
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ __fini_array_end = .;
+
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+
+ . = ALIGN(4);
+ _efixed = .; /* End of text section */
+ } > ram
+
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ PROVIDE_HIDDEN (__exidx_start = .);
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > ram
+ PROVIDE_HIDDEN (__exidx_end = .);
+
+ . = ALIGN(4);
+ _etext = .;
+
+ .relocate : AT (_etext)
+ {
+ . = ALIGN(4);
+ _srelocate = .;
+ *(.ramfunc .ramfunc.*);
+ *(.data .data.*);
+ . = ALIGN(4);
+ _erelocate = .;
+ } > ram
+
+ /* .bss section which is used for uninitialized data */
+ .bss (NOLOAD) :
+ {
+ . = ALIGN(4);
+ _sbss = . ;
+ _szero = .;
+ *(.bss .bss.*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = . ;
+ _ezero = .;
+ } > ram
+
+ /* stack section */
+ .stack (NOLOAD):
+ {
+ . = ALIGN(8);
+ _sstack = .;
+ . = . + STACK_SIZE;
+ . = ALIGN(8);
+ _estack = .;
+ } > ram
+
+ . = ALIGN(4);
+ _end = . ;
+}
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/startup_samd21.c b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/startup_samd21.c
new file mode 100644
index 0000000000000000000000000000000000000000..b2c0d90fcd34955487deefb058c041fa417c01a7
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/as_gcc/startup_samd21.c
@@ -0,0 +1,282 @@
+/**
+ * \file
+ *
+ * \brief gcc starttup file for SAMD21
+ *
+ * Copyright (c) 2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include "samd21.h"
+
+/* Initialize segments */
+extern uint32_t _sfixed;
+extern uint32_t _efixed;
+extern uint32_t _etext;
+extern uint32_t _srelocate;
+extern uint32_t _erelocate;
+extern uint32_t _szero;
+extern uint32_t _ezero;
+extern uint32_t _sstack;
+extern uint32_t _estack;
+
+/** \cond DOXYGEN_SHOULD_SKIP_THIS */
+int main(void);
+/** \endcond */
+
+void __libc_init_array(void);
+
+/* Default empty handler */
+void Dummy_Handler(void);
+
+/* Cortex-M0+ core handlers */
+void NMI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SVC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Peripherals handlers */
+void PM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SYSCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void EIC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void NVMCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef ID_USB
+void USB_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void EVSYS_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SERCOM0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SERCOM1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SERCOM2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SERCOM3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef ID_SERCOM4
+void SERCOM4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_SERCOM5
+void SERCOM5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void TCC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TCC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TCC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef ID_TC6
+void TC6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_TC7
+void TC7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_ADC
+void ADC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_AC
+void AC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_DAC
+void DAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_PTC
+void PTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_I2S
+void I2S_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_AC1
+void AC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+
+/* Exception Table */
+__attribute__ ((section(".vectors")))
+const DeviceVectors exception_table = {
+
+ /* Configure Initial Stack Pointer, using linker-generated symbols */
+ (void*) (&_estack),
+
+ (void*) Reset_Handler,
+ (void*) NMI_Handler,
+ (void*) HardFault_Handler,
+ (void*) (0UL), /* Reserved */
+ (void*) (0UL), /* Reserved */
+ (void*) (0UL), /* Reserved */
+ (void*) (0UL), /* Reserved */
+ (void*) (0UL), /* Reserved */
+ (void*) (0UL), /* Reserved */
+ (void*) (0UL), /* Reserved */
+ (void*) SVC_Handler,
+ (void*) (0UL), /* Reserved */
+ (void*) (0UL), /* Reserved */
+ (void*) PendSV_Handler,
+ (void*) SysTick_Handler,
+
+ /* Configurable interrupts */
+ (void*) PM_Handler, /* 0 Power Manager */
+ (void*) SYSCTRL_Handler, /* 1 System Control */
+ (void*) WDT_Handler, /* 2 Watchdog Timer */
+ (void*) RTC_Handler, /* 3 Real-Time Counter */
+ (void*) EIC_Handler, /* 4 External Interrupt Controller */
+ (void*) NVMCTRL_Handler, /* 5 Non-Volatile Memory Controller */
+ (void*) DMAC_Handler, /* 6 Direct Memory Access Controller */
+#ifdef ID_USB
+ (void*) USB_Handler, /* 7 Universal Serial Bus */
+#else
+ (void*) (0UL), /* Reserved */
+#endif
+ (void*) EVSYS_Handler, /* 8 Event System Interface */
+ (void*) SERCOM0_Handler, /* 9 Serial Communication Interface 0 */
+ (void*) SERCOM1_Handler, /* 10 Serial Communication Interface 1 */
+ (void*) SERCOM2_Handler, /* 11 Serial Communication Interface 2 */
+ (void*) SERCOM3_Handler, /* 12 Serial Communication Interface 3 */
+#ifdef ID_SERCOM4
+ (void*) SERCOM4_Handler, /* 13 Serial Communication Interface 4 */
+#else
+ (void*) (0UL), /* Reserved */
+#endif
+#ifdef ID_SERCOM5
+ (void*) SERCOM5_Handler, /* 14 Serial Communication Interface 5 */
+#else
+ (void*) (0UL), /* Reserved */
+#endif
+ (void*) TCC0_Handler, /* 15 Timer Counter Control 0 */
+ (void*) TCC1_Handler, /* 16 Timer Counter Control 1 */
+ (void*) TCC2_Handler, /* 17 Timer Counter Control 2 */
+ (void*) TC3_Handler, /* 18 Basic Timer Counter 0 */
+ (void*) TC4_Handler, /* 19 Basic Timer Counter 1 */
+ (void*) TC5_Handler, /* 20 Basic Timer Counter 2 */
+#ifdef ID_TC6
+ (void*) TC6_Handler, /* 21 Basic Timer Counter 3 */
+#else
+ (void*) (0UL), /* Reserved */
+#endif
+#ifdef ID_TC7
+ (void*) TC7_Handler, /* 22 Basic Timer Counter 4 */
+#else
+ (void*) (0UL), /* Reserved */
+#endif
+#ifdef ID_ADC
+ (void*) ADC_Handler, /* 23 Analog Digital Converter */
+#else
+ (void*) (0UL), /* Reserved */
+#endif
+#ifdef ID_AC
+ (void*) AC_Handler, /* 24 Analog Comparators 0 */
+#else
+ (void*) (0UL), /* Reserved */
+#endif
+#ifdef ID_DAC
+ (void*) DAC_Handler, /* 25 Digital Analog Converter */
+#else
+ (void*) (0UL), /* Reserved */
+#endif
+#ifdef ID_PTC
+ (void*) PTC_Handler, /* 26 Peripheral Touch Controller */
+#else
+ (void*) (0UL), /* Reserved */
+#endif
+#ifdef ID_I2S
+ (void*) I2S_Handler, /* 27 Inter-IC Sound Interface */
+#else
+ (void*) (0UL), /* Reserved */
+#endif
+#ifdef ID_AC1
+ (void*) AC1_Handler /* 28 Analog Comparators 1 */
+#else
+ (void*) (0UL) /* Reserved */
+#endif
+};
+
+/**
+ * \brief This is the code that gets called on processor reset.
+ * To initialize the device, and call the main() routine.
+ */
+void Reset_Handler(void)
+{
+ uint32_t *pSrc, *pDest;
+
+ /* Initialize the relocate segment */
+ pSrc = &_etext;
+ pDest = &_srelocate;
+
+ if (pSrc != pDest) {
+ for (; pDest < &_erelocate;) {
+ *pDest++ = *pSrc++;
+ }
+ }
+
+ /* Clear the zero segment */
+ for (pDest = &_szero; pDest < &_ezero;) {
+ *pDest++ = 0;
+ }
+
+ /* Set the vector table base address */
+ pSrc = (uint32_t *) & _sfixed;
+ SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
+
+ /* Change default QOS values to have the best performance and correct USB behaviour */
+ SBMATRIX->SFR[SBMATRIX_SLAVE_HMCRAMC0].reg = 2;
+#if defined(ID_USB)
+ USB->DEVICE.QOSCTRL.bit.CQOS = 2;
+ USB->DEVICE.QOSCTRL.bit.DQOS = 2;
+#endif
+ DMAC->QOSCTRL.bit.DQOS = 2;
+ DMAC->QOSCTRL.bit.FQOS = 2;
+ DMAC->QOSCTRL.bit.WRBQOS = 2;
+
+ /* Overwriting the default value of the NVMCTRL.CTRLB.MANW bit (errata reference 13134) */
+ NVMCTRL->CTRLB.bit.MANW = 1;
+
+ /* Initialize the C library */
+ __libc_init_array();
+
+ /* Branch to main function */
+ main();
+
+ /* Infinite loop */
+ while (1);
+}
+
+/**
+ * \brief Default interrupt handler for unused IRQs.
+ */
+void Dummy_Handler(void)
+{
+ while (1) {
+ }
+}
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/system_samd21.c b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/system_samd21.c
new file mode 100644
index 0000000000000000000000000000000000000000..c554030f3dbeb119967c328e825885d600a2624e
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/samd21/source/system_samd21.c
@@ -0,0 +1,78 @@
+/**
+ * \file
+ *
+ * \brief Low-level initialization functions called upon chip startup.
+ *
+ * Copyright (c) 2014 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ * Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include "samd21.h"
+
+/**
+ * Initial system clock frequency. The System RC Oscillator (RCSYS) provides
+ * the source for the main clock at chip startup.
+ */
+#define __SYSTEM_CLOCK (1000000)
+
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
+
+/**
+ * Initialize the system
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System and update the SystemCoreClock variable.
+ */
+void SystemInit(void)
+{
+ // Keep the default device state after reset
+ SystemCoreClock = __SYSTEM_CLOCK;
+ return;
+}
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @brief Updates the SystemCoreClock with current core Clock
+ * retrieved from cpu registers.
+ */
+void SystemCoreClockUpdate(void)
+{
+ // Not implemented
+ SystemCoreClock = __SYSTEM_CLOCK;
+ return;
+}
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/wiring.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/wiring.h
new file mode 100644
index 0000000000000000000000000000000000000000..55e4e6a8166938f4f9c652ac284ed3ab1800363c
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/wiring.h
@@ -0,0 +1,29 @@
+/*
+ Copyright (c) 2015 Arduino LLC. All right reserved.
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ See the GNU Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern void init(void);
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/wiring_analog.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/wiring_analog.h
new file mode 100644
index 0000000000000000000000000000000000000000..cca46359c77847351a6d1e475db18dfc819c2d51
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/wiring_analog.h
@@ -0,0 +1,84 @@
+/*
+ Copyright (c) 2015 Arduino LLC. All right reserved.
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ See the GNU Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#pragma once
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * \brief SAMD products have only one reference for ADC
+ */
+typedef enum _eAnalogReference
+{
+ AR_DEFAULT,
+ AR_INTERNAL,
+ AR_EXTERNAL,
+ AR_INTERNAL1V0,
+ AR_INTERNAL1V65,
+ AR_INTERNAL2V23
+} eAnalogReference ;
+
+
+/*
+ * \brief Configures the reference voltage used for analog input (i.e. the value used as the top of the input range).
+ * This function is kept only for compatibility with existing AVR based API.
+ *
+ * \param ulMmode Should be set to AR_DEFAULT.
+ */
+extern void analogReference( eAnalogReference ulMode ) ;
+
+/*
+ * \brief Writes an analog value (PWM wave) to a pin.
+ *
+ * \param ulPin
+ * \param ulValue
+ */
+extern void analogWrite( uint32_t ulPin, uint32_t ulValue ) ;
+
+/*
+ * \brief Reads the value from the specified analog pin.
+ *
+ * \param ulPin
+ *
+ * \return Read value from selected pin, if no error.
+ */
+extern uint32_t analogRead( uint32_t ulPin ) ;
+
+/*
+ * \brief Set the resolution of analogRead return values. Default is 10 bits (range from 0 to 1023).
+ *
+ * \param res
+ */
+extern void analogReadResolution(int res);
+
+/*
+ * \brief Set the resolution of analogWrite parameters. Default is 8 bits (range from 0 to 255).
+ *
+ * \param res
+ */
+extern void analogWriteResolution(int res);
+
+extern void analogOutputInit( void ) ;
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/wiring_constants.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/wiring_constants.h
new file mode 100644
index 0000000000000000000000000000000000000000..e8573aeda97f99f7f7c1ecbbd1b758a6501779fa
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/wiring_constants.h
@@ -0,0 +1,63 @@
+/*
+ Copyright (c) 2014 Arduino. All right reserved.
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ See the GNU Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#ifndef _WIRING_CONSTANTS_
+#define _WIRING_CONSTANTS_
+
+#ifdef __cplusplus
+extern "C"{
+#endif // __cplusplus
+
+#define LOW (0x0)
+#define HIGH (0x1)
+
+#define INPUT (0x0)
+#define OUTPUT (0x1)
+#define INPUT_PULLUP (0x2)
+#define INPUT_PULLDOWN (0x3)
+
+#define PI 3.1415926535897932384626433832795
+#define HALF_PI 1.5707963267948966192313216916398
+#define TWO_PI 6.283185307179586476925286766559
+#define DEG_TO_RAD 0.017453292519943295769236907684886
+#define RAD_TO_DEG 57.295779513082320876798154814105
+#define EULER 2.718281828459045235360287471352
+
+#define SERIAL 0x0
+#define DISPLAY 0x1
+
+enum BitOrder {
+ LSBFIRST = 0,
+ MSBFIRST = 1
+};
+
+// moved to WInterrupts.h
+//// LOW 0
+//// HIGH 1
+//#define CHANGE 2
+//#define FALLING 3
+//#define RISING 4
+//
+//#define DEFAULT 1
+//#define EXTERNAL 0
+
+#ifdef __cplusplus
+} // extern "C"
+#endif // __cplusplus
+
+#endif /* _WIRING_CONSTANTS_ */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/wiring_digital.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/wiring_digital.h
new file mode 100644
index 0000000000000000000000000000000000000000..9895390f2b93ad6341e3205d472a4667cb4b6537
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/wiring_digital.h
@@ -0,0 +1,71 @@
+/*
+ Copyright (c) 2014 Arduino. All right reserved.
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ See the GNU Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#ifndef _WIRING_DIGITAL_
+#define _WIRING_DIGITAL_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "WVariant.h"
+
+/**
+ * \brief Configures the specified pin to behave either as an input or an output. See the description of digital pins for details.
+ *
+ * \param ulPin The number of the pin whose mode you wish to set
+ * \param ulMode Can be INPUT, OUTPUT, INPUT_PULLUP or INPUT_PULLDOWN
+ */
+extern void pinMode( uint32_t dwPin, uint32_t dwMode ) ;
+
+/**
+ * \brief Write a HIGH or a LOW value to a digital pin.
+ *
+ * If the pin has been configured as an OUTPUT with pinMode(), its voltage will be set to the
+ * corresponding value: 5V (or 3.3V on 3.3V boards) for HIGH, 0V (ground) for LOW.
+ *
+ * If the pin is configured as an INPUT, writing a HIGH value with digitalWrite() will enable an internal
+ * 20K pullup resistor (see the tutorial on digital pins). Writing LOW will disable the pullup. The pullup
+ * resistor is enough to light an LED dimly, so if LEDs appear to work, but very dimly, this is a likely
+ * cause. The remedy is to set the pin to an output with the pinMode() function.
+ *
+ * \note Digital pin PIN_LED is harder to use as a digital input than the other digital pins because it has an LED
+ * and resistor attached to it that's soldered to the board on most boards. If you enable its internal 20k pull-up
+ * resistor, it will hang at around 1.7 V instead of the expected 5V because the onboard LED and series resistor
+ * pull the voltage level down, meaning it always returns LOW. If you must use pin PIN_LED as a digital input, use an
+ * external pull down resistor.
+ *
+ * \param dwPin the pin number
+ * \param dwVal HIGH or LOW
+ */
+extern void digitalWrite( uint32_t dwPin, uint32_t dwVal ) ;
+
+/**
+ * \brief Reads the value from a specified digital pin, either HIGH or LOW.
+ *
+ * \param ulPin The number of the digital pin you want to read (int)
+ *
+ * \return HIGH or LOW
+ */
+extern int digitalRead( uint32_t ulPin ) ;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _WIRING_DIGITAL_ */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/wiring_private.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/wiring_private.h
new file mode 100644
index 0000000000000000000000000000000000000000..ce64e2def4a2a210e3f3ee63c7d9d6f4301e6f72
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/wiring_private.h
@@ -0,0 +1,41 @@
+/*
+ Copyright (c) 2015 Arduino LLC. All right reserved.
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ See the GNU Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#pragma once
+
+#include <stdint.h>
+#include <stdio.h>
+#include <stdarg.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// Includes Atmel CMSIS
+#include "sam.h"
+
+#include "wiring_constants.h"
+
+int pinPeripheral( uint32_t ulPin, EPioType ulPeripheral );
+
+#ifdef __cplusplus
+} // extern "C"
+
+#include "HardwareSerial.h"
+
+#endif
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/core/wiring_shift.h b/UsbReceive/UsbReceive/ArduinoCore/include/core/wiring_shift.h
new file mode 100644
index 0000000000000000000000000000000000000000..6026bdc6127957d8ce4b2ac5005a5b08765f61cd
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/core/wiring_shift.h
@@ -0,0 +1,42 @@
+/*
+ Copyright (c) 2014 Arduino. All right reserved.
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ See the GNU Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#ifndef _WIRING_SHIFT_
+#define _WIRING_SHIFT_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/*
+ * \brief
+ */
+extern uint32_t shiftIn( uint32_t ulDataPin, uint32_t ulClockPin, uint32_t ulBitOrder ) ;
+
+
+/*
+ * \brief
+ */
+extern void shiftOut( uint32_t ulDataPin, uint32_t ulClockPin, uint32_t ulBitOrder, uint32_t ulVal ) ;
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _WIRING_SHIFT_ */
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/libraries/wire/Wire.h b/UsbReceive/UsbReceive/ArduinoCore/include/libraries/wire/Wire.h
new file mode 100644
index 0000000000000000000000000000000000000000..4260da201911e06df23c96ca92bc020798629cf2
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/libraries/wire/Wire.h
@@ -0,0 +1,110 @@
+/*
+ * TWI/I2C library for Arduino Zero
+ * Copyright (c) 2015 Arduino LLC. All rights reserved.
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef TwoWire_h
+#define TwoWire_h
+
+#include "Stream.h"
+#include "variant.h"
+
+#include "SERCOM.h"
+#include "RingBuffer.h"
+
+ // WIRE_HAS_END means Wire has end()
+#define WIRE_HAS_END 1
+
+class TwoWire : public Stream
+{
+ public:
+ TwoWire(SERCOM *s, uint8_t pinSDA, uint8_t pinSCL);
+ #if defined(_VARIANT_WIRELINGZERO_)
+ void changeInterface(uint8_t wireInterface);
+ #endif
+ void begin();
+ void begin(uint8_t, bool enableGeneralCall = false);
+ void end();
+ void setClock(uint32_t);
+
+ void beginTransmission(uint8_t);
+ uint8_t endTransmission(bool stopBit);
+ uint8_t endTransmission(void);
+
+ uint8_t requestFrom(uint8_t address, size_t quantity, bool stopBit);
+ uint8_t requestFrom(uint8_t address, size_t quantity);
+
+ size_t write(uint8_t data);
+ size_t write(const uint8_t * data, size_t quantity);
+
+ virtual int available(void);
+ virtual int read(void);
+ virtual int peek(void);
+ virtual void flush(void);
+ void onReceive(void(*)(int));
+ void onRequest(void(*)(void));
+
+ inline size_t write(unsigned long n) { return write((uint8_t)n); }
+ inline size_t write(long n) { return write((uint8_t)n); }
+ inline size_t write(unsigned int n) { return write((uint8_t)n); }
+ inline size_t write(int n) { return write((uint8_t)n); }
+ using Print::write;
+
+ void onService(void);
+
+ private:
+ SERCOM * sercom;
+ uint8_t _uc_pinSDA;
+ uint8_t _uc_pinSCL;
+
+ bool transmissionBegun;
+
+ // RX Buffer
+ RingBufferN<256> rxBuffer;
+
+ //TX buffer
+ RingBufferN<256> txBuffer;
+ uint8_t txAddress;
+
+ // Callback user functions
+ void (*onRequestCallback)(void);
+ void (*onReceiveCallback)(int);
+
+ // TWI clock frequency
+ static const uint32_t TWI_CLOCK = 100000;
+};
+
+#if WIRE_INTERFACES_COUNT > 0
+ extern TwoWire Wire;
+#endif
+#if WIRE_INTERFACES_COUNT > 1
+ extern TwoWire Wire1;
+#endif
+#if WIRE_INTERFACES_COUNT > 2
+ extern TwoWire Wire2;
+#endif
+#if WIRE_INTERFACES_COUNT > 3
+ extern TwoWire Wire3;
+#endif
+#if WIRE_INTERFACES_COUNT > 4
+ extern TwoWire Wire4;
+#endif
+#if WIRE_INTERFACES_COUNT > 5
+ extern TwoWire Wire5;
+#endif
+
+#endif
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/variants/pins_arduino.h b/UsbReceive/UsbReceive/ArduinoCore/include/variants/pins_arduino.h
new file mode 100644
index 0000000000000000000000000000000000000000..db0e40c3debd699f03024aedff25f6d6795d0b40
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/variants/pins_arduino.h
@@ -0,0 +1,21 @@
+/*
+ Copyright (c) 2014-2015 Arduino LLC. All right reserved.
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ See the GNU Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+// API compatibility
+#include "variant.h"
+
diff --git a/UsbReceive/UsbReceive/ArduinoCore/include/variants/variant.h b/UsbReceive/UsbReceive/ArduinoCore/include/variants/variant.h
new file mode 100644
index 0000000000000000000000000000000000000000..d7950bfe55e236cd757c39ea6261f4ff02eb693c
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/include/variants/variant.h
@@ -0,0 +1,242 @@
+/*
+ Copyright (c) 2014-2015 Arduino LLC. All right reserved.
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ See the GNU Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#ifndef _VARIANT_TINYZERO_
+#define _VARIANT_TINYZERO_
+
+// The definitions here needs a SAMD core >=1.6.10
+#define ARDUINO_SAMD_VARIANT_COMPLIANCE 10610
+
+/*----------------------------------------------------------------------------
+ * Definitions
+ *----------------------------------------------------------------------------*/
+
+/** Frequency of the board main oscillator */
+#define VARIANT_MAINOSC (32768ul)
+
+/** Master clock frequency */
+#define VARIANT_MCK (48000000ul)
+
+/*----------------------------------------------------------------------------
+ * Headers
+ *----------------------------------------------------------------------------*/
+
+#include "WVariant.h"
+
+#ifdef __cplusplus
+#include "SERCOM.h"
+#include "Uart.h"
+#endif // __cplusplus
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif // __cplusplus
+
+/*----------------------------------------------------------------------------
+ * Pins
+ *----------------------------------------------------------------------------*/
+
+// Number of pins defined in PinDescription array
+#define PINS_COUNT (26u)
+#define NUM_DIGITAL_PINS (20u)
+#define NUM_ANALOG_INPUTS (6u)
+#define NUM_ANALOG_OUTPUTS (1u)
+#define analogInputToDigitalPin(p) ((p < 6u) ? (p) + 14u : -1)
+
+#define digitalPinToPort(P) ( &(PORT->Group[g_APinDescription[P].ulPort]) )
+#define digitalPinToBitMask(P) ( 1 << g_APinDescription[P].ulPin )
+//#define analogInPinToBit(P) ( )
+#define portOutputRegister(port) ( &(port->OUT.reg) )
+#define portInputRegister(port) ( &(port->IN.reg) )
+#define portModeRegister(port) ( &(port->DIR.reg) )
+#define digitalPinHasPWM(P) ( g_APinDescription[P].ulPWMChannel != NOT_ON_PWM || g_APinDescription[P].ulTCChannel != NOT_ON_TIMER )
+
+/*
+ * digitalPinToTimer(..) is AVR-specific and is not defined for SAMD
+ * architecture. If you need to check if a pin supports PWM you must
+ * use digitalPinHasPWM(..).
+ *
+ * https://github.com/arduino/Arduino/issues/1833
+ */
+// #define digitalPinToTimer(P)
+
+// Interrupts
+#define digitalPinToInterrupt(P) ( g_APinDescription[P].ulExtInt )
+
+// LEDs
+#define PIN_LED_13 (13u)
+//#define PIN_LED_RXL (25u)
+//#define PIN_LED_TXL (26u)
+#define PIN_LED PIN_LED_13
+//#define PIN_LED2 PIN_LED_RXL
+//#define PIN_LED3 PIN_LED_TXL
+#define LED_BUILTIN PIN_LED_13
+
+/*
+ * Analog pins
+ */
+#define PIN_A0 (14ul)
+#define PIN_A1 (15ul)
+#define PIN_A2 (16ul)
+#define PIN_A3 (17ul)
+#define PIN_A4 (18ul)
+#define PIN_A5 (19ul)
+#define PIN_DAC0 (14ul)
+
+static const uint8_t A0 = PIN_A0 ;
+static const uint8_t A1 = PIN_A1 ;
+static const uint8_t A2 = PIN_A2 ;
+static const uint8_t A3 = PIN_A3 ;
+static const uint8_t A4 = PIN_A4 ;
+static const uint8_t A5 = PIN_A5 ;
+static const uint8_t DAC0 = PIN_DAC0;
+#define ADC_RESOLUTION 12
+
+// Other pins
+#define PIN_ATN (38ul)
+static const uint8_t ATN = PIN_ATN;
+
+/*
+ * Serial interfaces
+ */
+
+// Serial - pins 0/1
+#define PIN_SERIAL_RX (0ul)
+#define PIN_SERIAL_TX (1ul)
+#define PAD_SERIAL_TX (UART_TX_PAD_2)
+#define PAD_SERIAL_RX (SERCOM_RX_PAD_3)
+
+
+// Serial1
+#define PIN_SERIAL1_RX (31ul)
+#define PIN_SERIAL1_TX (30ul)
+#define PAD_SERIAL1_TX (UART_TX_PAD_2)
+#define PAD_SERIAL1_RX (SERCOM_RX_PAD_3)
+
+/*
+ * SPI Interfaces
+ */
+#define SPI_INTERFACES_COUNT 2
+
+#define PIN_SPI_MISO (12u)
+#define PIN_SPI_MOSI (11u)
+#define PIN_SPI_SCK (13u)
+#define PERIPH_SPI sercom1
+#define PAD_SPI_TX SPI_PAD_0_SCK_1
+#define PAD_SPI_RX SERCOM_RX_PAD_3
+
+#define PIN_SPI1_MISO (22u)
+#define PIN_SPI1_MOSI (23u)
+#define PIN_SPI1_SCK (24u)
+#define PERIPH_SPI1 sercom4
+#define PAD_SPI1_TX SPI_PAD_2_SCK_3
+#define PAD_SPI1_RX SERCOM_RX_PAD_0
+
+static const uint8_t SS = (10u) ; // HW SS isn't used.
+static const uint8_t MOSI = PIN_SPI_MOSI ;
+static const uint8_t MISO = PIN_SPI_MISO ;
+static const uint8_t SCK = PIN_SPI_SCK ;
+
+/*
+ * Wire Interfaces
+ */
+#define WIRE_INTERFACES_COUNT 2
+
+#define PIN_WIRE_SDA (20u)
+#define PIN_WIRE_SCL (21u)
+#define PERIPH_WIRE sercom3
+#define WIRE_IT_HANDLER SERCOM3_Handler
+
+static const uint8_t SDA = PIN_WIRE_SDA;
+static const uint8_t SCL = PIN_WIRE_SCL;
+
+#define PIN_WIRE1_SDA (22u)
+#define PIN_WIRE1_SCL (38u)
+#define PERIPH_WIRE1 sercom2
+#define WIRE1_IT_HANDLER SERCOM2_Handler
+
+static const uint8_t SDA1 = PIN_WIRE1_SDA;
+static const uint8_t SCL1 = PIN_WIRE1_SCL;
+
+/*
+ * USB
+ */
+#define PIN_USB_HOST_ENABLE (27ul)
+#define PIN_USB_DM (28ul)
+#define PIN_USB_DP (29ul)
+
+/*
+ * I2S Interfaces
+ */
+#define I2S_INTERFACES_COUNT 1
+
+#define I2S_DEVICE 0
+#define I2S_CLOCK_GENERATOR 3
+#define PIN_I2S_SD (9u)
+#define PIN_I2S_SCK (1u)
+#define PIN_I2S_FS (0u)
+
+#ifdef __cplusplus
+}
+#endif
+
+/*----------------------------------------------------------------------------
+ * Arduino objects - C++ only
+ *----------------------------------------------------------------------------*/
+
+#ifdef __cplusplus
+
+/* =========================
+ * ===== SERCOM DEFINITION
+ * =========================
+*/
+extern SERCOM sercom0;
+extern SERCOM sercom1;
+extern SERCOM sercom2;
+extern SERCOM sercom3;
+extern SERCOM sercom4;
+extern SERCOM sercom5;
+
+extern Uart Serial;
+extern Uart Serial1;
+
+#endif
+
+// These serial port names are intended to allow libraries and architecture-neutral
+// sketches to automatically default to the correct port name for a particular type
+// of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN,
+// the first hardware serial port whose RX/TX pins are not dedicated to another use.
+//
+// SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor
+//
+// SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial
+//
+// SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library
+//
+// SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins.
+//
+// SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX
+// pins are NOT connected to anything by default.
+#define SERIAL_PORT_USBVIRTUAL SerialUSB
+#define SERIAL_PORT_MONITOR SerialUSB
+#define SERIAL_PORT_HARDWARE Serial
+#define SERIAL_PORT_HARDWARE_OPEN Serial
+
+#endif /* _VARIANT_TINYZERO_ */
+
diff --git a/UsbReceive/UsbReceive/ArduinoCore/library.cpp b/UsbReceive/UsbReceive/ArduinoCore/library.cpp
new file mode 100644
index 0000000000000000000000000000000000000000..944dcaace2c9aa6a6a10bd616d40b2300703cca3
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/library.cpp
@@ -0,0 +1,15 @@
+/*
+ * ArduinoCore.cpp
+ *
+ * Created: 2022-01-03 09:08:13
+ * Author : benra10
+ */
+
+#include "sam.h"
+
+
+/* Replace with your library code */
+int myfunc(void)
+{
+ return 0;
+}
diff --git a/UsbReceive/UsbReceive/ArduinoCore/src/core/IPAddress.cpp b/UsbReceive/UsbReceive/ArduinoCore/src/core/IPAddress.cpp
new file mode 100644
index 0000000000000000000000000000000000000000..76aefa8b21f390840ab3ece5780b8bc9806f6c8c
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/src/core/IPAddress.cpp
@@ -0,0 +1,116 @@
+/*
+ IPAddress.cpp - Base class that provides IPAddress
+ Copyright (c) 2011 Adrian McEwen. All right reserved.
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#include <Arduino.h>
+#include <IPAddress.h>
+
+IPAddress::IPAddress()
+{
+ _address.dword = 0;
+}
+
+IPAddress::IPAddress(uint8_t first_octet, uint8_t second_octet, uint8_t third_octet, uint8_t fourth_octet)
+{
+ _address.bytes[0] = first_octet;
+ _address.bytes[1] = second_octet;
+ _address.bytes[2] = third_octet;
+ _address.bytes[3] = fourth_octet;
+}
+
+IPAddress::IPAddress(uint32_t address)
+{
+ _address.dword = address;
+}
+
+IPAddress::IPAddress(const uint8_t *address)
+{
+ memcpy(_address.bytes, address, sizeof(_address.bytes));
+}
+
+bool IPAddress::fromString(const char *address)
+{
+ // TODO: add support for "a", "a.b", "a.b.c" formats
+
+ uint16_t acc = 0; // Accumulator
+ uint8_t dots = 0;
+
+ while (*address)
+ {
+ char c = *address++;
+ if (c >= '0' && c <= '9')
+ {
+ acc = acc * 10 + (c - '0');
+ if (acc > 255) {
+ // Value out of [0..255] range
+ return false;
+ }
+ }
+ else if (c == '.')
+ {
+ if (dots == 3) {
+ // Too much dots (there must be 3 dots)
+ return false;
+ }
+ _address.bytes[dots++] = acc;
+ acc = 0;
+ }
+ else
+ {
+ // Invalid char
+ return false;
+ }
+ }
+
+ if (dots != 3) {
+ // Too few dots (there must be 3 dots)
+ return false;
+ }
+ _address.bytes[3] = acc;
+ return true;
+}
+
+IPAddress& IPAddress::operator=(const uint8_t *address)
+{
+ memcpy(_address.bytes, address, sizeof(_address.bytes));
+ return *this;
+}
+
+IPAddress& IPAddress::operator=(uint32_t address)
+{
+ _address.dword = address;
+ return *this;
+}
+
+bool IPAddress::operator==(const uint8_t* addr) const
+{
+ return memcmp(addr, _address.bytes, sizeof(_address.bytes)) == 0;
+}
+
+size_t IPAddress::printTo(Print& p) const
+{
+ size_t n = 0;
+ for (int i =0; i < 3; i++)
+ {
+ n += p.print(_address.bytes[i], DEC);
+ n += p.print('.');
+ }
+ n += p.print(_address.bytes[3], DEC);
+ return n;
+}
+
diff --git a/UsbReceive/UsbReceive/ArduinoCore/src/core/PreprocessingAssembly/pulse_asm.S b/UsbReceive/UsbReceive/ArduinoCore/src/core/PreprocessingAssembly/pulse_asm.S
new file mode 100644
index 0000000000000000000000000000000000000000..7b94f158bfce52b76d3901d1bfd4eefa2b2016d8
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/src/core/PreprocessingAssembly/pulse_asm.S
@@ -0,0 +1,175 @@
+/*
+ Copyright (c) 2015 Arduino LLC. All right reserved.
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ See the GNU Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+/*
+
+The following function has been compiled to ASM with gcc
+
+ unsigned long countPulseASM(const volatile uint32_t *port, uint32_t bit, uint32_t stateMask, unsigned long maxloops)
+ {
+ unsigned long width = 0;
+
+ // wait for any previous pulse to end
+ while ((*port & bit) == stateMask)
+ if (--maxloops == 0)
+ return 0;
+
+ // wait for the pulse to start
+ while ((*port & bit) != stateMask)
+ if (--maxloops == 0)
+ return 0;
+
+ // wait for the pulse to stop
+ while ((*port & bit) == stateMask) {
+ if (++width == maxloops)
+ return 0;
+ }
+ return width;
+ }
+
+using the command line:
+
+ arm-none-eabi-gcc -mcpu=cortex-m0plus -mthumb -c -Os -W -ffunction-sections -fdata-sections \
+ -nostdlib --param max-inline-insns-single=500 -fno-exceptions -MMD \
+ -DF_CPU=48000000L -DARDUINO=10602 -DARDUINO_SAMD_ZERO -DARDUINO_ARCH_SAMD \
+ -D__SAMD21G18A__ -DUSB_VID=0x2341 -DUSB_PID=0x004d -DUSBCON \
+ -DUSB_MANUFACTURER="Arduino LLC" -DUSB_PRODUCT="Arduino Zero" \
+ -I/Code/arduino/build/linux/work/hardware/tools/CMSIS/CMSIS/Include/ \
+ -I/Code/arduino/build/linux/work/hardware/tools/CMSIS/Device/ATMEL/ \
+ -I/Code/arduino/build/linux/work/hardware/arduino/samd/cores/arduino \
+ -I/Code/arduino/build/linux/work/hardware/arduino/samd/variants/arduino_zero \
+ count.c -Wa,-ahlmsd=output.lst -dp -fverbose-asm -S
+
+The result has been slightly edited to increase readability.
+
+*/
+
+ .cpu cortex-m0plus
+ .fpu softvfp
+ .eabi_attribute 20, 1 @ Tag_ABI_FP_denormal
+ .eabi_attribute 21, 1 @ Tag_ABI_FP_exceptions
+ .eabi_attribute 23, 3 @ Tag_ABI_FP_number_model
+ .eabi_attribute 24, 1 @ Tag_ABI_align8_needed
+ .eabi_attribute 25, 1 @ Tag_ABI_align8_preserved
+ .eabi_attribute 26, 1 @ Tag_ABI_enum_size
+ .eabi_attribute 30, 4 @ Tag_ABI_optimization_goals
+ .eabi_attribute 34, 0 @ Tag_CPU_unaligned_access
+ .eabi_attribute 18, 4 @ Tag_ABI_PCS_wchar_t
+ .file "count.c"
+@ GNU C (GNU Tools for ARM Embedded Processors (Arduino build)) version 4.8.3 20140228 (release) [ARM/embedded-4_8-branch revision 208322] (arm-none-eabi)
+@ compiled by GNU C version 4.3.2, GMP version 4.3.2, MPFR version 2.4.2, MPC version 0.8.1
+@ GGC heuristics: --param ggc-min-expand=100 --param ggc-min-heapsize=131072
+@ options passed:
+@ -I /Code/arduino/build/linux/work/hardware/tools/CMSIS/CMSIS/Include/
+@ -I /Code/arduino/build/linux/work/hardware/tools/CMSIS/Device/ATMEL/
+@ -I /Code/arduino/build/linux/work/hardware/arduino/samd/cores/arduino
+@ -I /Code/arduino/build/linux/work/hardware/arduino/samd/variants/arduino_zero
+@ -imultilib armv6-m
+@ -iprefix /Code/arduino/build/linux/work/hardware/tools/gcc-arm-none-eabi-4.8.3-2014q1/bin/../lib/gcc/arm-none-eabi/4.8.3/
+@ -isysroot /Code/arduino/build/linux/work/hardware/tools/gcc-arm-none-eabi-4.8.3-2014q1/bin/../arm-none-eabi
+@ -MMD count.d -D__USES_INITFINI__ -D F_CPU=48000000L -D ARDUINO=10602
+@ -D ARDUINO_SAMD_ZERO -D ARDUINO_ARCH_SAMD -D __SAMD21G18A__
+@ -D USB_VID=0x2341 -D USB_PID=0x004d -D USBCON
+@ -D USB_MANUFACTURER=Arduino LLC -D USB_PRODUCT=Arduino Zero count.c
+@ -mcpu=cortex-m0plus -mthumb -Os -Wextra -ffunction-sections
+@ -fdata-sections -fno-exceptions -fverbose-asm
+@ --param max-inline-insns-single=500
+@ options enabled: -faggressive-loop-optimizations -fauto-inc-dec
+@ -fbranch-count-reg -fcaller-saves -fcombine-stack-adjustments -fcommon
+@ -fcompare-elim -fcprop-registers -fcrossjumping -fcse-follow-jumps
+@ -fdata-sections -fdefer-pop -fdelete-null-pointer-checks -fdevirtualize
+@ -fdwarf2-cfi-asm -fearly-inlining -feliminate-unused-debug-types
+@ -fexpensive-optimizations -fforward-propagate -ffunction-cse
+@ -ffunction-sections -fgcse -fgcse-lm -fgnu-runtime
+@ -fguess-branch-probability -fhoist-adjacent-loads -fident -fif-conversion
+@ -fif-conversion2 -findirect-inlining -finline -finline-atomics
+@ -finline-functions -finline-functions-called-once
+@ -finline-small-functions -fipa-cp -fipa-profile -fipa-pure-const
+@ -fipa-reference -fipa-sra -fira-hoist-pressure -fira-share-save-slots
+@ -fira-share-spill-slots -fivopts -fkeep-static-consts
+@ -fleading-underscore -fmath-errno -fmerge-constants -fmerge-debug-strings
+@ -fomit-frame-pointer -foptimize-register-move -foptimize-sibling-calls
+@ -fpartial-inlining -fpeephole -fpeephole2 -fprefetch-loop-arrays
+@ -freg-struct-return -fregmove -freorder-blocks -freorder-functions
+@ -frerun-cse-after-loop -fsched-critical-path-heuristic
+@ -fsched-dep-count-heuristic -fsched-group-heuristic -fsched-interblock
+@ -fsched-last-insn-heuristic -fsched-pressure -fsched-rank-heuristic
+@ -fsched-spec -fsched-spec-insn-heuristic -fsched-stalled-insns-dep
+@ -fschedule-insns2 -fsection-anchors -fshow-column -fshrink-wrap
+@ -fsigned-zeros -fsplit-ivs-in-unroller -fsplit-wide-types
+@ -fstrict-aliasing -fstrict-overflow -fstrict-volatile-bitfields
+@ -fsync-libcalls -fthread-jumps -ftoplevel-reorder -ftrapping-math
+@ -ftree-bit-ccp -ftree-builtin-call-dce -ftree-ccp -ftree-ch
+@ -ftree-coalesce-vars -ftree-copy-prop -ftree-copyrename -ftree-cselim
+@ -ftree-dce -ftree-dominator-opts -ftree-dse -ftree-forwprop -ftree-fre
+@ -ftree-loop-if-convert -ftree-loop-im -ftree-loop-ivcanon
+@ -ftree-loop-optimize -ftree-parallelize-loops= -ftree-phiprop -ftree-pre
+@ -ftree-pta -ftree-reassoc -ftree-scev-cprop -ftree-sink
+@ -ftree-slp-vectorize -ftree-slsr -ftree-sra -ftree-switch-conversion
+@ -ftree-tail-merge -ftree-ter -ftree-vect-loop-version -ftree-vrp
+@ -funit-at-a-time -fverbose-asm -fzero-initialized-in-bss -mlittle-endian
+@ -mpic-data-is-text-relative -msched-prolog -mthumb
+@ -mvectorize-with-neon-quad
+
+ .section .text.countPulseASM,"ax",%progbits
+ .align 1
+ .global countPulseASM
+ .code 16
+ .thumb_func
+ .type countPulseASM, %function
+countPulseASM:
+ push {r4, r5, lr} @ @ 112 *push_multi [length = 2]
+.L2:
+ ldr r4, [r0] @ D.11539, *port_7(D) @ 22 *thumb1_movsi_insn/7 [length = 2]
+ and r4, r1 @ D.11539, bit @ 24 *thumb1_andsi3_insn [length = 2]
+ cmp r4, r2 @ D.11539, stateMask @ 25 cbranchsi4_insn/1 [length = 4]
+ bne .L5 @,
+ sub r3, r3, #1 @ maxloops, @ 17 *thumb1_addsi3/2 [length = 2]
+ cmp r3, #0 @ maxloops, @ 18 cbranchsi4_insn/1 [length = 4]
+ bne .L2 @,
+ b .L10 @ @ 127 *thumb_jump [length = 2]
+.L6:
+ sub r3, r3, #1 @ maxloops, @ 30 *thumb1_addsi3/2 [length = 2]
+ cmp r3, #0 @ maxloops, @ 31 cbranchsi4_insn/1 [length = 4]
+ beq .L10 @,
+.L5:
+ ldr r4, [r0] @ D.11539, *port_7(D) @ 35 *thumb1_movsi_insn/7 [length = 2]
+ and r4, r1 @ D.11539, bit @ 37 *thumb1_andsi3_insn [length = 2]
+ cmp r4, r2 @ D.11539, stateMask @ 38 cbranchsi4_insn/1 [length = 4]
+ bne .L6 @,
+ mov r4, #0 @ width, @ 7 *thumb1_movsi_insn/2 [length = 2]
+.L7:
+ ldr r5, [r0] @ D.11539, *port_7(D) @ 48 *thumb1_movsi_insn/7 [length = 2]
+ and r5, r1 @ D.11539, bit @ 50 *thumb1_andsi3_insn [length = 2]
+ cmp r5, r2 @ D.11539, stateMask @ 51 cbranchsi4_insn/1 [length = 4]
+ bne .L13 @,
+ add r4, r4, #1 @ width, @ 43 *thumb1_addsi3/1 [length = 2]
+ cmp r4, r3 @ width, maxloops @ 44 cbranchsi4_insn/1 [length = 4]
+ bne .L7 @,
+ mov r0, #0 @ D.11539, @ 11 *thumb1_movsi_insn/2 [length = 2]
+ b .L3 @ @ 130 *thumb_jump [length = 2]
+.L13:
+ mov r0, r4 @ D.11539, width @ 9 *thumb1_movsi_insn/1 [length = 2]
+ b .L3 @ @ 132 *thumb_jump [length = 2]
+.L10:
+ mov r0, r3 @ D.11539, maxloops @ 8 *thumb1_movsi_insn/1 [length = 2]
+.L3:
+ @ sp needed @ @ 115 force_register_use [length = 0]
+ pop {r4, r5, pc}
+ .size countPulseASM, .-countPulseASM
+ .ident "GCC: (GNU Tools for ARM Embedded Processors (Arduino build)) 4.8.3 20140228 (release) [ARM/embedded-4_8-branch revision 208322]"
diff --git a/UsbReceive/UsbReceive/ArduinoCore/src/core/Print.cpp b/UsbReceive/UsbReceive/ArduinoCore/src/core/Print.cpp
new file mode 100644
index 0000000000000000000000000000000000000000..9fc5c311677fb17afc1afc4225ac53cb0424de3b
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/src/core/Print.cpp
@@ -0,0 +1,251 @@
+/*
+ Copyright (c) 2014 Arduino. All right reserved.
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ See the GNU Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#include <math.h>
+#include "Arduino.h"
+
+#include "Print.h"
+
+// Public Methods //////////////////////////////////////////////////////////////
+
+/* default implementation: may be overridden */
+size_t Print::write(const uint8_t *buffer, size_t size)
+{
+ size_t n = 0;
+ while (size--) {
+ if (write(*buffer++)) n++;
+ else break;
+ }
+ return n;
+}
+
+size_t Print::print(const __FlashStringHelper *ifsh)
+{
+ return print(reinterpret_cast<const char *>(ifsh));
+}
+
+size_t Print::print(const String &s)
+{
+ return write(s.c_str(), s.length());
+}
+
+size_t Print::print(const char str[])
+{
+ return write(str);
+}
+
+size_t Print::print(char c)
+{
+ return write(c);
+}
+
+size_t Print::print(unsigned char b, int base)
+{
+ return print((unsigned long) b, base);
+}
+
+size_t Print::print(int n, int base)
+{
+ return print((long) n, base);
+}
+
+size_t Print::print(unsigned int n, int base)
+{
+ return print((unsigned long) n, base);
+}
+
+size_t Print::print(long n, int base)
+{
+ if (base == 0) {
+ return write(n);
+ } else if (base == 10) {
+ if (n < 0) {
+ int t = print('-');
+ n = -n;
+ return printNumber(n, 10) + t;
+ }
+ return printNumber(n, 10);
+ } else {
+ return printNumber(n, base);
+ }
+}
+
+size_t Print::print(unsigned long n, int base)
+{
+ if (base == 0) return write(n);
+ else return printNumber(n, base);
+}
+
+size_t Print::print(double n, int digits)
+{
+ return printFloat(n, digits);
+}
+
+size_t Print::println(const __FlashStringHelper *ifsh)
+{
+ size_t n = print(ifsh);
+ n += println();
+ return n;
+}
+
+size_t Print::print(const Printable& x)
+{
+ return x.printTo(*this);
+}
+
+size_t Print::println(void)
+{
+ return write("\r\n");
+}
+
+size_t Print::println(const String &s)
+{
+ size_t n = print(s);
+ n += println();
+ return n;
+}
+
+size_t Print::println(const char c[])
+{
+ size_t n = print(c);
+ n += println();
+ return n;
+}
+
+size_t Print::println(char c)
+{
+ size_t n = print(c);
+ n += println();
+ return n;
+}
+
+size_t Print::println(unsigned char b, int base)
+{
+ size_t n = print(b, base);
+ n += println();
+ return n;
+}
+
+size_t Print::println(int num, int base)
+{
+ size_t n = print(num, base);
+ n += println();
+ return n;
+}
+
+size_t Print::println(unsigned int num, int base)
+{
+ size_t n = print(num, base);
+ n += println();
+ return n;
+}
+
+size_t Print::println(long num, int base)
+{
+ size_t n = print(num, base);
+ n += println();
+ return n;
+}
+
+size_t Print::println(unsigned long num, int base)
+{
+ size_t n = print(num, base);
+ n += println();
+ return n;
+}
+
+size_t Print::println(double num, int digits)
+{
+ size_t n = print(num, digits);
+ n += println();
+ return n;
+}
+
+size_t Print::println(const Printable& x)
+{
+ size_t n = print(x);
+ n += println();
+ return n;
+}
+
+// Private Methods /////////////////////////////////////////////////////////////
+
+size_t Print::printNumber(unsigned long n, uint8_t base)
+{
+ char buf[8 * sizeof(long) + 1]; // Assumes 8-bit chars plus zero byte.
+ char *str = &buf[sizeof(buf) - 1];
+
+ *str = '\0';
+
+ // prevent crash if called with base == 1
+ if (base < 2) base = 10;
+
+ do {
+ char c = n % base;
+ n /= base;
+
+ *--str = c < 10 ? c + '0' : c + 'A' - 10;
+ } while(n);
+
+ return write(str);
+}
+
+size_t Print::printFloat(double number, uint8_t digits)
+{
+ size_t n = 0;
+
+ if (isnan(number)) return print("nan");
+ if (isinf(number)) return print("inf");
+ if (number > 4294967040.0) return print ("ovf"); // constant determined empirically
+ if (number <-4294967040.0) return print ("ovf"); // constant determined empirically
+
+ // Handle negative numbers
+ if (number < 0.0)
+ {
+ n += print('-');
+ number = -number;
+ }
+
+ // Round correctly so that print(1.999, 2) prints as "2.00"
+ double rounding = 0.5;
+ for (uint8_t i=0; i<digits; ++i)
+ rounding /= 10.0;
+
+ number += rounding;
+
+ // Extract the integer part of the number and print it
+ unsigned long int_part = (unsigned long)number;
+ double remainder = number - (double)int_part;
+ n += print(int_part);
+
+ // Print the decimal point, but only if there are digits beyond
+ if (digits > 0) {
+ n += print('.');
+ }
+
+ // Extract digits from the remainder one at a time
+ while (digits-- > 0)
+ {
+ remainder *= 10.0;
+ unsigned int toPrint = (unsigned int)(remainder);
+ n += print(toPrint);
+ remainder -= toPrint;
+ }
+
+ return n;
+}
diff --git a/UsbReceive/UsbReceive/ArduinoCore/src/core/Reset.cpp b/UsbReceive/UsbReceive/ArduinoCore/src/core/Reset.cpp
new file mode 100644
index 0000000000000000000000000000000000000000..21592d7593cfdae3e35dc5956eb6a631676e695b
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/src/core/Reset.cpp
@@ -0,0 +1,90 @@
+/*
+ Copyright (c) 2015 Arduino LLC. All right reserved.
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ See the GNU Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#include <Arduino.h>
+#include "Reset.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define NVM_MEMORY ((volatile uint16_t *)0x000000)
+
+#if (ARDUINO_SAMD_VARIANT_COMPLIANCE >= 10610)
+
+extern const uint32_t __text_start__;
+#define APP_START ((volatile uint32_t)(&__text_start__) + 4)
+
+#else
+#define APP_START 0x00002004
+#endif
+
+static inline bool nvmReady(void) {
+ return NVMCTRL->INTFLAG.reg & NVMCTRL_INTFLAG_READY;
+}
+
+__attribute__ ((long_call, section (".ramfunc")))
+static void banzai() {
+ // Disable all interrupts
+ __disable_irq();
+
+ // Avoid erasing the application if APP_START is < than the minimum bootloader size
+ // This could happen if without_bootloader linker script was chosen
+ // Minimum bootloader size in SAMD21 family is 512bytes (RM section 22.6.5)
+ if (APP_START < (0x200 + 4)) {
+ goto reset;
+ }
+
+ // Erase application
+ while (!nvmReady())
+ ;
+ NVMCTRL->STATUS.reg |= NVMCTRL_STATUS_MASK;
+ NVMCTRL->ADDR.reg = (uintptr_t)&NVM_MEMORY[APP_START / 4];
+ NVMCTRL->CTRLA.reg = NVMCTRL_CTRLA_CMD_ER | NVMCTRL_CTRLA_CMDEX_KEY;
+ while (!nvmReady())
+ ;
+
+reset:
+ // Reset the device
+ NVIC_SystemReset() ;
+
+ while (true);
+}
+
+static int ticks = -1;
+
+void initiateReset(int _ticks) {
+ resetExternalChip();
+ ticks = _ticks;
+}
+
+void cancelReset() {
+ ticks = -1;
+}
+
+void tickReset() {
+ if (ticks == -1)
+ return;
+ ticks--;
+ if (ticks == 0)
+ banzai();
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/UsbReceive/UsbReceive/ArduinoCore/src/core/SERCOM.cpp b/UsbReceive/UsbReceive/ArduinoCore/src/core/SERCOM.cpp
new file mode 100644
index 0000000000000000000000000000000000000000..8bf5a45214e6955e9f6c746fd046e898f20378cc
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/src/core/SERCOM.cpp
@@ -0,0 +1,741 @@
+/*
+ Copyright (c) 2014 Arduino. All right reserved.
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ See the GNU Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#include "Arduino.h"
+#include "SERCOM.h"
+#include "variant.h"
+
+#ifndef WIRE_RISE_TIME_NANOSECONDS
+// Default rise time in nanoseconds, based on 4.7K ohm pull up resistors
+// you can override this value in your variant if needed
+#define WIRE_RISE_TIME_NANOSECONDS 125
+#endif
+
+SERCOM::SERCOM(Sercom* s)
+{
+ sercom = s;
+}
+
+/* =========================
+ * ===== Sercom UART
+ * =========================
+*/
+void SERCOM::initUART(SercomUartMode mode, SercomUartSampleRate sampleRate, uint32_t baudrate)
+{
+ initClockNVIC();
+ resetUART();
+
+ //Setting the CTRLA register
+ sercom->USART.CTRLA.reg = SERCOM_USART_CTRLA_MODE(mode) |
+ SERCOM_USART_CTRLA_SAMPR(sampleRate);
+
+ //Setting the Interrupt register
+ sercom->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXC | //Received complete
+ SERCOM_USART_INTENSET_ERROR; //All others errors
+
+ if ( mode == UART_INT_CLOCK )
+ {
+ uint16_t sampleRateValue;
+
+ if (sampleRate == SAMPLE_RATE_x16) {
+ sampleRateValue = 16;
+ } else {
+ sampleRateValue = 8;
+ }
+
+ // Asynchronous fractional mode (Table 24-2 in datasheet)
+ // BAUD = fref / (sampleRateValue * fbaud)
+ // (multiply by 8, to calculate fractional piece)
+ uint32_t baudTimes8 = (SystemCoreClock * 8) / (sampleRateValue * baudrate);
+
+ sercom->USART.BAUD.FRAC.FP = (baudTimes8 % 8);
+ sercom->USART.BAUD.FRAC.BAUD = (baudTimes8 / 8);
+ }
+}
+void SERCOM::initFrame(SercomUartCharSize charSize, SercomDataOrder dataOrder, SercomParityMode parityMode, SercomNumberStopBit nbStopBits)
+{
+ //Setting the CTRLA register
+ sercom->USART.CTRLA.reg |= SERCOM_USART_CTRLA_FORM( (parityMode == SERCOM_NO_PARITY ? 0 : 1) ) |
+ dataOrder << SERCOM_USART_CTRLA_DORD_Pos;
+
+ //Setting the CTRLB register
+ sercom->USART.CTRLB.reg |= SERCOM_USART_CTRLB_CHSIZE(charSize) |
+ nbStopBits << SERCOM_USART_CTRLB_SBMODE_Pos |
+ (parityMode == SERCOM_NO_PARITY ? 0 : parityMode) << SERCOM_USART_CTRLB_PMODE_Pos; //If no parity use default value
+}
+
+void SERCOM::initPads(SercomUartTXPad txPad, SercomRXPad rxPad)
+{
+ //Setting the CTRLA register
+ sercom->USART.CTRLA.reg |= SERCOM_USART_CTRLA_TXPO(txPad) |
+ SERCOM_USART_CTRLA_RXPO(rxPad);
+
+ // Enable Transceiver and Receiver
+ sercom->USART.CTRLB.reg |= SERCOM_USART_CTRLB_TXEN | SERCOM_USART_CTRLB_RXEN ;
+}
+
+void SERCOM::resetUART()
+{
+ // Start the Software Reset
+ sercom->USART.CTRLA.bit.SWRST = 1 ;
+
+ while ( sercom->USART.CTRLA.bit.SWRST || sercom->USART.SYNCBUSY.bit.SWRST )
+ {
+ // Wait for both bits Software Reset from CTRLA and SYNCBUSY coming back to 0
+ }
+}
+
+void SERCOM::enableUART()
+{
+ //Setting the enable bit to 1
+ sercom->USART.CTRLA.bit.ENABLE = 0x1u;
+
+ //Wait for then enable bit from SYNCBUSY is equal to 0;
+ while(sercom->USART.SYNCBUSY.bit.ENABLE);
+}
+
+void SERCOM::flushUART()
+{
+ // Skip checking transmission completion if data register is empty
+ if(isDataRegisterEmptyUART())
+ return;
+
+ // Wait for transmission to complete
+ while(!sercom->USART.INTFLAG.bit.TXC);
+}
+
+void SERCOM::clearStatusUART()
+{
+ //Reset (with 0) the STATUS register
+ sercom->USART.STATUS.reg = SERCOM_USART_STATUS_RESETVALUE;
+}
+
+bool SERCOM::availableDataUART()
+{
+ //RXC : Receive Complete
+ return sercom->USART.INTFLAG.bit.RXC;
+}
+
+bool SERCOM::isUARTError()
+{
+ return sercom->USART.INTFLAG.bit.ERROR;
+}
+
+void SERCOM::acknowledgeUARTError()
+{
+ sercom->USART.INTFLAG.bit.ERROR = 1;
+}
+
+bool SERCOM::isBufferOverflowErrorUART()
+{
+ //BUFOVF : Buffer Overflow
+ return sercom->USART.STATUS.bit.BUFOVF;
+}
+
+bool SERCOM::isFrameErrorUART()
+{
+ //FERR : Frame Error
+ return sercom->USART.STATUS.bit.FERR;
+}
+
+void SERCOM::clearFrameErrorUART()
+{
+ // clear FERR bit writing 1 status bit
+ sercom->USART.STATUS.bit.FERR = 1;
+}
+
+bool SERCOM::isParityErrorUART()
+{
+ //PERR : Parity Error
+ return sercom->USART.STATUS.bit.PERR;
+}
+
+bool SERCOM::isDataRegisterEmptyUART()
+{
+ //DRE : Data Register Empty
+ return sercom->USART.INTFLAG.bit.DRE;
+}
+
+uint8_t SERCOM::readDataUART()
+{
+ return sercom->USART.DATA.bit.DATA;
+}
+
+int SERCOM::writeDataUART(uint8_t data)
+{
+ // Wait for data register to be empty
+ while(!isDataRegisterEmptyUART());
+
+ //Put data into DATA register
+ sercom->USART.DATA.reg = (uint16_t)data;
+ return 1;
+}
+
+void SERCOM::enableDataRegisterEmptyInterruptUART()
+{
+ sercom->USART.INTENSET.reg = SERCOM_USART_INTENSET_DRE;
+}
+
+void SERCOM::disableDataRegisterEmptyInterruptUART()
+{
+ sercom->USART.INTENCLR.reg = SERCOM_USART_INTENCLR_DRE;
+}
+
+/* =========================
+ * ===== Sercom SPI
+ * =========================
+*/
+void SERCOM::initSPI(SercomSpiTXPad mosi, SercomRXPad miso, SercomSpiCharSize charSize, SercomDataOrder dataOrder)
+{
+ resetSPI();
+ initClockNVIC();
+
+ //Setting the CTRLA register
+ sercom->SPI.CTRLA.reg = SERCOM_SPI_CTRLA_MODE_SPI_MASTER |
+ SERCOM_SPI_CTRLA_DOPO(mosi) |
+ SERCOM_SPI_CTRLA_DIPO(miso) |
+ dataOrder << SERCOM_SPI_CTRLA_DORD_Pos;
+
+ //Setting the CTRLB register
+ sercom->SPI.CTRLB.reg = SERCOM_SPI_CTRLB_CHSIZE(charSize) |
+ SERCOM_SPI_CTRLB_RXEN; //Active the SPI receiver.
+
+
+}
+
+void SERCOM::initSPIClock(SercomSpiClockMode clockMode, uint32_t baudrate)
+{
+ //Extract data from clockMode
+ int cpha, cpol;
+
+ if((clockMode & (0x1ul)) == 0 )
+ cpha = 0;
+ else
+ cpha = 1;
+
+ if((clockMode & (0x2ul)) == 0)
+ cpol = 0;
+ else
+ cpol = 1;
+
+ //Setting the CTRLA register
+ sercom->SPI.CTRLA.reg |= ( cpha << SERCOM_SPI_CTRLA_CPHA_Pos ) |
+ ( cpol << SERCOM_SPI_CTRLA_CPOL_Pos );
+
+ //Synchronous arithmetic
+ sercom->SPI.BAUD.reg = calculateBaudrateSynchronous(baudrate);
+}
+
+void SERCOM::resetSPI()
+{
+ //Setting the Software Reset bit to 1
+ sercom->SPI.CTRLA.bit.SWRST = 1;
+
+ //Wait both bits Software Reset from CTRLA and SYNCBUSY are equal to 0
+ while(sercom->SPI.CTRLA.bit.SWRST || sercom->SPI.SYNCBUSY.bit.SWRST);
+}
+
+void SERCOM::enableSPI()
+{
+ //Setting the enable bit to 1
+ sercom->SPI.CTRLA.bit.ENABLE = 1;
+
+ while(sercom->SPI.SYNCBUSY.bit.ENABLE)
+ {
+ //Waiting then enable bit from SYNCBUSY is equal to 0;
+ }
+}
+
+void SERCOM::disableSPI()
+{
+ while(sercom->SPI.SYNCBUSY.bit.ENABLE)
+ {
+ //Waiting then enable bit from SYNCBUSY is equal to 0;
+ }
+
+ //Setting the enable bit to 0
+ sercom->SPI.CTRLA.bit.ENABLE = 0;
+}
+
+void SERCOM::setDataOrderSPI(SercomDataOrder dataOrder)
+{
+ //Register enable-protected
+ disableSPI();
+
+ sercom->SPI.CTRLA.bit.DORD = dataOrder;
+
+ enableSPI();
+}
+
+SercomDataOrder SERCOM::getDataOrderSPI()
+{
+ return (sercom->SPI.CTRLA.bit.DORD ? LSB_FIRST : MSB_FIRST);
+}
+
+void SERCOM::setBaudrateSPI(uint8_t divider)
+{
+ //Can't divide by 0
+ if(divider == 0)
+ return;
+
+ //Register enable-protected
+ disableSPI();
+
+ sercom->SPI.BAUD.reg = calculateBaudrateSynchronous( SERCOM_FREQ_REF / divider );
+
+ enableSPI();
+}
+
+void SERCOM::setClockModeSPI(SercomSpiClockMode clockMode)
+{
+ int cpha, cpol;
+ if((clockMode & (0x1ul)) == 0)
+ cpha = 0;
+ else
+ cpha = 1;
+
+ if((clockMode & (0x2ul)) == 0)
+ cpol = 0;
+ else
+ cpol = 1;
+
+ //Register enable-protected
+ disableSPI();
+
+ sercom->SPI.CTRLA.bit.CPOL = cpol;
+ sercom->SPI.CTRLA.bit.CPHA = cpha;
+
+ enableSPI();
+}
+
+uint8_t SERCOM::transferDataSPI(uint8_t data)
+{
+ sercom->SPI.DATA.bit.DATA = data; // Writing data into Data register
+
+ while( sercom->SPI.INTFLAG.bit.RXC == 0 )
+ {
+ // Waiting Complete Reception
+ }
+
+ return sercom->SPI.DATA.bit.DATA; // Reading data
+}
+
+bool SERCOM::isBufferOverflowErrorSPI()
+{
+ return sercom->SPI.STATUS.bit.BUFOVF;
+}
+
+bool SERCOM::isDataRegisterEmptySPI()
+{
+ //DRE : Data Register Empty
+ return sercom->SPI.INTFLAG.bit.DRE;
+}
+
+//bool SERCOM::isTransmitCompleteSPI()
+//{
+// //TXC : Transmit complete
+// return sercom->SPI.INTFLAG.bit.TXC;
+//}
+//
+//bool SERCOM::isReceiveCompleteSPI()
+//{
+// //RXC : Receive complete
+// return sercom->SPI.INTFLAG.bit.RXC;
+//}
+
+uint8_t SERCOM::calculateBaudrateSynchronous(uint32_t baudrate)
+{
+ return SERCOM_FREQ_REF / (2 * baudrate) - 1;
+}
+
+
+/* =========================
+ * ===== Sercom WIRE
+ * =========================
+ */
+void SERCOM::resetWIRE()
+{
+ //I2CM OR I2CS, no matter SWRST is the same bit.
+
+ //Setting the Software bit to 1
+ sercom->I2CM.CTRLA.bit.SWRST = 1;
+
+ //Wait both bits Software Reset from CTRLA and SYNCBUSY are equal to 0
+ while(sercom->I2CM.CTRLA.bit.SWRST || sercom->I2CM.SYNCBUSY.bit.SWRST);
+}
+
+void SERCOM::enableWIRE()
+{
+ // I2C Master and Slave modes share the ENABLE bit function.
+
+ // Enable the I2C master mode
+ sercom->I2CM.CTRLA.bit.ENABLE = 1 ;
+
+ while ( sercom->I2CM.SYNCBUSY.bit.ENABLE != 0 )
+ {
+ // Waiting the enable bit from SYNCBUSY is equal to 0;
+ }
+
+ // Setting bus idle mode
+ sercom->I2CM.STATUS.bit.BUSSTATE = 1 ;
+
+ while ( sercom->I2CM.SYNCBUSY.bit.SYSOP != 0 )
+ {
+ // Wait the SYSOP bit from SYNCBUSY coming back to 0
+ }
+}
+
+void SERCOM::disableWIRE()
+{
+ // I2C Master and Slave modes share the ENABLE bit function.
+
+ // Enable the I2C master mode
+ sercom->I2CM.CTRLA.bit.ENABLE = 0 ;
+
+ while ( sercom->I2CM.SYNCBUSY.bit.ENABLE != 0 )
+ {
+ // Waiting the enable bit from SYNCBUSY is equal to 0;
+ }
+}
+
+void SERCOM::initSlaveWIRE( uint8_t ucAddress, bool enableGeneralCall )
+{
+ // Initialize the peripheral clock and interruption
+ initClockNVIC() ;
+ resetWIRE() ;
+
+ // Set slave mode
+ sercom->I2CS.CTRLA.bit.MODE = I2C_SLAVE_OPERATION;
+
+ sercom->I2CS.ADDR.reg = SERCOM_I2CS_ADDR_ADDR( ucAddress & 0x7Ful ) | // 0x7F, select only 7 bits
+ SERCOM_I2CS_ADDR_ADDRMASK( 0x00ul ); // 0x00, only match exact address
+ if (enableGeneralCall) {
+ sercom->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_GENCEN; // enable general call (address 0x00)
+ }
+
+ // Set the interrupt register
+ sercom->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_PREC | // Stop
+ SERCOM_I2CS_INTENSET_AMATCH | // Address Match
+ SERCOM_I2CS_INTENSET_DRDY ; // Data Ready
+
+ while ( sercom->I2CM.SYNCBUSY.bit.SYSOP != 0 )
+ {
+ // Wait the SYSOP bit from SYNCBUSY to come back to 0
+ }
+}
+
+void SERCOM::initMasterWIRE( uint32_t baudrate )
+{
+ // Initialize the peripheral clock and interruption
+ initClockNVIC() ;
+
+ resetWIRE() ;
+
+ // Set master mode and enable SCL Clock Stretch mode (stretch after ACK bit)
+ sercom->I2CM.CTRLA.reg = SERCOM_I2CM_CTRLA_MODE( I2C_MASTER_OPERATION )/* |
+ SERCOM_I2CM_CTRLA_SCLSM*/ ;
+
+ // Enable Smart mode and Quick Command
+ //sercom->I2CM.CTRLB.reg = SERCOM_I2CM_CTRLB_SMEN /*| SERCOM_I2CM_CTRLB_QCEN*/ ;
+
+
+ // Enable all interrupts
+// sercom->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_MB | SERCOM_I2CM_INTENSET_SB | SERCOM_I2CM_INTENSET_ERROR ;
+
+ // Synchronous arithmetic baudrate
+ sercom->I2CM.BAUD.bit.BAUD = SystemCoreClock / ( 2 * baudrate) - 5 - (((SystemCoreClock / 1000000) * WIRE_RISE_TIME_NANOSECONDS) / (2 * 1000));
+}
+
+void SERCOM::prepareNackBitWIRE( void )
+{
+ if(isMasterWIRE()) {
+ // Send a NACK
+ sercom->I2CM.CTRLB.bit.ACKACT = 1;
+ } else {
+ sercom->I2CS.CTRLB.bit.ACKACT = 1;
+ }
+}
+
+void SERCOM::prepareAckBitWIRE( void )
+{
+ if(isMasterWIRE()) {
+ // Send an ACK
+ sercom->I2CM.CTRLB.bit.ACKACT = 0;
+ } else {
+ sercom->I2CS.CTRLB.bit.ACKACT = 0;
+ }
+}
+
+void SERCOM::prepareCommandBitsWire(uint8_t cmd)
+{
+ if(isMasterWIRE()) {
+ sercom->I2CM.CTRLB.bit.CMD = cmd;
+
+ while(sercom->I2CM.SYNCBUSY.bit.SYSOP)
+ {
+ // Waiting for synchronization
+ }
+ } else {
+ sercom->I2CS.CTRLB.bit.CMD = cmd;
+ }
+}
+
+bool SERCOM::startTransmissionWIRE(uint8_t address, SercomWireReadWriteFlag flag)
+{
+ // 7-bits address + 1-bits R/W
+ address = (address << 0x1ul) | flag;
+
+ // If another master owns the bus or the last bus owner has not properly
+ // sent a stop, return failure early. This will prevent some misbehaved
+ // devices from deadlocking here at the cost of the caller being responsible
+ // for retrying the failed transmission. See SercomWireBusState for the
+ // possible bus states.
+ if(!isBusOwnerWIRE())
+ {
+ if( isBusBusyWIRE() || (isArbLostWIRE() && !isBusIdleWIRE()) )
+ {
+ return false;
+ }
+ }
+
+ // Send start and address
+ sercom->I2CM.ADDR.bit.ADDR = address;
+
+ // Address Transmitted
+ if ( flag == WIRE_WRITE_FLAG ) // Write mode
+ {
+ while( !sercom->I2CM.INTFLAG.bit.MB )
+ {
+ // Wait transmission complete
+ }
+ // Check for loss of arbitration (multiple masters starting communication at the same time)
+ if(!isBusOwnerWIRE())
+ {
+ // Restart communication
+ startTransmissionWIRE(address >> 1, flag);
+ }
+ }
+ else // Read mode
+ {
+ while( !sercom->I2CM.INTFLAG.bit.SB )
+ {
+ // If the slave NACKS the address, the MB bit will be set.
+ // In that case, send a stop condition and return false.
+ if (sercom->I2CM.INTFLAG.bit.MB) {
+ sercom->I2CM.CTRLB.bit.CMD = 3; // Stop condition
+ return false;
+ }
+ // Wait transmission complete
+ }
+
+ // Clean the 'Slave on Bus' flag, for further usage.
+ //sercom->I2CM.INTFLAG.bit.SB = 0x1ul;
+ }
+
+
+ //ACK received (0: ACK, 1: NACK)
+ if(sercom->I2CM.STATUS.bit.RXNACK)
+ {
+ return false;
+ }
+ else
+ {
+ return true;
+ }
+}
+
+bool SERCOM::sendDataMasterWIRE(uint8_t data)
+{
+ //Send data
+ sercom->I2CM.DATA.bit.DATA = data;
+
+ //Wait transmission successful
+ while(!sercom->I2CM.INTFLAG.bit.MB) {
+
+ // If a bus error occurs, the MB bit may never be set.
+ // Check the bus error bit and bail if it's set.
+ if (sercom->I2CM.STATUS.bit.BUSERR) {
+ return false;
+ }
+ }
+
+ //Problems on line? nack received?
+ if(sercom->I2CM.STATUS.bit.RXNACK)
+ return false;
+ else
+ return true;
+}
+
+bool SERCOM::sendDataSlaveWIRE(uint8_t data)
+{
+ //Send data
+ sercom->I2CS.DATA.bit.DATA = data;
+
+ //Problems on line? nack received?
+ if(!sercom->I2CS.INTFLAG.bit.DRDY || sercom->I2CS.STATUS.bit.RXNACK)
+ return false;
+ else
+ return true;
+}
+
+bool SERCOM::isMasterWIRE( void )
+{
+ return sercom->I2CS.CTRLA.bit.MODE == I2C_MASTER_OPERATION;
+}
+
+bool SERCOM::isSlaveWIRE( void )
+{
+ return sercom->I2CS.CTRLA.bit.MODE == I2C_SLAVE_OPERATION;
+}
+
+bool SERCOM::isBusIdleWIRE( void )
+{
+ return sercom->I2CM.STATUS.bit.BUSSTATE == WIRE_IDLE_STATE;
+}
+
+bool SERCOM::isBusOwnerWIRE( void )
+{
+ return sercom->I2CM.STATUS.bit.BUSSTATE == WIRE_OWNER_STATE;
+}
+
+bool SERCOM::isArbLostWIRE( void )
+{
+ return sercom->I2CM.STATUS.bit.ARBLOST == 1;
+}
+
+bool SERCOM::isBusBusyWIRE( void )
+{
+ return sercom->I2CM.STATUS.bit.BUSSTATE == WIRE_BUSY_STATE;
+}
+
+bool SERCOM::isDataReadyWIRE( void )
+{
+ return sercom->I2CS.INTFLAG.bit.DRDY;
+}
+
+bool SERCOM::isStopDetectedWIRE( void )
+{
+ return sercom->I2CS.INTFLAG.bit.PREC;
+}
+
+bool SERCOM::isRestartDetectedWIRE( void )
+{
+ return sercom->I2CS.STATUS.bit.SR;
+}
+
+bool SERCOM::isAddressMatch( void )
+{
+ return sercom->I2CS.INTFLAG.bit.AMATCH;
+}
+
+bool SERCOM::isMasterReadOperationWIRE( void )
+{
+ return sercom->I2CS.STATUS.bit.DIR;
+}
+
+bool SERCOM::isRXNackReceivedWIRE( void )
+{
+ return sercom->I2CM.STATUS.bit.RXNACK;
+}
+
+int SERCOM::availableWIRE( void )
+{
+ if(isMasterWIRE())
+ return sercom->I2CM.INTFLAG.bit.SB;
+ else
+ return sercom->I2CS.INTFLAG.bit.DRDY;
+}
+
+uint8_t SERCOM::readDataWIRE( void )
+{
+ if(isMasterWIRE())
+ {
+ while( sercom->I2CM.INTFLAG.bit.SB == 0 && sercom->I2CM.INTFLAG.bit.MB == 0 )
+ {
+ // Waiting complete receive
+ }
+
+ return sercom->I2CM.DATA.bit.DATA ;
+ }
+ else
+ {
+ return sercom->I2CS.DATA.reg ;
+ }
+}
+
+
+void SERCOM::initClockNVIC( void )
+{
+ uint8_t clockId = 0;
+ IRQn_Type IdNvic=PendSV_IRQn ; // Dummy init to intercept potential error later
+
+ if(sercom == SERCOM0)
+ {
+ clockId = GCM_SERCOM0_CORE;
+ IdNvic = SERCOM0_IRQn;
+ }
+ else if(sercom == SERCOM1)
+ {
+ clockId = GCM_SERCOM1_CORE;
+ IdNvic = SERCOM1_IRQn;
+ }
+ else if(sercom == SERCOM2)
+ {
+ clockId = GCM_SERCOM2_CORE;
+ IdNvic = SERCOM2_IRQn;
+ }
+ else if(sercom == SERCOM3)
+ {
+ clockId = GCM_SERCOM3_CORE;
+ IdNvic = SERCOM3_IRQn;
+ }
+ #if defined(SERCOM4)
+ else if(sercom == SERCOM4)
+ {
+ clockId = GCM_SERCOM4_CORE;
+ IdNvic = SERCOM4_IRQn;
+ }
+ #endif // SERCOM4
+ #if defined(SERCOM5)
+ else if(sercom == SERCOM5)
+ {
+ clockId = GCM_SERCOM5_CORE;
+ IdNvic = SERCOM5_IRQn;
+ }
+ #endif // SERCOM5
+
+ if ( IdNvic == PendSV_IRQn )
+ {
+ // We got a problem here
+ return ;
+ }
+
+ // Setting NVIC
+ NVIC_EnableIRQ(IdNvic);
+ NVIC_SetPriority (IdNvic, SERCOM_NVIC_PRIORITY); /* set Priority */
+
+ //Setting clock
+ GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID( clockId ) | // Generic Clock 0 (SERCOMx)
+ GCLK_CLKCTRL_GEN_GCLK0 | // Generic Clock Generator 0 is source
+ GCLK_CLKCTRL_CLKEN ;
+
+ while ( GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY )
+ {
+ /* Wait for synchronization */
+ }
+}
diff --git a/UsbReceive/UsbReceive/ArduinoCore/src/core/Stream.cpp b/UsbReceive/UsbReceive/ArduinoCore/src/core/Stream.cpp
new file mode 100644
index 0000000000000000000000000000000000000000..d2846316d348d3d54a1c0d330355e9d26781ad94
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/src/core/Stream.cpp
@@ -0,0 +1,319 @@
+/*
+ Stream.cpp - adds parsing methods to Stream class
+ Copyright (c) 2008 David A. Mellis. All right reserved.
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+
+ Created July 2011
+ parsing functions based on TextFinder library by Michael Margolis
+
+ findMulti/findUntil routines written by Jim Leonard/Xuth
+ */
+
+#include "Arduino.h"
+#include "Stream.h"
+
+#define PARSE_TIMEOUT 1000 // default number of milli-seconds to wait
+
+// protected method to read stream with timeout
+int Stream::timedRead()
+{
+ int c;
+ _startMillis = millis();
+ do {
+ c = read();
+ if (c >= 0) return c;
+ } while(millis() - _startMillis < _timeout);
+ return -1; // -1 indicates timeout
+}
+
+// protected method to peek stream with timeout
+int Stream::timedPeek()
+{
+ int c;
+ _startMillis = millis();
+ do {
+ c = peek();
+ if (c >= 0) return c;
+ } while(millis() - _startMillis < _timeout);
+ return -1; // -1 indicates timeout
+}
+
+// returns peek of the next digit in the stream or -1 if timeout
+// discards non-numeric characters
+int Stream::peekNextDigit(LookaheadMode lookahead, bool detectDecimal)
+{
+ int c;
+ while (1) {
+ c = timedPeek();
+
+ if( c < 0 ||
+ c == '-' ||
+ (c >= '0' && c <= '9') ||
+ (detectDecimal && c == '.')) return c;
+
+ switch( lookahead ){
+ case SKIP_NONE: return -1; // Fail code.
+ case SKIP_WHITESPACE:
+ switch( c ){
+ case ' ':
+ case '\t':
+ case '\r':
+ case '\n': break;
+ default: return -1; // Fail code.
+ }
+ case SKIP_ALL:
+ break;
+ }
+ read(); // discard non-numeric
+ }
+}
+
+// Public Methods
+//////////////////////////////////////////////////////////////
+
+void Stream::setTimeout(unsigned long timeout) // sets the maximum number of milliseconds to wait
+{
+ _timeout = timeout;
+}
+
+ // find returns true if the target string is found
+bool Stream::find(char *target)
+{
+ return findUntil(target, strlen(target), NULL, 0);
+}
+
+// reads data from the stream until the target string of given length is found
+// returns true if target string is found, false if timed out
+bool Stream::find(char *target, size_t length)
+{
+ return findUntil(target, length, NULL, 0);
+}
+
+// as find but search ends if the terminator string is found
+bool Stream::findUntil(char *target, char *terminator)
+{
+ return findUntil(target, strlen(target), terminator, strlen(terminator));
+}
+
+// reads data from the stream until the target string of the given length is found
+// search terminated if the terminator string is found
+// returns true if target string is found, false if terminated or timed out
+bool Stream::findUntil(char *target, size_t targetLen, char *terminator, size_t termLen)
+{
+ if (terminator == NULL) {
+ MultiTarget t[1] = {{target, targetLen, 0}};
+ return findMulti(t, 1) == 0 ? true : false;
+ } else {
+ MultiTarget t[2] = {{target, targetLen, 0}, {terminator, termLen, 0}};
+ return findMulti(t, 2) == 0 ? true : false;
+ }
+}
+
+// returns the first valid (long) integer value from the current position.
+// lookahead determines how parseInt looks ahead in the stream.
+// See LookaheadMode enumeration at the top of the file.
+// Lookahead is terminated by the first character that is not a valid part of an integer.
+// Once parsing commences, 'ignore' will be skipped in the stream.
+long Stream::parseInt(LookaheadMode lookahead, char ignore)
+{
+ bool isNegative = false;
+ long value = 0;
+ int c;
+
+ c = peekNextDigit(lookahead, false);
+ // ignore non numeric leading characters
+ if(c < 0)
+ return 0; // zero returned if timeout
+
+ do{
+ if(c == ignore)
+ ; // ignore this character
+ else if(c == '-')
+ isNegative = true;
+ else if(c >= '0' && c <= '9') // is c a digit?
+ value = value * 10 + c - '0';
+ read(); // consume the character we got with peek
+ c = timedPeek();
+ }
+ while( (c >= '0' && c <= '9') || c == ignore );
+
+ if(isNegative)
+ value = -value;
+ return value;
+}
+
+// as parseInt but returns a floating point value
+float Stream::parseFloat(LookaheadMode lookahead, char ignore)
+{
+ bool isNegative = false;
+ bool isFraction = false;
+ long value = 0;
+ int c;
+ float fraction = 1.0;
+
+ c = peekNextDigit(lookahead, true);
+ // ignore non numeric leading characters
+ if(c < 0)
+ return 0; // zero returned if timeout
+
+ do{
+ if(c == ignore)
+ ; // ignore
+ else if(c == '-')
+ isNegative = true;
+ else if (c == '.')
+ isFraction = true;
+ else if(c >= '0' && c <= '9') { // is c a digit?
+ value = value * 10 + c - '0';
+ if(isFraction)
+ fraction *= 0.1;
+ }
+ read(); // consume the character we got with peek
+ c = timedPeek();
+ }
+ while( (c >= '0' && c <= '9') || (c == '.' && !isFraction) || c == ignore );
+
+ if(isNegative)
+ value = -value;
+ if(isFraction)
+ return value * fraction;
+ else
+ return value;
+}
+
+// read characters from stream into buffer
+// terminates if length characters have been read, or timeout (see setTimeout)
+// returns the number of characters placed in the buffer
+// the buffer is NOT null terminated.
+//
+size_t Stream::readBytes(char *buffer, size_t length)
+{
+ size_t count = 0;
+ while (count < length) {
+ int c = timedRead();
+ if (c < 0) break;
+ *buffer++ = (char)c;
+ count++;
+ }
+ return count;
+}
+
+
+// as readBytes with terminator character
+// terminates if length characters have been read, timeout, or if the terminator character detected
+// returns the number of characters placed in the buffer (0 means no valid data found)
+
+size_t Stream::readBytesUntil(char terminator, char *buffer, size_t length)
+{
+ if (length < 1) return 0;
+ size_t index = 0;
+ while (index < length) {
+ int c = timedRead();
+ if (c < 0 || c == terminator) break;
+ *buffer++ = (char)c;
+ index++;
+ }
+ return index; // return number of characters, not including null terminator
+}
+
+String Stream::readString()
+{
+ String ret;
+ int c = timedRead();
+ while (c >= 0)
+ {
+ ret += (char)c;
+ c = timedRead();
+ }
+ return ret;
+}
+
+String Stream::readStringUntil(char terminator)
+{
+ String ret;
+ int c = timedRead();
+ while (c >= 0 && c != terminator)
+ {
+ ret += (char)c;
+ c = timedRead();
+ }
+ return ret;
+}
+
+int Stream::findMulti( struct Stream::MultiTarget *targets, int tCount) {
+ // any zero length target string automatically matches and would make
+ // a mess of the rest of the algorithm.
+ for (struct MultiTarget *t = targets; t < targets+tCount; ++t) {
+ if (t->len <= 0)
+ return t - targets;
+ }
+
+ while (1) {
+ int c = timedRead();
+ if (c < 0)
+ return -1;
+
+ for (struct MultiTarget *t = targets; t < targets+tCount; ++t) {
+ // the simple case is if we match, deal with that first.
+ if (c == t->str[t->index]) {
+ if (++t->index == t->len)
+ return t - targets;
+ else
+ continue;
+ }
+
+ // if not we need to walk back and see if we could have matched further
+ // down the stream (ie '1112' doesn't match the first position in '11112'
+ // but it will match the second position so we can't just reset the current
+ // index to 0 when we find a mismatch.
+ if (t->index == 0)
+ continue;
+
+ int origIndex = t->index;
+ do {
+ --t->index;
+ // first check if current char works against the new current index
+ if (c != t->str[t->index])
+ continue;
+
+ // if it's the only char then we're good, nothing more to check
+ if (t->index == 0) {
+ t->index++;
+ break;
+ }
+
+ // otherwise we need to check the rest of the found string
+ int diff = origIndex - t->index;
+ size_t i;
+ for (i = 0; i < t->index; ++i) {
+ if (t->str[i] != t->str[i + diff])
+ break;
+ }
+
+ // if we successfully got through the previous loop then our current
+ // index is good.
+ if (i == t->index) {
+ t->index++;
+ break;
+ }
+
+ // otherwise we just try the next index
+ } while (t->index);
+ }
+ }
+ // unreachable
+ return -1;
+}
diff --git a/UsbReceive/UsbReceive/ArduinoCore/src/core/Tone.cpp b/UsbReceive/UsbReceive/ArduinoCore/src/core/Tone.cpp
new file mode 100644
index 0000000000000000000000000000000000000000..b54781133ce67c818bf1cb0df144afe9b70cd8f6
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/src/core/Tone.cpp
@@ -0,0 +1,197 @@
+/*
+ Copyright (c) 2015 Arduino LLC. All right reserved.
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ See the GNU Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#include "Tone.h"
+#include "variant.h"
+
+#define WAIT_TC16_REGS_SYNC(x) while(x->COUNT16.STATUS.bit.SYNCBUSY);
+
+uint32_t toneMaxFrequency = F_CPU / 2;
+uint32_t lastOutputPin = 0xFFFFFFFF;
+
+volatile uint32_t *portToggleRegister;
+volatile uint32_t *portClearRegister;
+volatile uint32_t portBitMask;
+volatile int64_t toggleCount;
+volatile bool toneIsActive = false;
+volatile bool firstTimeRunning = false;
+
+#define TONE_TC TC5
+#define TONE_TC_IRQn TC5_IRQn
+#define TONE_TC_TOP 0xFFFF
+#define TONE_TC_CHANNEL 0
+
+void TC5_Handler (void) __attribute__ ((weak, alias("Tone_Handler")));
+
+static inline void resetTC (Tc* TCx)
+{
+ // Disable TCx
+ TCx->COUNT16.CTRLA.reg &= ~TC_CTRLA_ENABLE;
+ WAIT_TC16_REGS_SYNC(TCx)
+
+ // Reset TCx
+ TCx->COUNT16.CTRLA.reg = TC_CTRLA_SWRST;
+ WAIT_TC16_REGS_SYNC(TCx)
+ while (TCx->COUNT16.CTRLA.bit.SWRST);
+}
+
+void toneAccurateClock (uint32_t accurateSystemCoreClockFrequency)
+{
+ toneMaxFrequency = accurateSystemCoreClockFrequency / 2;
+}
+
+void tone (uint32_t outputPin, uint32_t frequency, uint32_t duration)
+{
+ // Configure interrupt request
+ NVIC_DisableIRQ(TONE_TC_IRQn);
+ NVIC_ClearPendingIRQ(TONE_TC_IRQn);
+
+ if(!firstTimeRunning)
+ {
+ firstTimeRunning = true;
+
+ NVIC_SetPriority(TONE_TC_IRQn, 0);
+
+ // Enable GCLK for TC4 and TC5 (timer counter input clock)
+ GCLK->CLKCTRL.reg = (uint16_t) (GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN_GCLK0 | GCLK_CLKCTRL_ID(GCM_TC4_TC5));
+ while (GCLK->STATUS.bit.SYNCBUSY);
+ }
+
+ if (toneIsActive && (outputPin != lastOutputPin))
+ noTone(lastOutputPin);
+
+ //
+ // Calculate best prescaler divider and comparator value for a 16 bit TC peripheral
+ //
+
+ uint32_t prescalerConfigBits;
+ uint32_t ccValue;
+
+ ccValue = toneMaxFrequency / frequency - 1;
+ prescalerConfigBits = TC_CTRLA_PRESCALER_DIV1;
+
+ uint8_t i = 0;
+
+ while(ccValue > TONE_TC_TOP)
+ {
+ ccValue = toneMaxFrequency / frequency / (2<<i) - 1;
+ i++;
+ if(i == 4 || i == 6 || i == 8) //DIV32 DIV128 and DIV512 are not available
+ i++;
+ }
+
+ switch(i-1)
+ {
+ case 0: prescalerConfigBits = TC_CTRLA_PRESCALER_DIV2; break;
+
+ case 1: prescalerConfigBits = TC_CTRLA_PRESCALER_DIV4; break;
+
+ case 2: prescalerConfigBits = TC_CTRLA_PRESCALER_DIV8; break;
+
+ case 3: prescalerConfigBits = TC_CTRLA_PRESCALER_DIV16; break;
+
+ case 5: prescalerConfigBits = TC_CTRLA_PRESCALER_DIV64; break;
+
+ case 7: prescalerConfigBits = TC_CTRLA_PRESCALER_DIV256; break;
+
+ case 9: prescalerConfigBits = TC_CTRLA_PRESCALER_DIV1024; break;
+
+ default: break;
+ }
+
+ toggleCount = (duration > 0 ? frequency * duration * 2 / 1000UL : -1LL);
+
+ resetTC(TONE_TC);
+
+ uint16_t tmpReg = 0;
+ tmpReg |= TC_CTRLA_MODE_COUNT16; // Set Timer counter Mode to 16 bits
+ tmpReg |= TC_CTRLA_WAVEGEN_MFRQ; // Set TONE_TC mode as match frequency
+ tmpReg |= prescalerConfigBits;
+ TONE_TC->COUNT16.CTRLA.reg |= tmpReg;
+ WAIT_TC16_REGS_SYNC(TONE_TC)
+
+ TONE_TC->COUNT16.CC[TONE_TC_CHANNEL].reg = (uint16_t) ccValue;
+ WAIT_TC16_REGS_SYNC(TONE_TC)
+
+ portToggleRegister = &(PORT->Group[g_APinDescription[outputPin].ulPort].OUTTGL.reg);
+ portClearRegister = &(PORT->Group[g_APinDescription[outputPin].ulPort].OUTCLR.reg);
+ portBitMask = (1ul << g_APinDescription[outputPin].ulPin);
+
+ // Enable the TONE_TC interrupt request
+ TONE_TC->COUNT16.INTENSET.bit.MC0 = 1;
+
+ if (outputPin != lastOutputPin)
+ {
+ lastOutputPin = outputPin;
+ digitalWrite(outputPin, LOW);
+ pinMode(outputPin, OUTPUT);
+ toneIsActive = true;
+ }
+
+ // Enable TONE_TC
+ TONE_TC->COUNT16.CTRLA.reg |= TC_CTRLA_ENABLE;
+ WAIT_TC16_REGS_SYNC(TONE_TC)
+
+ NVIC_EnableIRQ(TONE_TC_IRQn);
+}
+
+void noTone (uint32_t outputPin)
+{
+ /* 'tone' need to run at least once in order to enable GCLK for
+ * the timers used for the tone-functionality. If 'noTone' is called
+ * without ever calling 'tone' before then 'WAIT_TC16_REGS_SYNC(TCx)'
+ * will wait infinitely. The variable 'firstTimeRunning' is set the
+ * 1st time 'tone' is set so it can be used to detect wether or not
+ * 'tone' has been called before.
+ */
+ if(firstTimeRunning)
+ {
+ resetTC(TONE_TC);
+ digitalWrite(outputPin, LOW);
+ toneIsActive = false;
+ }
+}
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void Tone_Handler (void)
+{
+ if (toggleCount != 0)
+ {
+ // Toggle the ouput pin
+ *portToggleRegister = portBitMask;
+
+ if (toggleCount > 0)
+ --toggleCount;
+
+ // Clear the interrupt
+ TONE_TC->COUNT16.INTFLAG.bit.MC0 = 1;
+ }
+ else
+ {
+ resetTC(TONE_TC);
+ *portClearRegister = portBitMask;
+ toneIsActive = false;
+ }
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/UsbReceive/UsbReceive/ArduinoCore/src/core/USB/CDC.cpp b/UsbReceive/UsbReceive/ArduinoCore/src/core/USB/CDC.cpp
new file mode 100644
index 0000000000000000000000000000000000000000..890b6736775d477aef7eed3d843768fa4a75583c
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/src/core/USB/CDC.cpp
@@ -0,0 +1,350 @@
+/*
+ Copyright (c) 2015 Arduino LLC. All right reserved.
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ See the GNU Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#include <Arduino.h>
+#include <Reset.h> // Needed for auto-reset with 1200bps port touch
+#include "CDC.h"
+#include "SAMD21_USBDevice.h"
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <stdint.h>
+
+#ifdef CDC_ENABLED
+
+extern USBDevice_SAMD21G18x usbd;
+
+#define CDC_SERIAL_BUFFER_SIZE 256
+
+/* For information purpose only since RTS is not always handled by the terminal application */
+#define CDC_LINESTATE_DTR 0x01 // Data Terminal Ready
+#define CDC_LINESTATE_RTS 0x02 // Ready to Send
+
+#define CDC_LINESTATE_READY (CDC_LINESTATE_RTS | CDC_LINESTATE_DTR)
+
+typedef struct __attribute__((packed)) {
+ uint32_t dwDTERate;
+ uint8_t bCharFormat;
+ uint8_t bParityType;
+ uint8_t bDataBits;
+ uint8_t lineState;
+} LineInfo;
+
+static volatile LineInfo _usbLineInfo = {
+ 115200, // dWDTERate
+ 0x00, // bCharFormat
+ 0x00, // bParityType
+ 0x08, // bDataBits
+ 0x00 // lineState
+};
+
+static volatile int32_t breakValue = -1;
+
+// CDC
+#define CDC_ACM_INTERFACE pluggedInterface // CDC ACM
+#define CDC_DATA_INTERFACE uint8_t(pluggedInterface + 1) // CDC Data
+#define CDC_ENDPOINT_ACM pluggedEndpoint
+#define CDC_ENDPOINT_OUT pluggedEndpoint + 1
+#define CDC_ENDPOINT_IN pluggedEndpoint + 2
+
+#define CDC_RX CDC_ENDPOINT_OUT
+#define CDC_TX CDC_ENDPOINT_IN
+
+int Serial_::getInterface(uint8_t* interfaceNum)
+{
+ interfaceNum[0] += 2; // uses 2
+ CDCDescriptor _cdcInterface = {
+ D_IAD(pluggedInterface, 2, CDC_COMMUNICATION_INTERFACE_CLASS, CDC_ABSTRACT_CONTROL_MODEL, 0),
+
+ // CDC communication interface
+ D_INTERFACE(CDC_ACM_INTERFACE, 1, CDC_COMMUNICATION_INTERFACE_CLASS, CDC_ABSTRACT_CONTROL_MODEL, 0),
+ D_CDCCS(CDC_HEADER, CDC_V1_10 & 0xFF, (CDC_V1_10>>8) & 0x0FF), // Header (1.10 bcd)
+
+ D_CDCCS4(CDC_ABSTRACT_CONTROL_MANAGEMENT, 6), // SET_LINE_CODING, GET_LINE_CODING, SET_CONTROL_LINE_STATE supported
+ D_CDCCS(CDC_UNION, CDC_ACM_INTERFACE, CDC_DATA_INTERFACE), // Communication interface is master, data interface is slave 0
+ D_CDCCS(CDC_CALL_MANAGEMENT, 1, 1), // Device handles call management (not)
+ D_ENDPOINT(USB_ENDPOINT_IN(CDC_ENDPOINT_ACM), USB_ENDPOINT_TYPE_INTERRUPT, 0x10, 0x10),
+
+ // CDC data interface
+ D_INTERFACE(CDC_DATA_INTERFACE, 2, CDC_DATA_INTERFACE_CLASS, 0, 0),
+ D_ENDPOINT(USB_ENDPOINT_OUT(CDC_ENDPOINT_OUT), USB_ENDPOINT_TYPE_BULK, EPX_SIZE, 0),
+ D_ENDPOINT(USB_ENDPOINT_IN (CDC_ENDPOINT_IN), USB_ENDPOINT_TYPE_BULK, EPX_SIZE, 0)
+ };
+
+ return USBDevice.sendControl(&_cdcInterface, sizeof(_cdcInterface));
+}
+
+int Serial_::getDescriptor(USBSetup& /* setup */)
+{
+ return 0;
+}
+
+static void utox8(uint32_t val, char* s) {
+ for (int i = 0; i < 8; i++) {
+ int d = val & 0XF;
+ val = (val >> 4);
+
+ s[7 - i] = d > 9 ? 'A' + d - 10 : '0' + d;
+ }
+}
+
+uint8_t Serial_::getShortName(char* name) {
+ // from section 9.3.3 of the datasheet
+ #define SERIAL_NUMBER_WORD_0 *(volatile uint32_t*)(0x0080A00C)
+ #define SERIAL_NUMBER_WORD_1 *(volatile uint32_t*)(0x0080A040)
+ #define SERIAL_NUMBER_WORD_2 *(volatile uint32_t*)(0x0080A044)
+ #define SERIAL_NUMBER_WORD_3 *(volatile uint32_t*)(0x0080A048)
+
+ utox8(SERIAL_NUMBER_WORD_0, &name[0]);
+ utox8(SERIAL_NUMBER_WORD_1, &name[8]);
+ utox8(SERIAL_NUMBER_WORD_2, &name[16]);
+ utox8(SERIAL_NUMBER_WORD_3, &name[24]);
+ return 32;
+}
+
+void Serial_::handleEndpoint(int /* ep */) {
+}
+
+bool Serial_::setup(USBSetup& setup)
+{
+ uint8_t requestType = setup.bmRequestType;
+ uint8_t r = setup.bRequest;
+ uint8_t i = setup.wIndex;
+
+ if (CDC_ACM_INTERFACE != i) {
+ return false;
+ }
+
+ if (requestType == REQUEST_DEVICETOHOST_CLASS_INTERFACE)
+ {
+ if (r == CDC_GET_LINE_CODING)
+ {
+ USBDevice.sendControl((void*)&_usbLineInfo, 7);
+ return true;
+ }
+ }
+
+ if (requestType == REQUEST_HOSTTODEVICE_CLASS_INTERFACE)
+ {
+
+ if (r == CDC_SET_LINE_CODING)
+ {
+ USBDevice.recvControl((void*)&_usbLineInfo, 7);
+ }
+
+ if (r == CDC_SET_CONTROL_LINE_STATE)
+ {
+ _usbLineInfo.lineState = setup.wValueL;
+ }
+
+ if (r == CDC_SET_LINE_CODING || r == CDC_SET_CONTROL_LINE_STATE)
+ {
+ // auto-reset into the bootloader is triggered when the port, already
+ // open at 1200 bps, is closed. We check DTR state to determine if host
+ // port is open (bit 0 of lineState).
+ if (_usbLineInfo.dwDTERate == 1200 && (_usbLineInfo.lineState & CDC_LINESTATE_DTR) == 0)
+ {
+ initiateReset(250);
+ }
+ else
+ {
+ cancelReset();
+ }
+ USBDevice.sendZlp(0);
+ }
+
+ if (CDC_SEND_BREAK == r)
+ {
+ breakValue = ((uint16_t)setup.wValueH << 8) | setup.wValueL;
+ USBDevice.sendZlp(0);
+ }
+ return true;
+ }
+ return false;
+}
+
+Serial_::Serial_(USBDeviceClass &_usb) : PluggableUSBModule(3, 2, epType), usb(_usb), stalled(false)
+{
+ epType[0] = USB_ENDPOINT_TYPE_INTERRUPT | USB_ENDPOINT_IN(0);
+ epType[1] = USB_ENDPOINT_TYPE_BULK | USB_ENDPOINT_OUT(0);
+ epType[2] = USB_ENDPOINT_TYPE_BULK | USB_ENDPOINT_IN(0);
+ PluggableUSB().plug(this);
+}
+
+void Serial_::enableInterrupt() {
+ usbd.epBank1EnableTransferComplete(CDC_ENDPOINT_ACM);
+ usbd.epBank0EnableTransferComplete(CDC_ENDPOINT_OUT);
+}
+
+void Serial_::begin(uint32_t /* baud_count */)
+{
+ // uart config is ignored in USB-CDC
+}
+
+void Serial_::begin(uint32_t /* baud_count */, uint8_t /* config */)
+{
+ // uart config is ignored in USB-CDC
+}
+
+void Serial_::end(void)
+{
+ memset((void*)&_usbLineInfo, 0, sizeof(_usbLineInfo));
+}
+
+int _serialPeek = -1;
+
+int Serial_::available(void)
+{
+ return usb.available(CDC_ENDPOINT_OUT) + (_serialPeek != -1);
+}
+
+int Serial_::availableForWrite(void)
+{
+ // return the number of bytes left in the current bank,
+ // always EP size - 1, because bank is flushed on every write
+ return (EPX_SIZE - 1);
+}
+
+int Serial_::peek(void)
+{
+ if (_serialPeek != -1)
+ return _serialPeek;
+ _serialPeek = read();
+ return _serialPeek;
+}
+
+int Serial_::read(void)
+{
+ if (_serialPeek != -1) {
+ int res = _serialPeek;
+ _serialPeek = -1;
+ return res;
+ }
+ return usb.recv(CDC_ENDPOINT_OUT);
+}
+
+size_t Serial_::readBytes(char *buffer, size_t length)
+{
+ size_t count = 0;
+ _startMillis = millis();
+ while (count < length)
+ {
+ uint32_t n = usb.recv(CDC_ENDPOINT_OUT, buffer+count, length-count);
+ if (n == 0 && (millis() - _startMillis) >= _timeout)
+ break;
+ count += n;
+ }
+ return count;
+}
+
+void Serial_::flush(void)
+{
+ usb.flush(CDC_ENDPOINT_IN);
+}
+
+void Serial_::clear(void) {
+ usb.clear(CDC_ENDPOINT_IN);
+}
+
+size_t Serial_::write(const uint8_t *buffer, size_t size)
+{
+ uint32_t r = usb.send(CDC_ENDPOINT_IN, buffer, size);
+
+ if (r > 0) {
+ return r;
+ } else {
+ setWriteError();
+ return 0;
+ }
+}
+
+size_t Serial_::write(uint8_t c) {
+ return write(&c, 1);
+}
+
+// This operator is a convenient way for a sketch to check whether the
+// port has actually been configured and opened by the host (as opposed
+// to just being connected to the host). It can be used, for example, in
+// setup() before printing to ensure that an application on the host is
+// actually ready to receive and display the data.
+// We add a short delay before returning to fix a bug observed by Federico
+// where the port is configured (lineState != 0) but not quite opened.
+Serial_::operator bool()
+{
+ // this is here to avoid spurious opening after upload
+ if (millis() < 500)
+ return false;
+
+ bool result = false;
+
+ if (_usbLineInfo.lineState > 0)
+ {
+ result = true;
+ }
+
+ delay(10);
+ return result;
+}
+
+int32_t Serial_::readBreak() {
+ uint8_t enableInterrupts = ((__get_PRIMASK() & 0x1) == 0);
+
+ // disable interrupts,
+ // to avoid clearing a breakValue that might occur
+ // while processing the current break value
+ __disable_irq();
+
+ int32_t ret = breakValue;
+
+ breakValue = -1;
+
+ if (enableInterrupts) {
+ // re-enable the interrupts
+ __enable_irq();
+ }
+
+ return ret;
+}
+
+unsigned long Serial_::baud() {
+ return _usbLineInfo.dwDTERate;
+}
+
+uint8_t Serial_::stopbits() {
+ return _usbLineInfo.bCharFormat;
+}
+
+uint8_t Serial_::paritytype() {
+ return _usbLineInfo.bParityType;
+}
+
+uint8_t Serial_::numbits() {
+ return _usbLineInfo.bDataBits;
+}
+
+bool Serial_::dtr() {
+ return ((_usbLineInfo.lineState & CDC_LINESTATE_DTR) == CDC_LINESTATE_DTR);
+}
+
+bool Serial_::rts() {
+ return ((_usbLineInfo.lineState & CDC_LINESTATE_RTS) == CDC_LINESTATE_RTS);
+}
+
+Serial_ SerialUSB(USBDevice);
+
+#endif
diff --git a/UsbReceive/UsbReceive/ArduinoCore/src/core/USB/PluggableUSB.cpp b/UsbReceive/UsbReceive/ArduinoCore/src/core/USB/PluggableUSB.cpp
new file mode 100644
index 0000000000000000000000000000000000000000..d90ff2c505a7c651513c587f71afd51f4d107c41
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/src/core/USB/PluggableUSB.cpp
@@ -0,0 +1,124 @@
+/*
+ PluggableUSB.cpp
+ Copyright (c) 2015 Arduino LLC
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#include "USBAPI.h"
+#include "USBDesc.h"
+#include "USBCore.h"
+#include "PluggableUSB.h"
+
+#if defined(USBCON) && defined(PLUGGABLE_USB_ENABLED)
+
+extern uint32_t EndPoints[];
+
+int PluggableUSB_::getInterface(uint8_t* interfaceCount)
+{
+ int sent = 0;
+ PluggableUSBModule* node;
+ for (node = rootNode; node; node = node->next) {
+ int res = node->getInterface(interfaceCount);
+ if (res < 0)
+ return -1;
+ sent += res;
+ }
+ return sent;
+}
+
+int PluggableUSB_::getDescriptor(USBSetup& setup)
+{
+ PluggableUSBModule* node;
+ for (node = rootNode; node; node = node->next) {
+ int ret = node->getDescriptor(setup);
+ // ret!=0 -> request has been processed
+ if (ret)
+ return ret;
+ }
+ return 0;
+}
+
+uint8_t PluggableUSB_::getShortName(char *iSerialNum)
+{
+ PluggableUSBModule* node;
+ uint8_t size = 0;
+ for (node = rootNode; node; node = node->next) {
+ uint8_t len = node->getShortName(iSerialNum);
+ iSerialNum += len;
+ size += len;
+ }
+ *iSerialNum = 0;
+ return size;
+}
+
+bool PluggableUSB_::setup(USBSetup& setup)
+{
+ PluggableUSBModule* node;
+ for (node = rootNode; node; node = node->next) {
+ if (node->setup(setup)) {
+ return true;
+ }
+ }
+ return false;
+}
+
+void PluggableUSB_::handleEndpoint(int ep)
+{
+ PluggableUSBModule* node;
+ for (node = rootNode; node; node = node->next) {
+ node->handleEndpoint(ep);
+ }
+}
+
+bool PluggableUSB_::plug(PluggableUSBModule *node)
+{
+ if ((lastEp + node->numEndpoints) > USB_ENDPOINTS) {
+ return false;
+ }
+
+ if (!rootNode) {
+ rootNode = node;
+ } else {
+ PluggableUSBModule *current = rootNode;
+ while (current->next) {
+ current = current->next;
+ }
+ current->next = node;
+ }
+
+ node->pluggedInterface = lastIf;
+ node->pluggedEndpoint = lastEp;
+ lastIf += node->numInterfaces;
+ for (uint8_t i = 0; i < node->numEndpoints; i++) {
+ EndPoints[lastEp] = node->endpointType[i];
+ lastEp++;
+ }
+ return true;
+ // restart USB layer???
+}
+
+PluggableUSB_& PluggableUSB()
+{
+ static PluggableUSB_ obj;
+ return obj;
+}
+
+PluggableUSB_::PluggableUSB_() : lastIf(0), lastEp(1), rootNode(NULL)
+{
+ // Empty
+}
+
+#endif
\ No newline at end of file
diff --git a/UsbReceive/UsbReceive/ArduinoCore/src/core/USB/USBCore.cpp b/UsbReceive/UsbReceive/ArduinoCore/src/core/USB/USBCore.cpp
new file mode 100644
index 0000000000000000000000000000000000000000..c49cc077dad8f8b9d4521b4bb4d9b21720a39cb5
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/src/core/USB/USBCore.cpp
@@ -0,0 +1,928 @@
+/*
+ Copyright (c) 2016 Arduino LLC. All right reserved.
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ See the GNU Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#if defined(USBCON)
+
+#include <Arduino.h>
+
+#include "SAMD21_USBDevice.h"
+#include "PluggableUSB.h"
+#include "CDC.h"
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <stdint.h>
+#include <limits.h>
+
+USBDevice_SAMD21G18x usbd;
+
+/** Pulse generation counters to keep track of the number of milliseconds remaining for each pulse type */
+#define TX_RX_LED_PULSE_MS 100
+#ifdef PIN_LED_TXL
+static volatile uint8_t txLEDPulse; /**< Milliseconds remaining for data Tx LED pulse */
+#endif
+#ifdef PIN_LED_RXL
+static volatile uint8_t rxLEDPulse; /**< Milliseconds remaining for data Rx LED pulse */
+#endif
+static char isRemoteWakeUpEnabled = 0;
+static char isEndpointHalt = 0;
+
+extern void (*gpf_isr)(void);
+
+// USB_Handler ISR
+extern "C" void UDD_Handler(void) {
+ USBDevice.ISRHandler();
+}
+
+const uint16_t STRING_LANGUAGE[2] = {
+ (3<<8) | (2+2),
+ 0x0409 // English
+};
+
+#ifndef USB_PRODUCT
+// If no product is provided, use USB IO Board
+#define USB_PRODUCT "USB IO Board"
+#endif
+
+const uint8_t STRING_PRODUCT[] = USB_PRODUCT;
+
+#if USB_VID == 0x2341
+# if defined(USB_MANUFACTURER)
+# undef USB_MANUFACTURER
+# endif
+# define USB_MANUFACTURER "Arduino LLC"
+#elif !defined(USB_MANUFACTURER)
+// Fall through to unknown if no manufacturer name was provided in a macro
+# define USB_MANUFACTURER "Unknown"
+#endif
+
+const uint8_t STRING_MANUFACTURER[] = USB_MANUFACTURER;
+
+
+// DEVICE DESCRIPTOR
+const DeviceDescriptor USB_DeviceDescriptorB = D_DEVICE(0xEF, 0x02, 0x01, 64, USB_VID, USB_PID, 0x100, IMANUFACTURER, IPRODUCT, ISERIAL, 1);
+const DeviceDescriptor USB_DeviceDescriptor = D_DEVICE(0x00, 0x00, 0x00, 64, USB_VID, USB_PID, 0x100, IMANUFACTURER, IPRODUCT, ISERIAL, 1);
+
+//==================================================================
+
+volatile uint32_t _usbConfiguration = 0;
+volatile uint32_t _usbSetInterface = 0;
+
+static __attribute__((__aligned__(4))) //__attribute__((__section__(".bss_hram0")))
+uint8_t udd_ep_out_cache_buffer[7][64];
+
+static __attribute__((__aligned__(4))) //__attribute__((__section__(".bss_hram0")))
+uint8_t udd_ep_in_cache_buffer[7][64];
+
+// Some EP are handled using EPHanlders.
+// Possibly all the sparse EP handling subroutines will be
+// converted into reusable EPHandlers in the future.
+static EPHandler *epHandlers[7] = {NULL, NULL, NULL, NULL, NULL, NULL, NULL};
+
+//==================================================================
+
+// Send a USB descriptor string. The string is stored as a
+// plain ASCII string but is sent out as UTF-16 with the
+// correct 2-byte prefix
+bool USBDeviceClass::sendStringDescriptor(const uint8_t *string, uint32_t maxlen)
+{
+ if (maxlen < 2)
+ return false;
+
+ uint8_t* buffer = (uint8_t*)malloc(maxlen);
+ buffer[0] = strlen((const char*)string) * 2 + 2;
+ buffer[1] = 0x03;
+
+ uint8_t i;
+ for (i = 2; i < maxlen && *string; i++) {
+ buffer[i++] = *string++;
+ if (i == maxlen) break;
+ buffer[i] = 0;
+ }
+
+ bool ret = USBDevice.sendControl(buffer, i);
+ free(buffer);
+ return ret;
+}
+
+bool _dry_run = false;
+bool _pack_message = false;
+uint16_t _pack_size = 0;
+uint8_t _pack_buffer[256];
+
+void USBDeviceClass::packMessages(bool val)
+{
+ if (val) {
+ _pack_message = true;
+ _pack_size = 0;
+ } else {
+ _pack_message = false;
+ sendControl(_pack_buffer, _pack_size);
+ }
+}
+
+uint8_t USBDeviceClass::SendInterfaces(uint32_t* total)
+{
+ uint8_t interfaces = 0;
+
+#ifdef PLUGGABLE_USB_ENABLED
+ total[0] += PluggableUSB().getInterface(&interfaces);
+#endif
+
+ return interfaces;
+}
+
+// Construct a dynamic configuration descriptor
+// This really needs dynamic endpoint allocation etc
+uint32_t USBDeviceClass::sendConfiguration(uint32_t maxlen)
+{
+ uint32_t total = 0;
+ // Count and measure interfaces
+ _dry_run = true;
+ uint8_t interfaces = SendInterfaces(&total);
+
+ ConfigDescriptor config = D_CONFIG((uint16_t)(total + sizeof(ConfigDescriptor)), interfaces);
+
+ // Now send them
+ _dry_run = false;
+
+ if (maxlen == sizeof(ConfigDescriptor)) {
+ sendControl(&config, sizeof(ConfigDescriptor));
+ return true;
+ }
+
+ total = 0;
+
+ packMessages(true);
+ sendControl(&config, sizeof(ConfigDescriptor));
+ SendInterfaces(&total);
+ packMessages(false);
+
+ return true;
+}
+
+bool USBDeviceClass::sendDescriptor(USBSetup &setup)
+{
+ uint8_t t = setup.wValueH;
+ uint8_t desc_length = 0;
+ bool _cdcComposite;
+ int ret;
+ const uint8_t *desc_addr = 0;
+
+ if (t == USB_CONFIGURATION_DESCRIPTOR_TYPE)
+ {
+ return USBDevice.sendConfiguration(setup.wLength);
+ }
+
+#ifdef PLUGGABLE_USB_ENABLED
+ ret = PluggableUSB().getDescriptor(setup);
+ if (ret != 0) {
+ return (ret > 0 ? true : false);
+ }
+#endif
+
+ if (t == USB_DEVICE_DESCRIPTOR_TYPE)
+ {
+ if (setup.wLength == 8)
+ _cdcComposite = 1;
+
+ desc_addr = _cdcComposite ? (const uint8_t*)&USB_DeviceDescriptorB : (const uint8_t*)&USB_DeviceDescriptor;
+
+ if (*desc_addr > setup.wLength) {
+ desc_length = setup.wLength;
+ }
+ }
+ else if (USB_STRING_DESCRIPTOR_TYPE == t)
+ {
+ if (setup.wValueL == 0) {
+ desc_addr = (const uint8_t*)&STRING_LANGUAGE;
+ }
+ else if (setup.wValueL == IPRODUCT) {
+ return sendStringDescriptor(STRING_PRODUCT, setup.wLength);
+ }
+ else if (setup.wValueL == IMANUFACTURER) {
+ return sendStringDescriptor(STRING_MANUFACTURER, setup.wLength);
+ }
+ else if (setup.wValueL == ISERIAL) {
+ char name[ISERIAL_MAX_LEN];
+ memset(name, 0, sizeof(name));
+ uint8_t idx = 0;
+#ifdef PLUGGABLE_USB_ENABLED
+ idx += PluggableUSB().getShortName(&name[idx]);
+#endif
+ if (idx > 0) {
+ return sendStringDescriptor((uint8_t*)name, setup.wLength);
+ }
+ }
+ else {
+ return false;
+ }
+ if (*desc_addr > setup.wLength) {
+ desc_length = setup.wLength;
+ }
+ }
+ else
+ {
+ }
+
+ if (desc_addr == 0) {
+ return false;
+ }
+
+ if (desc_length == 0) {
+ desc_length = *desc_addr;
+ }
+
+ sendControl(desc_addr, desc_length);
+
+ return true;
+}
+
+void USBDeviceClass::standby() {
+ usbd.noRunInStandby();
+}
+
+void USBDeviceClass::init()
+{
+#ifdef PIN_LED_TXL
+ txLEDPulse = 0;
+ pinMode(PIN_LED_TXL, OUTPUT);
+ digitalWrite(PIN_LED_TXL, HIGH);
+#endif
+
+#ifdef PIN_LED_RXL
+ rxLEDPulse = 0;
+ pinMode(PIN_LED_RXL, OUTPUT);
+ digitalWrite(PIN_LED_RXL, HIGH);
+#endif
+
+ // Enable USB clock
+ PM->APBBMASK.reg |= PM_APBBMASK_USB;
+
+ // Set up the USB DP/DN pins
+ PORT->Group[0].PINCFG[PIN_PA24G_USB_DM].bit.PMUXEN = 1;
+ PORT->Group[0].PMUX[PIN_PA24G_USB_DM/2].reg &= ~(0xF << (4 * (PIN_PA24G_USB_DM & 0x01u)));
+ PORT->Group[0].PMUX[PIN_PA24G_USB_DM/2].reg |= MUX_PA24G_USB_DM << (4 * (PIN_PA24G_USB_DM & 0x01u));
+ PORT->Group[0].PINCFG[PIN_PA25G_USB_DP].bit.PMUXEN = 1;
+ PORT->Group[0].PMUX[PIN_PA25G_USB_DP/2].reg &= ~(0xF << (4 * (PIN_PA25G_USB_DP & 0x01u)));
+ PORT->Group[0].PMUX[PIN_PA25G_USB_DP/2].reg |= MUX_PA25G_USB_DP << (4 * (PIN_PA25G_USB_DP & 0x01u));
+
+ // Put Generic Clock Generator 0 as source for Generic Clock Multiplexer 6 (USB reference)
+ GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID(6) | // Generic Clock Multiplexer 6
+ GCLK_CLKCTRL_GEN_GCLK0 | // Generic Clock Generator 0 is source
+ GCLK_CLKCTRL_CLKEN;
+ while (GCLK->STATUS.bit.SYNCBUSY)
+ ;
+
+ USB_SetHandler(&UDD_Handler);
+
+ // Reset USB Device
+ usbd.reset();
+
+ usbd.calibrate();
+ usbd.setUSBDeviceMode();
+ usbd.runInStandby();
+ usbd.setFullSpeed();
+
+ // Configure interrupts
+ NVIC_SetPriority((IRQn_Type) USB_IRQn, 0UL);
+ NVIC_EnableIRQ((IRQn_Type) USB_IRQn);
+
+ usbd.enable();
+
+ initialized = true;
+
+#ifdef CDC_ENABLED
+ SerialUSB.begin(0);
+#endif
+}
+
+bool USBDeviceClass::attach()
+{
+ if (!initialized)
+ return false;
+
+ usbd.attach();
+ usbd.enableEndOfResetInterrupt();
+ usbd.enableStartOfFrameInterrupt();
+
+ _usbConfiguration = 0;
+ return true;
+}
+
+void USBDeviceClass::setAddress(uint32_t addr)
+{
+ usbd.epBank1SetByteCount(0, 0);
+ usbd.epBank1AckTransferComplete(0);
+
+ // RAM buffer is full, we can send data (IN)
+ usbd.epBank1SetReady(0);
+
+ // Wait for transfer to complete
+ while (!usbd.epBank1IsTransferComplete(0)) {}
+
+ // Set USB address to addr
+ USB->DEVICE.DADD.bit.DADD = addr; // Address
+ USB->DEVICE.DADD.bit.ADDEN = 1; // Enable
+}
+
+bool USBDeviceClass::detach()
+{
+ if (!initialized)
+ return false;
+ usbd.detach();
+ return true;
+}
+
+bool USBDeviceClass::end() {
+ if (!initialized)
+ return false;
+ usbd.disable();
+ return true;
+}
+
+bool USBDeviceClass::configured()
+{
+ return _usbConfiguration != 0;
+}
+
+bool USBDeviceClass::handleClassInterfaceSetup(USBSetup& setup)
+{
+#if defined(PLUGGABLE_USB_ENABLED)
+ bool ret = PluggableUSB().setup(setup);
+ if ( ret == false) {
+ sendZlp(0);
+ }
+ return ret;
+#endif
+
+ return false;
+}
+
+uint32_t EndPoints[] =
+{
+ USB_ENDPOINT_TYPE_CONTROL,
+
+#ifdef PLUGGABLE_USB_ENABLED
+ //allocate 9 endpoints and remove const so they can be changed by the user
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+#endif
+};
+#define EP_ARRAY_SIZE (sizeof(EndPoints)/sizeof(EndPoints[0]))
+
+void USBDeviceClass::initEndpoints() {
+ for (uint8_t i = 1; (i < EP_ARRAY_SIZE) && (EndPoints[i] != 0); i++) {
+ initEP(i, EndPoints[i]);
+ }
+}
+
+void USBDeviceClass::initEP(uint32_t ep, uint32_t config)
+{
+ if (config == (USB_ENDPOINT_TYPE_INTERRUPT | USB_ENDPOINT_IN(0)))
+ {
+ usbd.epBank1SetSize(ep, 64);
+ usbd.epBank1SetAddress(ep, &udd_ep_in_cache_buffer[ep]);
+ usbd.epBank1SetType(ep, 4); // INTERRUPT IN
+ }
+ else if (config == (USB_ENDPOINT_TYPE_BULK | USB_ENDPOINT_OUT(0)))
+ {
+ if (epHandlers[ep] != NULL) {
+ delete (DoubleBufferedEPOutHandler*)epHandlers[ep];
+ }
+ epHandlers[ep] = new DoubleBufferedEPOutHandler(usbd, ep);
+ }
+ else if (config == (USB_ENDPOINT_TYPE_BULK | USB_ENDPOINT_IN(0)))
+ {
+ usbd.epBank1SetSize(ep, 64);
+ usbd.epBank1SetAddress(ep, &udd_ep_in_cache_buffer[ep]);
+ usbd.epBank1SetType(ep, 3); // BULK IN
+ }
+ else if (config == USB_ENDPOINT_TYPE_CONTROL)
+ {
+ // Setup Control OUT
+ usbd.epBank0SetSize(ep, 64);
+ usbd.epBank0SetAddress(ep, &udd_ep_out_cache_buffer[ep]);
+ usbd.epBank0SetType(ep, 1); // CONTROL OUT / SETUP
+
+ // Setup Control IN
+ usbd.epBank1SetSize(ep, 64);
+ usbd.epBank1SetAddress(ep, &udd_ep_in_cache_buffer[ep]);
+ usbd.epBank1SetType(ep, 1); // CONTROL IN
+
+ // Release OUT EP
+ usbd.epReleaseOutBank0(ep, 64);
+ }
+}
+
+void USBDeviceClass::flush(uint32_t ep)
+{
+ if (available(ep)) {
+ // RAM buffer is full, we can send data (IN)
+ usbd.epBank1SetReady(ep);
+
+ // Clear the transfer complete flag
+ usbd.epBank1AckTransferComplete(ep);
+ }
+}
+
+void USBDeviceClass::clear(uint32_t ep) {
+ usbd.epBank1SetAddress(ep, &udd_ep_in_cache_buffer[ep]);
+ usbd.epBank1SetByteCount(ep, 0);
+
+ // Clear the transfer complete flag
+ usbd.epBank1AckTransferComplete(ep);
+
+ // RAM buffer is full, we can send data (IN)
+ usbd.epBank1SetReady(ep);
+}
+
+void USBDeviceClass::stall(uint32_t ep)
+{
+ // TODO: test
+ // TODO: use .bit. notation
+
+ // Stall endpoint
+ USB->DEVICE.DeviceEndpoint[ep].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_STALLRQ(2);
+}
+
+bool USBDeviceClass::connected()
+{
+ // Count frame numbers
+ uint8_t f = USB->DEVICE.FNUM.bit.FNUM;
+ //delay(3);
+ return f != USB->DEVICE.FNUM.bit.FNUM;
+}
+
+
+uint32_t USBDeviceClass::recvControl(void *_data, uint32_t len)
+{
+ uint8_t *data = reinterpret_cast<uint8_t *>(_data);
+
+ //usbd.epBank0AckSetupReceived(0);
+ uint32_t read = armRecvCtrlOUT(0);
+ if (read > len)
+ read = len;
+ //while (!usbd.epBank0AckTransferComplete(0)) {}
+ uint8_t *buffer = udd_ep_out_cache_buffer[0];
+ for (uint32_t i=0; i<len; i++) {
+ data[i] = buffer[i];
+ }
+
+ return read;
+}
+
+// Number of bytes, assumes a rx endpoint
+uint32_t USBDeviceClass::available(uint32_t ep)
+{
+ if (epHandlers[ep]) {
+ return epHandlers[ep]->available();
+ } else {
+ return usbd.epBank0ByteCount(ep);
+ }
+}
+
+// Non Blocking receive
+// Return number of bytes read
+uint32_t USBDeviceClass::recv(uint32_t ep, void *_data, uint32_t len)
+{
+ if (!_usbConfiguration)
+ return -1;
+
+#ifdef PIN_LED_RXL
+ if (rxLEDPulse == 0)
+ digitalWrite(PIN_LED_RXL, LOW);
+
+ rxLEDPulse = TX_RX_LED_PULSE_MS;
+#endif
+
+ if (epHandlers[ep]) {
+ return epHandlers[ep]->recv(_data, len);
+ }
+
+ if (available(ep) < len)
+ len = available(ep);
+
+ usbd.epBank0SetByteCount(ep, 0);
+ usbd.epBank0DisableTransferComplete(ep);
+
+ memcpy(_data, udd_ep_out_cache_buffer[ep], len);
+
+ // release empty buffer
+ if (len && !available(ep)) {
+ // The RAM Buffer is empty: we can receive data
+ usbd.epBank0ResetReady(ep);
+
+ // Clear Transfer complete 0 flag
+ usbd.epBank0AckTransferComplete(ep);
+
+ // Enable Transfer complete 0 interrupt
+ usbd.epBank0EnableTransferComplete(ep);
+ }
+
+ return len;
+}
+
+// Recv 1 byte if ready
+int USBDeviceClass::recv(uint32_t ep)
+{
+ uint8_t c;
+ if (recv(ep, &c, 1) != 1) {
+ return -1;
+ } else {
+ return c;
+ }
+}
+
+uint8_t USBDeviceClass::armRecvCtrlOUT(uint32_t ep)
+{
+ // Get endpoint configuration from setting register
+ usbd.epBank0SetAddress(ep, &udd_ep_out_cache_buffer[ep]);
+ /* Atmel-42181G–SAM-D21_Datasheet–09/2015 / Page 806
+ *
+ * For OUT endpoints, MULTI_PACKET_SIZE holds the total
+ * data size for the complete transfer. This value must
+ * be a multiple of the maximum packet size.
+ *
+ * Since SIZE is 64 (see 'USBDeviceClass::initEP') for
+ * all endpoints MULTI_PACKET_SIZE should not be set to
+ * a value < SIZE, this means at least to 64.
+ */
+ usbd.epBank0SetMultiPacketSize(ep, 64);
+ usbd.epBank0SetByteCount(ep, 0);
+
+ usbd.epBank0ResetReady(ep);
+
+ // Wait OUT
+ while (!usbd.epBank0IsReady(ep)) {}
+ while (!usbd.epBank0IsTransferComplete(ep)) {}
+ return usbd.epBank0ByteCount(ep);
+}
+
+// Timeout for sends
+#define TX_TIMEOUT_MS 70
+
+static char LastTransmitTimedOut[7] = {
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0
+};
+
+// Blocking Send of data to an endpoint
+uint32_t USBDeviceClass::send(uint32_t ep, const void *data, uint32_t len)
+{
+ uint32_t written = 0;
+ uint32_t length = 0;
+
+ if (!_usbConfiguration)
+ return -1;
+ if (len > 16384)
+ return -1;
+
+#ifdef PIN_LED_TXL
+ if (txLEDPulse == 0)
+ digitalWrite(PIN_LED_TXL, LOW);
+
+ txLEDPulse = TX_RX_LED_PULSE_MS;
+#endif
+
+ // Flash area
+ while (len != 0)
+ {
+ if (usbd.epBank1IsReady(ep)) {
+ // previous transfer is still not complete
+
+ // convert the timeout from microseconds to a number of times through
+ // the wait loop; it takes (roughly) 23 clock cycles per iteration.
+ uint32_t timeout = microsecondsToClockCycles(TX_TIMEOUT_MS * 1000) / 23;
+
+ // Wait for (previous) transfer to complete
+ // inspired by Paul Stoffregen's work on Teensy
+ while (!usbd.epBank1IsTransferComplete(ep)) {
+ if (LastTransmitTimedOut[ep] || timeout-- == 0) {
+ LastTransmitTimedOut[ep] = 1;
+
+ // set byte count to zero, so that ZLP is sent
+ // instead of stale data
+ usbd.epBank1SetByteCount(ep, 0);
+ return -1;
+ }
+ }
+ }
+
+ LastTransmitTimedOut[ep] = 0;
+
+ if (len >= EPX_SIZE) {
+ usbd.epBank1EnableAutoZLP(ep);
+ length = EPX_SIZE;
+ } else {
+ length = len;
+ }
+
+ /* memcopy could be safer in multi threaded environment */
+ memcpy(&udd_ep_in_cache_buffer[ep], data, length);
+
+ usbd.epBank1SetAddress(ep, &udd_ep_in_cache_buffer[ep]);
+ usbd.epBank1SetByteCount(ep, length);
+
+ // Clear the transfer complete flag
+ usbd.epBank1AckTransferComplete(ep);
+
+ // RAM buffer is full, we can send data (IN)
+ usbd.epBank1SetReady(ep);
+
+ written += length;
+ len -= length;
+ data = (char *)data + length;
+ }
+ return written;
+}
+
+uint32_t USBDeviceClass::armSend(uint32_t ep, const void* data, uint32_t len)
+{
+ memcpy(&udd_ep_in_cache_buffer[ep], data, len);
+
+ // Get endpoint configuration from setting register
+ usbd.epBank1SetAddress(ep, &udd_ep_in_cache_buffer[ep]);
+ usbd.epBank1SetMultiPacketSize(ep, 0);
+ usbd.epBank1SetByteCount(ep, len);
+
+ return len;
+}
+
+uint32_t USBDeviceClass::sendControl(const void* _data, uint32_t len)
+{
+ const uint8_t *data = reinterpret_cast<const uint8_t *>(_data);
+ uint32_t length = len;
+ uint32_t sent = 0;
+ uint32_t pos = 0;
+
+ if (_dry_run == true)
+ return length;
+
+ if (_pack_message == true) {
+ memcpy(&_pack_buffer[_pack_size], data, len);
+ _pack_size += len;
+ return length;
+ }
+
+ while (len > 0)
+ {
+ sent = armSend(EP0, data + pos, len);
+ pos += sent;
+ len -= sent;
+ }
+
+ return length;
+}
+
+void USBDeviceClass::sendZlp(uint32_t ep)
+{
+ // Set the byte count as zero
+ usbd.epBank1SetByteCount(ep, 0);
+}
+
+bool USBDeviceClass::handleStandardSetup(USBSetup &setup)
+{
+ switch (setup.bRequest) {
+ case GET_STATUS:
+ if (setup.bmRequestType == 0) // device
+ {
+ // Send the device status
+ // TODO: Check current configuration for power mode (if device is configured)
+ // TODO: Check if remote wake-up is enabled
+ uint8_t buff[] = { 0, 0 };
+ armSend(0, buff, 2);
+ return true;
+ }
+ // if( setup.bmRequestType == 2 ) // Endpoint:
+ else
+ {
+ // Send the endpoint status
+ // Check if the endpoint if currently halted
+ uint8_t buff[] = { 0, 0 };
+ if (isEndpointHalt == 1)
+ buff[0] = 1;
+ armSend(0, buff, 2);
+ return true;
+ }
+
+ case CLEAR_FEATURE:
+ // Check which is the selected feature
+ if (setup.wValueL == 1) // DEVICEREMOTEWAKEUP
+ {
+ // Enable remote wake-up and send a ZLP
+ uint8_t buff[] = { 0, 0 };
+ if (isRemoteWakeUpEnabled == 1)
+ buff[0] = 1;
+ armSend(0, buff, 2);
+ return true;
+ }
+ else // if( setup.wValueL == 0) // ENDPOINTHALT
+ {
+ isEndpointHalt = 0;
+ sendZlp(0);
+ return true;
+ }
+
+ case SET_FEATURE:
+ // Check which is the selected feature
+ if (setup.wValueL == 1) // DEVICEREMOTEWAKEUP
+ {
+ // Enable remote wake-up and send a ZLP
+ isRemoteWakeUpEnabled = 1;
+ uint8_t buff[] = { 0 };
+ armSend(0, buff, 1);
+ return true;
+ }
+ if (setup.wValueL == 0) // ENDPOINTHALT
+ {
+ // Halt endpoint
+ isEndpointHalt = 1;
+ sendZlp(0);
+ return true;
+ }
+ break;
+
+ case SET_ADDRESS:
+ setAddress(setup.wValueL);
+ return true;
+
+ case GET_DESCRIPTOR:
+ return sendDescriptor(setup);
+
+ case SET_DESCRIPTOR:
+ return false;
+
+ case GET_CONFIGURATION:
+ armSend(0, (void*)&_usbConfiguration, 1);
+ return true;
+
+ case SET_CONFIGURATION:
+ if (REQUEST_DEVICE == (setup.bmRequestType & REQUEST_RECIPIENT)) {
+
+ initEndpoints();
+ _usbConfiguration = setup.wValueL;
+
+ #ifdef CDC_ENABLED
+ SerialUSB.enableInterrupt();
+ #endif
+
+ sendZlp(0);
+ return true;
+ } else {
+ return false;
+ }
+
+ case GET_INTERFACE:
+ armSend(0, (void*)&_usbSetInterface, 1);
+ return true;
+
+ case SET_INTERFACE:
+ _usbSetInterface = setup.wValueL;
+ sendZlp(0);
+ return true;
+
+ default:
+ return true;
+ }
+ return true;
+}
+
+void USBDeviceClass::ISRHandler()
+{
+ if (_pack_message == true) {
+ return;
+ }
+
+ // End-Of-Reset
+ if (usbd.isEndOfResetInterrupt())
+ {
+ usbd.ackEndOfResetInterrupt();
+
+ // Configure EP 0
+ initEP(0, USB_ENDPOINT_TYPE_CONTROL);
+
+ // Enable Setup-Received interrupt
+ usbd.epBank0EnableSetupReceived(0);
+
+ _usbConfiguration = 0;
+ }
+
+ // Start-Of-Frame
+ if (usbd.isStartOfFrameInterrupt())
+ {
+ usbd.ackStartOfFrameInterrupt();
+
+ // check whether the one-shot period has elapsed. if so, turn off the LED
+#ifdef PIN_LED_TXL
+ if (txLEDPulse > 0) {
+ txLEDPulse--;
+ if (txLEDPulse == 0)
+ digitalWrite(PIN_LED_TXL, HIGH);
+ }
+#endif
+
+#ifdef PIN_LED_RXL
+ if (rxLEDPulse > 0) {
+ rxLEDPulse--;
+ if (rxLEDPulse == 0)
+ digitalWrite(PIN_LED_RXL, HIGH);
+ }
+#endif
+ }
+
+ /* Remove any stall requests for endpoint #0 */
+ if (usbd.epBank0IsStalled(0)) { usbd.epBank0DisableStalled(0); }
+
+ // Endpoint 0 Received Setup interrupt
+ if (usbd.epBank0IsSetupReceived(0))
+ {
+ /* Retrieve received endpoint #0 data from buffer */
+ USBSetup setup;
+ memcpy(&setup, udd_ep_out_cache_buffer[0], sizeof(USBSetup));
+
+ /* Tell the USB hardware that we are ready to receive more data for endpoint #0 and also reset the byte count
+ * for endpoint #0 - the clearing seems to be necessary for the code to function correctly, although the datasheet
+ * is not clear on the subject.
+ *
+ * Atmel-42181G–SAM-D21_Datasheet–09/2015 / Page 806
+ * For IN endpoints, BYTE_COUNT holds the number of bytes to be sent in the next IN transaction.
+ * For OUT endpoint or SETUP endpoints, BYTE_COUNT holds the number of bytes received upon the last OUT or SETUP transaction.
+ */
+ usbd.epBank0SetByteCount(0, 0);
+ usbd.epBank0ResetReady(0);
+
+ bool ok;
+ if (REQUEST_STANDARD == (setup.bmRequestType & REQUEST_TYPE)) {
+ // Standard Requests
+ ok = handleStandardSetup(setup);
+ } else {
+ // Class Interface Requests
+ ok = handleClassInterfaceSetup(setup);
+ }
+
+ if (ok) {
+ usbd.epBank1SetReady(0);
+ } else {
+ stall(0);
+ }
+
+ if (usbd.epBank1IsStalled(0))
+ {
+ // Remove stall request
+ usbd.epBank1DisableStalled(0);
+ }
+ } // end Received Setup handler
+ usbd.epAckPendingInterrupts(0);
+
+ for (int ep = 1; ep < USB_EPT_NUM; ep++) {
+ // Endpoint Transfer Complete (0/1) Interrupt
+ if (usbd.epHasPendingInterrupts(ep)) {
+ if (epHandlers[ep]) {
+ epHandlers[ep]->handleEndpoint();
+ } else {
+ #if defined(PLUGGABLE_USB_ENABLED)
+ PluggableUSB().handleEndpoint(ep);
+ usbd.epAckPendingInterrupts(ep);
+ #endif
+ }
+ }
+ }
+}
+
+/*
+ * USB Device instance
+ * -------------------
+ */
+
+// USBDevice class instance
+USBDeviceClass USBDevice;
+
+#endif
diff --git a/UsbReceive/UsbReceive/ArduinoCore/src/core/USB/samd21_host.c b/UsbReceive/UsbReceive/ArduinoCore/src/core/USB/samd21_host.c
new file mode 100644
index 0000000000000000000000000000000000000000..64255c04f8b2627c3ad52f7026710defc3a03808
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/src/core/USB/samd21_host.c
@@ -0,0 +1,512 @@
+/*
+ Copyright (c) 2014 Arduino LLC. All right reserved.
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ See the GNU Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#include "Arduino.h"
+#include "USB_host.h"
+#include "samd21_host.h"
+#include "wiring_private.h"
+
+#define HOST_DEFINED
+#ifdef HOST_DEFINED
+
+//#define TRACE_UOTGHS_HOST(x) x
+#define TRACE_UOTGHS_HOST(x)
+
+// Handle UOTGHS Host driver state
+static uhd_vbus_state_t uhd_state = UHD_STATE_NO_VBUS;
+
+__attribute__((__aligned__(4))) volatile UsbHostDescriptor usb_pipe_table[USB_EPT_NUM];
+
+extern void (*gpf_isr)(void);
+
+
+// NVM Software Calibration Area Mapping
+// USB TRANSN calibration value. Should be written to the USB PADCAL register.
+#define NVM_USB_PAD_TRANSN_POS 45
+#define NVM_USB_PAD_TRANSN_SIZE 5
+// USB TRANSP calibration value. Should be written to the USB PADCAL register.
+#define NVM_USB_PAD_TRANSP_POS 50
+#define NVM_USB_PAD_TRANSP_SIZE 5
+// USB TRIM calibration value. Should be written to the USB PADCAL register.
+#define NVM_USB_PAD_TRIM_POS 55
+#define NVM_USB_PAD_TRIM_SIZE 3
+
+/**
+ * \brief Initialize the SAMD21 host driver.
+ */
+void UHD_Init(void)
+{
+ uint32_t pad_transn;
+ uint32_t pad_transp;
+ uint32_t pad_trim;
+
+ USB_SetHandler(&UHD_Handler);
+
+ /* Enable USB clock */
+ PM->APBBMASK.reg |= PM_APBBMASK_USB;
+
+ /* Set up the USB DP/DM pins */
+ pinPeripheral( PIN_USB_DM, PIO_COM );
+ pinPeripheral( PIN_USB_DP, PIO_COM );
+// PORT->Group[0].PINCFG[PIN_PA24G_USB_DM].bit.PMUXEN = 1;
+// PORT->Group[0].PMUX[PIN_PA24G_USB_DM/2].reg &= ~(0xF << (4 * (PIN_PA24G_USB_DM & 0x01u)));
+// PORT->Group[0].PMUX[PIN_PA24G_USB_DM/2].reg |= MUX_PA24G_USB_DM << (4 * (PIN_PA24G_USB_DM & 0x01u));
+// PORT->Group[0].PINCFG[PIN_PA25G_USB_DP].bit.PMUXEN = 1;
+// PORT->Group[0].PMUX[PIN_PA25G_USB_DP/2].reg &= ~(0xF << (4 * (PIN_PA25G_USB_DP & 0x01u)));
+// PORT->Group[0].PMUX[PIN_PA25G_USB_DP/2].reg |= MUX_PA25G_USB_DP << (4 * (PIN_PA25G_USB_DP & 0x01u));
+
+ /* ----------------------------------------------------------------------------------------------
+ * Put Generic Clock Generator 0 as source for Generic Clock Multiplexer 6 (USB reference)
+ */
+ GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID(6) | // Generic Clock Multiplexer 6
+ GCLK_CLKCTRL_GEN_GCLK0 | // Generic Clock Generator 0 is source
+ GCLK_CLKCTRL_CLKEN;
+
+ while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY)
+ {
+ /* Wait for synchronization */
+ }
+
+ /* Reset */
+ USB->HOST.CTRLA.bit.SWRST = 1;
+ while (USB->HOST.SYNCBUSY.bit.SWRST)
+ {
+ /* Sync wait */
+ }
+
+ // uhd_enable();
+ USB->DEVICE.CTRLA.reg |= USB_CTRLA_ENABLE | USB_CTRLA_MODE;
+ uhd_force_host_mode();
+ while (USB->HOST.SYNCBUSY.reg == USB_SYNCBUSY_ENABLE);
+
+ /* Load Pad Calibration */
+ pad_transn = (*((uint32_t *)(NVMCTRL_OTP4) // Non-Volatile Memory Controller
+ + (NVM_USB_PAD_TRANSN_POS / 32))
+ >> (NVM_USB_PAD_TRANSN_POS % 32))
+ & ((1 << NVM_USB_PAD_TRANSN_SIZE) - 1);
+
+ if (pad_transn == 0x1F) // maximum value (31)
+ {
+ pad_transn = 5;
+ }
+
+ USB->HOST.PADCAL.bit.TRANSN = pad_transn;
+
+ pad_transp = (*((uint32_t *)(NVMCTRL_OTP4)
+ + (NVM_USB_PAD_TRANSP_POS / 32))
+ >> (NVM_USB_PAD_TRANSP_POS % 32))
+ & ((1 << NVM_USB_PAD_TRANSP_SIZE) - 1);
+
+ if (pad_transp == 0x1F) // maximum value (31)
+ {
+ pad_transp = 29;
+ }
+
+ USB->HOST.PADCAL.bit.TRANSP = pad_transp;
+
+ pad_trim = (*((uint32_t *)(NVMCTRL_OTP4)
+ + (NVM_USB_PAD_TRIM_POS / 32))
+ >> (NVM_USB_PAD_TRIM_POS % 32))
+ & ((1 << NVM_USB_PAD_TRIM_SIZE) - 1);
+
+ if (pad_trim == 0x7) // maximum value (7)
+ {
+ pad_trim = 3;
+ }
+
+ USB->HOST.PADCAL.bit.TRIM = pad_trim;
+
+
+ /* Set the configuration */
+ uhd_run_in_standby();
+ // Set address of USB SRAM
+ USB->HOST.DESCADD.reg = (uint32_t)(&usb_pipe_table[0]);
+ // For USB_SPEED_FULL
+ uhd_force_full_speed();
+ memset((void *)usb_pipe_table, 0, sizeof(usb_pipe_table));
+
+ uhd_state = UHD_STATE_NO_VBUS;
+
+ // Put VBUS on USB port
+ #ifdef PIN_USB_HOST_ENABLE
+ pinMode( PIN_USB_HOST_ENABLE, OUTPUT );
+ digitalWrite( PIN_USB_HOST_ENABLE, HIGH );
+ #endif
+
+ uhd_enable_connection_int();
+
+ USB->HOST.INTENSET.reg = USB_HOST_INTENSET_DCONN;
+ USB->HOST.INTENSET.reg = USB_HOST_INTENSET_WAKEUP;
+ USB->HOST.INTENSET.reg = USB_HOST_INTENSET_DDISC;
+
+ USB->HOST.CTRLB.bit.VBUSOK = 1;
+
+ // Configure interrupts
+ NVIC_SetPriority((IRQn_Type)USB_IRQn, 0UL);
+ NVIC_EnableIRQ((IRQn_Type)USB_IRQn);
+}
+
+
+/**
+ * \brief Interrupt sub routine for USB Host state machine management.
+ */
+void UHD_Handler(void)
+{
+ uint16_t flags;
+
+ if (USB->HOST.CTRLA.bit.MODE) {
+ /*host mode ISR */
+
+ /* get interrupt flags */
+ flags = USB->HOST.INTFLAG.reg;
+
+ /* host SOF interrupt */
+ if (flags & USB_HOST_INTFLAG_HSOF)
+ {
+ /* clear the flag */
+ USB->HOST.INTFLAG.reg = USB_HOST_INTFLAG_HSOF;
+ uhd_state = UHD_STATE_CONNECTED;
+ return;
+ }
+
+ /* host reset interrupt */
+ if (flags & USB_HOST_INTFLAG_RST)
+ {
+ /* clear the flag */
+ USB->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RST;
+ uhd_state = UHD_STATE_DISCONNECTED; //UHD_STATE_ERROR;
+ return;
+ }
+
+ /* host upstream resume interrupts */
+ if (flags & USB_HOST_INTFLAG_UPRSM)
+ {
+ /* clear the flags */
+ USB->HOST.INTFLAG.reg = USB_HOST_INTFLAG_UPRSM;
+ uhd_state = UHD_STATE_DISCONNECTED; //UHD_STATE_ERROR;
+ return;
+ }
+
+ /* host downstream resume interrupts */
+ if (flags & USB_HOST_INTFLAG_DNRSM)
+ {
+ /* clear the flags */
+ USB->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DNRSM;
+ uhd_state = UHD_STATE_DISCONNECTED; //UHD_STATE_ERROR;
+ return;
+ }
+
+ /* host wakeup interrupts */
+ if (flags & USB_HOST_INTFLAG_WAKEUP)
+ {
+ /* clear the flags */
+ USB->HOST.INTFLAG.reg = USB_HOST_INTFLAG_WAKEUP;
+ uhd_state = UHD_STATE_CONNECTED; //UHD_STATE_ERROR;
+ return;
+ }
+
+ /* host ram access interrupt */
+ if (flags & USB_HOST_INTFLAG_RAMACER)
+ {
+ /* clear the flag */
+ USB->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RAMACER;
+ uhd_state = UHD_STATE_DISCONNECTED; //UHD_STATE_ERROR;
+ return;
+ }
+
+ /* host connect interrupt */
+ if (flags & USB_HOST_INTFLAG_DCONN)
+ {
+ TRACE_UOTGHS_HOST(printf(">>> UHD_ISR : Connection INT\r\n");
+ )
+ /* clear the flag */
+ uhd_ack_connection();
+ uhd_disable_connection_int();
+ uhd_ack_disconnection();
+ uhd_enable_disconnection_int();
+ //uhd_enable_sof();
+ uhd_state = UHD_STATE_CONNECTED;
+ return;
+ }
+
+ /* host disconnect interrupt */
+ if (flags & USB_HOST_INTFLAG_DDISC)
+ {
+ TRACE_UOTGHS_HOST(printf(">>> UHD_ISR : Disconnection INT\r\n");
+ )
+ /* clear the flag */
+ uhd_ack_disconnection();
+ uhd_disable_disconnection_int();
+ // Stop reset signal, in case of disconnection during reset
+ uhd_stop_reset();
+ // Disable wakeup/resumes interrupts,
+ // in case of disconnection during suspend mode
+ uhd_ack_connection();
+ uhd_enable_connection_int();
+ uhd_state = UHD_STATE_DISCONNECTED;
+ return;
+ }
+ }
+ else {
+ while(1);
+ }
+}
+
+
+
+/**
+ * \brief Get VBUS state.
+ *
+ * \return VBUS status.
+ */
+uhd_vbus_state_t UHD_GetVBUSState(void)
+{
+ return uhd_state;
+}
+
+
+/**
+ * \brief Allocate FIFO for pipe 0.
+ *
+ * \param ul_add Address of remote device for pipe 0.
+ * \param ul_ep_size Actual size of the FIFO in bytes.
+ *
+ * \retval 0 success.
+ * \retval 1 error.
+ */
+uint32_t UHD_Pipe0_Alloc(uint32_t ul_add , uint32_t ul_ep_size)
+{
+ (void)(ul_add); // Unused argument
+
+ if( USB->HOST.STATUS.reg & USB_HOST_STATUS_SPEED(1) )
+ ul_ep_size = USB_PCKSIZE_SIZE_8_BYTES; // Low Speed
+ else
+ ul_ep_size = USB_PCKSIZE_SIZE_64_BYTES; // Full Speed
+
+ USB->HOST.HostPipe[0].PCFG.bit.PTYPE = 1; //USB_HOST_PCFG_PTYPE_CTRL;
+ usb_pipe_table[0].HostDescBank[0].CTRL_PIPE.bit.PEPNUM = 0;
+ usb_pipe_table[0].HostDescBank[0].PCKSIZE.bit.SIZE = ul_ep_size;
+
+ return 0;
+}
+
+
+/**
+ * \brief Allocate a new pipe.
+ *
+ * \note UOTGHS maximum pipe number is limited to 10, meaning that only a limited
+ * amount of devices can be connected. Unfortunately, using only one pipe shared accross
+ * various endpoints and devices is not possible because the UOTGHS IP does not allow to
+ * change the data toggle value through register interface.
+ *
+ * \param ul_dev_addr Address of remote device.
+ * \param ul_dev_ep Targeted endpoint of remote device.
+ * \param ul_type Pipe type.
+ * \param ul_dir Pipe direction.
+ * \param ul_maxsize Pipe size.
+ * \param ul_interval Polling interval (if applicable to pipe type).
+ * \param ul_nb_bank Number of banks associated with this pipe.
+ *
+ * \return 1.
+ */
+uint32_t UHD_Pipe_Alloc(uint32_t ul_dev_addr, uint32_t ul_dev_ep, uint32_t ul_type, uint32_t ul_dir, uint32_t ul_maxsize, uint32_t ul_interval, uint32_t ul_nb_bank)
+{
+ /* set pipe config */
+ USB->HOST.HostPipe[ul_dev_ep].PCFG.bit.BK = ul_nb_bank;
+ // PTYPE:
+ USB->HOST.HostPipe[ul_dev_ep].PCFG.reg &= ~USB_HOST_PCFG_MASK; // USB->HOST.HostPipe[0].PCFG.bit.PTYPE = 1; //USB_HOST_PCFG_PTYPE_CTRL;
+ USB->HOST.HostPipe[ul_dev_ep].PCFG.reg |= ul_type;
+ USB->HOST.HostPipe[ul_dev_ep].BINTERVAL.reg = ul_interval;
+
+ if (ul_dir & USB_EP_DIR_IN)
+ {
+ USB->HOST.HostPipe[ul_dev_ep].PCFG.bit.PTOKEN = USB_HOST_PCFG_PTOKEN_IN;
+ USB->HOST.HostPipe[ul_dev_ep].PSTATUSSET.reg = USB_HOST_PSTATUSSET_BK0RDY;
+ }
+ else
+ {
+ USB->HOST.HostPipe[ul_dev_ep].PCFG.bit.PTOKEN = USB_HOST_PCFG_PTOKEN_OUT;
+ USB->HOST.HostPipe[ul_dev_ep].PSTATUSCLR.reg = USB_HOST_PSTATUSCLR_BK0RDY;
+ }
+
+ if( USB->HOST.STATUS.reg & USB_HOST_STATUS_SPEED(1) )
+ ul_maxsize = USB_PCKSIZE_SIZE_8_BYTES; // Low Speed
+ else
+ ul_maxsize = USB_PCKSIZE_SIZE_64_BYTES; // Full Speed
+
+ memset((uint8_t *)&usb_pipe_table[ul_dev_ep], 0, sizeof(usb_pipe_table[ul_dev_ep]));
+
+ usb_pipe_table[ul_dev_ep].HostDescBank[0].CTRL_PIPE.bit.PDADDR = ul_dev_addr;
+ usb_pipe_table[ul_dev_ep].HostDescBank[0].CTRL_PIPE.bit.PEPNUM = ul_dev_ep;
+ usb_pipe_table[ul_dev_ep].HostDescBank[0].PCKSIZE.bit.SIZE = ul_maxsize;
+
+ return 1;
+}
+
+
+void UHD_Pipe_CountZero(uint32_t ul_pipe)
+{
+ usb_pipe_table[ul_pipe].HostDescBank[0].PCKSIZE.bit.BYTE_COUNT = 0;
+}
+
+/**
+ * \brief Free a pipe.
+ *
+ * \param ul_pipe Pipe number to free.
+ */
+void UHD_Pipe_Free(uint32_t ul_pipe)
+{
+ // The Pipe is frozen and no additional requests will be sent to the device on this pipe address.
+ USB->HOST.HostPipe[ul_pipe].PSTATUSSET.reg = USB_HOST_PSTATUSSET_PFREEZE;
+}
+
+
+/**
+ * \brief Read from a pipe.
+ *
+ * \param ul_pipe Pipe number.
+ * \param ul_size Maximum number of data to read.
+ * \param data Buffer to store the data.
+ *
+ * \return number of data read.
+ */
+uint32_t UHD_Pipe_Read(uint32_t pipe_num, uint32_t buf_size, uint8_t *buf)
+{
+ if (USB->HOST.HostPipe[pipe_num].PCFG.bit.PTYPE == USB_HOST_PTYPE_DIS)
+ {
+ return 0;
+ }
+
+ /* get pipe config from setting register */
+ usb_pipe_table[pipe_num].HostDescBank[0].ADDR.reg = (uint32_t)buf;
+ usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.BYTE_COUNT = 0;
+ usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE = buf_size;
+ USB->HOST.HostPipe[pipe_num].PCFG.bit.PTOKEN = USB_HOST_PCFG_PTOKEN_IN;
+
+ /* Start transfer */
+ USB->HOST.HostPipe[pipe_num].PSTATUSCLR.reg = USB_HOST_PSTATUSCLR_BK0RDY;
+
+ // Unfreeze pipe
+ USB->HOST.HostPipe[pipe_num].PSTATUSCLR.reg = USB_HOST_PSTATUSCLR_PFREEZE;
+
+ return buf_size;
+}
+
+
+/**
+ * \brief Write into a pipe.
+ *
+ * \param ul_pipe Pipe number.
+ * \param ul_size Maximum number of data to read.
+ * \param data Buffer containing data to write.
+ */
+void UHD_Pipe_Write(uint32_t ul_pipe, uint32_t ul_size, uint8_t *buf)
+{
+ /* get pipe config from setting register */
+ usb_pipe_table[ul_pipe].HostDescBank[0].ADDR.reg = (uint32_t)buf;
+ usb_pipe_table[ul_pipe].HostDescBank[0].PCKSIZE.bit.BYTE_COUNT = ul_size;
+ usb_pipe_table[ul_pipe].HostDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE = 0;
+}
+
+/**
+ * \brief Send a pipe content.
+ *
+ * \param ul_pipe Pipe number.
+ * \param ul_token_type Token type.
+ */
+void UHD_Pipe_Send(uint32_t ul_pipe, uint32_t ul_token_type)
+{
+ USB->HOST.HostPipe[ul_pipe].PCFG.bit.PTOKEN = ul_token_type;
+
+ /* Start transfer */
+ if(ul_token_type == USB_HOST_PCFG_PTOKEN_SETUP )
+ {
+ USB->HOST.HostPipe[ul_pipe].PINTFLAG.reg = USB_HOST_PINTFLAG_TXSTP;
+ USB->HOST.HostPipe[ul_pipe].PSTATUSSET.reg = USB_HOST_PSTATUSSET_BK0RDY;
+ }
+ else if(ul_token_type == USB_HOST_PCFG_PTOKEN_IN )
+ {
+ USB->HOST.HostPipe[ul_pipe].PSTATUSCLR.reg = USB_HOST_PSTATUSCLR_BK0RDY;
+ }
+ else
+ {
+ USB->HOST.HostPipe[ul_pipe].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT(1); // Transfer Complete 0
+ USB->HOST.HostPipe[ul_pipe].PSTATUSSET.reg = USB_HOST_PSTATUSSET_BK0RDY;
+ }
+
+ // Unfreeze pipe
+ uhd_unfreeze_pipe(ul_pipe);
+}
+
+/**
+ * \brief Check for pipe transfer completion.
+ *
+ * \param ul_pipe Pipe number.
+ * \param ul_token_type Token type.
+ *
+ * \retval 0 transfer is not complete.
+ * \retval 1 transfer is complete.
+ */
+uint32_t UHD_Pipe_Is_Transfer_Complete(uint32_t ul_pipe, uint32_t ul_token_type)
+{
+ // Check for transfer completion depending on token type
+ switch (ul_token_type)
+ {
+ case USB_HOST_PCFG_PTOKEN_SETUP:
+ if (Is_uhd_setup_ready(ul_pipe))
+ {
+ uhd_ack_setup_ready(ul_pipe);
+ uhd_freeze_pipe(ul_pipe);
+ return 1;
+ }
+ break;
+
+ case USB_HOST_PCFG_PTOKEN_IN:
+ if (Is_uhd_in_received(ul_pipe))
+ {
+ // IN packet received
+ uhd_ack_in_received(ul_pipe);
+ // Freeze will stop after the transfer
+ uhd_freeze_pipe(ul_pipe);
+ return 1;
+ }
+ break;
+
+ case USB_HOST_PCFG_PTOKEN_OUT:
+ if (Is_uhd_out_ready(ul_pipe))
+ {
+ // OUT packet sent
+ uhd_ack_out_ready(ul_pipe);
+ uhd_freeze_pipe(ul_pipe);
+ return 1;
+ }
+ break;
+ }
+
+ return 0;
+}
+
+
+
+
+// USB_Handler ISR
+// void USB_Handler(void) {
+// UHD_Handler();
+// }
+
+#endif // HOST_DEFINED
diff --git a/UsbReceive/UsbReceive/ArduinoCore/src/core/Uart.cpp b/UsbReceive/UsbReceive/ArduinoCore/src/core/Uart.cpp
new file mode 100644
index 0000000000000000000000000000000000000000..e7d3adcd45cb26f392f94c3b4da216bd860951f0
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/src/core/Uart.cpp
@@ -0,0 +1,240 @@
+/*
+ Copyright (c) 2015 Arduino LLC. All right reserved.
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ See the GNU Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#include "Arduino.h"
+#include "wiring_private.h"
+#include "Uart.h"
+
+#define NO_RTS_PIN 255
+#define NO_CTS_PIN 255
+#define RTS_RX_THRESHOLD 10
+
+Uart::Uart(SERCOM *_s, uint8_t _pinRX, uint8_t _pinTX, SercomRXPad _padRX, SercomUartTXPad _padTX) :
+ Uart(_s, _pinRX, _pinTX, _padRX, _padTX, NO_RTS_PIN, NO_CTS_PIN)
+{
+}
+
+Uart::Uart(SERCOM *_s, uint8_t _pinRX, uint8_t _pinTX, SercomRXPad _padRX, SercomUartTXPad _padTX, uint8_t _pinRTS, uint8_t _pinCTS)
+{
+ sercom = _s;
+ uc_pinRX = _pinRX;
+ uc_pinTX = _pinTX;
+ uc_padRX = _padRX ;
+ uc_padTX = _padTX;
+ uc_pinRTS = _pinRTS;
+ uc_pinCTS = _pinCTS;
+}
+
+void Uart::begin(unsigned long baudrate)
+{
+ begin(baudrate, SERIAL_8N1);
+}
+
+void Uart::begin(unsigned long baudrate, uint16_t config)
+{
+ pinPeripheral(uc_pinRX, g_APinDescription[uc_pinRX].ulPinType);
+ pinPeripheral(uc_pinTX, g_APinDescription[uc_pinTX].ulPinType);
+
+ if (uc_padTX == UART_TX_RTS_CTS_PAD_0_2_3) {
+ if (uc_pinCTS != NO_CTS_PIN) {
+ pinPeripheral(uc_pinCTS, g_APinDescription[uc_pinCTS].ulPinType);
+ }
+ }
+
+ if (uc_pinRTS != NO_RTS_PIN) {
+ pinMode(uc_pinRTS, OUTPUT);
+
+ EPortType rtsPort = g_APinDescription[uc_pinRTS].ulPort;
+ pul_outsetRTS = &PORT->Group[rtsPort].OUTSET.reg;
+ pul_outclrRTS = &PORT->Group[rtsPort].OUTCLR.reg;
+ ul_pinMaskRTS = (1ul << g_APinDescription[uc_pinRTS].ulPin);
+
+ *pul_outclrRTS = ul_pinMaskRTS;
+ }
+
+ sercom->initUART(UART_INT_CLOCK, SAMPLE_RATE_x16, baudrate);
+ sercom->initFrame(extractCharSize(config), LSB_FIRST, extractParity(config), extractNbStopBit(config));
+ sercom->initPads(uc_padTX, uc_padRX);
+
+ sercom->enableUART();
+}
+
+void Uart::end()
+{
+ sercom->resetUART();
+ rxBuffer.clear();
+ txBuffer.clear();
+}
+
+void Uart::flush()
+{
+ while(txBuffer.available()); // wait until TX buffer is empty
+
+ sercom->flushUART();
+}
+
+void Uart::IrqHandler()
+{
+ if (sercom->isFrameErrorUART()) {
+ // frame error, next byte is invalid so read and discard it
+ sercom->readDataUART();
+
+ sercom->clearFrameErrorUART();
+ }
+
+ if (sercom->availableDataUART()) {
+ rxBuffer.store_char(sercom->readDataUART());
+
+ if (uc_pinRTS != NO_RTS_PIN) {
+ // RX buffer space is below the threshold, de-assert RTS
+ if (rxBuffer.availableForStore() < RTS_RX_THRESHOLD) {
+ *pul_outsetRTS = ul_pinMaskRTS;
+ }
+ }
+ }
+
+ if (sercom->isDataRegisterEmptyUART()) {
+ if (txBuffer.available()) {
+ uint8_t data = txBuffer.read_char();
+
+ sercom->writeDataUART(data);
+ } else {
+ sercom->disableDataRegisterEmptyInterruptUART();
+ }
+ }
+
+ if (sercom->isUARTError()) {
+ sercom->acknowledgeUARTError();
+ // TODO: if (sercom->isBufferOverflowErrorUART()) ....
+ // TODO: if (sercom->isParityErrorUART()) ....
+ sercom->clearStatusUART();
+ }
+}
+
+int Uart::available()
+{
+ return rxBuffer.available();
+}
+
+int Uart::availableForWrite()
+{
+ return txBuffer.availableForStore();
+}
+
+int Uart::peek()
+{
+ return rxBuffer.peek();
+}
+
+int Uart::read()
+{
+ int c = rxBuffer.read_char();
+
+ if (uc_pinRTS != NO_RTS_PIN) {
+ // if there is enough space in the RX buffer, assert RTS
+ if (rxBuffer.availableForStore() > RTS_RX_THRESHOLD) {
+ *pul_outclrRTS = ul_pinMaskRTS;
+ }
+ }
+
+ return c;
+}
+
+size_t Uart::write(const uint8_t data)
+{
+ if (sercom->isDataRegisterEmptyUART() && txBuffer.available() == 0) {
+ sercom->writeDataUART(data);
+ } else {
+ // spin lock until a spot opens up in the buffer
+ while(txBuffer.isFull()) {
+ uint8_t interruptsEnabled = ((__get_PRIMASK() & 0x1) == 0);
+
+ if (interruptsEnabled) {
+ uint32_t exceptionNumber = (SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk);
+
+ if (exceptionNumber == 0 ||
+ NVIC_GetPriority((IRQn_Type)(exceptionNumber - 16)) > SERCOM_NVIC_PRIORITY) {
+ // no exception or called from an ISR with lower priority,
+ // wait for free buffer spot via IRQ
+ continue;
+ }
+ }
+
+ // interrupts are disabled or called from ISR with higher or equal priority than the SERCOM IRQ
+ // manually call the UART IRQ handler when the data register is empty
+ if (sercom->isDataRegisterEmptyUART()) {
+ IrqHandler();
+ }
+ }
+
+ txBuffer.store_char(data);
+
+ sercom->enableDataRegisterEmptyInterruptUART();
+ }
+
+ return 1;
+}
+
+SercomNumberStopBit Uart::extractNbStopBit(uint16_t config)
+{
+ switch(config & HARDSER_STOP_BIT_MASK)
+ {
+ case HARDSER_STOP_BIT_1:
+ default:
+ return SERCOM_STOP_BIT_1;
+
+ case HARDSER_STOP_BIT_2:
+ return SERCOM_STOP_BITS_2;
+ }
+}
+
+SercomUartCharSize Uart::extractCharSize(uint16_t config)
+{
+ switch(config & HARDSER_DATA_MASK)
+ {
+ case HARDSER_DATA_5:
+ return UART_CHAR_SIZE_5_BITS;
+
+ case HARDSER_DATA_6:
+ return UART_CHAR_SIZE_6_BITS;
+
+ case HARDSER_DATA_7:
+ return UART_CHAR_SIZE_7_BITS;
+
+ case HARDSER_DATA_8:
+ default:
+ return UART_CHAR_SIZE_8_BITS;
+
+ }
+}
+
+SercomParityMode Uart::extractParity(uint16_t config)
+{
+ switch(config & HARDSER_PARITY_MASK)
+ {
+ case HARDSER_PARITY_NONE:
+ default:
+ return SERCOM_NO_PARITY;
+
+ case HARDSER_PARITY_EVEN:
+ return SERCOM_EVEN_PARITY;
+
+ case HARDSER_PARITY_ODD:
+ return SERCOM_ODD_PARITY;
+ }
+}
diff --git a/UsbReceive/UsbReceive/ArduinoCore/src/core/WInterrupts.c b/UsbReceive/UsbReceive/ArduinoCore/src/core/WInterrupts.c
new file mode 100644
index 0000000000000000000000000000000000000000..c78ddf62b984c657ffa2a7fff0941727318bbb19
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/src/core/WInterrupts.c
@@ -0,0 +1,200 @@
+/*
+ Copyright (c) 2015 Arduino LLC. All right reserved.
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ See the GNU Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#include "Arduino.h"
+#include "wiring_private.h"
+
+#include <string.h>
+
+static voidFuncPtr ISRcallback[EXTERNAL_NUM_INTERRUPTS];
+static uint32_t ISRlist[EXTERNAL_NUM_INTERRUPTS];
+static uint32_t nints; // Stores total number of attached interrupts
+
+
+/* Configure I/O interrupt sources */
+static void __initialize()
+{
+ memset(ISRlist, 0, sizeof(ISRlist));
+ memset(ISRcallback, 0, sizeof(ISRcallback));
+ nints = 0;
+
+ NVIC_DisableIRQ(EIC_IRQn);
+ NVIC_ClearPendingIRQ(EIC_IRQn);
+ NVIC_SetPriority(EIC_IRQn, 0);
+ NVIC_EnableIRQ(EIC_IRQn);
+
+ // Enable GCLK for IEC (External Interrupt Controller)
+ GCLK->CLKCTRL.reg = (uint16_t) (GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN_GCLK0 | GCLK_CLKCTRL_ID(GCM_EIC));
+
+/* Shall we do that?
+ // Do a software reset on EIC
+ EIC->CTRL.SWRST.bit = 1 ;
+ while ((EIC->CTRL.SWRST.bit == 1) && (EIC->STATUS.SYNCBUSY.bit == 1)) { }
+*/
+
+ // Enable EIC
+ EIC->CTRL.bit.ENABLE = 1;
+ while (EIC->STATUS.bit.SYNCBUSY == 1) { }
+}
+
+/*
+ * \brief Specifies a named Interrupt Service Routine (ISR) to call when an interrupt occurs.
+ * Replaces any previous function that was attached to the interrupt.
+ */
+void attachInterrupt(uint32_t pin, voidFuncPtr callback, uint32_t mode)
+{
+ static int enabled = 0;
+ uint32_t config;
+ uint32_t pos;
+
+#if ARDUINO_SAMD_VARIANT_COMPLIANCE >= 10606
+ EExt_Interrupts in = g_APinDescription[pin].ulExtInt;
+#else
+ EExt_Interrupts in = digitalPinToInterrupt(pin);
+#endif
+ if (in == NOT_AN_INTERRUPT || in == EXTERNAL_INT_NMI)
+ return;
+
+ if (!enabled) {
+ __initialize();
+ enabled = 1;
+ }
+
+ // Enable wakeup capability on pin in case being used during sleep
+ uint32_t inMask = 1 << in;
+ EIC->WAKEUP.reg |= inMask;
+
+ // Assign pin to EIC
+ pinPeripheral(pin, PIO_EXTINT);
+
+ // Only store when there is really an ISR to call.
+ // This allow for calling attachInterrupt(pin, NULL, mode), we set up all needed register
+ // but won't service the interrupt, this way we also don't need to check it inside the ISR.
+ if (callback)
+ {
+ // Store interrupts to service in order of when they were attached
+ // to allow for first come first serve handler
+ uint32_t current = 0;
+
+ // Check if we already have this interrupt
+ for (current=0; current<nints; current++) {
+ if (ISRlist[current] == inMask) {
+ break;
+ }
+ }
+ if (current == nints) {
+ // Need to make a new entry
+ nints++;
+ }
+ ISRlist[current] = inMask; // List of interrupt in order of when they were attached
+ ISRcallback[current] = callback; // List of callback adresses
+
+ // Look for right CONFIG register to be addressed
+ if (in > EXTERNAL_INT_7) {
+ config = 1;
+ pos = (in - 8) << 2;
+ } else {
+ config = 0;
+ pos = in << 2;
+ }
+
+ // Configure the interrupt mode
+ EIC->CONFIG[config].reg &=~ (EIC_CONFIG_SENSE0_Msk << pos); // Reset sense mode, important when changing trigger mode during runtime
+ switch (mode)
+ {
+ case LOW:
+ EIC->CONFIG[config].reg |= EIC_CONFIG_SENSE0_LOW_Val << pos;
+ break;
+
+ case HIGH:
+ EIC->CONFIG[config].reg |= EIC_CONFIG_SENSE0_HIGH_Val << pos;
+ break;
+
+ case CHANGE:
+ EIC->CONFIG[config].reg |= EIC_CONFIG_SENSE0_BOTH_Val << pos;
+ break;
+
+ case FALLING:
+ EIC->CONFIG[config].reg |= EIC_CONFIG_SENSE0_FALL_Val << pos;
+ break;
+
+ case RISING:
+ EIC->CONFIG[config].reg |= EIC_CONFIG_SENSE0_RISE_Val << pos;
+ break;
+ }
+ }
+ // Enable the interrupt
+ EIC->INTENSET.reg = EIC_INTENSET_EXTINT(inMask);
+}
+
+/*
+ * \brief Turns off the given interrupt.
+ */
+void detachInterrupt(uint32_t pin)
+{
+#if (ARDUINO_SAMD_VARIANT_COMPLIANCE >= 10606)
+ EExt_Interrupts in = g_APinDescription[pin].ulExtInt;
+#else
+ EExt_Interrupts in = digitalPinToInterrupt(pin);
+#endif
+ if (in == NOT_AN_INTERRUPT || in == EXTERNAL_INT_NMI)
+ return;
+
+ uint32_t inMask = 1 << in;
+ EIC->INTENCLR.reg = EIC_INTENCLR_EXTINT(inMask);
+
+ // Disable wakeup capability on pin during sleep
+ EIC->WAKEUP.reg &= ~inMask;
+
+ // Remove callback from the ISR list
+ uint32_t current;
+ for (current=0; current<nints; current++) {
+ if (ISRlist[current] == inMask) {
+ break;
+ }
+ }
+ if (current == nints) return; // We didn't have it
+
+ // Shift the reminder down
+ for (; current<nints-1; current++) {
+ ISRlist[current] = ISRlist[current+1];
+ ISRcallback[current] = ISRcallback[current+1];
+ }
+ nints--;
+}
+
+/*
+ * External Interrupt Controller NVIC Interrupt Handler
+ */
+void EIC_Handler(void)
+{
+ // Calling the routine directly from -here- takes about 1us
+ // Depending on where you are in the list it will take longer
+
+ // Loop over all enabled interrupts in the list
+ for (uint32_t i=0; i<nints; i++)
+ {
+ if ((EIC->INTFLAG.reg & ISRlist[i]) != 0)
+ {
+ // Call the callback function
+ ISRcallback[i]();
+ // Clear the interrupt
+ EIC->INTFLAG.reg = ISRlist[i];
+ }
+ }
+}
diff --git a/UsbReceive/UsbReceive/ArduinoCore/src/core/WMath.cpp b/UsbReceive/UsbReceive/ArduinoCore/src/core/WMath.cpp
new file mode 100644
index 0000000000000000000000000000000000000000..55caddd62324cb77c6021e36f561847077888440
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/src/core/WMath.cpp
@@ -0,0 +1,68 @@
+/*
+ Copyright (c) 2014 Arduino. All right reserved.
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ See the GNU Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+extern "C" {
+ #include "stdlib.h"
+ #include "stdint.h"
+}
+#include "WMath.h"
+
+extern void randomSeed( uint32_t dwSeed )
+{
+ if ( dwSeed != 0 )
+ {
+ srand( dwSeed ) ;
+ }
+}
+
+extern long random( long howbig )
+{
+ if ( howbig == 0 )
+ {
+ return 0 ;
+ }
+
+ return rand() % howbig;
+}
+
+extern long random( long howsmall, long howbig )
+{
+ if (howsmall >= howbig)
+ {
+ return howsmall;
+ }
+
+ long diff = howbig - howsmall;
+
+ return random(diff) + howsmall;
+}
+
+extern long map(long x, long in_min, long in_max, long out_min, long out_max)
+{
+ return (x - in_min) * (out_max - out_min) / (in_max - in_min) + out_min;
+}
+
+extern uint16_t makeWord( uint16_t w )
+{
+ return w ;
+}
+
+extern uint16_t makeWord( uint8_t h, uint8_t l )
+{
+ return (h << 8) | l ;
+}
diff --git a/UsbReceive/UsbReceive/ArduinoCore/src/core/WString.cpp b/UsbReceive/UsbReceive/ArduinoCore/src/core/WString.cpp
new file mode 100644
index 0000000000000000000000000000000000000000..4c0155998938c7825cce61be078c5e9fcb1b441d
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/src/core/WString.cpp
@@ -0,0 +1,752 @@
+/*
+ WString.cpp - String library for Wiring & Arduino
+ ...mostly rewritten by Paul Stoffregen...
+ Copyright (c) 2009-10 Hernando Barragan. All rights reserved.
+ Copyright 2011, Paul Stoffregen, paul@pjrc.com
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#include "WString.h"
+#include "itoa.h"
+#include "avr/dtostrf.h"
+
+/*********************************************/
+/* Constructors */
+/*********************************************/
+
+String::String(const char *cstr)
+{
+ init();
+ if (cstr) copy(cstr, strlen(cstr));
+}
+
+String::String(const String &value)
+{
+ init();
+ *this = value;
+}
+
+String::String(const __FlashStringHelper *pstr)
+{
+ init();
+ *this = pstr;
+}
+
+#if __cplusplus >= 201103L || defined(__GXX_EXPERIMENTAL_CXX0X__)
+String::String(String &&rval)
+{
+ init();
+ move(rval);
+}
+String::String(StringSumHelper &&rval)
+{
+ init();
+ move(rval);
+}
+#endif
+
+String::String(char c)
+{
+ init();
+ char buf[2];
+ buf[0] = c;
+ buf[1] = 0;
+ *this = buf;
+}
+
+String::String(unsigned char value, unsigned char base)
+{
+ init();
+ char buf[1 + 8 * sizeof(unsigned char)];
+ utoa(value, buf, base);
+ *this = buf;
+}
+
+String::String(int value, unsigned char base)
+{
+ init();
+ char buf[2 + 8 * sizeof(int)];
+ itoa(value, buf, base);
+ *this = buf;
+}
+
+String::String(unsigned int value, unsigned char base)
+{
+ init();
+ char buf[1 + 8 * sizeof(unsigned int)];
+ utoa(value, buf, base);
+ *this = buf;
+}
+
+String::String(long value, unsigned char base)
+{
+ init();
+ char buf[2 + 8 * sizeof(long)];
+ ltoa(value, buf, base);
+ *this = buf;
+}
+
+String::String(unsigned long value, unsigned char base)
+{
+ init();
+ char buf[1 + 8 * sizeof(unsigned long)];
+ ultoa(value, buf, base);
+ *this = buf;
+}
+
+String::String(float value, unsigned char decimalPlaces)
+{
+ init();
+ char buf[33];
+ *this = dtostrf(value, (decimalPlaces + 2), decimalPlaces, buf);
+}
+
+String::String(double value, unsigned char decimalPlaces)
+{
+ init();
+ char buf[33];
+ *this = dtostrf(value, (decimalPlaces + 2), decimalPlaces, buf);
+}
+
+String::~String()
+{
+ if (buffer) free(buffer);
+}
+
+/*********************************************/
+/* Memory Management */
+/*********************************************/
+
+inline void String::init(void)
+{
+ buffer = NULL;
+ capacity = 0;
+ len = 0;
+}
+
+void String::invalidate(void)
+{
+ if (buffer) free(buffer);
+ buffer = NULL;
+ capacity = len = 0;
+}
+
+unsigned char String::reserve(unsigned int size)
+{
+ if (buffer && capacity >= size) return 1;
+ if (changeBuffer(size)) {
+ if (len == 0) buffer[0] = 0;
+ return 1;
+ }
+ return 0;
+}
+
+unsigned char String::changeBuffer(unsigned int maxStrLen)
+{
+ char *newbuffer = (char *)realloc(buffer, maxStrLen + 1);
+ if (newbuffer) {
+ buffer = newbuffer;
+ capacity = maxStrLen;
+ return 1;
+ }
+ return 0;
+}
+
+/*********************************************/
+/* Copy and Move */
+/*********************************************/
+
+String & String::copy(const char *cstr, unsigned int length)
+{
+ if (!reserve(length)) {
+ invalidate();
+ return *this;
+ }
+ len = length;
+ strcpy(buffer, cstr);
+ return *this;
+}
+
+String & String::copy(const __FlashStringHelper *pstr, unsigned int length)
+{
+ if (!reserve(length)) {
+ invalidate();
+ return *this;
+ }
+ len = length;
+ strcpy_P(buffer, (PGM_P)pstr);
+ return *this;
+}
+
+#if __cplusplus >= 201103L || defined(__GXX_EXPERIMENTAL_CXX0X__)
+void String::move(String &rhs)
+{
+ if (buffer) {
+ if (rhs && capacity >= rhs.len) {
+ strcpy(buffer, rhs.buffer);
+ len = rhs.len;
+ rhs.len = 0;
+ return;
+ } else {
+ free(buffer);
+ }
+ }
+ buffer = rhs.buffer;
+ capacity = rhs.capacity;
+ len = rhs.len;
+ rhs.buffer = NULL;
+ rhs.capacity = 0;
+ rhs.len = 0;
+}
+#endif
+
+String & String::operator = (const String &rhs)
+{
+ if (this == &rhs) return *this;
+
+ if (rhs.buffer) copy(rhs.buffer, rhs.len);
+ else invalidate();
+
+ return *this;
+}
+
+#if __cplusplus >= 201103L || defined(__GXX_EXPERIMENTAL_CXX0X__)
+String & String::operator = (String &&rval)
+{
+ if (this != &rval) move(rval);
+ return *this;
+}
+
+String & String::operator = (StringSumHelper &&rval)
+{
+ if (this != &rval) move(rval);
+ return *this;
+}
+#endif
+
+String & String::operator = (const char *cstr)
+{
+ if (cstr) copy(cstr, strlen(cstr));
+ else invalidate();
+
+ return *this;
+}
+
+String & String::operator = (const __FlashStringHelper *pstr)
+{
+ if (pstr) copy(pstr, strlen_P((PGM_P)pstr));
+ else invalidate();
+
+ return *this;
+}
+
+/*********************************************/
+/* concat */
+/*********************************************/
+
+unsigned char String::concat(const String &s)
+{
+ return concat(s.buffer, s.len);
+}
+
+unsigned char String::concat(const char *cstr, unsigned int length)
+{
+ unsigned int newlen = len + length;
+ if (!cstr) return 0;
+ if (length == 0) return 1;
+ if (!reserve(newlen)) return 0;
+ strcpy(buffer + len, cstr);
+ len = newlen;
+ return 1;
+}
+
+unsigned char String::concat(const char *cstr)
+{
+ if (!cstr) return 0;
+ return concat(cstr, strlen(cstr));
+}
+
+unsigned char String::concat(char c)
+{
+ char buf[2];
+ buf[0] = c;
+ buf[1] = 0;
+ return concat(buf, 1);
+}
+
+unsigned char String::concat(unsigned char num)
+{
+ char buf[1 + 3 * sizeof(unsigned char)];
+ itoa(num, buf, 10);
+ return concat(buf, strlen(buf));
+}
+
+unsigned char String::concat(int num)
+{
+ char buf[2 + 3 * sizeof(int)];
+ itoa(num, buf, 10);
+ return concat(buf, strlen(buf));
+}
+
+unsigned char String::concat(unsigned int num)
+{
+ char buf[1 + 3 * sizeof(unsigned int)];
+ utoa(num, buf, 10);
+ return concat(buf, strlen(buf));
+}
+
+unsigned char String::concat(long num)
+{
+ char buf[2 + 3 * sizeof(long)];
+ ltoa(num, buf, 10);
+ return concat(buf, strlen(buf));
+}
+
+unsigned char String::concat(unsigned long num)
+{
+ char buf[1 + 3 * sizeof(unsigned long)];
+ ultoa(num, buf, 10);
+ return concat(buf, strlen(buf));
+}
+
+unsigned char String::concat(float num)
+{
+ char buf[20];
+ char* string = dtostrf(num, 4, 2, buf);
+ return concat(string, strlen(string));
+}
+
+unsigned char String::concat(double num)
+{
+ char buf[20];
+ char* string = dtostrf(num, 4, 2, buf);
+ return concat(string, strlen(string));
+}
+
+unsigned char String::concat(const __FlashStringHelper * str)
+{
+ if (!str) return 0;
+ int length = strlen_P((const char *) str);
+ if (length == 0) return 1;
+ unsigned int newlen = len + length;
+ if (!reserve(newlen)) return 0;
+ strcpy_P(buffer + len, (const char *) str);
+ len = newlen;
+ return 1;
+}
+
+/*********************************************/
+/* Concatenate */
+/*********************************************/
+
+StringSumHelper & operator + (const StringSumHelper &lhs, const String &rhs)
+{
+ StringSumHelper &a = const_cast<StringSumHelper&>(lhs);
+ if (!a.concat(rhs.buffer, rhs.len)) a.invalidate();
+ return a;
+}
+
+StringSumHelper & operator + (const StringSumHelper &lhs, const char *cstr)
+{
+ StringSumHelper &a = const_cast<StringSumHelper&>(lhs);
+ if (!cstr || !a.concat(cstr, strlen(cstr))) a.invalidate();
+ return a;
+}
+
+StringSumHelper & operator + (const StringSumHelper &lhs, char c)
+{
+ StringSumHelper &a = const_cast<StringSumHelper&>(lhs);
+ if (!a.concat(c)) a.invalidate();
+ return a;
+}
+
+StringSumHelper & operator + (const StringSumHelper &lhs, unsigned char num)
+{
+ StringSumHelper &a = const_cast<StringSumHelper&>(lhs);
+ if (!a.concat(num)) a.invalidate();
+ return a;
+}
+
+StringSumHelper & operator + (const StringSumHelper &lhs, int num)
+{
+ StringSumHelper &a = const_cast<StringSumHelper&>(lhs);
+ if (!a.concat(num)) a.invalidate();
+ return a;
+}
+
+StringSumHelper & operator + (const StringSumHelper &lhs, unsigned int num)
+{
+ StringSumHelper &a = const_cast<StringSumHelper&>(lhs);
+ if (!a.concat(num)) a.invalidate();
+ return a;
+}
+
+StringSumHelper & operator + (const StringSumHelper &lhs, long num)
+{
+ StringSumHelper &a = const_cast<StringSumHelper&>(lhs);
+ if (!a.concat(num)) a.invalidate();
+ return a;
+}
+
+StringSumHelper & operator + (const StringSumHelper &lhs, unsigned long num)
+{
+ StringSumHelper &a = const_cast<StringSumHelper&>(lhs);
+ if (!a.concat(num)) a.invalidate();
+ return a;
+}
+
+StringSumHelper & operator + (const StringSumHelper &lhs, float num)
+{
+ StringSumHelper &a = const_cast<StringSumHelper&>(lhs);
+ if (!a.concat(num)) a.invalidate();
+ return a;
+}
+
+StringSumHelper & operator + (const StringSumHelper &lhs, double num)
+{
+ StringSumHelper &a = const_cast<StringSumHelper&>(lhs);
+ if (!a.concat(num)) a.invalidate();
+ return a;
+}
+
+StringSumHelper & operator + (const StringSumHelper &lhs, const __FlashStringHelper *rhs)
+{
+ StringSumHelper &a = const_cast<StringSumHelper&>(lhs);
+ if (!a.concat(rhs)) a.invalidate();
+ return a;
+}
+
+/*********************************************/
+/* Comparison */
+/*********************************************/
+
+int String::compareTo(const String &s) const
+{
+ if (!buffer || !s.buffer) {
+ if (s.buffer && s.len > 0) return 0 - *(unsigned char *)s.buffer;
+ if (buffer && len > 0) return *(unsigned char *)buffer;
+ return 0;
+ }
+ return strcmp(buffer, s.buffer);
+}
+
+unsigned char String::equals(const String &s2) const
+{
+ return (len == s2.len && compareTo(s2) == 0);
+}
+
+unsigned char String::equals(const char *cstr) const
+{
+ if (len == 0) return (cstr == NULL || *cstr == 0);
+ if (cstr == NULL) return buffer[0] == 0;
+ return strcmp(buffer, cstr) == 0;
+}
+
+unsigned char String::operator<(const String &rhs) const
+{
+ return compareTo(rhs) < 0;
+}
+
+unsigned char String::operator>(const String &rhs) const
+{
+ return compareTo(rhs) > 0;
+}
+
+unsigned char String::operator<=(const String &rhs) const
+{
+ return compareTo(rhs) <= 0;
+}
+
+unsigned char String::operator>=(const String &rhs) const
+{
+ return compareTo(rhs) >= 0;
+}
+
+unsigned char String::equalsIgnoreCase( const String &s2 ) const
+{
+ if (this == &s2) return 1;
+ if (len != s2.len) return 0;
+ if (len == 0) return 1;
+ const char *p1 = buffer;
+ const char *p2 = s2.buffer;
+ while (*p1) {
+ if (tolower(*p1++) != tolower(*p2++)) return 0;
+ }
+ return 1;
+}
+
+unsigned char String::startsWith( const String &s2 ) const
+{
+ if (len < s2.len) return 0;
+ return startsWith(s2, 0);
+}
+
+unsigned char String::startsWith( const String &s2, unsigned int offset ) const
+{
+ if (offset > len - s2.len || !buffer || !s2.buffer) return 0;
+ return strncmp( &buffer[offset], s2.buffer, s2.len ) == 0;
+}
+
+unsigned char String::endsWith( const String &s2 ) const
+{
+ if ( len < s2.len || !buffer || !s2.buffer) return 0;
+ return strcmp(&buffer[len - s2.len], s2.buffer) == 0;
+}
+
+/*********************************************/
+/* Character Access */
+/*********************************************/
+
+char String::charAt(unsigned int loc) const
+{
+ return operator[](loc);
+}
+
+void String::setCharAt(unsigned int loc, char c)
+{
+ if (loc < len) buffer[loc] = c;
+}
+
+char & String::operator[](unsigned int index)
+{
+ static char dummy_writable_char;
+ if (index >= len || !buffer) {
+ dummy_writable_char = 0;
+ return dummy_writable_char;
+ }
+ return buffer[index];
+}
+
+char String::operator[]( unsigned int index ) const
+{
+ if (index >= len || !buffer) return 0;
+ return buffer[index];
+}
+
+void String::getBytes(unsigned char *buf, unsigned int bufsize, unsigned int index) const
+{
+ if (!bufsize || !buf) return;
+ if (index >= len) {
+ buf[0] = 0;
+ return;
+ }
+ unsigned int n = bufsize - 1;
+ if (n > len - index) n = len - index;
+ strncpy((char *)buf, buffer + index, n);
+ buf[n] = 0;
+}
+
+/*********************************************/
+/* Search */
+/*********************************************/
+
+int String::indexOf(char c) const
+{
+ return indexOf(c, 0);
+}
+
+int String::indexOf( char ch, unsigned int fromIndex ) const
+{
+ if (fromIndex >= len) return -1;
+ const char* temp = strchr(buffer + fromIndex, ch);
+ if (temp == NULL) return -1;
+ return temp - buffer;
+}
+
+int String::indexOf(const String &s2) const
+{
+ return indexOf(s2, 0);
+}
+
+int String::indexOf(const String &s2, unsigned int fromIndex) const
+{
+ if (fromIndex >= len) return -1;
+ const char *found = strstr(buffer + fromIndex, s2.buffer);
+ if (found == NULL) return -1;
+ return found - buffer;
+}
+
+int String::lastIndexOf( char theChar ) const
+{
+ return lastIndexOf(theChar, len - 1);
+}
+
+int String::lastIndexOf(char ch, unsigned int fromIndex) const
+{
+ if (fromIndex >= len) return -1;
+ char tempchar = buffer[fromIndex + 1];
+ buffer[fromIndex + 1] = '\0';
+ char* temp = strrchr( buffer, ch );
+ buffer[fromIndex + 1] = tempchar;
+ if (temp == NULL) return -1;
+ return temp - buffer;
+}
+
+int String::lastIndexOf(const String &s2) const
+{
+ return lastIndexOf(s2, len - s2.len);
+}
+
+int String::lastIndexOf(const String &s2, unsigned int fromIndex) const
+{
+ if (s2.len == 0 || len == 0 || s2.len > len) return -1;
+ if (fromIndex >= len) fromIndex = len - 1;
+ int found = -1;
+ for (char *p = buffer; p <= buffer + fromIndex; p++) {
+ p = strstr(p, s2.buffer);
+ if (!p) break;
+ if ((unsigned int)(p - buffer) <= fromIndex) found = p - buffer;
+ }
+ return found;
+}
+
+String String::substring(unsigned int left, unsigned int right) const
+{
+ if (left > right) {
+ unsigned int temp = right;
+ right = left;
+ left = temp;
+ }
+ String out;
+ if (left >= len) return out;
+ if (right > len) right = len;
+ char temp = buffer[right]; // save the replaced character
+ buffer[right] = '\0';
+ out = buffer + left; // pointer arithmetic
+ buffer[right] = temp; //restore character
+ return out;
+}
+
+/*********************************************/
+/* Modification */
+/*********************************************/
+
+void String::replace(char find, char replace)
+{
+ if (!buffer) return;
+ for (char *p = buffer; *p; p++) {
+ if (*p == find) *p = replace;
+ }
+}
+
+void String::replace(const String& find, const String& replace)
+{
+ if (len == 0 || find.len == 0) return;
+ int diff = replace.len - find.len;
+ char *readFrom = buffer;
+ char *foundAt;
+ if (diff == 0) {
+ while ((foundAt = strstr(readFrom, find.buffer)) != NULL) {
+ memcpy(foundAt, replace.buffer, replace.len);
+ readFrom = foundAt + replace.len;
+ }
+ } else if (diff < 0) {
+ char *writeTo = buffer;
+ while ((foundAt = strstr(readFrom, find.buffer)) != NULL) {
+ unsigned int n = foundAt - readFrom;
+ memcpy(writeTo, readFrom, n);
+ writeTo += n;
+ memcpy(writeTo, replace.buffer, replace.len);
+ writeTo += replace.len;
+ readFrom = foundAt + find.len;
+ len += diff;
+ }
+ strcpy(writeTo, readFrom);
+ } else {
+ unsigned int size = len; // compute size needed for result
+ while ((foundAt = strstr(readFrom, find.buffer)) != NULL) {
+ readFrom = foundAt + find.len;
+ size += diff;
+ }
+ if (size == len) return;
+ if (size > capacity && !changeBuffer(size)) return; // XXX: tell user!
+ int index = len - 1;
+ while (index >= 0 && (index = lastIndexOf(find, index)) >= 0) {
+ readFrom = buffer + index + find.len;
+ memmove(readFrom + diff, readFrom, len - (readFrom - buffer));
+ len += diff;
+ buffer[len] = 0;
+ memcpy(buffer + index, replace.buffer, replace.len);
+ index--;
+ }
+ }
+}
+
+void String::remove(unsigned int index){
+ // Pass the biggest integer as the count. The remove method
+ // below will take care of truncating it at the end of the
+ // string.
+ remove(index, (unsigned int)-1);
+}
+
+void String::remove(unsigned int index, unsigned int count){
+ if (index >= len) { return; }
+ if (count <= 0) { return; }
+ if (count > len - index) { count = len - index; }
+ char *writeTo = buffer + index;
+ len = len - count;
+ strncpy(writeTo, buffer + index + count,len - index);
+ buffer[len] = 0;
+}
+
+void String::toLowerCase(void)
+{
+ if (!buffer) return;
+ for (char *p = buffer; *p; p++) {
+ *p = tolower(*p);
+ }
+}
+
+void String::toUpperCase(void)
+{
+ if (!buffer) return;
+ for (char *p = buffer; *p; p++) {
+ *p = toupper(*p);
+ }
+}
+
+void String::trim(void)
+{
+ if (!buffer || len == 0) return;
+ char *begin = buffer;
+ while (isspace(*begin)) begin++;
+ char *end = buffer + len - 1;
+ while (isspace(*end) && end >= begin) end--;
+ len = end + 1 - begin;
+ if (begin > buffer) memcpy(buffer, begin, len);
+ buffer[len] = 0;
+}
+
+/*********************************************/
+/* Parsing / Conversion */
+/*********************************************/
+
+long String::toInt(void) const
+{
+ if (buffer) return atol(buffer);
+ return 0;
+}
+
+float String::toFloat(void) const
+{
+ return float(toDouble());
+}
+
+double String::toDouble(void) const
+{
+ if (buffer) return atof(buffer);
+ return 0;
+}
diff --git a/UsbReceive/UsbReceive/ArduinoCore/src/core/abi.cpp b/UsbReceive/UsbReceive/ArduinoCore/src/core/abi.cpp
new file mode 100644
index 0000000000000000000000000000000000000000..bd2f43ad160aa6fb801413626b6bfbe49b71f110
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/src/core/abi.cpp
@@ -0,0 +1,37 @@
+/*
+ Copyright (c) 2014 Arduino LLC. All right reserved.
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ See the GNU Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#include <stdlib.h>
+
+extern "C" void __cxa_pure_virtual(void) __attribute__ ((__noreturn__));
+extern "C" void __cxa_deleted_virtual(void) __attribute__ ((__noreturn__));
+
+void __cxa_pure_virtual(void) {
+ // We might want to write some diagnostics to uart in this case
+ //std::terminate();
+ while (1)
+ ;
+}
+
+void __cxa_deleted_virtual(void) {
+ // We might want to write some diagnostics to uart in this case
+ //std::terminate();
+ while (1)
+ ;
+}
+
diff --git a/UsbReceive/UsbReceive/ArduinoCore/src/core/avr/dtostrf.c b/UsbReceive/UsbReceive/ArduinoCore/src/core/avr/dtostrf.c
new file mode 100644
index 0000000000000000000000000000000000000000..de164277bdbcc742b2a746ab520567c4a93b1660
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/src/core/avr/dtostrf.c
@@ -0,0 +1,30 @@
+/*
+ dtostrf - Emulation for dtostrf function from avr-libc
+ Copyright (c) 2015 Arduino LLC. All rights reserved.
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#include <stdio.h>
+
+char *dtostrf (double val, signed char width, unsigned char prec, char *sout) {
+ asm(".global _printf_float");
+
+ char fmt[20];
+ sprintf(fmt, "%%%d.%df", width, prec);
+ sprintf(sout, fmt, val);
+ return sout;
+}
+
diff --git a/UsbReceive/UsbReceive/ArduinoCore/src/core/cortex_handlers.c b/UsbReceive/UsbReceive/ArduinoCore/src/core/cortex_handlers.c
new file mode 100644
index 0000000000000000000000000000000000000000..a910d08894f90343967ab473da24c1d3f43945b5
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/src/core/cortex_handlers.c
@@ -0,0 +1,188 @@
+/*
+ Copyright (c) 2015 Arduino LLC. All right reserved.
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ See the GNU Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#include <sam.h>
+#include <variant.h>
+#include <stdio.h>
+
+/* RTOS Hooks */
+extern void svcHook(void);
+extern void pendSVHook(void);
+extern int sysTickHook(void);
+
+/* Default empty handler */
+void Dummy_Handler(void)
+{
+#if defined DEBUG
+ __BKPT(3);
+#endif
+ for (;;) { }
+}
+
+/* Cortex-M0+ core handlers */
+void HardFault_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
+void Reset_Handler (void);
+void NMI_Handler (void) __attribute__ ((weak, alias("Dummy_Handler")));
+void SVC_Handler (void) __attribute__ ((weak, alias("Dummy_Handler")));
+void PendSV_Handler (void) __attribute__ ((weak, alias("Dummy_Handler")));
+void SysTick_Handler (void);
+
+/* Peripherals handlers */
+void PM_Handler (void) __attribute__ ((weak, alias("Dummy_Handler")));
+void SYSCTRL_Handler (void) __attribute__ ((weak, alias("Dummy_Handler")));
+void WDT_Handler (void) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTC_Handler (void) __attribute__ ((weak, alias("Dummy_Handler")));
+void EIC_Handler (void) __attribute__ ((weak, alias("Dummy_Handler")));
+void NVMCTRL_Handler (void) __attribute__ ((weak, alias("Dummy_Handler")));
+void DMAC_Handler (void) __attribute__ ((weak, alias("Dummy_Handler")));
+void USB_Handler (void) __attribute__ ((weak));
+void EVSYS_Handler (void) __attribute__ ((weak, alias("Dummy_Handler")));
+void SERCOM0_Handler (void) __attribute__ ((weak, alias("Dummy_Handler")));
+void SERCOM1_Handler (void) __attribute__ ((weak, alias("Dummy_Handler")));
+void SERCOM2_Handler (void) __attribute__ ((weak, alias("Dummy_Handler")));
+void SERCOM3_Handler (void) __attribute__ ((weak, alias("Dummy_Handler")));
+void SERCOM4_Handler (void) __attribute__ ((weak, alias("Dummy_Handler")));
+void SERCOM5_Handler (void) __attribute__ ((weak, alias("Dummy_Handler")));
+void TCC0_Handler (void) __attribute__ ((weak, alias("Dummy_Handler")));
+void TCC1_Handler (void) __attribute__ ((weak, alias("Dummy_Handler")));
+void TCC2_Handler (void) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC3_Handler (void) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC4_Handler (void) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC5_Handler (void) __attribute__ ((weak)); // Used in Tone.cpp
+void TC6_Handler (void) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC7_Handler (void) __attribute__ ((weak, alias("Dummy_Handler")));
+void ADC_Handler (void) __attribute__ ((weak, alias("Dummy_Handler")));
+void AC_Handler (void) __attribute__ ((weak, alias("Dummy_Handler")));
+void DAC_Handler (void) __attribute__ ((weak, alias("Dummy_Handler")));
+void PTC_Handler (void) __attribute__ ((weak, alias("Dummy_Handler")));
+void I2S_Handler (void) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Initialize segments */
+extern uint32_t __etext;
+extern uint32_t __data_start__;
+extern uint32_t __data_end__;
+extern uint32_t __bss_start__;
+extern uint32_t __bss_end__;
+extern uint32_t __StackTop;
+
+/* Exception Table */
+__attribute__ ((section(".isr_vector"))) const DeviceVectors exception_table =
+{
+ /* Configure Initial Stack Pointer, using linker-generated symbols */
+ (void*) (&__StackTop),
+
+ (void*) Reset_Handler,
+ (void*) NMI_Handler,
+ (void*) HardFault_Handler,
+ (void*) (0UL), /* Reserved */
+ (void*) (0UL), /* Reserved */
+ (void*) (0UL), /* Reserved */
+ (void*) (0UL), /* Reserved */
+ (void*) (0UL), /* Reserved */
+ (void*) (0UL), /* Reserved */
+ (void*) (0UL), /* Reserved */
+ (void*) SVC_Handler,
+ (void*) (0UL), /* Reserved */
+ (void*) (0UL), /* Reserved */
+ (void*) PendSV_Handler,
+ (void*) SysTick_Handler,
+
+ /* Configurable interrupts */
+ (void*) PM_Handler, /* 0 Power Manager */
+ (void*) SYSCTRL_Handler, /* 1 System Control */
+ (void*) WDT_Handler, /* 2 Watchdog Timer */
+ (void*) RTC_Handler, /* 3 Real-Time Counter */
+ (void*) EIC_Handler, /* 4 External Interrupt Controller */
+ (void*) NVMCTRL_Handler, /* 5 Non-Volatile Memory Controller */
+ (void*) DMAC_Handler, /* 6 Direct Memory Access Controller */
+ (void*) USB_Handler, /* 7 Universal Serial Bus */
+ (void*) EVSYS_Handler, /* 8 Event System Interface */
+ (void*) SERCOM0_Handler, /* 9 Serial Communication Interface 0 */
+ (void*) SERCOM1_Handler, /* 10 Serial Communication Interface 1 */
+ (void*) SERCOM2_Handler, /* 11 Serial Communication Interface 2 */
+ (void*) SERCOM3_Handler, /* 12 Serial Communication Interface 3 */
+ (void*) SERCOM4_Handler, /* 13 Serial Communication Interface 4 */
+ (void*) SERCOM5_Handler, /* 14 Serial Communication Interface 5 */
+ (void*) TCC0_Handler, /* 15 Timer Counter Control 0 */
+ (void*) TCC1_Handler, /* 16 Timer Counter Control 1 */
+ (void*) TCC2_Handler, /* 17 Timer Counter Control 2 */
+ (void*) TC3_Handler, /* 18 Basic Timer Counter 0 */
+ (void*) TC4_Handler, /* 19 Basic Timer Counter 1 */
+ (void*) TC5_Handler, /* 20 Basic Timer Counter 2 */
+ (void*) TC6_Handler, /* 21 Basic Timer Counter 3 */
+ (void*) TC7_Handler, /* 22 Basic Timer Counter 4 */
+ (void*) ADC_Handler, /* 23 Analog Digital Converter */
+ (void*) AC_Handler, /* 24 Analog Comparators */
+ (void*) DAC_Handler, /* 25 Digital Analog Converter */
+ (void*) PTC_Handler, /* 26 Peripheral Touch Controller */
+ (void*) I2S_Handler, /* 27 Inter-IC Sound Interface */
+ (void*) (0UL), /* Reserved */
+};
+
+extern int main(void);
+
+/* This is called on processor reset to initialize the device and call main() */
+void Reset_Handler(void)
+{
+ uint32_t *pSrc, *pDest;
+
+ /* Initialize the initialized data section */
+ pSrc = &__etext;
+ pDest = &__data_start__;
+
+ if ((&__data_start__ != &__data_end__) && (pSrc != pDest)) {
+ for (; pDest < &__data_end__; pDest++, pSrc++)
+ *pDest = *pSrc;
+ }
+
+ /* Clear the zero section */
+ if ((&__data_start__ != &__data_end__) && (pSrc != pDest)) {
+ for (pDest = &__bss_start__; pDest < &__bss_end__; pDest++)
+ *pDest = 0;
+ }
+
+ SystemInit();
+
+ main();
+
+ while (1)
+ ;
+}
+
+/* Default Arduino systick handler */
+extern void SysTick_DefaultHandler(void);
+
+void SysTick_Handler(void)
+{
+ if (sysTickHook())
+ return;
+ SysTick_DefaultHandler();
+}
+
+static void (*usb_isr)(void) = NULL;
+
+void USB_Handler(void)
+{
+ if (usb_isr)
+ usb_isr();
+}
+
+void USB_SetHandler(void (*new_usb_isr)(void))
+{
+ usb_isr = new_usb_isr;
+}
diff --git a/UsbReceive/UsbReceive/ArduinoCore/src/core/delay.c b/UsbReceive/UsbReceive/ArduinoCore/src/core/delay.c
new file mode 100644
index 0000000000000000000000000000000000000000..84c8ea7e496a31b90ee3480bfb24fb10cb6055ff
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/src/core/delay.c
@@ -0,0 +1,95 @@
+/*
+ Copyright (c) 2015 Arduino LLC. All right reserved.
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ See the GNU Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#include "delay.h"
+#include "Arduino.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Tick Counter united by ms */
+static volatile uint32_t _ulTickCount=0 ;
+
+unsigned long millis( void )
+{
+// todo: ensure no interrupts
+ return _ulTickCount ;
+}
+
+// Interrupt-compatible version of micros
+// Theory: repeatedly take readings of SysTick counter, millis counter and SysTick interrupt pending flag.
+// When it appears that millis counter and pending is stable and SysTick hasn't rolled over, use these
+// values to calculate micros. If there is a pending SysTick, add one to the millis counter in the calculation.
+unsigned long micros( void )
+{
+ uint32_t ticks, ticks2;
+ uint32_t pend, pend2;
+ uint32_t count, count2;
+
+ ticks2 = SysTick->VAL;
+ pend2 = !!(SCB->ICSR & SCB_ICSR_PENDSTSET_Msk) ;
+ count2 = _ulTickCount ;
+
+ do
+ {
+ ticks=ticks2;
+ pend=pend2;
+ count=count2;
+ ticks2 = SysTick->VAL;
+ pend2 = !!(SCB->ICSR & SCB_ICSR_PENDSTSET_Msk) ;
+ count2 = _ulTickCount ;
+ } while ((pend != pend2) || (count != count2) || (ticks < ticks2));
+
+ return ((count+pend) * 1000) + (((SysTick->LOAD - ticks)*(1048576/(VARIANT_MCK/1000000)))>>20) ;
+ // this is an optimization to turn a runtime division into two compile-time divisions and
+ // a runtime multiplication and shift, saving a few cycles
+}
+
+void delay( unsigned long ms )
+{
+ if (ms == 0)
+ {
+ return;
+ }
+
+ uint32_t start = micros();
+
+ while (ms > 0)
+ {
+ yield();
+ while (ms > 0 && (micros() - start) >= 1000)
+ {
+ ms--;
+ start += 1000;
+ }
+ }
+}
+
+#include "Reset.h" // for tickReset()
+
+void SysTick_DefaultHandler(void)
+{
+ // Increment tick count each ms
+ _ulTickCount++;
+ tickReset();
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/UsbReceive/UsbReceive/ArduinoCore/src/core/hooks.c b/UsbReceive/UsbReceive/ArduinoCore/src/core/hooks.c
new file mode 100644
index 0000000000000000000000000000000000000000..f87c20444cefa2bcb3b4b67f149a688b06c122ec
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/src/core/hooks.c
@@ -0,0 +1,58 @@
+/*
+ Copyright (c) 2015 Arduino LLC. All right reserved.
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ See the GNU Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+/**
+ * Empty yield() hook.
+ *
+ * This function is intended to be used by library writers to build
+ * libraries or sketches that supports cooperative threads.
+ *
+ * Its defined as a weak symbol and it can be redefined to implement a
+ * real cooperative scheduler.
+ */
+static void __empty() {
+ // Empty
+}
+void yield(void) __attribute__ ((weak, alias("__empty")));
+
+/**
+ * SysTick hook
+ *
+ * This function is called from SysTick handler, before the default
+ * handler provided by Arduino.
+ */
+static int __false() {
+ // Return false
+ return 0;
+}
+int sysTickHook(void) __attribute__ ((weak, alias("__false")));
+
+/**
+ * SVC hook
+ * PendSV hook
+ *
+ * These functions are called from SVC handler, and PensSV handler.
+ * Default action is halting.
+ */
+static void __halt() {
+ // Halts
+ while (1)
+ ;
+}
+void svcHook(void) __attribute__ ((weak, alias("__halt")));
+void pendSVHook(void) __attribute__ ((weak, alias("__halt")));
diff --git a/UsbReceive/UsbReceive/ArduinoCore/src/core/itoa.c b/UsbReceive/UsbReceive/ArduinoCore/src/core/itoa.c
new file mode 100644
index 0000000000000000000000000000000000000000..f66a7ba537f8def832a5acfa8e7349317f4c4f8e
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/src/core/itoa.c
@@ -0,0 +1,127 @@
+
+/*
+ Copyright (c) 2014 Arduino LLC. All right reserved.
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ See the GNU Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#include "itoa.h"
+#include <string.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern char* itoa(int value, char*string, int radix)
+ {
+ return ltoa(value, string, radix);
+ }
+
+ extern char* ltoa(long value, char*string, int radix)
+ {
+ char tmp[33];
+ char* tp = tmp;
+ long i;
+ unsigned long v;
+ int sign;
+ char* sp;
+
+ if (string == NULL)
+ {
+ return 0;
+ }
+
+ if (radix > 36 || radix <= 1)
+ {
+ return 0;
+ }
+
+ sign = (radix == 10 && value < 0);
+ if (sign)
+ {
+ v = -value;
+ }
+ else
+ {
+ v = (unsigned long)value;
+ }
+
+ while (v || tp == tmp)
+ {
+ i = v % radix;
+ v = v / radix;
+ if (i < 10)
+ *tp++ = i + '0';
+ else
+ *tp++ = i + 'a' - 10;
+ }
+
+ sp = string;
+
+ if (sign)
+ *sp++ = '-';
+ while (tp > tmp)
+ *sp++ = *--tp;
+ *sp = 0;
+
+ return string;
+ }
+
+ extern char* utoa(unsigned value, char*string, int radix)
+ {
+ return ultoa(value, string, radix);
+ }
+
+ extern char* ultoa(unsigned long value, char*string, int radix)
+ {
+ char tmp[33];
+ char* tp = tmp;
+ long i;
+ unsigned long v = value;
+ char* sp;
+
+ if (string == NULL)
+ {
+ return 0;
+ }
+
+ if (radix > 36 || radix <= 1)
+ {
+ return 0;
+ }
+
+ while (v || tp == tmp)
+ {
+ i = v % radix;
+ v = v / radix;
+ if (i < 10)
+ *tp++ = i + '0';
+ else
+ *tp++ = i + 'a' - 10;
+ }
+
+ sp = string;
+
+
+ while (tp > tmp)
+ *sp++ = *--tp;
+ *sp = 0;
+
+ return string;
+ }
+
+# ifdef __cplusplus
+ } // extern "C"
+#endif
\ No newline at end of file
diff --git a/UsbReceive/UsbReceive/ArduinoCore/src/core/main.cpp b/UsbReceive/UsbReceive/ArduinoCore/src/core/main.cpp
new file mode 100644
index 0000000000000000000000000000000000000000..00c2425faab1ce602281508cd214dcf5b90613bb
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/src/core/main.cpp
@@ -0,0 +1,58 @@
+/*
+ Copyright (c) 2015 Arduino LLC. All right reserved.
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ See the GNU Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#define ARDUINO_MAIN
+#include "Arduino.h"
+
+// Weak empty variant initialization function.
+// May be redefined by variant files.
+void initVariant() __attribute__((weak));
+void initVariant() { }
+
+// Initialize C library
+extern "C" void __libc_init_array(void);
+
+/*
+ * \brief Main entry point of Arduino application
+ */
+int main( void )
+{
+ init();
+
+ __libc_init_array();
+
+ initVariant();
+
+ delay(1);
+#if defined(USBCON)
+ #if !defined(USB_NO_INIT)
+ USBDevice.init();
+ USBDevice.attach();
+ #endif
+#endif
+
+ setup();
+
+ for (;;)
+ {
+ loop();
+ if (serialEventRun) serialEventRun();
+ }
+
+ return 0;
+}
diff --git a/UsbReceive/UsbReceive/ArduinoCore/src/core/new.cpp b/UsbReceive/UsbReceive/ArduinoCore/src/core/new.cpp
new file mode 100644
index 0000000000000000000000000000000000000000..f18977585efdf95bc92e5561c369e525023348b5
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/src/core/new.cpp
@@ -0,0 +1,36 @@
+/*
+ Copyright (c) 2014 Arduino. All right reserved.
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ See the GNU Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#include <stdlib.h>
+
+void *operator new(size_t size) {
+ return malloc(size);
+}
+
+void *operator new[](size_t size) {
+ return malloc(size);
+}
+
+void operator delete(void * ptr) {
+ free(ptr);
+}
+
+void operator delete[](void * ptr) {
+ free(ptr);
+}
+
diff --git a/UsbReceive/UsbReceive/ArduinoCore/src/core/pulse.c b/UsbReceive/UsbReceive/ArduinoCore/src/core/pulse.c
new file mode 100644
index 0000000000000000000000000000000000000000..2dd03bf476f8c6dd2596859b8b1eb14fa96b5f0b
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/src/core/pulse.c
@@ -0,0 +1,52 @@
+/*
+ Copyright (c) 2015 Arduino LLC. All right reserved.
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ See the GNU Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#include <Arduino.h>
+
+// See pulse_asm.S
+extern unsigned long countPulseASM(const volatile uint32_t *port, uint32_t bit, uint32_t stateMask, unsigned long maxloops);
+
+/* Measures the length (in microseconds) of a pulse on the pin; state is HIGH
+ * or LOW, the type of pulse to measure. Works on pulses from 2-3 microseconds
+ * to 3 minutes in length, but must be called at least a few dozen microseconds
+ * before the start of the pulse. */
+uint32_t pulseIn(uint32_t pin, uint32_t state, uint32_t timeout)
+{
+ // cache the port and bit of the pin in order to speed up the
+ // pulse width measuring loop and achieve finer resolution. calling
+ // digitalRead() instead yields much coarser resolution.
+ PinDescription p = g_APinDescription[pin];
+ uint32_t bit = 1 << p.ulPin;
+ uint32_t stateMask = state ? bit : 0;
+
+ // convert the timeout from microseconds to a number of times through
+ // the initial loop; it takes (roughly) 13 clock cycles per iteration.
+ uint32_t maxloops = microsecondsToClockCycles(timeout) / 13;
+
+ uint32_t width = countPulseASM(&(PORT->Group[p.ulPort].IN.reg), bit, stateMask, maxloops);
+
+ // convert the reading to microseconds. The loop has been determined
+ // to be 13 clock cycles long and have about 16 clocks between the edge
+ // and the start of the loop. There will be some error introduced by
+ // the interrupt handlers.
+ if (width)
+ return clockCyclesToMicroseconds(width * 13 + 16);
+ else
+ return 0;
+}
+
diff --git a/UsbReceive/UsbReceive/ArduinoCore/src/core/pulse_asm.S b/UsbReceive/UsbReceive/ArduinoCore/src/core/pulse_asm.S
new file mode 100644
index 0000000000000000000000000000000000000000..7b94f158bfce52b76d3901d1bfd4eefa2b2016d8
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/src/core/pulse_asm.S
@@ -0,0 +1,175 @@
+/*
+ Copyright (c) 2015 Arduino LLC. All right reserved.
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ See the GNU Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+/*
+
+The following function has been compiled to ASM with gcc
+
+ unsigned long countPulseASM(const volatile uint32_t *port, uint32_t bit, uint32_t stateMask, unsigned long maxloops)
+ {
+ unsigned long width = 0;
+
+ // wait for any previous pulse to end
+ while ((*port & bit) == stateMask)
+ if (--maxloops == 0)
+ return 0;
+
+ // wait for the pulse to start
+ while ((*port & bit) != stateMask)
+ if (--maxloops == 0)
+ return 0;
+
+ // wait for the pulse to stop
+ while ((*port & bit) == stateMask) {
+ if (++width == maxloops)
+ return 0;
+ }
+ return width;
+ }
+
+using the command line:
+
+ arm-none-eabi-gcc -mcpu=cortex-m0plus -mthumb -c -Os -W -ffunction-sections -fdata-sections \
+ -nostdlib --param max-inline-insns-single=500 -fno-exceptions -MMD \
+ -DF_CPU=48000000L -DARDUINO=10602 -DARDUINO_SAMD_ZERO -DARDUINO_ARCH_SAMD \
+ -D__SAMD21G18A__ -DUSB_VID=0x2341 -DUSB_PID=0x004d -DUSBCON \
+ -DUSB_MANUFACTURER="Arduino LLC" -DUSB_PRODUCT="Arduino Zero" \
+ -I/Code/arduino/build/linux/work/hardware/tools/CMSIS/CMSIS/Include/ \
+ -I/Code/arduino/build/linux/work/hardware/tools/CMSIS/Device/ATMEL/ \
+ -I/Code/arduino/build/linux/work/hardware/arduino/samd/cores/arduino \
+ -I/Code/arduino/build/linux/work/hardware/arduino/samd/variants/arduino_zero \
+ count.c -Wa,-ahlmsd=output.lst -dp -fverbose-asm -S
+
+The result has been slightly edited to increase readability.
+
+*/
+
+ .cpu cortex-m0plus
+ .fpu softvfp
+ .eabi_attribute 20, 1 @ Tag_ABI_FP_denormal
+ .eabi_attribute 21, 1 @ Tag_ABI_FP_exceptions
+ .eabi_attribute 23, 3 @ Tag_ABI_FP_number_model
+ .eabi_attribute 24, 1 @ Tag_ABI_align8_needed
+ .eabi_attribute 25, 1 @ Tag_ABI_align8_preserved
+ .eabi_attribute 26, 1 @ Tag_ABI_enum_size
+ .eabi_attribute 30, 4 @ Tag_ABI_optimization_goals
+ .eabi_attribute 34, 0 @ Tag_CPU_unaligned_access
+ .eabi_attribute 18, 4 @ Tag_ABI_PCS_wchar_t
+ .file "count.c"
+@ GNU C (GNU Tools for ARM Embedded Processors (Arduino build)) version 4.8.3 20140228 (release) [ARM/embedded-4_8-branch revision 208322] (arm-none-eabi)
+@ compiled by GNU C version 4.3.2, GMP version 4.3.2, MPFR version 2.4.2, MPC version 0.8.1
+@ GGC heuristics: --param ggc-min-expand=100 --param ggc-min-heapsize=131072
+@ options passed:
+@ -I /Code/arduino/build/linux/work/hardware/tools/CMSIS/CMSIS/Include/
+@ -I /Code/arduino/build/linux/work/hardware/tools/CMSIS/Device/ATMEL/
+@ -I /Code/arduino/build/linux/work/hardware/arduino/samd/cores/arduino
+@ -I /Code/arduino/build/linux/work/hardware/arduino/samd/variants/arduino_zero
+@ -imultilib armv6-m
+@ -iprefix /Code/arduino/build/linux/work/hardware/tools/gcc-arm-none-eabi-4.8.3-2014q1/bin/../lib/gcc/arm-none-eabi/4.8.3/
+@ -isysroot /Code/arduino/build/linux/work/hardware/tools/gcc-arm-none-eabi-4.8.3-2014q1/bin/../arm-none-eabi
+@ -MMD count.d -D__USES_INITFINI__ -D F_CPU=48000000L -D ARDUINO=10602
+@ -D ARDUINO_SAMD_ZERO -D ARDUINO_ARCH_SAMD -D __SAMD21G18A__
+@ -D USB_VID=0x2341 -D USB_PID=0x004d -D USBCON
+@ -D USB_MANUFACTURER=Arduino LLC -D USB_PRODUCT=Arduino Zero count.c
+@ -mcpu=cortex-m0plus -mthumb -Os -Wextra -ffunction-sections
+@ -fdata-sections -fno-exceptions -fverbose-asm
+@ --param max-inline-insns-single=500
+@ options enabled: -faggressive-loop-optimizations -fauto-inc-dec
+@ -fbranch-count-reg -fcaller-saves -fcombine-stack-adjustments -fcommon
+@ -fcompare-elim -fcprop-registers -fcrossjumping -fcse-follow-jumps
+@ -fdata-sections -fdefer-pop -fdelete-null-pointer-checks -fdevirtualize
+@ -fdwarf2-cfi-asm -fearly-inlining -feliminate-unused-debug-types
+@ -fexpensive-optimizations -fforward-propagate -ffunction-cse
+@ -ffunction-sections -fgcse -fgcse-lm -fgnu-runtime
+@ -fguess-branch-probability -fhoist-adjacent-loads -fident -fif-conversion
+@ -fif-conversion2 -findirect-inlining -finline -finline-atomics
+@ -finline-functions -finline-functions-called-once
+@ -finline-small-functions -fipa-cp -fipa-profile -fipa-pure-const
+@ -fipa-reference -fipa-sra -fira-hoist-pressure -fira-share-save-slots
+@ -fira-share-spill-slots -fivopts -fkeep-static-consts
+@ -fleading-underscore -fmath-errno -fmerge-constants -fmerge-debug-strings
+@ -fomit-frame-pointer -foptimize-register-move -foptimize-sibling-calls
+@ -fpartial-inlining -fpeephole -fpeephole2 -fprefetch-loop-arrays
+@ -freg-struct-return -fregmove -freorder-blocks -freorder-functions
+@ -frerun-cse-after-loop -fsched-critical-path-heuristic
+@ -fsched-dep-count-heuristic -fsched-group-heuristic -fsched-interblock
+@ -fsched-last-insn-heuristic -fsched-pressure -fsched-rank-heuristic
+@ -fsched-spec -fsched-spec-insn-heuristic -fsched-stalled-insns-dep
+@ -fschedule-insns2 -fsection-anchors -fshow-column -fshrink-wrap
+@ -fsigned-zeros -fsplit-ivs-in-unroller -fsplit-wide-types
+@ -fstrict-aliasing -fstrict-overflow -fstrict-volatile-bitfields
+@ -fsync-libcalls -fthread-jumps -ftoplevel-reorder -ftrapping-math
+@ -ftree-bit-ccp -ftree-builtin-call-dce -ftree-ccp -ftree-ch
+@ -ftree-coalesce-vars -ftree-copy-prop -ftree-copyrename -ftree-cselim
+@ -ftree-dce -ftree-dominator-opts -ftree-dse -ftree-forwprop -ftree-fre
+@ -ftree-loop-if-convert -ftree-loop-im -ftree-loop-ivcanon
+@ -ftree-loop-optimize -ftree-parallelize-loops= -ftree-phiprop -ftree-pre
+@ -ftree-pta -ftree-reassoc -ftree-scev-cprop -ftree-sink
+@ -ftree-slp-vectorize -ftree-slsr -ftree-sra -ftree-switch-conversion
+@ -ftree-tail-merge -ftree-ter -ftree-vect-loop-version -ftree-vrp
+@ -funit-at-a-time -fverbose-asm -fzero-initialized-in-bss -mlittle-endian
+@ -mpic-data-is-text-relative -msched-prolog -mthumb
+@ -mvectorize-with-neon-quad
+
+ .section .text.countPulseASM,"ax",%progbits
+ .align 1
+ .global countPulseASM
+ .code 16
+ .thumb_func
+ .type countPulseASM, %function
+countPulseASM:
+ push {r4, r5, lr} @ @ 112 *push_multi [length = 2]
+.L2:
+ ldr r4, [r0] @ D.11539, *port_7(D) @ 22 *thumb1_movsi_insn/7 [length = 2]
+ and r4, r1 @ D.11539, bit @ 24 *thumb1_andsi3_insn [length = 2]
+ cmp r4, r2 @ D.11539, stateMask @ 25 cbranchsi4_insn/1 [length = 4]
+ bne .L5 @,
+ sub r3, r3, #1 @ maxloops, @ 17 *thumb1_addsi3/2 [length = 2]
+ cmp r3, #0 @ maxloops, @ 18 cbranchsi4_insn/1 [length = 4]
+ bne .L2 @,
+ b .L10 @ @ 127 *thumb_jump [length = 2]
+.L6:
+ sub r3, r3, #1 @ maxloops, @ 30 *thumb1_addsi3/2 [length = 2]
+ cmp r3, #0 @ maxloops, @ 31 cbranchsi4_insn/1 [length = 4]
+ beq .L10 @,
+.L5:
+ ldr r4, [r0] @ D.11539, *port_7(D) @ 35 *thumb1_movsi_insn/7 [length = 2]
+ and r4, r1 @ D.11539, bit @ 37 *thumb1_andsi3_insn [length = 2]
+ cmp r4, r2 @ D.11539, stateMask @ 38 cbranchsi4_insn/1 [length = 4]
+ bne .L6 @,
+ mov r4, #0 @ width, @ 7 *thumb1_movsi_insn/2 [length = 2]
+.L7:
+ ldr r5, [r0] @ D.11539, *port_7(D) @ 48 *thumb1_movsi_insn/7 [length = 2]
+ and r5, r1 @ D.11539, bit @ 50 *thumb1_andsi3_insn [length = 2]
+ cmp r5, r2 @ D.11539, stateMask @ 51 cbranchsi4_insn/1 [length = 4]
+ bne .L13 @,
+ add r4, r4, #1 @ width, @ 43 *thumb1_addsi3/1 [length = 2]
+ cmp r4, r3 @ width, maxloops @ 44 cbranchsi4_insn/1 [length = 4]
+ bne .L7 @,
+ mov r0, #0 @ D.11539, @ 11 *thumb1_movsi_insn/2 [length = 2]
+ b .L3 @ @ 130 *thumb_jump [length = 2]
+.L13:
+ mov r0, r4 @ D.11539, width @ 9 *thumb1_movsi_insn/1 [length = 2]
+ b .L3 @ @ 132 *thumb_jump [length = 2]
+.L10:
+ mov r0, r3 @ D.11539, maxloops @ 8 *thumb1_movsi_insn/1 [length = 2]
+.L3:
+ @ sp needed @ @ 115 force_register_use [length = 0]
+ pop {r4, r5, pc}
+ .size countPulseASM, .-countPulseASM
+ .ident "GCC: (GNU Tools for ARM Embedded Processors (Arduino build)) 4.8.3 20140228 (release) [ARM/embedded-4_8-branch revision 208322]"
diff --git a/UsbReceive/UsbReceive/ArduinoCore/src/core/startup.c b/UsbReceive/UsbReceive/ArduinoCore/src/core/startup.c
new file mode 100644
index 0000000000000000000000000000000000000000..2a1aed63389cd9385ce3fc52a257dd0900360770
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/src/core/startup.c
@@ -0,0 +1,301 @@
+/*
+ Copyright (c) 2015 Arduino LLC. All right reserved.
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ See the GNU Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#include "sam.h"
+#include "variant.h"
+
+#include <stdio.h>
+
+/**
+ * \brief SystemInit() configures the needed clocks and according Flash Read Wait States.
+ * At reset:
+ * - OSC8M clock source is enabled with a divider by 8 (1MHz).
+ * - Generic Clock Generator 0 (GCLKMAIN) is using OSC8M as source.
+ * We need to:
+ * 1) Enable XOSC32K clock (External on-board 32.768Hz oscillator), will be used as DFLL48M reference.
+ * 2) Put XOSC32K as source of Generic Clock Generator 1
+ * 3) Put Generic Clock Generator 1 as source for Generic Clock Multiplexer 0 (DFLL48M reference)
+ * 4) Enable DFLL48M clock
+ * 5) Switch Generic Clock Generator 0 to DFLL48M. CPU will run at 48MHz.
+ * 6) Modify PRESCaler value of OSCM to have 8MHz
+ * 7) Put OSC8M as source for Generic Clock Generator 3
+ */
+// Constants for Clock generators
+#define GENERIC_CLOCK_GENERATOR_MAIN (0u)
+#define GENERIC_CLOCK_GENERATOR_XOSC32K (1u)
+#define GENERIC_CLOCK_GENERATOR_OSC32K (1u)
+#define GENERIC_CLOCK_GENERATOR_OSCULP32K (2u) /* Initialized at reset for WDT */
+#define GENERIC_CLOCK_GENERATOR_OSC8M (3u)
+// Constants for Clock multiplexers
+#define GENERIC_CLOCK_MULTIPLEXER_DFLL48M (0u)
+
+void SystemInit( void )
+{
+ /* Set 1 Flash Wait State for 48MHz, cf tables 20.9 and 35.27 in SAMD21 Datasheet */
+ NVMCTRL->CTRLB.bit.RWS = NVMCTRL_CTRLB_RWS_HALF_Val ;
+
+ /* Turn on the digital interface clock */
+ PM->APBAMASK.reg |= PM_APBAMASK_GCLK ;
+
+
+#if defined(CRYSTALLESS)
+
+ /* ----------------------------------------------------------------------------------------------
+ * 1) Enable OSC32K clock (Internal 32.768Hz oscillator)
+ */
+
+ uint32_t calib = (*((uint32_t *) FUSES_OSC32K_CAL_ADDR) & FUSES_OSC32K_CAL_Msk) >> FUSES_OSC32K_CAL_Pos;
+
+ SYSCTRL->OSC32K.reg = SYSCTRL_OSC32K_CALIB(calib) |
+ SYSCTRL_OSC32K_STARTUP( 0x3u ) | // cf table 15.10 of product datasheet in chapter 15.8.6
+ SYSCTRL_OSC32K_EN32K |
+ SYSCTRL_OSC32K_ENABLE;
+
+ while ( (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_OSC32KRDY) == 0 ); // Wait for oscillator stabilization
+
+#else // has crystal
+
+ /* ----------------------------------------------------------------------------------------------
+ * 1) Enable XOSC32K clock (External on-board 32.768Hz oscillator)
+ */
+ SYSCTRL->XOSC32K.reg = SYSCTRL_XOSC32K_STARTUP( 0x3u ) | /* cf table 15.10 of product datasheet in chapter 15.8.6 */
+ SYSCTRL_XOSC32K_XTALEN | SYSCTRL_XOSC32K_EN32K ;
+ SYSCTRL->XOSC32K.bit.ENABLE = 1 ; /* separate call, as described in chapter 15.6.3 */
+
+ while ( (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_XOSC32KRDY) == 0 )
+ {
+ /* Wait for oscillator stabilization */
+ }
+
+#endif
+
+ /* Software reset the module to ensure it is re-initialized correctly */
+ /* Note: Due to synchronization, there is a delay from writing CTRL.SWRST until the reset is complete.
+ * CTRL.SWRST and STATUS.SYNCBUSY will both be cleared when the reset is complete, as described in chapter 13.8.1
+ */
+ GCLK->CTRL.reg = GCLK_CTRL_SWRST ;
+
+ while ( (GCLK->CTRL.reg & GCLK_CTRL_SWRST) && (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY) )
+ {
+ /* Wait for reset to complete */
+ }
+
+ /* ----------------------------------------------------------------------------------------------
+ * 2) Put XOSC32K as source of Generic Clock Generator 1
+ */
+ GCLK->GENDIV.reg = GCLK_GENDIV_ID( GENERIC_CLOCK_GENERATOR_XOSC32K ) ; // Generic Clock Generator 1
+
+ while ( GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY )
+ {
+ /* Wait for synchronization */
+ }
+
+ /* Write Generic Clock Generator 1 configuration */
+ GCLK->GENCTRL.reg = GCLK_GENCTRL_ID( GENERIC_CLOCK_GENERATOR_OSC32K ) | // Generic Clock Generator 1
+#if defined(CRYSTALLESS)
+ GCLK_GENCTRL_SRC_OSC32K | // Selected source is Internal 32KHz Oscillator
+#else
+ GCLK_GENCTRL_SRC_XOSC32K | // Selected source is External 32KHz Oscillator
+#endif
+// GCLK_GENCTRL_OE | // Output clock to a pin for tests
+ GCLK_GENCTRL_GENEN ;
+
+ while ( GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY )
+ {
+ /* Wait for synchronization */
+ }
+
+ /* ----------------------------------------------------------------------------------------------
+ * 3) Put Generic Clock Generator 1 as source for Generic Clock Multiplexer 0 (DFLL48M reference)
+ */
+ GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID( GENERIC_CLOCK_MULTIPLEXER_DFLL48M ) | // Generic Clock Multiplexer 0
+ GCLK_CLKCTRL_GEN_GCLK1 | // Generic Clock Generator 1 is source
+ GCLK_CLKCTRL_CLKEN ;
+
+ while ( GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY )
+ {
+ /* Wait for synchronization */
+ }
+
+ /* ----------------------------------------------------------------------------------------------
+ * 4) Enable DFLL48M clock
+ */
+
+ /* DFLL Configuration in Closed Loop mode, cf product datasheet chapter 15.6.7.1 - Closed-Loop Operation */
+
+ /* Remove the OnDemand mode, Bug http://avr32.icgroup.norway.atmel.com/bugzilla/show_bug.cgi?id=9905 */
+ SYSCTRL->DFLLCTRL.reg = SYSCTRL_DFLLCTRL_ENABLE;
+
+ while ( (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY) == 0 )
+ {
+ /* Wait for synchronization */
+ }
+
+ SYSCTRL->DFLLMUL.reg = SYSCTRL_DFLLMUL_CSTEP( 31 ) | // Coarse step is 31, half of the max value
+ SYSCTRL_DFLLMUL_FSTEP( 511 ) | // Fine step is 511, half of the max value
+ SYSCTRL_DFLLMUL_MUL( (VARIANT_MCK + VARIANT_MAINOSC/2) / VARIANT_MAINOSC ) ; // External 32KHz is the reference
+
+ while ( (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY) == 0 )
+ {
+ /* Wait for synchronization */
+ }
+
+#if defined(CRYSTALLESS)
+
+ #define NVM_SW_CALIB_DFLL48M_COARSE_VAL 58
+
+ // Turn on DFLL
+ uint32_t coarse =( *((uint32_t *)(NVMCTRL_OTP4) + (NVM_SW_CALIB_DFLL48M_COARSE_VAL / 32)) >> (NVM_SW_CALIB_DFLL48M_COARSE_VAL % 32) )
+ & ((1 << 6) - 1);
+ if (coarse == 0x3f) {
+ coarse = 0x1f;
+ }
+ // TODO(tannewt): Load this value from memory we've written previously. There
+ // isn't a value from the Atmel factory.
+ uint32_t fine = 0x1ff;
+
+ SYSCTRL->DFLLVAL.bit.COARSE = coarse;
+ SYSCTRL->DFLLVAL.bit.FINE = fine;
+ /* Write full configuration to DFLL control register */
+ SYSCTRL->DFLLMUL.reg = SYSCTRL_DFLLMUL_CSTEP( 0x1f / 4 ) | // Coarse step is 31, half of the max value
+ SYSCTRL_DFLLMUL_FSTEP( 10 ) |
+ SYSCTRL_DFLLMUL_MUL( (48000) ) ;
+
+ SYSCTRL->DFLLCTRL.reg = 0;
+
+ while ( (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY) == 0 )
+ {
+ /* Wait for synchronization */
+ }
+
+ SYSCTRL->DFLLCTRL.reg = SYSCTRL_DFLLCTRL_MODE |
+ SYSCTRL_DFLLCTRL_CCDIS |
+ SYSCTRL_DFLLCTRL_USBCRM | /* USB correction */
+ SYSCTRL_DFLLCTRL_BPLCKC;
+
+ while ( (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY) == 0 )
+ {
+ /* Wait for synchronization */
+ }
+
+ /* Enable the DFLL */
+ SYSCTRL->DFLLCTRL.reg |= SYSCTRL_DFLLCTRL_ENABLE ;
+
+#else // has crystal
+
+ /* Write full configuration to DFLL control register */
+ SYSCTRL->DFLLCTRL.reg |= SYSCTRL_DFLLCTRL_MODE | /* Enable the closed loop mode */
+ SYSCTRL_DFLLCTRL_WAITLOCK |
+ SYSCTRL_DFLLCTRL_QLDIS ; /* Disable Quick lock */
+
+ while ( (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY) == 0 )
+ {
+ /* Wait for synchronization */
+ }
+
+ /* Enable the DFLL */
+ SYSCTRL->DFLLCTRL.reg |= SYSCTRL_DFLLCTRL_ENABLE ;
+
+ while ( (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLLCKC) == 0 ||
+ (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLLCKF) == 0 )
+ {
+ /* Wait for locks flags */
+ }
+
+#endif
+
+ while ( (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY) == 0 )
+ {
+ /* Wait for synchronization */
+ }
+
+ /* ----------------------------------------------------------------------------------------------
+ * 5) Switch Generic Clock Generator 0 to DFLL48M. CPU will run at 48MHz.
+ */
+ GCLK->GENDIV.reg = GCLK_GENDIV_ID( GENERIC_CLOCK_GENERATOR_MAIN ) ; // Generic Clock Generator 0
+
+ while ( GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY )
+ {
+ /* Wait for synchronization */
+ }
+
+ /* Write Generic Clock Generator 0 configuration */
+ GCLK->GENCTRL.reg = GCLK_GENCTRL_ID( GENERIC_CLOCK_GENERATOR_MAIN ) | // Generic Clock Generator 0
+ GCLK_GENCTRL_SRC_DFLL48M | // Selected source is DFLL 48MHz
+// GCLK_GENCTRL_OE | // Output clock to a pin for tests
+ GCLK_GENCTRL_IDC | // Set 50/50 duty cycle
+ GCLK_GENCTRL_GENEN ;
+
+ while ( GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY )
+ {
+ /* Wait for synchronization */
+ }
+
+ /* ----------------------------------------------------------------------------------------------
+ * 6) Modify PRESCaler value of OSC8M to have 8MHz
+ */
+ SYSCTRL->OSC8M.bit.PRESC = SYSCTRL_OSC8M_PRESC_0_Val ; //CMSIS 4.5 changed the prescaler defines
+ SYSCTRL->OSC8M.bit.ONDEMAND = 0 ;
+
+ /* ----------------------------------------------------------------------------------------------
+ * 7) Put OSC8M as source for Generic Clock Generator 3
+ */
+ GCLK->GENDIV.reg = GCLK_GENDIV_ID( GENERIC_CLOCK_GENERATOR_OSC8M ) ; // Generic Clock Generator 3
+
+ /* Write Generic Clock Generator 3 configuration */
+ GCLK->GENCTRL.reg = GCLK_GENCTRL_ID( GENERIC_CLOCK_GENERATOR_OSC8M ) | // Generic Clock Generator 3
+ GCLK_GENCTRL_SRC_OSC8M | // Selected source is RC OSC 8MHz (already enabled at reset)
+// GCLK_GENCTRL_OE | // Output clock to a pin for tests
+ GCLK_GENCTRL_GENEN ;
+
+ while ( GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY )
+ {
+ /* Wait for synchronization */
+ }
+
+ /*
+ * Now that all system clocks are configured, we can set CPU and APBx BUS clocks.
+ * There values are normally the one present after Reset.
+ */
+ PM->CPUSEL.reg = PM_CPUSEL_CPUDIV_DIV1 ;
+ PM->APBASEL.reg = PM_APBASEL_APBADIV_DIV1_Val ;
+ PM->APBBSEL.reg = PM_APBBSEL_APBBDIV_DIV1_Val ;
+ PM->APBCSEL.reg = PM_APBCSEL_APBCDIV_DIV1_Val ;
+
+ SystemCoreClock=VARIANT_MCK ;
+
+ /* ----------------------------------------------------------------------------------------------
+ * 8) Load ADC factory calibration values
+ */
+
+ // ADC Bias Calibration
+ uint32_t bias = (*((uint32_t *) ADC_FUSES_BIASCAL_ADDR) & ADC_FUSES_BIASCAL_Msk) >> ADC_FUSES_BIASCAL_Pos;
+
+ // ADC Linearity bits 4:0
+ uint32_t linearity = (*((uint32_t *) ADC_FUSES_LINEARITY_0_ADDR) & ADC_FUSES_LINEARITY_0_Msk) >> ADC_FUSES_LINEARITY_0_Pos;
+
+ // ADC Linearity bits 7:5
+ linearity |= ((*((uint32_t *) ADC_FUSES_LINEARITY_1_ADDR) & ADC_FUSES_LINEARITY_1_Msk) >> ADC_FUSES_LINEARITY_1_Pos) << 5;
+
+ ADC->CALIB.reg = ADC_CALIB_BIAS_CAL(bias) | ADC_CALIB_LINEARITY_CAL(linearity);
+
+ /*
+ * 9) Disable automatic NVM write operations
+ */
+ NVMCTRL->CTRLB.bit.MANW = 1;
+}
diff --git a/UsbReceive/UsbReceive/ArduinoCore/src/core/wiring.c b/UsbReceive/UsbReceive/ArduinoCore/src/core/wiring.c
new file mode 100644
index 0000000000000000000000000000000000000000..894e91b465e92efb395ed85f3bbb83a8a950fb1d
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/src/core/wiring.c
@@ -0,0 +1,132 @@
+/*
+ Copyright (c) 2015 Arduino LLC. All right reserved.
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ See the GNU Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#include "Arduino.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * System Core Clock is at 1MHz (8MHz/8) at Reset.
+ * It is switched to 48MHz in the Reset Handler (startup.c)
+ */
+uint32_t SystemCoreClock=1000000ul ;
+
+/*
+void calibrateADC()
+{
+ volatile uint32_t valeur = 0;
+
+ for(int i = 0; i < 5; ++i)
+ {
+ ADC->SWTRIG.bit.START = 1;
+ while( ADC->INTFLAG.bit.RESRDY == 0 || ADC->STATUS.bit.SYNCBUSY == 1 )
+ {
+ // Waiting for a complete conversion and complete synchronization
+ }
+
+ valeur += ADC->RESULT.bit.RESULT;
+ }
+
+ valeur = valeur/5;
+}*/
+
+/*
+ * Arduino Zero board initialization
+ *
+ * Good to know:
+ * - At reset, ResetHandler did the system clock configuration. Core is running at 48MHz.
+ * - Watchdog is disabled by default, unless someone plays with NVM User page
+ * - During reset, all PORT lines are configured as inputs with input buffers, output buffers and pull disabled.
+ */
+void init( void )
+{
+ // Set Systick to 1ms interval, common to all Cortex-M variants
+ if ( SysTick_Config( SystemCoreClock / 1000 ) )
+ {
+ // Capture error
+ while ( 1 ) ;
+ }
+ NVIC_SetPriority (SysTick_IRQn, (1 << __NVIC_PRIO_BITS) - 2); /* set Priority for Systick Interrupt (2nd lowest) */
+
+ // Clock PORT for Digital I/O
+// PM->APBBMASK.reg |= PM_APBBMASK_PORT ;
+//
+// // Clock EIC for I/O interrupts
+// PM->APBAMASK.reg |= PM_APBAMASK_EIC ;
+
+ // Clock SERCOM for Serial
+ PM->APBCMASK.reg |= PM_APBCMASK_SERCOM0 | PM_APBCMASK_SERCOM1 | PM_APBCMASK_SERCOM2 | PM_APBCMASK_SERCOM3 | PM_APBCMASK_SERCOM4 | PM_APBCMASK_SERCOM5 ;
+
+ // Clock TC/TCC for Pulse and Analog
+ PM->APBCMASK.reg |= PM_APBCMASK_TCC0 | PM_APBCMASK_TCC1 | PM_APBCMASK_TCC2 | PM_APBCMASK_TC3 | PM_APBCMASK_TC4 | PM_APBCMASK_TC5 ;
+
+ // Clock ADC/DAC for Analog
+ PM->APBCMASK.reg |= PM_APBCMASK_ADC | PM_APBCMASK_DAC ;
+
+// Defining VERY_LOW_POWER breaks Arduino APIs since all pins are considered INPUT at startup
+// However, it really lowers the power consumption by a factor of 20 in low power mode (0.03mA vs 0.6mA)
+#ifndef VERY_LOW_POWER
+ // Setup all pins (digital and analog) in INPUT mode (default is nothing)
+ for (uint32_t ul = 0 ; ul < NUM_DIGITAL_PINS ; ul++ )
+ {
+ pinMode( ul, INPUT ) ;
+ }
+#endif
+
+ // Initialize Analog Controller
+ // Setting clock
+ while(GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY);
+
+ GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID( GCM_ADC ) | // Generic Clock ADC
+ GCLK_CLKCTRL_GEN_GCLK0 | // Generic Clock Generator 0 is source
+ GCLK_CLKCTRL_CLKEN ;
+
+ while( ADC->STATUS.bit.SYNCBUSY == 1 ); // Wait for synchronization of registers between the clock domains
+
+ ADC->CTRLB.reg = ADC_CTRLB_PRESCALER_DIV512 | // Divide Clock by 512.
+ ADC_CTRLB_RESSEL_10BIT; // 10 bits resolution as default
+
+ ADC->SAMPCTRL.reg = 0x3f; // Set max Sampling Time Length
+
+ while( ADC->STATUS.bit.SYNCBUSY == 1 ); // Wait for synchronization of registers between the clock domains
+
+ ADC->INPUTCTRL.reg = ADC_INPUTCTRL_MUXNEG_GND; // No Negative input (Internal Ground)
+
+ // Averaging (see datasheet table in AVGCTRL register description)
+ ADC->AVGCTRL.reg = ADC_AVGCTRL_SAMPLENUM_1 | // 1 sample only (no oversampling nor averaging)
+ ADC_AVGCTRL_ADJRES(0x0ul); // Adjusting result by 0
+
+ analogReference( AR_DEFAULT ) ; // Analog Reference is AREF pin (3.3v)
+
+ // Initialize DAC
+ // Setting clock
+ while ( GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY );
+ GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID( GCM_DAC ) | // Generic Clock ADC
+ GCLK_CLKCTRL_GEN_GCLK0 | // Generic Clock Generator 0 is source
+ GCLK_CLKCTRL_CLKEN ;
+
+ while ( DAC->STATUS.bit.SYNCBUSY == 1 ); // Wait for synchronization of registers between the clock domains
+ DAC->CTRLB.reg = DAC_CTRLB_REFSEL_AVCC | // Using the 3.3V reference
+ DAC_CTRLB_EOEN ; // External Output Enable (Vout)
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/UsbReceive/UsbReceive/ArduinoCore/src/core/wiring_analog.c b/UsbReceive/UsbReceive/ArduinoCore/src/core/wiring_analog.c
new file mode 100644
index 0000000000000000000000000000000000000000..8655f6ecf69a4afb38894f541f20259792887799
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/src/core/wiring_analog.c
@@ -0,0 +1,321 @@
+/*
+ Copyright (c) 2014 Arduino LLC. All right reserved.
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ See the GNU Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#include "Arduino.h"
+#include "wiring_private.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+static int _readResolution = 10;
+static int _ADCResolution = 10;
+static int _writeResolution = 8;
+
+// Wait for synchronization of registers between the clock domains
+static __inline__ void syncADC() __attribute__((always_inline, unused));
+static void syncADC() {
+ while (ADC->STATUS.bit.SYNCBUSY == 1)
+ ;
+}
+
+// Wait for synchronization of registers between the clock domains
+static __inline__ void syncDAC() __attribute__((always_inline, unused));
+static void syncDAC() {
+ while (DAC->STATUS.bit.SYNCBUSY == 1)
+ ;
+}
+
+// Wait for synchronization of registers between the clock domains
+static __inline__ void syncTC_16(Tc* TCx) __attribute__((always_inline, unused));
+static void syncTC_16(Tc* TCx) {
+ while (TCx->COUNT16.STATUS.bit.SYNCBUSY);
+}
+
+// Wait for synchronization of registers between the clock domains
+static __inline__ void syncTCC(Tcc* TCCx) __attribute__((always_inline, unused));
+static void syncTCC(Tcc* TCCx) {
+ while (TCCx->SYNCBUSY.reg & TCC_SYNCBUSY_MASK);
+}
+
+void analogReadResolution(int res)
+{
+ _readResolution = res;
+ if (res > 10) {
+ ADC->CTRLB.bit.RESSEL = ADC_CTRLB_RESSEL_12BIT_Val;
+ _ADCResolution = 12;
+ } else if (res > 8) {
+ ADC->CTRLB.bit.RESSEL = ADC_CTRLB_RESSEL_10BIT_Val;
+ _ADCResolution = 10;
+ } else {
+ ADC->CTRLB.bit.RESSEL = ADC_CTRLB_RESSEL_8BIT_Val;
+ _ADCResolution = 8;
+ }
+ syncADC();
+}
+
+void analogWriteResolution(int res)
+{
+ _writeResolution = res;
+}
+
+static inline uint32_t mapResolution(uint32_t value, uint32_t from, uint32_t to)
+{
+ if (from == to) {
+ return value;
+ }
+ if (from > to) {
+ return value >> (from-to);
+ }
+ return value << (to-from);
+}
+
+/*
+ * Internal Reference is at 1.0v
+ * External Reference should be between 1v and VDDANA-0.6v=2.7v
+ *
+ * Warning : On Arduino Zero board the input/output voltage for SAMD21G18 is 3.3 volts maximum
+ */
+void analogReference(eAnalogReference mode)
+{
+ syncADC();
+ switch (mode)
+ {
+ case AR_INTERNAL:
+ case AR_INTERNAL2V23:
+ ADC->INPUTCTRL.bit.GAIN = ADC_INPUTCTRL_GAIN_1X_Val; // Gain Factor Selection
+ ADC->REFCTRL.bit.REFSEL = ADC_REFCTRL_REFSEL_INTVCC0_Val; // 1/1.48 VDDANA = 1/1.48* 3V3 = 2.2297
+ break;
+
+ case AR_EXTERNAL:
+ ADC->INPUTCTRL.bit.GAIN = ADC_INPUTCTRL_GAIN_1X_Val; // Gain Factor Selection
+ ADC->REFCTRL.bit.REFSEL = ADC_REFCTRL_REFSEL_AREFA_Val;
+ break;
+
+ case AR_INTERNAL1V0:
+ ADC->INPUTCTRL.bit.GAIN = ADC_INPUTCTRL_GAIN_1X_Val; // Gain Factor Selection
+ ADC->REFCTRL.bit.REFSEL = ADC_REFCTRL_REFSEL_INT1V_Val; // 1.0V voltage reference
+ break;
+
+ case AR_INTERNAL1V65:
+ ADC->INPUTCTRL.bit.GAIN = ADC_INPUTCTRL_GAIN_1X_Val; // Gain Factor Selection
+ ADC->REFCTRL.bit.REFSEL = ADC_REFCTRL_REFSEL_INTVCC1_Val; // 1/2 VDDANA = 0.5* 3V3 = 1.65V
+ break;
+
+ case AR_DEFAULT:
+ default:
+ ADC->INPUTCTRL.bit.GAIN = ADC_INPUTCTRL_GAIN_DIV2_Val;
+ ADC->REFCTRL.bit.REFSEL = ADC_REFCTRL_REFSEL_INTVCC1_Val; // 1/2 VDDANA = 0.5* 3V3 = 1.65V
+ break;
+ }
+}
+
+uint32_t analogRead(uint32_t pin)
+{
+ uint32_t valueRead = 0;
+
+ if (pin < A0) {
+ pin += A0;
+ }
+
+ pinPeripheral(pin, PIO_ANALOG);
+
+ // Disable DAC, if analogWrite() was used previously to enable the DAC
+ if ((g_APinDescription[pin].ulADCChannelNumber == ADC_Channel0) || (g_APinDescription[pin].ulADCChannelNumber == DAC_Channel0)) {
+ syncDAC();
+ DAC->CTRLA.bit.ENABLE = 0x00; // Disable DAC
+ //DAC->CTRLB.bit.EOEN = 0x00; // The DAC output is turned off.
+ syncDAC();
+ }
+
+ syncADC();
+ ADC->INPUTCTRL.bit.MUXPOS = g_APinDescription[pin].ulADCChannelNumber; // Selection for the positive ADC input
+
+ // Control A
+ /*
+ * Bit 1 ENABLE: Enable
+ * 0: The ADC is disabled.
+ * 1: The ADC is enabled.
+ * Due to synchronization, there is a delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The
+ * value written to CTRL.ENABLE will read back immediately and the Synchronization Busy bit in the Status register
+ * (STATUS.SYNCBUSY) will be set. STATUS.SYNCBUSY will be cleared when the operation is complete.
+ *
+ * Before enabling the ADC, the asynchronous clock source must be selected and enabled, and the ADC reference must be
+ * configured. The first conversion after the reference is changed must not be used.
+ */
+ syncADC();
+ ADC->CTRLA.bit.ENABLE = 0x01; // Enable ADC
+
+ // Start conversion
+ syncADC();
+ ADC->SWTRIG.bit.START = 1;
+
+ // Waiting for the 1st conversion to complete
+ while (ADC->INTFLAG.bit.RESRDY == 0);
+
+ // Clear the Data Ready flag
+ ADC->INTFLAG.reg = ADC_INTFLAG_RESRDY;
+
+ // Start conversion again, since The first conversion after the reference is changed must not be used.
+ syncADC();
+ ADC->SWTRIG.bit.START = 1;
+
+ // Store the value
+ while (ADC->INTFLAG.bit.RESRDY == 0); // Waiting for conversion to complete
+ valueRead = ADC->RESULT.reg;
+
+ syncADC();
+ ADC->CTRLA.bit.ENABLE = 0x00; // Disable ADC
+ syncADC();
+
+ return mapResolution(valueRead, _ADCResolution, _readResolution);
+}
+
+
+// Right now, PWM output only works on the pins with
+// hardware support. These are defined in the appropriate
+// pins_*.c file. For the rest of the pins, we default
+// to digital output.
+void analogWrite(uint32_t pin, uint32_t value)
+{
+ PinDescription pinDesc = g_APinDescription[pin];
+ uint32_t attr = pinDesc.ulPinAttribute;
+
+ if ((attr & PIN_ATTR_ANALOG) == PIN_ATTR_ANALOG)
+ {
+ // DAC handling code
+
+ if ((pinDesc.ulADCChannelNumber != ADC_Channel0) && (pinDesc.ulADCChannelNumber != DAC_Channel0)) { // Only 1 DAC on AIN0 / PA02
+ return;
+ }
+
+ value = mapResolution(value, _writeResolution, 10);
+
+ syncDAC();
+ DAC->DATA.reg = value & 0x3FF; // DAC on 10 bits.
+ syncDAC();
+ DAC->CTRLA.bit.ENABLE = 0x01; // Enable DAC
+ syncDAC();
+ return;
+ }
+
+ if ((attr & PIN_ATTR_PWM) == PIN_ATTR_PWM)
+ {
+ value = mapResolution(value, _writeResolution, 16);
+
+ uint32_t tcNum = GetTCNumber(pinDesc.ulPWMChannel);
+ uint8_t tcChannel = GetTCChannelNumber(pinDesc.ulPWMChannel);
+ static bool tcEnabled[TCC_INST_NUM+TC_INST_NUM];
+
+ if (attr & PIN_ATTR_TIMER) {
+ #if !(ARDUINO_SAMD_VARIANT_COMPLIANCE >= 10603)
+ // Compatibility for cores based on SAMD core <=1.6.2
+ if (pinDesc.ulPinType == PIO_TIMER_ALT) {
+ pinPeripheral(pin, PIO_TIMER_ALT);
+ } else
+ #endif
+ {
+ pinPeripheral(pin, PIO_TIMER);
+ }
+ } else {
+ // We suppose that attr has PIN_ATTR_TIMER_ALT bit set...
+ pinPeripheral(pin, PIO_TIMER_ALT);
+ }
+
+ if (!tcEnabled[tcNum]) {
+ tcEnabled[tcNum] = true;
+
+ uint16_t GCLK_CLKCTRL_IDs[] = {
+ GCLK_CLKCTRL_ID(GCM_TCC0_TCC1), // TCC0
+ GCLK_CLKCTRL_ID(GCM_TCC0_TCC1), // TCC1
+ GCLK_CLKCTRL_ID(GCM_TCC2_TC3), // TCC2
+ GCLK_CLKCTRL_ID(GCM_TCC2_TC3), // TC3
+ GCLK_CLKCTRL_ID(GCM_TC4_TC5), // TC4
+ GCLK_CLKCTRL_ID(GCM_TC4_TC5), // TC5
+ GCLK_CLKCTRL_ID(GCM_TC6_TC7), // TC6
+ GCLK_CLKCTRL_ID(GCM_TC6_TC7), // TC7
+ };
+ GCLK->CLKCTRL.reg = (uint16_t) (GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN_GCLK0 | GCLK_CLKCTRL_IDs[tcNum]);
+ while (GCLK->STATUS.bit.SYNCBUSY == 1);
+
+ // Set PORT
+ if (tcNum >= TCC_INST_NUM) {
+ // -- Configure TC
+ Tc* TCx = (Tc*) GetTC(pinDesc.ulPWMChannel);
+ // Disable TCx
+ TCx->COUNT16.CTRLA.bit.ENABLE = 0;
+ syncTC_16(TCx);
+ // Set Timer counter Mode to 16 bits, normal PWM
+ TCx->COUNT16.CTRLA.reg |= TC_CTRLA_MODE_COUNT16 | TC_CTRLA_WAVEGEN_NPWM;
+ syncTC_16(TCx);
+ // Set the initial value
+ TCx->COUNT16.CC[tcChannel].reg = (uint32_t) value;
+ syncTC_16(TCx);
+ // Enable TCx
+ TCx->COUNT16.CTRLA.bit.ENABLE = 1;
+ syncTC_16(TCx);
+ } else {
+ // -- Configure TCC
+ Tcc* TCCx = (Tcc*) GetTC(pinDesc.ulPWMChannel);
+ // Disable TCCx
+ TCCx->CTRLA.bit.ENABLE = 0;
+ syncTCC(TCCx);
+ // Set TCCx as normal PWM
+ TCCx->WAVE.reg |= TCC_WAVE_WAVEGEN_NPWM;
+ syncTCC(TCCx);
+ // Set the initial value
+ TCCx->CC[tcChannel].reg = (uint32_t) value;
+ syncTCC(TCCx);
+ // Set PER to maximum counter value (resolution : 0xFFFF)
+ TCCx->PER.reg = 0xFFFF;
+ syncTCC(TCCx);
+ // Enable TCCx
+ TCCx->CTRLA.bit.ENABLE = 1;
+ syncTCC(TCCx);
+ }
+ } else {
+ if (tcNum >= TCC_INST_NUM) {
+ Tc* TCx = (Tc*) GetTC(pinDesc.ulPWMChannel);
+ TCx->COUNT16.CC[tcChannel].reg = (uint32_t) value;
+ syncTC_16(TCx);
+ } else {
+ Tcc* TCCx = (Tcc*) GetTC(pinDesc.ulPWMChannel);
+ TCCx->CTRLBSET.bit.LUPD = 1;
+ syncTCC(TCCx);
+ TCCx->CCB[tcChannel].reg = (uint32_t) value;
+ syncTCC(TCCx);
+ TCCx->CTRLBCLR.bit.LUPD = 1;
+ syncTCC(TCCx);
+ }
+ }
+ return;
+ }
+
+ // -- Defaults to digital write
+ pinMode(pin, OUTPUT);
+ value = mapResolution(value, _writeResolution, 8);
+ if (value < 128) {
+ digitalWrite(pin, LOW);
+ } else {
+ digitalWrite(pin, HIGH);
+ }
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/UsbReceive/UsbReceive/ArduinoCore/src/core/wiring_digital.c b/UsbReceive/UsbReceive/ArduinoCore/src/core/wiring_digital.c
new file mode 100644
index 0000000000000000000000000000000000000000..026af80dfecca72d68054aa80ea2579437927ace
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/src/core/wiring_digital.c
@@ -0,0 +1,124 @@
+/*
+ Copyright (c) 2015 Arduino LLC. All right reserved.
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ See the GNU Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#include "Arduino.h"
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+void pinMode( uint32_t ulPin, uint32_t ulMode )
+{
+ // Handle the case the pin isn't usable as PIO
+ if ( g_APinDescription[ulPin].ulPinType == PIO_NOT_A_PIN )
+ {
+ return ;
+ }
+
+ // Set pin mode according to chapter '22.6.3 I/O Pin Configuration'
+ switch ( ulMode )
+ {
+ case INPUT:
+ // Set pin to input mode
+ PORT->Group[g_APinDescription[ulPin].ulPort].PINCFG[g_APinDescription[ulPin].ulPin].reg=(uint8_t)(PORT_PINCFG_INEN) ;
+ PORT->Group[g_APinDescription[ulPin].ulPort].DIRCLR.reg = (uint32_t)(1<<g_APinDescription[ulPin].ulPin) ;
+ break ;
+
+ case INPUT_PULLUP:
+ // Set pin to input mode with pull-up resistor enabled
+ PORT->Group[g_APinDescription[ulPin].ulPort].PINCFG[g_APinDescription[ulPin].ulPin].reg=(uint8_t)(PORT_PINCFG_INEN|PORT_PINCFG_PULLEN) ;
+ PORT->Group[g_APinDescription[ulPin].ulPort].DIRCLR.reg = (uint32_t)(1<<g_APinDescription[ulPin].ulPin) ;
+
+ // Enable pull level (cf '22.6.3.2 Input Configuration' and '22.8.7 Data Output Value Set')
+ PORT->Group[g_APinDescription[ulPin].ulPort].OUTSET.reg = (uint32_t)(1<<g_APinDescription[ulPin].ulPin) ;
+ break ;
+
+ case INPUT_PULLDOWN:
+ // Set pin to input mode with pull-down resistor enabled
+ PORT->Group[g_APinDescription[ulPin].ulPort].PINCFG[g_APinDescription[ulPin].ulPin].reg=(uint8_t)(PORT_PINCFG_INEN|PORT_PINCFG_PULLEN) ;
+ PORT->Group[g_APinDescription[ulPin].ulPort].DIRCLR.reg = (uint32_t)(1<<g_APinDescription[ulPin].ulPin) ;
+
+ // Enable pull level (cf '22.6.3.2 Input Configuration' and '22.8.6 Data Output Value Clear')
+ PORT->Group[g_APinDescription[ulPin].ulPort].OUTCLR.reg = (uint32_t)(1<<g_APinDescription[ulPin].ulPin) ;
+ break ;
+
+ case OUTPUT:
+ // enable input, to support reading back values, with pullups disabled
+ PORT->Group[g_APinDescription[ulPin].ulPort].PINCFG[g_APinDescription[ulPin].ulPin].reg=(uint8_t)(PORT_PINCFG_INEN) ;
+
+ // Set pin to output mode
+ PORT->Group[g_APinDescription[ulPin].ulPort].DIRSET.reg = (uint32_t)(1<<g_APinDescription[ulPin].ulPin) ;
+ break ;
+
+ default:
+ // do nothing
+ break ;
+ }
+}
+
+void digitalWrite( uint32_t ulPin, uint32_t ulVal )
+{
+ // Handle the case the pin isn't usable as PIO
+ if ( g_APinDescription[ulPin].ulPinType == PIO_NOT_A_PIN )
+ {
+ return ;
+ }
+
+ EPortType port = g_APinDescription[ulPin].ulPort;
+ uint32_t pin = g_APinDescription[ulPin].ulPin;
+ uint32_t pinMask = (1ul << pin);
+
+ if ( (PORT->Group[port].DIRSET.reg & pinMask) == 0 ) {
+ // the pin is not an output, disable pull-up if val is LOW, otherwise enable pull-up
+ PORT->Group[port].PINCFG[pin].bit.PULLEN = ((ulVal == LOW) ? 0 : 1) ;
+ }
+
+ switch ( ulVal )
+ {
+ case LOW:
+ PORT->Group[port].OUTCLR.reg = pinMask;
+ break ;
+
+ default:
+ PORT->Group[port].OUTSET.reg = pinMask;
+ break ;
+ }
+
+ return ;
+}
+
+int digitalRead( uint32_t ulPin )
+{
+ // Handle the case the pin isn't usable as PIO
+ if ( g_APinDescription[ulPin].ulPinType == PIO_NOT_A_PIN )
+ {
+ return LOW ;
+ }
+
+ if ( (PORT->Group[g_APinDescription[ulPin].ulPort].IN.reg & (1ul << g_APinDescription[ulPin].ulPin)) != 0 )
+ {
+ return HIGH ;
+ }
+
+ return LOW ;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
diff --git a/UsbReceive/UsbReceive/ArduinoCore/src/core/wiring_private.c b/UsbReceive/UsbReceive/ArduinoCore/src/core/wiring_private.c
new file mode 100644
index 0000000000000000000000000000000000000000..a5aaba42c67df29c618ad7947643af8f706cf2e3
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/src/core/wiring_private.c
@@ -0,0 +1,118 @@
+/*
+ Copyright (c) 2015 Arduino LLC. All right reserved.
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ See the GNU Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#include "Arduino.h"
+#include "wiring_private.h"
+
+int pinPeripheral( uint32_t ulPin, EPioType ulPeripheral )
+{
+ // Handle the case the pin isn't usable as PIO
+ if ( g_APinDescription[ulPin].ulPinType == PIO_NOT_A_PIN )
+ {
+ return -1 ;
+ }
+
+ switch ( ulPeripheral )
+ {
+ case PIO_DIGITAL:
+ case PIO_INPUT:
+ case PIO_INPUT_PULLUP:
+ case PIO_OUTPUT:
+ // Disable peripheral muxing, done in pinMode
+// PORT->Group[g_APinDescription[ulPin].ulPort].PINCFG[g_APinDescription[ulPin].ulPin].bit.PMUXEN = 0 ;
+
+ // Configure pin mode, if requested
+ if ( ulPeripheral == PIO_INPUT )
+ {
+ pinMode( ulPin, INPUT ) ;
+ }
+ else
+ {
+ if ( ulPeripheral == PIO_INPUT_PULLUP )
+ {
+ pinMode( ulPin, INPUT_PULLUP ) ;
+ }
+ else
+ {
+ if ( ulPeripheral == PIO_OUTPUT )
+ {
+ pinMode( ulPin, OUTPUT ) ;
+ }
+ else
+ {
+ // PIO_DIGITAL, do we have to do something as all cases are covered?
+ }
+ }
+ }
+ break ;
+
+ case PIO_ANALOG:
+ case PIO_SERCOM:
+ case PIO_SERCOM_ALT:
+ case PIO_TIMER:
+ case PIO_TIMER_ALT:
+ case PIO_EXTINT:
+ case PIO_COM:
+ case PIO_AC_CLK:
+#if 0
+ // Is the pio pin in the lower 16 ones?
+ // The WRCONFIG register allows update of only 16 pin max out of 32
+ if ( g_APinDescription[ulPin].ulPin < 16 )
+ {
+ PORT->Group[g_APinDescription[ulPin].ulPort].WRCONFIG.reg = PORT_WRCONFIG_WRPMUX | PORT_WRCONFIG_PMUXEN | PORT_WRCONFIG_PMUX( ulPeripheral ) |
+ PORT_WRCONFIG_WRPINCFG |
+ PORT_WRCONFIG_PINMASK( g_APinDescription[ulPin].ulPin ) ;
+ }
+ else
+ {
+ PORT->Group[g_APinDescription[ulPin].ulPort].WRCONFIG.reg = PORT_WRCONFIG_HWSEL |
+ PORT_WRCONFIG_WRPMUX | PORT_WRCONFIG_PMUXEN | PORT_WRCONFIG_PMUX( ulPeripheral ) |
+ PORT_WRCONFIG_WRPINCFG |
+ PORT_WRCONFIG_PINMASK( g_APinDescription[ulPin].ulPin - 16 ) ;
+ }
+#else
+ if ( g_APinDescription[ulPin].ulPin & 1 ) // is pin odd?
+ {
+ uint32_t temp ;
+
+ // Get whole current setup for both odd and even pins and remove odd one
+ temp = (PORT->Group[g_APinDescription[ulPin].ulPort].PMUX[g_APinDescription[ulPin].ulPin >> 1].reg) & PORT_PMUX_PMUXE( 0xF ) ;
+ // Set new muxing
+ PORT->Group[g_APinDescription[ulPin].ulPort].PMUX[g_APinDescription[ulPin].ulPin >> 1].reg = temp|PORT_PMUX_PMUXO( ulPeripheral ) ;
+ // Enable port mux
+ PORT->Group[g_APinDescription[ulPin].ulPort].PINCFG[g_APinDescription[ulPin].ulPin].reg |= PORT_PINCFG_PMUXEN ;
+ }
+ else // even pin
+ {
+ uint32_t temp ;
+
+ temp = (PORT->Group[g_APinDescription[ulPin].ulPort].PMUX[g_APinDescription[ulPin].ulPin >> 1].reg) & PORT_PMUX_PMUXO( 0xF ) ;
+ PORT->Group[g_APinDescription[ulPin].ulPort].PMUX[g_APinDescription[ulPin].ulPin >> 1].reg = temp|PORT_PMUX_PMUXE( ulPeripheral ) ;
+ PORT->Group[g_APinDescription[ulPin].ulPort].PINCFG[g_APinDescription[ulPin].ulPin].reg |= PORT_PINCFG_PMUXEN ; // Enable port mux
+ }
+#endif
+ break ;
+
+ case PIO_NOT_A_PIN:
+ return -1l ;
+ break ;
+ }
+
+ return 0l ;
+}
+
diff --git a/UsbReceive/UsbReceive/ArduinoCore/src/core/wiring_shift.c b/UsbReceive/UsbReceive/ArduinoCore/src/core/wiring_shift.c
new file mode 100644
index 0000000000000000000000000000000000000000..3260d2b12b7cef626e78769d620a293d9f8afdca
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/src/core/wiring_shift.c
@@ -0,0 +1,74 @@
+/*
+ Copyright (c) 2014 Arduino. All right reserved.
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ See the GNU Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#include <stdint.h>
+#include "wiring_shift.h"
+#include "wiring_digital.h"
+#include "wiring_private.h"
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+uint32_t shiftIn( uint32_t ulDataPin, uint32_t ulClockPin, uint32_t ulBitOrder )
+{
+ uint8_t value = 0 ;
+ uint8_t i ;
+
+ for ( i=0 ; i < 8 ; ++i )
+ {
+ digitalWrite( ulClockPin, HIGH ) ;
+
+ if ( ulBitOrder == LSBFIRST )
+ {
+ value |= digitalRead( ulDataPin ) << i ;
+ }
+ else
+ {
+ value |= digitalRead( ulDataPin ) << (7 - i) ;
+ }
+
+ digitalWrite( ulClockPin, LOW ) ;
+ }
+
+ return value ;
+}
+
+void shiftOut( uint32_t ulDataPin, uint32_t ulClockPin, uint32_t ulBitOrder, uint32_t ulVal )
+{
+ uint8_t i ;
+
+ for ( i=0 ; i < 8 ; i++ )
+ {
+ if ( ulBitOrder == LSBFIRST )
+ {
+ digitalWrite( ulDataPin, !!(ulVal & (1 << i)) ) ;
+ }
+ else
+ {
+ digitalWrite( ulDataPin, !!(ulVal & (1 << (7 - i))) ) ;
+ }
+
+ digitalWrite( ulClockPin, HIGH ) ;
+ digitalWrite( ulClockPin, LOW ) ;
+ }
+}
+
+#ifdef __cplusplus
+} // extern "C"
+#endif
diff --git a/UsbReceive/UsbReceive/ArduinoCore/src/libraries/wire/Wire.cpp b/UsbReceive/UsbReceive/ArduinoCore/src/libraries/wire/Wire.cpp
new file mode 100644
index 0000000000000000000000000000000000000000..714c997ebc720687a19cde26d2b2d5a5d1a557cc
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/src/libraries/wire/Wire.cpp
@@ -0,0 +1,378 @@
+/*
+ * TWI/I2C library for Arduino Zero
+ * Copyright (c) 2015 Arduino LLC. All rights reserved.
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+extern "C" {
+#include <string.h>
+}
+
+#include <Arduino.h>
+#include <wiring_private.h>
+
+#include "Wire.h"
+
+TwoWire::TwoWire(SERCOM * s, uint8_t pinSDA, uint8_t pinSCL)
+{
+ this->sercom = s;
+ this->_uc_pinSDA=pinSDA;
+ this->_uc_pinSCL=pinSCL;
+ transmissionBegun = false;
+}
+
+#if defined(_VARIANT_WIRELINGZERO_)
+void TwoWire::changeInterface(uint8_t wireInterface){
+ sercom->disableWIRE();
+ transmissionBegun=false;
+ if(wireInterface==0){
+ this->sercom = &PERIPH_WIRE;
+ this->_uc_pinSDA=PIN_WIRE_SDA;
+ this->_uc_pinSCL=PIN_WIRE_SCL;
+ }else if(wireInterface==1){
+ this->sercom = &PERIPH_WIRE1;
+ this->_uc_pinSDA=PIN_WIRE1_SDA;
+ this->_uc_pinSCL=PIN_WIRE1_SCL;
+ }else if(wireInterface==2){
+ this->sercom = &PERIPH_WIRE2;
+ this->_uc_pinSDA=PIN_WIRE2_SDA;
+ this->_uc_pinSCL=PIN_WIRE2_SCL;
+ }else if(wireInterface==3){
+ this->sercom = &PERIPH_WIRE3;
+ this->_uc_pinSDA=PIN_WIRE3_SDA;
+ this->_uc_pinSCL=PIN_WIRE3_SCL;
+ }
+ sercom->initMasterWIRE(TWI_CLOCK);
+ sercom->enableWIRE();
+ pinPeripheral(_uc_pinSDA, g_APinDescription[_uc_pinSDA].ulPinType);
+ pinPeripheral(_uc_pinSCL, g_APinDescription[_uc_pinSCL].ulPinType);
+}
+#endif
+
+void TwoWire::begin(void) {
+ //Master Mode
+ sercom->initMasterWIRE(TWI_CLOCK);
+ sercom->enableWIRE();
+
+ pinPeripheral(_uc_pinSDA, g_APinDescription[_uc_pinSDA].ulPinType);
+ pinPeripheral(_uc_pinSCL, g_APinDescription[_uc_pinSCL].ulPinType);
+}
+
+void TwoWire::begin(uint8_t address, bool enableGeneralCall) {
+ //Slave mode
+ sercom->initSlaveWIRE(address, enableGeneralCall);
+ sercom->enableWIRE();
+
+ pinPeripheral(_uc_pinSDA, g_APinDescription[_uc_pinSDA].ulPinType);
+ pinPeripheral(_uc_pinSCL, g_APinDescription[_uc_pinSCL].ulPinType);
+}
+
+void TwoWire::setClock(uint32_t baudrate) {
+ sercom->disableWIRE();
+ sercom->initMasterWIRE(baudrate);
+ sercom->enableWIRE();
+}
+
+void TwoWire::end() {
+ sercom->disableWIRE();
+}
+
+uint8_t TwoWire::requestFrom(uint8_t address, size_t quantity, bool stopBit)
+{
+ if(quantity == 0)
+ {
+ return 0;
+ }
+
+ size_t byteRead = 0;
+
+ rxBuffer.clear();
+
+ if(sercom->startTransmissionWIRE(address, WIRE_READ_FLAG))
+ {
+ // Read first data
+ rxBuffer.store_char(sercom->readDataWIRE());
+
+ bool busOwner;
+ // Connected to slave
+ for (byteRead = 1; byteRead < quantity && (busOwner = sercom->isBusOwnerWIRE()); ++byteRead)
+ {
+ sercom->prepareAckBitWIRE(); // Prepare Acknowledge
+ sercom->prepareCommandBitsWire(WIRE_MASTER_ACT_READ); // Prepare the ACK command for the slave
+ rxBuffer.store_char(sercom->readDataWIRE()); // Read data and send the ACK
+ }
+ sercom->prepareNackBitWIRE(); // Prepare NACK to stop slave transmission
+ //sercom->readDataWIRE(); // Clear data register to send NACK
+
+ if (stopBit && busOwner)
+ {
+ sercom->prepareCommandBitsWire(WIRE_MASTER_ACT_STOP); // Send Stop unless arbitration was lost
+ }
+
+ if (!busOwner)
+ {
+ byteRead--; // because last read byte was garbage/invalid
+ }
+ }
+
+ return byteRead;
+}
+
+uint8_t TwoWire::requestFrom(uint8_t address, size_t quantity)
+{
+ return requestFrom(address, quantity, true);
+}
+
+void TwoWire::beginTransmission(uint8_t address) {
+ // save address of target and clear buffer
+ txAddress = address;
+ txBuffer.clear();
+
+ transmissionBegun = true;
+}
+
+// Errors:
+// 0 : Success
+// 1 : Data too long
+// 2 : NACK on transmit of address
+// 3 : NACK on transmit of data
+// 4 : Other error
+uint8_t TwoWire::endTransmission(bool stopBit)
+{
+ transmissionBegun = false ;
+
+ // Start I2C transmission
+ if ( !sercom->startTransmissionWIRE( txAddress, WIRE_WRITE_FLAG ) )
+ {
+ sercom->prepareCommandBitsWire(WIRE_MASTER_ACT_STOP);
+ return 2 ; // Address error
+ }
+
+ // Send all buffer
+ while( txBuffer.available() )
+ {
+ // Trying to send data
+ if ( !sercom->sendDataMasterWIRE( txBuffer.read_char() ) )
+ {
+ sercom->prepareCommandBitsWire(WIRE_MASTER_ACT_STOP);
+ return 3 ; // Nack or error
+ }
+ }
+
+ if (stopBit)
+ {
+ sercom->prepareCommandBitsWire(WIRE_MASTER_ACT_STOP);
+ }
+
+ return 0;
+}
+
+uint8_t TwoWire::endTransmission()
+{
+ return endTransmission(true);
+}
+
+size_t TwoWire::write(uint8_t ucData)
+{
+ // No writing, without begun transmission or a full buffer
+ if ( !transmissionBegun || txBuffer.isFull() )
+ {
+ return 0 ;
+ }
+
+ txBuffer.store_char( ucData ) ;
+
+ return 1 ;
+}
+
+size_t TwoWire::write(const uint8_t *data, size_t quantity)
+{
+ //Try to store all data
+ for(size_t i = 0; i < quantity; ++i)
+ {
+ //Return the number of data stored, when the buffer is full (if write return 0)
+ if(!write(data[i]))
+ return i;
+ }
+
+ //All data stored
+ return quantity;
+}
+
+int TwoWire::available(void)
+{
+ return rxBuffer.available();
+}
+
+int TwoWire::read(void)
+{
+ return rxBuffer.read_char();
+}
+
+int TwoWire::peek(void)
+{
+ return rxBuffer.peek();
+}
+
+void TwoWire::flush(void)
+{
+ // Do nothing, use endTransmission(..) to force
+ // data transfer.
+}
+
+void TwoWire::onReceive(void(*function)(int))
+{
+ onReceiveCallback = function;
+}
+
+void TwoWire::onRequest(void(*function)(void))
+{
+ onRequestCallback = function;
+}
+
+void TwoWire::onService(void)
+{
+ if ( sercom->isSlaveWIRE() )
+ {
+ if(sercom->isStopDetectedWIRE() ||
+ (sercom->isAddressMatch() && sercom->isRestartDetectedWIRE() && !sercom->isMasterReadOperationWIRE())) //Stop or Restart detected
+ {
+ sercom->prepareAckBitWIRE();
+ sercom->prepareCommandBitsWire(0x03);
+
+ //Calling onReceiveCallback, if exists
+ if(onReceiveCallback)
+ {
+ onReceiveCallback(available());
+ }
+
+ rxBuffer.clear();
+ }
+ else if(sercom->isAddressMatch()) //Address Match
+ {
+ sercom->prepareAckBitWIRE();
+ sercom->prepareCommandBitsWire(0x03);
+
+ if(sercom->isMasterReadOperationWIRE()) //Is a request ?
+ {
+ txBuffer.clear();
+
+ transmissionBegun = true;
+
+ //Calling onRequestCallback, if exists
+ if(onRequestCallback)
+ {
+ onRequestCallback();
+ }
+ }
+ }
+ else if(sercom->isDataReadyWIRE())
+ {
+ if (sercom->isMasterReadOperationWIRE())
+ {
+ uint8_t c = 0xff;
+
+ if( txBuffer.available() ) {
+ c = txBuffer.read_char();
+ }
+
+ transmissionBegun = sercom->sendDataSlaveWIRE(c);
+ } else { //Received data
+ if (rxBuffer.isFull()) {
+ sercom->prepareNackBitWIRE();
+ } else {
+ //Store data
+ rxBuffer.store_char(sercom->readDataWIRE());
+
+ sercom->prepareAckBitWIRE();
+ }
+
+ sercom->prepareCommandBitsWire(0x03);
+ }
+ }
+ }
+}
+
+#if WIRE_INTERFACES_COUNT > 0
+ /* In case new variant doesn't define these macros,
+ * we put here the ones for Arduino Zero.
+ *
+ * These values should be different on some variants!
+ */
+ #ifndef PERIPH_WIRE
+ #define PERIPH_WIRE sercom3
+ #define WIRE_IT_HANDLER SERCOM3_Handler
+ #endif // PERIPH_WIRE
+ TwoWire Wire(&PERIPH_WIRE, PIN_WIRE_SDA, PIN_WIRE_SCL);
+
+ void WIRE_IT_HANDLER(void) {
+ Wire.onService();
+ }
+ #if defined(_VARIANT_WIRELINGZERO_)
+ void WIRE1_IT_HANDLER(void) {
+ Wire.onService();
+ }
+ void WIRE2_IT_HANDLER(void) {
+ Wire.onService();
+ }
+ void WIRE3_IT_HANDLER(void) {
+ Wire.onService();
+ }
+ #endif
+#endif
+
+#if !defined(_VARIANT_WIRELINGZERO_)
+ #if WIRE_INTERFACES_COUNT > 1
+ TwoWire Wire1(&PERIPH_WIRE1, PIN_WIRE1_SDA, PIN_WIRE1_SCL);
+
+ void WIRE1_IT_HANDLER(void) {
+ Wire1.onService();
+ }
+ #endif
+
+ #if WIRE_INTERFACES_COUNT > 2
+ TwoWire Wire2(&PERIPH_WIRE2, PIN_WIRE2_SDA, PIN_WIRE2_SCL);
+
+ void WIRE2_IT_HANDLER(void) {
+ Wire2.onService();
+ }
+ #endif
+
+ #if WIRE_INTERFACES_COUNT > 3
+ TwoWire Wire3(&PERIPH_WIRE3, PIN_WIRE3_SDA, PIN_WIRE3_SCL);
+
+ void WIRE3_IT_HANDLER(void) {
+ Wire3.onService();
+ }
+ #endif
+
+ #if WIRE_INTERFACES_COUNT > 4
+ TwoWire Wire4(&PERIPH_WIRE4, PIN_WIRE4_SDA, PIN_WIRE4_SCL);
+
+ void WIRE4_IT_HANDLER(void) {
+ Wire4.onService();
+ }
+ #endif
+
+ #if WIRE_INTERFACES_COUNT > 5
+ TwoWire Wire5(&PERIPH_WIRE5, PIN_WIRE5_SDA, PIN_WIRE5_SCL);
+
+ void WIRE5_IT_HANDLER(void) {
+ Wire5.onService();
+ }
+ #endif
+#endif
+
diff --git a/UsbReceive/UsbReceive/ArduinoCore/src/variants/openocd_scripts/arduino_zero.cfg b/UsbReceive/UsbReceive/ArduinoCore/src/variants/openocd_scripts/arduino_zero.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..36c65c32db1dbb6ecbdc0415209a86f913020b0f
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/src/variants/openocd_scripts/arduino_zero.cfg
@@ -0,0 +1,30 @@
+#
+# Arduino Zero OpenOCD script.
+#
+# Copyright (c) 2014-2015 Arduino LLC. All right reserved.
+#
+# This library is free software; you can redistribute it and/or
+# modify it under the terms of the GNU Lesser General Public
+# License as published by the Free Software Foundation; either
+# version 2.1 of the License, or (at your option) any later version.
+#
+# This library is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+# See the GNU Lesser General Public License for more details.
+#
+# You should have received a copy of the GNU Lesser General Public
+# License along with this library; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+#
+
+source [find interface/cmsis-dap.cfg]
+
+# chip name
+set CHIPNAME at91samd21g18
+set ENDIAN little
+
+# choose a port here
+set telnet_port 0
+
+source [find target/at91samdXX.cfg]
diff --git a/UsbReceive/UsbReceive/ArduinoCore/src/variants/variant.cpp b/UsbReceive/UsbReceive/ArduinoCore/src/variants/variant.cpp
new file mode 100644
index 0000000000000000000000000000000000000000..57150183c8baa97648abd54392f5b2ac930f24b9
--- /dev/null
+++ b/UsbReceive/UsbReceive/ArduinoCore/src/variants/variant.cpp
@@ -0,0 +1,220 @@
+/*
+ Copyright (c) 2014-2015 Arduino LLC. All right reserved.
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ See the GNU Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+/*
+ * +------------+------------------+--------+-----------------+--------------------------------------------------------------------------------------------------------
+ * + Pin number + TS+ Board pin | PIN | Label/Name | Comments (* is for default peripheral in use)
+ * +------------+------------------+--------+-----------------+--------------------------------------------------------------------------------------------------------
+ * | | Digital Low | | |
+ * +------------+------------------+--------+-----------------+--------------------------------------------------------------------------------------------------------
+ * | 0 | 0 -> RX | PA11 | | EIC/EXTINT[11] ADC/AIN[19] PTC/X[3] *SERCOM0/PAD[3] SERCOM2/PAD[3] TCC0/WO[3] TCC1/WO[1]
+ * | 1 | 1 <- TX | PA10 | | EIC/EXTINT[10] ADC/AIN[18] PTC/X[2] *SERCOM0/PAD[2] TCC0/WO[2] TCC1/WO[0]
+ * | 2 | 2 | PA14 | | EIC/EXTINT[14] SERCOM2/PAD[2] SERCOM4/PAD[2] TC3/WO[0] TCC0/WO[4]
+ * | 3 | ~3 | PA09 | | EIC/EXTINT[9] ADC/AIN[17] PTC/X[1] SERCOM0/PAD[1] SERCOM2/PAD[1] *TCC0/WO[1] TCC1/WO[3]
+ * | 4 | ~4 | PA08 | | EIC/NMI ADC/AIN[16] PTC/X[0] SERCOM0/PAD[0] SERCOM2/PAD[0] *TCC0/WO[0] TCC1/WO[2]
+ * | 5 | ~5 | PA15 | | EIC/EXTINT[15] SERCOM2/PAD[3] SERCOM4/PAD[3] *TC3/WO[1] TCC0/WO[5]
+ * | 6 | ~6 | PA20 | | EIC/EXTINT[4] PTC/X[8] SERCOM5/PAD[2] SERCOM3/PAD[2] *TCC0/WO[6]
+ * | 7 | 7 | PA21 | | EIC/EXTINT[5] PTC/X[9] SERCOM5/PAD[3] SERCOM3/PAD[3] TCC0/WO[7]
+ * +------------+------------------+--------+-----------------+--------------------------------------------------------------------------------------------------------
+ * | | Digital High | | |
+ * +------------+------------------+--------+-----------------+--------------------------------------------------------------------------------------------------------
+ * | 8 | ~8 | PA06 | | EIC/EXTINT[6] ADC/AIN[6] AC/AIN[2] PTC/Y[4] SERCOM0/PAD[2] *TCC1/WO[0]
+ * | 9 | ~9 | PA07 | | EIC/EXTINT[7] ADC/AIN[7] AC/AIN[3] PTC/Y[5] SERCOM0/PAD[3] *TCC1/WO[1]
+ * | 10 | ~10 | PA18 | SS | EIC/EXTINT[2] PTC/X[6] +SERCOM1/PAD[2] SERCOM3/PAD[2] *TC3/WO[0] TCC0/WO[2]
+ * | 11 | ~11 | PA16 | MISO | EIC/EXTINT[0] PTC/X[4] +SERCOM1/PAD[0] SERCOM3/PAD[0] *TCC2/WO[0] TCC0/WO[6]
+ * | 12 | ~12 | PA19 | MOSI | EIC/EXTINT[3] PTC/X[7] +SERCOM1/PAD[3] SERCOM3/PAD[3] TC3/WO[1] *TCC0/WO[3]
+ * | 13 | ~13 | PA17 | SCK, LED | EIC/EXTINT[1] PTC/X[5] +SERCOM1/PAD[1] SERCOM3/PAD[1] *TCC2/WO[1] TCC0/WO[7]
+ * +------------+------------------+--------+-----------------+--------------------------------------------------------------------------------------------------------
+ * | | Analog Connector | | |
+ * +------------+------------------+--------+-----------------+--------------------------------------------------------------------------------------------------------
+ * | 14 | A0 | PA02 | A0 | EIC/EXTINT[2] *ADC/AIN[0] DAC/VOUT PTC/Y[0]
+ * | 15 | A1 | PB08 | A1 | EIC/EXTINT[8] *ADC/AIN[2] PTC/Y[14] SERCOM4/PAD[0] TC4/WO[0]
+ * | 16 | A2 | PB09 | A2 | EIC/EXTINT[9] *ADC/AIN[3] PTC/Y[15] SERCOM4/PAD[1] TC4/WO[1]
+ * | 17 | A3 | PA04 | A3 | EIC/EXTINT[4] *ADC/AIN[4] AC/AIN[0] PTC/Y[2] SERCOM0/PAD[0] TCC0/WO[0]
+ * | 18 | | PA05 | A4 | EIC/EXTINT[5] *ADC/AIN[5] AC/AIN[1] PTC/Y[5] SERCOM0/PAD[1] TCC0/WO[1]
+ * | 19 | | PB02 | A5 | EIC/EXTINT[2] *ADC/AIN[10] PTC/Y[8] SERCOM5/PAD[0]
+ * +------------+------------------+--------+-----------------+--------------------------------------------------------------------------------------------------------
+ * | | Wire | | |
+ * +------------+------------------+--------+-----------------+--------------------------------------------------------------------------------------------------------
+ * | 20 | A4 | PA22 | SDA | EIC/EXTINT[6] PTC/X[10] *SERCOM3/PAD[0] SERCOM5/PAD[0] TC4/WO[0] TCC0/WO[4]
+ * | 21 | A5 | PA23 | SCL | EIC/EXTINT[7] PTC/X[11] *SERCOM3/PAD[1] SERCOM5/PAD[1] TC4/WO[1] TCC0/WO[5]
+ * +------------+------------------+--------+-----------------+--------------------------------------------------------------------------------------------------------
+ * | | Extra Interfaces | | |
+ * +------------+------------------+--------+-----------------+--------------------------------------------------------------------------------------------------------
+ * | 22 | 1 | PA12 | MISO | EIC/EXTINT[12] SERCOM2/PAD[0] *SERCOM4/PAD[0] TCC2/WO[0] TCC0/WO[6]
+ * | 23 | 4 | PB10 | MOSI | EIC/EXTINT[10] *SERCOM4/PAD[2] TC5/WO[0] TCC0/WO[4]
+ * | 24 | 3 | PB11 | SCK | EIC/EXTINT[11] *SERCOM4/PAD[3] TC5/WO[1] TCC0/WO[5]
+ * +------------+------------------+--------+-----------------+--------------------------------------------------------------------------------------------------------
+ * | 25 | | PB03 | |
+ * | 26 | | PA27 | |
+ * +------------+------------------+--------+-----------------+--------------------------------------------------------------------------------------------------------
+ * | | USB | | |
+ * +------------+------------------+--------+-----------------+--------------------------------------------------------------------------------------------------------
+ * | 27 | | PA28 | USB_HOST_ENABLE | EIC/EXTINT[8]
+ * | 28 | | PA24 | USB_NEGATIVE | *USB/DM
+ * | 29 | | PA25 | USB_POSITIVE | *USB/DP
+ * +------------+------------------+--------+-----------------+--------------------------------------------------------------------------------------------------------
+ * | | Extra Interfaces | | |
+ * +------------+------------------+--------+-----------------+--------------------------------------------------------------------------------------------------------
+ * | 30 | | PB22 | EDBG_UART TX | *SERCOM5/PAD[2]
+ * | 31 | | PB23 | EDBG_UART RX | *SERCOM5/PAD[3]
+ * +------------+------------------+--------+-----------------+--------------------------------------------------------------------------------------------------------
+ * | 32 | | PA22 | EDBG_SDA | Pin 20 (SDA)
+ * | 33 | | PA23 | EDBG_SCL | Pin 21 (SCL)
+ * +------------+------------------+--------+-----------------+--------------------------------------------------------------------------------------------------------
+ * | 34 | | PA19 | EDBG_MISO | EIC/EXTINT[3] *SERCOM1/PAD[3] SERCOM3/PAD[3] TC3/WO[1] TCC0/WO[3]
+ * | 35 | | PA16 | EDBG_MOSI | EIC/EXTINT[0] *SERCOM1/PAD[0] SERCOM3/PAD[0] TCC2/WO[0] TCC0/WO[6]
+ * | 36 | | PA18 | EDBG_SS | EIC/EXTINT[2] *SERCOM1/PAD[2] SERCOM3/PAD[2] TC3/WO[0] TCC0/WO[2]
+ * | 37 | | PA17 | EDBG_SCK | EIC/EXTINT[1] *SERCOM1/PAD[1] SERCOM3/PAD[1] TCC2/WO[1] TCC0/WO[7]
+ * +------------+------------------+--------+-----------------+--------------------------------------------------------------------------------------------------------
+ * | 38 | ATN | PA13 | EDBG_GPIO0 | EIC/EXTINT[13] SERCOM2/PAD[1] SERCOM4/PAD[1] *TCC2/WO[1] TCC0/WO[7]
+ * | 39 | | PA21 | EDBG_GPIO1 | Pin 7
+ * | 40 | | PA06 | EDBG_GPIO2 | Pin 8
+ * | 41 | | PA07 | EDBG_GPIO3 | Pin 9
+ * +------------+------------------+--------+-----------------+--------------------------------------------------------------------------------------------------------
+ * | | | | |
+ * +------------+------------------+--------+-----------------+--------------------------------------------------------------------------------------------------------
+ * | | GND | | |
+ * | 42 | AREF | PA03 | | EIC/EXTINT[3] *[ADC|DAC]/VREFA ADC/AIN[1] PTC/Y[1]
+ * +------------+------------------+--------+-----------------+--------------------------------------------------------------------------------------------------------
+ * | |32.768KHz Crystal | | |
+ * +------------+------------------+--------+-----------------+--------------------------------------------------------------------------------------------------------
+ * | | | PA00 | XIN32 | EIC/EXTINT[0] SERCOM1/PAD[0] TCC2/WO[0]
+ * | | | PA01 | XOUT32 | EIC/EXTINT[1] SERCOM1/PAD[1] TCC2/WO[1]
+ * +------------+------------------+--------+-----------------+--------------------------------------------------------------------------------------------------------
+ */
+
+
+#include "variant.h"
+
+/*
+ * Pins descriptions
+ */
+const PinDescription g_APinDescription[]=
+{
+ // 0..13 - Digital pins
+ // ----------------------
+ // 0/1 - SERCOM/UART (Serial)
+ { PORTA, 11, PIO_SERCOM, (PIN_ATTR_DIGITAL), No_ADC_Channel, NOT_ON_PWM, NOT_ON_TIMER, EXTERNAL_INT_11 }, // RX: SERCOM0/PAD[3]
+ { PORTA, 10, PIO_SERCOM, (PIN_ATTR_DIGITAL), No_ADC_Channel, NOT_ON_PWM, NOT_ON_TIMER, EXTERNAL_INT_10 }, // TX: SERCOM0/PAD[2]
+
+ // 2..12
+ // Digital Low
+ { PORTA, 14, PIO_DIGITAL, (PIN_ATTR_DIGITAL), No_ADC_Channel, NOT_ON_PWM, NOT_ON_TIMER, EXTERNAL_INT_14 },
+ { PORTA, 9, PIO_TIMER, (PIN_ATTR_DIGITAL|PIN_ATTR_PWM|PIN_ATTR_TIMER), No_ADC_Channel, PWM0_CH1, TCC0_CH1, EXTERNAL_INT_9 }, // TCC0/WO[1]
+ { PORTA, 8, PIO_TIMER, (PIN_ATTR_DIGITAL|PIN_ATTR_PWM|PIN_ATTR_TIMER), No_ADC_Channel, PWM0_CH0, TCC0_CH0, EXTERNAL_INT_NMI }, // TCC0/WO[0]
+ { PORTA, 15, PIO_TIMER, (PIN_ATTR_DIGITAL|PIN_ATTR_PWM|PIN_ATTR_TIMER), No_ADC_Channel, PWM3_CH1, TC3_CH1, EXTERNAL_INT_15 }, // TC3/WO[1]
+ { PORTA, 20, PIO_TIMER_ALT, (PIN_ATTR_DIGITAL|PIN_ATTR_PWM|PIN_ATTR_TIMER), No_ADC_Channel, PWM0_CH6, TCC0_CH6, EXTERNAL_INT_4 }, // TCC0/WO[6]
+ { PORTA, 21, PIO_DIGITAL, (PIN_ATTR_DIGITAL), No_ADC_Channel, NOT_ON_PWM, NOT_ON_TIMER, EXTERNAL_INT_5 },
+
+ // Digital High
+ { PORTA, 6, PIO_TIMER, (PIN_ATTR_DIGITAL|PIN_ATTR_PWM|PIN_ATTR_TIMER), No_ADC_Channel, PWM1_CH0, TCC1_CH0, EXTERNAL_INT_6 }, // TCC1/WO[0]
+ { PORTA, 7, PIO_TIMER, (PIN_ATTR_DIGITAL|PIN_ATTR_PWM|PIN_ATTR_TIMER), No_ADC_Channel, PWM1_CH1, TCC1_CH1, EXTERNAL_INT_7 }, // TCC1/WO[1]
+ { PORTA, 18, PIO_TIMER, (PIN_ATTR_DIGITAL|PIN_ATTR_PWM|PIN_ATTR_TIMER), No_ADC_Channel, PWM3_CH0, TC3_CH0, EXTERNAL_INT_2 }, // TC3/WO[0]
+ { PORTA, 16, PIO_SERCOM, (PIN_ATTR_DIGITAL|PIN_ATTR_PWM|PIN_ATTR_TIMER), No_ADC_Channel, PWM2_CH0, TCC2_CH0, EXTERNAL_INT_0 }, // TCC2/WO[0]
+ { PORTA, 19, PIO_SERCOM, (PIN_ATTR_DIGITAL|PIN_ATTR_PWM|PIN_ATTR_TIMER), No_ADC_Channel, PWM0_CH3, TCC0_CH3, EXTERNAL_INT_3 }, // TCC0/WO[3]
+ { PORTA, 17, PIO_SERCOM, (PIN_ATTR_DIGITAL|PIN_ATTR_PWM), No_ADC_Channel, PWM2_CH1, NOT_ON_TIMER, EXTERNAL_INT_1 }, // TCC2/WO[1]
+
+ // 14..19 - Analog pins
+ // --------------------
+ { PORTA, 2, PIO_ANALOG, PIN_ATTR_ANALOG, ADC_Channel0, NOT_ON_PWM, NOT_ON_TIMER, EXTERNAL_INT_2 }, // ADC/AIN[0]
+ { PORTB, 8, PIO_ANALOG, PIN_ATTR_ANALOG, ADC_Channel2, NOT_ON_PWM, NOT_ON_TIMER, EXTERNAL_INT_8 }, // ADC/AIN[2]
+ { PORTB, 9, PIO_ANALOG, PIN_ATTR_ANALOG, ADC_Channel3, NOT_ON_PWM, NOT_ON_TIMER, EXTERNAL_INT_9 }, // ADC/AIN[3]
+ { PORTA, 4, PIO_ANALOG, PIN_ATTR_ANALOG, ADC_Channel4, NOT_ON_PWM, NOT_ON_TIMER, EXTERNAL_INT_4 }, // ADC/AIN[4]
+ { PORTA, 5, PIO_ANALOG, PIN_ATTR_ANALOG, ADC_Channel5, NOT_ON_PWM, NOT_ON_TIMER, EXTERNAL_INT_5 }, // ADC/AIN[5]
+ { PORTB, 2, PIO_ANALOG, PIN_ATTR_ANALOG, ADC_Channel10, NOT_ON_PWM, NOT_ON_TIMER, EXTERNAL_INT_2 }, // ADC/AIN[10]
+
+ // 20..21 I2C pins (SDA/SCL)
+ // ----------------------
+ { PORTA, 22, PIO_SERCOM, PIN_ATTR_DIGITAL, No_ADC_Channel, NOT_ON_PWM, NOT_ON_TIMER, EXTERNAL_INT_6 }, // SDA: SERCOM3/PAD[0]
+ { PORTA, 23, PIO_SERCOM, PIN_ATTR_DIGITAL, No_ADC_Channel, NOT_ON_PWM, NOT_ON_TIMER, EXTERNAL_INT_7 }, // SCL: SERCOM3/PAD[1]
+
+ // 22..24 - SPI pins (ICSP:MISO,SCK,MOSI)
+ // ----------------------
+ { PORTA, 12, PIO_SERCOM_ALT, PIN_ATTR_DIGITAL, No_ADC_Channel, NOT_ON_PWM, NOT_ON_TIMER, EXTERNAL_INT_12 }, // MISO: SERCOM4/PAD[0]
+ { PORTB, 10, PIO_SERCOM_ALT, PIN_ATTR_DIGITAL, No_ADC_Channel, NOT_ON_PWM, NOT_ON_TIMER, EXTERNAL_INT_10 }, // MOSI: SERCOM4/PAD[2]
+ { PORTB, 11, PIO_SERCOM_ALT, PIN_ATTR_DIGITAL, No_ADC_Channel, NOT_ON_PWM, NOT_ON_TIMER, EXTERNAL_INT_11 }, // SCK: SERCOM4/PAD[3]
+
+ // 25..26 - RX/TX LEDS (PB03/PA27)
+ // --------------------
+ { PORTB, 3, PIO_DIGITAL, PIN_ATTR_DIGITAL, ADC_Channel11, NOT_ON_PWM, NOT_ON_TIMER, EXTERNAL_INT_3 }, // general IO pin
+ { PORTA, 27, PIO_DIGITAL, PIN_ATTR_DIGITAL, No_ADC_Channel, NOT_ON_PWM, NOT_ON_TIMER, EXTERNAL_INT_15 }, // general IO pin
+
+ // 27..29 - USB
+ // --------------------
+ { PORTA, 28, PIO_COM, PIN_ATTR_NONE, No_ADC_Channel, NOT_ON_PWM, NOT_ON_TIMER, EXTERNAL_INT_NONE }, // USB Host enable
+ { PORTA, 24, PIO_COM, PIN_ATTR_NONE, No_ADC_Channel, NOT_ON_PWM, NOT_ON_TIMER, EXTERNAL_INT_NONE }, // USB/DM
+ { PORTA, 25, PIO_COM, PIN_ATTR_NONE, No_ADC_Channel, NOT_ON_PWM, NOT_ON_TIMER, EXTERNAL_INT_NONE }, // USB/DP
+
+ // 30..41 - EDBG
+ // ----------------------
+ // 30/31 - EDBG/UART
+ { PORTB, 22, PIO_SERCOM_ALT, PIN_ATTR_NONE, No_ADC_Channel, NOT_ON_PWM, NOT_ON_TIMER, EXTERNAL_INT_6 }, // TX: SERCOM5/PAD[2]
+ { PORTB, 23, PIO_SERCOM_ALT, PIN_ATTR_NONE, No_ADC_Channel, NOT_ON_PWM, NOT_ON_TIMER, EXTERNAL_INT_7 }, // RX: SERCOM5/PAD[3]
+
+ // 32/33 I2C (SDA/SCL and also EDBG:SDA/SCL)
+ { PORTA, 22, PIO_SERCOM, PIN_ATTR_NONE, No_ADC_Channel, NOT_ON_PWM, NOT_ON_TIMER, EXTERNAL_INT_NONE }, // SDA: SERCOM3/PAD[0]
+ { PORTA, 23, PIO_SERCOM, PIN_ATTR_NONE, No_ADC_Channel, NOT_ON_PWM, NOT_ON_TIMER, EXTERNAL_INT_NONE }, // SCL: SERCOM3/PAD[1]
+
+ // 34..37 - EDBG/SPI
+ { PORTA, 19, PIO_SERCOM, PIN_ATTR_NONE, No_ADC_Channel, NOT_ON_PWM, NOT_ON_TIMER, EXTERNAL_INT_NONE }, // MISO: SERCOM1/PAD[3]
+ { PORTA, 16, PIO_SERCOM, PIN_ATTR_NONE, No_ADC_Channel, NOT_ON_PWM, NOT_ON_TIMER, EXTERNAL_INT_NONE }, // MOSI: SERCOM1/PAD[0]
+ { PORTA, 18, PIO_SERCOM, PIN_ATTR_NONE, No_ADC_Channel, NOT_ON_PWM, NOT_ON_TIMER, EXTERNAL_INT_NONE }, // SS: SERCOM1/PAD[2]
+ { PORTA, 17, PIO_SERCOM, PIN_ATTR_NONE, No_ADC_Channel, NOT_ON_PWM, NOT_ON_TIMER, EXTERNAL_INT_NONE }, // SCK: SERCOM1/PAD[1]
+
+ // 38..41 - EDBG/Digital
+ { PORTA, 13, PIO_SERCOM, (PIN_ATTR_DIGITAL|PIN_ATTR_PWM), No_ADC_Channel, PWM0_CH5, NOT_ON_TIMER, EXTERNAL_INT_13 }, // EIC/EXTINT[13] *TCC2/WO[1] TCC0/WO[7]
+ { PORTA, 21, PIO_PWM_ALT, (PIN_ATTR_DIGITAL|PIN_ATTR_PWM), No_ADC_Channel, PWM0_CH7, NOT_ON_TIMER, EXTERNAL_INT_NONE }, // Pin 7
+ { PORTA, 6, PIO_PWM, (PIN_ATTR_DIGITAL|PIN_ATTR_PWM), No_ADC_Channel, PWM1_CH0, NOT_ON_TIMER, EXTERNAL_INT_NONE }, // Pin 8
+ { PORTA, 7, PIO_PWM, (PIN_ATTR_DIGITAL|PIN_ATTR_PWM), No_ADC_Channel, PWM1_CH1, NOT_ON_TIMER, EXTERNAL_INT_NONE }, // Pin 9
+
+ // 42 (AREF)
+ { PORTA, 3, PIO_ANALOG, PIN_ATTR_ANALOG, ADC_Channel1, NOT_ON_PWM, NOT_ON_TIMER, EXTERNAL_INT_NONE }, // DAC/VREFP
+
+ // ----------------------
+ // 43 - Alternate use of A0 (DAC output)
+ { PORTA, 2, PIO_ANALOG, PIN_ATTR_ANALOG, DAC_Channel0, NOT_ON_PWM, NOT_ON_TIMER, EXTERNAL_INT_2 }, // DAC/VOUT
+
+ // ----------------------
+ // 44..45 - SWCLK/SWDIO
+ { PORTA, 30, PIO_DIGITAL, PIN_ATTR_DIGITAL, No_ADC_Channel, NOT_ON_PWM, NOT_ON_TIMER, EXTERNAL_INT_NONE }, // SW
+ { PORTA, 31, PIO_DIGITAL, PIN_ATTR_DIGITAL, No_ADC_Channel, NOT_ON_PWM, NOT_ON_TIMER, EXTERNAL_INT_NONE }, // DAC/VOUT
+
+} ;
+
+const void* g_apTCInstances[TCC_INST_NUM+TC_INST_NUM]={ TCC0, TCC1, TCC2, TC3, TC4, TC5 } ;
+
+// Multi-serial objects instantiation
+SERCOM sercom0( SERCOM0 ) ;
+SERCOM sercom1( SERCOM1 ) ;
+SERCOM sercom2( SERCOM2 ) ;
+SERCOM sercom3( SERCOM3 ) ;
+SERCOM sercom4( SERCOM4 ) ;
+SERCOM sercom5( SERCOM5 ) ;
+
+Uart Serial( &sercom0, PIN_SERIAL_RX, PIN_SERIAL_TX, PAD_SERIAL_RX, PAD_SERIAL_TX ) ;
+Uart Serial1( &sercom5, PIN_SERIAL1_RX, PIN_SERIAL1_TX, PAD_SERIAL1_RX, PAD_SERIAL1_TX ) ;
+
+void SERCOM0_Handler()
+{
+ Serial.IrqHandler();
+}
+
+void SERCOM5_Handler()
+{
+ Serial1.IrqHandler();
+}
\ No newline at end of file
diff --git a/UsbReceive/UsbReceive/UsbReceive/Debug/Makefile b/UsbReceive/UsbReceive/UsbReceive/Debug/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..24f501d04832e96c18d4be468515798292d47f04
--- /dev/null
+++ b/UsbReceive/UsbReceive/UsbReceive/Debug/Makefile
@@ -0,0 +1,135 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+SHELL := cmd.exe
+RM := rm -rf
+
+USER_OBJS :=
+
+LIBS :=
+PROJ :=
+
+O_SRCS :=
+C_SRCS :=
+S_SRCS :=
+S_UPPER_SRCS :=
+OBJ_SRCS :=
+ASM_SRCS :=
+PREPROCESSING_SRCS :=
+OBJS :=
+OBJS_AS_ARGS :=
+C_DEPS :=
+C_DEPS_AS_ARGS :=
+EXECUTABLES :=
+OUTPUT_FILE_PATH :=
+OUTPUT_FILE_PATH_AS_ARGS :=
+AVR_APP_PATH :=$$$AVR_APP_PATH$$$
+QUOTE := "
+ADDITIONAL_DEPENDENCIES:=
+OUTPUT_FILE_DEP:=
+LIB_DEP:=
+LINKER_SCRIPT_DEP:=
+
+# Every subdirectory with source files must be described here
+SUBDIRS := \
+../linker_scripts/ \
+../linker_scripts/linker_scripts/ \
+../linker_scripts/linker_scripts/gcc/
+
+
+# Add inputs and outputs from these tool invocations to the build variables
+C_SRCS += \
+../Sketch.cpp
+
+
+PREPROCESSING_SRCS +=
+
+
+ASM_SRCS +=
+
+
+OBJS += \
+Sketch.o
+
+OBJS_AS_ARGS += \
+Sketch.o
+
+C_DEPS += \
+Sketch.d
+
+C_DEPS_AS_ARGS += \
+Sketch.d
+
+OUTPUT_FILE_PATH +=UsbReceive.elf
+
+OUTPUT_FILE_PATH_AS_ARGS +=UsbReceive.elf
+
+ADDITIONAL_DEPENDENCIES:=
+
+OUTPUT_FILE_DEP:= ./makedep.mk
+
+LIB_DEP+= \
+C:/GIT/serial-communication-arduino/UsbReceive/UsbReceive/ArduinoCore/Debug/libArduinoCore.a
+
+LINKER_SCRIPT_DEP+= \
+../linker_scripts/linker_scripts/gcc/flash_without_bootloader.ld \
+../linker_scripts/linker_scripts/gcc/flash_with_bootloader.ld \
+../linker_scripts/linker_scripts/gcc/link_for_menu.ld
+
+
+# AVR32/GNU C Compiler
+./Sketch.o: .././Sketch.cpp
+ @echo Building file: $<
+ @echo Invoking: ARM/GNU C Compiler : 6.3.1
+ $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-g++.exe$(QUOTE) -mthumb -D__SAMD21G18A__ -DDEBUG -DF_CPU=48000000L -DARDUINO=108019 -DARDUINO_SAMD_ZERO -DARDUINO_ARCH_SAMD -DUSB_VID=0x03EB -DUSB_PID=0x8009 -DUSB_PRODUCT="\"TinyZero\"" -DUSB_MANUFACTURER="\"TinyCircuits\"" -DUSBCON -DSAMD_SERIES -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"..\\..\ArduinoCore\include\core" -I"..\\..\ArduinoCore\include\variants" -I"..\\..\ArduinoCore\include\core\avr" -I"..\\..\ArduinoCore\include\core\USB" -I"..\\..\ArduinoCore\include\libraries\wire" -Os -fno-threadsafe-statics -fno-exceptions -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -g3 -w -mcpu=cortex-m0plus -c -std=gnu++11 --param max-inline-insns-single=500 -nostdlib -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
+ @echo Finished building: $<
+
+
+
+
+
+# AVR32/GNU Preprocessing Assembler
+
+
+
+# AVR32/GNU Assembler
+
+
+
+
+ifneq ($(MAKECMDGOALS),clean)
+ifneq ($(strip $(C_DEPS)),)
+-include $(C_DEPS)
+endif
+endif
+
+# Add inputs and outputs from these tool invocations to the build variables
+
+# All Target
+all: $(OUTPUT_FILE_PATH) $(ADDITIONAL_DEPENDENCIES)
+
+$(OUTPUT_FILE_PATH): $(OBJS) $(USER_OBJS) $(OUTPUT_FILE_DEP) $(LIB_DEP) $(LINKER_SCRIPT_DEP)
+ @echo Building target: $@
+ @echo Invoking: ARM/GNU Linker : 6.3.1
+ $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-g++.exe$(QUOTE) -o$(OUTPUT_FILE_PATH_AS_ARGS) $(OBJS_AS_ARGS) $(USER_OBJS) $(LIBS) -mthumb -Wl,-Map="UsbReceive.map" --specs=nano.specs --specs=nosys.specs -Wl,--start-group -lm -lArduinoCore -Wl,--end-group -L"..\linker_scripts\linker_scripts\gcc" -L"C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug" -Wl,--gc-sections -mcpu=cortex-m0plus -Tflash_without_bootloader.ld -Wl,--cref -Os -Wl,--check-sections -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align
+ @echo Finished building target: $@
+ "C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-objcopy.exe" -O binary "UsbReceive.elf" "UsbReceive.bin"
+ "C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-objcopy.exe" -O ihex -R .eeprom -R .fuse -R .lock -R .signature "UsbReceive.elf" "UsbReceive.hex"
+ "C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-objcopy.exe" -j .eeprom --set-section-flags=.eeprom=alloc,load --change-section-lma .eeprom=0 --no-change-warnings -O binary "UsbReceive.elf" "UsbReceive.eep" || exit 0
+ "C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-objdump.exe" -h -S "UsbReceive.elf" > "UsbReceive.lss"
+ "C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-objcopy.exe" -O srec -R .eeprom -R .fuse -R .lock -R .signature "UsbReceive.elf" "UsbReceive.srec"
+ "C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-size.exe" "UsbReceive.elf"
+
+
+
+
+
+
+
+# Other Targets
+clean:
+ -$(RM) $(OBJS_AS_ARGS) $(EXECUTABLES)
+ -$(RM) $(C_DEPS_AS_ARGS)
+ rm -rf "UsbReceive.elf" "UsbReceive.a" "UsbReceive.hex" "UsbReceive.bin" "UsbReceive.lss" "UsbReceive.eep" "UsbReceive.map" "UsbReceive.srec"
+
\ No newline at end of file
diff --git a/UsbReceive/UsbReceive/UsbReceive/Debug/Sketch.d b/UsbReceive/UsbReceive/UsbReceive/Debug/Sketch.d
new file mode 100644
index 0000000000000000000000000000000000000000..4b9b715fa629316df8bcc133ad4df8269e0eb6b9
--- /dev/null
+++ b/UsbReceive/UsbReceive/UsbReceive/Debug/Sketch.d
@@ -0,0 +1,469 @@
+Sketch.d Sketch.o: .././Sketch.cpp \
+ ..\\..\ArduinoCore\include\core/Arduino.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cstdlib \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\c++config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\os_defines.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\cpu_defines.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\string.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\xlocale.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\string.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\math.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cmath \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\bits\cpp_type_traits.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\ext\type_traits.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\math.h \
+ ..\\..\ArduinoCore\include\core/avr/pgmspace.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\inttypes.h \
+ ..\\..\ArduinoCore\include\core/avr/interrupt.h \
+ ..\\..\ArduinoCore\include\core/avr/io.h \
+ ..\\..\ArduinoCore\include\core/binary.h \
+ ..\\..\ArduinoCore\include\core/itoa.h \
+ ..\\..\ArduinoCore\include\core/sam.h \
+ ..\\..\ArduinoCore\include\core/samd.h \
+ ..\\..\ArduinoCore\include\core/samd21/include/samd21.h \
+ ..\\..\ArduinoCore\include\core/samd21/include/samd21g18a.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h \
+ C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h \
+ ..\\..\ArduinoCore\include\core/samd21/include/system_samd21.h \
+ ..\\..\ArduinoCore\include\core/samd21/include/component/ac.h \
+ ..\\..\ArduinoCore\include\core/samd21/include/component/adc.h \
+ ..\\..\ArduinoCore\include\core/samd21/include/component/dac.h \
+ ..\\..\ArduinoCore\include\core/samd21/include/component/dmac.h \
+ ..\\..\ArduinoCore\include\core/samd21/include/component/dsu.h \
+ ..\\..\ArduinoCore\include\core/samd21/include/component/eic.h \
+ ..\\..\ArduinoCore\include\core/samd21/include/component/evsys.h \
+ ..\\..\ArduinoCore\include\core/samd21/include/component/gclk.h \
+ ..\\..\ArduinoCore\include\core/samd21/include/component/hmatrixb.h \
+ ..\\..\ArduinoCore\include\core/samd21/include/component/i2s.h \
+ ..\\..\ArduinoCore\include\core/samd21/include/component/mtb.h \
+ ..\\..\ArduinoCore\include\core/samd21/include/component/nvmctrl.h \
+ ..\\..\ArduinoCore\include\core/samd21/include/component/pac.h \
+ ..\\..\ArduinoCore\include\core/samd21/include/component/pm.h \
+ ..\\..\ArduinoCore\include\core/samd21/include/component/port.h \
+ ..\\..\ArduinoCore\include\core/samd21/include/component/rtc.h \
+ ..\\..\ArduinoCore\include\core/samd21/include/component/sercom.h \
+ ..\\..\ArduinoCore\include\core/samd21/include/component/sysctrl.h \
+ ..\\..\ArduinoCore\include\core/samd21/include/component/tc.h \
+ ..\\..\ArduinoCore\include\core/samd21/include/component/tcc.h \
+ ..\\..\ArduinoCore\include\core/samd21/include/component/usb.h \
+ ..\\..\ArduinoCore\include\core/samd21/include/component/wdt.h \
+ ..\\..\ArduinoCore\include\core/samd21/include/instance/ac.h \
+ ..\\..\ArduinoCore\include\core/samd21/include/instance/adc.h \
+ ..\\..\ArduinoCore\include\core/samd21/include/instance/dac.h \
+ ..\\..\ArduinoCore\include\core/samd21/include/instance/dmac.h \
+ ..\\..\ArduinoCore\include\core/samd21/include/instance/dsu.h \
+ ..\\..\ArduinoCore\include\core/samd21/include/instance/eic.h \
+ ..\\..\ArduinoCore\include\core/samd21/include/instance/evsys.h \
+ ..\\..\ArduinoCore\include\core/samd21/include/instance/gclk.h \
+ ..\\..\ArduinoCore\include\core/samd21/include/instance/sbmatrix.h \
+ ..\\..\ArduinoCore\include\core/samd21/include/instance/i2s.h \
+ ..\\..\ArduinoCore\include\core/samd21/include/instance/mtb.h \
+ ..\\..\ArduinoCore\include\core/samd21/include/instance/nvmctrl.h \
+ ..\\..\ArduinoCore\include\core/samd21/include/instance/pac0.h \
+ ..\\..\ArduinoCore\include\core/samd21/include/instance/pac1.h \
+ ..\\..\ArduinoCore\include\core/samd21/include/instance/pac2.h \
+ ..\\..\ArduinoCore\include\core/samd21/include/instance/pm.h \
+ ..\\..\ArduinoCore\include\core/samd21/include/instance/port.h \
+ ..\\..\ArduinoCore\include\core/samd21/include/instance/rtc.h \
+ ..\\..\ArduinoCore\include\core/samd21/include/instance/sercom0.h \
+ ..\\..\ArduinoCore\include\core/samd21/include/instance/sercom1.h \
+ ..\\..\ArduinoCore\include\core/samd21/include/instance/sercom2.h \
+ ..\\..\ArduinoCore\include\core/samd21/include/instance/sercom3.h \
+ ..\\..\ArduinoCore\include\core/samd21/include/instance/sercom4.h \
+ ..\\..\ArduinoCore\include\core/samd21/include/instance/sercom5.h \
+ ..\\..\ArduinoCore\include\core/samd21/include/instance/sysctrl.h \
+ ..\\..\ArduinoCore\include\core/samd21/include/instance/tc3.h \
+ ..\\..\ArduinoCore\include\core/samd21/include/instance/tc4.h \
+ ..\\..\ArduinoCore\include\core/samd21/include/instance/tc5.h \
+ ..\\..\ArduinoCore\include\core/samd21/include/instance/tcc0.h \
+ ..\\..\ArduinoCore\include\core/samd21/include/instance/tcc1.h \
+ ..\\..\ArduinoCore\include\core/samd21/include/instance/tcc2.h \
+ ..\\..\ArduinoCore\include\core/samd21/include/instance/usb.h \
+ ..\\..\ArduinoCore\include\core/samd21/include/instance/wdt.h \
+ ..\\..\ArduinoCore\include\core/samd21/include/pio/samd21g18a.h \
+ ..\\..\ArduinoCore\include\core/wiring_constants.h \
+ ..\\..\ArduinoCore\include\core/WVariant.h \
+ ..\\..\ArduinoCore\include\core/WCharacter.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\ctype.h \
+ ..\\..\ArduinoCore\include\core/WString.h \
+ ..\\..\ArduinoCore\include\core/avr/pgmspace.h \
+ ..\\..\ArduinoCore\include\core/Tone.h \
+ ..\\..\ArduinoCore\include\core/Arduino.h \
+ ..\\..\ArduinoCore\include\core/WMath.h \
+ ..\\..\ArduinoCore\include\core/HardwareSerial.h \
+ ..\\..\ArduinoCore\include\core/Stream.h \
+ ..\\..\ArduinoCore\include\core/Print.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h \
+ ..\\..\ArduinoCore\include\core/Printable.h \
+ ..\\..\ArduinoCore\include\core/pulse.h \
+ ..\\..\ArduinoCore\include\core/delay.h \
+ ..\\..\ArduinoCore\include\variants/variant.h \
+ ..\\..\ArduinoCore\include\core/SERCOM.h \
+ ..\\..\ArduinoCore\include\core/Uart.h \
+ ..\\..\ArduinoCore\include\core/SERCOM.h \
+ ..\\..\ArduinoCore\include\core/RingBuffer.h \
+ c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cstddef \
+ ..\\..\ArduinoCore\include\core/wiring.h \
+ ..\\..\ArduinoCore\include\core/wiring_digital.h \
+ ..\\..\ArduinoCore\include\core/wiring_analog.h \
+ ..\\..\ArduinoCore\include\core/wiring_shift.h \
+ ..\\..\ArduinoCore\include\core/WInterrupts.h \
+ ..\\..\ArduinoCore\include\core/USB/USBDesc.h \
+ ..\\..\ArduinoCore\include\core/USB/USBCore.h \
+ ..\\..\ArduinoCore\include\core/USB/USBAPI.h \
+ ..\\..\ArduinoCore\include\core/Stream.h \
+ ..\\..\ArduinoCore\include\core/RingBuffer.h \
+ ..\\..\ArduinoCore\include\core/USB/USB_host.h \
+ ..\\..\ArduinoCore\include\core/USB/samd21_host.h \
+ ..\\..\ArduinoCore\include\core/USB/CDC.h \
+ ..\\..\ArduinoCore\include\core/USB/USBDesc.h \
+ ..\\..\ArduinoCore\include\core/USB/PluggableUSB.h
+
+..\\..\ArduinoCore\include\core/Arduino.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdbool.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_default_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\features.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_newlib_version.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_intsup.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_stdint.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cstdlib:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\c++config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\os_defines.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\arm-none-eabi\thumb\v6-m\bits\cpu_defines.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\ieeefp.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\newlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\config.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stddef.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\reent.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\_ansi.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\lock.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\cdefs.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\stdlib.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\alloca.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\string.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\xlocale.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\string.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\math.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cmath:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\bits\cpp_type_traits.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\ext\type_traits.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\math.h:
+
+..\\..\ArduinoCore\include\core/avr/pgmspace.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\inttypes.h:
+
+..\\..\ArduinoCore\include\core/avr/interrupt.h:
+
+..\\..\ArduinoCore\include\core/avr/io.h:
+
+..\\..\ArduinoCore\include\core/binary.h:
+
+..\\..\ArduinoCore\include\core/itoa.h:
+
+..\\..\ArduinoCore\include\core/sam.h:
+
+..\\..\ArduinoCore\include\core/samd.h:
+
+..\\..\ArduinoCore\include\core/samd21/include/samd21.h:
+
+..\\..\ArduinoCore\include\core/samd21/include/samd21g18a.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/core_cm0plus.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_version.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_compiler.h:
+
+C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include/cmsis_gcc.h:
+
+..\\..\ArduinoCore\include\core/samd21/include/system_samd21.h:
+
+..\\..\ArduinoCore\include\core/samd21/include/component/ac.h:
+
+..\\..\ArduinoCore\include\core/samd21/include/component/adc.h:
+
+..\\..\ArduinoCore\include\core/samd21/include/component/dac.h:
+
+..\\..\ArduinoCore\include\core/samd21/include/component/dmac.h:
+
+..\\..\ArduinoCore\include\core/samd21/include/component/dsu.h:
+
+..\\..\ArduinoCore\include\core/samd21/include/component/eic.h:
+
+..\\..\ArduinoCore\include\core/samd21/include/component/evsys.h:
+
+..\\..\ArduinoCore\include\core/samd21/include/component/gclk.h:
+
+..\\..\ArduinoCore\include\core/samd21/include/component/hmatrixb.h:
+
+..\\..\ArduinoCore\include\core/samd21/include/component/i2s.h:
+
+..\\..\ArduinoCore\include\core/samd21/include/component/mtb.h:
+
+..\\..\ArduinoCore\include\core/samd21/include/component/nvmctrl.h:
+
+..\\..\ArduinoCore\include\core/samd21/include/component/pac.h:
+
+..\\..\ArduinoCore\include\core/samd21/include/component/pm.h:
+
+..\\..\ArduinoCore\include\core/samd21/include/component/port.h:
+
+..\\..\ArduinoCore\include\core/samd21/include/component/rtc.h:
+
+..\\..\ArduinoCore\include\core/samd21/include/component/sercom.h:
+
+..\\..\ArduinoCore\include\core/samd21/include/component/sysctrl.h:
+
+..\\..\ArduinoCore\include\core/samd21/include/component/tc.h:
+
+..\\..\ArduinoCore\include\core/samd21/include/component/tcc.h:
+
+..\\..\ArduinoCore\include\core/samd21/include/component/usb.h:
+
+..\\..\ArduinoCore\include\core/samd21/include/component/wdt.h:
+
+..\\..\ArduinoCore\include\core/samd21/include/instance/ac.h:
+
+..\\..\ArduinoCore\include\core/samd21/include/instance/adc.h:
+
+..\\..\ArduinoCore\include\core/samd21/include/instance/dac.h:
+
+..\\..\ArduinoCore\include\core/samd21/include/instance/dmac.h:
+
+..\\..\ArduinoCore\include\core/samd21/include/instance/dsu.h:
+
+..\\..\ArduinoCore\include\core/samd21/include/instance/eic.h:
+
+..\\..\ArduinoCore\include\core/samd21/include/instance/evsys.h:
+
+..\\..\ArduinoCore\include\core/samd21/include/instance/gclk.h:
+
+..\\..\ArduinoCore\include\core/samd21/include/instance/sbmatrix.h:
+
+..\\..\ArduinoCore\include\core/samd21/include/instance/i2s.h:
+
+..\\..\ArduinoCore\include\core/samd21/include/instance/mtb.h:
+
+..\\..\ArduinoCore\include\core/samd21/include/instance/nvmctrl.h:
+
+..\\..\ArduinoCore\include\core/samd21/include/instance/pac0.h:
+
+..\\..\ArduinoCore\include\core/samd21/include/instance/pac1.h:
+
+..\\..\ArduinoCore\include\core/samd21/include/instance/pac2.h:
+
+..\\..\ArduinoCore\include\core/samd21/include/instance/pm.h:
+
+..\\..\ArduinoCore\include\core/samd21/include/instance/port.h:
+
+..\\..\ArduinoCore\include\core/samd21/include/instance/rtc.h:
+
+..\\..\ArduinoCore\include\core/samd21/include/instance/sercom0.h:
+
+..\\..\ArduinoCore\include\core/samd21/include/instance/sercom1.h:
+
+..\\..\ArduinoCore\include\core/samd21/include/instance/sercom2.h:
+
+..\\..\ArduinoCore\include\core/samd21/include/instance/sercom3.h:
+
+..\\..\ArduinoCore\include\core/samd21/include/instance/sercom4.h:
+
+..\\..\ArduinoCore\include\core/samd21/include/instance/sercom5.h:
+
+..\\..\ArduinoCore\include\core/samd21/include/instance/sysctrl.h:
+
+..\\..\ArduinoCore\include\core/samd21/include/instance/tc3.h:
+
+..\\..\ArduinoCore\include\core/samd21/include/instance/tc4.h:
+
+..\\..\ArduinoCore\include\core/samd21/include/instance/tc5.h:
+
+..\\..\ArduinoCore\include\core/samd21/include/instance/tcc0.h:
+
+..\\..\ArduinoCore\include\core/samd21/include/instance/tcc1.h:
+
+..\\..\ArduinoCore\include\core/samd21/include/instance/tcc2.h:
+
+..\\..\ArduinoCore\include\core/samd21/include/instance/usb.h:
+
+..\\..\ArduinoCore\include\core/samd21/include/instance/wdt.h:
+
+..\\..\ArduinoCore\include\core/samd21/include/pio/samd21g18a.h:
+
+..\\..\ArduinoCore\include\core/wiring_constants.h:
+
+..\\..\ArduinoCore\include\core/WVariant.h:
+
+..\\..\ArduinoCore\include\core/WCharacter.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\ctype.h:
+
+..\\..\ArduinoCore\include\core/WString.h:
+
+..\\..\ArduinoCore\include\core/avr/pgmspace.h:
+
+..\\..\ArduinoCore\include\core/Tone.h:
+
+..\\..\ArduinoCore\include\core/Arduino.h:
+
+..\\..\ArduinoCore\include\core/WMath.h:
+
+..\\..\ArduinoCore\include\core/HardwareSerial.h:
+
+..\\..\ArduinoCore\include\core/Stream.h:
+
+..\\..\ArduinoCore\include\core/Print.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\stdio.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\lib\gcc\arm-none-eabi\6.3.1\include\stdarg.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\_endian.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\select.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_sigset.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timeval.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_timespec.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\_pthreadtypes.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\machine\types.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\sys\stdio.h:
+
+..\\..\ArduinoCore\include\core/Printable.h:
+
+..\\..\ArduinoCore\include\core/pulse.h:
+
+..\\..\ArduinoCore\include\core/delay.h:
+
+..\\..\ArduinoCore\include\variants/variant.h:
+
+..\\..\ArduinoCore\include\core/SERCOM.h:
+
+..\\..\ArduinoCore\include\core/Uart.h:
+
+..\\..\ArduinoCore\include\core/SERCOM.h:
+
+..\\..\ArduinoCore\include\core/RingBuffer.h:
+
+c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\arm\arm-gnu-toolchain\arm-none-eabi\include\c++\6.3.1\cstddef:
+
+..\\..\ArduinoCore\include\core/wiring.h:
+
+..\\..\ArduinoCore\include\core/wiring_digital.h:
+
+..\\..\ArduinoCore\include\core/wiring_analog.h:
+
+..\\..\ArduinoCore\include\core/wiring_shift.h:
+
+..\\..\ArduinoCore\include\core/WInterrupts.h:
+
+..\\..\ArduinoCore\include\core/USB/USBDesc.h:
+
+..\\..\ArduinoCore\include\core/USB/USBCore.h:
+
+..\\..\ArduinoCore\include\core/USB/USBAPI.h:
+
+..\\..\ArduinoCore\include\core/Stream.h:
+
+..\\..\ArduinoCore\include\core/RingBuffer.h:
+
+..\\..\ArduinoCore\include\core/USB/USB_host.h:
+
+..\\..\ArduinoCore\include\core/USB/samd21_host.h:
+
+..\\..\ArduinoCore\include\core/USB/CDC.h:
+
+..\\..\ArduinoCore\include\core/USB/USBDesc.h:
+
+..\\..\ArduinoCore\include\core/USB/PluggableUSB.h:
diff --git a/UsbReceive/UsbReceive/UsbReceive/Debug/Sketch.o b/UsbReceive/UsbReceive/UsbReceive/Debug/Sketch.o
new file mode 100644
index 0000000000000000000000000000000000000000..6dff371ea035f1de5bf9a3bd36f9aa7c104ac22f
Binary files /dev/null and b/UsbReceive/UsbReceive/UsbReceive/Debug/Sketch.o differ
diff --git a/UsbReceive/UsbReceive/UsbReceive/Debug/UsbReceive.bin b/UsbReceive/UsbReceive/UsbReceive/Debug/UsbReceive.bin
new file mode 100644
index 0000000000000000000000000000000000000000..7c31cec3309efe057f2bbbcbd2163d771c44f6cb
Binary files /dev/null and b/UsbReceive/UsbReceive/UsbReceive/Debug/UsbReceive.bin differ
diff --git a/UsbReceive/UsbReceive/UsbReceive/Debug/UsbReceive.eep b/UsbReceive/UsbReceive/UsbReceive/Debug/UsbReceive.eep
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/UsbReceive/UsbReceive/UsbReceive/Debug/UsbReceive.elf b/UsbReceive/UsbReceive/UsbReceive/Debug/UsbReceive.elf
new file mode 100644
index 0000000000000000000000000000000000000000..1033f63bb351e1eb836c3b72488501f249197dab
Binary files /dev/null and b/UsbReceive/UsbReceive/UsbReceive/Debug/UsbReceive.elf differ
diff --git a/UsbReceive/UsbReceive/UsbReceive/Debug/UsbReceive.hex b/UsbReceive/UsbReceive/UsbReceive/Debug/UsbReceive.hex
new file mode 100644
index 0000000000000000000000000000000000000000..f0af31da6fea15dbc07b0397f75539387b93cbe2
--- /dev/null
+++ b/UsbReceive/UsbReceive/UsbReceive/Debug/UsbReceive.hex
@@ -0,0 +1,769 @@
+:1000000000800020750100005D0100005D0100001E
+:1000100000000000000000000000000000000000E0
+:100020000000000000000000000000005D01000072
+:1000300000000000000000005D010000C901000098
+:100040005D0100005D0100005D0100005D01000038
+:100050005D0100005D0100005D0100006101000024
+:100060005D0100002D1F00005D0100005D0100002A
+:100070005D0100005D0100003D1F00005D0100000A
+:100080005D0100005D0100005D0100005D010000F8
+:10009000000000005D0100005D0100005D01000046
+:1000A0005D0100005D0100005D0100005D010000D8
+:1000B0000000000010B5064C2378002B07D1054B3B
+:1000C000002B02D0044800E000BF0123237010BDC4
+:1000D000B000002000000000382F0000084B10B5D1
+:1000E000002B03D00749084800E000BF0748036819
+:1000F000002B00D110BD064B002BFBD09847F9E731
+:1001000000000000B4000020382F0000AC000020E8
+:1001100000000000E12110B54902054800F028FC6C
+:100120000A2001F005FD00210E2001F039FD10BD6F
+:10013000D400002010B5084C200000F08BFB0028F4
+:1001400008DB00210122200000F006FA01000E2049
+:1001500001F026FD10BDC046D400002003BEFEE71E
+:10016000034B10B51B68002B00D0984710BDC0464C
+:10017000CC00002070B50F490F4CA14204D100F013
+:10018000FDF800F08DF8FEE70C4D00238D42F6D00F
+:10019000CA18E818A24205D39042F0D0084B09498A
+:1001A000002204E0006804331060F1E704C38B42CE
+:1001B000FCD3E4E700000020B00000203C2F00004A
+:1001C000B0000020A00B002010B500F066F8002859
+:1001D00001D100F057F810BD014B18607047C046C0
+:1001E000CC000020014B18687047C046D0000020AA
+:1001F000F7B51348012284461249134C8E68636890
+:1002000005689B0E1340019288686268019F920EF8
+:100210003A4067463F6893420ED1BD420CD18642B8
+:100220000AD35B19FA254868AD00861B07486B4363
+:100230007043000DC018FEBD3D0013000600E3E74B
+:10024000D000002010E000E000ED00E05555000077
+:1002500070B5041E10D0FFF7CBFF050000F01CF8AE
+:10026000FFF7C6FF054B401B9842F7D9FA23013C24
+:100270009B00ED18002CF3D170BDC046E7030000D1
+:100280007047000010B5034A13680133136000F093
+:1002900039F810BDD000002070470020704770472B
+:1002A00010B501F0C3FB02F07FFAFFF7F8FF012061
+:1002B000FFF7CEFF084C200000F066FE200000F0A3
+:1002C000FDFEFFF727FFFFF735FF044B002BFAD0A9
+:1002D00000E000BFF7E7C0463C010020000000003E
+:1002E00010B50400FFF7CCFF014B1C6010BDC046E9
+:1002F000000000200122024B52421A607047C046A3
+:1003000000000020164A10B51368591C27D0013B85
+:100310001360002B23D172B6124B134A043393425D
+:1003200008D8BFF34F8F114A114BDA60BFF34F8FDC
+:10033000C046FDE70F4A01211000147D0C42FCD09D
+:100340002021148BFF319B085B0021431183D36173
+:10035000094B13800123027D1A42FCD0E1E710BD56
+:100360000000002000000000030200000400FA0565
+:1003700000ED00E00040004102A5FFFF1E2270B525
+:1003800046484749436893431C3A13434360082354
+:100390008C692343C3248B61424BA4009C829C8ABA
+:1003A00014439C82DC681442FCD001243E4A147041
+:1003B0001578254203D055786DB2002DF8DB012465
+:1003C0009460547864B2002CFBDB384C5460547851
+:1003D00064B2002CFBDB8224E4015480547864B2C4
+:1003E000002CFBDB02249C840E34DD682542FCD00B
+:1003F0002F4CDC621024DD682542FCD09D8C2D4CF6
+:100400002C439C841024DD682542FCD002249D8C62
+:1004100080262C439C844024DD683542FCD0DD6876
+:100420002542F9D01024DD682542FCD000249460D8
+:10043000547864B2002CFBDB1F4C5460547864B2D7
+:10044000002CFBDB1C6A1D4D2C4080251C621C6AA5
+:10045000AC431C6203239360194B536053785BB227
+:10046000002BFBDB0023FF240B72164A4B728B72AE
+:10047000CB72154B1A60154B154A1B6811689A060A
+:100480005B01C90E2340520F12020B431343114A62
+:100490001385802342681343436070BD00400041D0
+:1004A0000004004000080040000C0040010501006D
+:1004B000B905FF7D040A000000070300FFFCFFFFF1
+:1004C00003060100006CDC021400002024608000A0
+:1004D000206080000040004210B50400FFF782FE5B
+:1004E000E060236820009B699847002808DAFFF73E
+:1004F00079FEE368C01AA3689842F2D30120404213
+:1005000010BD0000F8B504000D0016000127200002
+:10051000FFF7E2FF00281CDB2D281AD00300303B38
+:10052000092B16D9002E01D02E2812D0012D0ED065
+:10053000022D07D10938172809D83A008240054B07
+:100540001A4204D0236820005B699847DFE7012046
+:100550004042F8BD13008000F8B5170000220500E6
+:100560000024FFF7CFFFA0421CDB2600B84209D0D1
+:100570002D2819D00300303B092B03D80A235C43F4
+:100580002418303C2B6828005B6998472800FFF747
+:10059000A3FF0300303B092BE8D98742E6D0002EA9
+:1005A00000D064422000F8BD0126EBE70020704730
+:1005B00008B4024B9C46103808BC6047AD050000EB
+:1005C00030B50F25CB1D013902002A401400000967
+:1005D0003034092A01DD373214001C70013B8B4294
+:1005E000F2D130BD10B50C000B4B1868FFF7E8FFD7
+:1005F00021000A4B08311868FFF7E2FF2100084B81
+:1006000010311868FFF7DCFF2100064B183118681D
+:10061000FFF7D6FF202010BD0CA0800040A0800076
+:1006200044A0800048A0800008B4024B9C461038CB
+:1006300008BC6047E50500007047000008B4024BA5
+:100640009C46103808BC6047390600003F207047C0
+:1006500013B56B460268D97107335468190001223B
+:10066000A04716BDF0B50B7895B003AC02330190EE
+:100670000B7042220021200002F0D7F80922042545
+:1006800022720422A575627206250522242002AE7C
+:10069000657625779519A074E075E076E8773000E7
+:1006A00001210630C17730000730C17704A8C17737
+:1006B00009202173617580190631C1770A208019DC
+:1006C000C27703208446654605A8C5772E201027EB
+:1006D000801907702F20092508238019057004252B
+:1006E0002370033363700EA8093BE37023716371B9
+:1006F0006373A37362742376A276E27727752785E6
+:1007000005703320350080190A2603700FA8067083
+:1007100010A801703920401902703B203536761937
+:10072000317012A90A7080213D32401952190370AC
+:1007300013704020002249420E0041335B191870AB
+:100740005A70019B20871B7D019AA370A372637767
+:100750000133DBB2A377527D353816434019C67793
+:100760003120401903703A23501C5B191870412343
+:1007700002320A435B191A7021004222024800F03B
+:1007800025FF15B0F0BDC0463C01002008B4024B67
+:100790009C46103808BC60476506000070B50A79B1
+:1007A000037D0C0000259A420BD10B784E78A12BCB
+:1007B00009D1212E05D107221F49204800F006FF4C
+:1007C0000135280070BD212BFBD1202E19D1072225
+:1007D00019491A4800F03CFE174B1A78597809025B
+:1007E00011439A7812041143DA7812060A439621CB
+:1007F000C9008A4202D1DB79DB0708D5FFF77AFD11
+:1008000008E0222E0AD18A780B4BDA71E4E7FA204D
+:10081000FFF766FD0021094800F0EEFF0125232EB9
+:10082000CFD1E378A2781B021343054A0021034885
+:10083000136000F0E1FFC4E7080000203C01002045
+:100840000400002008B4024B9C46103808BC6047E6
+:100850009D07000010B5417D006A013100F02EFDBA
+:10086000034B1B6801335A1E9341181810BDC04634
+:100870001000002010B5417D006A023100F034FD07
+:1008800010BD10B5417D006A023100F0FBFC10BDC7
+:1008900070B50D00417D0400130002312A00006A8A
+:1008A00000F0EAFD002801D10123636070BD000063
+:1008B00010B5054C23685A1C04D103685B6998473E
+:1008C00003002060180010BD10000020074A03003C
+:1008D000106810B5411C03D001235B42136010BDAA
+:1008E000597D186A013100F077FDF8E7100000200B
+:1008F000FA239B0070B504008360032383752300F3
+:10090000002228334260A3610C4B02201D004433B7
+:1009100023610835631DE26125602162E075DA77A5
+:100920008323A362013B2363E06200F0ADF8210062
+:10093000103100F07DF8200070BDC046F82900009D
+:1009400010B5437D094A0220590101331268DBB218
+:100950005B015118D3180122FF318C7AFF332043F9
+:100960008872997A0A439A7210BDC046F405002035
+:100970007047000010B502490248FFF7B9FF10BDEB
+:100980003C010020D400002070B50E000025446812
+:10099000002C0BD0236831005B68200098470028AA
+:1009A00002DB2D18E468F3E701256D42280070BDD5
+:1009B00070B50D004468002C08D0236829009B689E
+:1009C00020009847002802D1E468F4E7200070BDB9
+:1009D00070B50D0000264468002C09D0236829005A
+:1009E00020001B69984736182D18F6B2E468F3E723
+:1009F00030002C7070BD70B50D004468002C08D01C
+:100A0000236829001B6820009847002802D1E46869
+:100A1000F4E7200070BD70B50D004468002C06D0CE
+:100A200023682000DB6829009847E468F6E770BD7A
+:100A3000F0B58C79457803002A190020072A1FDCBD
+:100A40005A68824216D159601A78C8790A71121808
+:100A50004D711A7000220B4D944210DD8F6858784A
+:100A60009600F7590132860001307751D2B25870A2
+:100A7000F2E70200D0680028FBD1D160E4E7012052
+:100A8000F0BDC046140100200122054905480B684D
+:100A9000134003D10370427043600A607047C04640
+:100AA000080100200C010020704710B5040001F07F
+:100AB0009BFA200010BD0000F0B5822919D1C3B205
+:100AC000294D5A01AA189169284C80010C40C02177
+:100AD0008905214391612649083308187021506126
+:100AE00028685B011A5C8A43110030220A431A54B9
+:100AF000F0BD0029FCD1C026C1B21B4C4B01E3184C
+:100B00009A681A4DB6052A4032439A60194A800104
+:100B100012185A600A000727246808325201115D32
+:100B2000B9430F000121394311559F6910493D40D8
+:100B300008182E439E6158617020115D81430800A2
+:100B400010210143115599680B48A21808408021D3
+:100B50004903014399609968890B8903996040238F
+:100B600011790B431371C3E7F4050020FFFFFF8FDA
+:100B70006801002028030020FF3F00F0EFF31083FE
+:100B800003600123436072B670470368002B02D1F3
+:100B900062B6BFF36F8F7047F7B50600FC36B369D6
+:100BA0000400002B18D1B2277F00C55D6846FFF70F
+:100BB000E5FF019BEDB2013B02D3E55DEDB2FAE743
+:100BC00068460193FFF7E1FF002D01D10020FEBD33
+:100BD000706E336EC01AFAE76846FFF7CFFFD8226F
+:100BE0000025019B5200013B02D3A55CEDB2FAE760
+:100BF00068460193FFF7C9FF002DE7D0D6235B00BD
+:100C0000E058043BE358E5E710B54468FC3043691D
+:100C10000B48DBB25A01A2189168083308408021C2
+:100C200049030143916091685B01890B89039160DD
+:100C30002268D318402219790A431A7110BDC046A0
+:100C4000FF3F00F0F7B50500FC352B7D4268190029
+:100C500004000831106849014118C979C90711D544
+:100C60005B01D21893689B049B0C0CD12000FFF70A
+:100C7000CBFF63681A686B69DBB208335B01D3187A
+:100C80007F22DA71F7BDE969002923D16B66230061
+:100C900001266933FF33EE6168465360B227FFF7E0
+:100CA0006DFF7F00B221019BFF31013B5A1C38D000
+:100CB000D822E6555200A25C581ED2B26254625C41
+:100CC0008446002A04D120000193FFF79DFFE9E745
+:100CD0006346EBE7D621490063500023EB61230014
+:100CE0001D33FF3353606846D826FFF747FF0127BF
+:100CF0007600B221019BFF31013B5A1C11D0B22278
+:100D0000A7555200A25C581ED2B26254625C84465F
+:100D1000002A04D120000193FFF776FFE9E763463C
+:100D2000EBE768460193FFF730FFA2E7F7B5050050
+:100D300068462C00FFF722FF0027FF22019BFC34AE
+:100D4000013B0DD3E0682169884204DBE768206934
+:100D5000D71B3F18F4E72769E1687F1A013FEFE7E7
+:100D600068460193FFF711FFA3696846002B41D144
+:100D7000FFF704FFB221019B4900013B5A1C0CD034
+:100D80006E5C5A1EF6B2002E05D168460193FFF73D
+:100D9000FCFE3000FEBD1300F0E76846019300261C
+:100DA000FFF7F3FEFF22BE4203D0236E616E8B423B
+:100DB00060D3636E226E9A42EBD100232366013327
+:100DC000A3616846B224FFF7D9FE6400B222002175
+:100DD000019BFF32013B581CD7D02955A85C5F1EF0
+:100DE000002805D0A95428000193FFF70DFFEDE777
+:100DF0003B00F0E7FFF7C2FED821019B4900013B11
+:100E00005A1C06D06E5C5A1EF6B2002EBDD01300DE
+:100E1000F6E768460193FFF7B8FED4220026520099
+:100E2000BE4205D0D6214900AB5869588B4232D317
+:100E3000D6235B00EB58A9589942AAD100236846F3
+:100E4000AB50A361D824FFF799FE6400B2220021C1
+:100E5000019BFF32013B581C97D02955A85C5F1EAF
+:100E6000002805D0A95428000193FFF7CDFEEDE737
+:100E70003B00F0E7591CEB18FF332166597FE3680C
+:100E8000206901331340834203D0E06828180172BF
+:100E9000E360013687E7591CA950FF21EB1869333D
+:100EA000FF331B789C46E36801330B4021698B427A
+:100EB00004D06046E16869180872E3600136AFE764
+:100EC00010B50400FFF732FF2300FC331969DA681C
+:100ED000914203D01B69E418207A10BD01204042E2
+:100EE000FBE710B50400FC34FFF720FFE06823693E
+:100EF000C01A01D50130FF3010BDF0B585B00192A8
+:100F000000910500FFF712FF02A8FFF737FE01204E
+:100F10000024FF26039A4042013A1DD32B00FC33E4
+:100F200001998C42F8D2D9681F69C91B01D50131DA
+:100F3000FF310029F0D01969DF688C460100BC45FB
+:100F400006D019691F69691801373740097A1F618E
+:100F5000009F39550134E3E702A80392FFF715FE1D
+:100F6000200005B0F0BD37B56B46DC1D00230D0039
+:100F70002370FFF789FD2100FFF706FD2B68181885
+:100F8000286020783EBD0000F8B520233E4A0500C9
+:100F9000D1690F200B43D36101223C490B781343E5
+:100FA0000B703B4B19788143197006211C78214343
+:100FB000197038490C7822430A701A7802401A7066
+:100FC000602219780A431A70334B344A5A805F788A
+:100FD000FF09FCD13248FFF7FFF8324E0123300001
+:100FE00010C839002278134380222370520001F088
+:100FF0001CFCA378DB07FCD41F2004362A4B666256
+:101000001B685A0B990C9B01024001405B0F824206
+:1010100000D105221F2900D10239072B00D1043B42
+:10102000268D224F02403E40920132432285228D7E
+:10103000014082430E00110031432185228D1903A6
+:101040001B4B1C4813407F220B4323852378C1216F
+:101050001340237004232278890013430C22237049
+:1010600023899343144A238153581B021B0A53506C
+:101070008023136022787E3B1343237001230021D9
+:101080002B70FFF775FCF8BD000400405844004188
+:101090003C44004159440041000C0040064000001F
+:1010A0000D1A0000F4050020246080003FF8FFFFC7
+:1010B000FF8FFFFFD400002000E100E0007800284F
+:1010C00010D00121084B1B681A898A431A81082213
+:1010D000198B0A431A830422198B0A431A830022AC
+:1010E000024B1A607047C046F4050020EC05002052
+:1010F00010B50F4A93699B0B9B03936113680222FF
+:10110000FF331A729879823A02439A711A7A9207D7
+:10111000FCD57F24074A2140937A0800A343190095
+:10112000802301439172917A5B420B43937210BD0D
+:10113000F40500200050004110B50C00FFF7A4FC9E
+:101140002100FFF758FC002804D1034A93699B0B48
+:101150009B03936110BDC046F4050020F8B50D0057
+:10116000832A19D1CBB2394C5A01A2189169384857
+:10117000AD010840C02189050143916135492068CE
+:101180004D197021083355615B011A5C8A431100C7
+:1011900040220A431A54F8BD022A52D12E4A8B002B
+:1011A0009858002802D003685B699847DA2040000D
+:1011B00000F016FF80220400244E284B4660036096
+:1011C00052000021083001F030FB22000023FC32E5
+:1011D000D3605561136113669361D3615366B22284
+:1011E0005200A3544432A3500432A3500432A354F7
+:1011F000B222FF32A354EAB2500131188B68144F67
+:1012000008321F40C0239B053B4307278B60336890
+:101210005201D65CAD00BE43B446032667463E434A
+:10122000D65422001D32FF324A6001221B18FF33C0
+:10123000997A20000A439A72FFF7E6FC064B5C514C
+:10124000A9E711002800FFF737FCA4E7F405002008
+:10125000FFFFFF8F6801002040010020582A000096
+:1012600070B505000124064BA200D258002A06D012
+:10127000210028000134FFF771FF0A2CF3D170BD63
+:10128000140100200B4BCAB20B48890159185301B5
+:10129000C318596199690832890B890399610368F8
+:1012A00052019A180223D3715179823B0B43537137
+:1012B0007047C04668010020F4050020084B8A00F2
+:1012C000D05810B5002803D003689B68984710BD1C
+:1012D000C9B2044B4901591888688004800CF6E7AC
+:1012E00040010020F405002010B50C00FFF7E6FFD8
+:1012F00000280CD0064BE4B21B68083464011C19AA
+:10130000802362795B42134363710223E37110BD52
+:10131000F4050020F0B51C002B4B85B01B680700BE
+:101320000D000292002B4BD0284B8A00D058002889
+:1013300008D0036822005B680299984704002000E7
+:1013400005B0F0BD3800FFF7B9FF844204D9290089
+:101350003800FFF7B3FF04000121EBB21C4E0393EA
+:101360005B010193F21893689B0B9B039360019AB6
+:10137000336802989B18FF335A7A0A4315495A7208
+:10138000AB01C918220001F047FA002CD7D0290080
+:101390003800FFF793FF0028D1D14021039B32682A
+:1013A00008335B01D3181879014319710121D971F0
+:1013B0000121019BD318FF339A7A0A439A72BEE740
+:1013C00001246442BBE7C046EC0500204001002038
+:1013D000F40500202803002013B56B46DC1D220015
+:1013E0000123FFF797FF012801D1207816BD0120C6
+:1013F0004042FBE770B5134BCCB2134A6001890140
+:101400005918131859609968104D08340D408021FF
+:1014100049032943402599609968890B890399609C
+:1014200011686301CB181E7935431D719D796D06D6
+:10143000FCD564010919CB79DB07FCD5121890683B
+:10144000C0B270BD28030020F4050020FF3F00F06B
+:1014500070B50D0000211400FFF7CCFFA04200D9A9
+:10146000200000230349A34203D05A5CEA5401330D
+:10147000F9E770BD28030020F0B51E003A4B85B097
+:101480001B680F000192002B35D08023DB019E42A8
+:1014900031D80025354A8B01D3180293002E2CD069
+:1014A000334B1B680393FF233B401C00009308341D
+:1014B000039B64011C19A379DB0921D02D4B2E4914
+:1014C000186801F0E5F82D4B1721584301F0E0F8BA
+:1014D0002B4BE279920713D4DA5D002A01D101384F
+:1014E000F7D20122DA55009B214A5B01D3189A6991
+:1014F000920B92039A6101256D42280005B0F0BD60
+:1015000000221F4B3400DA553F2E09D9009B40249E
+:101510005A01174B9B188022996912060A439A6157
+:1015200022000199029801F077F9009BA1045A0169
+:101530000F4B890C9B18029A2D195A619A69361B18
+:10154000920B92030A439A61009B039A08335B0152
+:10155000D3180222DA715979823A0A435A71019BEF
+:101560001B1901939AE7C046EC0500206801002092
+:10157000F40500201400002040420F00701101000B
+:101580005D01002070B50D001C000D4EAB01F6187A
+:1015900011003000220001F03FF9EDB209496D0160
+:1015A0004D196E61AB69084A20001340AB61AB690D
+:1015B000A2049B0B920C9B031343AB6170BDC0460E
+:1015C00068010020F4050020FF3F00F0F7B5104B44
+:1015D00001901B780F001500002B0CD10D4B16004D
+:1015E0001C78002C09D00C4E0C4834880019641962
+:1015F00001F012F934802800FEBD002EFBD03A190C
+:10160000330000210198FFF7BDFF2418361AF4E7D4
+:10161000E8040020E9050020EA050020E904002094
+:10162000F8B50E0015000027012A27D9100001F097
+:10163000DFF80400300001F0BBF901304000032363
+:10164000207002223800637095420DD9317800294C
+:101650000AD0531CDBB20136A1549D4203D00232A2
+:10166000E054D2B2F0E72A0021000548FFF7AEFFB0
+:10167000471EB841C7B2200001F0C4F83800F8BDD9
+:101680003C010020F0B50027012687B01E4B0091D9
+:1016900002A91E7005000297FFF765FC03AC0190DC
+:1016A00009223900200001F0C0F809232370022329
+:1016B00063709E33E3715A332372029B6671093360
+:1016C00063806B461B7923710F4B1F70009B092BA6
+:1016D00007D11A0021002800FFF778FF012007B08A
+:1016E000F0BD0A4B09221E70094E21002800029706
+:1016F0003780FFF76BFF02A92800FFF734FC034B8C
+:1017000032881F700349E6E7E8040020E90500205D
+:10171000EA050020E904002070B5CE7892B00500FB
+:101720000C00022E0BD18B79C9792E48090219437E
+:10173000FFF7A8FF411E8841C0B212B070BDFFF78D
+:10174000A3F92100FFF734F9002803D0C117081AC4
+:10175000C00FF2E7012E0ED1E279A37912021A43EB
+:101760002149112A3CDCD2B2002A39D02800FFF7E7
+:101770002DFF0120E1E7032EDFD1A378002B28D035
+:10178000022B08D1E279A379120218491A432800E2
+:10179000FFF746FFD1E7012B05D1E279A3791202C9
+:1017A0001A431349F3E7032BC7D10100412201A8D3
+:1017B00001F03BF8FFF768F901A9FFF709F90028E4
+:1017C00005D0E279A37912021A4301A9DFE7037871
+:1017D000FFDEE279A37912021A430649032AC2DD29
+:1017E0000A78C3E73C0100208F2A0000742A000019
+:1017F000822A00007E2A0000CBB204495B01C9188E
+:101800008B699B0B9B038B617047C046F4050020DE
+:1018100037B5050048780C000B2811D800F02EFFD2
+:10182000061D102E104348644C4F5D60097801AAD4
+:10183000002907D10223117051702800FFF7A2FE82
+:1018400001203EBD002313705370284B1B78012BE1
+:1018500000D1137002230021EFE78A780023012AC8
+:1018600004D101AA13705370214BEFE71F4A137084
+:10187000204A93699B0B9B039361E1E78C78012CD1
+:1018800006D100211A4B01AA1C7011702300D4E765
+:101890000120002CD5D1154B164A187093699B0B6B
+:1018A0009B039361CDE789782800FFF721FCC7E708
+:1018B0002800FFF731FFC4E701230F4ACBE70B787D
+:1018C0000020DB06BDD12800FFF7CAFCA2780A4B36
+:1018D0000A481A60FFF734F8CAE70123084ABAE752
+:1018E0008A78074B1A60C3E70020AAE75C01002052
+:1018F00064010020F4050020EC050020D400002045
+:10190000F00500203B4BF7B51E780500002E61D195
+:10191000394C23689A8B12070DD5082231009A831F
+:101920003000FFF7C9F810222368FF33997A0A4381
+:101930009A72324B1E6023689A8B520701D504229B
+:101940009A83FF331A7A920603D52022597A0A43E2
+:101950005A721A7AD20625D56846294A6946C0CAFB
+:10196000C0C0A268920B9203A26040225879024341
+:101970005A7160230A7828001A422CD1FFF748FFD9
+:1019800000282BD0802223685242FF3399790A43E2
+:101990009A712368FF331A7A520603D54022597A86
+:1019A0000A435A727F2601252368FF331E722F00D7
+:1019B000236808377F01DB19DB79002B07D0114B37
+:1019C000AA00D05800280CD003681B68984701353E
+:1019D000082DECD1F7BDFFF7AFFBD1E720220A4B72
+:1019E000D6E7FFF751F82900FFF715F82368DF194C
+:1019F000FE71ECE7E9050020F4050020EC0500206D
+:101A00002803002040010020FF50004110B502488B
+:101A1000FFF778FF10BDC0463C010020014A024B91
+:101A20001A60704700500041F4050020FA21314B44
+:101A300010B51868890000F02BFE2F4B0138984232
+:101A400056D82E492E4A4860C020136A00061B0251
+:101A50001B0A03431362002407238C600B60802160
+:101A6000136A09061B021B0A0B431362FC22254B57
+:101A7000196A0A431A62FC22196A92010A431A621D
+:101A8000A022196AD2020A431A62200000210134FE
+:101A900000F076F9142CF8D11B4B1C005A7852B286
+:101AA000002AFBDB194A5A80194B1A00597EC909D2
+:101AB0000129FBD0E421C90099803F21D970537ED0
+:101AC000DB09012BFBD0C02300205B011361907068
+:101AD00000F034F863785BB2002BFBDB0D4B0E4A51
+:101AE0006380D379DB09012BFBD04123537010BDF8
+:101AF000FEE7C04614000020FFFFFF0010E000E0FA
+:101B000000ED00E000040040000C00401E4000001A
+:101B1000004000422140000000480042914202D0B3
+:101B200002D98A1AD0407047521A9040FBE7000051
+:101B3000014B18607047C04618000020164A00B5D7
+:101B40001300517EC9090129FBD00138042816D899
+:101B50001969124A0A400F211A615A788A4300F023
+:101B60008DFD0308060B0300110001220A435A7081
+:101B700000BD11000322F9E711000222F6E7F0236D
+:101B800011691B050B430F21136153788B43190017
+:101B900002230B435370EBE700400042FFFFFFF0CE
+:101BA00018234343F0B56D4A87B09B18DA680700E5
+:101BB0000C000092920722D51B7C5BB2002B01D057
+:101BC000142B1AD1664B0A2219682000FFF7A6FFD2
+:101BD000644A1300D179C9090129FBD08005800D21
+:101BE0001081DA79D209012AFBD0022219780A433E
+:101BF0001A70DA79D209012AFBD007B0F0BD0826A5
+:101C0000009A574D3240019200D196E012229B5E1D
+:101C10002968200010220193FFF780FF019B050037
+:101C20001E126B461C79009B0421DB0600D40521A3
+:101C3000380000F01DF94C4B9A5D002A58D1013252
+:101C40009A554A490F3202A800F0E6FD02AA730035
+:101C50009B5A8022D2011A43454B5A805A78D209A6
+:101C6000012AFBD0434AB300D358022E1CD90221CB
+:101C70001A888A431A80DA7BD209FCD1198840324B
+:101C80000A431A80DA7BD209FCD10C34ADB264006D
+:101C9000E552DA7BD209FCD1198802320A431A8054
+:101CA000DA7BD209FCD1A8E702211A688A433249BB
+:101CB0001A600A0098680842FCD10221D86B0143DF
+:101CC000D96399681142FCD11034A4001C196560D5
+:101CD00099681142FCD12949196499681142FCD1D3
+:101CE000022118680143196099681142FCD184E708
+:101CF000204AB300022E08D9D2580C34ADB2640089
+:101D0000A552D37BDB09FCD177E7D358022259795E
+:101D10000A435A71184A110098681042FCD11C34C9
+:101D2000A400E5509A680A42FCD1022218790243C5
+:101D30001A719A680A42FCD15FE7012100F020F88D
+:101D4000296832002000FFF7E9FE01997F2800D9B9
+:101D50000121380000F060F84FE7C046B42A0000C7
+:101D60001800002000480042F8060020A22A0000C7
+:101D7000000C00401C000020FF0F7F00FFFF000050
+:101D8000182330B51D00040045430820204A55198A
+:101D90002856013014D0032912D808006343D156C5
+:101DA000D31800F06BFC02280E1B5868CB010221EF
+:101DB000184A9B181A1840321170012282405A604A
+:101DC00030BD5868CB010621124A9B181A184032C0
+:101DD0001170012282405A609A61F1E75868CB0184
+:101DE00006210C4A9B181A184032117001228240B9
+:101DF0005A605A61E4E75868CB010221054A9B18F2
+:101E00001A1840321170012282409A60D8E7C04609
+:101E1000B42A0000004400411823F0B508245843B8
+:101E2000114A13181C5701341BD0012635005F6876
+:101E30008356BD400D4ADB019A18906828420BD1A9
+:101E40000C00601E8441D2194032107834400336B1
+:101E5000A400B04320431070044A9B18002901D10C
+:101E60005D61F0BD9D61FCE7B42A000000440041C3
+:101E7000F8B50300182058432A4A1018007A40B2D7
+:101E80000400013013D0481C00240C280FD800F0A7
+:101E9000F5FB451C1C1C1C1C1C1C1C070707070011
+:101EA000092906D100211800FFF76AFF002420004D
+:101EB000F8BD0A2901D10839F5E700240B29F6D12C
+:101EC0000A391800FFF75CFFF1E718204343D018E8
+:101ED000466801253400D2561348D20112187308FF
+:101EE000D31830332C401878002C0BD00F24090164
+:101EF00020400143C9B292191970403213781D4332
+:101F00001570D3E70F27B84301439219C9B219706E
+:101F1000130040331A7815431D70C8E7012464424A
+:101F2000C5E7C046B42A00000044004110B502488D
+:101F300000F0A9FA10BDC0460007002010B5024805
+:101F400000F0A1FA10BDC0463C090020F7B50124FD
+:101F50000326154F1549380000F04AF81449154872
+:101F600000F046F81449154800F042F814491548A5
+:101F700000F03EF81449154800F03AF8144D1549A0
+:101F8000280000F035F83900009623000194002263
+:101F9000114800F00DFA0096290001941E231F221B
+:101FA0000E4800F005FAF7BD780B0020000800424B
+:101FB000000C00427C0B002000100042800B00202F
+:101FC00000140042840B002000180042880B0020FF
+:101FD0008C0B0020001C0042000700203C09002060
+:101FE00010B500F005FC10BD10B500F00BFC10BDE5
+:101FF00001607047F0B505AC25780468981E471E4F
+:10200000B841266892070006324302430720226047
+:102010000140AD01626829430020022B00D0580323
+:10202000114301436160F0BD10B5C0240368A403EF
+:102030001868120522400243C020090480020140B2
+:10204000114319605A681043586010BD012203689B
+:1020500019680A431A601A68D207FCD4DA69D207F1
+:10206000F9D470470222036819680A431A60DA69D2
+:102070009207FCD4704703681A7ED20702D41A7EF6
+:102080009207FCD57047002203685A8370470368A3
+:10209000187E4007C00F70470368187EC00970475C
+:1020A000802302685B42117E0B43137670470368FE
+:1020B000588B8007C00F704702230268518B0B4377
+:1020C000538370470368187EC007C00F70470368CA
+:1020D000188DC0B2704703681A7ED207FCD589B24A
+:1020E000012019857047012203689A757047012203
+:1020F00003681A75704700000368214A30B593429F
+:1021000011D0204A93422FD01F4A93422FD01F4A0A
+:1021100093422FD01E4A93422FD01E4A934222D17F
+:102120000E23192201E009231422012103259940DD
+:102130001948C024016099082B40AB40FC359D40F4
+:1021400089000918A4000859A843C0259D402B0008
+:1021500003430B518023DB011A43104B5A805A78FA
+:1021600052B2002AFBDB30BD0A231522DDE70B2328
+:102170001622DAE70C231722D7E70D231822D4E71B
+:1021800000080042000C004200100042001400420F
+:1021900000180042001C004200E100E0000C00407A
+:1021A000F8B5040016000F001D00FFF7A5FF200082
+:1021B000FFF74CFF1C22BB00134072072468120C6F
+:1021C000134323608423A375012F18D11021012EFE
+:1021D00000D008390A4B69431868C00000F058FA6B
+:1021E0000722A3890240DB045203DB0C1343A381C3
+:1021F0000304A089DB0C400B40031843A081F8BD09
+:10220000140000200120704710B50368014A1B6AC2
+:10221000984710BD130400000300FC33D9699A6984
+:10222000914203D0DB69C018007D70470120404215
+:10223000FBE710B504000069FFF708FF2200002348
+:10224000FC329361D36186229200A4186360A3607C
+:1022500010BDF02001403039484248417047F0231A
+:102260001B011940802306209B0099420AD00133AC
+:10227000FF330130994205D0802302385B00994238
+:1022800000D0002070470F2001400020012903D01A
+:102290000239481E8141481C704700008923F0B56F
+:1022A000182685B002919B000400C05C3300082111
+:1022B0004343324D1700EB185956FFF7D9FD304B09
+:1022C0000821E05C33004343EB185956FFF7D0FD7B
+:1022D0002C4BE25C0393022A09D11133E05CFF2806
+:1022E00005D008214643AE197156FFF7C1FD8A2675
+:1022F000B600A05DFF2819D00121FFF741FD18228B
+:10230000A35D21495A43AB56AD18DB0158188B2108
+:10231000890060501D4901225B188C21890063509F
+:1023200069688A408D21890062501A600122029BEF
+:1023300011002069FFF734FF39002000FFF78FFFFD
+:10234000390005002000FFF79EFF3900060020003D
+:10235000FFF77FFF33000090290020690122FFF77B
+:1023600049FE0B4B2069E25C039BE15CFFF75CFEDE
+:102370002069FFF777FE05B0F0BDC046B42A000023
+:1023800025020000270200001844004114440041C7
+:1023900026020000802210B504005200002100F047
+:1023A00044FA23000022FC335A6020009A6010BDDA
+:1023B000F7B51D0008AB1B780400009309AB1B7830
+:1023C0001600019300234360FA239B008360114BA6
+:1023D0000F00083303601430FFF7DCFF20001D30CE
+:1023E000FF30FFF7D7FF89236A469B002761E65439
+:1023F000094B1278E554094B2000E2546A46084B19
+:102400001279E2548A22293BFF3B9200A3541032F6
+:10241000A354FEBD042F0000250200002602000088
+:10242000270200000300FC3358689B68C01A01D5DE
+:102430000130FF30704710B5040020001D30FF3020
+:10244000FFF7F0FF0028F8D12069FFF714FE10BD58
+:1024500010B51430FFF7E6FF10BD0300FC335968D8
+:102460009A68914204DB5A689868801AFF30704776
+:1024700098685B68C01A0138F9E710B51D30FF3065
+:10248000FFF7EBFF10BD10B504000069FFF70FFE6A
+:10249000002805D02069FFF71AFE2069FFF70CFE1F
+:1024A0002069FFF7F4FD002820D02069FFF70FFE18
+:1024B0002200FC329369D1690133DBB28B4203D035
+:1024C00091696118087593618A239B00E35CFF2B77
+:1024D0000CD020001430FFF7C0FF092806DC8B2346
+:1024E0008D229B009200E358A2581A602069FFF7E2
+:1024F000E9FD00281AD020001D30FF30FFF792FFC1
+:10250000002822D086239B00E31899685A689142DC
+:1025100018D08E219A684900A218515C9A6801323D
+:10252000D2B29A60C9B22069FFF7D5FD2069FFF7E2
+:10253000B3FD002805D02069FFF7B2FD2069FFF741
+:10254000A2FD10BD01214942ECE72069FFF7CFFD54
+:10255000ECE7000070B5040000690D00FFF7B2FD64
+:10256000002824D1FF2686239B00E3185A68996827
+:10257000013232408A422FD1EFF31083DB070DD4B2
+:102580001E4B5B68DB05DB0DEDD0103B5BB2002B17
+:1025900019DB9B08C0331A4A9B009B582069FFF740
+:1025A00091FD0028DFD02000FFF76DFFDBE7200062
+:1025B0001D30FF30FFF736FF0028D3D129002069F6
+:1025C000FFF789FD17E00F221340083B9B080D4AD7
+:1025D0009B009B181B68E1E75A68013216409A6815
+:1025E000964205D08E215A684900A21855545E6063
+:1025F0002069FFF778FD012070BDC04600ED00E0C6
+:1026000000E100E01CED00E00300FC33D9699A69A9
+:1026100070B5040091421AD0DA698218157DDA6922
+:102620000132D2B2DA618A239B00E35CFF2B0CD02B
+:1026300020001430FFF711FF0A2806DD8C238D22BD
+:102640009B009200E358A2581A60280070BD012533
+:102650006D42E8E7F7B506000D000C008B180193FA
+:10266000019B671B9C4207D0336821781B683000B0
+:10267000984701340028F3D13800FEBD02B47146FA
+:1026800049084900095C49008E4402BC7047C046B5
+:10269000002243088B4274D303098B425FD3030AA1
+:1026A0008B4244D3030B8B4228D3030C8B420DD3B4
+:1026B000FF22090212BA030C8B4202D31212090242
+:1026C00065D0030B8B4219D300E0090AC30B8B4280
+:1026D00001D3CB03C01A5241830B8B4201D38B032E
+:1026E000C01A5241430B8B4201D34B03C01A5241D3
+:1026F000030B8B4201D30B03C01A5241C30A8B4216
+:1027000001D3CB02C01A5241830A8B4201D38B0200
+:10271000C01A5241430A8B4201D34B02C01A5241A4
+:10272000030A8B4201D30B02C01A5241CDD2C30916
+:102730008B4201D3CB01C01A524183098B4201D392
+:102740008B01C01A524143098B4201D34B01C01A7D
+:10275000524103098B4201D30B01C01A5241C308F5
+:102760008B4201D3CB00C01A524183088B4201D364
+:102770008B00C01A524143088B4201D34B00C01A50
+:102780005241411A00D20146524110467047FFE7BC
+:1027900001B5002000F006F802BDC0460029F7D0C0
+:1027A00076E770477047C04670B500260C4D0D4C5B
+:1027B000641BA410A64209D1002600F011F90A4DAD
+:1027C0000A4C641BA410A64205D170BDB300EB589F
+:1027D00098470136EEE7B300EB5898470136F2E729
+:1027E000980000209800002098000020A8000020F9
+:1027F00010B5034B0100186800F06AF810BDC04620
+:102800003400002010B5034B0100186800F016F8E2
+:1028100010BDC04634000020002310B59A4200D1FC
+:1028200010BDCC5CC4540133F8E703008218934216
+:1028300000D1704719700133F9E7000070B5050049
+:10284000002910D00C1F2368002B00DAE4182800A0
+:1028500000F0B5F81D4A1368002B05D163601460C1
+:10286000280000F0ADF870BDA34209D921686018B6
+:102870008342F3D118685B6841182160EEE71300CA
+:102880005A68002A01D0A242F9D919685818A04202
+:102890000BD120680918581819608242E0D11068DD
+:1028A0005268411819605A60DAE7A04202D90C2335
+:1028B0002B60D5E721686018824203D11068526806
+:1028C0004118216062605C60CAE7C046900B00203E
+:1028D000032370B5CD1C9D43083506000C2D1ED278
+:1028E0000C25A9421DD8300000F069F8254A14686B
+:1028F0002100002919D1244C2368002B03D130007A
+:1029000000F044F820602900300000F03FF8431C3C
+:102910002CD10C233000336000F052F803E0002D7E
+:10292000DFDA0C233360002070BD0B685B1B1AD408
+:102930000B2B03D90B60CC18256003E08C420ED121
+:1029400063681360300000F03BF8200007220B3072
+:10295000231D9043C31AE7D05A42E250E4E74B6884
+:1029600063600C00EEE70C004968C2E70323C41C57
+:102970009C43A042E0D0211A300000F007F8431C2D
+:10298000DAD1C6E7900B0020940B0020002370B52D
+:10299000064C05000800236000F014F8431C03D126
+:1029A0002368002B00D02B6070BDC0469C0B00201C
+:1029B0000023C25C0133002AFBD1581E70477047C8
+:1029C00070470000044A1368002B03D018181060E9
+:1029D00018007047014BF9E7980B0020A00B00206E
+:1029E000F8B5C046F8BC08BC9E467047F8B5C0466E
+:1029F000F8BC08BC9E4670470000000000000000C4
+:102A000051060000910800004D0600007508000006
+:102A100055080000CD080000B10800008308000040
+:102A200065060000AD0500009D070000E5050000FB
+:102A300039060000F0FFFFFF00000000450800001D
+:102A40008D070000B10500003D06000029060000CA
+:102A50000000000000000000450C0000FB0E00001C
+:102A6000E30E0000C10E0000A90A0000AB0A00003E
+:102A7000990B000054696E795A65726F0000040367
+:102A8000090454696E79436972637569747300123D
+:102A9000010002EF020140EB030980000101020383
+:102AA00001001A001A001B001B001C001C001D0066
+:102AB0001D000000000000000B00000002000000EC
+:102AC00004000000FF00FFFFFFFF0B0000000000FC
+:102AD0000A0000000200000004000000FF00FFFFE9
+:102AE000FFFF0A00000000000E00000008000000C8
+:102AF00004000000FF00FFFFFFFF0E0000000000C9
+:102B000009000000040000001C000000FF0001009C
+:102B1000010009000000000008000000040000009F
+:102B20001C000000FF00000000001000000000007A
+:102B30000F000000040000001C000000FF00010363
+:102B400001030F0000000000140000000500000059
+:102B50001C000000FF000200020004000000000052
+:102B6000150000000800000004000000FF00FFFF47
+:102B7000FFFF050000000000060000000400000048
+:102B80001C000000FF000001000106000000000022
+:102B900007000000040000001C000000FF0001010D
+:102BA0000101070000000000120000000400000006
+:102BB0001C000000FF0000030003020000000000F2
+:102BC00010000000020000001C000000FF000002D6
+:102BD00000020000000000001300000002000000DE
+:102BE0001C000000FF0003000300030000000000C1
+:102BF00011000000020000000C000000FF000102B4
+:102C0000FFFF0100000000000200000001000000C2
+:102C1000020000000000FFFFFFFF020001000000B3
+:102C20000800000001000000020000000200FFFF99
+:102C3000FFFF080001000000090000000100000083
+:102C4000020000000300FFFFFFFF0900000000007A
+:102C50000400000001000000020000000400FFFF6B
+:102C6000FFFF04000000000005000000010000005C
+:102C7000020000000500FFFFFFFF0500010000004B
+:102C80000200000001000000020000000A00FFFF37
+:102C9000FFFF02000000000016000000020000001C
+:102CA00004000000FF00FFFFFFFF0600000000001F
+:102CB000170000000200000004000000FF00FFFFFA
+:102CC000FFFF0700000000000C00000003000000F0
+:102CD00004000000FF00FFFFFFFF0C0001000000E8
+:102CE0000A0000000300000004000000FF00FFFFD6
+:102CF000FFFF0A00010000000B00000003000000BD
+:102D000004000000FF00FFFFFFFF0B0001000000B8
+:102D10000300000008000000040000000B00FFFF9B
+:102D2000FFFF0300000000001B000000080000007F
+:102D300004000000FF00FFFFFFFF0F000000000085
+:102D40001C0000000600000000000000FF00FFFF64
+:102D5000FFFFFF0000000000180000000600000058
+:102D600000000000FF00FFFFFFFFFF000000000069
+:102D7000190000000600000000000000FF00FFFF37
+:102D8000FFFFFF000100000016000000030000002C
+:102D900000000000FF00FFFFFFFF06000100000031
+:102DA000170000000300000000000000FF00FFFF0C
+:102DB000FFFF0700000000001600000002000000F6
+:102DC00000000000FF00FFFFFFFFFF000000000009
+:102DD000170000000200000000000000FF00FFFFDD
+:102DE000FFFFFF00000000001300000002000000D1
+:102DF00000000000FF00FFFFFFFFFF0000000000D9
+:102E0000100000000200000000000000FF00FFFFB3
+:102E1000FFFFFF00000000001200000002000000A1
+:102E200000000000FF00FFFFFFFFFF0000000000A8
+:102E3000110000000200000000000000FF00FFFF82
+:102E4000FFFFFF00000000000D0000000200000076
+:102E50000C000000FF000100FFFF0D00000000005B
+:102E600015000000050000000C000000FF0003003A
+:102E7000FFFFFF000000000006000000040000004B
+:102E80000C000000FF000001FFFFFF000000000039
+:102E900007000000040000000C000000FF0001011A
+:102EA000FFFFFF0000000000030000000100000021
+:102EB000020000000100FFFFFFFFFF000000000014
+:102EC0000200000001000000020000001400FFFFEB
+:102ED000FFFF0200000000001E00000008000000CC
+:102EE00004000000FF00FFFFFFFFFF0000000000E4
+:102EF0001F0000000800000004000000FF00FFFFAA
+:102F0000FFFFFF000000000000000000552500004A
+:102F1000552600007B2400003724000051240000C7
+:102F20000926000019220000092200009D2200004D
+:0C2F300033220000052200000000000019
+:102F3C00FFFFFFFFFFFFFFFF00C2010000000800C2
+:102F4C00FFFFFFFF40420F0008000000002000427E
+:102F5C000024004200280042002C004200300042B5
+:102F6C000034004238000020000000000000000087
+:102F7C000000000000000000000000000000000045
+:102F8C000000000000000000000000000000000035
+:102F9C000000000000000000000000000000000025
+:102FAC000000000000000000000000000000000015
+:102FBC000000000000000000000000000000000005
+:102FCC000000000000000000DD000000750900009A
+:102FDC001D1A00004D1F0000B5000000000000008D
+:040000030000017583
+:00000001FF
diff --git a/UsbReceive/UsbReceive/UsbReceive/Debug/UsbReceive.lss b/UsbReceive/UsbReceive/UsbReceive/Debug/UsbReceive.lss
new file mode 100644
index 0000000000000000000000000000000000000000..77c1f91dc18a9061ef8a9f81647a96915dc72945
--- /dev/null
+++ b/UsbReceive/UsbReceive/UsbReceive/Debug/UsbReceive.lss
@@ -0,0 +1,7847 @@
+
+UsbReceive.elf: file format elf32-littlearm
+
+Sections:
+Idx Name Size VMA LMA File off Algn
+ 0 .text 00002f3c 00000000 00000000 00010000 2**2
+ CONTENTS, ALLOC, LOAD, READONLY, CODE
+ 1 .data 000000b0 20000000 00002f3c 00020000 2**2
+ CONTENTS, ALLOC, LOAD, DATA
+ 2 .bss 00000af0 200000b0 00002fec 000200b0 2**2
+ ALLOC
+ 3 .ARM.attributes 00000028 00000000 00000000 000200b0 2**0
+ CONTENTS, READONLY
+ 4 .comment 00000059 00000000 00000000 000200d8 2**0
+ CONTENTS, READONLY
+ 5 .debug_info 0005bc66 00000000 00000000 00020131 2**0
+ CONTENTS, READONLY, DEBUGGING
+ 6 .debug_abbrev 00006748 00000000 00000000 0007bd97 2**0
+ CONTENTS, READONLY, DEBUGGING
+ 7 .debug_loc 00008597 00000000 00000000 000824df 2**0
+ CONTENTS, READONLY, DEBUGGING
+ 8 .debug_aranges 000009a0 00000000 00000000 0008aa76 2**0
+ CONTENTS, READONLY, DEBUGGING
+ 9 .debug_ranges 000014b0 00000000 00000000 0008b416 2**0
+ CONTENTS, READONLY, DEBUGGING
+ 10 .debug_macro 0001d3d4 00000000 00000000 0008c8c6 2**0
+ CONTENTS, READONLY, DEBUGGING
+ 11 .debug_line 0000de73 00000000 00000000 000a9c9a 2**0
+ CONTENTS, READONLY, DEBUGGING
+ 12 .debug_str 00081c1e 00000000 00000000 000b7b0d 2**0
+ CONTENTS, READONLY, DEBUGGING
+ 13 .debug_frame 000019cc 00000000 00000000 0013972c 2**2
+ CONTENTS, READONLY, DEBUGGING
+
+Disassembly of section .text:
+
+00000000 <exception_table>:
+
+void *operator new(size_t size) {
+ return malloc(size);
+}
+
+void *operator new[](size_t size) {
+ 0: 00 80 00 20 75 01 00 00 5d 01 00 00 5d 01 00 00 ... u...]...]...
+ ...
+ 2c: 5d 01 00 00 00 00 00 00 00 00 00 00 5d 01 00 00 ]...........]...
+ 3c: c9 01 00 00 5d 01 00 00 5d 01 00 00 5d 01 00 00 ....]...]...]...
+ 4c: 5d 01 00 00 5d 01 00 00 5d 01 00 00 5d 01 00 00 ]...]...]...]...
+ 5c: 61 01 00 00 5d 01 00 00 2d 1f 00 00 5d 01 00 00 a...]...-...]...
+ 6c: 5d 01 00 00 5d 01 00 00 5d 01 00 00 3d 1f 00 00 ]...]...]...=...
+ 7c: 5d 01 00 00 5d 01 00 00 5d 01 00 00 5d 01 00 00 ]...]...]...]...
+ 8c: 5d 01 00 00 00 00 00 00 5d 01 00 00 5d 01 00 00 ].......]...]...
+ 9c: 5d 01 00 00 5d 01 00 00 5d 01 00 00 5d 01 00 00 ]...]...]...]...
+ ac: 5d 01 00 00 00 00 00 00 ].......
+
+000000b4 <__do_global_dtors_aux>:
+ b4: b510 push {r4, lr}
+ b6: 4c06 ldr r4, [pc, #24] ; (d0 <__do_global_dtors_aux+0x1c>)
+ b8: 7823 ldrb r3, [r4, #0]
+ ba: 2b00 cmp r3, #0
+ bc: d107 bne.n ce <__do_global_dtors_aux+0x1a>
+ be: 4b05 ldr r3, [pc, #20] ; (d4 <__do_global_dtors_aux+0x20>)
+ c0: 2b00 cmp r3, #0
+ c2: d002 beq.n ca <__do_global_dtors_aux+0x16>
+ c4: 4804 ldr r0, [pc, #16] ; (d8 <__do_global_dtors_aux+0x24>)
+ c6: e000 b.n ca <__do_global_dtors_aux+0x16>
+ c8: bf00 nop
+ ca: 2301 movs r3, #1
+ cc: 7023 strb r3, [r4, #0]
+ ce: bd10 pop {r4, pc}
+ d0: 200000b0 .word 0x200000b0
+ d4: 00000000 .word 0x00000000
+ d8: 00002f38 .word 0x00002f38
+
+000000dc <frame_dummy>:
+ dc: 4b08 ldr r3, [pc, #32] ; (100 <frame_dummy+0x24>)
+ de: b510 push {r4, lr}
+ e0: 2b00 cmp r3, #0
+ e2: d003 beq.n ec <frame_dummy+0x10>
+ e4: 4907 ldr r1, [pc, #28] ; (104 <frame_dummy+0x28>)
+ e6: 4808 ldr r0, [pc, #32] ; (108 <frame_dummy+0x2c>)
+ e8: e000 b.n ec <frame_dummy+0x10>
+ ea: bf00 nop
+ ec: 4807 ldr r0, [pc, #28] ; (10c <frame_dummy+0x30>)
+ ee: 6803 ldr r3, [r0, #0]
+ f0: 2b00 cmp r3, #0
+ f2: d100 bne.n f6 <frame_dummy+0x1a>
+ f4: bd10 pop {r4, pc}
+ f6: 4b06 ldr r3, [pc, #24] ; (110 <frame_dummy+0x34>)
+ f8: 2b00 cmp r3, #0
+ fa: d0fb beq.n f4 <frame_dummy+0x18>
+ fc: 4798 blx r3
+ fe: e7f9 b.n f4 <frame_dummy+0x18>
+ 100: 00000000 .word 0x00000000
+ 104: 200000b4 .word 0x200000b4
+ 108: 00002f38 .word 0x00002f38
+ 10c: 200000ac .word 0x200000ac
+ 110: 00000000 .word 0x00000000
+
+00000114 <setup>:
+#endif
+
+
+void setup() {
+
+ SerialMonitorInterface.begin(115200);
+ 114: 21e1 movs r1, #225 ; 0xe1
+void setup() {
+ 116: b510 push {r4, lr}
+ SerialMonitorInterface.begin(115200);
+ 118: 0249 lsls r1, r1, #9
+ 11a: 4805 ldr r0, [pc, #20] ; (130 <setup+0x1c>)
+ 11c: f000 fc28 bl 970 <_ZN7Serial_5beginEm>
+
+ // Initialize Wireling
+// Wireling.begin();
+// Wireling.selectPort(0);
+
+ analogWriteResolution(10); // Change the DAC resolution to 10-bits
+ 120: 200a movs r0, #10
+ 122: f001 fd05 bl 1b30 <analogWriteResolution>
+ analogWrite(A0, 0); // Initialize Dac to Zero
+ 126: 2100 movs r1, #0
+ 128: 200e movs r0, #14
+ 12a: f001 fd39 bl 1ba0 <analogWrite>
+
+}
+ 12e: bd10 pop {r4, pc}
+ 130: 200000d4 .word 0x200000d4
+
+00000134 <loop>:
+
+void loop() {
+ 134: b510 push {r4, lr}
+ int output;
+ //static float x = 270; // Current degrees for sine wave (initially 270 so that
+ // the sine wave is initially zero).
+
+ // output = (int) (512.0 * sin(0.017453 * x) + 512); // Sine Wave
+ if (SerialMonitorInterface.available()> -1) {
+ 136: 4c08 ldr r4, [pc, #32] ; (158 <loop+0x24>)
+ 138: 0020 movs r0, r4
+ 13a: f000 fb8b bl 854 <_ZN7Serial_9availableEv>
+ 13e: 2800 cmp r0, #0
+ 140: db08 blt.n 154 <loop+0x20>
+ output = SerialMonitorInterface.parseInt();
+ 142: 2100 movs r1, #0
+ 144: 2201 movs r2, #1
+ 146: 0020 movs r0, r4
+ 148: f000 fa06 bl 558 <_ZN6Stream8parseIntE13LookaheadModec>
+ 14c: 0001 movs r1, r0
+
+ analogWrite(A0, output);
+ 14e: 200e movs r0, #14
+ 150: f001 fd26 bl 1ba0 <analogWrite>
+ //x += 0.35;
+ //if(x>=360.0) x -= 360.0;
+
+
+ //delay(1);
+}
+ 154: bd10 pop {r4, pc}
+ 156: 46c0 nop ; (mov r8, r8)
+ 158: 200000d4 .word 0x200000d4
+
+0000015c <Dummy_Handler>:
+
+/* Default empty handler */
+void Dummy_Handler(void)
+{
+#if defined DEBUG
+ __BKPT(3);
+ 15c: be03 bkpt 0x0003
+ 15e: e7fe b.n 15e <Dummy_Handler+0x2>
+
+00000160 <USB_Handler>:
+
+static void (*usb_isr)(void) = NULL;
+
+void USB_Handler(void)
+{
+ if (usb_isr)
+ 160: 4b03 ldr r3, [pc, #12] ; (170 <USB_Handler+0x10>)
+{
+ 162: b510 push {r4, lr}
+ if (usb_isr)
+ 164: 681b ldr r3, [r3, #0]
+ 166: 2b00 cmp r3, #0
+ 168: d000 beq.n 16c <USB_Handler+0xc>
+ usb_isr();
+ 16a: 4798 blx r3
+}
+ 16c: bd10 pop {r4, pc}
+ 16e: 46c0 nop ; (mov r8, r8)
+ 170: 200000cc .word 0x200000cc
+
+00000174 <Reset_Handler>:
+{
+ 174: b570 push {r4, r5, r6, lr}
+ if ((&__data_start__ != &__data_end__) && (pSrc != pDest)) {
+ 176: 490f ldr r1, [pc, #60] ; (1b4 <Reset_Handler+0x40>)
+ 178: 4c0f ldr r4, [pc, #60] ; (1b8 <Reset_Handler+0x44>)
+ 17a: 42a1 cmp r1, r4
+ 17c: d104 bne.n 188 <Reset_Handler+0x14>
+ SystemInit();
+ 17e: f000 f8fd bl 37c <SystemInit>
+ main();
+ 182: f000 f88d bl 2a0 <main>
+ 186: e7fe b.n 186 <Reset_Handler+0x12>
+ if ((&__data_start__ != &__data_end__) && (pSrc != pDest)) {
+ 188: 4d0c ldr r5, [pc, #48] ; (1bc <Reset_Handler+0x48>)
+ 18a: 2300 movs r3, #0
+ 18c: 428d cmp r5, r1
+ 18e: d0f6 beq.n 17e <Reset_Handler+0xa>
+ 190: 18ca adds r2, r1, r3
+ 192: 18e8 adds r0, r5, r3
+ for (; pDest < &__data_end__; pDest++, pSrc++)
+ 194: 42a2 cmp r2, r4
+ 196: d305 bcc.n 1a4 <Reset_Handler+0x30>
+ if ((&__data_start__ != &__data_end__) && (pSrc != pDest)) {
+ 198: 4290 cmp r0, r2
+ 19a: d0f0 beq.n 17e <Reset_Handler+0xa>
+ 19c: 4b08 ldr r3, [pc, #32] ; (1c0 <Reset_Handler+0x4c>)
+ for (pDest = &__bss_start__; pDest < &__bss_end__; pDest++)
+ 19e: 4909 ldr r1, [pc, #36] ; (1c4 <Reset_Handler+0x50>)
+ *pDest = 0;
+ 1a0: 2200 movs r2, #0
+ 1a2: e004 b.n 1ae <Reset_Handler+0x3a>
+ *pDest = *pSrc;
+ 1a4: 6800 ldr r0, [r0, #0]
+ 1a6: 3304 adds r3, #4
+ 1a8: 6010 str r0, [r2, #0]
+ 1aa: e7f1 b.n 190 <Reset_Handler+0x1c>
+ *pDest = 0;
+ 1ac: c304 stmia r3!, {r2}
+ for (pDest = &__bss_start__; pDest < &__bss_end__; pDest++)
+ 1ae: 428b cmp r3, r1
+ 1b0: d3fc bcc.n 1ac <Reset_Handler+0x38>
+ 1b2: e7e4 b.n 17e <Reset_Handler+0xa>
+ 1b4: 20000000 .word 0x20000000
+ 1b8: 200000b0 .word 0x200000b0
+ 1bc: 00002f3c .word 0x00002f3c
+ 1c0: 200000b0 .word 0x200000b0
+ 1c4: 20000ba0 .word 0x20000ba0
+
+000001c8 <SysTick_Handler>:
+{
+ 1c8: b510 push {r4, lr}
+ if (sysTickHook())
+ 1ca: f000 f866 bl 29a <sysTickHook>
+ 1ce: 2800 cmp r0, #0
+ 1d0: d101 bne.n 1d6 <SysTick_Handler+0xe>
+ SysTick_DefaultHandler();
+ 1d2: f000 f857 bl 284 <SysTick_DefaultHandler>
+}
+ 1d6: bd10 pop {r4, pc}
+
+000001d8 <USB_SetHandler>:
+
+void USB_SetHandler(void (*new_usb_isr)(void))
+{
+ usb_isr = new_usb_isr;
+ 1d8: 4b01 ldr r3, [pc, #4] ; (1e0 <USB_SetHandler+0x8>)
+ 1da: 6018 str r0, [r3, #0]
+}
+ 1dc: 4770 bx lr
+ 1de: 46c0 nop ; (mov r8, r8)
+ 1e0: 200000cc .word 0x200000cc
+
+000001e4 <millis>:
+static volatile uint32_t _ulTickCount=0 ;
+
+unsigned long millis( void )
+{
+// todo: ensure no interrupts
+ return _ulTickCount ;
+ 1e4: 4b01 ldr r3, [pc, #4] ; (1ec <millis+0x8>)
+ 1e6: 6818 ldr r0, [r3, #0]
+}
+ 1e8: 4770 bx lr
+ 1ea: 46c0 nop ; (mov r8, r8)
+ 1ec: 200000d0 .word 0x200000d0
+
+000001f0 <micros>:
+// Interrupt-compatible version of micros
+// Theory: repeatedly take readings of SysTick counter, millis counter and SysTick interrupt pending flag.
+// When it appears that millis counter and pending is stable and SysTick hasn't rolled over, use these
+// values to calculate micros. If there is a pending SysTick, add one to the millis counter in the calculation.
+unsigned long micros( void )
+{
+ 1f0: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr}
+ uint32_t pend, pend2;
+ uint32_t count, count2;
+
+ ticks2 = SysTick->VAL;
+ pend2 = !!(SCB->ICSR & SCB_ICSR_PENDSTSET_Msk) ;
+ count2 = _ulTickCount ;
+ 1f2: 4813 ldr r0, [pc, #76] ; (240 <micros+0x50>)
+ pend2 = !!(SCB->ICSR & SCB_ICSR_PENDSTSET_Msk) ;
+ 1f4: 2201 movs r2, #1
+ count2 = _ulTickCount ;
+ 1f6: 4684 mov ip, r0
+ ticks2 = SysTick->VAL;
+ 1f8: 4912 ldr r1, [pc, #72] ; (244 <micros+0x54>)
+ pend2 = !!(SCB->ICSR & SCB_ICSR_PENDSTSET_Msk) ;
+ 1fa: 4c13 ldr r4, [pc, #76] ; (248 <micros+0x58>)
+ ticks2 = SysTick->VAL;
+ 1fc: 688e ldr r6, [r1, #8]
+ pend2 = !!(SCB->ICSR & SCB_ICSR_PENDSTSET_Msk) ;
+ 1fe: 6863 ldr r3, [r4, #4]
+ count2 = _ulTickCount ;
+ 200: 6805 ldr r5, [r0, #0]
+ pend2 = !!(SCB->ICSR & SCB_ICSR_PENDSTSET_Msk) ;
+ 202: 0e9b lsrs r3, r3, #26
+ 204: 4013 ands r3, r2
+ {
+ ticks=ticks2;
+ pend=pend2;
+ count=count2;
+ ticks2 = SysTick->VAL;
+ pend2 = !!(SCB->ICSR & SCB_ICSR_PENDSTSET_Msk) ;
+ 206: 9201 str r2, [sp, #4]
+ ticks2 = SysTick->VAL;
+ 208: 6888 ldr r0, [r1, #8]
+ pend2 = !!(SCB->ICSR & SCB_ICSR_PENDSTSET_Msk) ;
+ 20a: 6862 ldr r2, [r4, #4]
+ 20c: 9f01 ldr r7, [sp, #4]
+ 20e: 0e92 lsrs r2, r2, #26
+ 210: 403a ands r2, r7
+ count2 = _ulTickCount ;
+ 212: 4667 mov r7, ip
+ 214: 683f ldr r7, [r7, #0]
+ } while ((pend != pend2) || (count != count2) || (ticks < ticks2));
+ 216: 4293 cmp r3, r2
+ 218: d10e bne.n 238 <micros+0x48>
+ 21a: 42bd cmp r5, r7
+ 21c: d10c bne.n 238 <micros+0x48>
+ 21e: 4286 cmp r6, r0
+ 220: d30a bcc.n 238 <micros+0x48>
+
+ return ((count+pend) * 1000) + (((SysTick->LOAD - ticks)*(1048576/(VARIANT_MCK/1000000)))>>20) ;
+ 222: 195b adds r3, r3, r5
+ 224: 25fa movs r5, #250 ; 0xfa
+ 226: 6848 ldr r0, [r1, #4]
+ 228: 00ad lsls r5, r5, #2
+ 22a: 1b86 subs r6, r0, r6
+ 22c: 4807 ldr r0, [pc, #28] ; (24c <micros+0x5c>)
+ 22e: 436b muls r3, r5
+ 230: 4370 muls r0, r6
+ 232: 0d00 lsrs r0, r0, #20
+ 234: 18c0 adds r0, r0, r3
+ // this is an optimization to turn a runtime division into two compile-time divisions and
+ // a runtime multiplication and shift, saving a few cycles
+}
+ 236: bdfe pop {r1, r2, r3, r4, r5, r6, r7, pc}
+{
+ 238: 003d movs r5, r7
+ 23a: 0013 movs r3, r2
+ 23c: 0006 movs r6, r0
+ 23e: e7e3 b.n 208 <micros+0x18>
+ 240: 200000d0 .word 0x200000d0
+ 244: e000e010 .word 0xe000e010
+ 248: e000ed00 .word 0xe000ed00
+ 24c: 00005555 .word 0x00005555
+
+00000250 <delay>:
+
+void delay( unsigned long ms )
+{
+ 250: b570 push {r4, r5, r6, lr}
+ 252: 1e04 subs r4, r0, #0
+ if (ms == 0)
+ 254: d010 beq.n 278 <delay+0x28>
+ {
+ return;
+ }
+
+ uint32_t start = micros();
+ 256: f7ff ffcb bl 1f0 <micros>
+ 25a: 0005 movs r5, r0
+
+ while (ms > 0)
+ {
+ yield();
+ 25c: f000 f81c bl 298 <yield>
+ while (ms > 0 && (micros() - start) >= 1000)
+ 260: f7ff ffc6 bl 1f0 <micros>
+ 264: 4b05 ldr r3, [pc, #20] ; (27c <delay+0x2c>)
+ 266: 1b40 subs r0, r0, r5
+ 268: 4298 cmp r0, r3
+ 26a: d9f7 bls.n 25c <delay+0xc>
+ {
+ ms--;
+ start += 1000;
+ 26c: 23fa movs r3, #250 ; 0xfa
+ ms--;
+ 26e: 3c01 subs r4, #1
+ start += 1000;
+ 270: 009b lsls r3, r3, #2
+ 272: 18ed adds r5, r5, r3
+ while (ms > 0 && (micros() - start) >= 1000)
+ 274: 2c00 cmp r4, #0
+ 276: d1f3 bne.n 260 <delay+0x10>
+ }
+ }
+}
+ 278: bd70 pop {r4, r5, r6, pc}
+ 27a: 46c0 nop ; (mov r8, r8)
+ 27c: 000003e7 .word 0x000003e7
+
+00000280 <resetExternalChip>:
+
+void initiateReset(int ms);
+void tickReset();
+void cancelReset();
+
+ __attribute__ ((weak)) void resetExternalChip() {};
+ 280: 4770 bx lr
+ ...
+
+00000284 <SysTick_DefaultHandler>:
+
+#include "Reset.h" // for tickReset()
+
+void SysTick_DefaultHandler(void)
+{
+ 284: b510 push {r4, lr}
+ // Increment tick count each ms
+ _ulTickCount++;
+ 286: 4a03 ldr r2, [pc, #12] ; (294 <SysTick_DefaultHandler+0x10>)
+ 288: 6813 ldr r3, [r2, #0]
+ 28a: 3301 adds r3, #1
+ 28c: 6013 str r3, [r2, #0]
+ tickReset();
+ 28e: f000 f839 bl 304 <tickReset>
+}
+ 292: bd10 pop {r4, pc}
+ 294: 200000d0 .word 0x200000d0
+
+00000298 <yield>:
+ * Its defined as a weak symbol and it can be redefined to implement a
+ * real cooperative scheduler.
+ */
+static void __empty() {
+ // Empty
+}
+ 298: 4770 bx lr
+
+0000029a <sysTickHook>:
+ * handler provided by Arduino.
+ */
+static int __false() {
+ // Return false
+ return 0;
+}
+ 29a: 2000 movs r0, #0
+ 29c: 4770 bx lr
+
+0000029e <_Z11initVariantv>:
+#include "Arduino.h"
+
+// Weak empty variant initialization function.
+// May be redefined by variant files.
+void initVariant() __attribute__((weak));
+void initVariant() { }
+ 29e: 4770 bx lr
+
+000002a0 <main>:
+
+/*
+ * \brief Main entry point of Arduino application
+ */
+int main( void )
+{
+ 2a0: b510 push {r4, lr}
+ init();
+ 2a2: f001 fbc3 bl 1a2c <init>
+
+ __libc_init_array();
+ 2a6: f002 fa7f bl 27a8 <__libc_init_array>
+
+ initVariant();
+ 2aa: f7ff fff8 bl 29e <_Z11initVariantv>
+
+ delay(1);
+ 2ae: 2001 movs r0, #1
+ 2b0: f7ff ffce bl 250 <delay>
+#if defined(USBCON)
+ #if !defined(USB_NO_INIT)
+ USBDevice.init();
+ 2b4: 4c08 ldr r4, [pc, #32] ; (2d8 <main+0x38>)
+ 2b6: 0020 movs r0, r4
+ 2b8: f000 fe66 bl f88 <_ZN14USBDeviceClass4initEv>
+ USBDevice.attach();
+ 2bc: 0020 movs r0, r4
+ 2be: f000 fefd bl 10bc <_ZN14USBDeviceClass6attachEv>
+ #endif
+#endif
+
+ setup();
+ 2c2: f7ff ff27 bl 114 <setup>
+
+ for (;;)
+ {
+ loop();
+ 2c6: f7ff ff35 bl 134 <loop>
+ if (serialEventRun) serialEventRun();
+ 2ca: 4b04 ldr r3, [pc, #16] ; (2dc <main+0x3c>)
+ 2cc: 2b00 cmp r3, #0
+ 2ce: d0fa beq.n 2c6 <main+0x26>
+ 2d0: e000 b.n 2d4 <main+0x34>
+ 2d2: bf00 nop
+ 2d4: e7f7 b.n 2c6 <main+0x26>
+ 2d6: 46c0 nop ; (mov r8, r8)
+ 2d8: 2000013c .word 0x2000013c
+ 2dc: 00000000 .word 0x00000000
+
+000002e0 <initiateReset>:
+ while (true);
+}
+
+static int ticks = -1;
+
+void initiateReset(int _ticks) {
+ 2e0: b510 push {r4, lr}
+ 2e2: 0004 movs r4, r0
+ resetExternalChip();
+ 2e4: f7ff ffcc bl 280 <resetExternalChip>
+ ticks = _ticks;
+ 2e8: 4b01 ldr r3, [pc, #4] ; (2f0 <initiateReset+0x10>)
+ 2ea: 601c str r4, [r3, #0]
+}
+ 2ec: bd10 pop {r4, pc}
+ 2ee: 46c0 nop ; (mov r8, r8)
+ 2f0: 20000000 .word 0x20000000
+
+000002f4 <cancelReset>:
+
+void cancelReset() {
+ ticks = -1;
+ 2f4: 2201 movs r2, #1
+ 2f6: 4b02 ldr r3, [pc, #8] ; (300 <cancelReset+0xc>)
+ 2f8: 4252 negs r2, r2
+ 2fa: 601a str r2, [r3, #0]
+}
+ 2fc: 4770 bx lr
+ 2fe: 46c0 nop ; (mov r8, r8)
+ 300: 20000000 .word 0x20000000
+
+00000304 <tickReset>:
+
+void tickReset() {
+ if (ticks == -1)
+ 304: 4a16 ldr r2, [pc, #88] ; (360 <tickReset+0x5c>)
+void tickReset() {
+ 306: b510 push {r4, lr}
+ if (ticks == -1)
+ 308: 6813 ldr r3, [r2, #0]
+ 30a: 1c59 adds r1, r3, #1
+ 30c: d027 beq.n 35e <tickReset+0x5a>
+ return;
+ ticks--;
+ 30e: 3b01 subs r3, #1
+ 310: 6013 str r3, [r2, #0]
+ if (ticks == 0)
+ 312: 2b00 cmp r3, #0
+ 314: d123 bne.n 35e <tickReset+0x5a>
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_irq(void)
+{
+ __ASM volatile ("cpsid i" : : : "memory");
+ 316: b672 cpsid i
+ if (APP_START < (0x200 + 4)) {
+ 318: 4b12 ldr r3, [pc, #72] ; (364 <tickReset+0x60>)
+ 31a: 4a13 ldr r2, [pc, #76] ; (368 <tickReset+0x64>)
+ 31c: 3304 adds r3, #4
+ 31e: 4293 cmp r3, r2
+ 320: d808 bhi.n 334 <tickReset+0x30>
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+__STATIC_FORCEINLINE void __DSB(void)
+{
+ __ASM volatile ("dsb 0xF":::"memory");
+ 322: f3bf 8f4f dsb sy
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ 326: 4a11 ldr r2, [pc, #68] ; (36c <tickReset+0x68>)
+ 328: 4b11 ldr r3, [pc, #68] ; (370 <tickReset+0x6c>)
+ 32a: 60da str r2, [r3, #12]
+ 32c: f3bf 8f4f dsb sy
+ SCB_AIRCR_SYSRESETREQ_Msk);
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ 330: 46c0 nop ; (mov r8, r8)
+ 332: e7fd b.n 330 <tickReset+0x2c>
+ return NVMCTRL->INTFLAG.reg & NVMCTRL_INTFLAG_READY;
+ 334: 4a0f ldr r2, [pc, #60] ; (374 <tickReset+0x70>)
+ while (!nvmReady())
+ 336: 2101 movs r1, #1
+ 338: 0010 movs r0, r2
+ return NVMCTRL->INTFLAG.reg & NVMCTRL_INTFLAG_READY;
+ 33a: 7d14 ldrb r4, [r2, #20]
+ while (!nvmReady())
+ 33c: 420c tst r4, r1
+ 33e: d0fc beq.n 33a <tickReset+0x36>
+ NVMCTRL->STATUS.reg |= NVMCTRL_STATUS_MASK;
+ 340: 2120 movs r1, #32
+ 342: 8b14 ldrh r4, [r2, #24]
+ 344: 31ff adds r1, #255 ; 0xff
+ NVMCTRL->ADDR.reg = (uintptr_t)&NVM_MEMORY[APP_START / 4];
+ 346: 089b lsrs r3, r3, #2
+ 348: 005b lsls r3, r3, #1
+ NVMCTRL->STATUS.reg |= NVMCTRL_STATUS_MASK;
+ 34a: 4321 orrs r1, r4
+ 34c: 8311 strh r1, [r2, #24]
+ NVMCTRL->ADDR.reg = (uintptr_t)&NVM_MEMORY[APP_START / 4];
+ 34e: 61d3 str r3, [r2, #28]
+ NVMCTRL->CTRLA.reg = NVMCTRL_CTRLA_CMD_ER | NVMCTRL_CTRLA_CMDEX_KEY;
+ 350: 4b09 ldr r3, [pc, #36] ; (378 <tickReset+0x74>)
+ 352: 8013 strh r3, [r2, #0]
+ while (!nvmReady())
+ 354: 2301 movs r3, #1
+ return NVMCTRL->INTFLAG.reg & NVMCTRL_INTFLAG_READY;
+ 356: 7d02 ldrb r2, [r0, #20]
+ while (!nvmReady())
+ 358: 421a tst r2, r3
+ 35a: d0fc beq.n 356 <tickReset+0x52>
+ 35c: e7e1 b.n 322 <tickReset+0x1e>
+ banzai();
+}
+ 35e: bd10 pop {r4, pc}
+ 360: 20000000 .word 0x20000000
+ 364: 00000000 .word 0x00000000
+ 368: 00000203 .word 0x00000203
+ 36c: 05fa0004 .word 0x05fa0004
+ 370: e000ed00 .word 0xe000ed00
+ 374: 41004000 .word 0x41004000
+ 378: ffffa502 .word 0xffffa502
+
+0000037c <SystemInit>:
+#define GENERIC_CLOCK_MULTIPLEXER_DFLL48M (0u)
+
+void SystemInit( void )
+{
+ /* Set 1 Flash Wait State for 48MHz, cf tables 20.9 and 35.27 in SAMD21 Datasheet */
+ NVMCTRL->CTRLB.bit.RWS = NVMCTRL_CTRLB_RWS_HALF_Val ;
+ 37c: 221e movs r2, #30
+{
+ 37e: b570 push {r4, r5, r6, lr}
+ NVMCTRL->CTRLB.bit.RWS = NVMCTRL_CTRLB_RWS_HALF_Val ;
+ 380: 4846 ldr r0, [pc, #280] ; (49c <SystemInit+0x120>)
+
+ /* Turn on the digital interface clock */
+ PM->APBAMASK.reg |= PM_APBAMASK_GCLK ;
+ 382: 4947 ldr r1, [pc, #284] ; (4a0 <SystemInit+0x124>)
+ NVMCTRL->CTRLB.bit.RWS = NVMCTRL_CTRLB_RWS_HALF_Val ;
+ 384: 6843 ldr r3, [r0, #4]
+ 386: 4393 bics r3, r2
+ 388: 3a1c subs r2, #28
+ 38a: 4313 orrs r3, r2
+ 38c: 6043 str r3, [r0, #4]
+ PM->APBAMASK.reg |= PM_APBAMASK_GCLK ;
+ 38e: 2308 movs r3, #8
+ 390: 698c ldr r4, [r1, #24]
+ 392: 4323 orrs r3, r4
+#else // has crystal
+
+ /* ----------------------------------------------------------------------------------------------
+ * 1) Enable XOSC32K clock (External on-board 32.768Hz oscillator)
+ */
+ SYSCTRL->XOSC32K.reg = SYSCTRL_XOSC32K_STARTUP( 0x3u ) | /* cf table 15.10 of product datasheet in chapter 15.8.6 */
+ 394: 24c3 movs r4, #195 ; 0xc3
+ PM->APBAMASK.reg |= PM_APBAMASK_GCLK ;
+ 396: 618b str r3, [r1, #24]
+ SYSCTRL->XOSC32K.reg = SYSCTRL_XOSC32K_STARTUP( 0x3u ) | /* cf table 15.10 of product datasheet in chapter 15.8.6 */
+ 398: 4b42 ldr r3, [pc, #264] ; (4a4 <SystemInit+0x128>)
+ 39a: 00a4 lsls r4, r4, #2
+ 39c: 829c strh r4, [r3, #20]
+ SYSCTRL_XOSC32K_XTALEN | SYSCTRL_XOSC32K_EN32K ;
+ SYSCTRL->XOSC32K.bit.ENABLE = 1 ; /* separate call, as described in chapter 15.6.3 */
+ 39e: 8a9c ldrh r4, [r3, #20]
+ 3a0: 4314 orrs r4, r2
+ 3a2: 829c strh r4, [r3, #20]
+
+ while ( (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_XOSC32KRDY) == 0 )
+ 3a4: 68dc ldr r4, [r3, #12]
+ 3a6: 4214 tst r4, r2
+ 3a8: d0fc beq.n 3a4 <SystemInit+0x28>
+
+ /* Software reset the module to ensure it is re-initialized correctly */
+ /* Note: Due to synchronization, there is a delay from writing CTRL.SWRST until the reset is complete.
+ * CTRL.SWRST and STATUS.SYNCBUSY will both be cleared when the reset is complete, as described in chapter 13.8.1
+ */
+ GCLK->CTRL.reg = GCLK_CTRL_SWRST ;
+ 3aa: 2401 movs r4, #1
+ 3ac: 4a3e ldr r2, [pc, #248] ; (4a8 <SystemInit+0x12c>)
+ 3ae: 7014 strb r4, [r2, #0]
+
+ while ( (GCLK->CTRL.reg & GCLK_CTRL_SWRST) && (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY) )
+ 3b0: 7815 ldrb r5, [r2, #0]
+ 3b2: 4225 tst r5, r4
+ 3b4: d003 beq.n 3be <SystemInit+0x42>
+ 3b6: 7855 ldrb r5, [r2, #1]
+ 3b8: b26d sxtb r5, r5
+ 3ba: 2d00 cmp r5, #0
+ 3bc: dbf8 blt.n 3b0 <SystemInit+0x34>
+ }
+
+ /* ----------------------------------------------------------------------------------------------
+ * 2) Put XOSC32K as source of Generic Clock Generator 1
+ */
+ GCLK->GENDIV.reg = GCLK_GENDIV_ID( GENERIC_CLOCK_GENERATOR_XOSC32K ) ; // Generic Clock Generator 1
+ 3be: 2401 movs r4, #1
+ 3c0: 6094 str r4, [r2, #8]
+
+ while ( GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY )
+ 3c2: 7854 ldrb r4, [r2, #1]
+ 3c4: b264 sxtb r4, r4
+ 3c6: 2c00 cmp r4, #0
+ 3c8: dbfb blt.n 3c2 <SystemInit+0x46>
+ {
+ /* Wait for synchronization */
+ }
+
+ /* Write Generic Clock Generator 1 configuration */
+ GCLK->GENCTRL.reg = GCLK_GENCTRL_ID( GENERIC_CLOCK_GENERATOR_OSC32K ) | // Generic Clock Generator 1
+ 3ca: 4c38 ldr r4, [pc, #224] ; (4ac <SystemInit+0x130>)
+ 3cc: 6054 str r4, [r2, #4]
+ GCLK_GENCTRL_SRC_XOSC32K | // Selected source is External 32KHz Oscillator
+#endif
+// GCLK_GENCTRL_OE | // Output clock to a pin for tests
+ GCLK_GENCTRL_GENEN ;
+
+ while ( GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY )
+ 3ce: 7854 ldrb r4, [r2, #1]
+ 3d0: b264 sxtb r4, r4
+ 3d2: 2c00 cmp r4, #0
+ 3d4: dbfb blt.n 3ce <SystemInit+0x52>
+ }
+
+ /* ----------------------------------------------------------------------------------------------
+ * 3) Put Generic Clock Generator 1 as source for Generic Clock Multiplexer 0 (DFLL48M reference)
+ */
+ GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID( GENERIC_CLOCK_MULTIPLEXER_DFLL48M ) | // Generic Clock Multiplexer 0
+ 3d6: 2482 movs r4, #130 ; 0x82
+ 3d8: 01e4 lsls r4, r4, #7
+ 3da: 8054 strh r4, [r2, #2]
+ GCLK_CLKCTRL_GEN_GCLK1 | // Generic Clock Generator 1 is source
+ GCLK_CLKCTRL_CLKEN ;
+
+ while ( GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY )
+ 3dc: 7854 ldrb r4, [r2, #1]
+ 3de: b264 sxtb r4, r4
+ 3e0: 2c00 cmp r4, #0
+ 3e2: dbfb blt.n 3dc <SystemInit+0x60>
+ */
+
+ /* DFLL Configuration in Closed Loop mode, cf product datasheet chapter 15.6.7.1 - Closed-Loop Operation */
+
+ /* Remove the OnDemand mode, Bug http://avr32.icgroup.norway.atmel.com/bugzilla/show_bug.cgi?id=9905 */
+ SYSCTRL->DFLLCTRL.reg = SYSCTRL_DFLLCTRL_ENABLE;
+ 3e4: 2402 movs r4, #2
+ 3e6: 849c strh r4, [r3, #36] ; 0x24
+
+ while ( (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY) == 0 )
+ 3e8: 340e adds r4, #14
+ 3ea: 68dd ldr r5, [r3, #12]
+ 3ec: 4225 tst r5, r4
+ 3ee: d0fc beq.n 3ea <SystemInit+0x6e>
+ {
+ /* Wait for synchronization */
+ }
+
+ SYSCTRL->DFLLMUL.reg = SYSCTRL_DFLLMUL_CSTEP( 31 ) | // Coarse step is 31, half of the max value
+ 3f0: 4c2f ldr r4, [pc, #188] ; (4b0 <SystemInit+0x134>)
+ 3f2: 62dc str r4, [r3, #44] ; 0x2c
+ SYSCTRL_DFLLMUL_FSTEP( 511 ) | // Fine step is 511, half of the max value
+ SYSCTRL_DFLLMUL_MUL( (VARIANT_MCK + VARIANT_MAINOSC/2) / VARIANT_MAINOSC ) ; // External 32KHz is the reference
+
+ while ( (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY) == 0 )
+ 3f4: 2410 movs r4, #16
+ 3f6: 68dd ldr r5, [r3, #12]
+ 3f8: 4225 tst r5, r4
+ 3fa: d0fc beq.n 3f6 <SystemInit+0x7a>
+ SYSCTRL->DFLLCTRL.reg |= SYSCTRL_DFLLCTRL_ENABLE ;
+
+#else // has crystal
+
+ /* Write full configuration to DFLL control register */
+ SYSCTRL->DFLLCTRL.reg |= SYSCTRL_DFLLCTRL_MODE | /* Enable the closed loop mode */
+ 3fc: 8c9d ldrh r5, [r3, #36] ; 0x24
+ 3fe: 4c2d ldr r4, [pc, #180] ; (4b4 <SystemInit+0x138>)
+ 400: 432c orrs r4, r5
+ 402: 849c strh r4, [r3, #36] ; 0x24
+ SYSCTRL_DFLLCTRL_WAITLOCK |
+ SYSCTRL_DFLLCTRL_QLDIS ; /* Disable Quick lock */
+
+ while ( (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY) == 0 )
+ 404: 2410 movs r4, #16
+ 406: 68dd ldr r5, [r3, #12]
+ 408: 4225 tst r5, r4
+ 40a: d0fc beq.n 406 <SystemInit+0x8a>
+ {
+ /* Wait for synchronization */
+ }
+
+ /* Enable the DFLL */
+ SYSCTRL->DFLLCTRL.reg |= SYSCTRL_DFLLCTRL_ENABLE ;
+ 40c: 2402 movs r4, #2
+ 40e: 8c9d ldrh r5, [r3, #36] ; 0x24
+
+ while ( (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLLCKC) == 0 ||
+ 410: 2680 movs r6, #128 ; 0x80
+ SYSCTRL->DFLLCTRL.reg |= SYSCTRL_DFLLCTRL_ENABLE ;
+ 412: 432c orrs r4, r5
+ 414: 849c strh r4, [r3, #36] ; 0x24
+ (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLLCKF) == 0 )
+ 416: 2440 movs r4, #64 ; 0x40
+ while ( (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLLCKC) == 0 ||
+ 418: 68dd ldr r5, [r3, #12]
+ 41a: 4235 tst r5, r6
+ 41c: d0fc beq.n 418 <SystemInit+0x9c>
+ (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLLCKF) == 0 )
+ 41e: 68dd ldr r5, [r3, #12]
+ while ( (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLLCKC) == 0 ||
+ 420: 4225 tst r5, r4
+ 422: d0f9 beq.n 418 <SystemInit+0x9c>
+ /* Wait for locks flags */
+ }
+
+#endif
+
+ while ( (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY) == 0 )
+ 424: 2410 movs r4, #16
+ 426: 68dd ldr r5, [r3, #12]
+ 428: 4225 tst r5, r4
+ 42a: d0fc beq.n 426 <SystemInit+0xaa>
+ }
+
+ /* ----------------------------------------------------------------------------------------------
+ * 5) Switch Generic Clock Generator 0 to DFLL48M. CPU will run at 48MHz.
+ */
+ GCLK->GENDIV.reg = GCLK_GENDIV_ID( GENERIC_CLOCK_GENERATOR_MAIN ) ; // Generic Clock Generator 0
+ 42c: 2400 movs r4, #0
+ 42e: 6094 str r4, [r2, #8]
+
+ while ( GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY )
+ 430: 7854 ldrb r4, [r2, #1]
+ 432: b264 sxtb r4, r4
+ 434: 2c00 cmp r4, #0
+ 436: dbfb blt.n 430 <SystemInit+0xb4>
+ {
+ /* Wait for synchronization */
+ }
+
+ /* Write Generic Clock Generator 0 configuration */
+ GCLK->GENCTRL.reg = GCLK_GENCTRL_ID( GENERIC_CLOCK_GENERATOR_MAIN ) | // Generic Clock Generator 0
+ 438: 4c1f ldr r4, [pc, #124] ; (4b8 <SystemInit+0x13c>)
+ 43a: 6054 str r4, [r2, #4]
+ GCLK_GENCTRL_SRC_DFLL48M | // Selected source is DFLL 48MHz
+// GCLK_GENCTRL_OE | // Output clock to a pin for tests
+ GCLK_GENCTRL_IDC | // Set 50/50 duty cycle
+ GCLK_GENCTRL_GENEN ;
+
+ while ( GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY )
+ 43c: 7854 ldrb r4, [r2, #1]
+ 43e: b264 sxtb r4, r4
+ 440: 2c00 cmp r4, #0
+ 442: dbfb blt.n 43c <SystemInit+0xc0>
+ }
+
+ /* ----------------------------------------------------------------------------------------------
+ * 6) Modify PRESCaler value of OSC8M to have 8MHz
+ */
+ SYSCTRL->OSC8M.bit.PRESC = SYSCTRL_OSC8M_PRESC_0_Val ; //CMSIS 4.5 changed the prescaler defines
+ 444: 6a1c ldr r4, [r3, #32]
+ 446: 4d1d ldr r5, [pc, #116] ; (4bc <SystemInit+0x140>)
+ 448: 402c ands r4, r5
+ SYSCTRL->OSC8M.bit.ONDEMAND = 0 ;
+ 44a: 2580 movs r5, #128 ; 0x80
+ SYSCTRL->OSC8M.bit.PRESC = SYSCTRL_OSC8M_PRESC_0_Val ; //CMSIS 4.5 changed the prescaler defines
+ 44c: 621c str r4, [r3, #32]
+ SYSCTRL->OSC8M.bit.ONDEMAND = 0 ;
+ 44e: 6a1c ldr r4, [r3, #32]
+ 450: 43ac bics r4, r5
+ 452: 621c str r4, [r3, #32]
+
+ /* ----------------------------------------------------------------------------------------------
+ * 7) Put OSC8M as source for Generic Clock Generator 3
+ */
+ GCLK->GENDIV.reg = GCLK_GENDIV_ID( GENERIC_CLOCK_GENERATOR_OSC8M ) ; // Generic Clock Generator 3
+ 454: 2303 movs r3, #3
+ 456: 6093 str r3, [r2, #8]
+
+ /* Write Generic Clock Generator 3 configuration */
+ GCLK->GENCTRL.reg = GCLK_GENCTRL_ID( GENERIC_CLOCK_GENERATOR_OSC8M ) | // Generic Clock Generator 3
+ 458: 4b19 ldr r3, [pc, #100] ; (4c0 <SystemInit+0x144>)
+ 45a: 6053 str r3, [r2, #4]
+ GCLK_GENCTRL_SRC_OSC8M | // Selected source is RC OSC 8MHz (already enabled at reset)
+// GCLK_GENCTRL_OE | // Output clock to a pin for tests
+ GCLK_GENCTRL_GENEN ;
+
+ while ( GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY )
+ 45c: 7853 ldrb r3, [r2, #1]
+ 45e: b25b sxtb r3, r3
+ 460: 2b00 cmp r3, #0
+ 462: dbfb blt.n 45c <SystemInit+0xe0>
+
+ /*
+ * Now that all system clocks are configured, we can set CPU and APBx BUS clocks.
+ * There values are normally the one present after Reset.
+ */
+ PM->CPUSEL.reg = PM_CPUSEL_CPUDIV_DIV1 ;
+ 464: 2300 movs r3, #0
+
+ // ADC Linearity bits 4:0
+ uint32_t linearity = (*((uint32_t *) ADC_FUSES_LINEARITY_0_ADDR) & ADC_FUSES_LINEARITY_0_Msk) >> ADC_FUSES_LINEARITY_0_Pos;
+
+ // ADC Linearity bits 7:5
+ linearity |= ((*((uint32_t *) ADC_FUSES_LINEARITY_1_ADDR) & ADC_FUSES_LINEARITY_1_Msk) >> ADC_FUSES_LINEARITY_1_Pos) << 5;
+ 466: 24ff movs r4, #255 ; 0xff
+ PM->CPUSEL.reg = PM_CPUSEL_CPUDIV_DIV1 ;
+ 468: 720b strb r3, [r1, #8]
+ SystemCoreClock=VARIANT_MCK ;
+ 46a: 4a16 ldr r2, [pc, #88] ; (4c4 <SystemInit+0x148>)
+ PM->APBASEL.reg = PM_APBASEL_APBADIV_DIV1_Val ;
+ 46c: 724b strb r3, [r1, #9]
+ PM->APBBSEL.reg = PM_APBBSEL_APBBDIV_DIV1_Val ;
+ 46e: 728b strb r3, [r1, #10]
+ PM->APBCSEL.reg = PM_APBCSEL_APBCDIV_DIV1_Val ;
+ 470: 72cb strb r3, [r1, #11]
+ SystemCoreClock=VARIANT_MCK ;
+ 472: 4b15 ldr r3, [pc, #84] ; (4c8 <SystemInit+0x14c>)
+ 474: 601a str r2, [r3, #0]
+ uint32_t bias = (*((uint32_t *) ADC_FUSES_BIASCAL_ADDR) & ADC_FUSES_BIASCAL_Msk) >> ADC_FUSES_BIASCAL_Pos;
+ 476: 4b15 ldr r3, [pc, #84] ; (4cc <SystemInit+0x150>)
+ uint32_t linearity = (*((uint32_t *) ADC_FUSES_LINEARITY_0_ADDR) & ADC_FUSES_LINEARITY_0_Msk) >> ADC_FUSES_LINEARITY_0_Pos;
+ 478: 4a15 ldr r2, [pc, #84] ; (4d0 <SystemInit+0x154>)
+ uint32_t bias = (*((uint32_t *) ADC_FUSES_BIASCAL_ADDR) & ADC_FUSES_BIASCAL_Msk) >> ADC_FUSES_BIASCAL_Pos;
+ 47a: 681b ldr r3, [r3, #0]
+ uint32_t linearity = (*((uint32_t *) ADC_FUSES_LINEARITY_0_ADDR) & ADC_FUSES_LINEARITY_0_Msk) >> ADC_FUSES_LINEARITY_0_Pos;
+ 47c: 6811 ldr r1, [r2, #0]
+ uint32_t bias = (*((uint32_t *) ADC_FUSES_BIASCAL_ADDR) & ADC_FUSES_BIASCAL_Msk) >> ADC_FUSES_BIASCAL_Pos;
+ 47e: 069a lsls r2, r3, #26
+ linearity |= ((*((uint32_t *) ADC_FUSES_LINEARITY_1_ADDR) & ADC_FUSES_LINEARITY_1_Msk) >> ADC_FUSES_LINEARITY_1_Pos) << 5;
+ 480: 015b lsls r3, r3, #5
+ uint32_t linearity = (*((uint32_t *) ADC_FUSES_LINEARITY_0_ADDR) & ADC_FUSES_LINEARITY_0_Msk) >> ADC_FUSES_LINEARITY_0_Pos;
+ 482: 0ec9 lsrs r1, r1, #27
+ linearity |= ((*((uint32_t *) ADC_FUSES_LINEARITY_1_ADDR) & ADC_FUSES_LINEARITY_1_Msk) >> ADC_FUSES_LINEARITY_1_Pos) << 5;
+ 484: 4023 ands r3, r4
+ uint32_t bias = (*((uint32_t *) ADC_FUSES_BIASCAL_ADDR) & ADC_FUSES_BIASCAL_Msk) >> ADC_FUSES_BIASCAL_Pos;
+ 486: 0f52 lsrs r2, r2, #29
+
+ ADC->CALIB.reg = ADC_CALIB_BIAS_CAL(bias) | ADC_CALIB_LINEARITY_CAL(linearity);
+ 488: 0212 lsls r2, r2, #8
+ linearity |= ((*((uint32_t *) ADC_FUSES_LINEARITY_1_ADDR) & ADC_FUSES_LINEARITY_1_Msk) >> ADC_FUSES_LINEARITY_1_Pos) << 5;
+ 48a: 430b orrs r3, r1
+ ADC->CALIB.reg = ADC_CALIB_BIAS_CAL(bias) | ADC_CALIB_LINEARITY_CAL(linearity);
+ 48c: 4313 orrs r3, r2
+ 48e: 4a11 ldr r2, [pc, #68] ; (4d4 <SystemInit+0x158>)
+ 490: 8513 strh r3, [r2, #40] ; 0x28
+
+ /*
+ * 9) Disable automatic NVM write operations
+ */
+ NVMCTRL->CTRLB.bit.MANW = 1;
+ 492: 2380 movs r3, #128 ; 0x80
+ 494: 6842 ldr r2, [r0, #4]
+ 496: 4313 orrs r3, r2
+ 498: 6043 str r3, [r0, #4]
+}
+ 49a: bd70 pop {r4, r5, r6, pc}
+ 49c: 41004000 .word 0x41004000
+ 4a0: 40000400 .word 0x40000400
+ 4a4: 40000800 .word 0x40000800
+ 4a8: 40000c00 .word 0x40000c00
+ 4ac: 00010501 .word 0x00010501
+ 4b0: 7dff05b9 .word 0x7dff05b9
+ 4b4: 00000a04 .word 0x00000a04
+ 4b8: 00030700 .word 0x00030700
+ 4bc: fffffcff .word 0xfffffcff
+ 4c0: 00010603 .word 0x00010603
+ 4c4: 02dc6c00 .word 0x02dc6c00
+ 4c8: 20000014 .word 0x20000014
+ 4cc: 00806024 .word 0x00806024
+ 4d0: 00806020 .word 0x00806020
+ 4d4: 42004000 .word 0x42004000
+
+000004d8 <_ZN6Stream9timedPeekEv>:
+ return -1; // -1 indicates timeout
+}
+
+// protected method to peek stream with timeout
+int Stream::timedPeek()
+{
+ 4d8: b510 push {r4, lr}
+ 4da: 0004 movs r4, r0
+ int c;
+ _startMillis = millis();
+ 4dc: f7ff fe82 bl 1e4 <millis>
+ 4e0: 60e0 str r0, [r4, #12]
+ do {
+ c = peek();
+ 4e2: 6823 ldr r3, [r4, #0]
+ 4e4: 0020 movs r0, r4
+ 4e6: 699b ldr r3, [r3, #24]
+ 4e8: 4798 blx r3
+ if (c >= 0) return c;
+ 4ea: 2800 cmp r0, #0
+ 4ec: da08 bge.n 500 <_ZN6Stream9timedPeekEv+0x28>
+ } while(millis() - _startMillis < _timeout);
+ 4ee: f7ff fe79 bl 1e4 <millis>
+ 4f2: 68e3 ldr r3, [r4, #12]
+ 4f4: 1ac0 subs r0, r0, r3
+ do {
+ 4f6: 68a3 ldr r3, [r4, #8]
+ 4f8: 4298 cmp r0, r3
+ 4fa: d3f2 bcc.n 4e2 <_ZN6Stream9timedPeekEv+0xa>
+ return -1; // -1 indicates timeout
+ 4fc: 2001 movs r0, #1
+ 4fe: 4240 negs r0, r0
+}
+ 500: bd10 pop {r4, pc}
+ ...
+
+00000504 <_ZN6Stream13peekNextDigitE13LookaheadModeb>:
+
+// returns peek of the next digit in the stream or -1 if timeout
+// discards non-numeric characters
+int Stream::peekNextDigit(LookaheadMode lookahead, bool detectDecimal)
+{
+ 504: b5f8 push {r3, r4, r5, r6, r7, lr}
+ 506: 0004 movs r4, r0
+ 508: 000d movs r5, r1
+ 50a: 0016 movs r6, r2
+ 50c: 2701 movs r7, #1
+ int c;
+ while (1) {
+ c = timedPeek();
+ 50e: 0020 movs r0, r4
+ 510: f7ff ffe2 bl 4d8 <_ZN6Stream9timedPeekEv>
+
+ if( c < 0 ||
+ 514: 2800 cmp r0, #0
+ 516: db1c blt.n 552 <_ZN6Stream13peekNextDigitE13LookaheadModeb+0x4e>
+ 518: 282d cmp r0, #45 ; 0x2d
+ 51a: d01a beq.n 552 <_ZN6Stream13peekNextDigitE13LookaheadModeb+0x4e>
+ c == '-' ||
+ (c >= '0' && c <= '9') ||
+ 51c: 0003 movs r3, r0
+ 51e: 3b30 subs r3, #48 ; 0x30
+ c == '-' ||
+ 520: 2b09 cmp r3, #9
+ 522: d916 bls.n 552 <_ZN6Stream13peekNextDigitE13LookaheadModeb+0x4e>
+ (c >= '0' && c <= '9') ||
+ 524: 2e00 cmp r6, #0
+ 526: d001 beq.n 52c <_ZN6Stream13peekNextDigitE13LookaheadModeb+0x28>
+ (detectDecimal && c == '.')) return c;
+ 528: 282e cmp r0, #46 ; 0x2e
+ 52a: d012 beq.n 552 <_ZN6Stream13peekNextDigitE13LookaheadModeb+0x4e>
+
+ switch( lookahead ){
+ 52c: 2d01 cmp r5, #1
+ 52e: d00e beq.n 54e <_ZN6Stream13peekNextDigitE13LookaheadModeb+0x4a>
+ 530: 2d02 cmp r5, #2
+ 532: d107 bne.n 544 <_ZN6Stream13peekNextDigitE13LookaheadModeb+0x40>
+ 534: 3809 subs r0, #9
+ 536: 2817 cmp r0, #23
+ 538: d809 bhi.n 54e <_ZN6Stream13peekNextDigitE13LookaheadModeb+0x4a>
+ 53a: 003a movs r2, r7
+ 53c: 4082 lsls r2, r0
+ 53e: 4b05 ldr r3, [pc, #20] ; (554 <_ZN6Stream13peekNextDigitE13LookaheadModeb+0x50>)
+ 540: 421a tst r2, r3
+ 542: d004 beq.n 54e <_ZN6Stream13peekNextDigitE13LookaheadModeb+0x4a>
+ default: return -1; // Fail code.
+ }
+ case SKIP_ALL:
+ break;
+ }
+ read(); // discard non-numeric
+ 544: 6823 ldr r3, [r4, #0]
+ 546: 0020 movs r0, r4
+ 548: 695b ldr r3, [r3, #20]
+ 54a: 4798 blx r3
+ c = timedPeek();
+ 54c: e7df b.n 50e <_ZN6Stream13peekNextDigitE13LookaheadModeb+0xa>
+ default: return -1; // Fail code.
+ 54e: 2001 movs r0, #1
+ 550: 4240 negs r0, r0
+ }
+}
+ 552: bdf8 pop {r3, r4, r5, r6, r7, pc}
+ 554: 00800013 .word 0x00800013
+
+00000558 <_ZN6Stream8parseIntE13LookaheadModec>:
+// lookahead determines how parseInt looks ahead in the stream.
+// See LookaheadMode enumeration at the top of the file.
+// Lookahead is terminated by the first character that is not a valid part of an integer.
+// Once parsing commences, 'ignore' will be skipped in the stream.
+long Stream::parseInt(LookaheadMode lookahead, char ignore)
+{
+ 558: b5f8 push {r3, r4, r5, r6, r7, lr}
+ 55a: 0017 movs r7, r2
+ bool isNegative = false;
+ long value = 0;
+ int c;
+
+ c = peekNextDigit(lookahead, false);
+ 55c: 2200 movs r2, #0
+{
+ 55e: 0005 movs r5, r0
+ // ignore non numeric leading characters
+ if(c < 0)
+ return 0; // zero returned if timeout
+ 560: 2400 movs r4, #0
+ c = peekNextDigit(lookahead, false);
+ 562: f7ff ffcf bl 504 <_ZN6Stream13peekNextDigitE13LookaheadModeb>
+ if(c < 0)
+ 566: 42a0 cmp r0, r4
+ 568: db1c blt.n 5a4 <_ZN6Stream8parseIntE13LookaheadModec+0x4c>
+ 56a: 0026 movs r6, r4
+
+ do{
+ if(c == ignore)
+ 56c: 42b8 cmp r0, r7
+ 56e: d009 beq.n 584 <_ZN6Stream8parseIntE13LookaheadModec+0x2c>
+ ; // ignore this character
+ else if(c == '-')
+ 570: 282d cmp r0, #45 ; 0x2d
+ 572: d019 beq.n 5a8 <_ZN6Stream8parseIntE13LookaheadModec+0x50>
+ isNegative = true;
+ else if(c >= '0' && c <= '9') // is c a digit?
+ 574: 0003 movs r3, r0
+ 576: 3b30 subs r3, #48 ; 0x30
+ 578: 2b09 cmp r3, #9
+ 57a: d803 bhi.n 584 <_ZN6Stream8parseIntE13LookaheadModec+0x2c>
+ value = value * 10 + c - '0';
+ 57c: 230a movs r3, #10
+ 57e: 435c muls r4, r3
+ 580: 1824 adds r4, r4, r0
+ 582: 3c30 subs r4, #48 ; 0x30
+ read(); // consume the character we got with peek
+ 584: 682b ldr r3, [r5, #0]
+ 586: 0028 movs r0, r5
+ 588: 695b ldr r3, [r3, #20]
+ 58a: 4798 blx r3
+ c = timedPeek();
+ 58c: 0028 movs r0, r5
+ 58e: f7ff ffa3 bl 4d8 <_ZN6Stream9timedPeekEv>
+ }
+ while( (c >= '0' && c <= '9') || c == ignore );
+ 592: 0003 movs r3, r0
+ 594: 3b30 subs r3, #48 ; 0x30
+ 596: 2b09 cmp r3, #9
+ 598: d9e8 bls.n 56c <_ZN6Stream8parseIntE13LookaheadModec+0x14>
+ 59a: 4287 cmp r7, r0
+ 59c: d0e6 beq.n 56c <_ZN6Stream8parseIntE13LookaheadModec+0x14>
+
+ if(isNegative)
+ 59e: 2e00 cmp r6, #0
+ 5a0: d000 beq.n 5a4 <_ZN6Stream8parseIntE13LookaheadModec+0x4c>
+ value = -value;
+ 5a2: 4264 negs r4, r4
+ return value;
+}
+ 5a4: 0020 movs r0, r4
+ 5a6: bdf8 pop {r3, r4, r5, r6, r7, pc}
+ isNegative = true;
+ 5a8: 2601 movs r6, #1
+ 5aa: e7eb b.n 584 <_ZN6Stream8parseIntE13LookaheadModec+0x2c>
+
+000005ac <_ZN7Serial_13getDescriptorER8USBSetup>:
+}
+
+int Serial_::getDescriptor(USBSetup& /* setup */)
+{
+ return 0;
+}
+ 5ac: 2000 movs r0, #0
+ 5ae: 4770 bx lr
+
+000005b0 <_ZThn16_N7Serial_13getDescriptorER8USBSetup>:
+ };
+
+protected:
+ // Implementation of the PUSBListNode
+ int getInterface(uint8_t* interfaceNum);
+ int getDescriptor(USBSetup& setup);
+ 5b0: b408 push {r3}
+ 5b2: 4b02 ldr r3, [pc, #8] ; (5bc <_ZThn16_N7Serial_13getDescriptorER8USBSetup+0xc>)
+ 5b4: 469c mov ip, r3
+ 5b6: 3810 subs r0, #16
+ 5b8: bc08 pop {r3}
+ 5ba: 4760 bx ip
+ 5bc: 000005ad .word 0x000005ad
+
+000005c0 <_ZL5utox8mPc>:
+
+static void utox8(uint32_t val, char* s) {
+ 5c0: b530 push {r4, r5, lr}
+ for (int i = 0; i < 8; i++) {
+ int d = val & 0XF;
+ 5c2: 250f movs r5, #15
+ 5c4: 1dcb adds r3, r1, #7
+ 5c6: 3901 subs r1, #1
+ 5c8: 0002 movs r2, r0
+ 5ca: 402a ands r2, r5
+ val = (val >> 4);
+
+ s[7 - i] = d > 9 ? 'A' + d - 10 : '0' + d;
+ 5cc: 0014 movs r4, r2
+ val = (val >> 4);
+ 5ce: 0900 lsrs r0, r0, #4
+ s[7 - i] = d > 9 ? 'A' + d - 10 : '0' + d;
+ 5d0: 3430 adds r4, #48 ; 0x30
+ 5d2: 2a09 cmp r2, #9
+ 5d4: dd01 ble.n 5da <_ZL5utox8mPc+0x1a>
+ 5d6: 3237 adds r2, #55 ; 0x37
+ 5d8: 0014 movs r4, r2
+ 5da: 701c strb r4, [r3, #0]
+ 5dc: 3b01 subs r3, #1
+ for (int i = 0; i < 8; i++) {
+ 5de: 428b cmp r3, r1
+ 5e0: d1f2 bne.n 5c8 <_ZL5utox8mPc+0x8>
+ }
+}
+ 5e2: bd30 pop {r4, r5, pc}
+
+000005e4 <_ZN7Serial_12getShortNameEPc>:
+
+uint8_t Serial_::getShortName(char* name) {
+ 5e4: b510 push {r4, lr}
+ 5e6: 000c movs r4, r1
+ #define SERIAL_NUMBER_WORD_0 *(volatile uint32_t*)(0x0080A00C)
+ #define SERIAL_NUMBER_WORD_1 *(volatile uint32_t*)(0x0080A040)
+ #define SERIAL_NUMBER_WORD_2 *(volatile uint32_t*)(0x0080A044)
+ #define SERIAL_NUMBER_WORD_3 *(volatile uint32_t*)(0x0080A048)
+
+ utox8(SERIAL_NUMBER_WORD_0, &name[0]);
+ 5e8: 4b0b ldr r3, [pc, #44] ; (618 <_ZN7Serial_12getShortNameEPc+0x34>)
+ 5ea: 6818 ldr r0, [r3, #0]
+ 5ec: f7ff ffe8 bl 5c0 <_ZL5utox8mPc>
+ utox8(SERIAL_NUMBER_WORD_1, &name[8]);
+ 5f0: 0021 movs r1, r4
+ 5f2: 4b0a ldr r3, [pc, #40] ; (61c <_ZN7Serial_12getShortNameEPc+0x38>)
+ 5f4: 3108 adds r1, #8
+ 5f6: 6818 ldr r0, [r3, #0]
+ 5f8: f7ff ffe2 bl 5c0 <_ZL5utox8mPc>
+ utox8(SERIAL_NUMBER_WORD_2, &name[16]);
+ 5fc: 0021 movs r1, r4
+ 5fe: 4b08 ldr r3, [pc, #32] ; (620 <_ZN7Serial_12getShortNameEPc+0x3c>)
+ 600: 3110 adds r1, #16
+ 602: 6818 ldr r0, [r3, #0]
+ 604: f7ff ffdc bl 5c0 <_ZL5utox8mPc>
+ utox8(SERIAL_NUMBER_WORD_3, &name[24]);
+ 608: 0021 movs r1, r4
+ 60a: 4b06 ldr r3, [pc, #24] ; (624 <_ZN7Serial_12getShortNameEPc+0x40>)
+ 60c: 3118 adds r1, #24
+ 60e: 6818 ldr r0, [r3, #0]
+ 610: f7ff ffd6 bl 5c0 <_ZL5utox8mPc>
+ return 32;
+}
+ 614: 2020 movs r0, #32
+ 616: bd10 pop {r4, pc}
+ 618: 0080a00c .word 0x0080a00c
+ 61c: 0080a040 .word 0x0080a040
+ 620: 0080a044 .word 0x0080a044
+ 624: 0080a048 .word 0x0080a048
+
+00000628 <_ZThn16_N7Serial_12getShortNameEPc>:
+ bool setup(USBSetup& setup);
+ uint8_t getShortName(char* name);
+ 628: b408 push {r3}
+ 62a: 4b02 ldr r3, [pc, #8] ; (634 <_ZThn16_N7Serial_12getShortNameEPc+0xc>)
+ 62c: 469c mov ip, r3
+ 62e: 3810 subs r0, #16
+ 630: bc08 pop {r3}
+ 632: 4760 bx ip
+ 634: 000005e5 .word 0x000005e5
+
+00000638 <_ZN7Serial_14handleEndpointEi>:
+
+void Serial_::handleEndpoint(int /* ep */) {
+}
+ 638: 4770 bx lr
+ ...
+
+0000063c <_ZThn16_N7Serial_14handleEndpointEi>:
+ void handleEndpoint(int ep);
+ 63c: b408 push {r3}
+ 63e: 4b02 ldr r3, [pc, #8] ; (648 <_ZThn16_N7Serial_14handleEndpointEi+0xc>)
+ 640: 469c mov ip, r3
+ 642: 3810 subs r0, #16
+ 644: bc08 pop {r3}
+ 646: 4760 bx ip
+ 648: 00000639 .word 0x00000639
+
+0000064c <_ZN7Serial_17availableForWriteEv>:
+int Serial_::availableForWrite(void)
+{
+ // return the number of bytes left in the current bank,
+ // always EP size - 1, because bank is flushed on every write
+ return (EPX_SIZE - 1);
+}
+ 64c: 203f movs r0, #63 ; 0x3f
+ 64e: 4770 bx lr
+
+00000650 <_ZN7Serial_5writeEh>:
+ setWriteError();
+ return 0;
+ }
+}
+
+size_t Serial_::write(uint8_t c) {
+ 650: b513 push {r0, r1, r4, lr}
+ 652: 466b mov r3, sp
+ return write(&c, 1);
+ 654: 6802 ldr r2, [r0, #0]
+size_t Serial_::write(uint8_t c) {
+ 656: 71d9 strb r1, [r3, #7]
+ 658: 3307 adds r3, #7
+ return write(&c, 1);
+ 65a: 6854 ldr r4, [r2, #4]
+ 65c: 0019 movs r1, r3
+ 65e: 2201 movs r2, #1
+ 660: 47a0 blx r4
+}
+ 662: bd16 pop {r1, r2, r4, pc}
+
+00000664 <_ZN7Serial_12getInterfaceEPh>:
+{
+ 664: b5f0 push {r4, r5, r6, r7, lr}
+ interfaceNum[0] += 2; // uses 2
+ 666: 780b ldrb r3, [r1, #0]
+{
+ 668: b095 sub sp, #84 ; 0x54
+ };
+ 66a: ac03 add r4, sp, #12
+ interfaceNum[0] += 2; // uses 2
+ 66c: 3302 adds r3, #2
+{
+ 66e: 9001 str r0, [sp, #4]
+ interfaceNum[0] += 2; // uses 2
+ 670: 700b strb r3, [r1, #0]
+ };
+ 672: 2242 movs r2, #66 ; 0x42
+ 674: 2100 movs r1, #0
+ 676: 0020 movs r0, r4
+ 678: f002 f8d7 bl 282a <memset>
+ 67c: 2209 movs r2, #9
+ 67e: 2504 movs r5, #4
+ 680: 7222 strb r2, [r4, #8]
+ 682: 2204 movs r2, #4
+ 684: 75a5 strb r5, [r4, #22]
+ 686: 7262 strb r2, [r4, #9]
+ 688: 2506 movs r5, #6
+ 68a: 2205 movs r2, #5
+ 68c: 2024 movs r0, #36 ; 0x24
+ 68e: ae02 add r6, sp, #8
+ 690: 7665 strb r5, [r4, #25]
+ 692: 7725 strb r5, [r4, #28]
+ 694: 1995 adds r5, r2, r6
+ 696: 74a0 strb r0, [r4, #18]
+ 698: 75e0 strb r0, [r4, #23]
+ 69a: 76e0 strb r0, [r4, #27]
+ 69c: 77e8 strb r0, [r5, #31]
+ 69e: 0030 movs r0, r6
+ 6a0: 2101 movs r1, #1
+ 6a2: 3006 adds r0, #6
+ 6a4: 77c1 strb r1, [r0, #31]
+ 6a6: 0030 movs r0, r6
+ 6a8: 3007 adds r0, #7
+ 6aa: 77c1 strb r1, [r0, #31]
+ 6ac: a804 add r0, sp, #16
+ 6ae: 77c1 strb r1, [r0, #31]
+ 6b0: 2009 movs r0, #9
+ 6b2: 7321 strb r1, [r4, #12]
+ 6b4: 7561 strb r1, [r4, #21]
+ 6b6: 1980 adds r0, r0, r6
+ 6b8: 3106 adds r1, #6
+ 6ba: 77c1 strb r1, [r0, #31]
+ 6bc: 200a movs r0, #10
+ 6be: 1980 adds r0, r0, r6
+ 6c0: 77c2 strb r2, [r0, #31]
+ 6c2: 2003 movs r0, #3
+ 6c4: 4684 mov ip, r0
+ 6c6: 4665 mov r5, ip
+ 6c8: a805 add r0, sp, #20
+ 6ca: 77c5 strb r5, [r0, #31]
+ 6cc: 202e movs r0, #46 ; 0x2e
+ 6ce: 2710 movs r7, #16
+ 6d0: 1980 adds r0, r0, r6
+ 6d2: 7007 strb r7, [r0, #0]
+ 6d4: 202f movs r0, #47 ; 0x2f
+ 6d6: 2509 movs r5, #9
+ 6d8: 2308 movs r3, #8
+ 6da: 1980 adds r0, r0, r6
+ 6dc: 7005 strb r5, [r0, #0]
+ 6de: 2504 movs r5, #4
+ 6e0: 7023 strb r3, [r4, #0]
+ 6e2: 3303 adds r3, #3
+ 6e4: 7063 strb r3, [r4, #1]
+ 6e6: a80e add r0, sp, #56 ; 0x38
+ 6e8: 3b09 subs r3, #9
+ 6ea: 70e3 strb r3, [r4, #3]
+ 6ec: 7123 strb r3, [r4, #4]
+ 6ee: 7163 strb r3, [r4, #5]
+ 6f0: 7363 strb r3, [r4, #13]
+ 6f2: 73a3 strb r3, [r4, #14]
+ 6f4: 7462 strb r2, [r4, #17]
+ 6f6: 7623 strb r3, [r4, #24]
+ 6f8: 76a2 strb r2, [r4, #26]
+ 6fa: 77e2 strb r2, [r4, #31]
+ 6fc: 7527 strb r7, [r4, #20]
+ 6fe: 8527 strh r7, [r4, #40] ; 0x28
+ 700: 7005 strb r5, [r0, #0]
+ 702: 2033 movs r0, #51 ; 0x33
+ 704: 0035 movs r5, r6
+ 706: 1980 adds r0, r0, r6
+ 708: 260a movs r6, #10
+ 70a: 7003 strb r3, [r0, #0]
+ 70c: a80f add r0, sp, #60 ; 0x3c
+ 70e: 7006 strb r6, [r0, #0]
+ 710: a810 add r0, sp, #64 ; 0x40
+ 712: 7001 strb r1, [r0, #0]
+ 714: 2039 movs r0, #57 ; 0x39
+ 716: 1940 adds r0, r0, r5
+ 718: 7002 strb r2, [r0, #0]
+ 71a: 203b movs r0, #59 ; 0x3b
+ 71c: 3635 adds r6, #53 ; 0x35
+ 71e: 1976 adds r6, r6, r5
+ 720: 7031 strb r1, [r6, #0]
+ 722: a912 add r1, sp, #72 ; 0x48
+ 724: 700a strb r2, [r1, #0]
+ D_ENDPOINT(USB_ENDPOINT_IN(CDC_ENDPOINT_ACM), USB_ENDPOINT_TYPE_INTERRUPT, 0x10, 0x10),
+ 726: 2180 movs r1, #128 ; 0x80
+ };
+ 728: 323d adds r2, #61 ; 0x3d
+ 72a: 1940 adds r0, r0, r5
+ 72c: 1952 adds r2, r2, r5
+ 72e: 7003 strb r3, [r0, #0]
+ 730: 7013 strb r3, [r2, #0]
+ 732: 2040 movs r0, #64 ; 0x40
+ 734: 2200 movs r2, #0
+ D_ENDPOINT(USB_ENDPOINT_IN(CDC_ENDPOINT_ACM), USB_ENDPOINT_TYPE_INTERRUPT, 0x10, 0x10),
+ 736: 4249 negs r1, r1
+ 738: 000e movs r6, r1
+ };
+ 73a: 3341 adds r3, #65 ; 0x41
+ 73c: 195b adds r3, r3, r5
+ 73e: 7018 strb r0, [r3, #0]
+ 740: 705a strb r2, [r3, #1]
+ D_IAD(pluggedInterface, 2, CDC_COMMUNICATION_INTERFACE_CLASS, CDC_ABSTRACT_CONTROL_MODEL, 0),
+ 742: 9b01 ldr r3, [sp, #4]
+ };
+ 744: 8720 strh r0, [r4, #56] ; 0x38
+ D_IAD(pluggedInterface, 2, CDC_COMMUNICATION_INTERFACE_CLASS, CDC_ABSTRACT_CONTROL_MODEL, 0),
+ 746: 7d1b ldrb r3, [r3, #20]
+ D_ENDPOINT(USB_ENDPOINT_IN(CDC_ENDPOINT_ACM), USB_ENDPOINT_TYPE_INTERRUPT, 0x10, 0x10),
+ 748: 9a01 ldr r2, [sp, #4]
+ };
+ 74a: 70a3 strb r3, [r4, #2]
+ 74c: 72a3 strb r3, [r4, #10]
+ 74e: 7763 strb r3, [r4, #29]
+ D_CDCCS(CDC_UNION, CDC_ACM_INTERFACE, CDC_DATA_INTERFACE), // Communication interface is master, data interface is slave 0
+ 750: 3301 adds r3, #1
+ 752: b2db uxtb r3, r3
+ };
+ 754: 77a3 strb r3, [r4, #30]
+ D_ENDPOINT(USB_ENDPOINT_IN(CDC_ENDPOINT_ACM), USB_ENDPOINT_TYPE_INTERRUPT, 0x10, 0x10),
+ 756: 7d52 ldrb r2, [r2, #21]
+ };
+ 758: 3835 subs r0, #53 ; 0x35
+ D_ENDPOINT(USB_ENDPOINT_IN(CDC_ENDPOINT_ACM), USB_ENDPOINT_TYPE_INTERRUPT, 0x10, 0x10),
+ 75a: 4316 orrs r6, r2
+ };
+ 75c: 1940 adds r0, r0, r5
+ 75e: 77c6 strb r6, [r0, #31]
+ 760: 2031 movs r0, #49 ; 0x31
+ 762: 1940 adds r0, r0, r5
+ 764: 7003 strb r3, [r0, #0]
+ 766: 233a movs r3, #58 ; 0x3a
+ D_ENDPOINT(USB_ENDPOINT_OUT(CDC_ENDPOINT_OUT), USB_ENDPOINT_TYPE_BULK, EPX_SIZE, 0),
+ 768: 1c50 adds r0, r2, #1
+ };
+ 76a: 195b adds r3, r3, r5
+ 76c: 7018 strb r0, [r3, #0]
+ 76e: 2341 movs r3, #65 ; 0x41
+ D_ENDPOINT(USB_ENDPOINT_IN (CDC_ENDPOINT_IN), USB_ENDPOINT_TYPE_BULK, EPX_SIZE, 0)
+ 770: 3202 adds r2, #2
+ 772: 430a orrs r2, r1
+ };
+ 774: 195b adds r3, r3, r5
+ 776: 701a strb r2, [r3, #0]
+ return USBDevice.sendControl(&_cdcInterface, sizeof(_cdcInterface));
+ 778: 0021 movs r1, r4
+ 77a: 2242 movs r2, #66 ; 0x42
+ 77c: 4802 ldr r0, [pc, #8] ; (788 <_ZN7Serial_12getInterfaceEPh+0x124>)
+ 77e: f000 ff25 bl 15cc <_ZN14USBDeviceClass11sendControlEPKvm>
+}
+ 782: b015 add sp, #84 ; 0x54
+ 784: bdf0 pop {r4, r5, r6, r7, pc}
+ 786: 46c0 nop ; (mov r8, r8)
+ 788: 2000013c .word 0x2000013c
+
+0000078c <_ZThn16_N7Serial_12getInterfaceEPh>:
+ int getInterface(uint8_t* interfaceNum);
+ 78c: b408 push {r3}
+ 78e: 4b02 ldr r3, [pc, #8] ; (798 <_ZThn16_N7Serial_12getInterfaceEPh+0xc>)
+ 790: 469c mov ip, r3
+ 792: 3810 subs r0, #16
+ 794: bc08 pop {r3}
+ 796: 4760 bx ip
+ 798: 00000665 .word 0x00000665
+
+0000079c <_ZN7Serial_5setupER8USBSetup>:
+{
+ 79c: b570 push {r4, r5, r6, lr}
+ if (CDC_ACM_INTERFACE != i) {
+ 79e: 790a ldrb r2, [r1, #4]
+ 7a0: 7d03 ldrb r3, [r0, #20]
+{
+ 7a2: 000c movs r4, r1
+ return false;
+ 7a4: 2500 movs r5, #0
+ if (CDC_ACM_INTERFACE != i) {
+ 7a6: 429a cmp r2, r3
+ 7a8: d10b bne.n 7c2 <_ZN7Serial_5setupER8USBSetup+0x26>
+ uint8_t requestType = setup.bmRequestType;
+ 7aa: 780b ldrb r3, [r1, #0]
+ uint8_t r = setup.bRequest;
+ 7ac: 784e ldrb r6, [r1, #1]
+ if (requestType == REQUEST_DEVICETOHOST_CLASS_INTERFACE)
+ 7ae: 2ba1 cmp r3, #161 ; 0xa1
+ 7b0: d109 bne.n 7c6 <_ZN7Serial_5setupER8USBSetup+0x2a>
+ if (r == CDC_GET_LINE_CODING)
+ 7b2: 2e21 cmp r6, #33 ; 0x21
+ 7b4: d105 bne.n 7c2 <_ZN7Serial_5setupER8USBSetup+0x26>
+ USBDevice.sendControl((void*)&_usbLineInfo, 7);
+ 7b6: 2207 movs r2, #7
+ 7b8: 491f ldr r1, [pc, #124] ; (838 <_ZN7Serial_5setupER8USBSetup+0x9c>)
+ 7ba: 4820 ldr r0, [pc, #128] ; (83c <_ZN7Serial_5setupER8USBSetup+0xa0>)
+ 7bc: f000 ff06 bl 15cc <_ZN14USBDeviceClass11sendControlEPKvm>
+ return true;
+ 7c0: 3501 adds r5, #1
+}
+ 7c2: 0028 movs r0, r5
+ 7c4: bd70 pop {r4, r5, r6, pc}
+ if (requestType == REQUEST_HOSTTODEVICE_CLASS_INTERFACE)
+ 7c6: 2b21 cmp r3, #33 ; 0x21
+ 7c8: d1fb bne.n 7c2 <_ZN7Serial_5setupER8USBSetup+0x26>
+ if (r == CDC_SET_LINE_CODING)
+ 7ca: 2e20 cmp r6, #32
+ 7cc: d119 bne.n 802 <_ZN7Serial_5setupER8USBSetup+0x66>
+ USBDevice.recvControl((void*)&_usbLineInfo, 7);
+ 7ce: 2207 movs r2, #7
+ 7d0: 4919 ldr r1, [pc, #100] ; (838 <_ZN7Serial_5setupER8USBSetup+0x9c>)
+ 7d2: 481a ldr r0, [pc, #104] ; (83c <_ZN7Serial_5setupER8USBSetup+0xa0>)
+ 7d4: f000 fe3c bl 1450 <_ZN14USBDeviceClass11recvControlEPvm>
+ if (_usbLineInfo.dwDTERate == 1200 && (_usbLineInfo.lineState & CDC_LINESTATE_DTR) == 0)
+ 7d8: 4b17 ldr r3, [pc, #92] ; (838 <_ZN7Serial_5setupER8USBSetup+0x9c>)
+ 7da: 781a ldrb r2, [r3, #0]
+ 7dc: 7859 ldrb r1, [r3, #1]
+ 7de: 0209 lsls r1, r1, #8
+ 7e0: 4311 orrs r1, r2
+ 7e2: 789a ldrb r2, [r3, #2]
+ 7e4: 0412 lsls r2, r2, #16
+ 7e6: 4311 orrs r1, r2
+ 7e8: 78da ldrb r2, [r3, #3]
+ 7ea: 0612 lsls r2, r2, #24
+ 7ec: 430a orrs r2, r1
+ 7ee: 2196 movs r1, #150 ; 0x96
+ 7f0: 00c9 lsls r1, r1, #3
+ 7f2: 428a cmp r2, r1
+ 7f4: d102 bne.n 7fc <_ZN7Serial_5setupER8USBSetup+0x60>
+ 7f6: 79db ldrb r3, [r3, #7]
+ 7f8: 07db lsls r3, r3, #31
+ 7fa: d508 bpl.n 80e <_ZN7Serial_5setupER8USBSetup+0x72>
+ cancelReset();
+ 7fc: f7ff fd7a bl 2f4 <cancelReset>
+ 800: e008 b.n 814 <_ZN7Serial_5setupER8USBSetup+0x78>
+ if (r == CDC_SET_CONTROL_LINE_STATE)
+ 802: 2e22 cmp r6, #34 ; 0x22
+ 804: d10a bne.n 81c <_ZN7Serial_5setupER8USBSetup+0x80>
+ _usbLineInfo.lineState = setup.wValueL;
+ 806: 788a ldrb r2, [r1, #2]
+ 808: 4b0b ldr r3, [pc, #44] ; (838 <_ZN7Serial_5setupER8USBSetup+0x9c>)
+ 80a: 71da strb r2, [r3, #7]
+ 80c: e7e4 b.n 7d8 <_ZN7Serial_5setupER8USBSetup+0x3c>
+ initiateReset(250);
+ 80e: 20fa movs r0, #250 ; 0xfa
+ 810: f7ff fd66 bl 2e0 <initiateReset>
+ USBDevice.sendZlp(0);
+ 814: 2100 movs r1, #0
+ 816: 4809 ldr r0, [pc, #36] ; (83c <_ZN7Serial_5setupER8USBSetup+0xa0>)
+ 818: f000 ffee bl 17f8 <_ZN14USBDeviceClass7sendZlpEm>
+ return true;
+ 81c: 2501 movs r5, #1
+ if (CDC_SEND_BREAK == r)
+ 81e: 2e23 cmp r6, #35 ; 0x23
+ 820: d1cf bne.n 7c2 <_ZN7Serial_5setupER8USBSetup+0x26>
+ breakValue = ((uint16_t)setup.wValueH << 8) | setup.wValueL;
+ 822: 78e3 ldrb r3, [r4, #3]
+ 824: 78a2 ldrb r2, [r4, #2]
+ 826: 021b lsls r3, r3, #8
+ 828: 4313 orrs r3, r2
+ 82a: 4a05 ldr r2, [pc, #20] ; (840 <_ZN7Serial_5setupER8USBSetup+0xa4>)
+ USBDevice.sendZlp(0);
+ 82c: 2100 movs r1, #0
+ 82e: 4803 ldr r0, [pc, #12] ; (83c <_ZN7Serial_5setupER8USBSetup+0xa0>)
+ breakValue = ((uint16_t)setup.wValueH << 8) | setup.wValueL;
+ 830: 6013 str r3, [r2, #0]
+ USBDevice.sendZlp(0);
+ 832: f000 ffe1 bl 17f8 <_ZN14USBDeviceClass7sendZlpEm>
+ 836: e7c4 b.n 7c2 <_ZN7Serial_5setupER8USBSetup+0x26>
+ 838: 20000008 .word 0x20000008
+ 83c: 2000013c .word 0x2000013c
+ 840: 20000004 .word 0x20000004
+
+00000844 <_ZThn16_N7Serial_5setupER8USBSetup>:
+ bool setup(USBSetup& setup);
+ 844: b408 push {r3}
+ 846: 4b02 ldr r3, [pc, #8] ; (850 <_ZThn16_N7Serial_5setupER8USBSetup+0xc>)
+ 848: 469c mov ip, r3
+ 84a: 3810 subs r0, #16
+ 84c: bc08 pop {r3}
+ 84e: 4760 bx ip
+ 850: 0000079d .word 0x0000079d
+
+00000854 <_ZN7Serial_9availableEv>:
+{
+ 854: b510 push {r4, lr}
+ return usb.available(CDC_ENDPOINT_OUT) + (_serialPeek != -1);
+ 856: 7d41 ldrb r1, [r0, #21]
+ 858: 6a00 ldr r0, [r0, #32]
+ 85a: 3101 adds r1, #1
+ 85c: f000 fd2e bl 12bc <_ZN14USBDeviceClass9availableEm>
+ 860: 4b03 ldr r3, [pc, #12] ; (870 <_ZN7Serial_9availableEv+0x1c>)
+ 862: 681b ldr r3, [r3, #0]
+ 864: 3301 adds r3, #1
+ 866: 1e5a subs r2, r3, #1
+ 868: 4193 sbcs r3, r2
+ 86a: 1818 adds r0, r3, r0
+}
+ 86c: bd10 pop {r4, pc}
+ 86e: 46c0 nop ; (mov r8, r8)
+ 870: 20000010 .word 0x20000010
+
+00000874 <_ZN7Serial_5flushEv>:
+{
+ 874: b510 push {r4, lr}
+ usb.flush(CDC_ENDPOINT_IN);
+ 876: 7d41 ldrb r1, [r0, #21]
+ 878: 6a00 ldr r0, [r0, #32]
+ 87a: 3102 adds r1, #2
+ 87c: f000 fd34 bl 12e8 <_ZN14USBDeviceClass5flushEm>
+}
+ 880: bd10 pop {r4, pc}
+
+00000882 <_ZN7Serial_5clearEv>:
+void Serial_::clear(void) {
+ 882: b510 push {r4, lr}
+ usb.clear(CDC_ENDPOINT_IN);
+ 884: 7d41 ldrb r1, [r0, #21]
+ 886: 6a00 ldr r0, [r0, #32]
+ 888: 3102 adds r1, #2
+ 88a: f000 fcfb bl 1284 <_ZN14USBDeviceClass5clearEm>
+}
+ 88e: bd10 pop {r4, pc}
+
+00000890 <_ZN7Serial_5writeEPKhj>:
+{
+ 890: b570 push {r4, r5, r6, lr}
+ 892: 000d movs r5, r1
+ uint32_t r = usb.send(CDC_ENDPOINT_IN, buffer, size);
+ 894: 7d41 ldrb r1, [r0, #21]
+{
+ 896: 0004 movs r4, r0
+ 898: 0013 movs r3, r2
+ uint32_t r = usb.send(CDC_ENDPOINT_IN, buffer, size);
+ 89a: 3102 adds r1, #2
+ 89c: 002a movs r2, r5
+ 89e: 6a00 ldr r0, [r0, #32]
+ 8a0: f000 fdea bl 1478 <_ZN14USBDeviceClass4sendEmPKvm>
+ if (r > 0) {
+ 8a4: 2800 cmp r0, #0
+ 8a6: d101 bne.n 8ac <_ZN7Serial_5writeEPKhj+0x1c>
+ private:
+ int write_error;
+ size_t printNumber(unsigned long, uint8_t);
+ size_t printFloat(double, uint8_t);
+ protected:
+ void setWriteError(int err = 1) { write_error = err; }
+ 8a8: 2301 movs r3, #1
+ 8aa: 6063 str r3, [r4, #4]
+}
+ 8ac: bd70 pop {r4, r5, r6, pc}
+ ...
+
+000008b0 <_ZN7Serial_4peekEv>:
+{
+ 8b0: b510 push {r4, lr}
+ if (_serialPeek != -1)
+ 8b2: 4c05 ldr r4, [pc, #20] ; (8c8 <_ZN7Serial_4peekEv+0x18>)
+ 8b4: 6823 ldr r3, [r4, #0]
+ 8b6: 1c5a adds r2, r3, #1
+ 8b8: d104 bne.n 8c4 <_ZN7Serial_4peekEv+0x14>
+ _serialPeek = read();
+ 8ba: 6803 ldr r3, [r0, #0]
+ 8bc: 695b ldr r3, [r3, #20]
+ 8be: 4798 blx r3
+ 8c0: 0003 movs r3, r0
+ 8c2: 6020 str r0, [r4, #0]
+}
+ 8c4: 0018 movs r0, r3
+ 8c6: bd10 pop {r4, pc}
+ 8c8: 20000010 .word 0x20000010
+
+000008cc <_ZN7Serial_4readEv>:
+ if (_serialPeek != -1) {
+ 8cc: 4a07 ldr r2, [pc, #28] ; (8ec <_ZN7Serial_4readEv+0x20>)
+{
+ 8ce: 0003 movs r3, r0
+ if (_serialPeek != -1) {
+ 8d0: 6810 ldr r0, [r2, #0]
+{
+ 8d2: b510 push {r4, lr}
+ if (_serialPeek != -1) {
+ 8d4: 1c41 adds r1, r0, #1
+ 8d6: d003 beq.n 8e0 <_ZN7Serial_4readEv+0x14>
+ _serialPeek = -1;
+ 8d8: 2301 movs r3, #1
+ 8da: 425b negs r3, r3
+ 8dc: 6013 str r3, [r2, #0]
+}
+ 8de: bd10 pop {r4, pc}
+ return usb.recv(CDC_ENDPOINT_OUT);
+ 8e0: 7d59 ldrb r1, [r3, #21]
+ 8e2: 6a18 ldr r0, [r3, #32]
+ 8e4: 3101 adds r1, #1
+ 8e6: f000 fd77 bl 13d8 <_ZN14USBDeviceClass4recvEm>
+ 8ea: e7f8 b.n 8de <_ZN7Serial_4readEv+0x12>
+ 8ec: 20000010 .word 0x20000010
+
+000008f0 <_ZN7Serial_C1ER14USBDeviceClass>:
+ public:
+ virtual int available() = 0;
+ virtual int read() = 0;
+ virtual int peek() = 0;
+
+ Stream() {_timeout=1000;}
+ 8f0: 23fa movs r3, #250 ; 0xfa
+ 8f2: 009b lsls r3, r3, #2
+Serial_::Serial_(USBDeviceClass &_usb) : PluggableUSBModule(3, 2, epType), usb(_usb), stalled(false)
+ 8f4: b570 push {r4, r5, r6, lr}
+ 8f6: 0004 movs r4, r0
+ 8f8: 6083 str r3, [r0, #8]
+#if defined(USBCON)
+
+class PluggableUSBModule {
+public:
+ PluggableUSBModule(uint8_t numEps, uint8_t numIfs, uint32_t *epType) :
+ numEndpoints(numEps), numInterfaces(numIfs), endpointType(epType)
+ 8fa: 2303 movs r3, #3
+ 8fc: 7583 strb r3, [r0, #22]
+ 8fe: 0023 movs r3, r4
+ public:
+ Print() : write_error(0) {}
+ 900: 2200 movs r2, #0
+ 902: 3328 adds r3, #40 ; 0x28
+ 904: 6042 str r2, [r0, #4]
+ 906: 61a3 str r3, [r4, #24]
+ 908: 4b0c ldr r3, [pc, #48] ; (93c <_ZN7Serial_C1ER14USBDeviceClass+0x4c>)
+ 90a: 2002 movs r0, #2
+ 90c: 001d movs r5, r3
+ 90e: 3344 adds r3, #68 ; 0x44
+ 910: 6123 str r3, [r4, #16]
+ 912: 3508 adds r5, #8
+ 914: 1d63 adds r3, r4, #5
+ 916: 61e2 str r2, [r4, #28]
+ 918: 6025 str r5, [r4, #0]
+ 91a: 6221 str r1, [r4, #32]
+ 91c: 75e0 strb r0, [r4, #23]
+ 91e: 77da strb r2, [r3, #31]
+ epType[0] = USB_ENDPOINT_TYPE_INTERRUPT | USB_ENDPOINT_IN(0);
+ 920: 2383 movs r3, #131 ; 0x83
+ 922: 62a3 str r3, [r4, #40] ; 0x28
+ epType[2] = USB_ENDPOINT_TYPE_BULK | USB_ENDPOINT_IN(0);
+ 924: 3b01 subs r3, #1
+ 926: 6323 str r3, [r4, #48] ; 0x30
+ epType[1] = USB_ENDPOINT_TYPE_BULK | USB_ENDPOINT_OUT(0);
+ 928: 62e0 str r0, [r4, #44] ; 0x2c
+ PluggableUSB().plug(this);
+ 92a: f000 f8ad bl a88 <_Z12PluggableUSBv>
+Serial_::Serial_(USBDeviceClass &_usb) : PluggableUSBModule(3, 2, epType), usb(_usb), stalled(false)
+ 92e: 0021 movs r1, r4
+ 930: 3110 adds r1, #16
+ PluggableUSB().plug(this);
+ 932: f000 f87d bl a30 <_ZN13PluggableUSB_4plugEP18PluggableUSBModule>
+}
+ 936: 0020 movs r0, r4
+ 938: bd70 pop {r4, r5, r6, pc}
+ 93a: 46c0 nop ; (mov r8, r8)
+ 93c: 000029f8 .word 0x000029f8
+
+00000940 <_ZN7Serial_15enableInterruptEv>:
+void Serial_::enableInterrupt() {
+ 940: b510 push {r4, lr}
+ usbd.epBank1EnableTransferComplete(CDC_ENDPOINT_ACM);
+ 942: 7d43 ldrb r3, [r0, #21]
+ inline void epBank0EnableStalled(ep_t ep) { usb.DeviceEndpoint[ep].EPINTENSET.bit.STALL0 = 1; }
+ inline void epBank1EnableStalled(ep_t ep) { usb.DeviceEndpoint[ep].EPINTENSET.bit.STALL1 = 1; }
+ inline void epBank0EnableTransferFailed(ep_t ep) { usb.DeviceEndpoint[ep].EPINTENSET.bit.TRFAIL0 = 1; }
+ inline void epBank1EnableTransferFailed(ep_t ep) { usb.DeviceEndpoint[ep].EPINTENSET.bit.TRFAIL1 = 1; }
+ inline void epBank0EnableTransferComplete(ep_t ep) { usb.DeviceEndpoint[ep].EPINTENSET.bit.TRCPT0 = 1; }
+ inline void epBank1EnableTransferComplete(ep_t ep) { usb.DeviceEndpoint[ep].EPINTENSET.bit.TRCPT1 = 1; }
+ 944: 4a09 ldr r2, [pc, #36] ; (96c <_ZN7Serial_15enableInterruptEv+0x2c>)
+ 946: 2002 movs r0, #2
+ 948: 0159 lsls r1, r3, #5
+ usbd.epBank0EnableTransferComplete(CDC_ENDPOINT_OUT);
+ 94a: 3301 adds r3, #1
+ 94c: 6812 ldr r2, [r2, #0]
+ inline void epBank0EnableTransferComplete(ep_t ep) { usb.DeviceEndpoint[ep].EPINTENSET.bit.TRCPT0 = 1; }
+ 94e: b2db uxtb r3, r3
+ 950: 015b lsls r3, r3, #5
+ inline void epBank1EnableTransferComplete(ep_t ep) { usb.DeviceEndpoint[ep].EPINTENSET.bit.TRCPT1 = 1; }
+ 952: 1851 adds r1, r2, r1
+ inline void epBank0EnableTransferComplete(ep_t ep) { usb.DeviceEndpoint[ep].EPINTENSET.bit.TRCPT0 = 1; }
+ 954: 18d3 adds r3, r2, r3
+ 956: 2201 movs r2, #1
+ inline void epBank1EnableTransferComplete(ep_t ep) { usb.DeviceEndpoint[ep].EPINTENSET.bit.TRCPT1 = 1; }
+ 958: 31ff adds r1, #255 ; 0xff
+ 95a: 7a8c ldrb r4, [r1, #10]
+ inline void epBank0EnableTransferComplete(ep_t ep) { usb.DeviceEndpoint[ep].EPINTENSET.bit.TRCPT0 = 1; }
+ 95c: 33ff adds r3, #255 ; 0xff
+ inline void epBank1EnableTransferComplete(ep_t ep) { usb.DeviceEndpoint[ep].EPINTENSET.bit.TRCPT1 = 1; }
+ 95e: 4320 orrs r0, r4
+ 960: 7288 strb r0, [r1, #10]
+ inline void epBank0EnableTransferComplete(ep_t ep) { usb.DeviceEndpoint[ep].EPINTENSET.bit.TRCPT0 = 1; }
+ 962: 7a99 ldrb r1, [r3, #10]
+ 964: 430a orrs r2, r1
+ 966: 729a strb r2, [r3, #10]
+}
+ 968: bd10 pop {r4, pc}
+ 96a: 46c0 nop ; (mov r8, r8)
+ 96c: 200005f4 .word 0x200005f4
+
+00000970 <_ZN7Serial_5beginEm>:
+}
+ 970: 4770 bx lr
+ ...
+
+00000974 <_GLOBAL__sub_I__ZN7Serial_12getInterfaceEPh>:
+
+bool Serial_::rts() {
+ return ((_usbLineInfo.lineState & CDC_LINESTATE_RTS) == CDC_LINESTATE_RTS);
+}
+
+Serial_ SerialUSB(USBDevice);
+ 974: b510 push {r4, lr}
+ 976: 4902 ldr r1, [pc, #8] ; (980 <_GLOBAL__sub_I__ZN7Serial_12getInterfaceEPh+0xc>)
+ 978: 4802 ldr r0, [pc, #8] ; (984 <_GLOBAL__sub_I__ZN7Serial_12getInterfaceEPh+0x10>)
+ 97a: f7ff ffb9 bl 8f0 <_ZN7Serial_C1ER14USBDeviceClass>
+ 97e: bd10 pop {r4, pc}
+ 980: 2000013c .word 0x2000013c
+ 984: 200000d4 .word 0x200000d4
+
+00000988 <_ZN13PluggableUSB_12getInterfaceEPh>:
+#if defined(USBCON) && defined(PLUGGABLE_USB_ENABLED)
+
+extern uint32_t EndPoints[];
+
+int PluggableUSB_::getInterface(uint8_t* interfaceCount)
+{
+ 988: b570 push {r4, r5, r6, lr}
+ 98a: 000e movs r6, r1
+ int sent = 0;
+ 98c: 2500 movs r5, #0
+ PluggableUSBModule* node;
+ for (node = rootNode; node; node = node->next) {
+ 98e: 6844 ldr r4, [r0, #4]
+ 990: 2c00 cmp r4, #0
+ 992: d00b beq.n 9ac <_ZN13PluggableUSB_12getInterfaceEPh+0x24>
+ int res = node->getInterface(interfaceCount);
+ 994: 6823 ldr r3, [r4, #0]
+ 996: 0031 movs r1, r6
+ 998: 685b ldr r3, [r3, #4]
+ 99a: 0020 movs r0, r4
+ 99c: 4798 blx r3
+ if (res < 0)
+ 99e: 2800 cmp r0, #0
+ 9a0: db02 blt.n 9a8 <_ZN13PluggableUSB_12getInterfaceEPh+0x20>
+ return -1;
+ sent += res;
+ 9a2: 182d adds r5, r5, r0
+ for (node = rootNode; node; node = node->next) {
+ 9a4: 68e4 ldr r4, [r4, #12]
+ 9a6: e7f3 b.n 990 <_ZN13PluggableUSB_12getInterfaceEPh+0x8>
+ return -1;
+ 9a8: 2501 movs r5, #1
+ 9aa: 426d negs r5, r5
+ }
+ return sent;
+}
+ 9ac: 0028 movs r0, r5
+ 9ae: bd70 pop {r4, r5, r6, pc}
+
+000009b0 <_ZN13PluggableUSB_13getDescriptorER8USBSetup>:
+
+int PluggableUSB_::getDescriptor(USBSetup& setup)
+{
+ 9b0: b570 push {r4, r5, r6, lr}
+ 9b2: 000d movs r5, r1
+ PluggableUSBModule* node;
+ for (node = rootNode; node; node = node->next) {
+ 9b4: 6844 ldr r4, [r0, #4]
+ 9b6: 2c00 cmp r4, #0
+ 9b8: d008 beq.n 9cc <_ZN13PluggableUSB_13getDescriptorER8USBSetup+0x1c>
+ int ret = node->getDescriptor(setup);
+ 9ba: 6823 ldr r3, [r4, #0]
+ 9bc: 0029 movs r1, r5
+ 9be: 689b ldr r3, [r3, #8]
+ 9c0: 0020 movs r0, r4
+ 9c2: 4798 blx r3
+ // ret!=0 -> request has been processed
+ if (ret)
+ 9c4: 2800 cmp r0, #0
+ 9c6: d102 bne.n 9ce <_ZN13PluggableUSB_13getDescriptorER8USBSetup+0x1e>
+ for (node = rootNode; node; node = node->next) {
+ 9c8: 68e4 ldr r4, [r4, #12]
+ 9ca: e7f4 b.n 9b6 <_ZN13PluggableUSB_13getDescriptorER8USBSetup+0x6>
+ return ret;
+ }
+ return 0;
+ 9cc: 0020 movs r0, r4
+}
+ 9ce: bd70 pop {r4, r5, r6, pc}
+
+000009d0 <_ZN13PluggableUSB_12getShortNameEPc>:
+
+uint8_t PluggableUSB_::getShortName(char *iSerialNum)
+{
+ 9d0: b570 push {r4, r5, r6, lr}
+ 9d2: 000d movs r5, r1
+ PluggableUSBModule* node;
+ uint8_t size = 0;
+ 9d4: 2600 movs r6, #0
+ for (node = rootNode; node; node = node->next) {
+ 9d6: 6844 ldr r4, [r0, #4]
+ 9d8: 2c00 cmp r4, #0
+ 9da: d009 beq.n 9f0 <_ZN13PluggableUSB_12getShortNameEPc+0x20>
+ uint8_t len = node->getShortName(iSerialNum);
+ 9dc: 6823 ldr r3, [r4, #0]
+ 9de: 0029 movs r1, r5
+ 9e0: 0020 movs r0, r4
+ 9e2: 691b ldr r3, [r3, #16]
+ 9e4: 4798 blx r3
+ iSerialNum += len;
+ size += len;
+ 9e6: 1836 adds r6, r6, r0
+ iSerialNum += len;
+ 9e8: 182d adds r5, r5, r0
+ size += len;
+ 9ea: b2f6 uxtb r6, r6
+ for (node = rootNode; node; node = node->next) {
+ 9ec: 68e4 ldr r4, [r4, #12]
+ 9ee: e7f3 b.n 9d8 <_ZN13PluggableUSB_12getShortNameEPc+0x8>
+ }
+ *iSerialNum = 0;
+ return size;
+}
+ 9f0: 0030 movs r0, r6
+ *iSerialNum = 0;
+ 9f2: 702c strb r4, [r5, #0]
+}
+ 9f4: bd70 pop {r4, r5, r6, pc}
+
+000009f6 <_ZN13PluggableUSB_5setupER8USBSetup>:
+
+bool PluggableUSB_::setup(USBSetup& setup)
+{
+ 9f6: b570 push {r4, r5, r6, lr}
+ 9f8: 000d movs r5, r1
+ PluggableUSBModule* node;
+ for (node = rootNode; node; node = node->next) {
+ 9fa: 6844 ldr r4, [r0, #4]
+ 9fc: 2c00 cmp r4, #0
+ 9fe: d008 beq.n a12 <_ZN13PluggableUSB_5setupER8USBSetup+0x1c>
+ if (node->setup(setup)) {
+ a00: 6823 ldr r3, [r4, #0]
+ a02: 0029 movs r1, r5
+ a04: 681b ldr r3, [r3, #0]
+ a06: 0020 movs r0, r4
+ a08: 4798 blx r3
+ a0a: 2800 cmp r0, #0
+ a0c: d102 bne.n a14 <_ZN13PluggableUSB_5setupER8USBSetup+0x1e>
+ for (node = rootNode; node; node = node->next) {
+ a0e: 68e4 ldr r4, [r4, #12]
+ a10: e7f4 b.n 9fc <_ZN13PluggableUSB_5setupER8USBSetup+0x6>
+ return true;
+ }
+ }
+ return false;
+ a12: 0020 movs r0, r4
+}
+ a14: bd70 pop {r4, r5, r6, pc}
+
+00000a16 <_ZN13PluggableUSB_14handleEndpointEi>:
+
+void PluggableUSB_::handleEndpoint(int ep)
+{
+ a16: b570 push {r4, r5, r6, lr}
+ a18: 000d movs r5, r1
+ PluggableUSBModule* node;
+ for (node = rootNode; node; node = node->next) {
+ a1a: 6844 ldr r4, [r0, #4]
+ a1c: 2c00 cmp r4, #0
+ a1e: d006 beq.n a2e <_ZN13PluggableUSB_14handleEndpointEi+0x18>
+ node->handleEndpoint(ep);
+ a20: 6823 ldr r3, [r4, #0]
+ a22: 0020 movs r0, r4
+ a24: 68db ldr r3, [r3, #12]
+ a26: 0029 movs r1, r5
+ a28: 4798 blx r3
+ for (node = rootNode; node; node = node->next) {
+ a2a: 68e4 ldr r4, [r4, #12]
+ a2c: e7f6 b.n a1c <_ZN13PluggableUSB_14handleEndpointEi+0x6>
+ }
+}
+ a2e: bd70 pop {r4, r5, r6, pc}
+
+00000a30 <_ZN13PluggableUSB_4plugEP18PluggableUSBModule>:
+
+bool PluggableUSB_::plug(PluggableUSBModule *node)
+{
+ a30: b5f0 push {r4, r5, r6, r7, lr}
+ if ((lastEp + node->numEndpoints) > USB_ENDPOINTS) {
+ a32: 798c ldrb r4, [r1, #6]
+ a34: 7845 ldrb r5, [r0, #1]
+{
+ a36: 0003 movs r3, r0
+ if ((lastEp + node->numEndpoints) > USB_ENDPOINTS) {
+ a38: 192a adds r2, r5, r4
+ return false;
+ a3a: 2000 movs r0, #0
+ if ((lastEp + node->numEndpoints) > USB_ENDPOINTS) {
+ a3c: 2a07 cmp r2, #7
+ a3e: dc1f bgt.n a80 <_ZN13PluggableUSB_4plugEP18PluggableUSBModule+0x50>
+ }
+
+ if (!rootNode) {
+ a40: 685a ldr r2, [r3, #4]
+ a42: 4282 cmp r2, r0
+ a44: d116 bne.n a74 <_ZN13PluggableUSB_4plugEP18PluggableUSBModule+0x44>
+ rootNode = node;
+ a46: 6059 str r1, [r3, #4]
+ current = current->next;
+ }
+ current->next = node;
+ }
+
+ node->pluggedInterface = lastIf;
+ a48: 781a ldrb r2, [r3, #0]
+ node->pluggedEndpoint = lastEp;
+ lastIf += node->numInterfaces;
+ a4a: 79c8 ldrb r0, [r1, #7]
+ node->pluggedInterface = lastIf;
+ a4c: 710a strb r2, [r1, #4]
+ lastIf += node->numInterfaces;
+ a4e: 1812 adds r2, r2, r0
+ node->pluggedEndpoint = lastEp;
+ a50: 714d strb r5, [r1, #5]
+ lastIf += node->numInterfaces;
+ a52: 701a strb r2, [r3, #0]
+ for (uint8_t i = 0; i < node->numEndpoints; i++) {
+ a54: 2200 movs r2, #0
+ EndPoints[lastEp] = node->endpointType[i];
+ a56: 4d0b ldr r5, [pc, #44] ; (a84 <_ZN13PluggableUSB_4plugEP18PluggableUSBModule+0x54>)
+ for (uint8_t i = 0; i < node->numEndpoints; i++) {
+ a58: 4294 cmp r4, r2
+ a5a: dd10 ble.n a7e <_ZN13PluggableUSB_4plugEP18PluggableUSBModule+0x4e>
+ EndPoints[lastEp] = node->endpointType[i];
+ a5c: 688f ldr r7, [r1, #8]
+ a5e: 7858 ldrb r0, [r3, #1]
+ a60: 0096 lsls r6, r2, #2
+ a62: 59f7 ldr r7, [r6, r7]
+ for (uint8_t i = 0; i < node->numEndpoints; i++) {
+ a64: 3201 adds r2, #1
+ EndPoints[lastEp] = node->endpointType[i];
+ a66: 0086 lsls r6, r0, #2
+ lastEp++;
+ a68: 3001 adds r0, #1
+ EndPoints[lastEp] = node->endpointType[i];
+ a6a: 5177 str r7, [r6, r5]
+ for (uint8_t i = 0; i < node->numEndpoints; i++) {
+ a6c: b2d2 uxtb r2, r2
+ lastEp++;
+ a6e: 7058 strb r0, [r3, #1]
+ for (uint8_t i = 0; i < node->numEndpoints; i++) {
+ a70: e7f2 b.n a58 <_ZN13PluggableUSB_4plugEP18PluggableUSBModule+0x28>
+ a72: 0002 movs r2, r0
+ while (current->next) {
+ a74: 68d0 ldr r0, [r2, #12]
+ a76: 2800 cmp r0, #0
+ a78: d1fb bne.n a72 <_ZN13PluggableUSB_4plugEP18PluggableUSBModule+0x42>
+ current->next = node;
+ a7a: 60d1 str r1, [r2, #12]
+ a7c: e7e4 b.n a48 <_ZN13PluggableUSB_4plugEP18PluggableUSBModule+0x18>
+ }
+ return true;
+ a7e: 2001 movs r0, #1
+ // restart USB layer???
+}
+ a80: bdf0 pop {r4, r5, r6, r7, pc}
+ a82: 46c0 nop ; (mov r8, r8)
+ a84: 20000114 .word 0x20000114
+
+00000a88 <_Z12PluggableUSBv>:
+
+PluggableUSB_& PluggableUSB()
+{
+ static PluggableUSB_ obj;
+ a88: 2201 movs r2, #1
+ a8a: 4905 ldr r1, [pc, #20] ; (aa0 <_Z12PluggableUSBv+0x18>)
+ a8c: 4805 ldr r0, [pc, #20] ; (aa4 <_Z12PluggableUSBv+0x1c>)
+ a8e: 680b ldr r3, [r1, #0]
+ a90: 4013 ands r3, r2
+ a92: d103 bne.n a9c <_Z12PluggableUSBv+0x14>
+ return obj;
+}
+
+PluggableUSB_::PluggableUSB_() : lastIf(0), lastEp(1), rootNode(NULL)
+ a94: 7003 strb r3, [r0, #0]
+ a96: 7042 strb r2, [r0, #1]
+ a98: 6043 str r3, [r0, #4]
+ static PluggableUSB_ obj;
+ a9a: 600a str r2, [r1, #0]
+}
+ a9c: 4770 bx lr
+ a9e: 46c0 nop ; (mov r8, r8)
+ aa0: 20000108 .word 0x20000108
+ aa4: 2000010c .word 0x2000010c
+
+00000aa8 <_ZN26DoubleBufferedEPOutHandlerD1Ev>:
+
+ release();
+ }
+
+ virtual ~DoubleBufferedEPOutHandler() {
+ }
+ aa8: 4770 bx lr
+
+00000aaa <_ZN26DoubleBufferedEPOutHandlerD0Ev>:
+ virtual ~DoubleBufferedEPOutHandler() {
+ aaa: b510 push {r4, lr}
+ aac: 0004 movs r4, r0
+ }
+ aae: f001 fa9b bl 1fe8 <_ZdlPv>
+ ab2: 0020 movs r0, r4
+ ab4: bd10 pop {r4, pc}
+ ...
+
+00000ab8 <_ZN14USBDeviceClass6initEPEmm.part.7>:
+ for (uint8_t i = 1; (i < EP_ARRAY_SIZE) && (EndPoints[i] != 0); i++) {
+ initEP(i, EndPoints[i]);
+ }
+}
+
+void USBDeviceClass::initEP(uint32_t ep, uint32_t config)
+ ab8: b5f0 push {r4, r5, r6, r7, lr}
+ if (epHandlers[ep] != NULL) {
+ delete (DoubleBufferedEPOutHandler*)epHandlers[ep];
+ }
+ epHandlers[ep] = new DoubleBufferedEPOutHandler(usbd, ep);
+ }
+ else if (config == (USB_ENDPOINT_TYPE_BULK | USB_ENDPOINT_IN(0)))
+ aba: 2982 cmp r1, #130 ; 0x82
+ abc: d119 bne.n af2 <_ZN14USBDeviceClass6initEPEmm.part.7+0x3a>
+ inline void epBank1SetSize(ep_t ep, uint16_t size) { EP[ep].DeviceDescBank[1].PCKSIZE.bit.SIZE = EP_PCKSIZE_SIZE(size); }
+ abe: b2c3 uxtb r3, r0
+ ac0: 4d29 ldr r5, [pc, #164] ; (b68 <_ZN14USBDeviceClass6initEPEmm.part.7+0xb0>)
+ ac2: 015a lsls r2, r3, #5
+ ac4: 18aa adds r2, r5, r2
+ ac6: 6991 ldr r1, [r2, #24]
+ ac8: 4c28 ldr r4, [pc, #160] ; (b6c <_ZN14USBDeviceClass6initEPEmm.part.7+0xb4>)
+ {
+ usbd.epBank1SetSize(ep, 64);
+ usbd.epBank1SetAddress(ep, &udd_ep_in_cache_buffer[ep]);
+ aca: 0180 lsls r0, r0, #6
+ acc: 400c ands r4, r1
+ ace: 21c0 movs r1, #192 ; 0xc0
+ ad0: 0589 lsls r1, r1, #22
+ ad2: 4321 orrs r1, r4
+ ad4: 6191 str r1, [r2, #24]
+ ad6: 4926 ldr r1, [pc, #152] ; (b70 <_ZN14USBDeviceClass6initEPEmm.part.7+0xb8>)
+ inline void epBank1SetType(ep_t ep, uint8_t type) { usb.DeviceEndpoint[ep].EPCFG.bit.EPTYPE1 = type; }
+ ad8: 3308 adds r3, #8
+ ada: 1808 adds r0, r1, r0
+ adc: 2170 movs r1, #112 ; 0x70
+ inline void epBank1SetAddress(ep_t ep, void *addr) { EP[ep].DeviceDescBank[1].ADDR.reg = (uint32_t)addr; }
+ ade: 6150 str r0, [r2, #20]
+ inline void epBank1SetType(ep_t ep, uint8_t type) { usb.DeviceEndpoint[ep].EPCFG.bit.EPTYPE1 = type; }
+ ae0: 6828 ldr r0, [r5, #0]
+ ae2: 015b lsls r3, r3, #5
+ ae4: 5c1a ldrb r2, [r3, r0]
+ ae6: 438a bics r2, r1
+ ae8: 0011 movs r1, r2
+ aea: 2230 movs r2, #48 ; 0x30
+ aec: 430a orrs r2, r1
+ aee: 541a strb r2, [r3, r0]
+ usbd.epBank1SetType(ep, 1); // CONTROL IN
+
+ // Release OUT EP
+ usbd.epReleaseOutBank0(ep, 64);
+ }
+}
+ af0: bdf0 pop {r4, r5, r6, r7, pc}
+ else if (config == USB_ENDPOINT_TYPE_CONTROL)
+ af2: 2900 cmp r1, #0
+ af4: d1fc bne.n af0 <_ZN14USBDeviceClass6initEPEmm.part.7+0x38>
+ inline void epBank0SetSize(ep_t ep, uint16_t size) { EP[ep].DeviceDescBank[0].PCKSIZE.bit.SIZE = EP_PCKSIZE_SIZE(size); }
+ af6: 26c0 movs r6, #192 ; 0xc0
+ af8: b2c1 uxtb r1, r0
+ afa: 4c1b ldr r4, [pc, #108] ; (b68 <_ZN14USBDeviceClass6initEPEmm.part.7+0xb0>)
+ afc: 014b lsls r3, r1, #5
+ afe: 18e3 adds r3, r4, r3
+ b00: 689a ldr r2, [r3, #8]
+ b02: 4d1a ldr r5, [pc, #104] ; (b6c <_ZN14USBDeviceClass6initEPEmm.part.7+0xb4>)
+ b04: 05b6 lsls r6, r6, #22
+ b06: 402a ands r2, r5
+ b08: 4332 orrs r2, r6
+ b0a: 609a str r2, [r3, #8]
+ usbd.epBank0SetAddress(ep, &udd_ep_out_cache_buffer[ep]);
+ b0c: 4a19 ldr r2, [pc, #100] ; (b74 <_ZN14USBDeviceClass6initEPEmm.part.7+0xbc>)
+ b0e: 0180 lsls r0, r0, #6
+ b10: 1812 adds r2, r2, r0
+ inline void epBank0SetAddress(ep_t ep, void *addr) { EP[ep].DeviceDescBank[0].ADDR.reg = (uint32_t)addr; }
+ b12: 605a str r2, [r3, #4]
+ inline void epBank0SetType(ep_t ep, uint8_t type) { usb.DeviceEndpoint[ep].EPCFG.bit.EPTYPE0 = type; }
+ b14: 000a movs r2, r1
+ b16: 2707 movs r7, #7
+ b18: 6824 ldr r4, [r4, #0]
+ b1a: 3208 adds r2, #8
+ b1c: 0152 lsls r2, r2, #5
+ b1e: 5d11 ldrb r1, [r2, r4]
+ b20: 43b9 bics r1, r7
+ b22: 000f movs r7, r1
+ b24: 2101 movs r1, #1
+ b26: 4339 orrs r1, r7
+ b28: 5511 strb r1, [r2, r4]
+ inline void epBank1SetSize(ep_t ep, uint16_t size) { EP[ep].DeviceDescBank[1].PCKSIZE.bit.SIZE = EP_PCKSIZE_SIZE(size); }
+ b2a: 699f ldr r7, [r3, #24]
+ usbd.epBank1SetAddress(ep, &udd_ep_in_cache_buffer[ep]);
+ b2c: 4910 ldr r1, [pc, #64] ; (b70 <_ZN14USBDeviceClass6initEPEmm.part.7+0xb8>)
+ b2e: 403d ands r5, r7
+ b30: 1808 adds r0, r1, r0
+ b32: 432e orrs r6, r5
+ b34: 619e str r6, [r3, #24]
+ inline void epBank1SetAddress(ep_t ep, void *addr) { EP[ep].DeviceDescBank[1].ADDR.reg = (uint32_t)addr; }
+ b36: 6158 str r0, [r3, #20]
+ inline void epBank1SetType(ep_t ep, uint8_t type) { usb.DeviceEndpoint[ep].EPCFG.bit.EPTYPE1 = type; }
+ b38: 2070 movs r0, #112 ; 0x70
+ b3a: 5d11 ldrb r1, [r2, r4]
+ b3c: 4381 bics r1, r0
+ b3e: 0008 movs r0, r1
+ b40: 2110 movs r1, #16
+ b42: 4301 orrs r1, r0
+ b44: 5511 strb r1, [r2, r4]
+ inline void epBank0SetMultiPacketSize(ep_t ep, uint16_t s) { EP[ep].DeviceDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE = s; }
+ b46: 6899 ldr r1, [r3, #8]
+ b48: 480b ldr r0, [pc, #44] ; (b78 <_ZN14USBDeviceClass6initEPEmm.part.7+0xc0>)
+ inline void epBank0ResetReady(ep_t ep) { usb.DeviceEndpoint[ep].EPSTATUSCLR.bit.BK0RDY = 1; }
+ b4a: 18a2 adds r2, r4, r2
+ inline void epBank0SetMultiPacketSize(ep_t ep, uint16_t s) { EP[ep].DeviceDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE = s; }
+ b4c: 4008 ands r0, r1
+ b4e: 2180 movs r1, #128 ; 0x80
+ b50: 0349 lsls r1, r1, #13
+ b52: 4301 orrs r1, r0
+ b54: 6099 str r1, [r3, #8]
+ inline void epBank0SetByteCount(ep_t ep, uint16_t bc) { EP[ep].DeviceDescBank[0].PCKSIZE.bit.BYTE_COUNT = bc; }
+ b56: 6899 ldr r1, [r3, #8]
+ b58: 0b89 lsrs r1, r1, #14
+ b5a: 0389 lsls r1, r1, #14
+ b5c: 6099 str r1, [r3, #8]
+ inline void epBank0ResetReady(ep_t ep) { usb.DeviceEndpoint[ep].EPSTATUSCLR.bit.BK0RDY = 1; }
+ b5e: 2340 movs r3, #64 ; 0x40
+ b60: 7911 ldrb r1, [r2, #4]
+ b62: 430b orrs r3, r1
+ b64: 7113 strb r3, [r2, #4]
+ b66: e7c3 b.n af0 <_ZN14USBDeviceClass6initEPEmm.part.7+0x38>
+ b68: 200005f4 .word 0x200005f4
+ b6c: 8fffffff .word 0x8fffffff
+ b70: 20000168 .word 0x20000168
+ b74: 20000328 .word 0x20000328
+ b78: f0003fff .word 0xf0003fff
+
+00000b7c <_ZN7__GuardC1Ev>:
+ __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
+ b7c: f3ef 8310 mrs r3, PRIMASK
+ __Guard() : primask(__get_PRIMASK()), loops(1) {
+ b80: 6003 str r3, [r0, #0]
+ b82: 2301 movs r3, #1
+ b84: 6043 str r3, [r0, #4]
+ __ASM volatile ("cpsid i" : : : "memory");
+ b86: b672 cpsid i
+ }
+ b88: 4770 bx lr
+
+00000b8a <_ZN7__GuardD1Ev>:
+ if (primask == 0) {
+ b8a: 6803 ldr r3, [r0, #0]
+ b8c: 2b00 cmp r3, #0
+ b8e: d102 bne.n b96 <_ZN7__GuardD1Ev+0xc>
+ __ASM volatile ("cpsie i" : : : "memory");
+ b90: b662 cpsie i
+ __ASM volatile ("isb 0xF":::"memory");
+ b92: f3bf 8f6f isb sy
+ }
+ b96: 4770 bx lr
+
+00000b98 <_ZNK26DoubleBufferedEPOutHandler10_availableEv>:
+ }
+ }
+ return i;
+ }
+
+ virtual uint32_t _available() const {
+ b98: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr}
+ if (current == 0) {
+ b9a: 0006 movs r6, r0
+ b9c: 36fc adds r6, #252 ; 0xfc
+ b9e: 69b3 ldr r3, [r6, #24]
+ virtual uint32_t _available() const {
+ ba0: 0004 movs r4, r0
+ if (current == 0) {
+ ba2: 2b00 cmp r3, #0
+ ba4: d118 bne.n bd8 <_ZNK26DoubleBufferedEPOutHandler10_availableEv+0x40>
+ bool ready = ready0;
+ ba6: 27b2 movs r7, #178 ; 0xb2
+ ba8: 007f lsls r7, r7, #1
+ baa: 5dc5 ldrb r5, [r0, r7]
+ synchronized {
+ bac: 4668 mov r0, sp
+ bae: f7ff ffe5 bl b7c <_ZN7__GuardC1Ev>
+ bb2: 9b01 ldr r3, [sp, #4]
+ bool ready = ready0;
+ bb4: b2ed uxtb r5, r5
+ synchronized {
+ bb6: 3b01 subs r3, #1
+ bb8: d302 bcc.n bc0 <_ZNK26DoubleBufferedEPOutHandler10_availableEv+0x28>
+ ready = ready0;
+ bba: 5de5 ldrb r5, [r4, r7]
+ bbc: b2ed uxtb r5, r5
+ bbe: e7fa b.n bb6 <_ZNK26DoubleBufferedEPOutHandler10_availableEv+0x1e>
+ synchronized {
+ bc0: 4668 mov r0, sp
+ bc2: 9301 str r3, [sp, #4]
+ bc4: f7ff ffe1 bl b8a <_ZN7__GuardD1Ev>
+ }
+ return ready ? (last0 - first0) : 0;
+ bc8: 2d00 cmp r5, #0
+ bca: d101 bne.n bd0 <_ZNK26DoubleBufferedEPOutHandler10_availableEv+0x38>
+ bcc: 2000 movs r0, #0
+ synchronized {
+ ready = ready1;
+ }
+ return ready ? (last1 - first1) : 0;
+ }
+ }
+ bce: bdfe pop {r1, r2, r3, r4, r5, r6, r7, pc}
+ return ready ? (last0 - first0) : 0;
+ bd0: 6e70 ldr r0, [r6, #100] ; 0x64
+ bd2: 6e33 ldr r3, [r6, #96] ; 0x60
+ return ready ? (last1 - first1) : 0;
+ bd4: 1ac0 subs r0, r0, r3
+ bd6: e7fa b.n bce <_ZNK26DoubleBufferedEPOutHandler10_availableEv+0x36>
+ synchronized {
+ bd8: 4668 mov r0, sp
+ bda: f7ff ffcf bl b7c <_ZN7__GuardC1Ev>
+ ready = ready1;
+ bde: 22d8 movs r2, #216 ; 0xd8
+ bool ready = false;
+ be0: 2500 movs r5, #0
+ be2: 9b01 ldr r3, [sp, #4]
+ ready = ready1;
+ be4: 0052 lsls r2, r2, #1
+ synchronized {
+ be6: 3b01 subs r3, #1
+ be8: d302 bcc.n bf0 <_ZNK26DoubleBufferedEPOutHandler10_availableEv+0x58>
+ ready = ready1;
+ bea: 5ca5 ldrb r5, [r4, r2]
+ bec: b2ed uxtb r5, r5
+ synchronized {
+ bee: e7fa b.n be6 <_ZNK26DoubleBufferedEPOutHandler10_availableEv+0x4e>
+ bf0: 4668 mov r0, sp
+ bf2: 9301 str r3, [sp, #4]
+ bf4: f7ff ffc9 bl b8a <_ZN7__GuardD1Ev>
+ return ready ? (last1 - first1) : 0;
+ bf8: 2d00 cmp r5, #0
+ bfa: d0e7 beq.n bcc <_ZNK26DoubleBufferedEPOutHandler10_availableEv+0x34>
+ bfc: 23d6 movs r3, #214 ; 0xd6
+ bfe: 005b lsls r3, r3, #1
+ c00: 58e0 ldr r0, [r4, r3]
+ c02: 3b04 subs r3, #4
+ c04: 58e3 ldr r3, [r4, r3]
+ c06: e7e5 b.n bd4 <_ZNK26DoubleBufferedEPOutHandler10_availableEv+0x3c>
+
+00000c08 <_ZN26DoubleBufferedEPOutHandler7releaseEv>:
+ virtual int peek() {
+ _recv();
+ return _rx_buffer.peek();
+ }
+
+ void release() {
+ c08: b510 push {r4, lr}
+ usbd.epReleaseOutBank0(ep, size);
+ c0a: 6844 ldr r4, [r0, #4]
+ c0c: 30fc adds r0, #252 ; 0xfc
+ inline void epBank0SetMultiPacketSize(ep_t ep, uint16_t s) { EP[ep].DeviceDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE = s; }
+ c0e: 6943 ldr r3, [r0, #20]
+ c10: 480b ldr r0, [pc, #44] ; (c40 <_ZN26DoubleBufferedEPOutHandler7releaseEv+0x38>)
+ c12: b2db uxtb r3, r3
+ c14: 015a lsls r2, r3, #5
+ c16: 18a2 adds r2, r4, r2
+ c18: 6891 ldr r1, [r2, #8]
+ inline void epBank0ResetReady(ep_t ep) { usb.DeviceEndpoint[ep].EPSTATUSCLR.bit.BK0RDY = 1; }
+ c1a: 3308 adds r3, #8
+ inline void epBank0SetMultiPacketSize(ep_t ep, uint16_t s) { EP[ep].DeviceDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE = s; }
+ c1c: 4008 ands r0, r1
+ c1e: 2180 movs r1, #128 ; 0x80
+ c20: 0349 lsls r1, r1, #13
+ c22: 4301 orrs r1, r0
+ c24: 6091 str r1, [r2, #8]
+ inline void epBank0SetByteCount(ep_t ep, uint16_t bc) { EP[ep].DeviceDescBank[0].PCKSIZE.bit.BYTE_COUNT = bc; }
+ c26: 6891 ldr r1, [r2, #8]
+ inline void epBank0ResetReady(ep_t ep) { usb.DeviceEndpoint[ep].EPSTATUSCLR.bit.BK0RDY = 1; }
+ c28: 015b lsls r3, r3, #5
+ inline void epBank0SetByteCount(ep_t ep, uint16_t bc) { EP[ep].DeviceDescBank[0].PCKSIZE.bit.BYTE_COUNT = bc; }
+ c2a: 0b89 lsrs r1, r1, #14
+ c2c: 0389 lsls r1, r1, #14
+ c2e: 6091 str r1, [r2, #8]
+ inline void epBank0ResetReady(ep_t ep) { usb.DeviceEndpoint[ep].EPSTATUSCLR.bit.BK0RDY = 1; }
+ c30: 6822 ldr r2, [r4, #0]
+ c32: 18d3 adds r3, r2, r3
+ c34: 2240 movs r2, #64 ; 0x40
+ c36: 7919 ldrb r1, [r3, #4]
+ c38: 430a orrs r2, r1
+ c3a: 711a strb r2, [r3, #4]
+ }
+ c3c: bd10 pop {r4, pc}
+ c3e: 46c0 nop ; (mov r8, r8)
+ c40: f0003fff .word 0xf0003fff
+
+00000c44 <_ZN26DoubleBufferedEPOutHandler14handleEndpointEv>:
+ virtual void handleEndpoint()
+ c44: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr}
+ if (usbd.epBank0IsTransferComplete(ep))
+ c46: 0005 movs r5, r0
+ c48: 35fc adds r5, #252 ; 0xfc
+ inline bool epBank0IsTransferComplete(ep_t ep) { return usb.DeviceEndpoint[ep].EPINTFLAG.bit.TRCPT0; }
+ c4a: 7d2b ldrb r3, [r5, #20]
+ if (usbd.epBank0IsTransferComplete(ep))
+ c4c: 6842 ldr r2, [r0, #4]
+ inline bool epBank0IsTransferComplete(ep_t ep) { return usb.DeviceEndpoint[ep].EPINTFLAG.bit.TRCPT0; }
+ c4e: 0019 movs r1, r3
+ virtual void handleEndpoint()
+ c50: 0004 movs r4, r0
+ inline bool epBank0IsTransferComplete(ep_t ep) { return usb.DeviceEndpoint[ep].EPINTFLAG.bit.TRCPT0; }
+ c52: 3108 adds r1, #8
+ c54: 6810 ldr r0, [r2, #0]
+ c56: 0149 lsls r1, r1, #5
+ c58: 1841 adds r1, r0, r1
+ c5a: 79c9 ldrb r1, [r1, #7]
+ if (usbd.epBank0IsTransferComplete(ep))
+ c5c: 07c9 lsls r1, r1, #31
+ c5e: d511 bpl.n c84 <_ZN26DoubleBufferedEPOutHandler14handleEndpointEv+0x40>
+ inline uint16_t epBank0ByteCount(ep_t ep) { return EP[ep].DeviceDescBank[0].PCKSIZE.bit.BYTE_COUNT; }
+ c60: 015b lsls r3, r3, #5
+ c62: 18d2 adds r2, r2, r3
+ c64: 6893 ldr r3, [r2, #8]
+ c66: 049b lsls r3, r3, #18
+ c68: 0c9b lsrs r3, r3, #18
+ if (received == 0) {
+ c6a: d10c bne.n c86 <_ZN26DoubleBufferedEPOutHandler14handleEndpointEv+0x42>
+ release();
+ c6c: 0020 movs r0, r4
+ c6e: f7ff ffcb bl c08 <_ZN26DoubleBufferedEPOutHandler7releaseEv>
+ inline void epAckPendingInterrupts(ep_t ep) { usb.DeviceEndpoint[ep].EPINTFLAG.reg = 0x7F; }
+ c72: 6863 ldr r3, [r4, #4]
+ c74: 681a ldr r2, [r3, #0]
+ c76: 696b ldr r3, [r5, #20]
+ c78: b2db uxtb r3, r3
+ c7a: 3308 adds r3, #8
+ c7c: 015b lsls r3, r3, #5
+ c7e: 18d3 adds r3, r2, r3
+ c80: 227f movs r2, #127 ; 0x7f
+ c82: 71da strb r2, [r3, #7]
+ }
+ c84: bdf7 pop {r0, r1, r2, r4, r5, r6, r7, pc}
+ } else if (incoming == 0) {
+ c86: 69e9 ldr r1, [r5, #28]
+ c88: 2900 cmp r1, #0
+ c8a: d123 bne.n cd4 <_ZN26DoubleBufferedEPOutHandler14handleEndpointEv+0x90>
+ last0 = received;
+ c8c: 666b str r3, [r5, #100] ; 0x64
+ usbd.epBank0SetAddress(ep, const_cast<uint8_t *>(data1));
+ c8e: 0023 movs r3, r4
+ incoming = 1;
+ c90: 2601 movs r6, #1
+ usbd.epBank0SetAddress(ep, const_cast<uint8_t *>(data1));
+ c92: 3369 adds r3, #105 ; 0x69
+ c94: 33ff adds r3, #255 ; 0xff
+ incoming = 1;
+ c96: 61ee str r6, [r5, #28]
+ synchronized {
+ c98: 4668 mov r0, sp
+ inline void epBank0SetAddress(ep_t ep, void *addr) { EP[ep].DeviceDescBank[0].ADDR.reg = (uint32_t)addr; }
+ c9a: 6053 str r3, [r2, #4]
+ ready0 = true;
+ c9c: 27b2 movs r7, #178 ; 0xb2
+ synchronized {
+ c9e: f7ff ff6d bl b7c <_ZN7__GuardC1Ev>
+ ready0 = true;
+ ca2: 007f lsls r7, r7, #1
+ notify = ready1;
+ ca4: 21b2 movs r1, #178 ; 0xb2
+ ca6: 9b01 ldr r3, [sp, #4]
+ ca8: 31ff adds r1, #255 ; 0xff
+ caa: 3b01 subs r3, #1
+ synchronized {
+ cac: 1c5a adds r2, r3, #1
+ cae: d038 beq.n d22 <_ZN26DoubleBufferedEPOutHandler14handleEndpointEv+0xde>
+ notify = ready1;
+ cb0: 22d8 movs r2, #216 ; 0xd8
+ ready0 = true;
+ cb2: 55e6 strb r6, [r4, r7]
+ notify = ready1;
+ cb4: 0052 lsls r2, r2, #1
+ cb6: 5ca2 ldrb r2, [r4, r2]
+ cb8: 1e58 subs r0, r3, #1
+ cba: b2d2 uxtb r2, r2
+ cbc: 5462 strb r2, [r4, r1]
+ if (!notify) {
+ cbe: 5c62 ldrb r2, [r4, r1]
+ cc0: 4684 mov ip, r0
+ cc2: 2a00 cmp r2, #0
+ cc4: d104 bne.n cd0 <_ZN26DoubleBufferedEPOutHandler14handleEndpointEv+0x8c>
+ release();
+ cc6: 0020 movs r0, r4
+ cc8: 9301 str r3, [sp, #4]
+ cca: f7ff ff9d bl c08 <_ZN26DoubleBufferedEPOutHandler7releaseEv>
+ cce: e7e9 b.n ca4 <_ZN26DoubleBufferedEPOutHandler14handleEndpointEv+0x60>
+ cd0: 4663 mov r3, ip
+ cd2: e7eb b.n cac <_ZN26DoubleBufferedEPOutHandler14handleEndpointEv+0x68>
+ last1 = received;
+ cd4: 21d6 movs r1, #214 ; 0xd6
+ cd6: 0049 lsls r1, r1, #1
+ cd8: 5063 str r3, [r4, r1]
+ incoming = 0;
+ cda: 2300 movs r3, #0
+ cdc: 61eb str r3, [r5, #28]
+ usbd.epBank0SetAddress(ep, const_cast<uint8_t *>(data0));
+ cde: 0023 movs r3, r4
+ ce0: 331d adds r3, #29
+ ce2: 33ff adds r3, #255 ; 0xff
+ inline void epBank0SetAddress(ep_t ep, void *addr) { EP[ep].DeviceDescBank[0].ADDR.reg = (uint32_t)addr; }
+ ce4: 6053 str r3, [r2, #4]
+ synchronized {
+ ce6: 4668 mov r0, sp
+ ready1 = true;
+ ce8: 26d8 movs r6, #216 ; 0xd8
+ synchronized {
+ cea: f7ff ff47 bl b7c <_ZN7__GuardC1Ev>
+ ready1 = true;
+ cee: 2701 movs r7, #1
+ cf0: 0076 lsls r6, r6, #1
+ notify = ready0;
+ cf2: 21b2 movs r1, #178 ; 0xb2
+ cf4: 9b01 ldr r3, [sp, #4]
+ cf6: 31ff adds r1, #255 ; 0xff
+ cf8: 3b01 subs r3, #1
+ synchronized {
+ cfa: 1c5a adds r2, r3, #1
+ cfc: d011 beq.n d22 <_ZN26DoubleBufferedEPOutHandler14handleEndpointEv+0xde>
+ notify = ready0;
+ cfe: 22b2 movs r2, #178 ; 0xb2
+ ready1 = true;
+ d00: 55a7 strb r7, [r4, r6]
+ notify = ready0;
+ d02: 0052 lsls r2, r2, #1
+ d04: 5ca2 ldrb r2, [r4, r2]
+ d06: 1e58 subs r0, r3, #1
+ d08: b2d2 uxtb r2, r2
+ d0a: 5462 strb r2, [r4, r1]
+ if (!notify) {
+ d0c: 5c62 ldrb r2, [r4, r1]
+ d0e: 4684 mov ip, r0
+ d10: 2a00 cmp r2, #0
+ d12: d104 bne.n d1e <_ZN26DoubleBufferedEPOutHandler14handleEndpointEv+0xda>
+ release();
+ d14: 0020 movs r0, r4
+ d16: 9301 str r3, [sp, #4]
+ d18: f7ff ff76 bl c08 <_ZN26DoubleBufferedEPOutHandler7releaseEv>
+ d1c: e7e9 b.n cf2 <_ZN26DoubleBufferedEPOutHandler14handleEndpointEv+0xae>
+ d1e: 4663 mov r3, ip
+ d20: e7eb b.n cfa <_ZN26DoubleBufferedEPOutHandler14handleEndpointEv+0xb6>
+ synchronized {
+ d22: 4668 mov r0, sp
+ d24: 9301 str r3, [sp, #4]
+ d26: f7ff ff30 bl b8a <_ZN7__GuardD1Ev>
+ d2a: e7a2 b.n c72 <_ZN26DoubleBufferedEPOutHandler14handleEndpointEv+0x2e>
+
+00000d2c <_ZN26DoubleBufferedEPOutHandler5_recvEv>:
+ uint32_t _recv()
+ d2c: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr}
+ d2e: 0005 movs r5, r0
+ synchronized {
+ d30: 4668 mov r0, sp
+ d32: 002c movs r4, r5
+ d34: f7ff ff22 bl b7c <_ZN7__GuardC1Ev>
+ uint32_t len = 0;
+ d38: 2700 movs r7, #0
+
+template <int N>
+int RingBufferN<N>::availableForStore()
+{
+ if (_iHead >= _iTail)
+ return N - 1 - _iHead + _iTail;
+ d3a: 22ff movs r2, #255 ; 0xff
+ d3c: 9b01 ldr r3, [sp, #4]
+ d3e: 34fc adds r4, #252 ; 0xfc
+ synchronized {
+ d40: 3b01 subs r3, #1
+ d42: d30d bcc.n d60 <_ZN26DoubleBufferedEPOutHandler5_recvEv+0x34>
+ if (_iHead >= _iTail)
+ d44: 68e0 ldr r0, [r4, #12]
+ d46: 6921 ldr r1, [r4, #16]
+ d48: 4288 cmp r0, r1
+ d4a: db04 blt.n d56 <_ZN26DoubleBufferedEPOutHandler5_recvEv+0x2a>
+ return N - 1 - _iHead + _iTail;
+ d4c: 68e7 ldr r7, [r4, #12]
+ d4e: 6920 ldr r0, [r4, #16]
+ d50: 1bd7 subs r7, r2, r7
+ d52: 183f adds r7, r7, r0
+ d54: e7f4 b.n d40 <_ZN26DoubleBufferedEPOutHandler5_recvEv+0x14>
+ else
+ return _iTail - _iHead - 1;
+ d56: 6927 ldr r7, [r4, #16]
+ d58: 68e1 ldr r1, [r4, #12]
+ d5a: 1a7f subs r7, r7, r1
+ d5c: 3f01 subs r7, #1
+ d5e: e7ef b.n d40 <_ZN26DoubleBufferedEPOutHandler5_recvEv+0x14>
+ d60: 4668 mov r0, sp
+ d62: 9301 str r3, [sp, #4]
+ d64: f7ff ff11 bl b8a <_ZN7__GuardD1Ev>
+ if (current == 0) {
+ d68: 69a3 ldr r3, [r4, #24]
+ synchronized {
+ d6a: 4668 mov r0, sp
+ if (current == 0) {
+ d6c: 2b00 cmp r3, #0
+ d6e: d141 bne.n df4 <_ZN26DoubleBufferedEPOutHandler5_recvEv+0xc8>
+ synchronized {
+ d70: f7ff ff04 bl b7c <_ZN7__GuardC1Ev>
+ if (!ready0) {
+ d74: 21b2 movs r1, #178 ; 0xb2
+ d76: 9b01 ldr r3, [sp, #4]
+ d78: 0049 lsls r1, r1, #1
+ d7a: 3b01 subs r3, #1
+ synchronized {
+ d7c: 1c5a adds r2, r3, #1
+ d7e: d00c beq.n d9a <_ZN26DoubleBufferedEPOutHandler5_recvEv+0x6e>
+ if (!ready0) {
+ d80: 5c6e ldrb r6, [r5, r1]
+ d82: 1e5a subs r2, r3, #1
+ d84: b2f6 uxtb r6, r6
+ d86: 2e00 cmp r6, #0
+ d88: d105 bne.n d96 <_ZN26DoubleBufferedEPOutHandler5_recvEv+0x6a>
+ synchronized {
+ d8a: 4668 mov r0, sp
+ d8c: 9301 str r3, [sp, #4]
+ d8e: f7ff fefc bl b8a <_ZN7__GuardD1Ev>
+ }
+ d92: 0030 movs r0, r6
+ d94: bdfe pop {r1, r2, r3, r4, r5, r6, r7, pc}
+ d96: 0013 movs r3, r2
+ d98: e7f0 b.n d7c <_ZN26DoubleBufferedEPOutHandler5_recvEv+0x50>
+ synchronized {
+ d9a: 4668 mov r0, sp
+ d9c: 9301 str r3, [sp, #4]
+ uint32_t i = 0;
+ d9e: 2600 movs r6, #0
+ synchronized {
+ da0: f7ff fef3 bl b8a <_ZN7__GuardD1Ev>
+}
+
+template <int N>
+int RingBufferN<N>::nextIndex(int index)
+{
+ return (uint32_t)(index + 1) % N;
+ da4: 22ff movs r2, #255 ; 0xff
+ for (; i<len && first0 < last0; i++) {
+ da6: 42be cmp r6, r7
+ da8: d003 beq.n db2 <_ZN26DoubleBufferedEPOutHandler5_recvEv+0x86>
+ daa: 6e23 ldr r3, [r4, #96] ; 0x60
+ dac: 6e61 ldr r1, [r4, #100] ; 0x64
+ dae: 428b cmp r3, r1
+ db0: d360 bcc.n e74 <_ZN26DoubleBufferedEPOutHandler5_recvEv+0x148>
+ if (first0 == last0) {
+ db2: 6e63 ldr r3, [r4, #100] ; 0x64
+ db4: 6e22 ldr r2, [r4, #96] ; 0x60
+ db6: 429a cmp r2, r3
+ db8: d1eb bne.n d92 <_ZN26DoubleBufferedEPOutHandler5_recvEv+0x66>
+ first0 = 0;
+ dba: 2300 movs r3, #0
+ dbc: 6623 str r3, [r4, #96] ; 0x60
+ current = 1;
+ dbe: 3301 adds r3, #1
+ dc0: 61a3 str r3, [r4, #24]
+ synchronized {
+ dc2: 4668 mov r0, sp
+ ready0 = false;
+ dc4: 24b2 movs r4, #178 ; 0xb2
+ synchronized {
+ dc6: f7ff fed9 bl b7c <_ZN7__GuardC1Ev>
+ ready0 = false;
+ dca: 0064 lsls r4, r4, #1
+ if (notify) {
+ dcc: 22b2 movs r2, #178 ; 0xb2
+ ready0 = false;
+ dce: 2100 movs r1, #0
+ dd0: 9b01 ldr r3, [sp, #4]
+ if (notify) {
+ dd2: 32ff adds r2, #255 ; 0xff
+ dd4: 3b01 subs r3, #1
+ synchronized {
+ dd6: 1c58 adds r0, r3, #1
+ dd8: d0d7 beq.n d8a <_ZN26DoubleBufferedEPOutHandler5_recvEv+0x5e>
+ ready0 = false;
+ dda: 5529 strb r1, [r5, r4]
+ if (notify) {
+ ddc: 5ca8 ldrb r0, [r5, r2]
+ dde: 1e5f subs r7, r3, #1
+ de0: 2800 cmp r0, #0
+ de2: d005 beq.n df0 <_ZN26DoubleBufferedEPOutHandler5_recvEv+0xc4>
+ notify = false;
+ de4: 54a9 strb r1, [r5, r2]
+ release();
+ de6: 0028 movs r0, r5
+ de8: 9301 str r3, [sp, #4]
+ dea: f7ff ff0d bl c08 <_ZN26DoubleBufferedEPOutHandler7releaseEv>
+ dee: e7ed b.n dcc <_ZN26DoubleBufferedEPOutHandler5_recvEv+0xa0>
+ df0: 003b movs r3, r7
+ df2: e7f0 b.n dd6 <_ZN26DoubleBufferedEPOutHandler5_recvEv+0xaa>
+ synchronized {
+ df4: f7ff fec2 bl b7c <_ZN7__GuardC1Ev>
+ if (!ready1) {
+ df8: 21d8 movs r1, #216 ; 0xd8
+ dfa: 9b01 ldr r3, [sp, #4]
+ dfc: 0049 lsls r1, r1, #1
+ dfe: 3b01 subs r3, #1
+ synchronized {
+ e00: 1c5a adds r2, r3, #1
+ e02: d006 beq.n e12 <_ZN26DoubleBufferedEPOutHandler5_recvEv+0xe6>
+ if (!ready1) {
+ e04: 5c6e ldrb r6, [r5, r1]
+ e06: 1e5a subs r2, r3, #1
+ e08: b2f6 uxtb r6, r6
+ e0a: 2e00 cmp r6, #0
+ e0c: d0bd beq.n d8a <_ZN26DoubleBufferedEPOutHandler5_recvEv+0x5e>
+ e0e: 0013 movs r3, r2
+ e10: e7f6 b.n e00 <_ZN26DoubleBufferedEPOutHandler5_recvEv+0xd4>
+ synchronized {
+ e12: 4668 mov r0, sp
+ e14: 9301 str r3, [sp, #4]
+ e16: f7ff feb8 bl b8a <_ZN7__GuardD1Ev>
+ e1a: 22d4 movs r2, #212 ; 0xd4
+ uint32_t i = 0;
+ e1c: 2600 movs r6, #0
+ e1e: 0052 lsls r2, r2, #1
+ for (; i<len && first1 < last1; i++) {
+ e20: 42be cmp r6, r7
+ e22: d005 beq.n e30 <_ZN26DoubleBufferedEPOutHandler5_recvEv+0x104>
+ e24: 21d6 movs r1, #214 ; 0xd6
+ e26: 0049 lsls r1, r1, #1
+ e28: 58ab ldr r3, [r5, r2]
+ e2a: 5869 ldr r1, [r5, r1]
+ e2c: 428b cmp r3, r1
+ e2e: d332 bcc.n e96 <_ZN26DoubleBufferedEPOutHandler5_recvEv+0x16a>
+ if (first1 == last1) {
+ e30: 23d6 movs r3, #214 ; 0xd6
+ e32: 005b lsls r3, r3, #1
+ e34: 58eb ldr r3, [r5, r3]
+ e36: 58a9 ldr r1, [r5, r2]
+ e38: 4299 cmp r1, r3
+ e3a: d1aa bne.n d92 <_ZN26DoubleBufferedEPOutHandler5_recvEv+0x66>
+ first1 = 0;
+ e3c: 2300 movs r3, #0
+ synchronized {
+ e3e: 4668 mov r0, sp
+ first1 = 0;
+ e40: 50ab str r3, [r5, r2]
+ current = 0;
+ e42: 61a3 str r3, [r4, #24]
+ ready1 = false;
+ e44: 24d8 movs r4, #216 ; 0xd8
+ synchronized {
+ e46: f7ff fe99 bl b7c <_ZN7__GuardC1Ev>
+ ready1 = false;
+ e4a: 0064 lsls r4, r4, #1
+ if (notify) {
+ e4c: 22b2 movs r2, #178 ; 0xb2
+ ready1 = false;
+ e4e: 2100 movs r1, #0
+ e50: 9b01 ldr r3, [sp, #4]
+ if (notify) {
+ e52: 32ff adds r2, #255 ; 0xff
+ e54: 3b01 subs r3, #1
+ synchronized {
+ e56: 1c58 adds r0, r3, #1
+ e58: d097 beq.n d8a <_ZN26DoubleBufferedEPOutHandler5_recvEv+0x5e>
+ ready1 = false;
+ e5a: 5529 strb r1, [r5, r4]
+ if (notify) {
+ e5c: 5ca8 ldrb r0, [r5, r2]
+ e5e: 1e5f subs r7, r3, #1
+ e60: 2800 cmp r0, #0
+ e62: d005 beq.n e70 <_ZN26DoubleBufferedEPOutHandler5_recvEv+0x144>
+ notify = false;
+ e64: 54a9 strb r1, [r5, r2]
+ release();
+ e66: 0028 movs r0, r5
+ e68: 9301 str r3, [sp, #4]
+ e6a: f7ff fecd bl c08 <_ZN26DoubleBufferedEPOutHandler7releaseEv>
+ e6e: e7ed b.n e4c <_ZN26DoubleBufferedEPOutHandler5_recvEv+0x120>
+ e70: 003b movs r3, r7
+ e72: e7f0 b.n e56 <_ZN26DoubleBufferedEPOutHandler5_recvEv+0x12a>
+ _rx_buffer.store_char(data0[first0++]);
+ e74: 1c59 adds r1, r3, #1
+ e76: 18eb adds r3, r5, r3
+ e78: 33ff adds r3, #255 ; 0xff
+ e7a: 6621 str r1, [r4, #96] ; 0x60
+ e7c: 7f59 ldrb r1, [r3, #29]
+ int i = nextIndex(_iHead);
+ e7e: 68e3 ldr r3, [r4, #12]
+ if ( i != _iTail )
+ e80: 6920 ldr r0, [r4, #16]
+ return (uint32_t)(index + 1) % N;
+ e82: 3301 adds r3, #1
+ e84: 4013 ands r3, r2
+ if ( i != _iTail )
+ e86: 4283 cmp r3, r0
+ e88: d003 beq.n e92 <_ZN26DoubleBufferedEPOutHandler5_recvEv+0x166>
+ _aucBuffer[_iHead] = c ;
+ e8a: 68e0 ldr r0, [r4, #12]
+ e8c: 1828 adds r0, r5, r0
+ e8e: 7201 strb r1, [r0, #8]
+ _iHead = i ;
+ e90: 60e3 str r3, [r4, #12]
+ for (; i<len && first0 < last0; i++) {
+ e92: 3601 adds r6, #1
+ e94: e787 b.n da6 <_ZN26DoubleBufferedEPOutHandler5_recvEv+0x7a>
+ _rx_buffer.store_char(data1[first1++]);
+ e96: 1c59 adds r1, r3, #1
+ e98: 50a9 str r1, [r5, r2]
+ return (uint32_t)(index + 1) % N;
+ e9a: 21ff movs r1, #255 ; 0xff
+ e9c: 18eb adds r3, r5, r3
+ e9e: 3369 adds r3, #105 ; 0x69
+ ea0: 33ff adds r3, #255 ; 0xff
+ ea2: 781b ldrb r3, [r3, #0]
+ ea4: 469c mov ip, r3
+ int i = nextIndex(_iHead);
+ ea6: 68e3 ldr r3, [r4, #12]
+ return (uint32_t)(index + 1) % N;
+ ea8: 3301 adds r3, #1
+ eaa: 400b ands r3, r1
+ if ( i != _iTail )
+ eac: 6921 ldr r1, [r4, #16]
+ eae: 428b cmp r3, r1
+ eb0: d004 beq.n ebc <_ZN26DoubleBufferedEPOutHandler5_recvEv+0x190>
+ _aucBuffer[_iHead] = c ;
+ eb2: 4660 mov r0, ip
+ eb4: 68e1 ldr r1, [r4, #12]
+ eb6: 1869 adds r1, r5, r1
+ eb8: 7208 strb r0, [r1, #8]
+ _iHead = i ;
+ eba: 60e3 str r3, [r4, #12]
+ for (; i<len && first1 < last1; i++) {
+ ebc: 3601 adds r6, #1
+ ebe: e7af b.n e20 <_ZN26DoubleBufferedEPOutHandler5_recvEv+0xf4>
+
+00000ec0 <_ZN26DoubleBufferedEPOutHandler4peekEv>:
+ virtual int peek() {
+ ec0: b510 push {r4, lr}
+ ec2: 0004 movs r4, r0
+ _recv();
+ ec4: f7ff ff32 bl d2c <_ZN26DoubleBufferedEPOutHandler5_recvEv>
+ if(_iTail == _iHead)
+ ec8: 0023 movs r3, r4
+ eca: 33fc adds r3, #252 ; 0xfc
+ ecc: 6919 ldr r1, [r3, #16]
+ ece: 68da ldr r2, [r3, #12]
+ ed0: 4291 cmp r1, r2
+ ed2: d003 beq.n edc <_ZN26DoubleBufferedEPOutHandler4peekEv+0x1c>
+ return _aucBuffer[_iTail];
+ ed4: 691b ldr r3, [r3, #16]
+ ed6: 18e4 adds r4, r4, r3
+ ed8: 7a20 ldrb r0, [r4, #8]
+ }
+ eda: bd10 pop {r4, pc}
+ return -1;
+ edc: 2001 movs r0, #1
+ ede: 4240 negs r0, r0
+ return _rx_buffer.peek();
+ ee0: e7fb b.n eda <_ZN26DoubleBufferedEPOutHandler4peekEv+0x1a>
+
+00000ee2 <_ZN26DoubleBufferedEPOutHandler9availableEv>:
+ virtual uint32_t available() {
+ ee2: b510 push {r4, lr}
+ ee4: 0004 movs r4, r0
+ int delta = _iHead - _iTail;
+ ee6: 34fc adds r4, #252 ; 0xfc
+ _recv();
+ ee8: f7ff ff20 bl d2c <_ZN26DoubleBufferedEPOutHandler5_recvEv>
+ eec: 68e0 ldr r0, [r4, #12]
+ eee: 6923 ldr r3, [r4, #16]
+ ef0: 1ac0 subs r0, r0, r3
+ if(delta < 0)
+ ef2: d501 bpl.n ef8 <_ZN26DoubleBufferedEPOutHandler9availableEv+0x16>
+ return N + delta;
+ ef4: 3001 adds r0, #1
+ ef6: 30ff adds r0, #255 ; 0xff
+ }
+ ef8: bd10 pop {r4, pc}
+
+00000efa <_ZN26DoubleBufferedEPOutHandler4recvEPvm>:
+ virtual uint32_t recv(void *_data, uint32_t len) {
+ efa: b5f0 push {r4, r5, r6, r7, lr}
+ efc: b085 sub sp, #20
+ efe: 9201 str r2, [sp, #4]
+ f00: 9100 str r1, [sp, #0]
+ f02: 0005 movs r5, r0
+ _recv();
+ f04: f7ff ff12 bl d2c <_ZN26DoubleBufferedEPOutHandler5_recvEv>
+ synchronized {
+ f08: a802 add r0, sp, #8
+ f0a: f7ff fe37 bl b7c <_ZN7__GuardC1Ev>
+ return -1;
+ f0e: 2001 movs r0, #1
+ uint32_t i = 0;
+ f10: 2400 movs r4, #0
+ return (uint32_t)(index + 1) % N;
+ f12: 26ff movs r6, #255 ; 0xff
+ f14: 9a03 ldr r2, [sp, #12]
+ return -1;
+ f16: 4240 negs r0, r0
+ synchronized {
+ f18: 3a01 subs r2, #1
+ f1a: d31d bcc.n f58 <_ZN26DoubleBufferedEPOutHandler4recvEPvm+0x5e>
+ int delta = _iHead - _iTail;
+ f1c: 002b movs r3, r5
+ f1e: 33fc adds r3, #252 ; 0xfc
+ for (; i < len && _rx_buffer.available(); i++) {
+ f20: 9901 ldr r1, [sp, #4]
+ f22: 428c cmp r4, r1
+ f24: d2f8 bcs.n f18 <_ZN26DoubleBufferedEPOutHandler4recvEPvm+0x1e>
+ f26: 68d9 ldr r1, [r3, #12]
+ f28: 691f ldr r7, [r3, #16]
+ f2a: 1bc9 subs r1, r1, r7
+ if(delta < 0)
+ f2c: d501 bpl.n f32 <_ZN26DoubleBufferedEPOutHandler4recvEPvm+0x38>
+ return N + delta;
+ f2e: 3101 adds r1, #1
+ f30: 31ff adds r1, #255 ; 0xff
+ f32: 2900 cmp r1, #0
+ f34: d0f0 beq.n f18 <_ZN26DoubleBufferedEPOutHandler4recvEPvm+0x1e>
+ if(_iTail == _iHead)
+ f36: 6919 ldr r1, [r3, #16]
+ f38: 68df ldr r7, [r3, #12]
+ f3a: 468c mov ip, r1
+ return -1;
+ f3c: 0001 movs r1, r0
+ if(_iTail == _iHead)
+ f3e: 45bc cmp ip, r7
+ f40: d006 beq.n f50 <_ZN26DoubleBufferedEPOutHandler4recvEPvm+0x56>
+ uint8_t value = _aucBuffer[_iTail];
+ f42: 6919 ldr r1, [r3, #16]
+ _iTail = nextIndex(_iTail);
+ f44: 691f ldr r7, [r3, #16]
+ uint8_t value = _aucBuffer[_iTail];
+ f46: 1869 adds r1, r5, r1
+ return (uint32_t)(index + 1) % N;
+ f48: 3701 adds r7, #1
+ f4a: 4037 ands r7, r6
+ uint8_t value = _aucBuffer[_iTail];
+ f4c: 7a09 ldrb r1, [r1, #8]
+ _iTail = nextIndex(_iTail);
+ f4e: 611f str r7, [r3, #16]
+ data[i] = _rx_buffer.read_char();
+ f50: 9f00 ldr r7, [sp, #0]
+ f52: 5539 strb r1, [r7, r4]
+ for (; i < len && _rx_buffer.available(); i++) {
+ f54: 3401 adds r4, #1
+ f56: e7e3 b.n f20 <_ZN26DoubleBufferedEPOutHandler4recvEPvm+0x26>
+ synchronized {
+ f58: a802 add r0, sp, #8
+ f5a: 9203 str r2, [sp, #12]
+ f5c: f7ff fe15 bl b8a <_ZN7__GuardD1Ev>
+ }
+ f60: 0020 movs r0, r4
+ f62: b005 add sp, #20
+ f64: bdf0 pop {r4, r5, r6, r7, pc}
+
+00000f66 <_ZN14USBDeviceClass14SendInterfacesEPm>:
+{
+ f66: b537 push {r0, r1, r2, r4, r5, lr}
+ uint8_t interfaces = 0;
+ f68: 466b mov r3, sp
+ f6a: 1ddc adds r4, r3, #7
+ f6c: 2300 movs r3, #0
+{
+ f6e: 000d movs r5, r1
+ uint8_t interfaces = 0;
+ f70: 7023 strb r3, [r4, #0]
+ total[0] += PluggableUSB().getInterface(&interfaces);
+ f72: f7ff fd89 bl a88 <_Z12PluggableUSBv>
+ f76: 0021 movs r1, r4
+ f78: f7ff fd06 bl 988 <_ZN13PluggableUSB_12getInterfaceEPh>
+ f7c: 682b ldr r3, [r5, #0]
+ f7e: 1818 adds r0, r3, r0
+ f80: 6028 str r0, [r5, #0]
+ return interfaces;
+ f82: 7820 ldrb r0, [r4, #0]
+}
+ f84: bd3e pop {r1, r2, r3, r4, r5, pc}
+ ...
+
+00000f88 <_ZN14USBDeviceClass4initEv>:
+{
+ f88: b5f8 push {r3, r4, r5, r6, r7, lr}
+ PM->APBBMASK.reg |= PM_APBBMASK_USB;
+ f8a: 2320 movs r3, #32
+ f8c: 4a3e ldr r2, [pc, #248] ; (1088 <_ZN14USBDeviceClass4initEv+0x100>)
+{
+ f8e: 0005 movs r5, r0
+ PM->APBBMASK.reg |= PM_APBBMASK_USB;
+ f90: 69d1 ldr r1, [r2, #28]
+ PORT->Group[0].PMUX[PIN_PA24G_USB_DM/2].reg &= ~(0xF << (4 * (PIN_PA24G_USB_DM & 0x01u)));
+ f92: 200f movs r0, #15
+ PM->APBBMASK.reg |= PM_APBBMASK_USB;
+ f94: 430b orrs r3, r1
+ f96: 61d3 str r3, [r2, #28]
+ PORT->Group[0].PINCFG[PIN_PA24G_USB_DM].bit.PMUXEN = 1;
+ f98: 2201 movs r2, #1
+ f9a: 493c ldr r1, [pc, #240] ; (108c <_ZN14USBDeviceClass4initEv+0x104>)
+ f9c: 780b ldrb r3, [r1, #0]
+ f9e: 4313 orrs r3, r2
+ fa0: 700b strb r3, [r1, #0]
+ PORT->Group[0].PMUX[PIN_PA24G_USB_DM/2].reg &= ~(0xF << (4 * (PIN_PA24G_USB_DM & 0x01u)));
+ fa2: 4b3b ldr r3, [pc, #236] ; (1090 <_ZN14USBDeviceClass4initEv+0x108>)
+ fa4: 7819 ldrb r1, [r3, #0]
+ fa6: 4381 bics r1, r0
+ fa8: 7019 strb r1, [r3, #0]
+ PORT->Group[0].PMUX[PIN_PA24G_USB_DM/2].reg |= MUX_PA24G_USB_DM << (4 * (PIN_PA24G_USB_DM & 0x01u));
+ faa: 2106 movs r1, #6
+ fac: 781c ldrb r4, [r3, #0]
+ fae: 4321 orrs r1, r4
+ fb0: 7019 strb r1, [r3, #0]
+ PORT->Group[0].PINCFG[PIN_PA25G_USB_DP].bit.PMUXEN = 1;
+ fb2: 4938 ldr r1, [pc, #224] ; (1094 <_ZN14USBDeviceClass4initEv+0x10c>)
+ fb4: 780c ldrb r4, [r1, #0]
+ fb6: 4322 orrs r2, r4
+ fb8: 700a strb r2, [r1, #0]
+ PORT->Group[0].PMUX[PIN_PA25G_USB_DP/2].reg &= ~(0xF << (4 * (PIN_PA25G_USB_DP & 0x01u)));
+ fba: 781a ldrb r2, [r3, #0]
+ fbc: 4002 ands r2, r0
+ fbe: 701a strb r2, [r3, #0]
+ PORT->Group[0].PMUX[PIN_PA25G_USB_DP/2].reg |= MUX_PA25G_USB_DP << (4 * (PIN_PA25G_USB_DP & 0x01u));
+ fc0: 2260 movs r2, #96 ; 0x60
+ fc2: 7819 ldrb r1, [r3, #0]
+ fc4: 430a orrs r2, r1
+ fc6: 701a strb r2, [r3, #0]
+ GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID(6) | // Generic Clock Multiplexer 6
+ fc8: 4b33 ldr r3, [pc, #204] ; (1098 <_ZN14USBDeviceClass4initEv+0x110>)
+ fca: 4a34 ldr r2, [pc, #208] ; (109c <_ZN14USBDeviceClass4initEv+0x114>)
+ fcc: 805a strh r2, [r3, #2]
+ while (GCLK->STATUS.bit.SYNCBUSY)
+ fce: 785f ldrb r7, [r3, #1]
+ fd0: 09ff lsrs r7, r7, #7
+ fd2: d1fc bne.n fce <_ZN14USBDeviceClass4initEv+0x46>
+ USB_SetHandler(&UDD_Handler);
+ fd4: 4832 ldr r0, [pc, #200] ; (10a0 <_ZN14USBDeviceClass4initEv+0x118>)
+ fd6: f7ff f8ff bl 1d8 <USB_SetHandler>
+ usb.CTRLA.bit.SWRST = 1;
+ fda: 4e32 ldr r6, [pc, #200] ; (10a4 <_ZN14USBDeviceClass4initEv+0x11c>)
+ fdc: 2301 movs r3, #1
+ fde: 0030 movs r0, r6
+ fe0: c810 ldmia r0!, {r4}
+ memset(EP, 0, sizeof(EP));
+ fe2: 0039 movs r1, r7
+ usb.CTRLA.bit.SWRST = 1;
+ fe4: 7822 ldrb r2, [r4, #0]
+ fe6: 4313 orrs r3, r2
+ memset(EP, 0, sizeof(EP));
+ fe8: 2280 movs r2, #128 ; 0x80
+ usb.CTRLA.bit.SWRST = 1;
+ fea: 7023 strb r3, [r4, #0]
+ memset(EP, 0, sizeof(EP));
+ fec: 0052 lsls r2, r2, #1
+ fee: f001 fc1c bl 282a <memset>
+ while (usb.SYNCBUSY.bit.SWRST) {}
+ ff2: 78a3 ldrb r3, [r4, #2]
+ ff4: 07db lsls r3, r3, #31
+ ff6: d4fc bmi.n ff2 <_ZN14USBDeviceClass4initEv+0x6a>
+ uint32_t pad_transn = (*pad_transn_p & USB_FUSES_TRANSN_Msk) >> USB_FUSES_TRANSN_Pos;
+ ff8: 201f movs r0, #31
+ usb.DESCADD.reg = (uint32_t)(&EP);
+ ffa: 3604 adds r6, #4
+ uint32_t pad_transn = (*pad_transn_p & USB_FUSES_TRANSN_Msk) >> USB_FUSES_TRANSN_Pos;
+ ffc: 4b2a ldr r3, [pc, #168] ; (10a8 <_ZN14USBDeviceClass4initEv+0x120>)
+ usb.DESCADD.reg = (uint32_t)(&EP);
+ ffe: 6266 str r6, [r4, #36] ; 0x24
+ uint32_t pad_transn = (*pad_transn_p & USB_FUSES_TRANSN_Msk) >> USB_FUSES_TRANSN_Pos;
+ 1000: 681b ldr r3, [r3, #0]
+ 1002: 0b5a lsrs r2, r3, #13
+ uint32_t pad_transp = (*pad_transp_p & USB_FUSES_TRANSP_Msk) >> USB_FUSES_TRANSP_Pos;
+ 1004: 0c99 lsrs r1, r3, #18
+ uint32_t pad_trim = (*pad_trim_p & USB_FUSES_TRIM_Msk ) >> USB_FUSES_TRIM_Pos;
+ 1006: 019b lsls r3, r3, #6
+ uint32_t pad_transn = (*pad_transn_p & USB_FUSES_TRANSN_Msk) >> USB_FUSES_TRANSN_Pos;
+ 1008: 4002 ands r2, r0
+ uint32_t pad_transp = (*pad_transp_p & USB_FUSES_TRANSP_Msk) >> USB_FUSES_TRANSP_Pos;
+ 100a: 4001 ands r1, r0
+ uint32_t pad_trim = (*pad_trim_p & USB_FUSES_TRIM_Msk ) >> USB_FUSES_TRIM_Pos;
+ 100c: 0f5b lsrs r3, r3, #29
+ if (pad_transn == 0x1F) // maximum value (31)
+ 100e: 4282 cmp r2, r0
+ 1010: d100 bne.n 1014 <_ZN14USBDeviceClass4initEv+0x8c>
+ pad_transn = 5;
+ 1012: 2205 movs r2, #5
+ if (pad_transp == 0x1F) // maximum value (31)
+ 1014: 291f cmp r1, #31
+ 1016: d100 bne.n 101a <_ZN14USBDeviceClass4initEv+0x92>
+ pad_transp = 29;
+ 1018: 3902 subs r1, #2
+ if (pad_trim == 0x7) // maximum value (7)
+ 101a: 2b07 cmp r3, #7
+ 101c: d100 bne.n 1020 <_ZN14USBDeviceClass4initEv+0x98>
+ pad_trim = 3;
+ 101e: 3b04 subs r3, #4
+ usb.PADCAL.bit.TRANSN = pad_transn;
+ 1020: 8d26 ldrh r6, [r4, #40] ; 0x28
+ 1022: 4f22 ldr r7, [pc, #136] ; (10ac <_ZN14USBDeviceClass4initEv+0x124>)
+ 1024: 4002 ands r2, r0
+ 1026: 403e ands r6, r7
+ 1028: 0192 lsls r2, r2, #6
+ 102a: 4332 orrs r2, r6
+ 102c: 8522 strh r2, [r4, #40] ; 0x28
+ usb.PADCAL.bit.TRANSP = pad_transp;
+ 102e: 8d22 ldrh r2, [r4, #40] ; 0x28
+ 1030: 4001 ands r1, r0
+ 1032: 4382 bics r2, r0
+ 1034: 000e movs r6, r1
+ 1036: 0011 movs r1, r2
+ 1038: 4331 orrs r1, r6
+ 103a: 8521 strh r1, [r4, #40] ; 0x28
+ usb.PADCAL.bit.TRIM = pad_trim;
+ 103c: 8d22 ldrh r2, [r4, #40] ; 0x28
+ 103e: 0319 lsls r1, r3, #12
+ 1040: 4b1b ldr r3, [pc, #108] ; (10b0 <_ZN14USBDeviceClass4initEv+0x128>)
+ SerialUSB.begin(0);
+ 1042: 481c ldr r0, [pc, #112] ; (10b4 <_ZN14USBDeviceClass4initEv+0x12c>)
+ 1044: 4013 ands r3, r2
+ inline void setUSBDeviceMode() { usb.CTRLA.bit.MODE = USB_CTRLA_MODE_DEVICE_Val; }
+ 1046: 227f movs r2, #127 ; 0x7f
+ usb.PADCAL.bit.TRIM = pad_trim;
+ 1048: 430b orrs r3, r1
+ 104a: 8523 strh r3, [r4, #40] ; 0x28
+ inline void setUSBDeviceMode() { usb.CTRLA.bit.MODE = USB_CTRLA_MODE_DEVICE_Val; }
+ 104c: 7823 ldrb r3, [r4, #0]
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ 104e: 21c1 movs r1, #193 ; 0xc1
+ 1050: 4013 ands r3, r2
+ 1052: 7023 strb r3, [r4, #0]
+ inline void runInStandby() { usb.CTRLA.bit.RUNSTDBY = 1; }
+ 1054: 2304 movs r3, #4
+ 1056: 7822 ldrb r2, [r4, #0]
+ 1058: 0089 lsls r1, r1, #2
+ 105a: 4313 orrs r3, r2
+ inline void setFullSpeed() { usb.CTRLB.bit.SPDCONF = USB_DEVICE_CTRLB_SPDCONF_FS_Val; }
+ 105c: 220c movs r2, #12
+ inline void runInStandby() { usb.CTRLA.bit.RUNSTDBY = 1; }
+ 105e: 7023 strb r3, [r4, #0]
+ inline void setFullSpeed() { usb.CTRLB.bit.SPDCONF = USB_DEVICE_CTRLB_SPDCONF_FS_Val; }
+ 1060: 8923 ldrh r3, [r4, #8]
+ 1062: 4393 bics r3, r2
+ 1064: 4a14 ldr r2, [pc, #80] ; (10b8 <_ZN14USBDeviceClass4initEv+0x130>)
+ 1066: 8123 strh r3, [r4, #8]
+ 1068: 5853 ldr r3, [r2, r1]
+ 106a: 021b lsls r3, r3, #8
+ 106c: 0a1b lsrs r3, r3, #8
+ 106e: 5053 str r3, [r2, r1]
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ 1070: 2380 movs r3, #128 ; 0x80
+ 1072: 6013 str r3, [r2, #0]
+ inline void enable() { usb.CTRLA.bit.ENABLE = 1; }
+ 1074: 7822 ldrb r2, [r4, #0]
+ 1076: 3b7e subs r3, #126 ; 0x7e
+ 1078: 4313 orrs r3, r2
+ 107a: 7023 strb r3, [r4, #0]
+ initialized = true;
+ 107c: 2301 movs r3, #1
+ SerialUSB.begin(0);
+ 107e: 2100 movs r1, #0
+ initialized = true;
+ 1080: 702b strb r3, [r5, #0]
+ SerialUSB.begin(0);
+ 1082: f7ff fc75 bl 970 <_ZN7Serial_5beginEm>
+}
+ 1086: bdf8 pop {r3, r4, r5, r6, r7, pc}
+ 1088: 40000400 .word 0x40000400
+ 108c: 41004458 .word 0x41004458
+ 1090: 4100443c .word 0x4100443c
+ 1094: 41004459 .word 0x41004459
+ 1098: 40000c00 .word 0x40000c00
+ 109c: 00004006 .word 0x00004006
+ 10a0: 00001a0d .word 0x00001a0d
+ 10a4: 200005f4 .word 0x200005f4
+ 10a8: 00806024 .word 0x00806024
+ 10ac: fffff83f .word 0xfffff83f
+ 10b0: ffff8fff .word 0xffff8fff
+ 10b4: 200000d4 .word 0x200000d4
+ 10b8: e000e100 .word 0xe000e100
+
+000010bc <_ZN14USBDeviceClass6attachEv>:
+ if (!initialized)
+ 10bc: 7800 ldrb r0, [r0, #0]
+ 10be: 2800 cmp r0, #0
+ 10c0: d010 beq.n 10e4 <_ZN14USBDeviceClass6attachEv+0x28>
+ inline void attach() { usb.CTRLB.bit.DETACH = 0; }
+ 10c2: 2101 movs r1, #1
+ 10c4: 4b08 ldr r3, [pc, #32] ; (10e8 <_ZN14USBDeviceClass6attachEv+0x2c>)
+ 10c6: 681b ldr r3, [r3, #0]
+ 10c8: 891a ldrh r2, [r3, #8]
+ 10ca: 438a bics r2, r1
+ 10cc: 811a strh r2, [r3, #8]
+ inline void enableEndOfResetInterrupt() { usb.INTENSET.bit.EORST = 1; }
+ 10ce: 2208 movs r2, #8
+ 10d0: 8b19 ldrh r1, [r3, #24]
+ 10d2: 430a orrs r2, r1
+ 10d4: 831a strh r2, [r3, #24]
+ inline void enableStartOfFrameInterrupt() { usb.INTENSET.bit.SOF = 1; }
+ 10d6: 2204 movs r2, #4
+ 10d8: 8b19 ldrh r1, [r3, #24]
+ 10da: 430a orrs r2, r1
+ 10dc: 831a strh r2, [r3, #24]
+ _usbConfiguration = 0;
+ 10de: 2200 movs r2, #0
+ 10e0: 4b02 ldr r3, [pc, #8] ; (10ec <_ZN14USBDeviceClass6attachEv+0x30>)
+ 10e2: 601a str r2, [r3, #0]
+}
+ 10e4: 4770 bx lr
+ 10e6: 46c0 nop ; (mov r8, r8)
+ 10e8: 200005f4 .word 0x200005f4
+ 10ec: 200005ec .word 0x200005ec
+
+000010f0 <_ZN14USBDeviceClass10setAddressEm>:
+{
+ 10f0: b510 push {r4, lr}
+ inline void epBank1SetByteCount(ep_t ep, uint16_t bc) { EP[ep].DeviceDescBank[1].PCKSIZE.bit.BYTE_COUNT = bc; }
+ 10f2: 4a0f ldr r2, [pc, #60] ; (1130 <_ZN14USBDeviceClass10setAddressEm+0x40>)
+ 10f4: 6993 ldr r3, [r2, #24]
+ 10f6: 0b9b lsrs r3, r3, #14
+ 10f8: 039b lsls r3, r3, #14
+ 10fa: 6193 str r3, [r2, #24]
+ inline void epBank1AckTransferComplete(ep_t ep) { usb.DeviceEndpoint[ep].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT(2); }
+ 10fc: 6813 ldr r3, [r2, #0]
+ 10fe: 2202 movs r2, #2
+ 1100: 33ff adds r3, #255 ; 0xff
+ 1102: 721a strb r2, [r3, #8]
+ inline void epBank1SetReady(ep_t ep) { usb.DeviceEndpoint[ep].EPSTATUSSET.bit.BK1RDY = 1; }
+ 1104: 7998 ldrb r0, [r3, #6]
+ 1106: 3a82 subs r2, #130 ; 0x82
+ 1108: 4302 orrs r2, r0
+ 110a: 719a strb r2, [r3, #6]
+ inline bool epBank1IsTransferComplete(ep_t ep) { return usb.DeviceEndpoint[ep].EPINTFLAG.bit.TRCPT1; }
+ 110c: 7a1a ldrb r2, [r3, #8]
+ while (!usbd.epBank1IsTransferComplete(0)) {}
+ 110e: 0792 lsls r2, r2, #30
+ 1110: d5fc bpl.n 110c <_ZN14USBDeviceClass10setAddressEm+0x1c>
+ USB->DEVICE.DADD.bit.DADD = addr; // Address
+ 1112: 247f movs r4, #127 ; 0x7f
+ 1114: 4a07 ldr r2, [pc, #28] ; (1134 <_ZN14USBDeviceClass10setAddressEm+0x44>)
+ 1116: 4021 ands r1, r4
+ 1118: 7a93 ldrb r3, [r2, #10]
+ 111a: 0008 movs r0, r1
+ 111c: 43a3 bics r3, r4
+ 111e: 0019 movs r1, r3
+ USB->DEVICE.DADD.bit.ADDEN = 1; // Enable
+ 1120: 2380 movs r3, #128 ; 0x80
+ USB->DEVICE.DADD.bit.DADD = addr; // Address
+ 1122: 4301 orrs r1, r0
+ 1124: 7291 strb r1, [r2, #10]
+ USB->DEVICE.DADD.bit.ADDEN = 1; // Enable
+ 1126: 7a91 ldrb r1, [r2, #10]
+ 1128: 425b negs r3, r3
+ 112a: 430b orrs r3, r1
+ 112c: 7293 strb r3, [r2, #10]
+}
+ 112e: bd10 pop {r4, pc}
+ 1130: 200005f4 .word 0x200005f4
+ 1134: 41005000 .word 0x41005000
+
+00001138 <_ZN14USBDeviceClass25handleClassInterfaceSetupER8USBSetup>:
+{
+ 1138: b510 push {r4, lr}
+ 113a: 000c movs r4, r1
+ bool ret = PluggableUSB().setup(setup);
+ 113c: f7ff fca4 bl a88 <_Z12PluggableUSBv>
+ 1140: 0021 movs r1, r4
+ 1142: f7ff fc58 bl 9f6 <_ZN13PluggableUSB_5setupER8USBSetup>
+ if ( ret == false) {
+ 1146: 2800 cmp r0, #0
+ 1148: d104 bne.n 1154 <_ZN14USBDeviceClass25handleClassInterfaceSetupER8USBSetup+0x1c>
+ inline void epBank1SetByteCount(ep_t ep, uint16_t bc) { EP[ep].DeviceDescBank[1].PCKSIZE.bit.BYTE_COUNT = bc; }
+ 114a: 4a03 ldr r2, [pc, #12] ; (1158 <_ZN14USBDeviceClass25handleClassInterfaceSetupER8USBSetup+0x20>)
+ 114c: 6993 ldr r3, [r2, #24]
+ 114e: 0b9b lsrs r3, r3, #14
+ 1150: 039b lsls r3, r3, #14
+ 1152: 6193 str r3, [r2, #24]
+}
+ 1154: bd10 pop {r4, pc}
+ 1156: 46c0 nop ; (mov r8, r8)
+ 1158: 200005f4 .word 0x200005f4
+
+0000115c <_ZN14USBDeviceClass6initEPEmm>:
+{
+ 115c: b5f8 push {r3, r4, r5, r6, r7, lr}
+ 115e: 000d movs r5, r1
+ if (config == (USB_ENDPOINT_TYPE_INTERRUPT | USB_ENDPOINT_IN(0)))
+ 1160: 2a83 cmp r2, #131 ; 0x83
+ 1162: d119 bne.n 1198 <_ZN14USBDeviceClass6initEPEmm+0x3c>
+ inline void epBank1SetSize(ep_t ep, uint16_t size) { EP[ep].DeviceDescBank[1].PCKSIZE.bit.SIZE = EP_PCKSIZE_SIZE(size); }
+ 1164: b2cb uxtb r3, r1
+ 1166: 4c39 ldr r4, [pc, #228] ; (124c <_ZN14USBDeviceClass6initEPEmm+0xf0>)
+ 1168: 015a lsls r2, r3, #5
+ 116a: 18a2 adds r2, r4, r2
+ 116c: 6991 ldr r1, [r2, #24]
+ 116e: 4838 ldr r0, [pc, #224] ; (1250 <_ZN14USBDeviceClass6initEPEmm+0xf4>)
+ usbd.epBank1SetAddress(ep, &udd_ep_in_cache_buffer[ep]);
+ 1170: 01ad lsls r5, r5, #6
+ 1172: 4008 ands r0, r1
+ 1174: 21c0 movs r1, #192 ; 0xc0
+ 1176: 0589 lsls r1, r1, #22
+ 1178: 4301 orrs r1, r0
+ 117a: 6191 str r1, [r2, #24]
+ 117c: 4935 ldr r1, [pc, #212] ; (1254 <_ZN14USBDeviceClass6initEPEmm+0xf8>)
+ inline void epBank1SetType(ep_t ep, uint8_t type) { usb.DeviceEndpoint[ep].EPCFG.bit.EPTYPE1 = type; }
+ 117e: 6820 ldr r0, [r4, #0]
+ 1180: 194d adds r5, r1, r5
+ 1182: 2170 movs r1, #112 ; 0x70
+ 1184: 3308 adds r3, #8
+ inline void epBank1SetAddress(ep_t ep, void *addr) { EP[ep].DeviceDescBank[1].ADDR.reg = (uint32_t)addr; }
+ 1186: 6155 str r5, [r2, #20]
+ inline void epBank1SetType(ep_t ep, uint8_t type) { usb.DeviceEndpoint[ep].EPCFG.bit.EPTYPE1 = type; }
+ 1188: 015b lsls r3, r3, #5
+ 118a: 5c1a ldrb r2, [r3, r0]
+ 118c: 438a bics r2, r1
+ 118e: 0011 movs r1, r2
+ 1190: 2240 movs r2, #64 ; 0x40
+ 1192: 430a orrs r2, r1
+ 1194: 541a strb r2, [r3, r0]
+}
+ 1196: bdf8 pop {r3, r4, r5, r6, r7, pc}
+ else if (config == (USB_ENDPOINT_TYPE_BULK | USB_ENDPOINT_OUT(0)))
+ 1198: 2a02 cmp r2, #2
+ 119a: d152 bne.n 1242 <_ZN14USBDeviceClass6initEPEmm+0xe6>
+ if (epHandlers[ep] != NULL) {
+ 119c: 4a2e ldr r2, [pc, #184] ; (1258 <_ZN14USBDeviceClass6initEPEmm+0xfc>)
+ 119e: 008b lsls r3, r1, #2
+ 11a0: 5898 ldr r0, [r3, r2]
+ 11a2: 2800 cmp r0, #0
+ 11a4: d002 beq.n 11ac <_ZN14USBDeviceClass6initEPEmm+0x50>
+ delete (DoubleBufferedEPOutHandler*)epHandlers[ep];
+ 11a6: 6803 ldr r3, [r0, #0]
+ 11a8: 695b ldr r3, [r3, #20]
+ 11aa: 4798 blx r3
+ epHandlers[ep] = new DoubleBufferedEPOutHandler(usbd, ep);
+ 11ac: 20da movs r0, #218 ; 0xda
+ 11ae: 0040 lsls r0, r0, #1
+ 11b0: f000 ff16 bl 1fe0 <_Znwj>
+ memset( _aucBuffer, 0, N ) ;
+ 11b4: 2280 movs r2, #128 ; 0x80
+ 11b6: 0004 movs r4, r0
+ notify(false)
+ 11b8: 4e24 ldr r6, [pc, #144] ; (124c <_ZN14USBDeviceClass6initEPEmm+0xf0>)
+ 11ba: 4b28 ldr r3, [pc, #160] ; (125c <_ZN14USBDeviceClass6initEPEmm+0x100>)
+ 11bc: 6046 str r6, [r0, #4]
+ 11be: 6003 str r3, [r0, #0]
+ 11c0: 0052 lsls r2, r2, #1
+ 11c2: 2100 movs r1, #0
+ 11c4: 3008 adds r0, #8
+ 11c6: f001 fb30 bl 282a <memset>
+ _iHead = 0;
+ 11ca: 0022 movs r2, r4
+ 11cc: 2300 movs r3, #0
+ 11ce: 32fc adds r2, #252 ; 0xfc
+ 11d0: 60d3 str r3, [r2, #12]
+ 11d2: 6155 str r5, [r2, #20]
+ _iTail = 0;
+ 11d4: 6113 str r3, [r2, #16]
+ 11d6: 6613 str r3, [r2, #96] ; 0x60
+ 11d8: 6193 str r3, [r2, #24]
+ 11da: 61d3 str r3, [r2, #28]
+ 11dc: 6653 str r3, [r2, #100] ; 0x64
+ 11de: 22b2 movs r2, #178 ; 0xb2
+ 11e0: 0052 lsls r2, r2, #1
+ 11e2: 54a3 strb r3, [r4, r2]
+ 11e4: 3244 adds r2, #68 ; 0x44
+ 11e6: 50a3 str r3, [r4, r2]
+ 11e8: 3204 adds r2, #4
+ 11ea: 50a3 str r3, [r4, r2]
+ 11ec: 3204 adds r2, #4
+ 11ee: 54a3 strb r3, [r4, r2]
+ 11f0: 22b2 movs r2, #178 ; 0xb2
+ 11f2: 32ff adds r2, #255 ; 0xff
+ 11f4: 54a3 strb r3, [r4, r2]
+ inline void epBank0SetSize(ep_t ep, uint16_t size) { EP[ep].DeviceDescBank[0].PCKSIZE.bit.SIZE = EP_PCKSIZE_SIZE(size); }
+ 11f6: b2ea uxtb r2, r5
+ 11f8: 0150 lsls r0, r2, #5
+ 11fa: 1831 adds r1, r6, r0
+ 11fc: 688b ldr r3, [r1, #8]
+ 11fe: 4f14 ldr r7, [pc, #80] ; (1250 <_ZN14USBDeviceClass6initEPEmm+0xf4>)
+ inline void epBank0SetType(ep_t ep, uint8_t type) { usb.DeviceEndpoint[ep].EPCFG.bit.EPTYPE0 = type; }
+ 1200: 3208 adds r2, #8
+ inline void epBank0SetSize(ep_t ep, uint16_t size) { EP[ep].DeviceDescBank[0].PCKSIZE.bit.SIZE = EP_PCKSIZE_SIZE(size); }
+ 1202: 401f ands r7, r3
+ 1204: 23c0 movs r3, #192 ; 0xc0
+ 1206: 059b lsls r3, r3, #22
+ 1208: 433b orrs r3, r7
+ inline void epBank0SetType(ep_t ep, uint8_t type) { usb.DeviceEndpoint[ep].EPCFG.bit.EPTYPE0 = type; }
+ 120a: 2707 movs r7, #7
+ inline void epBank0SetSize(ep_t ep, uint16_t size) { EP[ep].DeviceDescBank[0].PCKSIZE.bit.SIZE = EP_PCKSIZE_SIZE(size); }
+ 120c: 608b str r3, [r1, #8]
+ inline void epBank0SetType(ep_t ep, uint8_t type) { usb.DeviceEndpoint[ep].EPCFG.bit.EPTYPE0 = type; }
+ 120e: 6833 ldr r3, [r6, #0]
+ 1210: 0152 lsls r2, r2, #5
+ 1212: 5cd6 ldrb r6, [r2, r3]
+ 1214: 00ad lsls r5, r5, #2
+ 1216: 43be bics r6, r7
+ 1218: 46b4 mov ip, r6
+ 121a: 2603 movs r6, #3
+ 121c: 4667 mov r7, ip
+ 121e: 433e orrs r6, r7
+ 1220: 54d6 strb r6, [r2, r3]
+ usbd.epBank0SetAddress(ep, const_cast<uint8_t *>(data0));
+ 1222: 0022 movs r2, r4
+ 1224: 321d adds r2, #29
+ 1226: 32ff adds r2, #255 ; 0xff
+ inline void epBank0SetAddress(ep_t ep, void *addr) { EP[ep].DeviceDescBank[0].ADDR.reg = (uint32_t)addr; }
+ 1228: 604a str r2, [r1, #4]
+ inline void epBank0EnableTransferComplete(ep_t ep) { usb.DeviceEndpoint[ep].EPINTENSET.bit.TRCPT0 = 1; }
+ 122a: 2201 movs r2, #1
+ 122c: 181b adds r3, r3, r0
+ 122e: 33ff adds r3, #255 ; 0xff
+ 1230: 7a99 ldrb r1, [r3, #10]
+ release();
+ 1232: 0020 movs r0, r4
+ inline void epBank0EnableTransferComplete(ep_t ep) { usb.DeviceEndpoint[ep].EPINTENSET.bit.TRCPT0 = 1; }
+ 1234: 430a orrs r2, r1
+ 1236: 729a strb r2, [r3, #10]
+ release();
+ 1238: f7ff fce6 bl c08 <_ZN26DoubleBufferedEPOutHandler7releaseEv>
+ 123c: 4b06 ldr r3, [pc, #24] ; (1258 <_ZN14USBDeviceClass6initEPEmm+0xfc>)
+ 123e: 515c str r4, [r3, r5]
+ 1240: e7a9 b.n 1196 <_ZN14USBDeviceClass6initEPEmm+0x3a>
+ 1242: 0011 movs r1, r2
+ 1244: 0028 movs r0, r5
+ 1246: f7ff fc37 bl ab8 <_ZN14USBDeviceClass6initEPEmm.part.7>
+}
+ 124a: e7a4 b.n 1196 <_ZN14USBDeviceClass6initEPEmm+0x3a>
+ 124c: 200005f4 .word 0x200005f4
+ 1250: 8fffffff .word 0x8fffffff
+ 1254: 20000168 .word 0x20000168
+ 1258: 20000140 .word 0x20000140
+ 125c: 00002a58 .word 0x00002a58
+
+00001260 <_ZN14USBDeviceClass13initEndpointsEv>:
+void USBDeviceClass::initEndpoints() {
+ 1260: b570 push {r4, r5, r6, lr}
+ 1262: 0005 movs r5, r0
+ 1264: 2401 movs r4, #1
+ for (uint8_t i = 1; (i < EP_ARRAY_SIZE) && (EndPoints[i] != 0); i++) {
+ 1266: 4b06 ldr r3, [pc, #24] ; (1280 <_ZN14USBDeviceClass13initEndpointsEv+0x20>)
+ 1268: 00a2 lsls r2, r4, #2
+ 126a: 58d2 ldr r2, [r2, r3]
+ 126c: 2a00 cmp r2, #0
+ 126e: d006 beq.n 127e <_ZN14USBDeviceClass13initEndpointsEv+0x1e>
+ initEP(i, EndPoints[i]);
+ 1270: 0021 movs r1, r4
+ 1272: 0028 movs r0, r5
+ 1274: 3401 adds r4, #1
+ 1276: f7ff ff71 bl 115c <_ZN14USBDeviceClass6initEPEmm>
+ for (uint8_t i = 1; (i < EP_ARRAY_SIZE) && (EndPoints[i] != 0); i++) {
+ 127a: 2c0a cmp r4, #10
+ 127c: d1f3 bne.n 1266 <_ZN14USBDeviceClass13initEndpointsEv+0x6>
+}
+ 127e: bd70 pop {r4, r5, r6, pc}
+ 1280: 20000114 .word 0x20000114
+
+00001284 <_ZN14USBDeviceClass5clearEm>:
+ usbd.epBank1AckTransferComplete(ep);
+ }
+}
+
+void USBDeviceClass::clear(uint32_t ep) {
+ usbd.epBank1SetAddress(ep, &udd_ep_in_cache_buffer[ep]);
+ 1284: 4b0b ldr r3, [pc, #44] ; (12b4 <_ZN14USBDeviceClass5clearEm+0x30>)
+ inline void epBank1SetAddress(ep_t ep, void *addr) { EP[ep].DeviceDescBank[1].ADDR.reg = (uint32_t)addr; }
+ 1286: b2ca uxtb r2, r1
+ 1288: 480b ldr r0, [pc, #44] ; (12b8 <_ZN14USBDeviceClass5clearEm+0x34>)
+ 128a: 0189 lsls r1, r1, #6
+ 128c: 1859 adds r1, r3, r1
+ 128e: 0153 lsls r3, r2, #5
+ 1290: 18c3 adds r3, r0, r3
+ 1292: 6159 str r1, [r3, #20]
+ inline void epBank1SetByteCount(ep_t ep, uint16_t bc) { EP[ep].DeviceDescBank[1].PCKSIZE.bit.BYTE_COUNT = bc; }
+ 1294: 6999 ldr r1, [r3, #24]
+ inline void epBank1AckTransferComplete(ep_t ep) { usb.DeviceEndpoint[ep].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT(2); }
+ 1296: 3208 adds r2, #8
+ inline void epBank1SetByteCount(ep_t ep, uint16_t bc) { EP[ep].DeviceDescBank[1].PCKSIZE.bit.BYTE_COUNT = bc; }
+ 1298: 0b89 lsrs r1, r1, #14
+ 129a: 0389 lsls r1, r1, #14
+ 129c: 6199 str r1, [r3, #24]
+ inline void epBank1AckTransferComplete(ep_t ep) { usb.DeviceEndpoint[ep].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT(2); }
+ 129e: 6803 ldr r3, [r0, #0]
+ 12a0: 0152 lsls r2, r2, #5
+ 12a2: 189a adds r2, r3, r2
+ 12a4: 2302 movs r3, #2
+ 12a6: 71d3 strb r3, [r2, #7]
+ inline void epBank1SetReady(ep_t ep) { usb.DeviceEndpoint[ep].EPSTATUSSET.bit.BK1RDY = 1; }
+ 12a8: 7951 ldrb r1, [r2, #5]
+ 12aa: 3b82 subs r3, #130 ; 0x82
+ 12ac: 430b orrs r3, r1
+ 12ae: 7153 strb r3, [r2, #5]
+ // Clear the transfer complete flag
+ usbd.epBank1AckTransferComplete(ep);
+
+ // RAM buffer is full, we can send data (IN)
+ usbd.epBank1SetReady(ep);
+}
+ 12b0: 4770 bx lr
+ 12b2: 46c0 nop ; (mov r8, r8)
+ 12b4: 20000168 .word 0x20000168
+ 12b8: 200005f4 .word 0x200005f4
+
+000012bc <_ZN14USBDeviceClass9availableEm>:
+}
+
+// Number of bytes, assumes a rx endpoint
+uint32_t USBDeviceClass::available(uint32_t ep)
+{
+ if (epHandlers[ep]) {
+ 12bc: 4b08 ldr r3, [pc, #32] ; (12e0 <_ZN14USBDeviceClass9availableEm+0x24>)
+ 12be: 008a lsls r2, r1, #2
+ 12c0: 58d0 ldr r0, [r2, r3]
+{
+ 12c2: b510 push {r4, lr}
+ if (epHandlers[ep]) {
+ 12c4: 2800 cmp r0, #0
+ 12c6: d003 beq.n 12d0 <_ZN14USBDeviceClass9availableEm+0x14>
+ return epHandlers[ep]->available();
+ 12c8: 6803 ldr r3, [r0, #0]
+ 12ca: 689b ldr r3, [r3, #8]
+ 12cc: 4798 blx r3
+ } else {
+ return usbd.epBank0ByteCount(ep);
+ }
+}
+ 12ce: bd10 pop {r4, pc}
+ inline uint16_t epBank0ByteCount(ep_t ep) { return EP[ep].DeviceDescBank[0].PCKSIZE.bit.BYTE_COUNT; }
+ 12d0: b2c9 uxtb r1, r1
+ 12d2: 4b04 ldr r3, [pc, #16] ; (12e4 <_ZN14USBDeviceClass9availableEm+0x28>)
+ 12d4: 0149 lsls r1, r1, #5
+ 12d6: 1859 adds r1, r3, r1
+ 12d8: 6888 ldr r0, [r1, #8]
+ 12da: 0480 lsls r0, r0, #18
+ 12dc: 0c80 lsrs r0, r0, #18
+ return usbd.epBank0ByteCount(ep);
+ 12de: e7f6 b.n 12ce <_ZN14USBDeviceClass9availableEm+0x12>
+ 12e0: 20000140 .word 0x20000140
+ 12e4: 200005f4 .word 0x200005f4
+
+000012e8 <_ZN14USBDeviceClass5flushEm>:
+{
+ 12e8: b510 push {r4, lr}
+ 12ea: 000c movs r4, r1
+ if (available(ep)) {
+ 12ec: f7ff ffe6 bl 12bc <_ZN14USBDeviceClass9availableEm>
+ 12f0: 2800 cmp r0, #0
+ 12f2: d00c beq.n 130e <_ZN14USBDeviceClass5flushEm+0x26>
+ inline void epBank1SetReady(ep_t ep) { usb.DeviceEndpoint[ep].EPSTATUSSET.bit.BK1RDY = 1; }
+ 12f4: 4b06 ldr r3, [pc, #24] ; (1310 <_ZN14USBDeviceClass5flushEm+0x28>)
+ 12f6: b2e4 uxtb r4, r4
+ 12f8: 681b ldr r3, [r3, #0]
+ 12fa: 3408 adds r4, #8
+ 12fc: 0164 lsls r4, r4, #5
+ 12fe: 191c adds r4, r3, r4
+ 1300: 2380 movs r3, #128 ; 0x80
+ 1302: 7962 ldrb r2, [r4, #5]
+ 1304: 425b negs r3, r3
+ 1306: 4313 orrs r3, r2
+ 1308: 7163 strb r3, [r4, #5]
+ inline void epBank1AckTransferComplete(ep_t ep) { usb.DeviceEndpoint[ep].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT(2); }
+ 130a: 2302 movs r3, #2
+ 130c: 71e3 strb r3, [r4, #7]
+}
+ 130e: bd10 pop {r4, pc}
+ 1310: 200005f4 .word 0x200005f4
+
+00001314 <_ZN14USBDeviceClass4recvEmPvm>:
+
+// Non Blocking receive
+// Return number of bytes read
+uint32_t USBDeviceClass::recv(uint32_t ep, void *_data, uint32_t len)
+{
+ 1314: b5f0 push {r4, r5, r6, r7, lr}
+ 1316: 001c movs r4, r3
+ if (!_usbConfiguration)
+ 1318: 4b2b ldr r3, [pc, #172] ; (13c8 <_ZN14USBDeviceClass4recvEmPvm+0xb4>)
+{
+ 131a: b085 sub sp, #20
+ if (!_usbConfiguration)
+ 131c: 681b ldr r3, [r3, #0]
+{
+ 131e: 0007 movs r7, r0
+ 1320: 000d movs r5, r1
+ 1322: 9202 str r2, [sp, #8]
+ if (!_usbConfiguration)
+ 1324: 2b00 cmp r3, #0
+ 1326: d04b beq.n 13c0 <_ZN14USBDeviceClass4recvEmPvm+0xac>
+ digitalWrite(PIN_LED_RXL, LOW);
+
+ rxLEDPulse = TX_RX_LED_PULSE_MS;
+#endif
+
+ if (epHandlers[ep]) {
+ 1328: 4b28 ldr r3, [pc, #160] ; (13cc <_ZN14USBDeviceClass4recvEmPvm+0xb8>)
+ 132a: 008a lsls r2, r1, #2
+ 132c: 58d0 ldr r0, [r2, r3]
+ 132e: 2800 cmp r0, #0
+ 1330: d008 beq.n 1344 <_ZN14USBDeviceClass4recvEmPvm+0x30>
+ return epHandlers[ep]->recv(_data, len);
+ 1332: 6803 ldr r3, [r0, #0]
+ 1334: 0022 movs r2, r4
+ 1336: 685b ldr r3, [r3, #4]
+ 1338: 9902 ldr r1, [sp, #8]
+ 133a: 4798 blx r3
+ 133c: 0004 movs r4, r0
+ // Enable Transfer complete 0 interrupt
+ usbd.epBank0EnableTransferComplete(ep);
+ }
+
+ return len;
+}
+ 133e: 0020 movs r0, r4
+ 1340: b005 add sp, #20
+ 1342: bdf0 pop {r4, r5, r6, r7, pc}
+ if (available(ep) < len)
+ 1344: 0038 movs r0, r7
+ 1346: f7ff ffb9 bl 12bc <_ZN14USBDeviceClass9availableEm>
+ 134a: 4284 cmp r4, r0
+ 134c: d904 bls.n 1358 <_ZN14USBDeviceClass4recvEmPvm+0x44>
+ len = available(ep);
+ 134e: 0029 movs r1, r5
+ 1350: 0038 movs r0, r7
+ 1352: f7ff ffb3 bl 12bc <_ZN14USBDeviceClass9availableEm>
+ 1356: 0004 movs r4, r0
+ inline void epBank0DisableTransferComplete(ep_t ep) { usb.DeviceEndpoint[ep].EPINTENCLR.bit.TRCPT0 = 1; }
+ 1358: 2101 movs r1, #1
+ inline void epBank0SetByteCount(ep_t ep, uint16_t bc) { EP[ep].DeviceDescBank[0].PCKSIZE.bit.BYTE_COUNT = bc; }
+ 135a: b2eb uxtb r3, r5
+ 135c: 4e1c ldr r6, [pc, #112] ; (13d0 <_ZN14USBDeviceClass4recvEmPvm+0xbc>)
+ 135e: 9303 str r3, [sp, #12]
+ 1360: 015b lsls r3, r3, #5
+ 1362: 9301 str r3, [sp, #4]
+ 1364: 18f2 adds r2, r6, r3
+ 1366: 6893 ldr r3, [r2, #8]
+ 1368: 0b9b lsrs r3, r3, #14
+ 136a: 039b lsls r3, r3, #14
+ 136c: 6093 str r3, [r2, #8]
+ inline void epBank0DisableTransferComplete(ep_t ep) { usb.DeviceEndpoint[ep].EPINTENCLR.bit.TRCPT0 = 1; }
+ 136e: 9a01 ldr r2, [sp, #4]
+ 1370: 6833 ldr r3, [r6, #0]
+ memcpy(_data, udd_ep_out_cache_buffer[ep], len);
+ 1372: 9802 ldr r0, [sp, #8]
+ 1374: 189b adds r3, r3, r2
+ 1376: 33ff adds r3, #255 ; 0xff
+ 1378: 7a5a ldrb r2, [r3, #9]
+ 137a: 430a orrs r2, r1
+ 137c: 4915 ldr r1, [pc, #84] ; (13d4 <_ZN14USBDeviceClass4recvEmPvm+0xc0>)
+ 137e: 725a strb r2, [r3, #9]
+ 1380: 01ab lsls r3, r5, #6
+ 1382: 18c9 adds r1, r1, r3
+ 1384: 0022 movs r2, r4
+ 1386: f001 fa47 bl 2818 <memcpy>
+ if (len && !available(ep)) {
+ 138a: 2c00 cmp r4, #0
+ 138c: d0d7 beq.n 133e <_ZN14USBDeviceClass4recvEmPvm+0x2a>
+ 138e: 0029 movs r1, r5
+ 1390: 0038 movs r0, r7
+ 1392: f7ff ff93 bl 12bc <_ZN14USBDeviceClass9availableEm>
+ 1396: 2800 cmp r0, #0
+ 1398: d1d1 bne.n 133e <_ZN14USBDeviceClass4recvEmPvm+0x2a>
+ inline void epBank0ResetReady(ep_t ep) { usb.DeviceEndpoint[ep].EPSTATUSCLR.bit.BK0RDY = 1; }
+ 139a: 2140 movs r1, #64 ; 0x40
+ 139c: 9b03 ldr r3, [sp, #12]
+ 139e: 6832 ldr r2, [r6, #0]
+ 13a0: 3308 adds r3, #8
+ 13a2: 015b lsls r3, r3, #5
+ 13a4: 18d3 adds r3, r2, r3
+ 13a6: 7918 ldrb r0, [r3, #4]
+ 13a8: 4301 orrs r1, r0
+ 13aa: 7119 strb r1, [r3, #4]
+ inline void epBank0AckTransferComplete(ep_t ep) { usb.DeviceEndpoint[ep].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT(1); }
+ 13ac: 2101 movs r1, #1
+ 13ae: 71d9 strb r1, [r3, #7]
+ inline void epBank0EnableTransferComplete(ep_t ep) { usb.DeviceEndpoint[ep].EPINTENSET.bit.TRCPT0 = 1; }
+ 13b0: 2101 movs r1, #1
+ 13b2: 9b01 ldr r3, [sp, #4]
+ 13b4: 18d3 adds r3, r2, r3
+ 13b6: 33ff adds r3, #255 ; 0xff
+ 13b8: 7a9a ldrb r2, [r3, #10]
+ 13ba: 430a orrs r2, r1
+ 13bc: 729a strb r2, [r3, #10]
+ 13be: e7be b.n 133e <_ZN14USBDeviceClass4recvEmPvm+0x2a>
+ return -1;
+ 13c0: 2401 movs r4, #1
+ 13c2: 4264 negs r4, r4
+ 13c4: e7bb b.n 133e <_ZN14USBDeviceClass4recvEmPvm+0x2a>
+ 13c6: 46c0 nop ; (mov r8, r8)
+ 13c8: 200005ec .word 0x200005ec
+ 13cc: 20000140 .word 0x20000140
+ 13d0: 200005f4 .word 0x200005f4
+ 13d4: 20000328 .word 0x20000328
+
+000013d8 <_ZN14USBDeviceClass4recvEm>:
+
+// Recv 1 byte if ready
+int USBDeviceClass::recv(uint32_t ep)
+{
+ 13d8: b513 push {r0, r1, r4, lr}
+ uint8_t c;
+ if (recv(ep, &c, 1) != 1) {
+ 13da: 466b mov r3, sp
+ 13dc: 1ddc adds r4, r3, #7
+ 13de: 0022 movs r2, r4
+ 13e0: 2301 movs r3, #1
+ 13e2: f7ff ff97 bl 1314 <_ZN14USBDeviceClass4recvEmPvm>
+ 13e6: 2801 cmp r0, #1
+ 13e8: d101 bne.n 13ee <_ZN14USBDeviceClass4recvEm+0x16>
+ return -1;
+ } else {
+ return c;
+ 13ea: 7820 ldrb r0, [r4, #0]
+ }
+}
+ 13ec: bd16 pop {r1, r2, r4, pc}
+ return -1;
+ 13ee: 2001 movs r0, #1
+ 13f0: 4240 negs r0, r0
+ 13f2: e7fb b.n 13ec <_ZN14USBDeviceClass4recvEm+0x14>
+
+000013f4 <_ZN14USBDeviceClass14armRecvCtrlOUTEm>:
+
+uint8_t USBDeviceClass::armRecvCtrlOUT(uint32_t ep)
+{
+ 13f4: b570 push {r4, r5, r6, lr}
+ // Get endpoint configuration from setting register
+ usbd.epBank0SetAddress(ep, &udd_ep_out_cache_buffer[ep]);
+ 13f6: 4b13 ldr r3, [pc, #76] ; (1444 <_ZN14USBDeviceClass14armRecvCtrlOUTEm+0x50>)
+ inline void epBank0SetAddress(ep_t ep, void *addr) { EP[ep].DeviceDescBank[0].ADDR.reg = (uint32_t)addr; }
+ 13f8: b2cc uxtb r4, r1
+ 13fa: 4a13 ldr r2, [pc, #76] ; (1448 <_ZN14USBDeviceClass14armRecvCtrlOUTEm+0x54>)
+ 13fc: 0160 lsls r0, r4, #5
+ 13fe: 0189 lsls r1, r1, #6
+ 1400: 1859 adds r1, r3, r1
+ 1402: 1813 adds r3, r2, r0
+ 1404: 6059 str r1, [r3, #4]
+ inline void epBank0SetMultiPacketSize(ep_t ep, uint16_t s) { EP[ep].DeviceDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE = s; }
+ 1406: 6899 ldr r1, [r3, #8]
+ 1408: 4d10 ldr r5, [pc, #64] ; (144c <_ZN14USBDeviceClass14armRecvCtrlOUTEm+0x58>)
+ inline void epBank0ResetReady(ep_t ep) { usb.DeviceEndpoint[ep].EPSTATUSCLR.bit.BK0RDY = 1; }
+ 140a: 3408 adds r4, #8
+ inline void epBank0SetMultiPacketSize(ep_t ep, uint16_t s) { EP[ep].DeviceDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE = s; }
+ 140c: 400d ands r5, r1
+ 140e: 2180 movs r1, #128 ; 0x80
+ 1410: 0349 lsls r1, r1, #13
+ 1412: 4329 orrs r1, r5
+ inline void epBank0ResetReady(ep_t ep) { usb.DeviceEndpoint[ep].EPSTATUSCLR.bit.BK0RDY = 1; }
+ 1414: 2540 movs r5, #64 ; 0x40
+ inline void epBank0SetMultiPacketSize(ep_t ep, uint16_t s) { EP[ep].DeviceDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE = s; }
+ 1416: 6099 str r1, [r3, #8]
+ inline void epBank0SetByteCount(ep_t ep, uint16_t bc) { EP[ep].DeviceDescBank[0].PCKSIZE.bit.BYTE_COUNT = bc; }
+ 1418: 6899 ldr r1, [r3, #8]
+ 141a: 0b89 lsrs r1, r1, #14
+ 141c: 0389 lsls r1, r1, #14
+ 141e: 6099 str r1, [r3, #8]
+ inline void epBank0ResetReady(ep_t ep) { usb.DeviceEndpoint[ep].EPSTATUSCLR.bit.BK0RDY = 1; }
+ 1420: 6811 ldr r1, [r2, #0]
+ 1422: 0163 lsls r3, r4, #5
+ 1424: 18cb adds r3, r1, r3
+ 1426: 791e ldrb r6, [r3, #4]
+ 1428: 4335 orrs r5, r6
+ 142a: 711d strb r5, [r3, #4]
+ inline bool epBank0IsReady(ep_t ep) { return usb.DeviceEndpoint[ep].EPSTATUS.bit.BK0RDY; }
+ 142c: 799d ldrb r5, [r3, #6]
+ usbd.epBank0SetByteCount(ep, 0);
+
+ usbd.epBank0ResetReady(ep);
+
+ // Wait OUT
+ while (!usbd.epBank0IsReady(ep)) {}
+ 142e: 066d lsls r5, r5, #25
+ 1430: d5fc bpl.n 142c <_ZN14USBDeviceClass14armRecvCtrlOUTEm+0x38>
+ inline bool epBank0IsTransferComplete(ep_t ep) { return usb.DeviceEndpoint[ep].EPINTFLAG.bit.TRCPT0; }
+ 1432: 0164 lsls r4, r4, #5
+ 1434: 1909 adds r1, r1, r4
+ 1436: 79cb ldrb r3, [r1, #7]
+ while (!usbd.epBank0IsTransferComplete(ep)) {}
+ 1438: 07db lsls r3, r3, #31
+ 143a: d5fc bpl.n 1436 <_ZN14USBDeviceClass14armRecvCtrlOUTEm+0x42>
+ inline uint16_t epBank0ByteCount(ep_t ep) { return EP[ep].DeviceDescBank[0].PCKSIZE.bit.BYTE_COUNT; }
+ 143c: 1812 adds r2, r2, r0
+ 143e: 6890 ldr r0, [r2, #8]
+ return usbd.epBank0ByteCount(ep);
+ 1440: b2c0 uxtb r0, r0
+}
+ 1442: bd70 pop {r4, r5, r6, pc}
+ 1444: 20000328 .word 0x20000328
+ 1448: 200005f4 .word 0x200005f4
+ 144c: f0003fff .word 0xf0003fff
+
+00001450 <_ZN14USBDeviceClass11recvControlEPvm>:
+{
+ 1450: b570 push {r4, r5, r6, lr}
+ 1452: 000d movs r5, r1
+ uint32_t read = armRecvCtrlOUT(0);
+ 1454: 2100 movs r1, #0
+{
+ 1456: 0014 movs r4, r2
+ uint32_t read = armRecvCtrlOUT(0);
+ 1458: f7ff ffcc bl 13f4 <_ZN14USBDeviceClass14armRecvCtrlOUTEm>
+ 145c: 42a0 cmp r0, r4
+ 145e: d900 bls.n 1462 <_ZN14USBDeviceClass11recvControlEPvm+0x12>
+ 1460: 0020 movs r0, r4
+ for (uint32_t i=0; i<len; i++) {
+ 1462: 2300 movs r3, #0
+ data[i] = buffer[i];
+ 1464: 4903 ldr r1, [pc, #12] ; (1474 <_ZN14USBDeviceClass11recvControlEPvm+0x24>)
+ for (uint32_t i=0; i<len; i++) {
+ 1466: 42a3 cmp r3, r4
+ 1468: d003 beq.n 1472 <_ZN14USBDeviceClass11recvControlEPvm+0x22>
+ data[i] = buffer[i];
+ 146a: 5c5a ldrb r2, [r3, r1]
+ 146c: 54ea strb r2, [r5, r3]
+ for (uint32_t i=0; i<len; i++) {
+ 146e: 3301 adds r3, #1
+ 1470: e7f9 b.n 1466 <_ZN14USBDeviceClass11recvControlEPvm+0x16>
+}
+ 1472: bd70 pop {r4, r5, r6, pc}
+ 1474: 20000328 .word 0x20000328
+
+00001478 <_ZN14USBDeviceClass4sendEmPKvm>:
+ 0
+};
+
+// Blocking Send of data to an endpoint
+uint32_t USBDeviceClass::send(uint32_t ep, const void *data, uint32_t len)
+{
+ 1478: b5f0 push {r4, r5, r6, r7, lr}
+ 147a: 001e movs r6, r3
+ uint32_t written = 0;
+ uint32_t length = 0;
+
+ if (!_usbConfiguration)
+ 147c: 4b3a ldr r3, [pc, #232] ; (1568 <_ZN14USBDeviceClass4sendEmPKvm+0xf0>)
+{
+ 147e: b085 sub sp, #20
+ if (!_usbConfiguration)
+ 1480: 681b ldr r3, [r3, #0]
+{
+ 1482: 000f movs r7, r1
+ 1484: 9201 str r2, [sp, #4]
+ if (!_usbConfiguration)
+ 1486: 2b00 cmp r3, #0
+ 1488: d035 beq.n 14f6 <_ZN14USBDeviceClass4sendEmPKvm+0x7e>
+ return -1;
+ if (len > 16384)
+ 148a: 2380 movs r3, #128 ; 0x80
+ 148c: 01db lsls r3, r3, #7
+ 148e: 429e cmp r6, r3
+ 1490: d831 bhi.n 14f6 <_ZN14USBDeviceClass4sendEmPKvm+0x7e>
+ inline void epBank1SetAddress(ep_t ep, void *addr) { EP[ep].DeviceDescBank[1].ADDR.reg = (uint32_t)addr; }
+ 1492: 2500 movs r5, #0
+ } else {
+ length = len;
+ }
+
+ /* memcopy could be safer in multi threaded environment */
+ memcpy(&udd_ep_in_cache_buffer[ep], data, length);
+ 1494: 4a35 ldr r2, [pc, #212] ; (156c <_ZN14USBDeviceClass4sendEmPKvm+0xf4>)
+ 1496: 018b lsls r3, r1, #6
+ 1498: 18d3 adds r3, r2, r3
+ 149a: 9302 str r3, [sp, #8]
+ while (len != 0)
+ 149c: 2e00 cmp r6, #0
+ 149e: d02c beq.n 14fa <_ZN14USBDeviceClass4sendEmPKvm+0x82>
+ inline bool epBank1IsReady(ep_t ep) { return usb.DeviceEndpoint[ep].EPSTATUS.bit.BK1RDY; }
+ 14a0: 4b33 ldr r3, [pc, #204] ; (1570 <_ZN14USBDeviceClass4sendEmPKvm+0xf8>)
+ 14a2: 681b ldr r3, [r3, #0]
+ 14a4: 9303 str r3, [sp, #12]
+ 14a6: 23ff movs r3, #255 ; 0xff
+ 14a8: 403b ands r3, r7
+ 14aa: 001c movs r4, r3
+ 14ac: 9300 str r3, [sp, #0]
+ 14ae: 3408 adds r4, #8
+ 14b0: 9b03 ldr r3, [sp, #12]
+ 14b2: 0164 lsls r4, r4, #5
+ 14b4: 191c adds r4, r3, r4
+ 14b6: 79a3 ldrb r3, [r4, #6]
+ 14b8: 09db lsrs r3, r3, #7
+ if (usbd.epBank1IsReady(ep)) {
+ 14ba: d021 beq.n 1500 <_ZN14USBDeviceClass4sendEmPKvm+0x88>
+ uint32_t timeout = microsecondsToClockCycles(TX_TIMEOUT_MS * 1000) / 23;
+ 14bc: 4b2d ldr r3, [pc, #180] ; (1574 <_ZN14USBDeviceClass4sendEmPKvm+0xfc>)
+ 14be: 492e ldr r1, [pc, #184] ; (1578 <_ZN14USBDeviceClass4sendEmPKvm+0x100>)
+ 14c0: 6818 ldr r0, [r3, #0]
+ 14c2: f001 f8e5 bl 2690 <__udivsi3>
+ 14c6: 4b2d ldr r3, [pc, #180] ; (157c <_ZN14USBDeviceClass4sendEmPKvm+0x104>)
+ 14c8: 2117 movs r1, #23
+ 14ca: 4358 muls r0, r3
+ 14cc: f001 f8e0 bl 2690 <__udivsi3>
+ if (LastTransmitTimedOut[ep] || timeout-- == 0) {
+ 14d0: 4b2b ldr r3, [pc, #172] ; (1580 <_ZN14USBDeviceClass4sendEmPKvm+0x108>)
+ inline bool epBank1IsTransferComplete(ep_t ep) { return usb.DeviceEndpoint[ep].EPINTFLAG.bit.TRCPT1; }
+ 14d2: 79e2 ldrb r2, [r4, #7]
+ while (!usbd.epBank1IsTransferComplete(ep)) {
+ 14d4: 0792 lsls r2, r2, #30
+ 14d6: d413 bmi.n 1500 <_ZN14USBDeviceClass4sendEmPKvm+0x88>
+ if (LastTransmitTimedOut[ep] || timeout-- == 0) {
+ 14d8: 5dda ldrb r2, [r3, r7]
+ 14da: 2a00 cmp r2, #0
+ 14dc: d101 bne.n 14e2 <_ZN14USBDeviceClass4sendEmPKvm+0x6a>
+ 14de: 3801 subs r0, #1
+ 14e0: d2f7 bcs.n 14d2 <_ZN14USBDeviceClass4sendEmPKvm+0x5a>
+ LastTransmitTimedOut[ep] = 1;
+ 14e2: 2201 movs r2, #1
+ 14e4: 55da strb r2, [r3, r7]
+ inline void epBank1SetByteCount(ep_t ep, uint16_t bc) { EP[ep].DeviceDescBank[1].PCKSIZE.bit.BYTE_COUNT = bc; }
+ 14e6: 9b00 ldr r3, [sp, #0]
+ 14e8: 4a21 ldr r2, [pc, #132] ; (1570 <_ZN14USBDeviceClass4sendEmPKvm+0xf8>)
+ 14ea: 015b lsls r3, r3, #5
+ 14ec: 18d3 adds r3, r2, r3
+ 14ee: 699a ldr r2, [r3, #24]
+ 14f0: 0b92 lsrs r2, r2, #14
+ 14f2: 0392 lsls r2, r2, #14
+ 14f4: 619a str r2, [r3, #24]
+ return -1;
+ 14f6: 2501 movs r5, #1
+ 14f8: 426d negs r5, r5
+ written += length;
+ len -= length;
+ data = (char *)data + length;
+ }
+ return written;
+}
+ 14fa: 0028 movs r0, r5
+ 14fc: b005 add sp, #20
+ 14fe: bdf0 pop {r4, r5, r6, r7, pc}
+ LastTransmitTimedOut[ep] = 0;
+ 1500: 2200 movs r2, #0
+ 1502: 4b1f ldr r3, [pc, #124] ; (1580 <_ZN14USBDeviceClass4sendEmPKvm+0x108>)
+ 1504: 0034 movs r4, r6
+ 1506: 55da strb r2, [r3, r7]
+ if (len >= EPX_SIZE) {
+ 1508: 2e3f cmp r6, #63 ; 0x3f
+ 150a: d909 bls.n 1520 <_ZN14USBDeviceClass4sendEmPKvm+0xa8>
+ inline void epBank1EnableAutoZLP(ep_t ep) { EP[ep].DeviceDescBank[1].PCKSIZE.bit.AUTO_ZLP = 1; }
+ 150c: 9b00 ldr r3, [sp, #0]
+ length = EPX_SIZE;
+ 150e: 2440 movs r4, #64 ; 0x40
+ 1510: 015a lsls r2, r3, #5
+ 1512: 4b17 ldr r3, [pc, #92] ; (1570 <_ZN14USBDeviceClass4sendEmPKvm+0xf8>)
+ 1514: 189b adds r3, r3, r2
+ 1516: 2280 movs r2, #128 ; 0x80
+ 1518: 6999 ldr r1, [r3, #24]
+ 151a: 0612 lsls r2, r2, #24
+ 151c: 430a orrs r2, r1
+ 151e: 619a str r2, [r3, #24]
+ memcpy(&udd_ep_in_cache_buffer[ep], data, length);
+ 1520: 0022 movs r2, r4
+ 1522: 9901 ldr r1, [sp, #4]
+ 1524: 9802 ldr r0, [sp, #8]
+ 1526: f001 f977 bl 2818 <memcpy>
+ inline void epBank1SetAddress(ep_t ep, void *addr) { EP[ep].DeviceDescBank[1].ADDR.reg = (uint32_t)addr; }
+ 152a: 9b00 ldr r3, [sp, #0]
+ inline void epBank1SetByteCount(ep_t ep, uint16_t bc) { EP[ep].DeviceDescBank[1].PCKSIZE.bit.BYTE_COUNT = bc; }
+ 152c: 04a1 lsls r1, r4, #18
+ inline void epBank1SetAddress(ep_t ep, void *addr) { EP[ep].DeviceDescBank[1].ADDR.reg = (uint32_t)addr; }
+ 152e: 015a lsls r2, r3, #5
+ 1530: 4b0f ldr r3, [pc, #60] ; (1570 <_ZN14USBDeviceClass4sendEmPKvm+0xf8>)
+ inline void epBank1SetByteCount(ep_t ep, uint16_t bc) { EP[ep].DeviceDescBank[1].PCKSIZE.bit.BYTE_COUNT = bc; }
+ 1532: 0c89 lsrs r1, r1, #18
+ inline void epBank1SetAddress(ep_t ep, void *addr) { EP[ep].DeviceDescBank[1].ADDR.reg = (uint32_t)addr; }
+ 1534: 189b adds r3, r3, r2
+ 1536: 9a02 ldr r2, [sp, #8]
+ written += length;
+ 1538: 192d adds r5, r5, r4
+ 153a: 615a str r2, [r3, #20]
+ inline void epBank1SetByteCount(ep_t ep, uint16_t bc) { EP[ep].DeviceDescBank[1].PCKSIZE.bit.BYTE_COUNT = bc; }
+ 153c: 699a ldr r2, [r3, #24]
+ len -= length;
+ 153e: 1b36 subs r6, r6, r4
+ 1540: 0b92 lsrs r2, r2, #14
+ 1542: 0392 lsls r2, r2, #14
+ 1544: 430a orrs r2, r1
+ 1546: 619a str r2, [r3, #24]
+ inline void epBank1AckTransferComplete(ep_t ep) { usb.DeviceEndpoint[ep].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT(2); }
+ 1548: 9b00 ldr r3, [sp, #0]
+ 154a: 9a03 ldr r2, [sp, #12]
+ 154c: 3308 adds r3, #8
+ 154e: 015b lsls r3, r3, #5
+ 1550: 18d3 adds r3, r2, r3
+ 1552: 2202 movs r2, #2
+ 1554: 71da strb r2, [r3, #7]
+ inline void epBank1SetReady(ep_t ep) { usb.DeviceEndpoint[ep].EPSTATUSSET.bit.BK1RDY = 1; }
+ 1556: 7959 ldrb r1, [r3, #5]
+ 1558: 3a82 subs r2, #130 ; 0x82
+ 155a: 430a orrs r2, r1
+ 155c: 715a strb r2, [r3, #5]
+ data = (char *)data + length;
+ 155e: 9b01 ldr r3, [sp, #4]
+ 1560: 191b adds r3, r3, r4
+ 1562: 9301 str r3, [sp, #4]
+ while (len != 0)
+ 1564: e79a b.n 149c <_ZN14USBDeviceClass4sendEmPKvm+0x24>
+ 1566: 46c0 nop ; (mov r8, r8)
+ 1568: 200005ec .word 0x200005ec
+ 156c: 20000168 .word 0x20000168
+ 1570: 200005f4 .word 0x200005f4
+ 1574: 20000014 .word 0x20000014
+ 1578: 000f4240 .word 0x000f4240
+ 157c: 00011170 .word 0x00011170
+ 1580: 2000015d .word 0x2000015d
+
+00001584 <_ZN14USBDeviceClass7armSendEmPKvm>:
+
+uint32_t USBDeviceClass::armSend(uint32_t ep, const void* data, uint32_t len)
+{
+ 1584: b570 push {r4, r5, r6, lr}
+ 1586: 000d movs r5, r1
+ 1588: 001c movs r4, r3
+ memcpy(&udd_ep_in_cache_buffer[ep], data, len);
+ 158a: 4e0d ldr r6, [pc, #52] ; (15c0 <_ZN14USBDeviceClass7armSendEmPKvm+0x3c>)
+ 158c: 01ab lsls r3, r5, #6
+ 158e: 18f6 adds r6, r6, r3
+{
+ 1590: 0011 movs r1, r2
+ memcpy(&udd_ep_in_cache_buffer[ep], data, len);
+ 1592: 0030 movs r0, r6
+ 1594: 0022 movs r2, r4
+ 1596: f001 f93f bl 2818 <memcpy>
+ inline void epBank1SetAddress(ep_t ep, void *addr) { EP[ep].DeviceDescBank[1].ADDR.reg = (uint32_t)addr; }
+ 159a: b2ed uxtb r5, r5
+ 159c: 4909 ldr r1, [pc, #36] ; (15c4 <_ZN14USBDeviceClass7armSendEmPKvm+0x40>)
+ 159e: 016d lsls r5, r5, #5
+ 15a0: 194d adds r5, r1, r5
+ 15a2: 616e str r6, [r5, #20]
+ inline void epBank1SetMultiPacketSize(ep_t ep, uint16_t s) { EP[ep].DeviceDescBank[1].PCKSIZE.bit.MULTI_PACKET_SIZE = s; }
+ 15a4: 69ab ldr r3, [r5, #24]
+ 15a6: 4a08 ldr r2, [pc, #32] ; (15c8 <_ZN14USBDeviceClass7armSendEmPKvm+0x44>)
+ usbd.epBank1SetAddress(ep, &udd_ep_in_cache_buffer[ep]);
+ usbd.epBank1SetMultiPacketSize(ep, 0);
+ usbd.epBank1SetByteCount(ep, len);
+
+ return len;
+}
+ 15a8: 0020 movs r0, r4
+ 15aa: 4013 ands r3, r2
+ 15ac: 61ab str r3, [r5, #24]
+ inline void epBank1SetByteCount(ep_t ep, uint16_t bc) { EP[ep].DeviceDescBank[1].PCKSIZE.bit.BYTE_COUNT = bc; }
+ 15ae: 69ab ldr r3, [r5, #24]
+ 15b0: 04a2 lsls r2, r4, #18
+ 15b2: 0b9b lsrs r3, r3, #14
+ 15b4: 0c92 lsrs r2, r2, #18
+ 15b6: 039b lsls r3, r3, #14
+ 15b8: 4313 orrs r3, r2
+ 15ba: 61ab str r3, [r5, #24]
+ 15bc: bd70 pop {r4, r5, r6, pc}
+ 15be: 46c0 nop ; (mov r8, r8)
+ 15c0: 20000168 .word 0x20000168
+ 15c4: 200005f4 .word 0x200005f4
+ 15c8: f0003fff .word 0xf0003fff
+
+000015cc <_ZN14USBDeviceClass11sendControlEPKvm>:
+
+uint32_t USBDeviceClass::sendControl(const void* _data, uint32_t len)
+{
+ 15cc: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr}
+ const uint8_t *data = reinterpret_cast<const uint8_t *>(_data);
+ uint32_t length = len;
+ uint32_t sent = 0;
+ uint32_t pos = 0;
+
+ if (_dry_run == true)
+ 15ce: 4b10 ldr r3, [pc, #64] ; (1610 <_ZN14USBDeviceClass11sendControlEPKvm+0x44>)
+{
+ 15d0: 9001 str r0, [sp, #4]
+ if (_dry_run == true)
+ 15d2: 781b ldrb r3, [r3, #0]
+{
+ 15d4: 000f movs r7, r1
+ 15d6: 0015 movs r5, r2
+ if (_dry_run == true)
+ 15d8: 2b00 cmp r3, #0
+ 15da: d10c bne.n 15f6 <_ZN14USBDeviceClass11sendControlEPKvm+0x2a>
+ return length;
+
+ if (_pack_message == true) {
+ 15dc: 4b0d ldr r3, [pc, #52] ; (1614 <_ZN14USBDeviceClass11sendControlEPKvm+0x48>)
+ 15de: 0016 movs r6, r2
+ 15e0: 781c ldrb r4, [r3, #0]
+ 15e2: 2c00 cmp r4, #0
+ 15e4: d009 beq.n 15fa <_ZN14USBDeviceClass11sendControlEPKvm+0x2e>
+ memcpy(&_pack_buffer[_pack_size], data, len);
+ 15e6: 4e0c ldr r6, [pc, #48] ; (1618 <_ZN14USBDeviceClass11sendControlEPKvm+0x4c>)
+ 15e8: 480c ldr r0, [pc, #48] ; (161c <_ZN14USBDeviceClass11sendControlEPKvm+0x50>)
+ 15ea: 8834 ldrh r4, [r6, #0]
+ 15ec: 1900 adds r0, r0, r4
+ _pack_size += len;
+ 15ee: 1964 adds r4, r4, r5
+ memcpy(&_pack_buffer[_pack_size], data, len);
+ 15f0: f001 f912 bl 2818 <memcpy>
+ _pack_size += len;
+ 15f4: 8034 strh r4, [r6, #0]
+ pos += sent;
+ len -= sent;
+ }
+
+ return length;
+}
+ 15f6: 0028 movs r0, r5
+ 15f8: bdfe pop {r1, r2, r3, r4, r5, r6, r7, pc}
+ while (len > 0)
+ 15fa: 2e00 cmp r6, #0
+ 15fc: d0fb beq.n 15f6 <_ZN14USBDeviceClass11sendControlEPKvm+0x2a>
+ sent = armSend(EP0, data + pos, len);
+ 15fe: 193a adds r2, r7, r4
+ 1600: 0033 movs r3, r6
+ 1602: 2100 movs r1, #0
+ 1604: 9801 ldr r0, [sp, #4]
+ 1606: f7ff ffbd bl 1584 <_ZN14USBDeviceClass7armSendEmPKvm>
+ pos += sent;
+ 160a: 1824 adds r4, r4, r0
+ len -= sent;
+ 160c: 1a36 subs r6, r6, r0
+ while (len > 0)
+ 160e: e7f4 b.n 15fa <_ZN14USBDeviceClass11sendControlEPKvm+0x2e>
+ 1610: 200004e8 .word 0x200004e8
+ 1614: 200005e9 .word 0x200005e9
+ 1618: 200005ea .word 0x200005ea
+ 161c: 200004e9 .word 0x200004e9
+
+00001620 <_ZN14USBDeviceClass20sendStringDescriptorEPKhm>:
+{
+ 1620: b5f8 push {r3, r4, r5, r6, r7, lr}
+ 1622: 000e movs r6, r1
+ 1624: 0015 movs r5, r2
+ return false;
+ 1626: 2700 movs r7, #0
+ if (maxlen < 2)
+ 1628: 2a01 cmp r2, #1
+ 162a: d927 bls.n 167c <_ZN14USBDeviceClass20sendStringDescriptorEPKhm+0x5c>
+ uint8_t* buffer = (uint8_t*)malloc(maxlen);
+ 162c: 0010 movs r0, r2
+ 162e: f001 f8df bl 27f0 <malloc>
+ 1632: 0004 movs r4, r0
+ buffer[0] = strlen((const char*)string) * 2 + 2;
+ 1634: 0030 movs r0, r6
+ 1636: f001 f9bb bl 29b0 <strlen>
+ 163a: 3001 adds r0, #1
+ 163c: 0040 lsls r0, r0, #1
+ buffer[1] = 0x03;
+ 163e: 2303 movs r3, #3
+ buffer[0] = strlen((const char*)string) * 2 + 2;
+ 1640: 7020 strb r0, [r4, #0]
+ for (i = 2; i < maxlen && *string; i++) {
+ 1642: 2202 movs r2, #2
+ buffer[i] = 0;
+ 1644: 0038 movs r0, r7
+ buffer[1] = 0x03;
+ 1646: 7063 strb r3, [r4, #1]
+ for (i = 2; i < maxlen && *string; i++) {
+ 1648: 4295 cmp r5, r2
+ 164a: d90d bls.n 1668 <_ZN14USBDeviceClass20sendStringDescriptorEPKhm+0x48>
+ 164c: 7831 ldrb r1, [r6, #0]
+ 164e: 2900 cmp r1, #0
+ 1650: d00a beq.n 1668 <_ZN14USBDeviceClass20sendStringDescriptorEPKhm+0x48>
+ buffer[i++] = *string++;
+ 1652: 1c53 adds r3, r2, #1
+ 1654: b2db uxtb r3, r3
+ 1656: 3601 adds r6, #1
+ 1658: 54a1 strb r1, [r4, r2]
+ if (i == maxlen) break;
+ 165a: 429d cmp r5, r3
+ 165c: d003 beq.n 1666 <_ZN14USBDeviceClass20sendStringDescriptorEPKhm+0x46>
+ for (i = 2; i < maxlen && *string; i++) {
+ 165e: 3202 adds r2, #2
+ buffer[i] = 0;
+ 1660: 54e0 strb r0, [r4, r3]
+ for (i = 2; i < maxlen && *string; i++) {
+ 1662: b2d2 uxtb r2, r2
+ 1664: e7f0 b.n 1648 <_ZN14USBDeviceClass20sendStringDescriptorEPKhm+0x28>
+ buffer[i++] = *string++;
+ 1666: 002a movs r2, r5
+ bool ret = USBDevice.sendControl(buffer, i);
+ 1668: 0021 movs r1, r4
+ 166a: 4805 ldr r0, [pc, #20] ; (1680 <_ZN14USBDeviceClass20sendStringDescriptorEPKhm+0x60>)
+ 166c: f7ff ffae bl 15cc <_ZN14USBDeviceClass11sendControlEPKvm>
+ 1670: 1e47 subs r7, r0, #1
+ 1672: 41b8 sbcs r0, r7
+ 1674: b2c7 uxtb r7, r0
+ free(buffer);
+ 1676: 0020 movs r0, r4
+ 1678: f001 f8c4 bl 2804 <free>
+}
+ 167c: 0038 movs r0, r7
+ 167e: bdf8 pop {r3, r4, r5, r6, r7, pc}
+ 1680: 2000013c .word 0x2000013c
+
+00001684 <_ZN14USBDeviceClass17sendConfigurationEm>:
+{
+ 1684: b5f0 push {r4, r5, r6, r7, lr}
+ uint32_t total = 0;
+ 1686: 2700 movs r7, #0
+ _dry_run = true;
+ 1688: 2601 movs r6, #1
+{
+ 168a: b087 sub sp, #28
+ _dry_run = true;
+ 168c: 4b1e ldr r3, [pc, #120] ; (1708 <_ZN14USBDeviceClass17sendConfigurationEm+0x84>)
+{
+ 168e: 9100 str r1, [sp, #0]
+ uint8_t interfaces = SendInterfaces(&total);
+ 1690: a902 add r1, sp, #8
+ _dry_run = true;
+ 1692: 701e strb r6, [r3, #0]
+{
+ 1694: 0005 movs r5, r0
+ uint32_t total = 0;
+ 1696: 9702 str r7, [sp, #8]
+ uint8_t interfaces = SendInterfaces(&total);
+ 1698: f7ff fc65 bl f66 <_ZN14USBDeviceClass14SendInterfacesEPm>
+ ConfigDescriptor config = D_CONFIG((uint16_t)(total + sizeof(ConfigDescriptor)), interfaces);
+ 169c: ac03 add r4, sp, #12
+ uint8_t interfaces = SendInterfaces(&total);
+ 169e: 9001 str r0, [sp, #4]
+ ConfigDescriptor config = D_CONFIG((uint16_t)(total + sizeof(ConfigDescriptor)), interfaces);
+ 16a0: 2209 movs r2, #9
+ 16a2: 0039 movs r1, r7
+ 16a4: 0020 movs r0, r4
+ 16a6: f001 f8c0 bl 282a <memset>
+ 16aa: 2309 movs r3, #9
+ 16ac: 7023 strb r3, [r4, #0]
+ 16ae: 2302 movs r3, #2
+ 16b0: 7063 strb r3, [r4, #1]
+ 16b2: 339e adds r3, #158 ; 0x9e
+ 16b4: 71e3 strb r3, [r4, #7]
+ 16b6: 335a adds r3, #90 ; 0x5a
+ 16b8: 7223 strb r3, [r4, #8]
+ 16ba: 9b02 ldr r3, [sp, #8]
+ 16bc: 7166 strb r6, [r4, #5]
+ 16be: 3309 adds r3, #9
+ 16c0: 8063 strh r3, [r4, #2]
+ 16c2: 466b mov r3, sp
+ 16c4: 791b ldrb r3, [r3, #4]
+ 16c6: 7123 strb r3, [r4, #4]
+ _dry_run = false;
+ 16c8: 4b0f ldr r3, [pc, #60] ; (1708 <_ZN14USBDeviceClass17sendConfigurationEm+0x84>)
+ 16ca: 701f strb r7, [r3, #0]
+ if (maxlen == sizeof(ConfigDescriptor)) {
+ 16cc: 9b00 ldr r3, [sp, #0]
+ 16ce: 2b09 cmp r3, #9
+ 16d0: d107 bne.n 16e2 <_ZN14USBDeviceClass17sendConfigurationEm+0x5e>
+ sendControl(&config, sizeof(ConfigDescriptor));
+ 16d2: 001a movs r2, r3
+ 16d4: 0021 movs r1, r4
+ sendControl(_pack_buffer, _pack_size);
+ 16d6: 0028 movs r0, r5
+ 16d8: f7ff ff78 bl 15cc <_ZN14USBDeviceClass11sendControlEPKvm>
+}
+ 16dc: 2001 movs r0, #1
+ 16de: b007 add sp, #28
+ 16e0: bdf0 pop {r4, r5, r6, r7, pc}
+ _pack_message = true;
+ 16e2: 4b0a ldr r3, [pc, #40] ; (170c <_ZN14USBDeviceClass17sendConfigurationEm+0x88>)
+ sendControl(&config, sizeof(ConfigDescriptor));
+ 16e4: 2209 movs r2, #9
+ _pack_message = true;
+ 16e6: 701e strb r6, [r3, #0]
+ _pack_size = 0;
+ 16e8: 4e09 ldr r6, [pc, #36] ; (1710 <_ZN14USBDeviceClass17sendConfigurationEm+0x8c>)
+ sendControl(&config, sizeof(ConfigDescriptor));
+ 16ea: 0021 movs r1, r4
+ 16ec: 0028 movs r0, r5
+ total = 0;
+ 16ee: 9702 str r7, [sp, #8]
+ _pack_size = 0;
+ 16f0: 8037 strh r7, [r6, #0]
+ sendControl(&config, sizeof(ConfigDescriptor));
+ 16f2: f7ff ff6b bl 15cc <_ZN14USBDeviceClass11sendControlEPKvm>
+ SendInterfaces(&total);
+ 16f6: a902 add r1, sp, #8
+ 16f8: 0028 movs r0, r5
+ 16fa: f7ff fc34 bl f66 <_ZN14USBDeviceClass14SendInterfacesEPm>
+ _pack_message = false;
+ 16fe: 4b03 ldr r3, [pc, #12] ; (170c <_ZN14USBDeviceClass17sendConfigurationEm+0x88>)
+ sendControl(_pack_buffer, _pack_size);
+ 1700: 8832 ldrh r2, [r6, #0]
+ _pack_message = false;
+ 1702: 701f strb r7, [r3, #0]
+ sendControl(_pack_buffer, _pack_size);
+ 1704: 4903 ldr r1, [pc, #12] ; (1714 <_ZN14USBDeviceClass17sendConfigurationEm+0x90>)
+ 1706: e7e6 b.n 16d6 <_ZN14USBDeviceClass17sendConfigurationEm+0x52>
+ 1708: 200004e8 .word 0x200004e8
+ 170c: 200005e9 .word 0x200005e9
+ 1710: 200005ea .word 0x200005ea
+ 1714: 200004e9 .word 0x200004e9
+
+00001718 <_ZN14USBDeviceClass14sendDescriptorER8USBSetup>:
+{
+ 1718: b570 push {r4, r5, r6, lr}
+ uint8_t t = setup.wValueH;
+ 171a: 78ce ldrb r6, [r1, #3]
+{
+ 171c: b092 sub sp, #72 ; 0x48
+ 171e: 0005 movs r5, r0
+ 1720: 000c movs r4, r1
+ if (t == USB_CONFIGURATION_DESCRIPTOR_TYPE)
+ 1722: 2e02 cmp r6, #2
+ 1724: d10b bne.n 173e <_ZN14USBDeviceClass14sendDescriptorER8USBSetup+0x26>
+ return USBDevice.sendConfiguration(setup.wLength);
+ 1726: 798b ldrb r3, [r1, #6]
+ 1728: 79c9 ldrb r1, [r1, #7]
+ 172a: 482e ldr r0, [pc, #184] ; (17e4 <_ZN14USBDeviceClass14sendDescriptorER8USBSetup+0xcc>)
+ 172c: 0209 lsls r1, r1, #8
+ 172e: 4319 orrs r1, r3
+ 1730: f7ff ffa8 bl 1684 <_ZN14USBDeviceClass17sendConfigurationEm>
+ 1734: 1e41 subs r1, r0, #1
+ 1736: 4188 sbcs r0, r1
+ 1738: b2c0 uxtb r0, r0
+}
+ 173a: b012 add sp, #72 ; 0x48
+ 173c: bd70 pop {r4, r5, r6, pc}
+ ret = PluggableUSB().getDescriptor(setup);
+ 173e: f7ff f9a3 bl a88 <_Z12PluggableUSBv>
+ 1742: 0021 movs r1, r4
+ 1744: f7ff f934 bl 9b0 <_ZN13PluggableUSB_13getDescriptorER8USBSetup>
+ if (ret != 0) {
+ 1748: 2800 cmp r0, #0
+ 174a: d003 beq.n 1754 <_ZN14USBDeviceClass14sendDescriptorER8USBSetup+0x3c>
+ return (ret > 0 ? true : false);
+ 174c: 17c1 asrs r1, r0, #31
+ 174e: 1a08 subs r0, r1, r0
+ 1750: 0fc0 lsrs r0, r0, #31
+ 1752: e7f2 b.n 173a <_ZN14USBDeviceClass14sendDescriptorER8USBSetup+0x22>
+ if (t == USB_DEVICE_DESCRIPTOR_TYPE)
+ 1754: 2e01 cmp r6, #1
+ 1756: d10e bne.n 1776 <_ZN14USBDeviceClass14sendDescriptorER8USBSetup+0x5e>
+ if (setup.wLength == 8)
+ 1758: 79e2 ldrb r2, [r4, #7]
+ 175a: 79a3 ldrb r3, [r4, #6]
+ 175c: 0212 lsls r2, r2, #8
+ 175e: 431a orrs r2, r3
+ 1760: 4921 ldr r1, [pc, #132] ; (17e8 <_ZN14USBDeviceClass14sendDescriptorER8USBSetup+0xd0>)
+ if (*desc_addr > setup.wLength) {
+ 1762: 2a11 cmp r2, #17
+ 1764: dc3c bgt.n 17e0 <_ZN14USBDeviceClass14sendDescriptorER8USBSetup+0xc8>
+ desc_length = setup.wLength;
+ 1766: b2d2 uxtb r2, r2
+ if (desc_length == 0) {
+ 1768: 2a00 cmp r2, #0
+ 176a: d039 beq.n 17e0 <_ZN14USBDeviceClass14sendDescriptorER8USBSetup+0xc8>
+ sendControl(desc_addr, desc_length);
+ 176c: 0028 movs r0, r5
+ 176e: f7ff ff2d bl 15cc <_ZN14USBDeviceClass11sendControlEPKvm>
+ return true;
+ 1772: 2001 movs r0, #1
+ 1774: e7e1 b.n 173a <_ZN14USBDeviceClass14sendDescriptorER8USBSetup+0x22>
+ else if (USB_STRING_DESCRIPTOR_TYPE == t)
+ 1776: 2e03 cmp r6, #3
+ 1778: d1df bne.n 173a <_ZN14USBDeviceClass14sendDescriptorER8USBSetup+0x22>
+ if (setup.wValueL == 0) {
+ 177a: 78a3 ldrb r3, [r4, #2]
+ 177c: 2b00 cmp r3, #0
+ 177e: d028 beq.n 17d2 <_ZN14USBDeviceClass14sendDescriptorER8USBSetup+0xba>
+ else if (setup.wValueL == IPRODUCT) {
+ 1780: 2b02 cmp r3, #2
+ 1782: d108 bne.n 1796 <_ZN14USBDeviceClass14sendDescriptorER8USBSetup+0x7e>
+ return sendStringDescriptor(STRING_PRODUCT, setup.wLength);
+ 1784: 79e2 ldrb r2, [r4, #7]
+ 1786: 79a3 ldrb r3, [r4, #6]
+ 1788: 0212 lsls r2, r2, #8
+ 178a: 4918 ldr r1, [pc, #96] ; (17ec <_ZN14USBDeviceClass14sendDescriptorER8USBSetup+0xd4>)
+ 178c: 431a orrs r2, r3
+ return sendStringDescriptor(STRING_MANUFACTURER, setup.wLength);
+ 178e: 0028 movs r0, r5
+ 1790: f7ff ff46 bl 1620 <_ZN14USBDeviceClass20sendStringDescriptorEPKhm>
+ 1794: e7d1 b.n 173a <_ZN14USBDeviceClass14sendDescriptorER8USBSetup+0x22>
+ else if (setup.wValueL == IMANUFACTURER) {
+ 1796: 2b01 cmp r3, #1
+ 1798: d105 bne.n 17a6 <_ZN14USBDeviceClass14sendDescriptorER8USBSetup+0x8e>
+ return sendStringDescriptor(STRING_MANUFACTURER, setup.wLength);
+ 179a: 79e2 ldrb r2, [r4, #7]
+ 179c: 79a3 ldrb r3, [r4, #6]
+ 179e: 0212 lsls r2, r2, #8
+ 17a0: 431a orrs r2, r3
+ 17a2: 4913 ldr r1, [pc, #76] ; (17f0 <_ZN14USBDeviceClass14sendDescriptorER8USBSetup+0xd8>)
+ 17a4: e7f3 b.n 178e <_ZN14USBDeviceClass14sendDescriptorER8USBSetup+0x76>
+ else if (setup.wValueL == ISERIAL) {
+ 17a6: 2b03 cmp r3, #3
+ 17a8: d1c7 bne.n 173a <_ZN14USBDeviceClass14sendDescriptorER8USBSetup+0x22>
+ memset(name, 0, sizeof(name));
+ 17aa: 0001 movs r1, r0
+ 17ac: 2241 movs r2, #65 ; 0x41
+ 17ae: a801 add r0, sp, #4
+ 17b0: f001 f83b bl 282a <memset>
+ idx += PluggableUSB().getShortName(&name[idx]);
+ 17b4: f7ff f968 bl a88 <_Z12PluggableUSBv>
+ 17b8: a901 add r1, sp, #4
+ 17ba: f7ff f909 bl 9d0 <_ZN13PluggableUSB_12getShortNameEPc>
+ if (idx > 0) {
+ 17be: 2800 cmp r0, #0
+ 17c0: d005 beq.n 17ce <_ZN14USBDeviceClass14sendDescriptorER8USBSetup+0xb6>
+ return sendStringDescriptor((uint8_t*)name, setup.wLength);
+ 17c2: 79e2 ldrb r2, [r4, #7]
+ 17c4: 79a3 ldrb r3, [r4, #6]
+ 17c6: 0212 lsls r2, r2, #8
+ 17c8: 431a orrs r2, r3
+ 17ca: a901 add r1, sp, #4
+ 17cc: e7df b.n 178e <_ZN14USBDeviceClass14sendDescriptorER8USBSetup+0x76>
+ if (*desc_addr > setup.wLength) {
+ 17ce: 7803 ldrb r3, [r0, #0]
+ 17d0: deff udf #255 ; 0xff
+ 17d2: 79e2 ldrb r2, [r4, #7]
+ 17d4: 79a3 ldrb r3, [r4, #6]
+ 17d6: 0212 lsls r2, r2, #8
+ 17d8: 431a orrs r2, r3
+ 17da: 4906 ldr r1, [pc, #24] ; (17f4 <_ZN14USBDeviceClass14sendDescriptorER8USBSetup+0xdc>)
+ 17dc: 2a03 cmp r2, #3
+ 17de: ddc2 ble.n 1766 <_ZN14USBDeviceClass14sendDescriptorER8USBSetup+0x4e>
+ desc_length = *desc_addr;
+ 17e0: 780a ldrb r2, [r1, #0]
+ 17e2: e7c3 b.n 176c <_ZN14USBDeviceClass14sendDescriptorER8USBSetup+0x54>
+ 17e4: 2000013c .word 0x2000013c
+ 17e8: 00002a8f .word 0x00002a8f
+ 17ec: 00002a74 .word 0x00002a74
+ 17f0: 00002a82 .word 0x00002a82
+ 17f4: 00002a7e .word 0x00002a7e
+
+000017f8 <_ZN14USBDeviceClass7sendZlpEm>:
+ 17f8: b2cb uxtb r3, r1
+ 17fa: 4904 ldr r1, [pc, #16] ; (180c <_ZN14USBDeviceClass7sendZlpEm+0x14>)
+ 17fc: 015b lsls r3, r3, #5
+ 17fe: 18c9 adds r1, r1, r3
+ 1800: 698b ldr r3, [r1, #24]
+ 1802: 0b9b lsrs r3, r3, #14
+ 1804: 039b lsls r3, r3, #14
+ 1806: 618b str r3, [r1, #24]
+
+void USBDeviceClass::sendZlp(uint32_t ep)
+{
+ // Set the byte count as zero
+ usbd.epBank1SetByteCount(ep, 0);
+}
+ 1808: 4770 bx lr
+ 180a: 46c0 nop ; (mov r8, r8)
+ 180c: 200005f4 .word 0x200005f4
+
+00001810 <_ZN14USBDeviceClass19handleStandardSetupER8USBSetup>:
+
+bool USBDeviceClass::handleStandardSetup(USBSetup &setup)
+{
+ 1810: b537 push {r0, r1, r2, r4, r5, lr}
+ 1812: 0005 movs r5, r0
+ switch (setup.bRequest) {
+ 1814: 7848 ldrb r0, [r1, #1]
+{
+ 1816: 000c movs r4, r1
+ switch (setup.bRequest) {
+ 1818: 280b cmp r0, #11
+ 181a: d811 bhi.n 1840 <_ZN14USBDeviceClass19handleStandardSetupER8USBSetup+0x30>
+ 181c: f000 ff2e bl 267c <__gnu_thumb1_case_uqi>
+ 1820: 2e101d06 .word 0x2e101d06
+ 1824: 64484310 .word 0x64484310
+ 1828: 605d4f4c .word 0x605d4f4c
+ case GET_STATUS:
+ if (setup.bmRequestType == 0) // device
+ 182c: 7809 ldrb r1, [r1, #0]
+ 182e: aa01 add r2, sp, #4
+ 1830: 2900 cmp r1, #0
+ 1832: d107 bne.n 1844 <_ZN14USBDeviceClass19handleStandardSetupER8USBSetup+0x34>
+ {
+ // Send the device status
+ // TODO: Check current configuration for power mode (if device is configured)
+ // TODO: Check if remote wake-up is enabled
+ uint8_t buff[] = { 0, 0 };
+ armSend(0, buff, 2);
+ 1834: 2302 movs r3, #2
+ uint8_t buff[] = { 0, 0 };
+ 1836: 7011 strb r1, [r2, #0]
+ 1838: 7051 strb r1, [r2, #1]
+ armSend(0, buff, 2);
+ 183a: 0028 movs r0, r5
+ 183c: f7ff fea2 bl 1584 <_ZN14USBDeviceClass7armSendEmPKvm>
+ return true;
+ 1840: 2001 movs r0, #1
+
+ default:
+ return true;
+ }
+ return true;
+}
+ 1842: bd3e pop {r1, r2, r3, r4, r5, pc}
+ uint8_t buff[] = { 0, 0 };
+ 1844: 2300 movs r3, #0
+ 1846: 7013 strb r3, [r2, #0]
+ 1848: 7053 strb r3, [r2, #1]
+ if (isEndpointHalt == 1)
+ 184a: 4b28 ldr r3, [pc, #160] ; (18ec <_ZN14USBDeviceClass19handleStandardSetupER8USBSetup+0xdc>)
+ if (isRemoteWakeUpEnabled == 1)
+ 184c: 781b ldrb r3, [r3, #0]
+ 184e: 2b01 cmp r3, #1
+ 1850: d100 bne.n 1854 <_ZN14USBDeviceClass19handleStandardSetupER8USBSetup+0x44>
+ buff[0] = 1;
+ 1852: 7013 strb r3, [r2, #0]
+ armSend(0, buff, 2);
+ 1854: 2302 movs r3, #2
+ armSend(0, (void*)&_usbSetInterface, 1);
+ 1856: 2100 movs r1, #0
+ 1858: e7ef b.n 183a <_ZN14USBDeviceClass19handleStandardSetupER8USBSetup+0x2a>
+ if (setup.wValueL == 1) // DEVICEREMOTEWAKEUP
+ 185a: 788a ldrb r2, [r1, #2]
+ 185c: 2300 movs r3, #0
+ 185e: 2a01 cmp r2, #1
+ 1860: d104 bne.n 186c <_ZN14USBDeviceClass19handleStandardSetupER8USBSetup+0x5c>
+ uint8_t buff[] = { 0, 0 };
+ 1862: aa01 add r2, sp, #4
+ 1864: 7013 strb r3, [r2, #0]
+ 1866: 7053 strb r3, [r2, #1]
+ if (isRemoteWakeUpEnabled == 1)
+ 1868: 4b21 ldr r3, [pc, #132] ; (18f0 <_ZN14USBDeviceClass19handleStandardSetupER8USBSetup+0xe0>)
+ 186a: e7ef b.n 184c <_ZN14USBDeviceClass19handleStandardSetupER8USBSetup+0x3c>
+ isEndpointHalt = 0;
+ 186c: 4a1f ldr r2, [pc, #124] ; (18ec <_ZN14USBDeviceClass19handleStandardSetupER8USBSetup+0xdc>)
+ 186e: 7013 strb r3, [r2, #0]
+ 1870: 4a20 ldr r2, [pc, #128] ; (18f4 <_ZN14USBDeviceClass19handleStandardSetupER8USBSetup+0xe4>)
+ 1872: 6993 ldr r3, [r2, #24]
+ 1874: 0b9b lsrs r3, r3, #14
+ 1876: 039b lsls r3, r3, #14
+ 1878: 6193 str r3, [r2, #24]
+ 187a: e7e1 b.n 1840 <_ZN14USBDeviceClass19handleStandardSetupER8USBSetup+0x30>
+ if (setup.wValueL == 1) // DEVICEREMOTEWAKEUP
+ 187c: 788c ldrb r4, [r1, #2]
+ 187e: 2c01 cmp r4, #1
+ 1880: d106 bne.n 1890 <_ZN14USBDeviceClass19handleStandardSetupER8USBSetup+0x80>
+ uint8_t buff[] = { 0 };
+ 1882: 2100 movs r1, #0
+ isRemoteWakeUpEnabled = 1;
+ 1884: 4b1a ldr r3, [pc, #104] ; (18f0 <_ZN14USBDeviceClass19handleStandardSetupER8USBSetup+0xe0>)
+ uint8_t buff[] = { 0 };
+ 1886: aa01 add r2, sp, #4
+ isRemoteWakeUpEnabled = 1;
+ 1888: 701c strb r4, [r3, #0]
+ uint8_t buff[] = { 0 };
+ 188a: 7011 strb r1, [r2, #0]
+ armSend(0, buff, 1);
+ 188c: 0023 movs r3, r4
+ 188e: e7d4 b.n 183a <_ZN14USBDeviceClass19handleStandardSetupER8USBSetup+0x2a>
+ 1890: 2001 movs r0, #1
+ if (setup.wValueL == 0) // ENDPOINTHALT
+ 1892: 2c00 cmp r4, #0
+ 1894: d1d5 bne.n 1842 <_ZN14USBDeviceClass19handleStandardSetupER8USBSetup+0x32>
+ isEndpointHalt = 1;
+ 1896: 4b15 ldr r3, [pc, #84] ; (18ec <_ZN14USBDeviceClass19handleStandardSetupER8USBSetup+0xdc>)
+ 1898: 4a16 ldr r2, [pc, #88] ; (18f4 <_ZN14USBDeviceClass19handleStandardSetupER8USBSetup+0xe4>)
+ 189a: 7018 strb r0, [r3, #0]
+ 189c: 6993 ldr r3, [r2, #24]
+ 189e: 0b9b lsrs r3, r3, #14
+ 18a0: 039b lsls r3, r3, #14
+ 18a2: 6193 str r3, [r2, #24]
+ return true;
+ 18a4: e7cd b.n 1842 <_ZN14USBDeviceClass19handleStandardSetupER8USBSetup+0x32>
+ setAddress(setup.wValueL);
+ 18a6: 7889 ldrb r1, [r1, #2]
+ 18a8: 0028 movs r0, r5
+ 18aa: f7ff fc21 bl 10f0 <_ZN14USBDeviceClass10setAddressEm>
+ 18ae: e7c7 b.n 1840 <_ZN14USBDeviceClass19handleStandardSetupER8USBSetup+0x30>
+ return sendDescriptor(setup);
+ 18b0: 0028 movs r0, r5
+ 18b2: f7ff ff31 bl 1718 <_ZN14USBDeviceClass14sendDescriptorER8USBSetup>
+ 18b6: e7c4 b.n 1842 <_ZN14USBDeviceClass19handleStandardSetupER8USBSetup+0x32>
+ armSend(0, (void*)&_usbConfiguration, 1);
+ 18b8: 2301 movs r3, #1
+ 18ba: 4a0f ldr r2, [pc, #60] ; (18f8 <_ZN14USBDeviceClass19handleStandardSetupER8USBSetup+0xe8>)
+ 18bc: e7cb b.n 1856 <_ZN14USBDeviceClass19handleStandardSetupER8USBSetup+0x46>
+ if (REQUEST_DEVICE == (setup.bmRequestType & REQUEST_RECIPIENT)) {
+ 18be: 780b ldrb r3, [r1, #0]
+ return false;
+ 18c0: 2000 movs r0, #0
+ if (REQUEST_DEVICE == (setup.bmRequestType & REQUEST_RECIPIENT)) {
+ 18c2: 06db lsls r3, r3, #27
+ 18c4: d1bd bne.n 1842 <_ZN14USBDeviceClass19handleStandardSetupER8USBSetup+0x32>
+ initEndpoints();
+ 18c6: 0028 movs r0, r5
+ 18c8: f7ff fcca bl 1260 <_ZN14USBDeviceClass13initEndpointsEv>
+ _usbConfiguration = setup.wValueL;
+ 18cc: 78a2 ldrb r2, [r4, #2]
+ 18ce: 4b0a ldr r3, [pc, #40] ; (18f8 <_ZN14USBDeviceClass19handleStandardSetupER8USBSetup+0xe8>)
+ SerialUSB.enableInterrupt();
+ 18d0: 480a ldr r0, [pc, #40] ; (18fc <_ZN14USBDeviceClass19handleStandardSetupER8USBSetup+0xec>)
+ _usbConfiguration = setup.wValueL;
+ 18d2: 601a str r2, [r3, #0]
+ SerialUSB.enableInterrupt();
+ 18d4: f7ff f834 bl 940 <_ZN7Serial_15enableInterruptEv>
+ 18d8: e7ca b.n 1870 <_ZN14USBDeviceClass19handleStandardSetupER8USBSetup+0x60>
+ armSend(0, (void*)&_usbSetInterface, 1);
+ 18da: 2301 movs r3, #1
+ 18dc: 4a08 ldr r2, [pc, #32] ; (1900 <_ZN14USBDeviceClass19handleStandardSetupER8USBSetup+0xf0>)
+ 18de: e7ba b.n 1856 <_ZN14USBDeviceClass19handleStandardSetupER8USBSetup+0x46>
+ _usbSetInterface = setup.wValueL;
+ 18e0: 788a ldrb r2, [r1, #2]
+ 18e2: 4b07 ldr r3, [pc, #28] ; (1900 <_ZN14USBDeviceClass19handleStandardSetupER8USBSetup+0xf0>)
+ 18e4: 601a str r2, [r3, #0]
+ 18e6: e7c3 b.n 1870 <_ZN14USBDeviceClass19handleStandardSetupER8USBSetup+0x60>
+ return false;
+ 18e8: 2000 movs r0, #0
+ 18ea: e7aa b.n 1842 <_ZN14USBDeviceClass19handleStandardSetupER8USBSetup+0x32>
+ 18ec: 2000015c .word 0x2000015c
+ 18f0: 20000164 .word 0x20000164
+ 18f4: 200005f4 .word 0x200005f4
+ 18f8: 200005ec .word 0x200005ec
+ 18fc: 200000d4 .word 0x200000d4
+ 1900: 200005f0 .word 0x200005f0
+
+00001904 <_ZN14USBDeviceClass10ISRHandlerEv>:
+
+void USBDeviceClass::ISRHandler()
+{
+ if (_pack_message == true) {
+ 1904: 4b3b ldr r3, [pc, #236] ; (19f4 <_ZN14USBDeviceClass10ISRHandlerEv+0xf0>)
+{
+ 1906: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr}
+ if (_pack_message == true) {
+ 1908: 781e ldrb r6, [r3, #0]
+{
+ 190a: 0005 movs r5, r0
+ if (_pack_message == true) {
+ 190c: 2e00 cmp r6, #0
+ 190e: d161 bne.n 19d4 <_ZN14USBDeviceClass10ISRHandlerEv+0xd0>
+ inline bool isEndOfResetInterrupt() { return usb.INTFLAG.bit.EORST; }
+ 1910: 4c39 ldr r4, [pc, #228] ; (19f8 <_ZN14USBDeviceClass10ISRHandlerEv+0xf4>)
+ 1912: 6823 ldr r3, [r4, #0]
+ 1914: 8b9a ldrh r2, [r3, #28]
+ return;
+ }
+
+ // End-Of-Reset
+ if (usbd.isEndOfResetInterrupt())
+ 1916: 0712 lsls r2, r2, #28
+ 1918: d50d bpl.n 1936 <_ZN14USBDeviceClass10ISRHandlerEv+0x32>
+ inline void ackEndOfResetInterrupt() { usb.INTFLAG.reg = USB_DEVICE_INTFLAG_EORST; }
+ 191a: 2208 movs r2, #8
+ 191c: 0031 movs r1, r6
+ 191e: 839a strh r2, [r3, #28]
+ 1920: 0030 movs r0, r6
+ 1922: f7ff f8c9 bl ab8 <_ZN14USBDeviceClass6initEPEmm.part.7>
+ inline void epBank0EnableSetupReceived(ep_t ep) { usb.DeviceEndpoint[ep].EPINTENSET.bit.RXSTP = 1; }
+ 1926: 2210 movs r2, #16
+ 1928: 6823 ldr r3, [r4, #0]
+ 192a: 33ff adds r3, #255 ; 0xff
+ 192c: 7a99 ldrb r1, [r3, #10]
+ 192e: 430a orrs r2, r1
+ 1930: 729a strb r2, [r3, #10]
+ initEP(0, USB_ENDPOINT_TYPE_CONTROL);
+
+ // Enable Setup-Received interrupt
+ usbd.epBank0EnableSetupReceived(0);
+
+ _usbConfiguration = 0;
+ 1932: 4b32 ldr r3, [pc, #200] ; (19fc <_ZN14USBDeviceClass10ISRHandlerEv+0xf8>)
+ 1934: 601e str r6, [r3, #0]
+ inline bool isStartOfFrameInterrupt() { return usb.INTFLAG.bit.SOF; }
+ 1936: 6823 ldr r3, [r4, #0]
+ 1938: 8b9a ldrh r2, [r3, #28]
+ }
+
+ // Start-Of-Frame
+ if (usbd.isStartOfFrameInterrupt())
+ 193a: 0752 lsls r2, r2, #29
+ 193c: d501 bpl.n 1942 <_ZN14USBDeviceClass10ISRHandlerEv+0x3e>
+ inline void ackStartOfFrameInterrupt() { usb.INTFLAG.reg = USB_DEVICE_INTFLAG_SOF; }
+ 193e: 2204 movs r2, #4
+ 1940: 839a strh r2, [r3, #28]
+ inline bool epBank0IsStalled(ep_t ep) { return usb.DeviceEndpoint[ep].EPINTFLAG.bit.STALL0; }
+ 1942: 33ff adds r3, #255 ; 0xff
+ 1944: 7a1a ldrb r2, [r3, #8]
+ }
+#endif
+ }
+
+ /* Remove any stall requests for endpoint #0 */
+ if (usbd.epBank0IsStalled(0)) { usbd.epBank0DisableStalled(0); }
+ 1946: 0692 lsls r2, r2, #26
+ 1948: d503 bpl.n 1952 <_ZN14USBDeviceClass10ISRHandlerEv+0x4e>
+ inline void epBank0DisableStalled(ep_t ep) { usb.DeviceEndpoint[ep].EPINTENCLR.bit.STALL0 = 1; }
+ 194a: 2220 movs r2, #32
+ 194c: 7a59 ldrb r1, [r3, #9]
+ 194e: 430a orrs r2, r1
+ 1950: 725a strb r2, [r3, #9]
+ inline bool epBank0IsSetupReceived(ep_t ep) { return usb.DeviceEndpoint[ep].EPINTFLAG.bit.RXSTP; }
+ 1952: 7a1a ldrb r2, [r3, #8]
+
+ // Endpoint 0 Received Setup interrupt
+ if (usbd.epBank0IsSetupReceived(0))
+ 1954: 06d2 lsls r2, r2, #27
+ 1956: d525 bpl.n 19a4 <_ZN14USBDeviceClass10ISRHandlerEv+0xa0>
+ {
+ /* Retrieve received endpoint #0 data from buffer */
+ USBSetup setup;
+ memcpy(&setup, udd_ep_out_cache_buffer[0], sizeof(USBSetup));
+ 1958: 4668 mov r0, sp
+ 195a: 4a29 ldr r2, [pc, #164] ; (1a00 <_ZN14USBDeviceClass10ISRHandlerEv+0xfc>)
+ 195c: 4669 mov r1, sp
+ 195e: cac0 ldmia r2!, {r6, r7}
+ 1960: c0c0 stmia r0!, {r6, r7}
+ inline void epBank0SetByteCount(ep_t ep, uint16_t bc) { EP[ep].DeviceDescBank[0].PCKSIZE.bit.BYTE_COUNT = bc; }
+ 1962: 68a2 ldr r2, [r4, #8]
+ 1964: 0b92 lsrs r2, r2, #14
+ 1966: 0392 lsls r2, r2, #14
+ 1968: 60a2 str r2, [r4, #8]
+ inline void epBank0ResetReady(ep_t ep) { usb.DeviceEndpoint[ep].EPSTATUSCLR.bit.BK0RDY = 1; }
+ 196a: 2240 movs r2, #64 ; 0x40
+ 196c: 7958 ldrb r0, [r3, #5]
+ 196e: 4302 orrs r2, r0
+ 1970: 715a strb r2, [r3, #5]
+ */
+ usbd.epBank0SetByteCount(0, 0);
+ usbd.epBank0ResetReady(0);
+
+ bool ok;
+ if (REQUEST_STANDARD == (setup.bmRequestType & REQUEST_TYPE)) {
+ 1972: 2360 movs r3, #96 ; 0x60
+ 1974: 780a ldrb r2, [r1, #0]
+ // Standard Requests
+ ok = handleStandardSetup(setup);
+ 1976: 0028 movs r0, r5
+ if (REQUEST_STANDARD == (setup.bmRequestType & REQUEST_TYPE)) {
+ 1978: 421a tst r2, r3
+ 197a: d12c bne.n 19d6 <_ZN14USBDeviceClass10ISRHandlerEv+0xd2>
+ ok = handleStandardSetup(setup);
+ 197c: f7ff ff48 bl 1810 <_ZN14USBDeviceClass19handleStandardSetupER8USBSetup>
+ } else {
+ // Class Interface Requests
+ ok = handleClassInterfaceSetup(setup);
+ }
+
+ if (ok) {
+ 1980: 2800 cmp r0, #0
+ 1982: d02b beq.n 19dc <_ZN14USBDeviceClass10ISRHandlerEv+0xd8>
+ inline void epBank1SetReady(ep_t ep) { usb.DeviceEndpoint[ep].EPSTATUSSET.bit.BK1RDY = 1; }
+ 1984: 2280 movs r2, #128 ; 0x80
+ 1986: 6823 ldr r3, [r4, #0]
+ 1988: 4252 negs r2, r2
+ 198a: 33ff adds r3, #255 ; 0xff
+ 198c: 7999 ldrb r1, [r3, #6]
+ 198e: 430a orrs r2, r1
+ USB->DEVICE.DeviceEndpoint[ep].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_STALLRQ(2);
+ 1990: 719a strb r2, [r3, #6]
+ inline bool epBank1IsStalled(ep_t ep) { return usb.DeviceEndpoint[ep].EPINTFLAG.bit.STALL1; }
+ 1992: 6823 ldr r3, [r4, #0]
+ 1994: 33ff adds r3, #255 ; 0xff
+ 1996: 7a1a ldrb r2, [r3, #8]
+ usbd.epBank1SetReady(0);
+ } else {
+ stall(0);
+ }
+
+ if (usbd.epBank1IsStalled(0))
+ 1998: 0652 lsls r2, r2, #25
+ 199a: d503 bpl.n 19a4 <_ZN14USBDeviceClass10ISRHandlerEv+0xa0>
+ inline void epBank1DisableStalled(ep_t ep) { usb.DeviceEndpoint[ep].EPINTENCLR.bit.STALL1 = 1; }
+ 199c: 2240 movs r2, #64 ; 0x40
+ 199e: 7a59 ldrb r1, [r3, #9]
+ 19a0: 430a orrs r2, r1
+ 19a2: 725a strb r2, [r3, #9]
+ inline void epAckPendingInterrupts(ep_t ep) { usb.DeviceEndpoint[ep].EPINTFLAG.reg = 0x7F; }
+ 19a4: 267f movs r6, #127 ; 0x7f
+ usbd.epBank1DisableStalled(0);
+ }
+ } // end Received Setup handler
+ usbd.epAckPendingInterrupts(0);
+
+ for (int ep = 1; ep < USB_EPT_NUM; ep++) {
+ 19a6: 2501 movs r5, #1
+ 19a8: 6823 ldr r3, [r4, #0]
+ 19aa: 33ff adds r3, #255 ; 0xff
+ 19ac: 721e strb r6, [r3, #8]
+ inline bool epHasPendingInterrupts(ep_t ep) { return usb.DeviceEndpoint[ep].EPINTFLAG.reg != 0; }
+ 19ae: 002f movs r7, r5
+ 19b0: 6823 ldr r3, [r4, #0]
+ 19b2: 3708 adds r7, #8
+ 19b4: 017f lsls r7, r7, #5
+ 19b6: 19db adds r3, r3, r7
+ 19b8: 79db ldrb r3, [r3, #7]
+ // Endpoint Transfer Complete (0/1) Interrupt
+ if (usbd.epHasPendingInterrupts(ep)) {
+ 19ba: 2b00 cmp r3, #0
+ 19bc: d007 beq.n 19ce <_ZN14USBDeviceClass10ISRHandlerEv+0xca>
+ if (epHandlers[ep]) {
+ 19be: 4b11 ldr r3, [pc, #68] ; (1a04 <_ZN14USBDeviceClass10ISRHandlerEv+0x100>)
+ 19c0: 00aa lsls r2, r5, #2
+ 19c2: 58d0 ldr r0, [r2, r3]
+ 19c4: 2800 cmp r0, #0
+ 19c6: d00c beq.n 19e2 <_ZN14USBDeviceClass10ISRHandlerEv+0xde>
+ epHandlers[ep]->handleEndpoint();
+ 19c8: 6803 ldr r3, [r0, #0]
+ 19ca: 681b ldr r3, [r3, #0]
+ 19cc: 4798 blx r3
+ for (int ep = 1; ep < USB_EPT_NUM; ep++) {
+ 19ce: 3501 adds r5, #1
+ 19d0: 2d08 cmp r5, #8
+ 19d2: d1ec bne.n 19ae <_ZN14USBDeviceClass10ISRHandlerEv+0xaa>
+ usbd.epAckPendingInterrupts(ep);
+ #endif
+ }
+ }
+ }
+}
+ 19d4: bdf7 pop {r0, r1, r2, r4, r5, r6, r7, pc}
+ ok = handleClassInterfaceSetup(setup);
+ 19d6: f7ff fbaf bl 1138 <_ZN14USBDeviceClass25handleClassInterfaceSetupER8USBSetup>
+ 19da: e7d1 b.n 1980 <_ZN14USBDeviceClass10ISRHandlerEv+0x7c>
+ USB->DEVICE.DeviceEndpoint[ep].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_STALLRQ(2);
+ 19dc: 2220 movs r2, #32
+ 19de: 4b0a ldr r3, [pc, #40] ; (1a08 <_ZN14USBDeviceClass10ISRHandlerEv+0x104>)
+ 19e0: e7d6 b.n 1990 <_ZN14USBDeviceClass10ISRHandlerEv+0x8c>
+ PluggableUSB().handleEndpoint(ep);
+ 19e2: f7ff f851 bl a88 <_Z12PluggableUSBv>
+ 19e6: 0029 movs r1, r5
+ 19e8: f7ff f815 bl a16 <_ZN13PluggableUSB_14handleEndpointEi>
+ inline void epAckPendingInterrupts(ep_t ep) { usb.DeviceEndpoint[ep].EPINTFLAG.reg = 0x7F; }
+ 19ec: 6823 ldr r3, [r4, #0]
+ 19ee: 19df adds r7, r3, r7
+ 19f0: 71fe strb r6, [r7, #7]
+ 19f2: e7ec b.n 19ce <_ZN14USBDeviceClass10ISRHandlerEv+0xca>
+ 19f4: 200005e9 .word 0x200005e9
+ 19f8: 200005f4 .word 0x200005f4
+ 19fc: 200005ec .word 0x200005ec
+ 1a00: 20000328 .word 0x20000328
+ 1a04: 20000140 .word 0x20000140
+ 1a08: 410050ff .word 0x410050ff
+
+00001a0c <UDD_Handler>:
+extern "C" void UDD_Handler(void) {
+ 1a0c: b510 push {r4, lr}
+ USBDevice.ISRHandler();
+ 1a0e: 4802 ldr r0, [pc, #8] ; (1a18 <UDD_Handler+0xc>)
+ 1a10: f7ff ff78 bl 1904 <_ZN14USBDeviceClass10ISRHandlerEv>
+}
+ 1a14: bd10 pop {r4, pc}
+ 1a16: 46c0 nop ; (mov r8, r8)
+ 1a18: 2000013c .word 0x2000013c
+
+00001a1c <_GLOBAL__sub_I_usbd>:
+ USBDevice_SAMD21G18x() : usb(USB->DEVICE) {
+ 1a1c: 4a01 ldr r2, [pc, #4] ; (1a24 <_GLOBAL__sub_I_usbd+0x8>)
+ 1a1e: 4b02 ldr r3, [pc, #8] ; (1a28 <_GLOBAL__sub_I_usbd+0xc>)
+ 1a20: 601a str r2, [r3, #0]
+ * USB Device instance
+ * -------------------
+ */
+
+// USBDevice class instance
+USBDeviceClass USBDevice;
+ 1a22: 4770 bx lr
+ 1a24: 41005000 .word 0x41005000
+ 1a28: 200005f4 .word 0x200005f4
+
+00001a2c <init>:
+ * - During reset, all PORT lines are configured as inputs with input buffers, output buffers and pull disabled.
+ */
+void init( void )
+{
+ // Set Systick to 1ms interval, common to all Cortex-M variants
+ if ( SysTick_Config( SystemCoreClock / 1000 ) )
+ 1a2c: 21fa movs r1, #250 ; 0xfa
+ 1a2e: 4b31 ldr r3, [pc, #196] ; (1af4 <init+0xc8>)
+{
+ 1a30: b510 push {r4, lr}
+ if ( SysTick_Config( SystemCoreClock / 1000 ) )
+ 1a32: 6818 ldr r0, [r3, #0]
+ 1a34: 0089 lsls r1, r1, #2
+ 1a36: f000 fe2b bl 2690 <__udivsi3>
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ 1a3a: 4b2f ldr r3, [pc, #188] ; (1af8 <init+0xcc>)
+ 1a3c: 3801 subs r0, #1
+ 1a3e: 4298 cmp r0, r3
+ 1a40: d856 bhi.n 1af0 <init+0xc4>
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ 1a42: 492e ldr r1, [pc, #184] ; (1afc <init+0xd0>)
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ 1a44: 4a2e ldr r2, [pc, #184] ; (1b00 <init+0xd4>)
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ 1a46: 6048 str r0, [r1, #4]
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ 1a48: 20c0 movs r0, #192 ; 0xc0
+ 1a4a: 6a13 ldr r3, [r2, #32]
+ 1a4c: 0600 lsls r0, r0, #24
+ 1a4e: 021b lsls r3, r3, #8
+ 1a50: 0a1b lsrs r3, r3, #8
+ 1a52: 4303 orrs r3, r0
+ 1a54: 6213 str r3, [r2, #32]
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ 1a56: 2400 movs r4, #0
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ 1a58: 2307 movs r3, #7
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ 1a5a: 608c str r4, [r1, #8]
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ 1a5c: 600b str r3, [r1, #0]
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ 1a5e: 2180 movs r1, #128 ; 0x80
+ 1a60: 6a13 ldr r3, [r2, #32]
+ 1a62: 0609 lsls r1, r1, #24
+ 1a64: 021b lsls r3, r3, #8
+ 1a66: 0a1b lsrs r3, r3, #8
+ 1a68: 430b orrs r3, r1
+ 1a6a: 6213 str r3, [r2, #32]
+//
+// // Clock EIC for I/O interrupts
+// PM->APBAMASK.reg |= PM_APBAMASK_EIC ;
+
+ // Clock SERCOM for Serial
+ PM->APBCMASK.reg |= PM_APBCMASK_SERCOM0 | PM_APBCMASK_SERCOM1 | PM_APBCMASK_SERCOM2 | PM_APBCMASK_SERCOM3 | PM_APBCMASK_SERCOM4 | PM_APBCMASK_SERCOM5 ;
+ 1a6c: 22fc movs r2, #252 ; 0xfc
+ 1a6e: 4b25 ldr r3, [pc, #148] ; (1b04 <init+0xd8>)
+ 1a70: 6a19 ldr r1, [r3, #32]
+ 1a72: 430a orrs r2, r1
+ 1a74: 621a str r2, [r3, #32]
+
+ // Clock TC/TCC for Pulse and Analog
+ PM->APBCMASK.reg |= PM_APBCMASK_TCC0 | PM_APBCMASK_TCC1 | PM_APBCMASK_TCC2 | PM_APBCMASK_TC3 | PM_APBCMASK_TC4 | PM_APBCMASK_TC5 ;
+ 1a76: 22fc movs r2, #252 ; 0xfc
+ 1a78: 6a19 ldr r1, [r3, #32]
+ 1a7a: 0192 lsls r2, r2, #6
+ 1a7c: 430a orrs r2, r1
+ 1a7e: 621a str r2, [r3, #32]
+
+ // Clock ADC/DAC for Analog
+ PM->APBCMASK.reg |= PM_APBCMASK_ADC | PM_APBCMASK_DAC ;
+ 1a80: 22a0 movs r2, #160 ; 0xa0
+ 1a82: 6a19 ldr r1, [r3, #32]
+ 1a84: 02d2 lsls r2, r2, #11
+ 1a86: 430a orrs r2, r1
+ 1a88: 621a str r2, [r3, #32]
+// However, it really lowers the power consumption by a factor of 20 in low power mode (0.03mA vs 0.6mA)
+#ifndef VERY_LOW_POWER
+ // Setup all pins (digital and analog) in INPUT mode (default is nothing)
+ for (uint32_t ul = 0 ; ul < NUM_DIGITAL_PINS ; ul++ )
+ {
+ pinMode( ul, INPUT ) ;
+ 1a8a: 0020 movs r0, r4
+ 1a8c: 2100 movs r1, #0
+ for (uint32_t ul = 0 ; ul < NUM_DIGITAL_PINS ; ul++ )
+ 1a8e: 3401 adds r4, #1
+ pinMode( ul, INPUT ) ;
+ 1a90: f000 f976 bl 1d80 <pinMode>
+ for (uint32_t ul = 0 ; ul < NUM_DIGITAL_PINS ; ul++ )
+ 1a94: 2c14 cmp r4, #20
+ 1a96: d1f8 bne.n 1a8a <init+0x5e>
+ }
+#endif
+
+ // Initialize Analog Controller
+ // Setting clock
+ while(GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY);
+ 1a98: 4b1b ldr r3, [pc, #108] ; (1b08 <init+0xdc>)
+ 1a9a: 001c movs r4, r3
+ 1a9c: 785a ldrb r2, [r3, #1]
+ 1a9e: b252 sxtb r2, r2
+ 1aa0: 2a00 cmp r2, #0
+ 1aa2: dbfb blt.n 1a9c <init+0x70>
+
+ GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID( GCM_ADC ) | // Generic Clock ADC
+ 1aa4: 4a19 ldr r2, [pc, #100] ; (1b0c <init+0xe0>)
+ 1aa6: 805a strh r2, [r3, #2]
+ GCLK_CLKCTRL_GEN_GCLK0 | // Generic Clock Generator 0 is source
+ GCLK_CLKCTRL_CLKEN ;
+
+ while( ADC->STATUS.bit.SYNCBUSY == 1 ); // Wait for synchronization of registers between the clock domains
+ 1aa8: 4b19 ldr r3, [pc, #100] ; (1b10 <init+0xe4>)
+ 1aaa: 001a movs r2, r3
+ 1aac: 7e59 ldrb r1, [r3, #25]
+ 1aae: 09c9 lsrs r1, r1, #7
+ 1ab0: 2901 cmp r1, #1
+ 1ab2: d0fb beq.n 1aac <init+0x80>
+
+ ADC->CTRLB.reg = ADC_CTRLB_PRESCALER_DIV512 | // Divide Clock by 512.
+ 1ab4: 21e4 movs r1, #228 ; 0xe4
+ 1ab6: 00c9 lsls r1, r1, #3
+ 1ab8: 8099 strh r1, [r3, #4]
+ ADC_CTRLB_RESSEL_10BIT; // 10 bits resolution as default
+
+ ADC->SAMPCTRL.reg = 0x3f; // Set max Sampling Time Length
+ 1aba: 213f movs r1, #63 ; 0x3f
+ 1abc: 70d9 strb r1, [r3, #3]
+
+ while( ADC->STATUS.bit.SYNCBUSY == 1 ); // Wait for synchronization of registers between the clock domains
+ 1abe: 7e53 ldrb r3, [r2, #25]
+ 1ac0: 09db lsrs r3, r3, #7
+ 1ac2: 2b01 cmp r3, #1
+ 1ac4: d0fb beq.n 1abe <init+0x92>
+
+ ADC->INPUTCTRL.reg = ADC_INPUTCTRL_MUXNEG_GND; // No Negative input (Internal Ground)
+ 1ac6: 23c0 movs r3, #192 ; 0xc0
+
+ // Averaging (see datasheet table in AVGCTRL register description)
+ ADC->AVGCTRL.reg = ADC_AVGCTRL_SAMPLENUM_1 | // 1 sample only (no oversampling nor averaging)
+ 1ac8: 2000 movs r0, #0
+ ADC->INPUTCTRL.reg = ADC_INPUTCTRL_MUXNEG_GND; // No Negative input (Internal Ground)
+ 1aca: 015b lsls r3, r3, #5
+ 1acc: 6113 str r3, [r2, #16]
+ ADC->AVGCTRL.reg = ADC_AVGCTRL_SAMPLENUM_1 | // 1 sample only (no oversampling nor averaging)
+ 1ace: 7090 strb r0, [r2, #2]
+ ADC_AVGCTRL_ADJRES(0x0ul); // Adjusting result by 0
+
+ analogReference( AR_DEFAULT ) ; // Analog Reference is AREF pin (3.3v)
+ 1ad0: f000 f834 bl 1b3c <analogReference>
+
+ // Initialize DAC
+ // Setting clock
+ while ( GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY );
+ 1ad4: 7863 ldrb r3, [r4, #1]
+ 1ad6: b25b sxtb r3, r3
+ 1ad8: 2b00 cmp r3, #0
+ 1ada: dbfb blt.n 1ad4 <init+0xa8>
+ GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID( GCM_DAC ) | // Generic Clock ADC
+ 1adc: 4b0d ldr r3, [pc, #52] ; (1b14 <init+0xe8>)
+ GCLK_CLKCTRL_GEN_GCLK0 | // Generic Clock Generator 0 is source
+ GCLK_CLKCTRL_CLKEN ;
+
+ while ( DAC->STATUS.bit.SYNCBUSY == 1 ); // Wait for synchronization of registers between the clock domains
+ 1ade: 4a0e ldr r2, [pc, #56] ; (1b18 <init+0xec>)
+ GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID( GCM_DAC ) | // Generic Clock ADC
+ 1ae0: 8063 strh r3, [r4, #2]
+ while ( DAC->STATUS.bit.SYNCBUSY == 1 ); // Wait for synchronization of registers between the clock domains
+ 1ae2: 79d3 ldrb r3, [r2, #7]
+ 1ae4: 09db lsrs r3, r3, #7
+ 1ae6: 2b01 cmp r3, #1
+ 1ae8: d0fb beq.n 1ae2 <init+0xb6>
+ DAC->CTRLB.reg = DAC_CTRLB_REFSEL_AVCC | // Using the 3.3V reference
+ 1aea: 2341 movs r3, #65 ; 0x41
+ 1aec: 7053 strb r3, [r2, #1]
+ DAC_CTRLB_EOEN ; // External Output Enable (Vout)
+}
+ 1aee: bd10 pop {r4, pc}
+ 1af0: e7fe b.n 1af0 <init+0xc4>
+ 1af2: 46c0 nop ; (mov r8, r8)
+ 1af4: 20000014 .word 0x20000014
+ 1af8: 00ffffff .word 0x00ffffff
+ 1afc: e000e010 .word 0xe000e010
+ 1b00: e000ed00 .word 0xe000ed00
+ 1b04: 40000400 .word 0x40000400
+ 1b08: 40000c00 .word 0x40000c00
+ 1b0c: 0000401e .word 0x0000401e
+ 1b10: 42004000 .word 0x42004000
+ 1b14: 00004021 .word 0x00004021
+ 1b18: 42004800 .word 0x42004800
+
+00001b1c <mapResolution>:
+ _writeResolution = res;
+}
+
+static inline uint32_t mapResolution(uint32_t value, uint32_t from, uint32_t to)
+{
+ if (from == to) {
+ 1b1c: 4291 cmp r1, r2
+ 1b1e: d002 beq.n 1b26 <mapResolution+0xa>
+ return value;
+ }
+ if (from > to) {
+ 1b20: d902 bls.n 1b28 <mapResolution+0xc>
+ return value >> (from-to);
+ 1b22: 1a8a subs r2, r1, r2
+ 1b24: 40d0 lsrs r0, r2
+ }
+ return value << (to-from);
+}
+ 1b26: 4770 bx lr
+ return value << (to-from);
+ 1b28: 1a52 subs r2, r2, r1
+ 1b2a: 4090 lsls r0, r2
+ 1b2c: e7fb b.n 1b26 <mapResolution+0xa>
+ ...
+
+00001b30 <analogWriteResolution>:
+ _writeResolution = res;
+ 1b30: 4b01 ldr r3, [pc, #4] ; (1b38 <analogWriteResolution+0x8>)
+ 1b32: 6018 str r0, [r3, #0]
+}
+ 1b34: 4770 bx lr
+ 1b36: 46c0 nop ; (mov r8, r8)
+ 1b38: 20000018 .word 0x20000018
+
+00001b3c <analogReference>:
+ while (ADC->STATUS.bit.SYNCBUSY == 1)
+ 1b3c: 4a16 ldr r2, [pc, #88] ; (1b98 <analogReference+0x5c>)
+ * External Reference should be between 1v and VDDANA-0.6v=2.7v
+ *
+ * Warning : On Arduino Zero board the input/output voltage for SAMD21G18 is 3.3 volts maximum
+ */
+void analogReference(eAnalogReference mode)
+{
+ 1b3e: b500 push {lr}
+ 1b40: 0013 movs r3, r2
+ while (ADC->STATUS.bit.SYNCBUSY == 1)
+ 1b42: 7e51 ldrb r1, [r2, #25]
+ 1b44: 09c9 lsrs r1, r1, #7
+ 1b46: 2901 cmp r1, #1
+ 1b48: d0fb beq.n 1b42 <analogReference+0x6>
+ syncADC();
+ switch (mode)
+ 1b4a: 3801 subs r0, #1
+ 1b4c: 2804 cmp r0, #4
+ 1b4e: d816 bhi.n 1b7e <analogReference+0x42>
+ ADC->INPUTCTRL.bit.GAIN = ADC_INPUTCTRL_GAIN_1X_Val; // Gain Factor Selection
+ ADC->REFCTRL.bit.REFSEL = ADC_REFCTRL_REFSEL_INT1V_Val; // 1.0V voltage reference
+ break;
+
+ case AR_INTERNAL1V65:
+ ADC->INPUTCTRL.bit.GAIN = ADC_INPUTCTRL_GAIN_1X_Val; // Gain Factor Selection
+ 1b50: 6919 ldr r1, [r3, #16]
+ 1b52: 4a12 ldr r2, [pc, #72] ; (1b9c <analogReference+0x60>)
+ 1b54: 400a ands r2, r1
+ ADC->REFCTRL.bit.REFSEL = ADC_REFCTRL_REFSEL_INTVCC1_Val; // 1/2 VDDANA = 0.5* 3V3 = 1.65V
+ 1b56: 210f movs r1, #15
+ ADC->INPUTCTRL.bit.GAIN = ADC_INPUTCTRL_GAIN_1X_Val; // Gain Factor Selection
+ 1b58: 611a str r2, [r3, #16]
+ ADC->REFCTRL.bit.REFSEL = ADC_REFCTRL_REFSEL_INTVCC1_Val; // 1/2 VDDANA = 0.5* 3V3 = 1.65V
+ 1b5a: 785a ldrb r2, [r3, #1]
+ 1b5c: 438a bics r2, r1
+ switch (mode)
+ 1b5e: f000 fd8d bl 267c <__gnu_thumb1_case_uqi>
+ 1b62: 0803 .short 0x0803
+ 1b64: 0b06 .short 0x0b06
+ 1b66: 03 .byte 0x03
+ 1b67: 00 .byte 0x00
+ ADC->REFCTRL.bit.REFSEL = ADC_REFCTRL_REFSEL_INTVCC0_Val; // 1/1.48 VDDANA = 1/1.48* 3V3 = 2.2297
+ 1b68: 0011 movs r1, r2
+ 1b6a: 2201 movs r2, #1
+ ADC->REFCTRL.bit.REFSEL = ADC_REFCTRL_REFSEL_INTVCC1_Val; // 1/2 VDDANA = 0.5* 3V3 = 1.65V
+ 1b6c: 430a orrs r2, r1
+ 1b6e: 705a strb r2, [r3, #1]
+ default:
+ ADC->INPUTCTRL.bit.GAIN = ADC_INPUTCTRL_GAIN_DIV2_Val;
+ ADC->REFCTRL.bit.REFSEL = ADC_REFCTRL_REFSEL_INTVCC1_Val; // 1/2 VDDANA = 0.5* 3V3 = 1.65V
+ break;
+ }
+}
+ 1b70: bd00 pop {pc}
+ ADC->REFCTRL.bit.REFSEL = ADC_REFCTRL_REFSEL_AREFA_Val;
+ 1b72: 0011 movs r1, r2
+ 1b74: 2203 movs r2, #3
+ 1b76: e7f9 b.n 1b6c <analogReference+0x30>
+ ADC->REFCTRL.bit.REFSEL = ADC_REFCTRL_REFSEL_INTVCC1_Val; // 1/2 VDDANA = 0.5* 3V3 = 1.65V
+ 1b78: 0011 movs r1, r2
+ 1b7a: 2202 movs r2, #2
+ 1b7c: e7f6 b.n 1b6c <analogReference+0x30>
+ ADC->INPUTCTRL.bit.GAIN = ADC_INPUTCTRL_GAIN_DIV2_Val;
+ 1b7e: 23f0 movs r3, #240 ; 0xf0
+ 1b80: 6911 ldr r1, [r2, #16]
+ 1b82: 051b lsls r3, r3, #20
+ 1b84: 430b orrs r3, r1
+ ADC->REFCTRL.bit.REFSEL = ADC_REFCTRL_REFSEL_INTVCC1_Val; // 1/2 VDDANA = 0.5* 3V3 = 1.65V
+ 1b86: 210f movs r1, #15
+ ADC->INPUTCTRL.bit.GAIN = ADC_INPUTCTRL_GAIN_DIV2_Val;
+ 1b88: 6113 str r3, [r2, #16]
+ ADC->REFCTRL.bit.REFSEL = ADC_REFCTRL_REFSEL_INTVCC1_Val; // 1/2 VDDANA = 0.5* 3V3 = 1.65V
+ 1b8a: 7853 ldrb r3, [r2, #1]
+ 1b8c: 438b bics r3, r1
+ 1b8e: 0019 movs r1, r3
+ 1b90: 2302 movs r3, #2
+ 1b92: 430b orrs r3, r1
+ 1b94: 7053 strb r3, [r2, #1]
+}
+ 1b96: e7eb b.n 1b70 <analogReference+0x34>
+ 1b98: 42004000 .word 0x42004000
+ 1b9c: f0ffffff .word 0xf0ffffff
+
+00001ba0 <analogWrite>:
+// hardware support. These are defined in the appropriate
+// pins_*.c file. For the rest of the pins, we default
+// to digital output.
+void analogWrite(uint32_t pin, uint32_t value)
+{
+ PinDescription pinDesc = g_APinDescription[pin];
+ 1ba0: 2318 movs r3, #24
+ 1ba2: 4343 muls r3, r0
+{
+ 1ba4: b5f0 push {r4, r5, r6, r7, lr}
+ PinDescription pinDesc = g_APinDescription[pin];
+ 1ba6: 4a6d ldr r2, [pc, #436] ; (1d5c <analogWrite+0x1bc>)
+{
+ 1ba8: b087 sub sp, #28
+ PinDescription pinDesc = g_APinDescription[pin];
+ 1baa: 189b adds r3, r3, r2
+ 1bac: 68da ldr r2, [r3, #12]
+{
+ 1bae: 0007 movs r7, r0
+ 1bb0: 000c movs r4, r1
+ PinDescription pinDesc = g_APinDescription[pin];
+ 1bb2: 9200 str r2, [sp, #0]
+ uint32_t attr = pinDesc.ulPinAttribute;
+
+ if ((attr & PIN_ATTR_ANALOG) == PIN_ATTR_ANALOG)
+ 1bb4: 0792 lsls r2, r2, #30
+ 1bb6: d522 bpl.n 1bfe <analogWrite+0x5e>
+ PinDescription pinDesc = g_APinDescription[pin];
+ 1bb8: 7c1b ldrb r3, [r3, #16]
+ 1bba: b25b sxtb r3, r3
+ {
+ // DAC handling code
+
+ if ((pinDesc.ulADCChannelNumber != ADC_Channel0) && (pinDesc.ulADCChannelNumber != DAC_Channel0)) { // Only 1 DAC on AIN0 / PA02
+ 1bbc: 2b00 cmp r3, #0
+ 1bbe: d001 beq.n 1bc4 <analogWrite+0x24>
+ 1bc0: 2b14 cmp r3, #20
+ 1bc2: d11a bne.n 1bfa <analogWrite+0x5a>
+ return;
+ }
+
+ value = mapResolution(value, _writeResolution, 10);
+ 1bc4: 4b66 ldr r3, [pc, #408] ; (1d60 <analogWrite+0x1c0>)
+ 1bc6: 220a movs r2, #10
+ 1bc8: 6819 ldr r1, [r3, #0]
+ 1bca: 0020 movs r0, r4
+ 1bcc: f7ff ffa6 bl 1b1c <mapResolution>
+ while (DAC->STATUS.bit.SYNCBUSY == 1)
+ 1bd0: 4a64 ldr r2, [pc, #400] ; (1d64 <analogWrite+0x1c4>)
+ 1bd2: 0013 movs r3, r2
+ 1bd4: 79d1 ldrb r1, [r2, #7]
+ 1bd6: 09c9 lsrs r1, r1, #7
+ 1bd8: 2901 cmp r1, #1
+ 1bda: d0fb beq.n 1bd4 <analogWrite+0x34>
+
+ syncDAC();
+ DAC->DATA.reg = value & 0x3FF; // DAC on 10 bits.
+ 1bdc: 0580 lsls r0, r0, #22
+ 1bde: 0d80 lsrs r0, r0, #22
+ 1be0: 8110 strh r0, [r2, #8]
+ while (DAC->STATUS.bit.SYNCBUSY == 1)
+ 1be2: 79da ldrb r2, [r3, #7]
+ 1be4: 09d2 lsrs r2, r2, #7
+ 1be6: 2a01 cmp r2, #1
+ 1be8: d0fb beq.n 1be2 <analogWrite+0x42>
+ syncDAC();
+ DAC->CTRLA.bit.ENABLE = 0x01; // Enable DAC
+ 1bea: 2202 movs r2, #2
+ 1bec: 7819 ldrb r1, [r3, #0]
+ 1bee: 430a orrs r2, r1
+ 1bf0: 701a strb r2, [r3, #0]
+ while (DAC->STATUS.bit.SYNCBUSY == 1)
+ 1bf2: 79da ldrb r2, [r3, #7]
+ 1bf4: 09d2 lsrs r2, r2, #7
+ 1bf6: 2a01 cmp r2, #1
+ 1bf8: d0fb beq.n 1bf2 <analogWrite+0x52>
+ if (value < 128) {
+ digitalWrite(pin, LOW);
+ } else {
+ digitalWrite(pin, HIGH);
+ }
+}
+ 1bfa: b007 add sp, #28
+ 1bfc: bdf0 pop {r4, r5, r6, r7, pc}
+ if ((attr & PIN_ATTR_PWM) == PIN_ATTR_PWM)
+ 1bfe: 2608 movs r6, #8
+ 1c00: 9a00 ldr r2, [sp, #0]
+ 1c02: 4d57 ldr r5, [pc, #348] ; (1d60 <analogWrite+0x1c0>)
+ 1c04: 4032 ands r2, r6
+ 1c06: 9201 str r2, [sp, #4]
+ 1c08: d100 bne.n 1c0c <analogWrite+0x6c>
+ 1c0a: e096 b.n 1d3a <analogWrite+0x19a>
+ PinDescription pinDesc = g_APinDescription[pin];
+ 1c0c: 2212 movs r2, #18
+ 1c0e: 5e9b ldrsh r3, [r3, r2]
+ value = mapResolution(value, _writeResolution, 16);
+ 1c10: 6829 ldr r1, [r5, #0]
+ 1c12: 0020 movs r0, r4
+ 1c14: 2210 movs r2, #16
+ PinDescription pinDesc = g_APinDescription[pin];
+ 1c16: 9301 str r3, [sp, #4]
+ value = mapResolution(value, _writeResolution, 16);
+ 1c18: f7ff ff80 bl 1b1c <mapResolution>
+ uint32_t tcNum = GetTCNumber(pinDesc.ulPWMChannel);
+ 1c1c: 9b01 ldr r3, [sp, #4]
+ value = mapResolution(value, _writeResolution, 16);
+ 1c1e: 0005 movs r5, r0
+ uint32_t tcNum = GetTCNumber(pinDesc.ulPWMChannel);
+ 1c20: 121e asrs r6, r3, #8
+ uint8_t tcChannel = GetTCChannelNumber(pinDesc.ulPWMChannel);
+ 1c22: 466b mov r3, sp
+ 1c24: 791c ldrb r4, [r3, #4]
+ if (attr & PIN_ATTR_TIMER) {
+ 1c26: 9b00 ldr r3, [sp, #0]
+ pinPeripheral(pin, PIO_TIMER);
+ 1c28: 2104 movs r1, #4
+ if (attr & PIN_ATTR_TIMER) {
+ 1c2a: 06db lsls r3, r3, #27
+ 1c2c: d400 bmi.n 1c30 <analogWrite+0x90>
+ pinPeripheral(pin, PIO_TIMER_ALT);
+ 1c2e: 2105 movs r1, #5
+ 1c30: 0038 movs r0, r7
+ 1c32: f000 f91d bl 1e70 <pinPeripheral>
+ if (!tcEnabled[tcNum]) {
+ 1c36: 4b4c ldr r3, [pc, #304] ; (1d68 <analogWrite+0x1c8>)
+ 1c38: 5d9a ldrb r2, [r3, r6]
+ 1c3a: 2a00 cmp r2, #0
+ 1c3c: d158 bne.n 1cf0 <analogWrite+0x150>
+ tcEnabled[tcNum] = true;
+ 1c3e: 3201 adds r2, #1
+ 1c40: 559a strb r2, [r3, r6]
+ uint16_t GCLK_CLKCTRL_IDs[] = {
+ 1c42: 494a ldr r1, [pc, #296] ; (1d6c <analogWrite+0x1cc>)
+ 1c44: 320f adds r2, #15
+ 1c46: a802 add r0, sp, #8
+ 1c48: f000 fde6 bl 2818 <memcpy>
+ GCLK->CLKCTRL.reg = (uint16_t) (GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN_GCLK0 | GCLK_CLKCTRL_IDs[tcNum]);
+ 1c4c: aa02 add r2, sp, #8
+ 1c4e: 0073 lsls r3, r6, #1
+ 1c50: 5a9b ldrh r3, [r3, r2]
+ 1c52: 2280 movs r2, #128 ; 0x80
+ 1c54: 01d2 lsls r2, r2, #7
+ 1c56: 431a orrs r2, r3
+ 1c58: 4b45 ldr r3, [pc, #276] ; (1d70 <analogWrite+0x1d0>)
+ 1c5a: 805a strh r2, [r3, #2]
+ while (GCLK->STATUS.bit.SYNCBUSY == 1);
+ 1c5c: 785a ldrb r2, [r3, #1]
+ 1c5e: 09d2 lsrs r2, r2, #7
+ 1c60: 2a01 cmp r2, #1
+ 1c62: d0fb beq.n 1c5c <analogWrite+0xbc>
+ 1c64: 4a43 ldr r2, [pc, #268] ; (1d74 <analogWrite+0x1d4>)
+ 1c66: 00b3 lsls r3, r6, #2
+ Tc* TCx = (Tc*) GetTC(pinDesc.ulPWMChannel);
+ 1c68: 58d3 ldr r3, [r2, r3]
+ if (tcNum >= TCC_INST_NUM) {
+ 1c6a: 2e02 cmp r6, #2
+ 1c6c: d91c bls.n 1ca8 <analogWrite+0x108>
+ TCx->COUNT16.CTRLA.bit.ENABLE = 0;
+ 1c6e: 2102 movs r1, #2
+ 1c70: 881a ldrh r2, [r3, #0]
+ 1c72: 438a bics r2, r1
+ 1c74: 801a strh r2, [r3, #0]
+ while (TCx->COUNT16.STATUS.bit.SYNCBUSY);
+ 1c76: 7bda ldrb r2, [r3, #15]
+ 1c78: 09d2 lsrs r2, r2, #7
+ 1c7a: d1fc bne.n 1c76 <analogWrite+0xd6>
+ TCx->COUNT16.CTRLA.reg |= TC_CTRLA_MODE_COUNT16 | TC_CTRLA_WAVEGEN_NPWM;
+ 1c7c: 8819 ldrh r1, [r3, #0]
+ 1c7e: 3240 adds r2, #64 ; 0x40
+ 1c80: 430a orrs r2, r1
+ 1c82: 801a strh r2, [r3, #0]
+ while (TCx->COUNT16.STATUS.bit.SYNCBUSY);
+ 1c84: 7bda ldrb r2, [r3, #15]
+ 1c86: 09d2 lsrs r2, r2, #7
+ 1c88: d1fc bne.n 1c84 <analogWrite+0xe4>
+ TCx->COUNT16.CC[tcChannel].reg = (uint32_t) value;
+ 1c8a: 340c adds r4, #12
+ 1c8c: b2ad uxth r5, r5
+ 1c8e: 0064 lsls r4, r4, #1
+ 1c90: 52e5 strh r5, [r4, r3]
+ while (TCx->COUNT16.STATUS.bit.SYNCBUSY);
+ 1c92: 7bda ldrb r2, [r3, #15]
+ 1c94: 09d2 lsrs r2, r2, #7
+ 1c96: d1fc bne.n 1c92 <analogWrite+0xf2>
+ TCx->COUNT16.CTRLA.bit.ENABLE = 1;
+ 1c98: 8819 ldrh r1, [r3, #0]
+ 1c9a: 3202 adds r2, #2
+ 1c9c: 430a orrs r2, r1
+ 1c9e: 801a strh r2, [r3, #0]
+ while (TCx->COUNT16.STATUS.bit.SYNCBUSY);
+ 1ca0: 7bda ldrb r2, [r3, #15]
+ 1ca2: 09d2 lsrs r2, r2, #7
+ 1ca4: d1fc bne.n 1ca0 <analogWrite+0x100>
+ 1ca6: e7a8 b.n 1bfa <analogWrite+0x5a>
+ TCCx->CTRLA.bit.ENABLE = 0;
+ 1ca8: 2102 movs r1, #2
+ 1caa: 681a ldr r2, [r3, #0]
+ 1cac: 438a bics r2, r1
+ while (TCCx->SYNCBUSY.reg & TCC_SYNCBUSY_MASK);
+ 1cae: 4932 ldr r1, [pc, #200] ; (1d78 <analogWrite+0x1d8>)
+ TCCx->CTRLA.bit.ENABLE = 0;
+ 1cb0: 601a str r2, [r3, #0]
+ 1cb2: 000a movs r2, r1
+ while (TCCx->SYNCBUSY.reg & TCC_SYNCBUSY_MASK);
+ 1cb4: 6898 ldr r0, [r3, #8]
+ 1cb6: 4208 tst r0, r1
+ 1cb8: d1fc bne.n 1cb4 <analogWrite+0x114>
+ TCCx->WAVE.reg |= TCC_WAVE_WAVEGEN_NPWM;
+ 1cba: 2102 movs r1, #2
+ 1cbc: 6bd8 ldr r0, [r3, #60] ; 0x3c
+ 1cbe: 4301 orrs r1, r0
+ 1cc0: 63d9 str r1, [r3, #60] ; 0x3c
+ while (TCCx->SYNCBUSY.reg & TCC_SYNCBUSY_MASK);
+ 1cc2: 6899 ldr r1, [r3, #8]
+ 1cc4: 4211 tst r1, r2
+ 1cc6: d1fc bne.n 1cc2 <analogWrite+0x122>
+ TCCx->CC[tcChannel].reg = (uint32_t) value;
+ 1cc8: 3410 adds r4, #16
+ 1cca: 00a4 lsls r4, r4, #2
+ 1ccc: 191c adds r4, r3, r4
+ 1cce: 6065 str r5, [r4, #4]
+ while (TCCx->SYNCBUSY.reg & TCC_SYNCBUSY_MASK);
+ 1cd0: 6899 ldr r1, [r3, #8]
+ 1cd2: 4211 tst r1, r2
+ 1cd4: d1fc bne.n 1cd0 <analogWrite+0x130>
+ TCCx->PER.reg = 0xFFFF;
+ 1cd6: 4929 ldr r1, [pc, #164] ; (1d7c <analogWrite+0x1dc>)
+ 1cd8: 6419 str r1, [r3, #64] ; 0x40
+ while (TCCx->SYNCBUSY.reg & TCC_SYNCBUSY_MASK);
+ 1cda: 6899 ldr r1, [r3, #8]
+ 1cdc: 4211 tst r1, r2
+ 1cde: d1fc bne.n 1cda <analogWrite+0x13a>
+ TCCx->CTRLA.bit.ENABLE = 1;
+ 1ce0: 2102 movs r1, #2
+ 1ce2: 6818 ldr r0, [r3, #0]
+ 1ce4: 4301 orrs r1, r0
+ 1ce6: 6019 str r1, [r3, #0]
+ while (TCCx->SYNCBUSY.reg & TCC_SYNCBUSY_MASK);
+ 1ce8: 6899 ldr r1, [r3, #8]
+ 1cea: 4211 tst r1, r2
+ 1cec: d1fc bne.n 1ce8 <analogWrite+0x148>
+ 1cee: e784 b.n 1bfa <analogWrite+0x5a>
+ 1cf0: 4a20 ldr r2, [pc, #128] ; (1d74 <analogWrite+0x1d4>)
+ 1cf2: 00b3 lsls r3, r6, #2
+ if (tcNum >= TCC_INST_NUM) {
+ 1cf4: 2e02 cmp r6, #2
+ 1cf6: d908 bls.n 1d0a <analogWrite+0x16a>
+ Tc* TCx = (Tc*) GetTC(pinDesc.ulPWMChannel);
+ 1cf8: 58d2 ldr r2, [r2, r3]
+ TCx->COUNT16.CC[tcChannel].reg = (uint32_t) value;
+ 1cfa: 340c adds r4, #12
+ 1cfc: b2ad uxth r5, r5
+ 1cfe: 0064 lsls r4, r4, #1
+ 1d00: 52a5 strh r5, [r4, r2]
+ while (TCx->COUNT16.STATUS.bit.SYNCBUSY);
+ 1d02: 7bd3 ldrb r3, [r2, #15]
+ 1d04: 09db lsrs r3, r3, #7
+ 1d06: d1fc bne.n 1d02 <analogWrite+0x162>
+ 1d08: e777 b.n 1bfa <analogWrite+0x5a>
+ Tcc* TCCx = (Tcc*) GetTC(pinDesc.ulPWMChannel);
+ 1d0a: 58d3 ldr r3, [r2, r3]
+ TCCx->CTRLBSET.bit.LUPD = 1;
+ 1d0c: 2202 movs r2, #2
+ 1d0e: 7959 ldrb r1, [r3, #5]
+ 1d10: 430a orrs r2, r1
+ 1d12: 715a strb r2, [r3, #5]
+ while (TCCx->SYNCBUSY.reg & TCC_SYNCBUSY_MASK);
+ 1d14: 4a18 ldr r2, [pc, #96] ; (1d78 <analogWrite+0x1d8>)
+ 1d16: 0011 movs r1, r2
+ 1d18: 6898 ldr r0, [r3, #8]
+ 1d1a: 4210 tst r0, r2
+ 1d1c: d1fc bne.n 1d18 <analogWrite+0x178>
+ TCCx->CCB[tcChannel].reg = (uint32_t) value;
+ 1d1e: 341c adds r4, #28
+ 1d20: 00a4 lsls r4, r4, #2
+ 1d22: 50e5 str r5, [r4, r3]
+ while (TCCx->SYNCBUSY.reg & TCC_SYNCBUSY_MASK);
+ 1d24: 689a ldr r2, [r3, #8]
+ 1d26: 420a tst r2, r1
+ 1d28: d1fc bne.n 1d24 <analogWrite+0x184>
+ TCCx->CTRLBCLR.bit.LUPD = 1;
+ 1d2a: 2202 movs r2, #2
+ 1d2c: 7918 ldrb r0, [r3, #4]
+ 1d2e: 4302 orrs r2, r0
+ 1d30: 711a strb r2, [r3, #4]
+ while (TCCx->SYNCBUSY.reg & TCC_SYNCBUSY_MASK);
+ 1d32: 689a ldr r2, [r3, #8]
+ 1d34: 420a tst r2, r1
+ 1d36: d1fc bne.n 1d32 <analogWrite+0x192>
+ 1d38: e75f b.n 1bfa <analogWrite+0x5a>
+ pinMode(pin, OUTPUT);
+ 1d3a: 2101 movs r1, #1
+ 1d3c: f000 f820 bl 1d80 <pinMode>
+ value = mapResolution(value, _writeResolution, 8);
+ 1d40: 6829 ldr r1, [r5, #0]
+ 1d42: 0032 movs r2, r6
+ 1d44: 0020 movs r0, r4
+ 1d46: f7ff fee9 bl 1b1c <mapResolution>
+ digitalWrite(pin, LOW);
+ 1d4a: 9901 ldr r1, [sp, #4]
+ if (value < 128) {
+ 1d4c: 287f cmp r0, #127 ; 0x7f
+ 1d4e: d900 bls.n 1d52 <analogWrite+0x1b2>
+ digitalWrite(pin, HIGH);
+ 1d50: 2101 movs r1, #1
+ 1d52: 0038 movs r0, r7
+ 1d54: f000 f860 bl 1e18 <digitalWrite>
+ 1d58: e74f b.n 1bfa <analogWrite+0x5a>
+ 1d5a: 46c0 nop ; (mov r8, r8)
+ 1d5c: 00002ab4 .word 0x00002ab4
+ 1d60: 20000018 .word 0x20000018
+ 1d64: 42004800 .word 0x42004800
+ 1d68: 200006f8 .word 0x200006f8
+ 1d6c: 00002aa2 .word 0x00002aa2
+ 1d70: 40000c00 .word 0x40000c00
+ 1d74: 2000001c .word 0x2000001c
+ 1d78: 007f0fff .word 0x007f0fff
+ 1d7c: 0000ffff .word 0x0000ffff
+
+00001d80 <pinMode>:
+#endif
+
+void pinMode( uint32_t ulPin, uint32_t ulMode )
+{
+ // Handle the case the pin isn't usable as PIO
+ if ( g_APinDescription[ulPin].ulPinType == PIO_NOT_A_PIN )
+ 1d80: 2318 movs r3, #24
+{
+ 1d82: b530 push {r4, r5, lr}
+ if ( g_APinDescription[ulPin].ulPinType == PIO_NOT_A_PIN )
+ 1d84: 001d movs r5, r3
+{
+ 1d86: 0004 movs r4, r0
+ if ( g_APinDescription[ulPin].ulPinType == PIO_NOT_A_PIN )
+ 1d88: 4345 muls r5, r0
+ 1d8a: 2008 movs r0, #8
+ 1d8c: 4a20 ldr r2, [pc, #128] ; (1e10 <pinMode+0x90>)
+ 1d8e: 1955 adds r5, r2, r5
+ 1d90: 5628 ldrsb r0, [r5, r0]
+ 1d92: 3001 adds r0, #1
+ 1d94: d014 beq.n 1dc0 <pinMode+0x40>
+ {
+ return ;
+ }
+
+ // Set pin mode according to chapter '22.6.3 I/O Pin Configuration'
+ switch ( ulMode )
+ 1d96: 2903 cmp r1, #3
+ 1d98: d812 bhi.n 1dc0 <pinMode+0x40>
+ 1d9a: 0008 movs r0, r1
+ PORT->Group[g_APinDescription[ulPin].ulPort].OUTSET.reg = (uint32_t)(1<<g_APinDescription[ulPin].ulPin) ;
+ break ;
+
+ case INPUT_PULLDOWN:
+ // Set pin to input mode with pull-down resistor enabled
+ PORT->Group[g_APinDescription[ulPin].ulPort].PINCFG[g_APinDescription[ulPin].ulPin].reg=(uint8_t)(PORT_PINCFG_INEN|PORT_PINCFG_PULLEN) ;
+ 1d9c: 4363 muls r3, r4
+ 1d9e: 56d1 ldrsb r1, [r2, r3]
+ 1da0: 18d3 adds r3, r2, r3
+ switch ( ulMode )
+ 1da2: f000 fc6b bl 267c <__gnu_thumb1_case_uqi>
+ 1da6: 2802 .short 0x2802
+ 1da8: 1b0e .short 0x1b0e
+ PORT->Group[g_APinDescription[ulPin].ulPort].PINCFG[g_APinDescription[ulPin].ulPin].reg=(uint8_t)(PORT_PINCFG_INEN) ;
+ 1daa: 6858 ldr r0, [r3, #4]
+ 1dac: 01cb lsls r3, r1, #7
+ 1dae: 2102 movs r1, #2
+ 1db0: 4a18 ldr r2, [pc, #96] ; (1e14 <pinMode+0x94>)
+ 1db2: 189b adds r3, r3, r2
+ 1db4: 181a adds r2, r3, r0
+ 1db6: 3240 adds r2, #64 ; 0x40
+ 1db8: 7011 strb r1, [r2, #0]
+ PORT->Group[g_APinDescription[ulPin].ulPort].DIRCLR.reg = (uint32_t)(1<<g_APinDescription[ulPin].ulPin) ;
+ 1dba: 2201 movs r2, #1
+ 1dbc: 4082 lsls r2, r0
+ 1dbe: 605a str r2, [r3, #4]
+
+ default:
+ // do nothing
+ break ;
+ }
+}
+ 1dc0: bd30 pop {r4, r5, pc}
+ PORT->Group[g_APinDescription[ulPin].ulPort].PINCFG[g_APinDescription[ulPin].ulPin].reg=(uint8_t)(PORT_PINCFG_INEN|PORT_PINCFG_PULLEN) ;
+ 1dc2: 6858 ldr r0, [r3, #4]
+ 1dc4: 01cb lsls r3, r1, #7
+ 1dc6: 2106 movs r1, #6
+ 1dc8: 4a12 ldr r2, [pc, #72] ; (1e14 <pinMode+0x94>)
+ 1dca: 189b adds r3, r3, r2
+ 1dcc: 181a adds r2, r3, r0
+ 1dce: 3240 adds r2, #64 ; 0x40
+ 1dd0: 7011 strb r1, [r2, #0]
+ PORT->Group[g_APinDescription[ulPin].ulPort].DIRCLR.reg = (uint32_t)(1<<g_APinDescription[ulPin].ulPin) ;
+ 1dd2: 2201 movs r2, #1
+ 1dd4: 4082 lsls r2, r0
+ 1dd6: 605a str r2, [r3, #4]
+ PORT->Group[g_APinDescription[ulPin].ulPort].OUTSET.reg = (uint32_t)(1<<g_APinDescription[ulPin].ulPin) ;
+ 1dd8: 619a str r2, [r3, #24]
+ break ;
+ 1dda: e7f1 b.n 1dc0 <pinMode+0x40>
+ PORT->Group[g_APinDescription[ulPin].ulPort].PINCFG[g_APinDescription[ulPin].ulPin].reg=(uint8_t)(PORT_PINCFG_INEN|PORT_PINCFG_PULLEN) ;
+ 1ddc: 6858 ldr r0, [r3, #4]
+ 1dde: 01cb lsls r3, r1, #7
+ 1de0: 2106 movs r1, #6
+ 1de2: 4a0c ldr r2, [pc, #48] ; (1e14 <pinMode+0x94>)
+ 1de4: 189b adds r3, r3, r2
+ 1de6: 181a adds r2, r3, r0
+ 1de8: 3240 adds r2, #64 ; 0x40
+ 1dea: 7011 strb r1, [r2, #0]
+ PORT->Group[g_APinDescription[ulPin].ulPort].DIRCLR.reg = (uint32_t)(1<<g_APinDescription[ulPin].ulPin) ;
+ 1dec: 2201 movs r2, #1
+ 1dee: 4082 lsls r2, r0
+ 1df0: 605a str r2, [r3, #4]
+ PORT->Group[g_APinDescription[ulPin].ulPort].OUTCLR.reg = (uint32_t)(1<<g_APinDescription[ulPin].ulPin) ;
+ 1df2: 615a str r2, [r3, #20]
+ break ;
+ 1df4: e7e4 b.n 1dc0 <pinMode+0x40>
+ PORT->Group[g_APinDescription[ulPin].ulPort].PINCFG[g_APinDescription[ulPin].ulPin].reg=(uint8_t)(PORT_PINCFG_INEN) ;
+ 1df6: 6858 ldr r0, [r3, #4]
+ 1df8: 01cb lsls r3, r1, #7
+ 1dfa: 2102 movs r1, #2
+ 1dfc: 4a05 ldr r2, [pc, #20] ; (1e14 <pinMode+0x94>)
+ 1dfe: 189b adds r3, r3, r2
+ 1e00: 181a adds r2, r3, r0
+ 1e02: 3240 adds r2, #64 ; 0x40
+ 1e04: 7011 strb r1, [r2, #0]
+ PORT->Group[g_APinDescription[ulPin].ulPort].DIRSET.reg = (uint32_t)(1<<g_APinDescription[ulPin].ulPin) ;
+ 1e06: 2201 movs r2, #1
+ 1e08: 4082 lsls r2, r0
+ 1e0a: 609a str r2, [r3, #8]
+ break ;
+ 1e0c: e7d8 b.n 1dc0 <pinMode+0x40>
+ 1e0e: 46c0 nop ; (mov r8, r8)
+ 1e10: 00002ab4 .word 0x00002ab4
+ 1e14: 41004400 .word 0x41004400
+
+00001e18 <digitalWrite>:
+
+void digitalWrite( uint32_t ulPin, uint32_t ulVal )
+{
+ // Handle the case the pin isn't usable as PIO
+ if ( g_APinDescription[ulPin].ulPinType == PIO_NOT_A_PIN )
+ 1e18: 2318 movs r3, #24
+{
+ 1e1a: b5f0 push {r4, r5, r6, r7, lr}
+ if ( g_APinDescription[ulPin].ulPinType == PIO_NOT_A_PIN )
+ 1e1c: 2408 movs r4, #8
+ 1e1e: 4358 muls r0, r3
+ 1e20: 4a11 ldr r2, [pc, #68] ; (1e68 <digitalWrite+0x50>)
+ 1e22: 1813 adds r3, r2, r0
+ 1e24: 571c ldrsb r4, [r3, r4]
+ 1e26: 3401 adds r4, #1
+ 1e28: d01b beq.n 1e62 <digitalWrite+0x4a>
+ return ;
+ }
+
+ EPortType port = g_APinDescription[ulPin].ulPort;
+ uint32_t pin = g_APinDescription[ulPin].ulPin;
+ uint32_t pinMask = (1ul << pin);
+ 1e2a: 2601 movs r6, #1
+ 1e2c: 0035 movs r5, r6
+ uint32_t pin = g_APinDescription[ulPin].ulPin;
+ 1e2e: 685f ldr r7, [r3, #4]
+
+ if ( (PORT->Group[port].DIRSET.reg & pinMask) == 0 ) {
+ 1e30: 5683 ldrsb r3, [r0, r2]
+ uint32_t pinMask = (1ul << pin);
+ 1e32: 40bd lsls r5, r7
+ if ( (PORT->Group[port].DIRSET.reg & pinMask) == 0 ) {
+ 1e34: 4a0d ldr r2, [pc, #52] ; (1e6c <digitalWrite+0x54>)
+ 1e36: 01db lsls r3, r3, #7
+ 1e38: 189a adds r2, r3, r2
+ 1e3a: 6890 ldr r0, [r2, #8]
+ 1e3c: 4228 tst r0, r5
+ 1e3e: d10b bne.n 1e58 <digitalWrite+0x40>
+ // the pin is not an output, disable pull-up if val is LOW, otherwise enable pull-up
+ PORT->Group[port].PINCFG[pin].bit.PULLEN = ((ulVal == LOW) ? 0 : 1) ;
+ 1e40: 000c movs r4, r1
+ 1e42: 1e60 subs r0, r4, #1
+ 1e44: 4184 sbcs r4, r0
+ 1e46: 19d2 adds r2, r2, r7
+ 1e48: 3240 adds r2, #64 ; 0x40
+ 1e4a: 7810 ldrb r0, [r2, #0]
+ 1e4c: 4034 ands r4, r6
+ 1e4e: 3603 adds r6, #3
+ 1e50: 00a4 lsls r4, r4, #2
+ 1e52: 43b0 bics r0, r6
+ 1e54: 4320 orrs r0, r4
+ 1e56: 7010 strb r0, [r2, #0]
+ }
+
+ switch ( ulVal )
+ {
+ case LOW:
+ PORT->Group[port].OUTCLR.reg = pinMask;
+ 1e58: 4a04 ldr r2, [pc, #16] ; (1e6c <digitalWrite+0x54>)
+ 1e5a: 189b adds r3, r3, r2
+ switch ( ulVal )
+ 1e5c: 2900 cmp r1, #0
+ 1e5e: d101 bne.n 1e64 <digitalWrite+0x4c>
+ PORT->Group[port].OUTCLR.reg = pinMask;
+ 1e60: 615d str r5, [r3, #20]
+ PORT->Group[port].OUTSET.reg = pinMask;
+ break ;
+ }
+
+ return ;
+}
+ 1e62: bdf0 pop {r4, r5, r6, r7, pc}
+ PORT->Group[port].OUTSET.reg = pinMask;
+ 1e64: 619d str r5, [r3, #24]
+ break ;
+ 1e66: e7fc b.n 1e62 <digitalWrite+0x4a>
+ 1e68: 00002ab4 .word 0x00002ab4
+ 1e6c: 41004400 .word 0x41004400
+
+00001e70 <pinPeripheral>:
+
+#include "Arduino.h"
+#include "wiring_private.h"
+
+int pinPeripheral( uint32_t ulPin, EPioType ulPeripheral )
+{
+ 1e70: b5f8 push {r3, r4, r5, r6, r7, lr}
+ 1e72: 0003 movs r3, r0
+ // Handle the case the pin isn't usable as PIO
+ if ( g_APinDescription[ulPin].ulPinType == PIO_NOT_A_PIN )
+ 1e74: 2018 movs r0, #24
+ 1e76: 4358 muls r0, r3
+ 1e78: 4a2a ldr r2, [pc, #168] ; (1f24 <pinPeripheral+0xb4>)
+ 1e7a: 1810 adds r0, r2, r0
+ 1e7c: 7a00 ldrb r0, [r0, #8]
+ 1e7e: b240 sxtb r0, r0
+ {
+ return -1 ;
+ 1e80: 0004 movs r4, r0
+ if ( g_APinDescription[ulPin].ulPinType == PIO_NOT_A_PIN )
+ 1e82: 3001 adds r0, #1
+ 1e84: d013 beq.n 1eae <pinPeripheral+0x3e>
+ }
+
+ switch ( ulPeripheral )
+ 1e86: 1c48 adds r0, r1, #1
+ case PIO_NOT_A_PIN:
+ return -1l ;
+ break ;
+ }
+
+ return 0l ;
+ 1e88: 2400 movs r4, #0
+ switch ( ulPeripheral )
+ 1e8a: 280c cmp r0, #12
+ 1e8c: d80f bhi.n 1eae <pinPeripheral+0x3e>
+ 1e8e: f000 fbf5 bl 267c <__gnu_thumb1_case_uqi>
+ 1e92: 1c45 .short 0x1c45
+ 1e94: 1c1c1c1c .word 0x1c1c1c1c
+ 1e98: 071c1c1c .word 0x071c1c1c
+ 1e9c: 0707 .short 0x0707
+ 1e9e: 07 .byte 0x07
+ 1e9f: 00 .byte 0x00
+ if ( ulPeripheral == PIO_INPUT )
+ 1ea0: 2909 cmp r1, #9
+ 1ea2: d106 bne.n 1eb2 <pinPeripheral+0x42>
+ pinMode( ulPin, INPUT ) ;
+ 1ea4: 2100 movs r1, #0
+ pinMode( ulPin, INPUT_PULLUP ) ;
+ 1ea6: 0018 movs r0, r3
+ 1ea8: f7ff ff6a bl 1d80 <pinMode>
+ return 0l ;
+ 1eac: 2400 movs r4, #0
+}
+ 1eae: 0020 movs r0, r4
+ 1eb0: bdf8 pop {r3, r4, r5, r6, r7, pc}
+ if ( ulPeripheral == PIO_INPUT_PULLUP )
+ 1eb2: 290a cmp r1, #10
+ 1eb4: d101 bne.n 1eba <pinPeripheral+0x4a>
+ pinMode( ulPin, INPUT_PULLUP ) ;
+ 1eb6: 3908 subs r1, #8
+ 1eb8: e7f5 b.n 1ea6 <pinPeripheral+0x36>
+ return 0l ;
+ 1eba: 2400 movs r4, #0
+ if ( ulPeripheral == PIO_OUTPUT )
+ 1ebc: 290b cmp r1, #11
+ 1ebe: d1f6 bne.n 1eae <pinPeripheral+0x3e>
+ pinMode( ulPin, OUTPUT ) ;
+ 1ec0: 390a subs r1, #10
+ 1ec2: 0018 movs r0, r3
+ 1ec4: f7ff ff5c bl 1d80 <pinMode>
+ 1ec8: e7f1 b.n 1eae <pinPeripheral+0x3e>
+ if ( g_APinDescription[ulPin].ulPin & 1 ) // is pin odd?
+ 1eca: 2018 movs r0, #24
+ 1ecc: 4343 muls r3, r0
+ 1ece: 18d0 adds r0, r2, r3
+ 1ed0: 6846 ldr r6, [r0, #4]
+ 1ed2: 2501 movs r5, #1
+ 1ed4: 0034 movs r4, r6
+ 1ed6: 56d2 ldrsb r2, [r2, r3]
+ temp = (PORT->Group[g_APinDescription[ulPin].ulPort].PMUX[g_APinDescription[ulPin].ulPin >> 1].reg) & PORT_PMUX_PMUXE( 0xF ) ;
+ 1ed8: 4813 ldr r0, [pc, #76] ; (1f28 <pinPeripheral+0xb8>)
+ 1eda: 01d2 lsls r2, r2, #7
+ 1edc: 1812 adds r2, r2, r0
+ 1ede: 0873 lsrs r3, r6, #1
+ 1ee0: 18d3 adds r3, r2, r3
+ 1ee2: 3330 adds r3, #48 ; 0x30
+ if ( g_APinDescription[ulPin].ulPin & 1 ) // is pin odd?
+ 1ee4: 402c ands r4, r5
+ temp = (PORT->Group[g_APinDescription[ulPin].ulPort].PMUX[g_APinDescription[ulPin].ulPin >> 1].reg) & PORT_PMUX_PMUXE( 0xF ) ;
+ 1ee6: 7818 ldrb r0, [r3, #0]
+ if ( g_APinDescription[ulPin].ulPin & 1 ) // is pin odd?
+ 1ee8: 2c00 cmp r4, #0
+ 1eea: d00b beq.n 1f04 <pinPeripheral+0x94>
+ PORT->Group[g_APinDescription[ulPin].ulPort].PMUX[g_APinDescription[ulPin].ulPin >> 1].reg = temp|PORT_PMUX_PMUXO( ulPeripheral ) ;
+ 1eec: 240f movs r4, #15
+ 1eee: 0109 lsls r1, r1, #4
+ 1ef0: 4020 ands r0, r4
+ 1ef2: 4301 orrs r1, r0
+ 1ef4: b2c9 uxtb r1, r1
+ PORT->Group[g_APinDescription[ulPin].ulPort].PINCFG[g_APinDescription[ulPin].ulPin].reg |= PORT_PINCFG_PMUXEN ;
+ 1ef6: 1992 adds r2, r2, r6
+ PORT->Group[g_APinDescription[ulPin].ulPort].PMUX[g_APinDescription[ulPin].ulPin >> 1].reg = temp|PORT_PMUX_PMUXO( ulPeripheral ) ;
+ 1ef8: 7019 strb r1, [r3, #0]
+ PORT->Group[g_APinDescription[ulPin].ulPort].PINCFG[g_APinDescription[ulPin].ulPin].reg |= PORT_PINCFG_PMUXEN ;
+ 1efa: 3240 adds r2, #64 ; 0x40
+ 1efc: 7813 ldrb r3, [r2, #0]
+ 1efe: 431d orrs r5, r3
+ 1f00: 7015 strb r5, [r2, #0]
+ 1f02: e7d3 b.n 1eac <pinPeripheral+0x3c>
+ PORT->Group[g_APinDescription[ulPin].ulPort].PMUX[g_APinDescription[ulPin].ulPin >> 1].reg = temp|PORT_PMUX_PMUXE( ulPeripheral ) ;
+ 1f04: 270f movs r7, #15
+ 1f06: 43b8 bics r0, r7
+ 1f08: 4301 orrs r1, r0
+ PORT->Group[g_APinDescription[ulPin].ulPort].PINCFG[g_APinDescription[ulPin].ulPin].reg |= PORT_PINCFG_PMUXEN ; // Enable port mux
+ 1f0a: 1992 adds r2, r2, r6
+ PORT->Group[g_APinDescription[ulPin].ulPort].PMUX[g_APinDescription[ulPin].ulPin >> 1].reg = temp|PORT_PMUX_PMUXE( ulPeripheral ) ;
+ 1f0c: b2c9 uxtb r1, r1
+ 1f0e: 7019 strb r1, [r3, #0]
+ PORT->Group[g_APinDescription[ulPin].ulPort].PINCFG[g_APinDescription[ulPin].ulPin].reg |= PORT_PINCFG_PMUXEN ; // Enable port mux
+ 1f10: 0013 movs r3, r2
+ 1f12: 3340 adds r3, #64 ; 0x40
+ 1f14: 781a ldrb r2, [r3, #0]
+ 1f16: 4315 orrs r5, r2
+ 1f18: 701d strb r5, [r3, #0]
+ 1f1a: e7c8 b.n 1eae <pinPeripheral+0x3e>
+ return -1l ;
+ 1f1c: 2401 movs r4, #1
+ 1f1e: 4264 negs r4, r4
+ 1f20: e7c5 b.n 1eae <pinPeripheral+0x3e>
+ 1f22: 46c0 nop ; (mov r8, r8)
+ 1f24: 00002ab4 .word 0x00002ab4
+ 1f28: 41004400 .word 0x41004400
+
+00001f2c <SERCOM0_Handler>:
+
+Uart Serial( &sercom0, PIN_SERIAL_RX, PIN_SERIAL_TX, PAD_SERIAL_RX, PAD_SERIAL_TX ) ;
+Uart Serial1( &sercom5, PIN_SERIAL1_RX, PIN_SERIAL1_TX, PAD_SERIAL1_RX, PAD_SERIAL1_TX ) ;
+
+void SERCOM0_Handler()
+{
+ 1f2c: b510 push {r4, lr}
+ Serial.IrqHandler();
+ 1f2e: 4802 ldr r0, [pc, #8] ; (1f38 <SERCOM0_Handler+0xc>)
+ 1f30: f000 faa9 bl 2486 <_ZN4Uart10IrqHandlerEv>
+}
+ 1f34: bd10 pop {r4, pc}
+ 1f36: 46c0 nop ; (mov r8, r8)
+ 1f38: 20000700 .word 0x20000700
+
+00001f3c <SERCOM5_Handler>:
+
+void SERCOM5_Handler()
+{
+ 1f3c: b510 push {r4, lr}
+ Serial1.IrqHandler();
+ 1f3e: 4802 ldr r0, [pc, #8] ; (1f48 <SERCOM5_Handler+0xc>)
+ 1f40: f000 faa1 bl 2486 <_ZN4Uart10IrqHandlerEv>
+ 1f44: bd10 pop {r4, pc}
+ 1f46: 46c0 nop ; (mov r8, r8)
+ 1f48: 2000093c .word 0x2000093c
+
+00001f4c <_GLOBAL__sub_I_g_APinDescription>:
+ 1f4c: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr}
+Uart Serial( &sercom0, PIN_SERIAL_RX, PIN_SERIAL_TX, PAD_SERIAL_RX, PAD_SERIAL_TX ) ;
+ 1f4e: 2401 movs r4, #1
+ 1f50: 2603 movs r6, #3
+SERCOM sercom0( SERCOM0 ) ;
+ 1f52: 4f15 ldr r7, [pc, #84] ; (1fa8 <_GLOBAL__sub_I_g_APinDescription+0x5c>)
+ 1f54: 4915 ldr r1, [pc, #84] ; (1fac <_GLOBAL__sub_I_g_APinDescription+0x60>)
+ 1f56: 0038 movs r0, r7
+ 1f58: f000 f84a bl 1ff0 <_ZN6SERCOMC1EP6Sercom>
+SERCOM sercom1( SERCOM1 ) ;
+ 1f5c: 4914 ldr r1, [pc, #80] ; (1fb0 <_GLOBAL__sub_I_g_APinDescription+0x64>)
+ 1f5e: 4815 ldr r0, [pc, #84] ; (1fb4 <_GLOBAL__sub_I_g_APinDescription+0x68>)
+ 1f60: f000 f846 bl 1ff0 <_ZN6SERCOMC1EP6Sercom>
+SERCOM sercom2( SERCOM2 ) ;
+ 1f64: 4914 ldr r1, [pc, #80] ; (1fb8 <_GLOBAL__sub_I_g_APinDescription+0x6c>)
+ 1f66: 4815 ldr r0, [pc, #84] ; (1fbc <_GLOBAL__sub_I_g_APinDescription+0x70>)
+ 1f68: f000 f842 bl 1ff0 <_ZN6SERCOMC1EP6Sercom>
+SERCOM sercom3( SERCOM3 ) ;
+ 1f6c: 4914 ldr r1, [pc, #80] ; (1fc0 <_GLOBAL__sub_I_g_APinDescription+0x74>)
+ 1f6e: 4815 ldr r0, [pc, #84] ; (1fc4 <_GLOBAL__sub_I_g_APinDescription+0x78>)
+ 1f70: f000 f83e bl 1ff0 <_ZN6SERCOMC1EP6Sercom>
+SERCOM sercom4( SERCOM4 ) ;
+ 1f74: 4914 ldr r1, [pc, #80] ; (1fc8 <_GLOBAL__sub_I_g_APinDescription+0x7c>)
+ 1f76: 4815 ldr r0, [pc, #84] ; (1fcc <_GLOBAL__sub_I_g_APinDescription+0x80>)
+ 1f78: f000 f83a bl 1ff0 <_ZN6SERCOMC1EP6Sercom>
+SERCOM sercom5( SERCOM5 ) ;
+ 1f7c: 4d14 ldr r5, [pc, #80] ; (1fd0 <_GLOBAL__sub_I_g_APinDescription+0x84>)
+ 1f7e: 4915 ldr r1, [pc, #84] ; (1fd4 <_GLOBAL__sub_I_g_APinDescription+0x88>)
+ 1f80: 0028 movs r0, r5
+ 1f82: f000 f835 bl 1ff0 <_ZN6SERCOMC1EP6Sercom>
+Uart Serial( &sercom0, PIN_SERIAL_RX, PIN_SERIAL_TX, PAD_SERIAL_RX, PAD_SERIAL_TX ) ;
+ 1f86: 0039 movs r1, r7
+ 1f88: 9600 str r6, [sp, #0]
+ 1f8a: 0023 movs r3, r4
+ 1f8c: 9401 str r4, [sp, #4]
+ 1f8e: 2200 movs r2, #0
+ 1f90: 4811 ldr r0, [pc, #68] ; (1fd8 <_GLOBAL__sub_I_g_APinDescription+0x8c>)
+ 1f92: f000 fa0d bl 23b0 <_ZN4UartC1EP6SERCOMhh11SercomRXPad15SercomUartTXPad>
+Uart Serial1( &sercom5, PIN_SERIAL1_RX, PIN_SERIAL1_TX, PAD_SERIAL1_RX, PAD_SERIAL1_TX ) ;
+ 1f96: 9600 str r6, [sp, #0]
+ 1f98: 0029 movs r1, r5
+ 1f9a: 9401 str r4, [sp, #4]
+ 1f9c: 231e movs r3, #30
+ 1f9e: 221f movs r2, #31
+ 1fa0: 480e ldr r0, [pc, #56] ; (1fdc <_GLOBAL__sub_I_g_APinDescription+0x90>)
+ 1fa2: f000 fa05 bl 23b0 <_ZN4UartC1EP6SERCOMhh11SercomRXPad15SercomUartTXPad>
+ 1fa6: bdf7 pop {r0, r1, r2, r4, r5, r6, r7, pc}
+ 1fa8: 20000b78 .word 0x20000b78
+ 1fac: 42000800 .word 0x42000800
+ 1fb0: 42000c00 .word 0x42000c00
+ 1fb4: 20000b7c .word 0x20000b7c
+ 1fb8: 42001000 .word 0x42001000
+ 1fbc: 20000b80 .word 0x20000b80
+ 1fc0: 42001400 .word 0x42001400
+ 1fc4: 20000b84 .word 0x20000b84
+ 1fc8: 42001800 .word 0x42001800
+ 1fcc: 20000b88 .word 0x20000b88
+ 1fd0: 20000b8c .word 0x20000b8c
+ 1fd4: 42001c00 .word 0x42001c00
+ 1fd8: 20000700 .word 0x20000700
+ 1fdc: 2000093c .word 0x2000093c
+
+00001fe0 <_Znwj>:
+ 1fe0: b510 push {r4, lr}
+ 1fe2: f000 fc05 bl 27f0 <malloc>
+ 1fe6: bd10 pop {r4, pc}
+
+00001fe8 <_ZdlPv>:
+ 1fe8: b510 push {r4, lr}
+ 1fea: f000 fc0b bl 2804 <free>
+ 1fee: bd10 pop {r4, pc}
+
+00001ff0 <_ZN6SERCOMC1EP6Sercom>:
+#define WIRE_RISE_TIME_NANOSECONDS 125
+#endif
+
+SERCOM::SERCOM(Sercom* s)
+{
+ sercom = s;
+ 1ff0: 6001 str r1, [r0, #0]
+}
+ 1ff2: 4770 bx lr
+
+00001ff4 <_ZN6SERCOM9initFrameE18SercomUartCharSize15SercomDataOrder16SercomParityMode19SercomNumberStopBit>:
+ sercom->USART.BAUD.FRAC.FP = (baudTimes8 % 8);
+ sercom->USART.BAUD.FRAC.BAUD = (baudTimes8 / 8);
+ }
+}
+void SERCOM::initFrame(SercomUartCharSize charSize, SercomDataOrder dataOrder, SercomParityMode parityMode, SercomNumberStopBit nbStopBits)
+{
+ 1ff4: b5f0 push {r4, r5, r6, r7, lr}
+ 1ff6: ac05 add r4, sp, #20
+ 1ff8: 7825 ldrb r5, [r4, #0]
+ //Setting the CTRLA register
+ sercom->USART.CTRLA.reg |= SERCOM_USART_CTRLA_FORM( (parityMode == SERCOM_NO_PARITY ? 0 : 1) ) |
+ 1ffa: 6804 ldr r4, [r0, #0]
+ 1ffc: 1e98 subs r0, r3, #2
+ 1ffe: 1e47 subs r7, r0, #1
+ 2000: 41b8 sbcs r0, r7
+ dataOrder << SERCOM_USART_CTRLA_DORD_Pos;
+ 2002: 6826 ldr r6, [r4, #0]
+ 2004: 0792 lsls r2, r2, #30
+ sercom->USART.CTRLA.reg |= SERCOM_USART_CTRLA_FORM( (parityMode == SERCOM_NO_PARITY ? 0 : 1) ) |
+ 2006: 0600 lsls r0, r0, #24
+ dataOrder << SERCOM_USART_CTRLA_DORD_Pos;
+ 2008: 4332 orrs r2, r6
+ 200a: 4302 orrs r2, r0
+
+ //Setting the CTRLB register
+ sercom->USART.CTRLB.reg |= SERCOM_USART_CTRLB_CHSIZE(charSize) |
+ 200c: 2007 movs r0, #7
+ sercom->USART.CTRLA.reg |= SERCOM_USART_CTRLA_FORM( (parityMode == SERCOM_NO_PARITY ? 0 : 1) ) |
+ 200e: 6022 str r2, [r4, #0]
+ sercom->USART.CTRLB.reg |= SERCOM_USART_CTRLB_CHSIZE(charSize) |
+ 2010: 4001 ands r1, r0
+ nbStopBits << SERCOM_USART_CTRLB_SBMODE_Pos |
+ 2012: 01ad lsls r5, r5, #6
+ (parityMode == SERCOM_NO_PARITY ? 0 : parityMode) << SERCOM_USART_CTRLB_PMODE_Pos; //If no parity use default value
+ 2014: 6862 ldr r2, [r4, #4]
+ 2016: 4329 orrs r1, r5
+ 2018: 2000 movs r0, #0
+ 201a: 2b02 cmp r3, #2
+ 201c: d000 beq.n 2020 <_ZN6SERCOM9initFrameE18SercomUartCharSize15SercomDataOrder16SercomParityMode19SercomNumberStopBit+0x2c>
+ 201e: 0358 lsls r0, r3, #13
+ 2020: 4311 orrs r1, r2
+ 2022: 4301 orrs r1, r0
+ sercom->USART.CTRLB.reg |= SERCOM_USART_CTRLB_CHSIZE(charSize) |
+ 2024: 6061 str r1, [r4, #4]
+}
+ 2026: bdf0 pop {r4, r5, r6, r7, pc}
+
+00002028 <_ZN6SERCOM8initPadsE15SercomUartTXPad11SercomRXPad>:
+
+void SERCOM::initPads(SercomUartTXPad txPad, SercomRXPad rxPad)
+{
+ 2028: b510 push {r4, lr}
+ //Setting the CTRLA register
+ sercom->USART.CTRLA.reg |= SERCOM_USART_CTRLA_TXPO(txPad) |
+ SERCOM_USART_CTRLA_RXPO(rxPad);
+ 202a: 24c0 movs r4, #192 ; 0xc0
+ sercom->USART.CTRLA.reg |= SERCOM_USART_CTRLA_TXPO(txPad) |
+ 202c: 6803 ldr r3, [r0, #0]
+ SERCOM_USART_CTRLA_RXPO(rxPad);
+ 202e: 03a4 lsls r4, r4, #14
+ 2030: 6818 ldr r0, [r3, #0]
+ 2032: 0512 lsls r2, r2, #20
+ 2034: 4022 ands r2, r4
+ 2036: 4302 orrs r2, r0
+ sercom->USART.CTRLA.reg |= SERCOM_USART_CTRLA_TXPO(txPad) |
+ 2038: 20c0 movs r0, #192 ; 0xc0
+ 203a: 0409 lsls r1, r1, #16
+ 203c: 0280 lsls r0, r0, #10
+ 203e: 4001 ands r1, r0
+ SERCOM_USART_CTRLA_RXPO(rxPad);
+ 2040: 4311 orrs r1, r2
+ sercom->USART.CTRLA.reg |= SERCOM_USART_CTRLA_TXPO(txPad) |
+ 2042: 6019 str r1, [r3, #0]
+
+ // Enable Transceiver and Receiver
+ sercom->USART.CTRLB.reg |= SERCOM_USART_CTRLB_TXEN | SERCOM_USART_CTRLB_RXEN ;
+ 2044: 685a ldr r2, [r3, #4]
+ 2046: 4310 orrs r0, r2
+ 2048: 6058 str r0, [r3, #4]
+}
+ 204a: bd10 pop {r4, pc}
+
+0000204c <_ZN6SERCOM9resetUARTEv>:
+
+void SERCOM::resetUART()
+{
+ // Start the Software Reset
+ sercom->USART.CTRLA.bit.SWRST = 1 ;
+ 204c: 2201 movs r2, #1
+ 204e: 6803 ldr r3, [r0, #0]
+ 2050: 6819 ldr r1, [r3, #0]
+ 2052: 430a orrs r2, r1
+ 2054: 601a str r2, [r3, #0]
+
+ while ( sercom->USART.CTRLA.bit.SWRST || sercom->USART.SYNCBUSY.bit.SWRST )
+ 2056: 681a ldr r2, [r3, #0]
+ 2058: 07d2 lsls r2, r2, #31
+ 205a: d4fc bmi.n 2056 <_ZN6SERCOM9resetUARTEv+0xa>
+ 205c: 69da ldr r2, [r3, #28]
+ 205e: 07d2 lsls r2, r2, #31
+ 2060: d4f9 bmi.n 2056 <_ZN6SERCOM9resetUARTEv+0xa>
+ {
+ // Wait for both bits Software Reset from CTRLA and SYNCBUSY coming back to 0
+ }
+}
+ 2062: 4770 bx lr
+
+00002064 <_ZN6SERCOM10enableUARTEv>:
+
+void SERCOM::enableUART()
+{
+ //Setting the enable bit to 1
+ sercom->USART.CTRLA.bit.ENABLE = 0x1u;
+ 2064: 2202 movs r2, #2
+ 2066: 6803 ldr r3, [r0, #0]
+ 2068: 6819 ldr r1, [r3, #0]
+ 206a: 430a orrs r2, r1
+ 206c: 601a str r2, [r3, #0]
+
+ //Wait for then enable bit from SYNCBUSY is equal to 0;
+ while(sercom->USART.SYNCBUSY.bit.ENABLE);
+ 206e: 69da ldr r2, [r3, #28]
+ 2070: 0792 lsls r2, r2, #30
+ 2072: d4fc bmi.n 206e <_ZN6SERCOM10enableUARTEv+0xa>
+}
+ 2074: 4770 bx lr
+
+00002076 <_ZN6SERCOM9flushUARTEv>:
+}
+
+bool SERCOM::isDataRegisterEmptyUART()
+{
+ //DRE : Data Register Empty
+ return sercom->USART.INTFLAG.bit.DRE;
+ 2076: 6803 ldr r3, [r0, #0]
+ 2078: 7e1a ldrb r2, [r3, #24]
+ if(isDataRegisterEmptyUART())
+ 207a: 07d2 lsls r2, r2, #31
+ 207c: d402 bmi.n 2084 <_ZN6SERCOM9flushUARTEv+0xe>
+ while(!sercom->USART.INTFLAG.bit.TXC);
+ 207e: 7e1a ldrb r2, [r3, #24]
+ 2080: 0792 lsls r2, r2, #30
+ 2082: d5fc bpl.n 207e <_ZN6SERCOM9flushUARTEv+0x8>
+}
+ 2084: 4770 bx lr
+
+00002086 <_ZN6SERCOM15clearStatusUARTEv>:
+ sercom->USART.STATUS.reg = SERCOM_USART_STATUS_RESETVALUE;
+ 2086: 2200 movs r2, #0
+ 2088: 6803 ldr r3, [r0, #0]
+ 208a: 835a strh r2, [r3, #26]
+}
+ 208c: 4770 bx lr
+
+0000208e <_ZN6SERCOM17availableDataUARTEv>:
+ return sercom->USART.INTFLAG.bit.RXC;
+ 208e: 6803 ldr r3, [r0, #0]
+ 2090: 7e18 ldrb r0, [r3, #24]
+ 2092: 0740 lsls r0, r0, #29
+ 2094: 0fc0 lsrs r0, r0, #31
+}
+ 2096: 4770 bx lr
+
+00002098 <_ZN6SERCOM11isUARTErrorEv>:
+ return sercom->USART.INTFLAG.bit.ERROR;
+ 2098: 6803 ldr r3, [r0, #0]
+ 209a: 7e18 ldrb r0, [r3, #24]
+ 209c: 09c0 lsrs r0, r0, #7
+}
+ 209e: 4770 bx lr
+
+000020a0 <_ZN6SERCOM20acknowledgeUARTErrorEv>:
+ sercom->USART.INTFLAG.bit.ERROR = 1;
+ 20a0: 2380 movs r3, #128 ; 0x80
+ 20a2: 6802 ldr r2, [r0, #0]
+ 20a4: 425b negs r3, r3
+ 20a6: 7e11 ldrb r1, [r2, #24]
+ 20a8: 430b orrs r3, r1
+ 20aa: 7613 strb r3, [r2, #24]
+}
+ 20ac: 4770 bx lr
+
+000020ae <_ZN6SERCOM16isFrameErrorUARTEv>:
+ return sercom->USART.STATUS.bit.FERR;
+ 20ae: 6803 ldr r3, [r0, #0]
+ 20b0: 8b58 ldrh r0, [r3, #26]
+ 20b2: 0780 lsls r0, r0, #30
+ 20b4: 0fc0 lsrs r0, r0, #31
+}
+ 20b6: 4770 bx lr
+
+000020b8 <_ZN6SERCOM19clearFrameErrorUARTEv>:
+ sercom->USART.STATUS.bit.FERR = 1;
+ 20b8: 2302 movs r3, #2
+ 20ba: 6802 ldr r2, [r0, #0]
+ 20bc: 8b51 ldrh r1, [r2, #26]
+ 20be: 430b orrs r3, r1
+ 20c0: 8353 strh r3, [r2, #26]
+}
+ 20c2: 4770 bx lr
+
+000020c4 <_ZN6SERCOM23isDataRegisterEmptyUARTEv>:
+ return sercom->USART.INTFLAG.bit.DRE;
+ 20c4: 6803 ldr r3, [r0, #0]
+ 20c6: 7e18 ldrb r0, [r3, #24]
+ 20c8: 07c0 lsls r0, r0, #31
+ 20ca: 0fc0 lsrs r0, r0, #31
+}
+ 20cc: 4770 bx lr
+
+000020ce <_ZN6SERCOM12readDataUARTEv>:
+
+uint8_t SERCOM::readDataUART()
+{
+ return sercom->USART.DATA.bit.DATA;
+ 20ce: 6803 ldr r3, [r0, #0]
+ 20d0: 8d18 ldrh r0, [r3, #40] ; 0x28
+ 20d2: b2c0 uxtb r0, r0
+}
+ 20d4: 4770 bx lr
+
+000020d6 <_ZN6SERCOM13writeDataUARTEh>:
+ return sercom->USART.INTFLAG.bit.DRE;
+ 20d6: 6803 ldr r3, [r0, #0]
+ 20d8: 7e1a ldrb r2, [r3, #24]
+
+int SERCOM::writeDataUART(uint8_t data)
+{
+ // Wait for data register to be empty
+ while(!isDataRegisterEmptyUART());
+ 20da: 07d2 lsls r2, r2, #31
+ 20dc: d5fc bpl.n 20d8 <_ZN6SERCOM13writeDataUARTEh+0x2>
+
+ //Put data into DATA register
+ sercom->USART.DATA.reg = (uint16_t)data;
+ 20de: b289 uxth r1, r1
+ return 1;
+}
+ 20e0: 2001 movs r0, #1
+ sercom->USART.DATA.reg = (uint16_t)data;
+ 20e2: 8519 strh r1, [r3, #40] ; 0x28
+}
+ 20e4: 4770 bx lr
+
+000020e6 <_ZN6SERCOM36enableDataRegisterEmptyInterruptUARTEv>:
+
+void SERCOM::enableDataRegisterEmptyInterruptUART()
+{
+ sercom->USART.INTENSET.reg = SERCOM_USART_INTENSET_DRE;
+ 20e6: 2201 movs r2, #1
+ 20e8: 6803 ldr r3, [r0, #0]
+ 20ea: 759a strb r2, [r3, #22]
+}
+ 20ec: 4770 bx lr
+
+000020ee <_ZN6SERCOM37disableDataRegisterEmptyInterruptUARTEv>:
+
+void SERCOM::disableDataRegisterEmptyInterruptUART()
+{
+ sercom->USART.INTENCLR.reg = SERCOM_USART_INTENCLR_DRE;
+ 20ee: 2201 movs r2, #1
+ 20f0: 6803 ldr r3, [r0, #0]
+ 20f2: 751a strb r2, [r3, #20]
+}
+ 20f4: 4770 bx lr
+ ...
+
+000020f8 <_ZN6SERCOM13initClockNVICEv>:
+void SERCOM::initClockNVIC( void )
+{
+ uint8_t clockId = 0;
+ IRQn_Type IdNvic=PendSV_IRQn ; // Dummy init to intercept potential error later
+
+ if(sercom == SERCOM0)
+ 20f8: 6803 ldr r3, [r0, #0]
+ 20fa: 4a21 ldr r2, [pc, #132] ; (2180 <_ZN6SERCOM13initClockNVICEv+0x88>)
+{
+ 20fc: b530 push {r4, r5, lr}
+ if(sercom == SERCOM0)
+ 20fe: 4293 cmp r3, r2
+ 2100: d011 beq.n 2126 <_ZN6SERCOM13initClockNVICEv+0x2e>
+ {
+ clockId = GCM_SERCOM0_CORE;
+ IdNvic = SERCOM0_IRQn;
+ }
+ else if(sercom == SERCOM1)
+ 2102: 4a20 ldr r2, [pc, #128] ; (2184 <_ZN6SERCOM13initClockNVICEv+0x8c>)
+ 2104: 4293 cmp r3, r2
+ 2106: d02f beq.n 2168 <_ZN6SERCOM13initClockNVICEv+0x70>
+ {
+ clockId = GCM_SERCOM1_CORE;
+ IdNvic = SERCOM1_IRQn;
+ }
+ else if(sercom == SERCOM2)
+ 2108: 4a1f ldr r2, [pc, #124] ; (2188 <_ZN6SERCOM13initClockNVICEv+0x90>)
+ 210a: 4293 cmp r3, r2
+ 210c: d02f beq.n 216e <_ZN6SERCOM13initClockNVICEv+0x76>
+ {
+ clockId = GCM_SERCOM2_CORE;
+ IdNvic = SERCOM2_IRQn;
+ }
+ else if(sercom == SERCOM3)
+ 210e: 4a1f ldr r2, [pc, #124] ; (218c <_ZN6SERCOM13initClockNVICEv+0x94>)
+ 2110: 4293 cmp r3, r2
+ 2112: d02f beq.n 2174 <_ZN6SERCOM13initClockNVICEv+0x7c>
+ {
+ clockId = GCM_SERCOM3_CORE;
+ IdNvic = SERCOM3_IRQn;
+ }
+ #if defined(SERCOM4)
+ else if(sercom == SERCOM4)
+ 2114: 4a1e ldr r2, [pc, #120] ; (2190 <_ZN6SERCOM13initClockNVICEv+0x98>)
+ 2116: 4293 cmp r3, r2
+ 2118: d02f beq.n 217a <_ZN6SERCOM13initClockNVICEv+0x82>
+ clockId = GCM_SERCOM4_CORE;
+ IdNvic = SERCOM4_IRQn;
+ }
+ #endif // SERCOM4
+ #if defined(SERCOM5)
+ else if(sercom == SERCOM5)
+ 211a: 4a1e ldr r2, [pc, #120] ; (2194 <_ZN6SERCOM13initClockNVICEv+0x9c>)
+ 211c: 4293 cmp r3, r2
+ 211e: d122 bne.n 2166 <_ZN6SERCOM13initClockNVICEv+0x6e>
+ {
+ clockId = GCM_SERCOM5_CORE;
+ IdNvic = SERCOM5_IRQn;
+ 2120: 230e movs r3, #14
+ clockId = GCM_SERCOM5_CORE;
+ 2122: 2219 movs r2, #25
+ 2124: e001 b.n 212a <_ZN6SERCOM13initClockNVICEv+0x32>
+ IdNvic = SERCOM0_IRQn;
+ 2126: 2309 movs r3, #9
+ clockId = GCM_SERCOM0_CORE;
+ 2128: 2214 movs r2, #20
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ 212a: 2101 movs r1, #1
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ 212c: 2503 movs r5, #3
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ 212e: 4099 lsls r1, r3
+ 2130: 4819 ldr r0, [pc, #100] ; (2198 <_ZN6SERCOM13initClockNVICEv+0xa0>)
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ 2132: 24c0 movs r4, #192 ; 0xc0
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ 2134: 6001 str r1, [r0, #0]
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ 2136: 0899 lsrs r1, r3, #2
+ 2138: 402b ands r3, r5
+ 213a: 40ab lsls r3, r5
+ 213c: 35fc adds r5, #252 ; 0xfc
+ 213e: 409d lsls r5, r3
+ 2140: 0089 lsls r1, r1, #2
+ 2142: 1809 adds r1, r1, r0
+ 2144: 00a4 lsls r4, r4, #2
+ 2146: 5908 ldr r0, [r1, r4]
+ 2148: 43a8 bics r0, r5
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ 214a: 25c0 movs r5, #192 ; 0xc0
+ 214c: 409d lsls r5, r3
+ 214e: 002b movs r3, r5
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ 2150: 4303 orrs r3, r0
+ 2152: 510b str r3, [r1, r4]
+ NVIC_EnableIRQ(IdNvic);
+ NVIC_SetPriority (IdNvic, SERCOM_NVIC_PRIORITY); /* set Priority */
+
+ //Setting clock
+ GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID( clockId ) | // Generic Clock 0 (SERCOMx)
+ GCLK_CLKCTRL_GEN_GCLK0 | // Generic Clock Generator 0 is source
+ 2154: 2380 movs r3, #128 ; 0x80
+ 2156: 01db lsls r3, r3, #7
+ 2158: 431a orrs r2, r3
+ GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID( clockId ) | // Generic Clock 0 (SERCOMx)
+ 215a: 4b10 ldr r3, [pc, #64] ; (219c <_ZN6SERCOM13initClockNVICEv+0xa4>)
+ 215c: 805a strh r2, [r3, #2]
+ GCLK_CLKCTRL_CLKEN ;
+
+ while ( GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY )
+ 215e: 785a ldrb r2, [r3, #1]
+ 2160: b252 sxtb r2, r2
+ 2162: 2a00 cmp r2, #0
+ 2164: dbfb blt.n 215e <_ZN6SERCOM13initClockNVICEv+0x66>
+ {
+ /* Wait for synchronization */
+ }
+}
+ 2166: bd30 pop {r4, r5, pc}
+ IdNvic = SERCOM1_IRQn;
+ 2168: 230a movs r3, #10
+ clockId = GCM_SERCOM1_CORE;
+ 216a: 2215 movs r2, #21
+ 216c: e7dd b.n 212a <_ZN6SERCOM13initClockNVICEv+0x32>
+ IdNvic = SERCOM2_IRQn;
+ 216e: 230b movs r3, #11
+ clockId = GCM_SERCOM2_CORE;
+ 2170: 2216 movs r2, #22
+ 2172: e7da b.n 212a <_ZN6SERCOM13initClockNVICEv+0x32>
+ IdNvic = SERCOM3_IRQn;
+ 2174: 230c movs r3, #12
+ clockId = GCM_SERCOM3_CORE;
+ 2176: 2217 movs r2, #23
+ 2178: e7d7 b.n 212a <_ZN6SERCOM13initClockNVICEv+0x32>
+ IdNvic = SERCOM4_IRQn;
+ 217a: 230d movs r3, #13
+ clockId = GCM_SERCOM4_CORE;
+ 217c: 2218 movs r2, #24
+ 217e: e7d4 b.n 212a <_ZN6SERCOM13initClockNVICEv+0x32>
+ 2180: 42000800 .word 0x42000800
+ 2184: 42000c00 .word 0x42000c00
+ 2188: 42001000 .word 0x42001000
+ 218c: 42001400 .word 0x42001400
+ 2190: 42001800 .word 0x42001800
+ 2194: 42001c00 .word 0x42001c00
+ 2198: e000e100 .word 0xe000e100
+ 219c: 40000c00 .word 0x40000c00
+
+000021a0 <_ZN6SERCOM8initUARTE14SercomUartMode20SercomUartSampleRatem>:
+{
+ 21a0: b5f8 push {r3, r4, r5, r6, r7, lr}
+ 21a2: 0004 movs r4, r0
+ 21a4: 0016 movs r6, r2
+ 21a6: 000f movs r7, r1
+ 21a8: 001d movs r5, r3
+ initClockNVIC();
+ 21aa: f7ff ffa5 bl 20f8 <_ZN6SERCOM13initClockNVICEv>
+ resetUART();
+ 21ae: 0020 movs r0, r4
+ 21b0: f7ff ff4c bl 204c <_ZN6SERCOM9resetUARTEv>
+ sercom->USART.CTRLA.reg = SERCOM_USART_CTRLA_MODE(mode) |
+ 21b4: 221c movs r2, #28
+ 21b6: 00bb lsls r3, r7, #2
+ 21b8: 4013 ands r3, r2
+ SERCOM_USART_CTRLA_SAMPR(sampleRate);
+ 21ba: 0772 lsls r2, r6, #29
+ sercom->USART.CTRLA.reg = SERCOM_USART_CTRLA_MODE(mode) |
+ 21bc: 6824 ldr r4, [r4, #0]
+ SERCOM_USART_CTRLA_SAMPR(sampleRate);
+ 21be: 0c12 lsrs r2, r2, #16
+ sercom->USART.CTRLA.reg = SERCOM_USART_CTRLA_MODE(mode) |
+ 21c0: 4313 orrs r3, r2
+ 21c2: 6023 str r3, [r4, #0]
+ sercom->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXC | //Received complete
+ 21c4: 2384 movs r3, #132 ; 0x84
+ 21c6: 75a3 strb r3, [r4, #22]
+ if ( mode == UART_INT_CLOCK )
+ 21c8: 2f01 cmp r7, #1
+ 21ca: d118 bne.n 21fe <_ZN6SERCOM8initUARTE14SercomUartMode20SercomUartSampleRatem+0x5e>
+ sampleRateValue = 16;
+ 21cc: 2110 movs r1, #16
+ if (sampleRate == SAMPLE_RATE_x16) {
+ 21ce: 2e01 cmp r6, #1
+ 21d0: d000 beq.n 21d4 <_ZN6SERCOM8initUARTE14SercomUartMode20SercomUartSampleRatem+0x34>
+ sampleRateValue = 8;
+ 21d2: 3908 subs r1, #8
+ uint32_t baudTimes8 = (SystemCoreClock * 8) / (sampleRateValue * baudrate);
+ 21d4: 4b0a ldr r3, [pc, #40] ; (2200 <_ZN6SERCOM8initUARTE14SercomUartMode20SercomUartSampleRatem+0x60>)
+ 21d6: 4369 muls r1, r5
+ 21d8: 6818 ldr r0, [r3, #0]
+ 21da: 00c0 lsls r0, r0, #3
+ 21dc: f000 fa58 bl 2690 <__udivsi3>
+ sercom->USART.BAUD.FRAC.FP = (baudTimes8 % 8);
+ 21e0: 2207 movs r2, #7
+ 21e2: 89a3 ldrh r3, [r4, #12]
+ 21e4: 4002 ands r2, r0
+ 21e6: 04db lsls r3, r3, #19
+ 21e8: 0352 lsls r2, r2, #13
+ 21ea: 0cdb lsrs r3, r3, #19
+ 21ec: 4313 orrs r3, r2
+ 21ee: 81a3 strh r3, [r4, #12]
+ sercom->USART.BAUD.FRAC.BAUD = (baudTimes8 / 8);
+ 21f0: 0403 lsls r3, r0, #16
+ 21f2: 89a0 ldrh r0, [r4, #12]
+ 21f4: 0cdb lsrs r3, r3, #19
+ 21f6: 0b40 lsrs r0, r0, #13
+ 21f8: 0340 lsls r0, r0, #13
+ 21fa: 4318 orrs r0, r3
+ 21fc: 81a0 strh r0, [r4, #12]
+}
+ 21fe: bdf8 pop {r3, r4, r5, r6, r7, pc}
+ 2200: 20000014 .word 0x20000014
+
+00002204 <_ZN4UartcvbEv>:
+ size_t write(const uint8_t data);
+ using Print::write; // pull in write(str) and write(buf, size) from Print
+
+ void IrqHandler();
+
+ operator bool() { return true; }
+ 2204: 2001 movs r0, #1
+ 2206: 4770 bx lr
+
+00002208 <_ZN4Uart5beginEm>:
+ uc_pinRTS = _pinRTS;
+ uc_pinCTS = _pinCTS;
+}
+
+void Uart::begin(unsigned long baudrate)
+{
+ 2208: b510 push {r4, lr}
+ begin(baudrate, SERIAL_8N1);
+ 220a: 6803 ldr r3, [r0, #0]
+ 220c: 4a01 ldr r2, [pc, #4] ; (2214 <_ZN4Uart5beginEm+0xc>)
+ 220e: 6a1b ldr r3, [r3, #32]
+ 2210: 4798 blx r3
+}
+ 2212: bd10 pop {r4, pc}
+ 2214: 00000413 .word 0x00000413
+
+00002218 <_ZN4Uart4peekEv>:
+ if(_iTail == _iHead)
+ 2218: 0003 movs r3, r0
+ 221a: 33fc adds r3, #252 ; 0xfc
+ 221c: 69d9 ldr r1, [r3, #28]
+ 221e: 699a ldr r2, [r3, #24]
+ 2220: 4291 cmp r1, r2
+ 2222: d003 beq.n 222c <_ZN4Uart4peekEv+0x14>
+ return _aucBuffer[_iTail];
+ 2224: 69db ldr r3, [r3, #28]
+ 2226: 18c0 adds r0, r0, r3
+ 2228: 7d00 ldrb r0, [r0, #20]
+}
+
+int Uart::peek()
+{
+ return rxBuffer.peek();
+}
+ 222a: 4770 bx lr
+ return -1;
+ 222c: 2001 movs r0, #1
+ 222e: 4240 negs r0, r0
+ return rxBuffer.peek();
+ 2230: e7fb b.n 222a <_ZN4Uart4peekEv+0x12>
+
+00002232 <_ZN4Uart3endEv>:
+{
+ 2232: b510 push {r4, lr}
+ 2234: 0004 movs r4, r0
+ sercom->resetUART();
+ 2236: 6900 ldr r0, [r0, #16]
+ 2238: f7ff ff08 bl 204c <_ZN6SERCOM9resetUARTEv>
+ _iHead = 0;
+ 223c: 0022 movs r2, r4
+ 223e: 2300 movs r3, #0
+ 2240: 32fc adds r2, #252 ; 0xfc
+ 2242: 6193 str r3, [r2, #24]
+ _iTail = 0;
+ 2244: 61d3 str r3, [r2, #28]
+ _iHead = 0;
+ 2246: 2286 movs r2, #134 ; 0x86
+ 2248: 0092 lsls r2, r2, #2
+ 224a: 18a4 adds r4, r4, r2
+ 224c: 6063 str r3, [r4, #4]
+ _iTail = 0;
+ 224e: 60a3 str r3, [r4, #8]
+}
+ 2250: bd10 pop {r4, pc}
+
+00002252 <_ZN4Uart16extractNbStopBitEt>:
+ return 1;
+}
+
+SercomNumberStopBit Uart::extractNbStopBit(uint16_t config)
+{
+ switch(config & HARDSER_STOP_BIT_MASK)
+ 2252: 20f0 movs r0, #240 ; 0xf0
+ 2254: 4001 ands r1, r0
+ {
+ case HARDSER_STOP_BIT_1:
+ default:
+ return SERCOM_STOP_BIT_1;
+ 2256: 3930 subs r1, #48 ; 0x30
+ 2258: 4248 negs r0, r1
+ 225a: 4148 adcs r0, r1
+
+ case HARDSER_STOP_BIT_2:
+ return SERCOM_STOP_BITS_2;
+ }
+}
+ 225c: 4770 bx lr
+
+0000225e <_ZN4Uart15extractCharSizeEt>:
+
+SercomUartCharSize Uart::extractCharSize(uint16_t config)
+{
+ switch(config & HARDSER_DATA_MASK)
+ 225e: 23f0 movs r3, #240 ; 0xf0
+ 2260: 011b lsls r3, r3, #4
+ 2262: 4019 ands r1, r3
+ 2264: 2380 movs r3, #128 ; 0x80
+ {
+ case HARDSER_DATA_5:
+ return UART_CHAR_SIZE_5_BITS;
+
+ case HARDSER_DATA_6:
+ return UART_CHAR_SIZE_6_BITS;
+ 2266: 2006 movs r0, #6
+ switch(config & HARDSER_DATA_MASK)
+ 2268: 009b lsls r3, r3, #2
+ 226a: 4299 cmp r1, r3
+ 226c: d00a beq.n 2284 <_ZN4Uart15extractCharSizeEt+0x26>
+ 226e: 3301 adds r3, #1
+ 2270: 33ff adds r3, #255 ; 0xff
+
+ case HARDSER_DATA_7:
+ return UART_CHAR_SIZE_7_BITS;
+ 2272: 3001 adds r0, #1
+ switch(config & HARDSER_DATA_MASK)
+ 2274: 4299 cmp r1, r3
+ 2276: d005 beq.n 2284 <_ZN4Uart15extractCharSizeEt+0x26>
+ 2278: 2380 movs r3, #128 ; 0x80
+ return UART_CHAR_SIZE_5_BITS;
+ 227a: 3802 subs r0, #2
+ switch(config & HARDSER_DATA_MASK)
+ 227c: 005b lsls r3, r3, #1
+ 227e: 4299 cmp r1, r3
+ 2280: d000 beq.n 2284 <_ZN4Uart15extractCharSizeEt+0x26>
+
+ case HARDSER_DATA_8:
+ default:
+ return UART_CHAR_SIZE_8_BITS;
+ 2282: 2000 movs r0, #0
+
+ }
+}
+ 2284: 4770 bx lr
+
+00002286 <_ZN4Uart13extractParityEt>:
+
+SercomParityMode Uart::extractParity(uint16_t config)
+{
+ switch(config & HARDSER_PARITY_MASK)
+ 2286: 200f movs r0, #15
+ 2288: 4001 ands r1, r0
+ case HARDSER_PARITY_NONE:
+ default:
+ return SERCOM_NO_PARITY;
+
+ case HARDSER_PARITY_EVEN:
+ return SERCOM_EVEN_PARITY;
+ 228a: 2000 movs r0, #0
+ switch(config & HARDSER_PARITY_MASK)
+ 228c: 2901 cmp r1, #1
+ 228e: d003 beq.n 2298 <_ZN4Uart13extractParityEt+0x12>
+ return SERCOM_NO_PARITY;
+ 2290: 3902 subs r1, #2
+ 2292: 1e48 subs r0, r1, #1
+ 2294: 4181 sbcs r1, r0
+ 2296: 1c48 adds r0, r1, #1
+
+ case HARDSER_PARITY_ODD:
+ return SERCOM_ODD_PARITY;
+ }
+}
+ 2298: 4770 bx lr
+ ...
+
+0000229c <_ZN4Uart5beginEmt>:
+ pinPeripheral(uc_pinRX, g_APinDescription[uc_pinRX].ulPinType);
+ 229c: 2389 movs r3, #137 ; 0x89
+{
+ 229e: b5f0 push {r4, r5, r6, r7, lr}
+ pinPeripheral(uc_pinRX, g_APinDescription[uc_pinRX].ulPinType);
+ 22a0: 2618 movs r6, #24
+{
+ 22a2: b085 sub sp, #20
+ 22a4: 9102 str r1, [sp, #8]
+ pinPeripheral(uc_pinRX, g_APinDescription[uc_pinRX].ulPinType);
+ 22a6: 009b lsls r3, r3, #2
+{
+ 22a8: 0004 movs r4, r0
+ pinPeripheral(uc_pinRX, g_APinDescription[uc_pinRX].ulPinType);
+ 22aa: 5cc0 ldrb r0, [r0, r3]
+ 22ac: 0033 movs r3, r6
+ 22ae: 2108 movs r1, #8
+ 22b0: 4343 muls r3, r0
+ 22b2: 4d32 ldr r5, [pc, #200] ; (237c <_ZN4Uart5beginEmt+0xe0>)
+{
+ 22b4: 0017 movs r7, r2
+ pinPeripheral(uc_pinRX, g_APinDescription[uc_pinRX].ulPinType);
+ 22b6: 18eb adds r3, r5, r3
+ 22b8: 5659 ldrsb r1, [r3, r1]
+ 22ba: f7ff fdd9 bl 1e70 <pinPeripheral>
+ pinPeripheral(uc_pinTX, g_APinDescription[uc_pinTX].ulPinType);
+ 22be: 4b30 ldr r3, [pc, #192] ; (2380 <_ZN4Uart5beginEmt+0xe4>)
+ 22c0: 2108 movs r1, #8
+ 22c2: 5ce0 ldrb r0, [r4, r3]
+ 22c4: 0033 movs r3, r6
+ 22c6: 4343 muls r3, r0
+ 22c8: 18eb adds r3, r5, r3
+ 22ca: 5659 ldrsb r1, [r3, r1]
+ 22cc: f7ff fdd0 bl 1e70 <pinPeripheral>
+ if (uc_padTX == UART_TX_RTS_CTS_PAD_0_2_3) {
+ 22d0: 4b2c ldr r3, [pc, #176] ; (2384 <_ZN4Uart5beginEmt+0xe8>)
+ 22d2: 5ce2 ldrb r2, [r4, r3]
+ 22d4: 9303 str r3, [sp, #12]
+ 22d6: 2a02 cmp r2, #2
+ 22d8: d109 bne.n 22ee <_ZN4Uart5beginEmt+0x52>
+ if (uc_pinCTS != NO_CTS_PIN) {
+ 22da: 3311 adds r3, #17
+ 22dc: 5ce0 ldrb r0, [r4, r3]
+ 22de: 28ff cmp r0, #255 ; 0xff
+ 22e0: d005 beq.n 22ee <_ZN4Uart5beginEmt+0x52>
+ pinPeripheral(uc_pinCTS, g_APinDescription[uc_pinCTS].ulPinType);
+ 22e2: 2108 movs r1, #8
+ 22e4: 4346 muls r6, r0
+ 22e6: 19ae adds r6, r5, r6
+ 22e8: 5671 ldrsb r1, [r6, r1]
+ 22ea: f7ff fdc1 bl 1e70 <pinPeripheral>
+ if (uc_pinRTS != NO_RTS_PIN) {
+ 22ee: 268a movs r6, #138 ; 0x8a
+ 22f0: 00b6 lsls r6, r6, #2
+ 22f2: 5da0 ldrb r0, [r4, r6]
+ 22f4: 28ff cmp r0, #255 ; 0xff
+ 22f6: d019 beq.n 232c <_ZN4Uart5beginEmt+0x90>
+ pinMode(uc_pinRTS, OUTPUT);
+ 22f8: 2101 movs r1, #1
+ 22fa: f7ff fd41 bl 1d80 <pinMode>
+ EPortType rtsPort = g_APinDescription[uc_pinRTS].ulPort;
+ 22fe: 2218 movs r2, #24
+ 2300: 5da3 ldrb r3, [r4, r6]
+ pul_outsetRTS = &PORT->Group[rtsPort].OUTSET.reg;
+ 2302: 4921 ldr r1, [pc, #132] ; (2388 <_ZN4Uart5beginEmt+0xec>)
+ EPortType rtsPort = g_APinDescription[uc_pinRTS].ulPort;
+ 2304: 435a muls r2, r3
+ pul_outsetRTS = &PORT->Group[rtsPort].OUTSET.reg;
+ 2306: 56ab ldrsb r3, [r5, r2]
+ ul_pinMaskRTS = (1ul << g_APinDescription[uc_pinRTS].ulPin);
+ 2308: 18ad adds r5, r5, r2
+ pul_outsetRTS = &PORT->Group[rtsPort].OUTSET.reg;
+ 230a: 01db lsls r3, r3, #7
+ 230c: 1858 adds r0, r3, r1
+ 230e: 218b movs r1, #139 ; 0x8b
+ 2310: 0089 lsls r1, r1, #2
+ 2312: 5060 str r0, [r4, r1]
+ pul_outclrRTS = &PORT->Group[rtsPort].OUTCLR.reg;
+ 2314: 491d ldr r1, [pc, #116] ; (238c <_ZN4Uart5beginEmt+0xf0>)
+ ul_pinMaskRTS = (1ul << g_APinDescription[uc_pinRTS].ulPin);
+ 2316: 2201 movs r2, #1
+ pul_outclrRTS = &PORT->Group[rtsPort].OUTCLR.reg;
+ 2318: 185b adds r3, r3, r1
+ 231a: 218c movs r1, #140 ; 0x8c
+ 231c: 0089 lsls r1, r1, #2
+ 231e: 5063 str r3, [r4, r1]
+ ul_pinMaskRTS = (1ul << g_APinDescription[uc_pinRTS].ulPin);
+ 2320: 6869 ldr r1, [r5, #4]
+ 2322: 408a lsls r2, r1
+ 2324: 218d movs r1, #141 ; 0x8d
+ 2326: 0089 lsls r1, r1, #2
+ 2328: 5062 str r2, [r4, r1]
+ *pul_outclrRTS = ul_pinMaskRTS;
+ 232a: 601a str r2, [r3, #0]
+ sercom->initUART(UART_INT_CLOCK, SAMPLE_RATE_x16, baudrate);
+ 232c: 2201 movs r2, #1
+ 232e: 9b02 ldr r3, [sp, #8]
+ 2330: 0011 movs r1, r2
+ 2332: 6920 ldr r0, [r4, #16]
+ 2334: f7ff ff34 bl 21a0 <_ZN6SERCOM8initUARTE14SercomUartMode20SercomUartSampleRatem>
+ sercom->initFrame(extractCharSize(config), LSB_FIRST, extractParity(config), extractNbStopBit(config));
+ 2338: 0039 movs r1, r7
+ 233a: 0020 movs r0, r4
+ 233c: f7ff ff8f bl 225e <_ZN4Uart15extractCharSizeEt>
+ 2340: 0039 movs r1, r7
+ 2342: 0005 movs r5, r0
+ 2344: 0020 movs r0, r4
+ 2346: f7ff ff9e bl 2286 <_ZN4Uart13extractParityEt>
+ 234a: 0039 movs r1, r7
+ 234c: 0006 movs r6, r0
+ 234e: 0020 movs r0, r4
+ 2350: f7ff ff7f bl 2252 <_ZN4Uart16extractNbStopBitEt>
+ 2354: 0033 movs r3, r6
+ 2356: 9000 str r0, [sp, #0]
+ 2358: 0029 movs r1, r5
+ 235a: 6920 ldr r0, [r4, #16]
+ 235c: 2201 movs r2, #1
+ 235e: f7ff fe49 bl 1ff4 <_ZN6SERCOM9initFrameE18SercomUartCharSize15SercomDataOrder16SercomParityMode19SercomNumberStopBit>
+ sercom->initPads(uc_padTX, uc_padRX);
+ 2362: 4b0b ldr r3, [pc, #44] ; (2390 <_ZN4Uart5beginEmt+0xf4>)
+ 2364: 6920 ldr r0, [r4, #16]
+ 2366: 5ce2 ldrb r2, [r4, r3]
+ 2368: 9b03 ldr r3, [sp, #12]
+ 236a: 5ce1 ldrb r1, [r4, r3]
+ 236c: f7ff fe5c bl 2028 <_ZN6SERCOM8initPadsE15SercomUartTXPad11SercomRXPad>
+ sercom->enableUART();
+ 2370: 6920 ldr r0, [r4, #16]
+ 2372: f7ff fe77 bl 2064 <_ZN6SERCOM10enableUARTEv>
+}
+ 2376: b005 add sp, #20
+ 2378: bdf0 pop {r4, r5, r6, r7, pc}
+ 237a: 46c0 nop ; (mov r8, r8)
+ 237c: 00002ab4 .word 0x00002ab4
+ 2380: 00000225 .word 0x00000225
+ 2384: 00000227 .word 0x00000227
+ 2388: 41004418 .word 0x41004418
+ 238c: 41004414 .word 0x41004414
+ 2390: 00000226 .word 0x00000226
+
+00002394 <_ZN11RingBufferNILi256EEC1Ev>:
+ memset( _aucBuffer, 0, N ) ;
+ 2394: 2280 movs r2, #128 ; 0x80
+RingBufferN<N>::RingBufferN( void )
+ 2396: b510 push {r4, lr}
+ 2398: 0004 movs r4, r0
+ memset( _aucBuffer, 0, N ) ;
+ 239a: 0052 lsls r2, r2, #1
+ 239c: 2100 movs r1, #0
+ 239e: f000 fa44 bl 282a <memset>
+ _iHead = 0;
+ 23a2: 0023 movs r3, r4
+ 23a4: 2200 movs r2, #0
+ 23a6: 33fc adds r3, #252 ; 0xfc
+ 23a8: 605a str r2, [r3, #4]
+}
+ 23aa: 0020 movs r0, r4
+ _iTail = 0;
+ 23ac: 609a str r2, [r3, #8]
+}
+ 23ae: bd10 pop {r4, pc}
+
+000023b0 <_ZN4UartC1EP6SERCOMhh11SercomRXPad15SercomUartTXPad>:
+Uart::Uart(SERCOM *_s, uint8_t _pinRX, uint8_t _pinTX, SercomRXPad _padRX, SercomUartTXPad _padTX) :
+ 23b0: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr}
+ 23b2: 001d movs r5, r3
+ 23b4: ab08 add r3, sp, #32
+ 23b6: 781b ldrb r3, [r3, #0]
+ 23b8: 0004 movs r4, r0
+ 23ba: 9300 str r3, [sp, #0]
+ 23bc: ab09 add r3, sp, #36 ; 0x24
+ 23be: 781b ldrb r3, [r3, #0]
+ 23c0: 0016 movs r6, r2
+ 23c2: 9301 str r3, [sp, #4]
+ 23c4: 2300 movs r3, #0
+ 23c6: 6043 str r3, [r0, #4]
+ 23c8: 23fa movs r3, #250 ; 0xfa
+ 23ca: 009b lsls r3, r3, #2
+ 23cc: 6083 str r3, [r0, #8]
+Uart::Uart(SERCOM *_s, uint8_t _pinRX, uint8_t _pinTX, SercomRXPad _padRX, SercomUartTXPad _padTX, uint8_t _pinRTS, uint8_t _pinCTS)
+ 23ce: 4b11 ldr r3, [pc, #68] ; (2414 <_ZN4UartC1EP6SERCOMhh11SercomRXPad15SercomUartTXPad+0x64>)
+Uart::Uart(SERCOM *_s, uint8_t _pinRX, uint8_t _pinTX, SercomRXPad _padRX, SercomUartTXPad _padTX) :
+ 23d0: 000f movs r7, r1
+Uart::Uart(SERCOM *_s, uint8_t _pinRX, uint8_t _pinTX, SercomRXPad _padRX, SercomUartTXPad _padTX, uint8_t _pinRTS, uint8_t _pinCTS)
+ 23d2: 3308 adds r3, #8
+ 23d4: 6003 str r3, [r0, #0]
+ 23d6: 3014 adds r0, #20
+ 23d8: f7ff ffdc bl 2394 <_ZN11RingBufferNILi256EEC1Ev>
+ 23dc: 0020 movs r0, r4
+ 23de: 301d adds r0, #29
+ 23e0: 30ff adds r0, #255 ; 0xff
+ 23e2: f7ff ffd7 bl 2394 <_ZN11RingBufferNILi256EEC1Ev>
+ uc_pinRX = _pinRX;
+ 23e6: 2389 movs r3, #137 ; 0x89
+ uc_padRX = _padRX ;
+ 23e8: 466a mov r2, sp
+ uc_pinRX = _pinRX;
+ 23ea: 009b lsls r3, r3, #2
+ sercom = _s;
+ 23ec: 6127 str r7, [r4, #16]
+ uc_pinRX = _pinRX;
+ 23ee: 54e6 strb r6, [r4, r3]
+ uc_pinTX = _pinTX;
+ 23f0: 4b09 ldr r3, [pc, #36] ; (2418 <_ZN4UartC1EP6SERCOMhh11SercomRXPad15SercomUartTXPad+0x68>)
+ uc_padRX = _padRX ;
+ 23f2: 7812 ldrb r2, [r2, #0]
+ uc_pinTX = _pinTX;
+ 23f4: 54e5 strb r5, [r4, r3]
+ uc_padRX = _padRX ;
+ 23f6: 4b09 ldr r3, [pc, #36] ; (241c <_ZN4UartC1EP6SERCOMhh11SercomRXPad15SercomUartTXPad+0x6c>)
+}
+ 23f8: 0020 movs r0, r4
+ uc_padRX = _padRX ;
+ 23fa: 54e2 strb r2, [r4, r3]
+ uc_padTX = _padTX;
+ 23fc: 466a mov r2, sp
+ 23fe: 4b08 ldr r3, [pc, #32] ; (2420 <_ZN4UartC1EP6SERCOMhh11SercomRXPad15SercomUartTXPad+0x70>)
+ 2400: 7912 ldrb r2, [r2, #4]
+ 2402: 54e2 strb r2, [r4, r3]
+ uc_pinRTS = _pinRTS;
+ 2404: 228a movs r2, #138 ; 0x8a
+ 2406: 3b29 subs r3, #41 ; 0x29
+ 2408: 3bff subs r3, #255 ; 0xff
+ 240a: 0092 lsls r2, r2, #2
+ 240c: 54a3 strb r3, [r4, r2]
+ uc_pinCTS = _pinCTS;
+ 240e: 3210 adds r2, #16
+ 2410: 54a3 strb r3, [r4, r2]
+}
+ 2412: bdfe pop {r1, r2, r3, r4, r5, r6, r7, pc}
+ 2414: 00002f04 .word 0x00002f04
+ 2418: 00000225 .word 0x00000225
+ 241c: 00000226 .word 0x00000226
+ 2420: 00000227 .word 0x00000227
+
+00002424 <_ZN11RingBufferNILi256EE9availableEv>:
+ int delta = _iHead - _iTail;
+ 2424: 0003 movs r3, r0
+ 2426: 33fc adds r3, #252 ; 0xfc
+ 2428: 6858 ldr r0, [r3, #4]
+ 242a: 689b ldr r3, [r3, #8]
+ 242c: 1ac0 subs r0, r0, r3
+ if(delta < 0)
+ 242e: d501 bpl.n 2434 <_ZN11RingBufferNILi256EE9availableEv+0x10>
+ return N + delta;
+ 2430: 3001 adds r0, #1
+ 2432: 30ff adds r0, #255 ; 0xff
+}
+ 2434: 4770 bx lr
+
+00002436 <_ZN4Uart5flushEv>:
+{
+ 2436: b510 push {r4, lr}
+ 2438: 0004 movs r4, r0
+ while(txBuffer.available()); // wait until TX buffer is empty
+ 243a: 0020 movs r0, r4
+ 243c: 301d adds r0, #29
+ 243e: 30ff adds r0, #255 ; 0xff
+ 2440: f7ff fff0 bl 2424 <_ZN11RingBufferNILi256EE9availableEv>
+ 2444: 2800 cmp r0, #0
+ 2446: d1f8 bne.n 243a <_ZN4Uart5flushEv+0x4>
+ sercom->flushUART();
+ 2448: 6920 ldr r0, [r4, #16]
+ 244a: f7ff fe14 bl 2076 <_ZN6SERCOM9flushUARTEv>
+}
+ 244e: bd10 pop {r4, pc}
+
+00002450 <_ZN4Uart9availableEv>:
+{
+ 2450: b510 push {r4, lr}
+ return rxBuffer.available();
+ 2452: 3014 adds r0, #20
+ 2454: f7ff ffe6 bl 2424 <_ZN11RingBufferNILi256EE9availableEv>
+}
+ 2458: bd10 pop {r4, pc}
+
+0000245a <_ZN11RingBufferNILi256EE17availableForStoreEv>:
+ if (_iHead >= _iTail)
+ 245a: 0003 movs r3, r0
+ 245c: 33fc adds r3, #252 ; 0xfc
+ 245e: 6859 ldr r1, [r3, #4]
+ 2460: 689a ldr r2, [r3, #8]
+ 2462: 4291 cmp r1, r2
+ 2464: db04 blt.n 2470 <_ZN11RingBufferNILi256EE17availableForStoreEv+0x16>
+ return N - 1 - _iHead + _iTail;
+ 2466: 685a ldr r2, [r3, #4]
+ 2468: 6898 ldr r0, [r3, #8]
+ 246a: 1a80 subs r0, r0, r2
+ 246c: 30ff adds r0, #255 ; 0xff
+}
+ 246e: 4770 bx lr
+ return _iTail - _iHead - 1;
+ 2470: 6898 ldr r0, [r3, #8]
+ 2472: 685b ldr r3, [r3, #4]
+ 2474: 1ac0 subs r0, r0, r3
+ 2476: 3801 subs r0, #1
+ 2478: e7f9 b.n 246e <_ZN11RingBufferNILi256EE17availableForStoreEv+0x14>
+
+0000247a <_ZN4Uart17availableForWriteEv>:
+{
+ 247a: b510 push {r4, lr}
+ return txBuffer.availableForStore();
+ 247c: 301d adds r0, #29
+ 247e: 30ff adds r0, #255 ; 0xff
+ 2480: f7ff ffeb bl 245a <_ZN11RingBufferNILi256EE17availableForStoreEv>
+}
+ 2484: bd10 pop {r4, pc}
+
+00002486 <_ZN4Uart10IrqHandlerEv>:
+{
+ 2486: b510 push {r4, lr}
+ 2488: 0004 movs r4, r0
+ if (sercom->isFrameErrorUART()) {
+ 248a: 6900 ldr r0, [r0, #16]
+ 248c: f7ff fe0f bl 20ae <_ZN6SERCOM16isFrameErrorUARTEv>
+ 2490: 2800 cmp r0, #0
+ 2492: d005 beq.n 24a0 <_ZN4Uart10IrqHandlerEv+0x1a>
+ sercom->readDataUART();
+ 2494: 6920 ldr r0, [r4, #16]
+ 2496: f7ff fe1a bl 20ce <_ZN6SERCOM12readDataUARTEv>
+ sercom->clearFrameErrorUART();
+ 249a: 6920 ldr r0, [r4, #16]
+ 249c: f7ff fe0c bl 20b8 <_ZN6SERCOM19clearFrameErrorUARTEv>
+ if (sercom->availableDataUART()) {
+ 24a0: 6920 ldr r0, [r4, #16]
+ 24a2: f7ff fdf4 bl 208e <_ZN6SERCOM17availableDataUARTEv>
+ 24a6: 2800 cmp r0, #0
+ 24a8: d020 beq.n 24ec <_ZN4Uart10IrqHandlerEv+0x66>
+ rxBuffer.store_char(sercom->readDataUART());
+ 24aa: 6920 ldr r0, [r4, #16]
+ 24ac: f7ff fe0f bl 20ce <_ZN6SERCOM12readDataUARTEv>
+ int i = nextIndex(_iHead);
+ 24b0: 0022 movs r2, r4
+ 24b2: 32fc adds r2, #252 ; 0xfc
+ 24b4: 6993 ldr r3, [r2, #24]
+ if ( i != _iTail )
+ 24b6: 69d1 ldr r1, [r2, #28]
+ return (uint32_t)(index + 1) % N;
+ 24b8: 3301 adds r3, #1
+ 24ba: b2db uxtb r3, r3
+ if ( i != _iTail )
+ 24bc: 428b cmp r3, r1
+ 24be: d003 beq.n 24c8 <_ZN4Uart10IrqHandlerEv+0x42>
+ _aucBuffer[_iHead] = c ;
+ 24c0: 6991 ldr r1, [r2, #24]
+ 24c2: 1861 adds r1, r4, r1
+ 24c4: 7508 strb r0, [r1, #20]
+ _iHead = i ;
+ 24c6: 6193 str r3, [r2, #24]
+ if (uc_pinRTS != NO_RTS_PIN) {
+ 24c8: 238a movs r3, #138 ; 0x8a
+ 24ca: 009b lsls r3, r3, #2
+ 24cc: 5ce3 ldrb r3, [r4, r3]
+ 24ce: 2bff cmp r3, #255 ; 0xff
+ 24d0: d00c beq.n 24ec <_ZN4Uart10IrqHandlerEv+0x66>
+ rxBuffer.store_char(sercom->readDataUART());
+ 24d2: 0020 movs r0, r4
+ 24d4: 3014 adds r0, #20
+ if (rxBuffer.availableForStore() < RTS_RX_THRESHOLD) {
+ 24d6: f7ff ffc0 bl 245a <_ZN11RingBufferNILi256EE17availableForStoreEv>
+ 24da: 2809 cmp r0, #9
+ 24dc: dc06 bgt.n 24ec <_ZN4Uart10IrqHandlerEv+0x66>
+ *pul_outsetRTS = ul_pinMaskRTS;
+ 24de: 238b movs r3, #139 ; 0x8b
+ 24e0: 228d movs r2, #141 ; 0x8d
+ 24e2: 009b lsls r3, r3, #2
+ 24e4: 0092 lsls r2, r2, #2
+ 24e6: 58e3 ldr r3, [r4, r3]
+ 24e8: 58a2 ldr r2, [r4, r2]
+ 24ea: 601a str r2, [r3, #0]
+ if (sercom->isDataRegisterEmptyUART()) {
+ 24ec: 6920 ldr r0, [r4, #16]
+ 24ee: f7ff fde9 bl 20c4 <_ZN6SERCOM23isDataRegisterEmptyUARTEv>
+ 24f2: 2800 cmp r0, #0
+ 24f4: d01a beq.n 252c <_ZN4Uart10IrqHandlerEv+0xa6>
+ if (txBuffer.available()) {
+ 24f6: 0020 movs r0, r4
+ 24f8: 301d adds r0, #29
+ 24fa: 30ff adds r0, #255 ; 0xff
+ 24fc: f7ff ff92 bl 2424 <_ZN11RingBufferNILi256EE9availableEv>
+ 2500: 2800 cmp r0, #0
+ 2502: d022 beq.n 254a <_ZN4Uart10IrqHandlerEv+0xc4>
+ if(_iTail == _iHead)
+ 2504: 2386 movs r3, #134 ; 0x86
+ 2506: 009b lsls r3, r3, #2
+ 2508: 18e3 adds r3, r4, r3
+ 250a: 6899 ldr r1, [r3, #8]
+ 250c: 685a ldr r2, [r3, #4]
+ 250e: 4291 cmp r1, r2
+ 2510: d018 beq.n 2544 <_ZN4Uart10IrqHandlerEv+0xbe>
+ uint8_t value = _aucBuffer[_iTail];
+ 2512: 218e movs r1, #142 ; 0x8e
+ 2514: 689a ldr r2, [r3, #8]
+ 2516: 0049 lsls r1, r1, #1
+ 2518: 18a2 adds r2, r4, r2
+ 251a: 5c51 ldrb r1, [r2, r1]
+ _iTail = nextIndex(_iTail);
+ 251c: 689a ldr r2, [r3, #8]
+ return (uint32_t)(index + 1) % N;
+ 251e: 3201 adds r2, #1
+ 2520: b2d2 uxtb r2, r2
+ _iTail = nextIndex(_iTail);
+ 2522: 609a str r2, [r3, #8]
+ sercom->writeDataUART(data);
+ 2524: b2c9 uxtb r1, r1
+ 2526: 6920 ldr r0, [r4, #16]
+ 2528: f7ff fdd5 bl 20d6 <_ZN6SERCOM13writeDataUARTEh>
+ if (sercom->isUARTError()) {
+ 252c: 6920 ldr r0, [r4, #16]
+ 252e: f7ff fdb3 bl 2098 <_ZN6SERCOM11isUARTErrorEv>
+ 2532: 2800 cmp r0, #0
+ 2534: d005 beq.n 2542 <_ZN4Uart10IrqHandlerEv+0xbc>
+ sercom->acknowledgeUARTError();
+ 2536: 6920 ldr r0, [r4, #16]
+ 2538: f7ff fdb2 bl 20a0 <_ZN6SERCOM20acknowledgeUARTErrorEv>
+ sercom->clearStatusUART();
+ 253c: 6920 ldr r0, [r4, #16]
+ 253e: f7ff fda2 bl 2086 <_ZN6SERCOM15clearStatusUARTEv>
+}
+ 2542: bd10 pop {r4, pc}
+ return -1;
+ 2544: 2101 movs r1, #1
+ 2546: 4249 negs r1, r1
+ 2548: e7ec b.n 2524 <_ZN4Uart10IrqHandlerEv+0x9e>
+ sercom->disableDataRegisterEmptyInterruptUART();
+ 254a: 6920 ldr r0, [r4, #16]
+ 254c: f7ff fdcf bl 20ee <_ZN6SERCOM37disableDataRegisterEmptyInterruptUARTEv>
+ 2550: e7ec b.n 252c <_ZN4Uart10IrqHandlerEv+0xa6>
+ ...
+
+00002554 <_ZN4Uart5writeEh>:
+{
+ 2554: b570 push {r4, r5, r6, lr}
+ 2556: 0004 movs r4, r0
+ if (sercom->isDataRegisterEmptyUART() && txBuffer.available() == 0) {
+ 2558: 6900 ldr r0, [r0, #16]
+{
+ 255a: 000d movs r5, r1
+ if (sercom->isDataRegisterEmptyUART() && txBuffer.available() == 0) {
+ 255c: f7ff fdb2 bl 20c4 <_ZN6SERCOM23isDataRegisterEmptyUARTEv>
+ 2560: 2800 cmp r0, #0
+ 2562: d124 bne.n 25ae <_ZN4Uart5writeEh+0x5a>
+ return (uint32_t)(index + 1) % N;
+ 2564: 26ff movs r6, #255 ; 0xff
+}
+
+template <int N>
+bool RingBufferN<N>::isFull()
+{
+ return (nextIndex(_iHead) == _iTail);
+ 2566: 2386 movs r3, #134 ; 0x86
+ 2568: 009b lsls r3, r3, #2
+ 256a: 18e3 adds r3, r4, r3
+ 256c: 685a ldr r2, [r3, #4]
+ 256e: 6899 ldr r1, [r3, #8]
+ return (uint32_t)(index + 1) % N;
+ 2570: 3201 adds r2, #1
+ 2572: 4032 ands r2, r6
+ while(txBuffer.isFull()) {
+ 2574: 428a cmp r2, r1
+ 2576: d12f bne.n 25d8 <_ZN4Uart5writeEh+0x84>
+ __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
+ 2578: f3ef 8310 mrs r3, PRIMASK
+ if (interruptsEnabled) {
+ 257c: 07db lsls r3, r3, #31
+ 257e: d40d bmi.n 259c <_ZN4Uart5writeEh+0x48>
+ uint32_t exceptionNumber = (SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk);
+ 2580: 4b1e ldr r3, [pc, #120] ; (25fc <_ZN4Uart5writeEh+0xa8>)
+ 2582: 685b ldr r3, [r3, #4]
+ 2584: 05db lsls r3, r3, #23
+ 2586: 0ddb lsrs r3, r3, #23
+ if (exceptionNumber == 0 ||
+ 2588: d0ed beq.n 2566 <_ZN4Uart5writeEh+0x12>
+ NVIC_GetPriority((IRQn_Type)(exceptionNumber - 16)) > SERCOM_NVIC_PRIORITY) {
+ 258a: 3b10 subs r3, #16
+ 258c: b25b sxtb r3, r3
+ if ((int32_t)(IRQn) >= 0)
+ 258e: 2b00 cmp r3, #0
+ 2590: db19 blt.n 25c6 <_ZN4Uart5writeEh+0x72>
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ 2592: 089b lsrs r3, r3, #2
+ 2594: 33c0 adds r3, #192 ; 0xc0
+ 2596: 4a1a ldr r2, [pc, #104] ; (2600 <_ZN4Uart5writeEh+0xac>)
+ 2598: 009b lsls r3, r3, #2
+ 259a: 589b ldr r3, [r3, r2]
+ if (sercom->isDataRegisterEmptyUART()) {
+ 259c: 6920 ldr r0, [r4, #16]
+ 259e: f7ff fd91 bl 20c4 <_ZN6SERCOM23isDataRegisterEmptyUARTEv>
+ 25a2: 2800 cmp r0, #0
+ 25a4: d0df beq.n 2566 <_ZN4Uart5writeEh+0x12>
+ IrqHandler();
+ 25a6: 0020 movs r0, r4
+ 25a8: f7ff ff6d bl 2486 <_ZN4Uart10IrqHandlerEv>
+ 25ac: e7db b.n 2566 <_ZN4Uart5writeEh+0x12>
+ if (sercom->isDataRegisterEmptyUART() && txBuffer.available() == 0) {
+ 25ae: 0020 movs r0, r4
+ 25b0: 301d adds r0, #29
+ 25b2: 30ff adds r0, #255 ; 0xff
+ 25b4: f7ff ff36 bl 2424 <_ZN11RingBufferNILi256EE9availableEv>
+ 25b8: 2800 cmp r0, #0
+ 25ba: d1d3 bne.n 2564 <_ZN4Uart5writeEh+0x10>
+ sercom->writeDataUART(data);
+ 25bc: 0029 movs r1, r5
+ 25be: 6920 ldr r0, [r4, #16]
+ 25c0: f7ff fd89 bl 20d6 <_ZN6SERCOM13writeDataUARTEh>
+ return 1;
+ 25c4: e017 b.n 25f6 <_ZN4Uart5writeEh+0xa2>
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+ 25c6: 220f movs r2, #15
+ 25c8: 4013 ands r3, r2
+ 25ca: 3b08 subs r3, #8
+ 25cc: 089b lsrs r3, r3, #2
+ 25ce: 4a0d ldr r2, [pc, #52] ; (2604 <_ZN4Uart5writeEh+0xb0>)
+ 25d0: 009b lsls r3, r3, #2
+ 25d2: 189b adds r3, r3, r2
+ 25d4: 681b ldr r3, [r3, #0]
+ 25d6: e7e1 b.n 259c <_ZN4Uart5writeEh+0x48>
+ int i = nextIndex(_iHead);
+ 25d8: 685a ldr r2, [r3, #4]
+ return (uint32_t)(index + 1) % N;
+ 25da: 3201 adds r2, #1
+ 25dc: 4016 ands r6, r2
+ if ( i != _iTail )
+ 25de: 689a ldr r2, [r3, #8]
+ 25e0: 4296 cmp r6, r2
+ 25e2: d005 beq.n 25f0 <_ZN4Uart5writeEh+0x9c>
+ _aucBuffer[_iHead] = c ;
+ 25e4: 218e movs r1, #142 ; 0x8e
+ 25e6: 685a ldr r2, [r3, #4]
+ 25e8: 0049 lsls r1, r1, #1
+ 25ea: 18a2 adds r2, r4, r2
+ 25ec: 5455 strb r5, [r2, r1]
+ _iHead = i ;
+ 25ee: 605e str r6, [r3, #4]
+ sercom->enableDataRegisterEmptyInterruptUART();
+ 25f0: 6920 ldr r0, [r4, #16]
+ 25f2: f7ff fd78 bl 20e6 <_ZN6SERCOM36enableDataRegisterEmptyInterruptUARTEv>
+}
+ 25f6: 2001 movs r0, #1
+ 25f8: bd70 pop {r4, r5, r6, pc}
+ 25fa: 46c0 nop ; (mov r8, r8)
+ 25fc: e000ed00 .word 0xe000ed00
+ 2600: e000e100 .word 0xe000e100
+ 2604: e000ed1c .word 0xe000ed1c
+
+00002608 <_ZN4Uart4readEv>:
+ if(_iTail == _iHead)
+ 2608: 0003 movs r3, r0
+ 260a: 33fc adds r3, #252 ; 0xfc
+ 260c: 69d9 ldr r1, [r3, #28]
+ 260e: 699a ldr r2, [r3, #24]
+{
+ 2610: b570 push {r4, r5, r6, lr}
+ 2612: 0004 movs r4, r0
+ 2614: 4291 cmp r1, r2
+ 2616: d01a beq.n 264e <_ZN4Uart4readEv+0x46>
+ uint8_t value = _aucBuffer[_iTail];
+ 2618: 69da ldr r2, [r3, #28]
+ 261a: 1882 adds r2, r0, r2
+ 261c: 7d15 ldrb r5, [r2, #20]
+ _iTail = nextIndex(_iTail);
+ 261e: 69da ldr r2, [r3, #28]
+ return (uint32_t)(index + 1) % N;
+ 2620: 3201 adds r2, #1
+ 2622: b2d2 uxtb r2, r2
+ _iTail = nextIndex(_iTail);
+ 2624: 61da str r2, [r3, #28]
+ if (uc_pinRTS != NO_RTS_PIN) {
+ 2626: 238a movs r3, #138 ; 0x8a
+ 2628: 009b lsls r3, r3, #2
+ 262a: 5ce3 ldrb r3, [r4, r3]
+ 262c: 2bff cmp r3, #255 ; 0xff
+ 262e: d00c beq.n 264a <_ZN4Uart4readEv+0x42>
+ int c = rxBuffer.read_char();
+ 2630: 0020 movs r0, r4
+ 2632: 3014 adds r0, #20
+ if (rxBuffer.availableForStore() > RTS_RX_THRESHOLD) {
+ 2634: f7ff ff11 bl 245a <_ZN11RingBufferNILi256EE17availableForStoreEv>
+ 2638: 280a cmp r0, #10
+ 263a: dd06 ble.n 264a <_ZN4Uart4readEv+0x42>
+ *pul_outclrRTS = ul_pinMaskRTS;
+ 263c: 238c movs r3, #140 ; 0x8c
+ 263e: 228d movs r2, #141 ; 0x8d
+ 2640: 009b lsls r3, r3, #2
+ 2642: 0092 lsls r2, r2, #2
+ 2644: 58e3 ldr r3, [r4, r3]
+ 2646: 58a2 ldr r2, [r4, r2]
+ 2648: 601a str r2, [r3, #0]
+}
+ 264a: 0028 movs r0, r5
+ 264c: bd70 pop {r4, r5, r6, pc}
+ return -1;
+ 264e: 2501 movs r5, #1
+ 2650: 426d negs r5, r5
+ 2652: e7e8 b.n 2626 <_ZN4Uart4readEv+0x1e>
+
+00002654 <_ZN5Print5writeEPKhj>:
+
+// Public Methods //////////////////////////////////////////////////////////////
+
+/* default implementation: may be overridden */
+size_t Print::write(const uint8_t *buffer, size_t size)
+{
+ 2654: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr}
+ 2656: 0006 movs r6, r0
+ 2658: 000d movs r5, r1
+ 265a: 000c movs r4, r1
+ 265c: 188b adds r3, r1, r2
+ 265e: 9301 str r3, [sp, #4]
+ size_t n = 0;
+ while (size--) {
+ 2660: 9b01 ldr r3, [sp, #4]
+ 2662: 1b67 subs r7, r4, r5
+ 2664: 429c cmp r4, r3
+ 2666: d007 beq.n 2678 <_ZN5Print5writeEPKhj+0x24>
+ if (write(*buffer++)) n++;
+ 2668: 6833 ldr r3, [r6, #0]
+ 266a: 7821 ldrb r1, [r4, #0]
+ 266c: 681b ldr r3, [r3, #0]
+ 266e: 0030 movs r0, r6
+ 2670: 4798 blx r3
+ 2672: 3401 adds r4, #1
+ 2674: 2800 cmp r0, #0
+ 2676: d1f3 bne.n 2660 <_ZN5Print5writeEPKhj+0xc>
+ else break;
+ }
+ return n;
+}
+ 2678: 0038 movs r0, r7
+ 267a: bdfe pop {r1, r2, r3, r4, r5, r6, r7, pc}
+
+0000267c <__gnu_thumb1_case_uqi>:
+ 267c: b402 push {r1}
+ 267e: 4671 mov r1, lr
+ 2680: 0849 lsrs r1, r1, #1
+ 2682: 0049 lsls r1, r1, #1
+ 2684: 5c09 ldrb r1, [r1, r0]
+ 2686: 0049 lsls r1, r1, #1
+ 2688: 448e add lr, r1
+ 268a: bc02 pop {r1}
+ 268c: 4770 bx lr
+ 268e: 46c0 nop ; (mov r8, r8)
+
+00002690 <__udivsi3>:
+ 2690: 2200 movs r2, #0
+ 2692: 0843 lsrs r3, r0, #1
+ 2694: 428b cmp r3, r1
+ 2696: d374 bcc.n 2782 <__udivsi3+0xf2>
+ 2698: 0903 lsrs r3, r0, #4
+ 269a: 428b cmp r3, r1
+ 269c: d35f bcc.n 275e <__udivsi3+0xce>
+ 269e: 0a03 lsrs r3, r0, #8
+ 26a0: 428b cmp r3, r1
+ 26a2: d344 bcc.n 272e <__udivsi3+0x9e>
+ 26a4: 0b03 lsrs r3, r0, #12
+ 26a6: 428b cmp r3, r1
+ 26a8: d328 bcc.n 26fc <__udivsi3+0x6c>
+ 26aa: 0c03 lsrs r3, r0, #16
+ 26ac: 428b cmp r3, r1
+ 26ae: d30d bcc.n 26cc <__udivsi3+0x3c>
+ 26b0: 22ff movs r2, #255 ; 0xff
+ 26b2: 0209 lsls r1, r1, #8
+ 26b4: ba12 rev r2, r2
+ 26b6: 0c03 lsrs r3, r0, #16
+ 26b8: 428b cmp r3, r1
+ 26ba: d302 bcc.n 26c2 <__udivsi3+0x32>
+ 26bc: 1212 asrs r2, r2, #8
+ 26be: 0209 lsls r1, r1, #8
+ 26c0: d065 beq.n 278e <__udivsi3+0xfe>
+ 26c2: 0b03 lsrs r3, r0, #12
+ 26c4: 428b cmp r3, r1
+ 26c6: d319 bcc.n 26fc <__udivsi3+0x6c>
+ 26c8: e000 b.n 26cc <__udivsi3+0x3c>
+ 26ca: 0a09 lsrs r1, r1, #8
+ 26cc: 0bc3 lsrs r3, r0, #15
+ 26ce: 428b cmp r3, r1
+ 26d0: d301 bcc.n 26d6 <__udivsi3+0x46>
+ 26d2: 03cb lsls r3, r1, #15
+ 26d4: 1ac0 subs r0, r0, r3
+ 26d6: 4152 adcs r2, r2
+ 26d8: 0b83 lsrs r3, r0, #14
+ 26da: 428b cmp r3, r1
+ 26dc: d301 bcc.n 26e2 <__udivsi3+0x52>
+ 26de: 038b lsls r3, r1, #14
+ 26e0: 1ac0 subs r0, r0, r3
+ 26e2: 4152 adcs r2, r2
+ 26e4: 0b43 lsrs r3, r0, #13
+ 26e6: 428b cmp r3, r1
+ 26e8: d301 bcc.n 26ee <__udivsi3+0x5e>
+ 26ea: 034b lsls r3, r1, #13
+ 26ec: 1ac0 subs r0, r0, r3
+ 26ee: 4152 adcs r2, r2
+ 26f0: 0b03 lsrs r3, r0, #12
+ 26f2: 428b cmp r3, r1
+ 26f4: d301 bcc.n 26fa <__udivsi3+0x6a>
+ 26f6: 030b lsls r3, r1, #12
+ 26f8: 1ac0 subs r0, r0, r3
+ 26fa: 4152 adcs r2, r2
+ 26fc: 0ac3 lsrs r3, r0, #11
+ 26fe: 428b cmp r3, r1
+ 2700: d301 bcc.n 2706 <__udivsi3+0x76>
+ 2702: 02cb lsls r3, r1, #11
+ 2704: 1ac0 subs r0, r0, r3
+ 2706: 4152 adcs r2, r2
+ 2708: 0a83 lsrs r3, r0, #10
+ 270a: 428b cmp r3, r1
+ 270c: d301 bcc.n 2712 <__udivsi3+0x82>
+ 270e: 028b lsls r3, r1, #10
+ 2710: 1ac0 subs r0, r0, r3
+ 2712: 4152 adcs r2, r2
+ 2714: 0a43 lsrs r3, r0, #9
+ 2716: 428b cmp r3, r1
+ 2718: d301 bcc.n 271e <__udivsi3+0x8e>
+ 271a: 024b lsls r3, r1, #9
+ 271c: 1ac0 subs r0, r0, r3
+ 271e: 4152 adcs r2, r2
+ 2720: 0a03 lsrs r3, r0, #8
+ 2722: 428b cmp r3, r1
+ 2724: d301 bcc.n 272a <__udivsi3+0x9a>
+ 2726: 020b lsls r3, r1, #8
+ 2728: 1ac0 subs r0, r0, r3
+ 272a: 4152 adcs r2, r2
+ 272c: d2cd bcs.n 26ca <__udivsi3+0x3a>
+ 272e: 09c3 lsrs r3, r0, #7
+ 2730: 428b cmp r3, r1
+ 2732: d301 bcc.n 2738 <__udivsi3+0xa8>
+ 2734: 01cb lsls r3, r1, #7
+ 2736: 1ac0 subs r0, r0, r3
+ 2738: 4152 adcs r2, r2
+ 273a: 0983 lsrs r3, r0, #6
+ 273c: 428b cmp r3, r1
+ 273e: d301 bcc.n 2744 <__udivsi3+0xb4>
+ 2740: 018b lsls r3, r1, #6
+ 2742: 1ac0 subs r0, r0, r3
+ 2744: 4152 adcs r2, r2
+ 2746: 0943 lsrs r3, r0, #5
+ 2748: 428b cmp r3, r1
+ 274a: d301 bcc.n 2750 <__udivsi3+0xc0>
+ 274c: 014b lsls r3, r1, #5
+ 274e: 1ac0 subs r0, r0, r3
+ 2750: 4152 adcs r2, r2
+ 2752: 0903 lsrs r3, r0, #4
+ 2754: 428b cmp r3, r1
+ 2756: d301 bcc.n 275c <__udivsi3+0xcc>
+ 2758: 010b lsls r3, r1, #4
+ 275a: 1ac0 subs r0, r0, r3
+ 275c: 4152 adcs r2, r2
+ 275e: 08c3 lsrs r3, r0, #3
+ 2760: 428b cmp r3, r1
+ 2762: d301 bcc.n 2768 <__udivsi3+0xd8>
+ 2764: 00cb lsls r3, r1, #3
+ 2766: 1ac0 subs r0, r0, r3
+ 2768: 4152 adcs r2, r2
+ 276a: 0883 lsrs r3, r0, #2
+ 276c: 428b cmp r3, r1
+ 276e: d301 bcc.n 2774 <__udivsi3+0xe4>
+ 2770: 008b lsls r3, r1, #2
+ 2772: 1ac0 subs r0, r0, r3
+ 2774: 4152 adcs r2, r2
+ 2776: 0843 lsrs r3, r0, #1
+ 2778: 428b cmp r3, r1
+ 277a: d301 bcc.n 2780 <__udivsi3+0xf0>
+ 277c: 004b lsls r3, r1, #1
+ 277e: 1ac0 subs r0, r0, r3
+ 2780: 4152 adcs r2, r2
+ 2782: 1a41 subs r1, r0, r1
+ 2784: d200 bcs.n 2788 <__udivsi3+0xf8>
+ 2786: 4601 mov r1, r0
+ 2788: 4152 adcs r2, r2
+ 278a: 4610 mov r0, r2
+ 278c: 4770 bx lr
+ 278e: e7ff b.n 2790 <__udivsi3+0x100>
+ 2790: b501 push {r0, lr}
+ 2792: 2000 movs r0, #0
+ 2794: f000 f806 bl 27a4 <__aeabi_idiv0>
+ 2798: bd02 pop {r1, pc}
+ 279a: 46c0 nop ; (mov r8, r8)
+
+0000279c <__aeabi_uidivmod>:
+ 279c: 2900 cmp r1, #0
+ 279e: d0f7 beq.n 2790 <__udivsi3+0x100>
+ 27a0: e776 b.n 2690 <__udivsi3>
+ 27a2: 4770 bx lr
+
+000027a4 <__aeabi_idiv0>:
+ 27a4: 4770 bx lr
+ 27a6: 46c0 nop ; (mov r8, r8)
+
+000027a8 <__libc_init_array>:
+ 27a8: b570 push {r4, r5, r6, lr}
+ 27aa: 2600 movs r6, #0
+ 27ac: 4d0c ldr r5, [pc, #48] ; (27e0 <__libc_init_array+0x38>)
+ 27ae: 4c0d ldr r4, [pc, #52] ; (27e4 <__libc_init_array+0x3c>)
+ 27b0: 1b64 subs r4, r4, r5
+ 27b2: 10a4 asrs r4, r4, #2
+ 27b4: 42a6 cmp r6, r4
+ 27b6: d109 bne.n 27cc <__libc_init_array+0x24>
+ 27b8: 2600 movs r6, #0
+ 27ba: f000 f911 bl 29e0 <_init>
+ 27be: 4d0a ldr r5, [pc, #40] ; (27e8 <__libc_init_array+0x40>)
+ 27c0: 4c0a ldr r4, [pc, #40] ; (27ec <__libc_init_array+0x44>)
+ 27c2: 1b64 subs r4, r4, r5
+ 27c4: 10a4 asrs r4, r4, #2
+ 27c6: 42a6 cmp r6, r4
+ 27c8: d105 bne.n 27d6 <__libc_init_array+0x2e>
+ 27ca: bd70 pop {r4, r5, r6, pc}
+ 27cc: 00b3 lsls r3, r6, #2
+ 27ce: 58eb ldr r3, [r5, r3]
+ 27d0: 4798 blx r3
+ 27d2: 3601 adds r6, #1
+ 27d4: e7ee b.n 27b4 <__libc_init_array+0xc>
+ 27d6: 00b3 lsls r3, r6, #2
+ 27d8: 58eb ldr r3, [r5, r3]
+ 27da: 4798 blx r3
+ 27dc: 3601 adds r6, #1
+ 27de: e7f2 b.n 27c6 <__libc_init_array+0x1e>
+ 27e0: 20000098 .word 0x20000098
+ 27e4: 20000098 .word 0x20000098
+ 27e8: 20000098 .word 0x20000098
+ 27ec: 200000a8 .word 0x200000a8
+
+000027f0 <malloc>:
+ 27f0: b510 push {r4, lr}
+ 27f2: 4b03 ldr r3, [pc, #12] ; (2800 <malloc+0x10>)
+ 27f4: 0001 movs r1, r0
+ 27f6: 6818 ldr r0, [r3, #0]
+ 27f8: f000 f86a bl 28d0 <_malloc_r>
+ 27fc: bd10 pop {r4, pc}
+ 27fe: 46c0 nop ; (mov r8, r8)
+ 2800: 20000034 .word 0x20000034
+
+00002804 <free>:
+ 2804: b510 push {r4, lr}
+ 2806: 4b03 ldr r3, [pc, #12] ; (2814 <free+0x10>)
+ 2808: 0001 movs r1, r0
+ 280a: 6818 ldr r0, [r3, #0]
+ 280c: f000 f816 bl 283c <_free_r>
+ 2810: bd10 pop {r4, pc}
+ 2812: 46c0 nop ; (mov r8, r8)
+ 2814: 20000034 .word 0x20000034
+
+00002818 <memcpy>:
+ 2818: 2300 movs r3, #0
+ 281a: b510 push {r4, lr}
+ 281c: 429a cmp r2, r3
+ 281e: d100 bne.n 2822 <memcpy+0xa>
+ 2820: bd10 pop {r4, pc}
+ 2822: 5ccc ldrb r4, [r1, r3]
+ 2824: 54c4 strb r4, [r0, r3]
+ 2826: 3301 adds r3, #1
+ 2828: e7f8 b.n 281c <memcpy+0x4>
+
+0000282a <memset>:
+ 282a: 0003 movs r3, r0
+ 282c: 1882 adds r2, r0, r2
+ 282e: 4293 cmp r3, r2
+ 2830: d100 bne.n 2834 <memset+0xa>
+ 2832: 4770 bx lr
+ 2834: 7019 strb r1, [r3, #0]
+ 2836: 3301 adds r3, #1
+ 2838: e7f9 b.n 282e <memset+0x4>
+ ...
+
+0000283c <_free_r>:
+ 283c: b570 push {r4, r5, r6, lr}
+ 283e: 0005 movs r5, r0
+ 2840: 2900 cmp r1, #0
+ 2842: d010 beq.n 2866 <_free_r+0x2a>
+ 2844: 1f0c subs r4, r1, #4
+ 2846: 6823 ldr r3, [r4, #0]
+ 2848: 2b00 cmp r3, #0
+ 284a: da00 bge.n 284e <_free_r+0x12>
+ 284c: 18e4 adds r4, r4, r3
+ 284e: 0028 movs r0, r5
+ 2850: f000 f8b5 bl 29be <__malloc_lock>
+ 2854: 4a1d ldr r2, [pc, #116] ; (28cc <_free_r+0x90>)
+ 2856: 6813 ldr r3, [r2, #0]
+ 2858: 2b00 cmp r3, #0
+ 285a: d105 bne.n 2868 <_free_r+0x2c>
+ 285c: 6063 str r3, [r4, #4]
+ 285e: 6014 str r4, [r2, #0]
+ 2860: 0028 movs r0, r5
+ 2862: f000 f8ad bl 29c0 <__malloc_unlock>
+ 2866: bd70 pop {r4, r5, r6, pc}
+ 2868: 42a3 cmp r3, r4
+ 286a: d909 bls.n 2880 <_free_r+0x44>
+ 286c: 6821 ldr r1, [r4, #0]
+ 286e: 1860 adds r0, r4, r1
+ 2870: 4283 cmp r3, r0
+ 2872: d1f3 bne.n 285c <_free_r+0x20>
+ 2874: 6818 ldr r0, [r3, #0]
+ 2876: 685b ldr r3, [r3, #4]
+ 2878: 1841 adds r1, r0, r1
+ 287a: 6021 str r1, [r4, #0]
+ 287c: e7ee b.n 285c <_free_r+0x20>
+ 287e: 0013 movs r3, r2
+ 2880: 685a ldr r2, [r3, #4]
+ 2882: 2a00 cmp r2, #0
+ 2884: d001 beq.n 288a <_free_r+0x4e>
+ 2886: 42a2 cmp r2, r4
+ 2888: d9f9 bls.n 287e <_free_r+0x42>
+ 288a: 6819 ldr r1, [r3, #0]
+ 288c: 1858 adds r0, r3, r1
+ 288e: 42a0 cmp r0, r4
+ 2890: d10b bne.n 28aa <_free_r+0x6e>
+ 2892: 6820 ldr r0, [r4, #0]
+ 2894: 1809 adds r1, r1, r0
+ 2896: 1858 adds r0, r3, r1
+ 2898: 6019 str r1, [r3, #0]
+ 289a: 4282 cmp r2, r0
+ 289c: d1e0 bne.n 2860 <_free_r+0x24>
+ 289e: 6810 ldr r0, [r2, #0]
+ 28a0: 6852 ldr r2, [r2, #4]
+ 28a2: 1841 adds r1, r0, r1
+ 28a4: 6019 str r1, [r3, #0]
+ 28a6: 605a str r2, [r3, #4]
+ 28a8: e7da b.n 2860 <_free_r+0x24>
+ 28aa: 42a0 cmp r0, r4
+ 28ac: d902 bls.n 28b4 <_free_r+0x78>
+ 28ae: 230c movs r3, #12
+ 28b0: 602b str r3, [r5, #0]
+ 28b2: e7d5 b.n 2860 <_free_r+0x24>
+ 28b4: 6821 ldr r1, [r4, #0]
+ 28b6: 1860 adds r0, r4, r1
+ 28b8: 4282 cmp r2, r0
+ 28ba: d103 bne.n 28c4 <_free_r+0x88>
+ 28bc: 6810 ldr r0, [r2, #0]
+ 28be: 6852 ldr r2, [r2, #4]
+ 28c0: 1841 adds r1, r0, r1
+ 28c2: 6021 str r1, [r4, #0]
+ 28c4: 6062 str r2, [r4, #4]
+ 28c6: 605c str r4, [r3, #4]
+ 28c8: e7ca b.n 2860 <_free_r+0x24>
+ 28ca: 46c0 nop ; (mov r8, r8)
+ 28cc: 20000b90 .word 0x20000b90
+
+000028d0 <_malloc_r>:
+ 28d0: 2303 movs r3, #3
+ 28d2: b570 push {r4, r5, r6, lr}
+ 28d4: 1ccd adds r5, r1, #3
+ 28d6: 439d bics r5, r3
+ 28d8: 3508 adds r5, #8
+ 28da: 0006 movs r6, r0
+ 28dc: 2d0c cmp r5, #12
+ 28de: d21e bcs.n 291e <_malloc_r+0x4e>
+ 28e0: 250c movs r5, #12
+ 28e2: 42a9 cmp r1, r5
+ 28e4: d81d bhi.n 2922 <_malloc_r+0x52>
+ 28e6: 0030 movs r0, r6
+ 28e8: f000 f869 bl 29be <__malloc_lock>
+ 28ec: 4a25 ldr r2, [pc, #148] ; (2984 <_malloc_r+0xb4>)
+ 28ee: 6814 ldr r4, [r2, #0]
+ 28f0: 0021 movs r1, r4
+ 28f2: 2900 cmp r1, #0
+ 28f4: d119 bne.n 292a <_malloc_r+0x5a>
+ 28f6: 4c24 ldr r4, [pc, #144] ; (2988 <_malloc_r+0xb8>)
+ 28f8: 6823 ldr r3, [r4, #0]
+ 28fa: 2b00 cmp r3, #0
+ 28fc: d103 bne.n 2906 <_malloc_r+0x36>
+ 28fe: 0030 movs r0, r6
+ 2900: f000 f844 bl 298c <_sbrk_r>
+ 2904: 6020 str r0, [r4, #0]
+ 2906: 0029 movs r1, r5
+ 2908: 0030 movs r0, r6
+ 290a: f000 f83f bl 298c <_sbrk_r>
+ 290e: 1c43 adds r3, r0, #1
+ 2910: d12c bne.n 296c <_malloc_r+0x9c>
+ 2912: 230c movs r3, #12
+ 2914: 0030 movs r0, r6
+ 2916: 6033 str r3, [r6, #0]
+ 2918: f000 f852 bl 29c0 <__malloc_unlock>
+ 291c: e003 b.n 2926 <_malloc_r+0x56>
+ 291e: 2d00 cmp r5, #0
+ 2920: dadf bge.n 28e2 <_malloc_r+0x12>
+ 2922: 230c movs r3, #12
+ 2924: 6033 str r3, [r6, #0]
+ 2926: 2000 movs r0, #0
+ 2928: bd70 pop {r4, r5, r6, pc}
+ 292a: 680b ldr r3, [r1, #0]
+ 292c: 1b5b subs r3, r3, r5
+ 292e: d41a bmi.n 2966 <_malloc_r+0x96>
+ 2930: 2b0b cmp r3, #11
+ 2932: d903 bls.n 293c <_malloc_r+0x6c>
+ 2934: 600b str r3, [r1, #0]
+ 2936: 18cc adds r4, r1, r3
+ 2938: 6025 str r5, [r4, #0]
+ 293a: e003 b.n 2944 <_malloc_r+0x74>
+ 293c: 428c cmp r4, r1
+ 293e: d10e bne.n 295e <_malloc_r+0x8e>
+ 2940: 6863 ldr r3, [r4, #4]
+ 2942: 6013 str r3, [r2, #0]
+ 2944: 0030 movs r0, r6
+ 2946: f000 f83b bl 29c0 <__malloc_unlock>
+ 294a: 0020 movs r0, r4
+ 294c: 2207 movs r2, #7
+ 294e: 300b adds r0, #11
+ 2950: 1d23 adds r3, r4, #4
+ 2952: 4390 bics r0, r2
+ 2954: 1ac3 subs r3, r0, r3
+ 2956: d0e7 beq.n 2928 <_malloc_r+0x58>
+ 2958: 425a negs r2, r3
+ 295a: 50e2 str r2, [r4, r3]
+ 295c: e7e4 b.n 2928 <_malloc_r+0x58>
+ 295e: 684b ldr r3, [r1, #4]
+ 2960: 6063 str r3, [r4, #4]
+ 2962: 000c movs r4, r1
+ 2964: e7ee b.n 2944 <_malloc_r+0x74>
+ 2966: 000c movs r4, r1
+ 2968: 6849 ldr r1, [r1, #4]
+ 296a: e7c2 b.n 28f2 <_malloc_r+0x22>
+ 296c: 2303 movs r3, #3
+ 296e: 1cc4 adds r4, r0, #3
+ 2970: 439c bics r4, r3
+ 2972: 42a0 cmp r0, r4
+ 2974: d0e0 beq.n 2938 <_malloc_r+0x68>
+ 2976: 1a21 subs r1, r4, r0
+ 2978: 0030 movs r0, r6
+ 297a: f000 f807 bl 298c <_sbrk_r>
+ 297e: 1c43 adds r3, r0, #1
+ 2980: d1da bne.n 2938 <_malloc_r+0x68>
+ 2982: e7c6 b.n 2912 <_malloc_r+0x42>
+ 2984: 20000b90 .word 0x20000b90
+ 2988: 20000b94 .word 0x20000b94
+
+0000298c <_sbrk_r>:
+ 298c: 2300 movs r3, #0
+ 298e: b570 push {r4, r5, r6, lr}
+ 2990: 4c06 ldr r4, [pc, #24] ; (29ac <_sbrk_r+0x20>)
+ 2992: 0005 movs r5, r0
+ 2994: 0008 movs r0, r1
+ 2996: 6023 str r3, [r4, #0]
+ 2998: f000 f814 bl 29c4 <_sbrk>
+ 299c: 1c43 adds r3, r0, #1
+ 299e: d103 bne.n 29a8 <_sbrk_r+0x1c>
+ 29a0: 6823 ldr r3, [r4, #0]
+ 29a2: 2b00 cmp r3, #0
+ 29a4: d000 beq.n 29a8 <_sbrk_r+0x1c>
+ 29a6: 602b str r3, [r5, #0]
+ 29a8: bd70 pop {r4, r5, r6, pc}
+ 29aa: 46c0 nop ; (mov r8, r8)
+ 29ac: 20000b9c .word 0x20000b9c
+
+000029b0 <strlen>:
+ 29b0: 2300 movs r3, #0
+ 29b2: 5cc2 ldrb r2, [r0, r3]
+ 29b4: 3301 adds r3, #1
+ 29b6: 2a00 cmp r2, #0
+ 29b8: d1fb bne.n 29b2 <strlen+0x2>
+ 29ba: 1e58 subs r0, r3, #1
+ 29bc: 4770 bx lr
+
+000029be <__malloc_lock>:
+ 29be: 4770 bx lr
+
+000029c0 <__malloc_unlock>:
+ 29c0: 4770 bx lr
+ ...
+
+000029c4 <_sbrk>:
+ 29c4: 4a04 ldr r2, [pc, #16] ; (29d8 <_sbrk+0x14>)
+ 29c6: 6813 ldr r3, [r2, #0]
+ 29c8: 2b00 cmp r3, #0
+ 29ca: d003 beq.n 29d4 <_sbrk+0x10>
+ 29cc: 1818 adds r0, r3, r0
+ 29ce: 6010 str r0, [r2, #0]
+ 29d0: 0018 movs r0, r3
+ 29d2: 4770 bx lr
+ 29d4: 4b01 ldr r3, [pc, #4] ; (29dc <_sbrk+0x18>)
+ 29d6: e7f9 b.n 29cc <_sbrk+0x8>
+ 29d8: 20000b98 .word 0x20000b98
+ 29dc: 20000ba0 .word 0x20000ba0
+
+000029e0 <_init>:
+ 29e0: b5f8 push {r3, r4, r5, r6, r7, lr}
+ 29e2: 46c0 nop ; (mov r8, r8)
+ 29e4: bcf8 pop {r3, r4, r5, r6, r7}
+ 29e6: bc08 pop {r3}
+ 29e8: 469e mov lr, r3
+ 29ea: 4770 bx lr
+
+000029ec <_fini>:
+ 29ec: b5f8 push {r3, r4, r5, r6, r7, lr}
+ 29ee: 46c0 nop ; (mov r8, r8)
+ 29f0: bcf8 pop {r3, r4, r5, r6, r7}
+ 29f2: bc08 pop {r3}
+ 29f4: 469e mov lr, r3
+ 29f6: 4770 bx lr
+
+000029f8 <_ZTV7Serial_>:
+ ...
+ 2a00: 0651 0000 0891 0000 064d 0000 0875 0000 Q.......M...u...
+ 2a10: 0855 0000 08cd 0000 08b1 0000 0883 0000 U...............
+ 2a20: 0665 0000 05ad 0000 079d 0000 05e5 0000 e...............
+ 2a30: 0639 0000 fff0 ffff 0000 0000 0845 0000 9...........E...
+ 2a40: 078d 0000 05b1 0000 063d 0000 0629 0000 ........=...)...
+
+00002a50 <_ZTV26DoubleBufferedEPOutHandler>:
+ ...
+ 2a58: 0c45 0000 0efb 0000 0ee3 0000 0ec1 0000 E...............
+ 2a68: 0aa9 0000 0aab 0000 0b99 0000 ............
+
+00002a74 <_ZL14STRING_PRODUCT>:
+ 2a74: 6954 796e 655a 6f72 0000 TinyZero..
+
+00002a7e <_ZL15STRING_LANGUAGE>:
+ 2a7e: 0304 0409 ....
+
+00002a82 <_ZL19STRING_MANUFACTURER>:
+ 2a82: 6954 796e 6943 6372 6975 7374 1200 TinyCircuits.
+
+00002a8f <_ZL21USB_DeviceDescriptorB>:
+ 2a8f: 0112 0200 02ef 4001 03eb 8009 0100 0201 .......@........
+ 2a9f: 0103 1a00 1a00 1b00 1b00 1c00 1c00 1d00 ................
+ 2aaf: 1d00 0000 0000 .....
+
+00002ab4 <g_APinDescription>:
+ 2ab4: 0000 0000 000b 0000 0002 0000 0004 0000 ................
+ 2ac4: 00ff ffff ffff 000b 0000 0000 000a 0000 ................
+ 2ad4: 0002 0000 0004 0000 00ff ffff ffff 000a ................
+ 2ae4: 0000 0000 000e 0000 0008 0000 0004 0000 ................
+ 2af4: 00ff ffff ffff 000e 0000 0000 0009 0000 ................
+ 2b04: 0004 0000 001c 0000 00ff 0001 0001 0009 ................
+ 2b14: 0000 0000 0008 0000 0004 0000 001c 0000 ................
+ 2b24: 00ff 0000 0000 0010 0000 0000 000f 0000 ................
+ 2b34: 0004 0000 001c 0000 00ff 0301 0301 000f ................
+ 2b44: 0000 0000 0014 0000 0005 0000 001c 0000 ................
+ 2b54: 00ff 0002 0002 0004 0000 0000 0015 0000 ................
+ 2b64: 0008 0000 0004 0000 00ff ffff ffff 0005 ................
+ 2b74: 0000 0000 0006 0000 0004 0000 001c 0000 ................
+ 2b84: 00ff 0100 0100 0006 0000 0000 0007 0000 ................
+ 2b94: 0004 0000 001c 0000 00ff 0101 0101 0007 ................
+ 2ba4: 0000 0000 0012 0000 0004 0000 001c 0000 ................
+ 2bb4: 00ff 0300 0300 0002 0000 0000 0010 0000 ................
+ 2bc4: 0002 0000 001c 0000 00ff 0200 0200 0000 ................
+ 2bd4: 0000 0000 0013 0000 0002 0000 001c 0000 ................
+ 2be4: 00ff 0003 0003 0003 0000 0000 0011 0000 ................
+ 2bf4: 0002 0000 000c 0000 00ff 0201 ffff 0001 ................
+ 2c04: 0000 0000 0002 0000 0001 0000 0002 0000 ................
+ 2c14: 0000 ffff ffff 0002 0001 0000 0008 0000 ................
+ 2c24: 0001 0000 0002 0000 0002 ffff ffff 0008 ................
+ 2c34: 0001 0000 0009 0000 0001 0000 0002 0000 ................
+ 2c44: 0003 ffff ffff 0009 0000 0000 0004 0000 ................
+ 2c54: 0001 0000 0002 0000 0004 ffff ffff 0004 ................
+ 2c64: 0000 0000 0005 0000 0001 0000 0002 0000 ................
+ 2c74: 0005 ffff ffff 0005 0001 0000 0002 0000 ................
+ 2c84: 0001 0000 0002 0000 000a ffff ffff 0002 ................
+ 2c94: 0000 0000 0016 0000 0002 0000 0004 0000 ................
+ 2ca4: 00ff ffff ffff 0006 0000 0000 0017 0000 ................
+ 2cb4: 0002 0000 0004 0000 00ff ffff ffff 0007 ................
+ 2cc4: 0000 0000 000c 0000 0003 0000 0004 0000 ................
+ 2cd4: 00ff ffff ffff 000c 0001 0000 000a 0000 ................
+ 2ce4: 0003 0000 0004 0000 00ff ffff ffff 000a ................
+ 2cf4: 0001 0000 000b 0000 0003 0000 0004 0000 ................
+ 2d04: 00ff ffff ffff 000b 0001 0000 0003 0000 ................
+ 2d14: 0008 0000 0004 0000 000b ffff ffff 0003 ................
+ 2d24: 0000 0000 001b 0000 0008 0000 0004 0000 ................
+ 2d34: 00ff ffff ffff 000f 0000 0000 001c 0000 ................
+ 2d44: 0006 0000 0000 0000 00ff ffff ffff 00ff ................
+ 2d54: 0000 0000 0018 0000 0006 0000 0000 0000 ................
+ 2d64: 00ff ffff ffff 00ff 0000 0000 0019 0000 ................
+ 2d74: 0006 0000 0000 0000 00ff ffff ffff 00ff ................
+ 2d84: 0001 0000 0016 0000 0003 0000 0000 0000 ................
+ 2d94: 00ff ffff ffff 0006 0001 0000 0017 0000 ................
+ 2da4: 0003 0000 0000 0000 00ff ffff ffff 0007 ................
+ 2db4: 0000 0000 0016 0000 0002 0000 0000 0000 ................
+ 2dc4: 00ff ffff ffff 00ff 0000 0000 0017 0000 ................
+ 2dd4: 0002 0000 0000 0000 00ff ffff ffff 00ff ................
+ 2de4: 0000 0000 0013 0000 0002 0000 0000 0000 ................
+ 2df4: 00ff ffff ffff 00ff 0000 0000 0010 0000 ................
+ 2e04: 0002 0000 0000 0000 00ff ffff ffff 00ff ................
+ 2e14: 0000 0000 0012 0000 0002 0000 0000 0000 ................
+ 2e24: 00ff ffff ffff 00ff 0000 0000 0011 0000 ................
+ 2e34: 0002 0000 0000 0000 00ff ffff ffff 00ff ................
+ 2e44: 0000 0000 000d 0000 0002 0000 000c 0000 ................
+ 2e54: 00ff 0001 ffff 000d 0000 0000 0015 0000 ................
+ 2e64: 0005 0000 000c 0000 00ff 0003 ffff 00ff ................
+ 2e74: 0000 0000 0006 0000 0004 0000 000c 0000 ................
+ 2e84: 00ff 0100 ffff 00ff 0000 0000 0007 0000 ................
+ 2e94: 0004 0000 000c 0000 00ff 0101 ffff 00ff ................
+ 2ea4: 0000 0000 0003 0000 0001 0000 0002 0000 ................
+ 2eb4: 0001 ffff ffff 00ff 0000 0000 0002 0000 ................
+ 2ec4: 0001 0000 0002 0000 0014 ffff ffff 0002 ................
+ 2ed4: 0000 0000 001e 0000 0008 0000 0004 0000 ................
+ 2ee4: 00ff ffff ffff 00ff 0000 0000 001f 0000 ................
+ 2ef4: 0008 0000 0004 0000 00ff ffff ffff 00ff ................
+
+00002f04 <_ZTV4Uart>:
+ ...
+ 2f0c: 2555 0000 2655 0000 247b 0000 2437 0000 U%..U&..{$..7$..
+ 2f1c: 2451 0000 2609 0000 2219 0000 2209 0000 Q$...&..."..."..
+ 2f2c: 229d 0000 2233 0000 2205 0000 ."..3"..."..
+
+00002f38 <__EH_FRAME_BEGIN__>:
+ 2f38: 0000 0000 ....
diff --git a/UsbReceive/UsbReceive/UsbReceive/Debug/UsbReceive.map b/UsbReceive/UsbReceive/UsbReceive/Debug/UsbReceive.map
new file mode 100644
index 0000000000000000000000000000000000000000..fbe259f90a655de607190d8878aa94ad8e846885
--- /dev/null
+++ b/UsbReceive/UsbReceive/UsbReceive/Debug/UsbReceive.map
@@ -0,0 +1,7881 @@
+Archive member included to satisfy reference by file (symbol)
+
+C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ (Reset_Handler)
+C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o) (SysTick_DefaultHandler)
+C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(hooks.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o) (yield)
+C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/crt0.o (main)
+C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o) (tickReset)
+C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o) (SystemInit)
+C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ Sketch.o (Stream::parseInt(LookaheadMode, char))
+C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ Sketch.o (Serial_::available())
+C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o) (PluggableUSB_::plug(PluggableUSBModule*))
+C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o) (USBDeviceClass::init())
+C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o) (init)
+C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ Sketch.o (analogWriteResolution)
+C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o) (pinMode)
+C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o) (pinPeripheral)
+C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o) (String::String(char const*))
+C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o) (g_apTCInstances)
+C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(dtostrf.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o) (dtostrf)
+C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(itoa.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o) (ltoa)
+C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(new.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o) (operator new(unsigned int))
+C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o) (SERCOM::SERCOM(Sercom*))
+C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o) (Uart::Uart(SERCOM*, unsigned char, unsigned char, SercomRXPad, SercomUartTXPad))
+C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o) (Print::write(unsigned char const*, unsigned int))
+C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(abi.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o) (__cxa_pure_virtual)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_thumb1_case_uqi.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o) (__gnu_thumb1_case_uqi)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_udivsi3.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o) (__aeabi_uidiv)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_divsi3.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o) (__aeabi_idiv)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_dvmd_tls.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_udivsi3.o) (__aeabi_idiv0)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_arm_cmpdf2.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o) (__aeabi_dcmplt)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_fixunsdfsi.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o) (__aeabi_d2uiz)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(mulsf3.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o) (__aeabi_fmul)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(floatsisf.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o) (__aeabi_i2f)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(adddf3.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o) (__aeabi_dadd)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(divdf3.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o) (__aeabi_ddiv)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(eqdf2.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_arm_cmpdf2.o) (__eqdf2)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(gedf2.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_arm_cmpdf2.o) (__gedf2)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(ledf2.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_arm_cmpdf2.o) (__ledf2)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(muldf3.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o) (__aeabi_dmul)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(subdf3.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o) (__aeabi_dsub)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(unorddf2.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o) (__aeabi_dcmpun)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(fixdfsi.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_fixunsdfsi.o) (__aeabi_d2iz)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(floatunsidf.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o) (__aeabi_ui2d)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(extendsfdf2.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o) (__aeabi_f2d)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(truncdfsf2.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o) (__aeabi_d2f)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_clzsi2.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(mulsf3.o) (__clzsi2)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-atof.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o) (atof)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-atol.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o) (atol)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-exit.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/crt0.o (exit)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-impure.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-exit.o) (_global_impure_ptr)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-init.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/crt0.o (__libc_init_array)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-isspace.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o) (isspace)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-locale.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-isspace.o) (__locale_ctype_ptr)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-malloc.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o) (malloc)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-mbtowc_r.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-locale.o) (__ascii_mbtowc)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-memcpy-stub.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o) (memcpy)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-memmove.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o) (memmove)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-memset.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/crt0.o (memset)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-freer.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-malloc.o) (_free_r)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-mallocr.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-malloc.o) (_malloc_r)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-vfprintf_float.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(dtostrf.o) (_printf_float)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-vfprintf_i.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-vfprintf_float.o) (_printf_common)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-realloc.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o) (realloc)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-sbrkr.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-mallocr.o) (_sbrk_r)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-sprintf.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(dtostrf.o) (sprintf)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strchr.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o) (strchr)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strcmp.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o) (strcmp)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strcpy.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o) (strcpy)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strlen.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o) (strlen)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strncmp.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o) (strncmp)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strncpy.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o) (strncpy)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strrchr.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o) (strrchr)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strstr.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o) (strstr)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtod.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-atof.o) (strtod)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtol.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-atol.o) (_strtol_r)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-tolower.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o) (tolower)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-toupper.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o) (toupper)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-wctomb_r.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-locale.o) (__ascii_wctomb)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-ctype_.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-locale.o) (_ctype_)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-dtoa.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-vfprintf_float.o) (_dtoa_r)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-gdtoa-gethex.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtod.o) (__gethex)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-gdtoa-hexnan.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtod.o) (__match)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-localeconv.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtod.o) (__localeconv_l)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-memchr-stub.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-vfprintf_i.o) (memchr)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-mlock.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-freer.o) (__malloc_lock)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-mprec.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtod.o) (_Balloc)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-callocr.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-mprec.o) (_calloc_r)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-reallocr.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-realloc.o) (_realloc_r)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-svfprintf.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-sprintf.o) (_svfprintf_r)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-reent.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-sbrkr.o) (errno)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-sf_nan.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtod.o) (nanf)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-msizer.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-reallocr.o) (_malloc_usable_size_r)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_arm_cmpsf2.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtod.o) (__aeabi_fcmple)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(eqsf2.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_arm_cmpsf2.o) (__eqsf2)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(gesf2.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_arm_cmpsf2.o) (__gesf2)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(lesf2.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_arm_cmpsf2.o) (__lesf2)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(unordsf2.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtod.o) (__aeabi_fcmpun)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(floatsidf.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtod.o) (__aeabi_i2d)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libnosys.a(sbrk.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-sbrkr.o) (_sbrk)
+c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libnosys.a(_exit.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-exit.o) (_exit)
+
+Allocating common symbols
+Common symbol size file
+
+errno 0x4 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-reent.o)
+
+Discarded input sections
+
+ .text 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crti.o
+ .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crti.o
+ .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crti.o
+ .data 0x00000000 0x4 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crtbegin.o
+ .text 0x00000000 0x78 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/crt0.o
+ .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/crt0.o
+ .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/crt0.o
+ .ARM.extab 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/crt0.o
+ .ARM.exidx 0x00000000 0x8 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/crt0.o
+ .ARM.attributes
+ 0x00000000 0x1b c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/crt0.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .group 0x00000000 0x8 Sketch.o
+ .text 0x00000000 0x0 Sketch.o
+ .data 0x00000000 0x0 Sketch.o
+ .bss 0x00000000 0x0 Sketch.o
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .text 0x00000000 0x0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .data 0x00000000 0x0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .bss 0x00000000 0x0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0x38e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0x22 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0x87 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0x51 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0xef C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0x6a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0x1df C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0x22 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0x682 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0x8bf C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0x235 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0xd6a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0x4ce C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0x9f8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0x82b C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0x45f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0x5e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0x906 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0x225 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0x797 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0x5e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0x634 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0x3b6 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0xc55 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0x1092 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0xc4a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0x6bf C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0x1b4b C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0x144a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0x34e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0x7c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0xa0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0x4c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0xca C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0x94 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0x58 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0x364 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0x82 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0x197 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0xb8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0xa0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0xb2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0x7c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0x161 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0xdc C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0x11e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0xe2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0xe2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0xe2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0x12c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0x100 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0xf4 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0x40f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0x40 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0x361 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0x16ea C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0x6d C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0x151 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0x1bc C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0x58 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0x35 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0x58 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0x1f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0x20 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0x187 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0x52 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0x40 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0x40 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0xd7 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00000000 0x18b C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .text 0x00000000 0x0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .data 0x00000000 0x0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .bss 0x00000000 0x0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x8e0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x22 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x87 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x51 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0xef C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x6a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x1df C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x38e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x40 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x22 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0xb5 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x3ad C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x682 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x8bf C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x235 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0xd6a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x4ce C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x9f8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x82b C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x45f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x5e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x906 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x225 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x797 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x5e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x634 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x3b6 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0xc55 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x1092 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0xc4a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x6bf C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x1b4b C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x144a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x34e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x7c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0xa0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x4c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0xca C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x94 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x58 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x364 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x82 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x197 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0xb8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0xa0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0xb2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x7c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x161 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0xdc C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x11e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0xe2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0xe2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0xe2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x12c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x100 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0xf4 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x40f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x40 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x361 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x16ea C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x6d C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x151 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x1bc C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x58 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x35 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x9c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x58 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x1f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x43 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x20 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x187 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x32a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x29 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x45d C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x190 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0xd93 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x5e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x28 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x70 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x2e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x19d C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x2e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x17e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00000000 0x22 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(hooks.o)
+ .text 0x00000000 0x0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(hooks.o)
+ .data 0x00000000 0x0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(hooks.o)
+ .bss 0x00000000 0x0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(hooks.o)
+ .text.__halt 0x00000000 0x2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(hooks.o)
+ .debug_macro 0x00000000 0x8e0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(hooks.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .text 0x00000000 0x0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .data 0x00000000 0x0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .bss 0x00000000 0x0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x982 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x22 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x87 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x51 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0xef C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x6a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x1df C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x143 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x3c3 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x58 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x35 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x9c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x10e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x94 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x58 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x1f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x43 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x20 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x187 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x353 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x29 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0xea C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x35 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x18 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x1da C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x3d3 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x45d C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x190 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0xd93 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x38e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x40 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x22 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0xaf C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x3ad C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x682 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x8bf C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x235 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0xd6a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x4ce C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x9f8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x82b C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x45f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x5e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x906 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x225 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x797 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x5e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x634 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x3b6 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0xc55 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x1092 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0xc4a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x6bf C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x1b4b C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x144a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x34e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x7c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0xa0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x4c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0xca C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x94 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x58 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x364 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x82 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x197 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0xb8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0xa0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0xb2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x7c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x161 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0xdc C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x11e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0xe2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0xe2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0xe2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x12c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x100 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0xf4 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x40f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x40 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x361 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x16ea C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x6d C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x5e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x151 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x4c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x52 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x40 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x40 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0xd7 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x18b C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x11 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0xe2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x28 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x1bc C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x28 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x70 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x2e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x19d C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x2e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x17e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x22 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00000000 0x40 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .text 0x00000000 0x0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .data 0x00000000 0x0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .bss 0x00000000 0x0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .text.resetExternalChip
+ 0x00000000 0x2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x982 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x22 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x87 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x51 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0xef C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x6a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x1df C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x143 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x3c3 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x58 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x35 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x9c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x10e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x94 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x58 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x1f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x43 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x20 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x187 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x353 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x29 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0xea C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x35 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x18 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x1da C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x3d3 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x45d C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x190 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0xd93 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x38e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x40 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x22 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0xaf C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x3ad C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x682 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x8bf C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x235 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0xd6a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x4ce C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x9f8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x82b C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x45f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x5e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x906 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x225 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x797 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x5e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x634 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x3b6 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0xc55 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x1092 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0xc4a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x6bf C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x1b4b C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x144a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x34e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x7c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0xa0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x4c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0xca C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x94 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x58 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x364 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x82 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x197 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0xb8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0xa0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0xb2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x7c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x161 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0xdc C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x11e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0xe2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0xe2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0xe2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x12c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x100 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0xf4 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x40f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x40 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x361 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x16ea C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x6d C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x5e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x151 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x4c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x52 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x40 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x40 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0xd7 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x18b C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x11 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0xe2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x28 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x1bc C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x28 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x70 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x2e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x19d C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x2e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x17e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x22 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x00000000 0x40 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .text 0x00000000 0x0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .data 0x00000000 0x0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .bss 0x00000000 0x0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0x8e0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0x38e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0x22 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0x87 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0x51 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0xef C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0x6a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0x1df C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0x3a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0x22 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0xb5 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0x3ad C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0x682 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0x8bf C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0x235 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0xd6a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0x4ce C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0x9f8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0x82b C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0x45f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0x5e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0x906 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0x225 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0x797 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0x5e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0x634 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0x3b6 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0xc55 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0x1092 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0xc4a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0x6bf C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0x1b4b C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0x144a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0x34e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0x7c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0xa0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0x4c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0xca C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0x94 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0x58 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0x364 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0x82 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0x197 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0xb8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0xa0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0xb2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0x7c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0x161 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0xdc C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0x11e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0xe2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0xe2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0xe2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0x12c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0x100 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0xf4 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0x40f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0x40 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0x361 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0x16ea C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0x6d C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0x151 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0x1bc C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0x58 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0x35 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0x9c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0x97 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0x32a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0xfd C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0x58 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0x1f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0x43 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0x20 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0x187 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0x52 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0x40 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0x40 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0xd7 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00000000 0x18b C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .text 0x00000000 0x0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .data 0x00000000 0x0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .bss 0x00000000 0x0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .text._ZN6Stream9timedReadEv
+ 0x00000000 0x2a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .text._ZN6Stream10setTimeoutEm
+ 0x00000000 0x4 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .text._ZN6Stream10parseFloatE13LookaheadModec
+ 0x00000000 0xac C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .text._ZN6Stream9readBytesEPcj
+ 0x00000000 0x24 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .text._ZN6Stream14readBytesUntilEcPcj
+ 0x00000000 0x30 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .text._ZN6Stream10readStringEv
+ 0x00000000 0x28 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .text._ZN6Stream15readStringUntilEc
+ 0x00000000 0x30 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .text._ZN6Stream9findMultiEPNS_11MultiTargetEi
+ 0x00000000 0xb0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .text._ZN6Stream9findUntilEPcjS0_j.part.0
+ 0x00000000 0x2a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .text._ZN6Stream4findEPc
+ 0x00000000 0x18 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .text._ZN6Stream4findEPcj
+ 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .text._ZN6Stream9findUntilEPcjS0_j
+ 0x00000000 0x3c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .text._ZN6Stream9findUntilEPcS0_
+ 0x00000000 0x26 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .rodata._ZN6Stream10readStringEv.str1.1
+ 0x00000000 0x1 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x982 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x22 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x87 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x51 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0xef C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x6a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x1df C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x143 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x3c3 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x58 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x35 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x9c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x10e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x94 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x58 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x1f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x43 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x20 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x187 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x353 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x29 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0xea C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x35 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x18 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x1da C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x3d3 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x45d C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x190 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0xd93 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x38e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x40 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x22 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0xaf C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x3ad C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x682 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x8bf C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x235 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0xd6a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x4ce C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x9f8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x82b C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x45f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x5e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x906 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x225 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x797 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x5e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x634 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x3b6 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0xc55 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x1092 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0xc4a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x6bf C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x1b4b C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x144a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x34e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x7c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0xa0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x4c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0xca C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x94 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x58 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x364 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x82 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x197 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0xb8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0xa0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0xb2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x7c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x161 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0xdc C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x11e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0xe2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0xe2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0xe2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x12c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x100 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0xf4 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x40f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x40 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x361 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x16ea C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x6d C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x5e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x151 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x4c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x52 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x40 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x40 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0xd7 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x18b C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x11 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0xe2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x28 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x1bc C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x28 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x70 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x2e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x19d C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x2e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x17e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x22 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00000000 0x40 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .text 0x00000000 0x0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .data 0x00000000 0x0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .bss 0x00000000 0x0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .text.resetExternalChip
+ 0x00000000 0x2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .text._ZN7Serial_5beginEmh
+ 0x00000000 0x2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .text._ZN7Serial_3endEv
+ 0x00000000 0x14 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .text._ZN7Serial_9readBytesEPcj
+ 0x00000000 0x3e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .text._ZN7Serial_cvbEv
+ 0x00000000 0x28 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .text._ZN7Serial_9readBreakEv
+ 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .text._ZN7Serial_4baudEv
+ 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .text._ZN7Serial_8stopbitsEv
+ 0x00000000 0xc C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .text._ZN7Serial_10paritytypeEv
+ 0x00000000 0xc C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .text._ZN7Serial_7numbitsEv
+ 0x00000000 0xc C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .text._ZN7Serial_3dtrEv
+ 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .text._ZN7Serial_3rtsEv
+ 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x982 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x22 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x87 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x51 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0xef C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x6a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x1df C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x143 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x3c3 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x58 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x35 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x9c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x10e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x94 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x58 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x1f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x43 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x20 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x187 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x353 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x29 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0xea C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x35 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x18 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x1da C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x3d3 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x45d C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x190 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0xd93 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x38e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x40 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x22 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0xaf C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x3ad C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x682 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x8bf C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x235 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0xd6a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x4ce C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x9f8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x82b C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x45f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x5e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x906 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x225 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x797 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x5e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x634 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x3b6 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0xc55 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x1092 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0xc4a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x6bf C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x1b4b C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x144a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x34e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x7c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0xa0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x4c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0xca C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x94 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x58 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x364 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x82 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x197 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0xb8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0xa0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0xb2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x7c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x161 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0xdc C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x11e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0xe2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0xe2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0xe2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x12c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x100 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0xf4 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x40f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x40 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x361 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x16ea C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x6d C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x5e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x151 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x4c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x52 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x40 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x40 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0xd7 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x18b C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x11 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0xe2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x28 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x1bc C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x28 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x70 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x2e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x19d C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x2e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x17e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x22 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00000000 0x40 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .text 0x00000000 0x0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .data 0x00000000 0x0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .bss 0x00000000 0x0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .text._ZN13PluggableUSB_C2Ev
+ 0x00000000 0xc C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .debug_macro 0x00000000 0x982 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .debug_macro 0x00000000 0x2e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .debug_macro 0x00000000 0x22 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .debug_macro 0x00000000 0x35 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .debug_macro 0x00000000 0xef C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .debug_macro 0x00000000 0x6a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .debug_macro 0x00000000 0x1df C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .debug_macro 0x00000000 0x45d C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .debug_macro 0x00000000 0x353 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .debug_macro 0x00000000 0x94 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .debug_macro 0x00000000 0x58 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .debug_macro 0x00000000 0x1f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .debug_macro 0x00000000 0x43 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .debug_macro 0x00000000 0x20 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .debug_macro 0x00000000 0x187 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .debug_macro 0x00000000 0x52 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .debug_macro 0x00000000 0x40 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .debug_macro 0x00000000 0x40 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .debug_macro 0x00000000 0xd7 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .debug_macro 0x00000000 0x18b C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .debug_macro 0x00000000 0x143 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .debug_macro 0x00000000 0x3c3 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .debug_macro 0x00000000 0x35 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .debug_macro 0x00000000 0x29 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .debug_macro 0x00000000 0xea C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .debug_macro 0x00000000 0x4c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .debug_macro 0x00000000 0x11 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .debug_macro 0x00000000 0x2e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .debug_macro 0x00000000 0x19d C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .debug_macro 0x00000000 0x28 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .group 0x00000000 0xc C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .text 0x00000000 0x0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .data 0x00000000 0x0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .bss 0x00000000 0x0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .text._ZN14USBDeviceClass7standbyEv
+ 0x00000000 0x14 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .text._ZN14USBDeviceClass6detachEv
+ 0x00000000 0x18 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .text._ZN14USBDeviceClass3endEv
+ 0x00000000 0x18 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .text._ZN14USBDeviceClass10configuredEv
+ 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .text._ZN14USBDeviceClass5stallEm
+ 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .text._ZN14USBDeviceClass9connectedEv
+ 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .text._ZN14USBDeviceClass12packMessagesEb
+ 0x00000000 0x2c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x982 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x22 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x87 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x51 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0xef C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x6a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x1df C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x143 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x3c3 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x58 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x35 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x9c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x10e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x94 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x58 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x1f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x43 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x20 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x187 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x353 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x29 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0xea C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x35 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x18 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x1da C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x3d3 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x45d C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x190 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0xd93 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x38e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x40 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x22 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0xaf C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x3ad C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x682 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x8bf C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x235 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0xd6a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x4ce C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x9f8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x82b C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x45f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x5e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x906 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x225 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x797 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x5e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x634 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x3b6 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0xc55 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x1092 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0xc4a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x6bf C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x1b4b C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x144a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x34e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x7c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0xa0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x4c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0xca C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x94 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x58 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x364 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x82 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x197 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0xb8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0xa0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0xb2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x7c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x161 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0xdc C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x11e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0xe2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0xe2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0xe2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x12c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x100 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0xf4 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x40f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x40 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x361 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x16ea C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x6d C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x5e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x151 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x4c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x52 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x40 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x40 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0xd7 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x18b C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x11 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0xe2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x28 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x1bc C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x28 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x70 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x2e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x19d C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x2e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x17e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x22 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00000000 0x40 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .text 0x00000000 0x0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .data 0x00000000 0x0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .bss 0x00000000 0x0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x8e0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x22 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x22 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x87 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x51 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0xef C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x6a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x1df C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x58 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x35 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x9c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x10e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x8d C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x58 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x1f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x43 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x20 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x187 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x29 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x35 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x1e1 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x45d C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x190 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0xd93 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x38e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x40 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x22 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0xaf C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x3ad C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x682 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x8bf C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x235 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0xd6a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x4ce C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x9f8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x82b C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x45f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x5e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x906 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x225 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x797 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x5e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x634 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x3b6 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0xc55 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x1092 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0xc4a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x6bf C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x1b4b C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x144a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x34e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x7c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0xa0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x4c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0xca C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x94 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x58 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x364 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x82 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x197 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0xb8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0xa0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0xb2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x7c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x161 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0xdc C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x11e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0xe2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0xe2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0xe2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x12c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x100 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0xf4 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x40f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x40 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x361 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x16ea C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x6d C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x5e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x151 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x28 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x70 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x2e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x19d C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x2e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x17e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00000000 0x22 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .text 0x00000000 0x0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .data 0x00000000 0x0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .bss 0x00000000 0x0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .text.analogReadResolution
+ 0x00000000 0x4c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .text.analogRead
+ 0x00000000 0xdc C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .data._ADCResolution
+ 0x00000000 0x4 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .data._readResolution
+ 0x00000000 0x4 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x8e0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x22 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x22 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x87 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x51 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0xef C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x6a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x1df C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x58 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x35 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x9c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x10e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x8d C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x58 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x1f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x43 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x20 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x187 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x330 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x29 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x35 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x1e1 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x45d C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x190 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0xd93 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x38e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x40 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x22 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0xaf C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x3ad C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x682 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x8bf C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x235 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0xd6a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x4ce C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x9f8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x82b C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x45f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x5e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x906 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x225 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x797 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x5e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x634 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x3b6 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0xc55 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x1092 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0xc4a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x6bf C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x1b4b C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x144a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x34e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x7c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0xa0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x4c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0xca C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x94 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x58 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x364 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x82 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x197 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0xb8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0xa0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0xb2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x7c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x161 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0xdc C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x11e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0xe2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0xe2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0xe2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x12c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x100 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0xf4 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x40f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x40 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x361 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x16ea C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x6d C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x5e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x151 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x1d4 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x28 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x70 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x2e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x19d C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x2e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x17e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x22 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x52 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x40 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x40 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0xd7 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x00000000 0x18b C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .text 0x00000000 0x0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .data 0x00000000 0x0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .bss 0x00000000 0x0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .text.digitalRead
+ 0x00000000 0x30 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x8e0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x22 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x22 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x87 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x51 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0xef C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x6a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x1df C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x58 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x35 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x9c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x10e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x8d C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x58 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x1f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x43 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x20 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x187 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x330 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x29 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x35 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x1e1 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x45d C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x190 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0xd93 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x38e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x40 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x22 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0xaf C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x3ad C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x682 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x8bf C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x235 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0xd6a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x4ce C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x9f8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x82b C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x45f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x5e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x906 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x225 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x797 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x5e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x634 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x3b6 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0xc55 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x1092 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0xc4a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x6bf C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x1b4b C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x144a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x34e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x7c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0xa0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x4c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0xca C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x94 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x58 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x364 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x82 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x197 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0xb8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0xa0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0xb2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x7c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x161 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0xdc C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x11e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0xe2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0xe2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0xe2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x12c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x100 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0xf4 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x40f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x40 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x361 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x16ea C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x6d C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x5e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x151 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x1d4 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x28 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x70 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x2e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x19d C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x2e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x17e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x00000000 0x22 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .text 0x00000000 0x0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .data 0x00000000 0x0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .bss 0x00000000 0x0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x8e0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x22 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x22 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x87 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x51 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0xef C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x6a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x1df C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x58 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x35 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x9c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x10e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x8d C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x58 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x1f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x43 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x20 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x187 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x330 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x29 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x35 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x1e1 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x45d C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x190 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0xd93 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x38e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x40 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x22 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0xaf C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x3ad C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x682 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x8bf C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x235 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0xd6a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x4ce C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x9f8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x82b C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x45f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x5e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x906 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x225 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x797 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x5e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x634 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x3b6 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0xc55 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x1092 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0xc4a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x6bf C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x1b4b C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x144a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x34e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x7c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0xa0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x4c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0xca C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x94 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x58 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x364 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x82 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x197 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0xb8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0xa0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0xb2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x7c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x161 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0xdc C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x11e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0xe2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0xe2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0xe2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x12c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x100 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0xf4 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x40f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x40 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x361 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x16ea C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x6d C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x5e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x151 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x1d4 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x28 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x70 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x2e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x19d C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x2e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x17e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x22 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x52 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x40 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x40 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0xd7 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x18b C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x00000000 0x4c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text 0x00000000 0x0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .data 0x00000000 0x0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .bss 0x00000000 0x0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZNK6String14StringIfHelperEv
+ 0x00000000 0x2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZN6StringC2EOS_
+ 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZN6StringC2EO15StringSumHelper
+ 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZN6StringD2Ev
+ 0x00000000 0x12 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZN6String10invalidateEv
+ 0x00000000 0x18 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZN6String12changeBufferEj
+ 0x00000000 0x18 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZN6String7reserveEj
+ 0x00000000 0x2a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZN6String4copyEPKcj
+ 0x00000000 0x28 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZN6StringC2EPKc
+ 0x00000000 0x26 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZN6String4copyEPK19__FlashStringHelperj
+ 0x00000000 0x28 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZN6String4moveERS_
+ 0x00000000 0x40 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZN6StringaSERKS_
+ 0x00000000 0x20 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZN6StringC2ERKS_
+ 0x00000000 0x14 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZN6StringaSEOS_
+ 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZN6StringaSEO15StringSumHelper
+ 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZN6StringaSEPKc
+ 0x00000000 0x22 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZN6StringC2Ec
+ 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZN6StringC2Ehh
+ 0x00000000 0x22 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZN6StringC2Eih
+ 0x00000000 0x24 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZN6StringC2Ejh
+ 0x00000000 0x24 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZN6StringC2Elh
+ 0x00000000 0x24 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZN6StringC2Emh
+ 0x00000000 0x24 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZN6StringC2Efh
+ 0x00000000 0x34 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZN6StringC2Edh
+ 0x00000000 0x30 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZN6StringaSEPK19__FlashStringHelper
+ 0x00000000 0x22 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZN6StringC2EPK19__FlashStringHelper
+ 0x00000000 0x14 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZN6String6concatEPKcj
+ 0x00000000 0x32 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZN6String6concatERKS_
+ 0x00000000 0xc C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZN6String6concatEPKc
+ 0x00000000 0x1a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZN6String6concatEc
+ 0x00000000 0x14 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZN6String6concatEh
+ 0x00000000 0x20 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZN6String6concatEi
+ 0x00000000 0x22 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZN6String6concatEj
+ 0x00000000 0x22 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZN6String6concatEl
+ 0x00000000 0x22 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZN6String6concatEm
+ 0x00000000 0x22 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZN6String6concatEf
+ 0x00000000 0x2c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZN6String6concatEd
+ 0x00000000 0x2a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZN6String6concatEPK19__FlashStringHelper
+ 0x00000000 0x3a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZplRK15StringSumHelperRK6String
+ 0x00000000 0x1a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZplRK15StringSumHelperPKc
+ 0x00000000 0x26 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZplRK15StringSumHelperc
+ 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZplRK15StringSumHelperh
+ 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZplRK15StringSumHelperi
+ 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZplRK15StringSumHelperj
+ 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZplRK15StringSumHelperl
+ 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZplRK15StringSumHelperm
+ 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZplRK15StringSumHelperf
+ 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZplRK15StringSumHelperd
+ 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZplRK15StringSumHelperPK19__FlashStringHelper
+ 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZNK6String9compareToERKS_
+ 0x00000000 0x38 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZNK6String6equalsERKS_
+ 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZNK6String6equalsEPKc
+ 0x00000000 0x2c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZNK6StringltERKS_
+ 0x00000000 0xa C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZNK6StringgtERKS_
+ 0x00000000 0xe C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZNK6StringleERKS_
+ 0x00000000 0xe C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZNK6StringgeERKS_
+ 0x00000000 0xc C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZNK6String16equalsIgnoreCaseERKS_
+ 0x00000000 0x40 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZNK6String10startsWithERKS_j
+ 0x00000000 0x2c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZNK6String10startsWithERKS_
+ 0x00000000 0x18 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZNK6String8endsWithERKS_
+ 0x00000000 0x2a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZN6String9setCharAtEjc
+ 0x00000000 0xc C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZN6StringixEj
+ 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZNK6StringixEj
+ 0x00000000 0x14 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZNK6String6charAtEj
+ 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZNK6String8getBytesEPhjj
+ 0x00000000 0x34 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZNK6String7indexOfEcj
+ 0x00000000 0x1e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZNK6String7indexOfEc
+ 0x00000000 0xa C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZNK6String7indexOfERKS_j
+ 0x00000000 0x20 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZNK6String7indexOfERKS_
+ 0x00000000 0xa C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZNK6String11lastIndexOfEcj
+ 0x00000000 0x30 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZNK6String11lastIndexOfEc
+ 0x00000000 0xc C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZNK6String11lastIndexOfERKS_j
+ 0x00000000 0x4c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZNK6String11lastIndexOfERKS_
+ 0x00000000 0xe C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZNK6String9substringEjj
+ 0x00000000 0x4c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZN6String7replaceEcc
+ 0x00000000 0x18 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZN6String7replaceERKS_S1_
+ 0x00000000 0x120 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZN6String6removeEjj
+ 0x00000000 0x34 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZN6String6removeEj
+ 0x00000000 0xc C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZN6String11toLowerCaseEv
+ 0x00000000 0x1a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZN6String11toUpperCaseEv
+ 0x00000000 0x1a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZN6String4trimEv
+ 0x00000000 0x52 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZNK6String5toIntEv
+ 0x00000000 0xe C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZNK6String8toDoubleEv
+ 0x00000000 0x14 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .text._ZNK6String7toFloatEv
+ 0x00000000 0xc C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .bss._ZZN6StringixEjE19dummy_writable_char
+ 0x00000000 0x1 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .rodata._ZNK6String9substringEjj.str1.1
+ 0x00000000 0x1 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .debug_info 0x00000000 0x4b92 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .debug_abbrev 0x00000000 0x6b5 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .debug_loc 0x00000000 0x2c0c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .debug_aranges
+ 0x00000000 0x2b8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .debug_ranges 0x00000000 0x578 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .debug_macro 0x00000000 0x1d1 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .debug_macro 0x00000000 0x982 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .debug_macro 0x00000000 0x143 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .debug_macro 0x00000000 0x3c3 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .debug_macro 0x00000000 0x22 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .debug_macro 0x00000000 0x52 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .debug_macro 0x00000000 0x8d C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .debug_macro 0x00000000 0x35 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .debug_macro 0x00000000 0x9c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .debug_macro 0x00000000 0x10e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .debug_macro 0x00000000 0x94 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .debug_macro 0x00000000 0x57 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .debug_macro 0x00000000 0x58 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .debug_macro 0x00000000 0x1f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .debug_macro 0x00000000 0x43 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .debug_macro 0x00000000 0x20 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .debug_macro 0x00000000 0x187 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .debug_macro 0x00000000 0x353 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .debug_macro 0x00000000 0x29 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .debug_macro 0x00000000 0xea C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .debug_macro 0x00000000 0x35 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .debug_macro 0x00000000 0x4c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .debug_macro 0x00000000 0xef C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .debug_macro 0x00000000 0x6a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .debug_macro 0x00000000 0x1df C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .debug_macro 0x00000000 0x45d C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .debug_macro 0x00000000 0x190 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .debug_line 0x00000000 0xf03 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .debug_str 0x00000000 0xab2a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .comment 0x00000000 0x5a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .debug_frame 0x00000000 0x884 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .ARM.attributes
+ 0x00000000 0x32 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .text 0x00000000 0x0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .data 0x00000000 0x0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .bss 0x00000000 0x0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x982 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x22 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x87 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x51 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0xef C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x6a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x1df C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x38e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x40 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x22 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0xb5 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x3ad C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x682 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x8bf C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x235 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0xd6a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x4ce C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x9f8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x82b C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x45f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x5e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x906 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x225 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x797 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x5e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x634 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x3b6 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0xc55 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x1092 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0xc4a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x6bf C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x1b4b C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x144a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x34e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x7c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0xa0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x4c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0xca C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x94 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x58 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x364 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x82 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x197 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0xb8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0xa0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0xb2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x7c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x161 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0xdc C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x11e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0xe2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0xe2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0xe2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x12c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x100 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0xf4 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x40f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x40 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x361 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x16ea C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x6d C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x151 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x58 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x35 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x82 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x45d C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0xa2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x97 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x94 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x58 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x1f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x43 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x20 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x187 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x52 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x40 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x40 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0xd7 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x18b C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x143 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x3c3 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x35 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x29 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0xea C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x4c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x196 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x11 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0xe2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x28 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x00000000 0x1bc C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(dtostrf.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(dtostrf.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(dtostrf.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(dtostrf.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(dtostrf.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(dtostrf.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(dtostrf.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(dtostrf.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(dtostrf.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(dtostrf.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(dtostrf.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(dtostrf.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(dtostrf.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(dtostrf.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(dtostrf.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(dtostrf.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(dtostrf.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(dtostrf.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(dtostrf.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(dtostrf.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(dtostrf.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(dtostrf.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(dtostrf.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(dtostrf.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(dtostrf.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(dtostrf.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(dtostrf.o)
+ .text 0x00000000 0x0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(dtostrf.o)
+ .data 0x00000000 0x0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(dtostrf.o)
+ .bss 0x00000000 0x0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(dtostrf.o)
+ .text.dtostrf 0x00000000 0x28 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(dtostrf.o)
+ .rodata.dtostrf.str1.1
+ 0x00000000 0x9 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(dtostrf.o)
+ .debug_info 0x00000000 0xa44 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(dtostrf.o)
+ .debug_abbrev 0x00000000 0x1f3 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(dtostrf.o)
+ .debug_loc 0x00000000 0x96 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(dtostrf.o)
+ .debug_aranges
+ 0x00000000 0x20 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(dtostrf.o)
+ .debug_ranges 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(dtostrf.o)
+ .debug_macro 0x00000000 0x189 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(dtostrf.o)
+ .debug_macro 0x00000000 0x8e0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(dtostrf.o)
+ .debug_macro 0x00000000 0x22 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(dtostrf.o)
+ .debug_macro 0x00000000 0x52 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(dtostrf.o)
+ .debug_macro 0x00000000 0x8d C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(dtostrf.o)
+ .debug_macro 0x00000000 0x35 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(dtostrf.o)
+ .debug_macro 0x00000000 0x9c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(dtostrf.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(dtostrf.o)
+ .debug_macro 0x00000000 0x57 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(dtostrf.o)
+ .debug_macro 0x00000000 0x97 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(dtostrf.o)
+ .debug_macro 0x00000000 0x330 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(dtostrf.o)
+ .debug_macro 0x00000000 0xfd C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(dtostrf.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(dtostrf.o)
+ .debug_macro 0x00000000 0x58 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(dtostrf.o)
+ .debug_macro 0x00000000 0x1f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(dtostrf.o)
+ .debug_macro 0x00000000 0x43 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(dtostrf.o)
+ .debug_macro 0x00000000 0x20 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(dtostrf.o)
+ .debug_macro 0x00000000 0x187 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(dtostrf.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(dtostrf.o)
+ .debug_macro 0x00000000 0x6a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(dtostrf.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(dtostrf.o)
+ .debug_macro 0x00000000 0x52 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(dtostrf.o)
+ .debug_macro 0x00000000 0x40 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(dtostrf.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(dtostrf.o)
+ .debug_macro 0x00000000 0x40 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(dtostrf.o)
+ .debug_macro 0x00000000 0xd7 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(dtostrf.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(dtostrf.o)
+ .debug_macro 0x00000000 0x18b C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(dtostrf.o)
+ .debug_line 0x00000000 0x33f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(dtostrf.o)
+ .debug_str 0x00000000 0x6bb4 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(dtostrf.o)
+ .comment 0x00000000 0x5a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(dtostrf.o)
+ .debug_frame 0x00000000 0x2c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(dtostrf.o)
+ .ARM.attributes
+ 0x00000000 0x32 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(dtostrf.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(itoa.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(itoa.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(itoa.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(itoa.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(itoa.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(itoa.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(itoa.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(itoa.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(itoa.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(itoa.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(itoa.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(itoa.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(itoa.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(itoa.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(itoa.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(itoa.o)
+ .text 0x00000000 0x0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(itoa.o)
+ .data 0x00000000 0x0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(itoa.o)
+ .bss 0x00000000 0x0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(itoa.o)
+ .text.ltoa 0x00000000 0x84 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(itoa.o)
+ .text.itoa 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(itoa.o)
+ .text.ultoa 0x00000000 0x64 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(itoa.o)
+ .text.utoa 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(itoa.o)
+ .debug_info 0x00000000 0xb95 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(itoa.o)
+ .debug_abbrev 0x00000000 0x20a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(itoa.o)
+ .debug_loc 0x00000000 0x4f0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(itoa.o)
+ .debug_aranges
+ 0x00000000 0x38 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(itoa.o)
+ .debug_ranges 0x00000000 0x28 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(itoa.o)
+ .debug_macro 0x00000000 0xee C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(itoa.o)
+ .debug_macro 0x00000000 0x8e0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(itoa.o)
+ .debug_macro 0x00000000 0x22 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(itoa.o)
+ .debug_macro 0x00000000 0x52 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(itoa.o)
+ .debug_macro 0x00000000 0x8d C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(itoa.o)
+ .debug_macro 0x00000000 0x35 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(itoa.o)
+ .debug_macro 0x00000000 0x9c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(itoa.o)
+ .debug_macro 0x00000000 0x174 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(itoa.o)
+ .debug_macro 0x00000000 0x57 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(itoa.o)
+ .debug_macro 0x00000000 0x58 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(itoa.o)
+ .debug_macro 0x00000000 0x1f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(itoa.o)
+ .debug_macro 0x00000000 0x43 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(itoa.o)
+ .debug_macro 0x00000000 0x20 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(itoa.o)
+ .debug_macro 0x00000000 0x187 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(itoa.o)
+ .debug_macro 0x00000000 0x330 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(itoa.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(itoa.o)
+ .debug_macro 0x00000000 0x35 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(itoa.o)
+ .debug_line 0x00000000 0x340 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(itoa.o)
+ .debug_str 0x00000000 0x58f7 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(itoa.o)
+ .comment 0x00000000 0x5a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(itoa.o)
+ .debug_frame 0x00000000 0x80 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(itoa.o)
+ .ARM.attributes
+ 0x00000000 0x32 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(itoa.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(new.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(new.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(new.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(new.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(new.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(new.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(new.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(new.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(new.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(new.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(new.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(new.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(new.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(new.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(new.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(new.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(new.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(new.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(new.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(new.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(new.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(new.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(new.o)
+ .text 0x00000000 0x0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(new.o)
+ .data 0x00000000 0x0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(new.o)
+ .bss 0x00000000 0x0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(new.o)
+ .text._Znaj 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(new.o)
+ .text._ZdaPv 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(new.o)
+ .debug_macro 0x00000000 0x982 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(new.o)
+ .debug_macro 0x00000000 0x143 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(new.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(new.o)
+ .debug_macro 0x00000000 0x3c3 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(new.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(new.o)
+ .debug_macro 0x00000000 0x22 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(new.o)
+ .debug_macro 0x00000000 0x52 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(new.o)
+ .debug_macro 0x00000000 0x8d C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(new.o)
+ .debug_macro 0x00000000 0x35 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(new.o)
+ .debug_macro 0x00000000 0x9c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(new.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(new.o)
+ .debug_macro 0x00000000 0x10e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(new.o)
+ .debug_macro 0x00000000 0x94 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(new.o)
+ .debug_macro 0x00000000 0x57 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(new.o)
+ .debug_macro 0x00000000 0x58 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(new.o)
+ .debug_macro 0x00000000 0x1f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(new.o)
+ .debug_macro 0x00000000 0x43 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(new.o)
+ .debug_macro 0x00000000 0x20 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(new.o)
+ .debug_macro 0x00000000 0x187 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(new.o)
+ .debug_macro 0x00000000 0x353 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(new.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(new.o)
+ .debug_macro 0x00000000 0x29 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(new.o)
+ .debug_macro 0x00000000 0xea C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(new.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .text 0x00000000 0x0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .data 0x00000000 0x0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .bss 0x00000000 0x0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .text._ZN6SERCOM25isBufferOverflowErrorUARTEv
+ 0x00000000 0xa C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .text._ZN6SERCOM17isParityErrorUARTEv
+ 0x00000000 0xa C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .text._ZN6SERCOM12initSPIClockE18SercomSpiClockModem
+ 0x00000000 0x2c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .text._ZN6SERCOM8resetSPIEv
+ 0x00000000 0x18 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .text._ZN6SERCOM9enableSPIEv
+ 0x00000000 0x12 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .text._ZN6SERCOM10disableSPIEv
+ 0x00000000 0x12 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .text._ZN6SERCOM15setDataOrderSPIE15SercomDataOrder
+ 0x00000000 0x28 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .text._ZN6SERCOM15getDataOrderSPIEv
+ 0x00000000 0xa C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .text._ZN6SERCOM14setBaudrateSPIEh
+ 0x00000000 0x30 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .text._ZN6SERCOM15setClockModeSPIE18SercomSpiClockMode
+ 0x00000000 0x3c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .text._ZN6SERCOM15transferDataSPIEh
+ 0x00000000 0x18 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .text._ZN6SERCOM24isBufferOverflowErrorSPIEv
+ 0x00000000 0xa C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .text._ZN6SERCOM22isDataRegisterEmptySPIEv
+ 0x00000000 0xa C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .text._ZN6SERCOM28calculateBaudrateSynchronousEm
+ 0x00000000 0x14 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .text._ZN6SERCOM9resetWIREEv
+ 0x00000000 0x18 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .text._ZN6SERCOM10enableWIREEv
+ 0x00000000 0x26 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .text._ZN6SERCOM11disableWIREEv
+ 0x00000000 0x12 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .text._ZN6SERCOM18prepareNackBitWIREEv
+ 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .text._ZN6SERCOM17prepareAckBitWIREEv
+ 0x00000000 0x14 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .text._ZN6SERCOM22prepareCommandBitsWireEh
+ 0x00000000 0x38 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .text._ZN6SERCOM21startTransmissionWIREEh23SercomWireReadWriteFlag
+ 0x00000000 0x84 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .text._ZN6SERCOM18sendDataMasterWIREEh
+ 0x00000000 0x24 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .text._ZN6SERCOM17sendDataSlaveWIREEh
+ 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .text._ZN6SERCOM12isMasterWIREEv
+ 0x00000000 0x12 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .text._ZN6SERCOM11isSlaveWIREEv
+ 0x00000000 0x12 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .text._ZN6SERCOM13isBusIdleWIREEv
+ 0x00000000 0x12 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .text._ZN6SERCOM14isBusOwnerWIREEv
+ 0x00000000 0x12 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .text._ZN6SERCOM13isArbLostWIREEv
+ 0x00000000 0xa C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .text._ZN6SERCOM13isBusBusyWIREEv
+ 0x00000000 0x12 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .text._ZN6SERCOM15isDataReadyWIREEv
+ 0x00000000 0xa C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .text._ZN6SERCOM18isStopDetectedWIREEv
+ 0x00000000 0xa C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .text._ZN6SERCOM21isRestartDetectedWIREEv
+ 0x00000000 0xa C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .text._ZN6SERCOM14isAddressMatchEv
+ 0x00000000 0xa C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .text._ZN6SERCOM25isMasterReadOperationWIREEv
+ 0x00000000 0xa C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .text._ZN6SERCOM20isRXNackReceivedWIREEv
+ 0x00000000 0xa C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .text._ZN6SERCOM13availableWIREEv
+ 0x00000000 0x18 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .text._ZN6SERCOM12readDataWIREEv
+ 0x00000000 0x20 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .text._ZN6SERCOM7initSPIE14SercomSpiTXPad11SercomRXPad17SercomSpiCharSize15SercomDataOrder
+ 0x00000000 0x48 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .text._ZN6SERCOM13initSlaveWIREEhb
+ 0x00000000 0x42 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .text._ZN6SERCOM14initMasterWIREEm
+ 0x00000000 0x54 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x982 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x22 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x87 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x51 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0xef C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x6a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x1df C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x143 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x3c3 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x58 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x35 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x9c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x10e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x94 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x58 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x1f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x43 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x20 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x187 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x353 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x29 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0xea C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x35 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x18 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x1da C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x3d3 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x45d C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x190 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0xd93 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x38e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x40 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x22 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0xaf C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x3ad C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x682 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x8bf C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x235 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0xd6a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x4ce C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x9f8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x82b C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x45f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x5e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x906 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x225 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x797 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x5e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x634 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x3b6 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0xc55 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x1092 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0xc4a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x6bf C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x1b4b C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x144a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x34e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x7c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0xa0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x4c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0xca C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x94 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x58 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x364 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x82 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x197 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0xb8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0xa0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0xb2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x7c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x161 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0xdc C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x11e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0xe2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0xe2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0xe2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x12c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x100 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0xf4 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x40f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x40 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x361 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x16ea C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x6d C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x5e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x151 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x4c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x52 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x40 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x40 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0xd7 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x18b C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x11 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0xe2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x28 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x1bc C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x28 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x70 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x2e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x19d C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x2e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x17e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x22 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x00000000 0x40 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .text 0x00000000 0x0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .data 0x00000000 0x0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .bss 0x00000000 0x0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .text._ZN4UartC2EP6SERCOMhh11SercomRXPad15SercomUartTXPadhh
+ 0x00000000 0x88 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x982 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x22 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x87 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x51 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0xef C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x6a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x1df C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x143 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x3c3 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x58 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x35 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x9c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x10e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x94 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x58 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x1f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x43 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x20 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x187 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x353 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x29 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0xea C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x35 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x18 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x1da C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x3d3 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x45d C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x190 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0xd93 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x38e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x40 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x22 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0xaf C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x3ad C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x682 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x8bf C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x235 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0xd6a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x4ce C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x9f8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x82b C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x45f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x5e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x906 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x225 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x797 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x5e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x634 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x3b6 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0xc55 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x1092 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0xc4a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x6bf C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x1b4b C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x144a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x34e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x7c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0xa0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x4c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0xca C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x94 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x58 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x364 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x82 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x197 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0xb8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0xa0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0xb2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x7c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x161 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0xdc C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x11e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0xe2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0xe2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0xe2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x12c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x100 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0xf4 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x40f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x40 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x361 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x16ea C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x6d C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x5e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x151 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x4c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x52 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x40 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x40 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0xd7 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x18b C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x11 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0xe2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x28 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x1bc C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x28 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x70 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x2e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x19d C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x2e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x17e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x22 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x40 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x00000000 0x4c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .text 0x00000000 0x0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .data 0x00000000 0x0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .bss 0x00000000 0x0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .text._ZN5Print17availableForWriteEv
+ 0x00000000 0x4 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .text._ZN5Print5flushEv
+ 0x00000000 0x2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .text._ZN5Print5writeEPKc
+ 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .text._ZN5Print5printEPK19__FlashStringHelper
+ 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .text._ZN5Print5printERK6String
+ 0x00000000 0xe C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .text._ZN5Print5printEPKc
+ 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .text._ZN5Print5printEc
+ 0x00000000 0xa C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .text._ZN5Print5printERK9Printable
+ 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .text._ZN5Print7printlnEv
+ 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .text._ZN5Print7printlnEPK19__FlashStringHelper
+ 0x00000000 0x14 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .text._ZN5Print7printlnERK6String
+ 0x00000000 0x14 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .text._ZN5Print7printlnEPKc
+ 0x00000000 0x14 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .text._ZN5Print7printlnEc
+ 0x00000000 0x14 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .text._ZN5Print7printlnERK9Printable
+ 0x00000000 0x14 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .text._ZN5Print11printNumberEmh
+ 0x00000000 0x56 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .text._ZN5Print5printEli
+ 0x00000000 0x40 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .text._ZN5Print5printEii
+ 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .text._ZN5Print7printlnEii
+ 0x00000000 0x14 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .text._ZN5Print7printlnEli
+ 0x00000000 0x14 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .text._ZN5Print5printEmi
+ 0x00000000 0x18 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .text._ZN5Print5printEhi
+ 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .text._ZN5Print7printlnEhi
+ 0x00000000 0x14 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .text._ZN5Print5printEji
+ 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .text._ZN5Print7printlnEji
+ 0x00000000 0x14 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .text._ZN5Print7printlnEmi
+ 0x00000000 0x14 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .text._ZN5Print10printFloatEdh
+ 0x00000000 0x174 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .text._ZN5Print5printEdi
+ 0x00000000 0x12 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .text._ZN5Print7printlnEdi
+ 0x00000000 0x20 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .rodata._ZN5Print10printFloatEdh.str1.1
+ 0x00000000 0xc C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .rodata._ZN5Print7printlnEv.str1.1
+ 0x00000000 0x3 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .rodata._ZTV5Print
+ 0x00000000 0x18 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x982 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x143 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x3c3 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x18 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x22 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x52 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x8d C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x35 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x9c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x57 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x58 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x1f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x43 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x20 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x187 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x353 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x1da C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x3d3 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0xef C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x6a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x1df C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x35 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x29 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0xea C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x45d C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x190 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0xd93 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x38e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x40 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x22 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0xaf C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x3ad C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x682 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x8bf C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x235 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0xd6a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x4ce C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x9f8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x82b C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x45f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x5e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x906 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x225 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x797 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x5e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x634 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x3b6 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0xc55 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x1092 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0xc4a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x6bf C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x1b4b C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x144a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x34e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x7c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0xa0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x4c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0xca C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x94 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x58 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x364 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x82 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x197 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0xb8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0xa0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0xb2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x7c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x161 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0xdc C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x12f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x11e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0xe2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0xe2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0xe2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x12c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x100 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0xf4 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x40f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x40 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x361 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x16ea C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x6d C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x5e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x151 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x4c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x52 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x40 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x40 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0xd7 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x18b C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x11 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0xe2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x28 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x1bc C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x28 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x70 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x2e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x19d C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x2e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x17e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x22 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x00000000 0x40 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(abi.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(abi.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(abi.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(abi.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(abi.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(abi.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(abi.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(abi.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(abi.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(abi.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(abi.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(abi.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(abi.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(abi.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(abi.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(abi.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(abi.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(abi.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(abi.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(abi.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(abi.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(abi.o)
+ .group 0x00000000 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(abi.o)
+ .text 0x00000000 0x0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(abi.o)
+ .data 0x00000000 0x0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(abi.o)
+ .bss 0x00000000 0x0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(abi.o)
+ .text.__cxa_pure_virtual
+ 0x00000000 0x2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(abi.o)
+ .text.__cxa_deleted_virtual
+ 0x00000000 0x2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(abi.o)
+ .debug_info 0x00000000 0xfa9 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(abi.o)
+ .debug_abbrev 0x00000000 0x24d C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(abi.o)
+ .debug_aranges
+ 0x00000000 0x28 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(abi.o)
+ .debug_ranges 0x00000000 0x18 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(abi.o)
+ .debug_macro 0x00000000 0x132 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(abi.o)
+ .debug_macro 0x00000000 0x982 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(abi.o)
+ .debug_macro 0x00000000 0x143 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(abi.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(abi.o)
+ .debug_macro 0x00000000 0x3c3 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(abi.o)
+ .debug_macro 0x00000000 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(abi.o)
+ .debug_macro 0x00000000 0x22 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(abi.o)
+ .debug_macro 0x00000000 0x52 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(abi.o)
+ .debug_macro 0x00000000 0x8d C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(abi.o)
+ .debug_macro 0x00000000 0x35 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(abi.o)
+ .debug_macro 0x00000000 0x9c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(abi.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(abi.o)
+ .debug_macro 0x00000000 0x10e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(abi.o)
+ .debug_macro 0x00000000 0x94 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(abi.o)
+ .debug_macro 0x00000000 0x57 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(abi.o)
+ .debug_macro 0x00000000 0x58 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(abi.o)
+ .debug_macro 0x00000000 0x1f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(abi.o)
+ .debug_macro 0x00000000 0x43 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(abi.o)
+ .debug_macro 0x00000000 0x20 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(abi.o)
+ .debug_macro 0x00000000 0x187 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(abi.o)
+ .debug_macro 0x00000000 0x353 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(abi.o)
+ .debug_macro 0x00000000 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(abi.o)
+ .debug_macro 0x00000000 0x29 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(abi.o)
+ .debug_macro 0x00000000 0xea C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(abi.o)
+ .debug_line 0x00000000 0x3f5 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(abi.o)
+ .debug_str 0x00000000 0x741b C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(abi.o)
+ .comment 0x00000000 0x5a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(abi.o)
+ .debug_frame 0x00000000 0x30 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(abi.o)
+ .ARM.attributes
+ 0x00000000 0x32 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(abi.o)
+ .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_thumb1_case_uqi.o)
+ .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_thumb1_case_uqi.o)
+ .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_udivsi3.o)
+ .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_udivsi3.o)
+ .text 0x00000000 0x1d4 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_divsi3.o)
+ .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_divsi3.o)
+ .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_divsi3.o)
+ .debug_frame 0x00000000 0x20 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_divsi3.o)
+ .ARM.attributes
+ 0x00000000 0x1e c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_divsi3.o)
+ .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_dvmd_tls.o)
+ .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_dvmd_tls.o)
+ .text 0x00000000 0x7c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_arm_cmpdf2.o)
+ .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_arm_cmpdf2.o)
+ .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_arm_cmpdf2.o)
+ .ARM.attributes
+ 0x00000000 0x1e c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_arm_cmpdf2.o)
+ .text 0x00000000 0x3c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_fixunsdfsi.o)
+ .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_fixunsdfsi.o)
+ .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_fixunsdfsi.o)
+ .debug_frame 0x00000000 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_fixunsdfsi.o)
+ .ARM.attributes
+ 0x00000000 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_fixunsdfsi.o)
+ .text 0x00000000 0x240 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(mulsf3.o)
+ .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(mulsf3.o)
+ .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(mulsf3.o)
+ .rodata 0x00000000 0x40 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(mulsf3.o)
+ .debug_frame 0x00000000 0x3c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(mulsf3.o)
+ .ARM.attributes
+ 0x00000000 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(mulsf3.o)
+ .text 0x00000000 0xa0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(floatsisf.o)
+ .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(floatsisf.o)
+ .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(floatsisf.o)
+ .debug_frame 0x00000000 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(floatsisf.o)
+ .ARM.attributes
+ 0x00000000 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(floatsisf.o)
+ .text 0x00000000 0x620 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(adddf3.o)
+ .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(adddf3.o)
+ .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(adddf3.o)
+ .debug_frame 0x00000000 0x3c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(adddf3.o)
+ .ARM.attributes
+ 0x00000000 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(adddf3.o)
+ .text 0x00000000 0x668 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(divdf3.o)
+ .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(divdf3.o)
+ .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(divdf3.o)
+ .rodata 0x00000000 0x40 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(divdf3.o)
+ .debug_frame 0x00000000 0x3c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(divdf3.o)
+ .ARM.attributes
+ 0x00000000 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(divdf3.o)
+ .text 0x00000000 0x74 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(eqdf2.o)
+ .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(eqdf2.o)
+ .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(eqdf2.o)
+ .debug_frame 0x00000000 0x38 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(eqdf2.o)
+ .ARM.attributes
+ 0x00000000 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(eqdf2.o)
+ .text 0x00000000 0xc8 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(gedf2.o)
+ .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(gedf2.o)
+ .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(gedf2.o)
+ .debug_frame 0x00000000 0x38 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(gedf2.o)
+ .ARM.attributes
+ 0x00000000 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(gedf2.o)
+ .text 0x00000000 0xc4 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(ledf2.o)
+ .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(ledf2.o)
+ .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(ledf2.o)
+ .debug_frame 0x00000000 0x38 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(ledf2.o)
+ .ARM.attributes
+ 0x00000000 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(ledf2.o)
+ .text 0x00000000 0x500 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(muldf3.o)
+ .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(muldf3.o)
+ .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(muldf3.o)
+ .rodata 0x00000000 0x40 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(muldf3.o)
+ .debug_frame 0x00000000 0x3c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(muldf3.o)
+ .ARM.attributes
+ 0x00000000 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(muldf3.o)
+ .text 0x00000000 0x62c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(subdf3.o)
+ .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(subdf3.o)
+ .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(subdf3.o)
+ .debug_frame 0x00000000 0x38 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(subdf3.o)
+ .ARM.attributes
+ 0x00000000 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(subdf3.o)
+ .text 0x00000000 0x40 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(unorddf2.o)
+ .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(unorddf2.o)
+ .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(unorddf2.o)
+ .debug_frame 0x00000000 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(unorddf2.o)
+ .ARM.attributes
+ 0x00000000 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(unorddf2.o)
+ .text 0x00000000 0x68 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(fixdfsi.o)
+ .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(fixdfsi.o)
+ .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(fixdfsi.o)
+ .debug_frame 0x00000000 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(fixdfsi.o)
+ .ARM.attributes
+ 0x00000000 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(fixdfsi.o)
+ .text 0x00000000 0x70 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(floatunsidf.o)
+ .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(floatunsidf.o)
+ .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(floatunsidf.o)
+ .debug_frame 0x00000000 0x28 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(floatunsidf.o)
+ .ARM.attributes
+ 0x00000000 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(floatunsidf.o)
+ .text 0x00000000 0xa4 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(extendsfdf2.o)
+ .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(extendsfdf2.o)
+ .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(extendsfdf2.o)
+ .debug_frame 0x00000000 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(extendsfdf2.o)
+ .ARM.attributes
+ 0x00000000 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(extendsfdf2.o)
+ .text 0x00000000 0x114 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(truncdfsf2.o)
+ .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(truncdfsf2.o)
+ .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(truncdfsf2.o)
+ .debug_frame 0x00000000 0x30 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(truncdfsf2.o)
+ .ARM.attributes
+ 0x00000000 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(truncdfsf2.o)
+ .text 0x00000000 0x3c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_clzsi2.o)
+ .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_clzsi2.o)
+ .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_clzsi2.o)
+ .ARM.attributes
+ 0x00000000 0x1e c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_clzsi2.o)
+ .text 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-atof.o)
+ .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-atof.o)
+ .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-atof.o)
+ .text.atof 0x00000000 0xa c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-atof.o)
+ .debug_frame 0x00000000 0x28 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-atof.o)
+ .ARM.attributes
+ 0x00000000 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-atof.o)
+ .text 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-atol.o)
+ .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-atol.o)
+ .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-atol.o)
+ .text.atol 0x00000000 0xc c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-atol.o)
+ .text._atol_r 0x00000000 0xc c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-atol.o)
+ .debug_frame 0x00000000 0x40 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-atol.o)
+ .ARM.attributes
+ 0x00000000 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-atol.o)
+ .text 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-exit.o)
+ .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-exit.o)
+ .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-exit.o)
+ .text.exit 0x00000000 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-exit.o)
+ .debug_frame 0x00000000 0x28 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-exit.o)
+ .ARM.attributes
+ 0x00000000 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-exit.o)
+ .text 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-impure.o)
+ .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-impure.o)
+ .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-impure.o)
+ .rodata._global_impure_ptr
+ 0x00000000 0x4 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-impure.o)
+ .text 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-init.o)
+ .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-init.o)
+ .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-init.o)
+ .text 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-isspace.o)
+ .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-isspace.o)
+ .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-isspace.o)
+ .text.isspace 0x00000000 0x12 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-isspace.o)
+ .debug_frame 0x00000000 0x28 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-isspace.o)
+ .ARM.attributes
+ 0x00000000 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-isspace.o)
+ .text 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-locale.o)
+ .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-locale.o)
+ .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-locale.o)
+ .text._setlocale_r
+ 0x00000000 0x40 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-locale.o)
+ .text.__locale_mb_cur_max
+ 0x00000000 0x1c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-locale.o)
+ .text.__locale_ctype_ptr_l
+ 0x00000000 0x6 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-locale.o)
+ .text.__locale_ctype_ptr
+ 0x00000000 0x1c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-locale.o)
+ .text.setlocale
+ 0x00000000 0x14 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-locale.o)
+ .bss._PathLocale
+ 0x00000000 0x4 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-locale.o)
+ .data.__global_locale
+ 0x00000000 0x16c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-locale.o)
+ .rodata._setlocale_r.str1.1
+ 0x00000000 0x9 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-locale.o)
+ .rodata.str1.1
+ 0x00000000 0x2 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-locale.o)
+ .debug_frame 0x00000000 0x74 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-locale.o)
+ .ARM.attributes
+ 0x00000000 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-locale.o)
+ .text 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-malloc.o)
+ .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-malloc.o)
+ .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-malloc.o)
+ .text 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-mbtowc_r.o)
+ .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-mbtowc_r.o)
+ .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-mbtowc_r.o)
+ .text._mbtowc_r
+ 0x00000000 0x24 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-mbtowc_r.o)
+ .text.__ascii_mbtowc
+ 0x00000000 0x24 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-mbtowc_r.o)
+ .debug_frame 0x00000000 0x44 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-mbtowc_r.o)
+ .ARM.attributes
+ 0x00000000 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-mbtowc_r.o)
+ .text 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-memcpy-stub.o)
+ .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-memcpy-stub.o)
+ .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-memcpy-stub.o)
+ .text 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-memmove.o)
+ .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-memmove.o)
+ .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-memmove.o)
+ .text.memmove 0x00000000 0x24 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-memmove.o)
+ .debug_frame 0x00000000 0x28 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-memmove.o)
+ .ARM.attributes
+ 0x00000000 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-memmove.o)
+ .text 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-memset.o)
+ .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-memset.o)
+ .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-memset.o)
+ .text 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-freer.o)
+ .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-freer.o)
+ .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-freer.o)
+ .text 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-mallocr.o)
+ .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-mallocr.o)
+ .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-mallocr.o)
+ .text 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-vfprintf_float.o)
+ .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-vfprintf_float.o)
+ .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-vfprintf_float.o)
+ .text.__cvt 0x00000000 0xc8 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-vfprintf_float.o)
+ .text.__exponent
+ 0x00000000 0x70 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-vfprintf_float.o)
+ .text._printf_float
+ 0x00000000 0x498 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-vfprintf_float.o)
+ .rodata._printf_float.str1.1
+ 0x00000000 0x12 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-vfprintf_float.o)
+ .debug_frame 0x00000000 0x70 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-vfprintf_float.o)
+ .ARM.attributes
+ 0x00000000 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-vfprintf_float.o)
+ .text 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-vfprintf_i.o)
+ .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-vfprintf_i.o)
+ .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-vfprintf_i.o)
+ .text._printf_common
+ 0x00000000 0xda c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-vfprintf_i.o)
+ .text._printf_i
+ 0x00000000 0x234 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-vfprintf_i.o)
+ .rodata._printf_i.str1.1
+ 0x00000000 0x22 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-vfprintf_i.o)
+ .debug_frame 0x00000000 0x54 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-vfprintf_i.o)
+ .ARM.attributes
+ 0x00000000 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-vfprintf_i.o)
+ .text 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-realloc.o)
+ .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-realloc.o)
+ .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-realloc.o)
+ .text.realloc 0x00000000 0x14 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-realloc.o)
+ .debug_frame 0x00000000 0x28 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-realloc.o)
+ .ARM.attributes
+ 0x00000000 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-realloc.o)
+ .text 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-sbrkr.o)
+ .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-sbrkr.o)
+ .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-sbrkr.o)
+ .text 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-sprintf.o)
+ .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-sprintf.o)
+ .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-sprintf.o)
+ .text._sprintf_r
+ 0x00000000 0x40 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-sprintf.o)
+ .text.sprintf 0x00000000 0x44 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-sprintf.o)
+ .debug_frame 0x00000000 0x50 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-sprintf.o)
+ .ARM.attributes
+ 0x00000000 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-sprintf.o)
+ .text 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strchr.o)
+ .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strchr.o)
+ .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strchr.o)
+ .text.strchr 0x00000000 0x1c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strchr.o)
+ .debug_frame 0x00000000 0x20 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strchr.o)
+ .ARM.attributes
+ 0x00000000 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strchr.o)
+ .text 0x00000000 0x14 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strcmp.o)
+ .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strcmp.o)
+ .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strcmp.o)
+ .debug_frame 0x00000000 0x20 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strcmp.o)
+ .ARM.attributes
+ 0x00000000 0x1c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strcmp.o)
+ .text 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strcpy.o)
+ .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strcpy.o)
+ .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strcpy.o)
+ .text.strcpy 0x00000000 0x10 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strcpy.o)
+ .debug_frame 0x00000000 0x20 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strcpy.o)
+ .ARM.attributes
+ 0x00000000 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strcpy.o)
+ .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strlen.o)
+ .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strlen.o)
+ .text 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strncmp.o)
+ .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strncmp.o)
+ .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strncmp.o)
+ .text.strncmp 0x00000000 0x22 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strncmp.o)
+ .debug_frame 0x00000000 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strncmp.o)
+ .ARM.attributes
+ 0x00000000 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strncmp.o)
+ .text 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strncpy.o)
+ .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strncpy.o)
+ .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strncpy.o)
+ .text.strncpy 0x00000000 0x2a c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strncpy.o)
+ .debug_frame 0x00000000 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strncpy.o)
+ .ARM.attributes
+ 0x00000000 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strncpy.o)
+ .text 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strrchr.o)
+ .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strrchr.o)
+ .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strrchr.o)
+ .text.strrchr 0x00000000 0x24 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strrchr.o)
+ .debug_frame 0x00000000 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strrchr.o)
+ .ARM.attributes
+ 0x00000000 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strrchr.o)
+ .text 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strstr.o)
+ .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strstr.o)
+ .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strstr.o)
+ .text.strstr 0x00000000 0x30 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strstr.o)
+ .debug_frame 0x00000000 0x28 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strstr.o)
+ .ARM.attributes
+ 0x00000000 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strstr.o)
+ .text 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtod.o)
+ .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtod.o)
+ .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtod.o)
+ .text.unlikely.sulp
+ 0x00000000 0x30 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtod.o)
+ .text._strtod_l
+ 0x00000000 0xc10 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtod.o)
+ .text._strtod_r
+ 0x00000000 0x1c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtod.o)
+ .text.strtod_l
+ 0x00000000 0x18 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtod.o)
+ .text.strtod 0x00000000 0x24 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtod.o)
+ .text.strtof_l
+ 0x00000000 0x94 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtod.o)
+ .text.strtof 0x00000000 0xa0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtod.o)
+ .rodata._strtod_l.str1.1
+ 0x00000000 0xc c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtod.o)
+ .rodata.fpi.6129
+ 0x00000000 0x14 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtod.o)
+ .rodata.fpinan.6165
+ 0x00000000 0x14 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtod.o)
+ .rodata.tinytens
+ 0x00000000 0x28 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtod.o)
+ .debug_frame 0x00000000 0xe0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtod.o)
+ .ARM.attributes
+ 0x00000000 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtod.o)
+ .text 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtol.o)
+ .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtol.o)
+ .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtol.o)
+ .text._strtol_l.isra.0
+ 0x00000000 0x10c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtol.o)
+ .text._strtol_r
+ 0x00000000 0x20 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtol.o)
+ .text.strtol_l
+ 0x00000000 0x18 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtol.o)
+ .text.strtol 0x00000000 0x28 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtol.o)
+ .debug_frame 0x00000000 0x88 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtol.o)
+ .ARM.attributes
+ 0x00000000 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtol.o)
+ .text 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-tolower.o)
+ .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-tolower.o)
+ .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-tolower.o)
+ .text.tolower 0x00000000 0x1a c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-tolower.o)
+ .debug_frame 0x00000000 0x28 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-tolower.o)
+ .ARM.attributes
+ 0x00000000 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-tolower.o)
+ .text 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-toupper.o)
+ .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-toupper.o)
+ .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-toupper.o)
+ .text.toupper 0x00000000 0x1a c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-toupper.o)
+ .debug_frame 0x00000000 0x28 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-toupper.o)
+ .ARM.attributes
+ 0x00000000 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-toupper.o)
+ .text 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-wctomb_r.o)
+ .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-wctomb_r.o)
+ .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-wctomb_r.o)
+ .text._wctomb_r
+ 0x00000000 0x20 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-wctomb_r.o)
+ .text.__ascii_wctomb
+ 0x00000000 0x18 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-wctomb_r.o)
+ .debug_frame 0x00000000 0x38 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-wctomb_r.o)
+ .ARM.attributes
+ 0x00000000 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-wctomb_r.o)
+ .text 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-ctype_.o)
+ .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-ctype_.o)
+ .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-ctype_.o)
+ .rodata._ctype_
+ 0x00000000 0x101 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-ctype_.o)
+ .ARM.attributes
+ 0x00000000 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-ctype_.o)
+ .text 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-dtoa.o)
+ .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-dtoa.o)
+ .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-dtoa.o)
+ .text.quorem 0x00000000 0x108 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-dtoa.o)
+ .text._dtoa_r 0x00000000 0xbd0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-dtoa.o)
+ .rodata._dtoa_r.str1.1
+ 0x00000000 0xf c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-dtoa.o)
+ .debug_frame 0x00000000 0x54 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-dtoa.o)
+ .ARM.attributes
+ 0x00000000 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-dtoa.o)
+ .text 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-gdtoa-gethex.o)
+ .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-gdtoa-gethex.o)
+ .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-gdtoa-gethex.o)
+ .text.rshift 0x00000000 0x64 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-gdtoa-gethex.o)
+ .text.__hexdig_fun
+ 0x00000000 0x2a c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-gdtoa-gethex.o)
+ .text.__gethex
+ 0x00000000 0x450 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-gdtoa-gethex.o)
+ .debug_frame 0x00000000 0x60 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-gdtoa-gethex.o)
+ .ARM.attributes
+ 0x00000000 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-gdtoa-gethex.o)
+ .text 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-gdtoa-hexnan.o)
+ .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-gdtoa-hexnan.o)
+ .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-gdtoa-hexnan.o)
+ .text.L_shift 0x00000000 0x22 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-gdtoa-hexnan.o)
+ .text.__match 0x00000000 0x28 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-gdtoa-hexnan.o)
+ .text.__hexnan
+ 0x00000000 0x12e c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-gdtoa-hexnan.o)
+ .debug_frame 0x00000000 0x68 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-gdtoa-hexnan.o)
+ .ARM.attributes
+ 0x00000000 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-gdtoa-hexnan.o)
+ .text 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-localeconv.o)
+ .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-localeconv.o)
+ .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-localeconv.o)
+ .text.__localeconv_l
+ 0x00000000 0x4 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-localeconv.o)
+ .text._localeconv_r
+ 0x00000000 0x18 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-localeconv.o)
+ .text.localeconv
+ 0x00000000 0x18 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-localeconv.o)
+ .debug_frame 0x00000000 0x40 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-localeconv.o)
+ .ARM.attributes
+ 0x00000000 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-localeconv.o)
+ .text 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-memchr-stub.o)
+ .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-memchr-stub.o)
+ .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-memchr-stub.o)
+ .text.memchr 0x00000000 0x16 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-memchr-stub.o)
+ .debug_frame 0x00000000 0x20 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-memchr-stub.o)
+ .ARM.attributes
+ 0x00000000 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-memchr-stub.o)
+ .text 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-mlock.o)
+ .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-mlock.o)
+ .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-mlock.o)
+ .text 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-mprec.o)
+ .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-mprec.o)
+ .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-mprec.o)
+ .text._Balloc 0x00000000 0x70 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-mprec.o)
+ .text._Bfree 0x00000000 0x32 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-mprec.o)
+ .text.__multadd
+ 0x00000000 0x78 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-mprec.o)
+ .text.__s2b 0x00000000 0x7e c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-mprec.o)
+ .text.__hi0bits
+ 0x00000000 0x34 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-mprec.o)
+ .text.__lo0bits
+ 0x00000000 0x5e c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-mprec.o)
+ .text.__i2b 0x00000000 0x12 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-mprec.o)
+ .text.__multiply
+ 0x00000000 0x11e c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-mprec.o)
+ .text.__pow5mult
+ 0x00000000 0xa4 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-mprec.o)
+ .text.__lshift
+ 0x00000000 0xa2 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-mprec.o)
+ .text.__mcmp 0x00000000 0x32 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-mprec.o)
+ .text.__mdiff 0x00000000 0xc8 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-mprec.o)
+ .text.__ulp 0x00000000 0x4c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-mprec.o)
+ .text.__b2d 0x00000000 0x98 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-mprec.o)
+ .text.__d2b 0x00000000 0xa8 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-mprec.o)
+ .text.__ratio 0x00000000 0x4e c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-mprec.o)
+ .text._mprec_log10
+ 0x00000000 0x34 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-mprec.o)
+ .text.__copybits
+ 0x00000000 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-mprec.o)
+ .text.__any_on
+ 0x00000000 0x44 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-mprec.o)
+ .rodata.__mprec_bigtens
+ 0x00000000 0x28 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-mprec.o)
+ .rodata.__mprec_tens
+ 0x00000000 0xc8 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-mprec.o)
+ .rodata.__mprec_tinytens
+ 0x00000000 0x28 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-mprec.o)
+ .rodata.p05.6047
+ 0x00000000 0xc c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-mprec.o)
+ .debug_frame 0x00000000 0x238 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-mprec.o)
+ .ARM.attributes
+ 0x00000000 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-mprec.o)
+ .text 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-callocr.o)
+ .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-callocr.o)
+ .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-callocr.o)
+ .text._calloc_r
+ 0x00000000 0x1c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-callocr.o)
+ .debug_frame 0x00000000 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-callocr.o)
+ .ARM.attributes
+ 0x00000000 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-callocr.o)
+ .text 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-reallocr.o)
+ .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-reallocr.o)
+ .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-reallocr.o)
+ .text._realloc_r
+ 0x00000000 0x4c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-reallocr.o)
+ .debug_frame 0x00000000 0x30 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-reallocr.o)
+ .ARM.attributes
+ 0x00000000 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-reallocr.o)
+ .text 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-svfprintf.o)
+ .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-svfprintf.o)
+ .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-svfprintf.o)
+ .text.__ssputs_r
+ 0x00000000 0xc4 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-svfprintf.o)
+ .text.__ssprint_r
+ 0x00000000 0xfc c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-svfprintf.o)
+ .text._svfprintf_r
+ 0x00000000 0x208 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-svfprintf.o)
+ .rodata._svfprintf_r.str1.1
+ 0x00000000 0x11 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-svfprintf.o)
+ .debug_frame 0x00000000 0x74 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-svfprintf.o)
+ .ARM.attributes
+ 0x00000000 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-svfprintf.o)
+ .text 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-reent.o)
+ .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-reent.o)
+ .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-reent.o)
+ .text.cleanup_glue
+ 0x00000000 0x1a c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-reent.o)
+ .text._reclaim_reent
+ 0x00000000 0xcc c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-reent.o)
+ .text 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-sf_nan.o)
+ .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-sf_nan.o)
+ .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-sf_nan.o)
+ .text.nanf 0x00000000 0x8 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-sf_nan.o)
+ .debug_frame 0x00000000 0x20 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-sf_nan.o)
+ .ARM.attributes
+ 0x00000000 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-sf_nan.o)
+ .text 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-msizer.o)
+ .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-msizer.o)
+ .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-msizer.o)
+ .text._malloc_usable_size_r
+ 0x00000000 0x10 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-msizer.o)
+ .debug_frame 0x00000000 0x20 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-msizer.o)
+ .ARM.attributes
+ 0x00000000 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-msizer.o)
+ .text 0x00000000 0x74 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_arm_cmpsf2.o)
+ .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_arm_cmpsf2.o)
+ .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_arm_cmpsf2.o)
+ .ARM.attributes
+ 0x00000000 0x1e c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_arm_cmpsf2.o)
+ .text 0x00000000 0x4c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(eqsf2.o)
+ .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(eqsf2.o)
+ .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(eqsf2.o)
+ .debug_frame 0x00000000 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(eqsf2.o)
+ .ARM.attributes
+ 0x00000000 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(eqsf2.o)
+ .text 0x00000000 0x80 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(gesf2.o)
+ .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(gesf2.o)
+ .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(gesf2.o)
+ .debug_frame 0x00000000 0x30 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(gesf2.o)
+ .ARM.attributes
+ 0x00000000 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(gesf2.o)
+ .text 0x00000000 0x84 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(lesf2.o)
+ .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(lesf2.o)
+ .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(lesf2.o)
+ .debug_frame 0x00000000 0x30 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(lesf2.o)
+ .ARM.attributes
+ 0x00000000 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(lesf2.o)
+ .text 0x00000000 0x30 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(unordsf2.o)
+ .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(unordsf2.o)
+ .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(unordsf2.o)
+ .debug_frame 0x00000000 0x20 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(unordsf2.o)
+ .ARM.attributes
+ 0x00000000 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(unordsf2.o)
+ .text 0x00000000 0x84 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(floatsidf.o)
+ .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(floatsidf.o)
+ .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(floatsidf.o)
+ .debug_frame 0x00000000 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(floatsidf.o)
+ .ARM.attributes
+ 0x00000000 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(floatsidf.o)
+ .text 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libnosys.a(sbrk.o)
+ .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libnosys.a(sbrk.o)
+ .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libnosys.a(sbrk.o)
+ .text 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libnosys.a(_exit.o)
+ .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libnosys.a(_exit.o)
+ .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libnosys.a(_exit.o)
+ .text._exit 0x00000000 0x4 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libnosys.a(_exit.o)
+ .debug_frame 0x00000000 0x20 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libnosys.a(_exit.o)
+ .ARM.attributes
+ 0x00000000 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libnosys.a(_exit.o)
+ .text 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crtend.o
+ .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crtend.o
+ .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crtend.o
+ .text 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crtn.o
+ .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crtn.o
+ .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crtn.o
+
+Memory Configuration
+
+Name Origin Length Attributes
+FLASH 0x00000000 0x00040000 xr
+RAM 0x20000000 0x00008000 xrw
+*default* 0x00000000 0xffffffff
+
+Linker script and memory map
+
+LOAD c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crti.o
+LOAD c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crtbegin.o
+LOAD c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/crt0.o
+LOAD Sketch.o
+START GROUP
+LOAD C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a
+END GROUP
+LOAD c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libstdc++_nano.a
+LOAD c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libm.a
+START GROUP
+LOAD c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a
+LOAD c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a
+END GROUP
+START GROUP
+LOAD c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a
+LOAD c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a
+LOAD c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libnosys.a
+END GROUP
+START GROUP
+LOAD c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a
+LOAD c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a
+LOAD c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libnosys.a
+END GROUP
+LOAD c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crtend.o
+LOAD c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crtn.o
+
+.text 0x00000000 0x2f3c
+ 0x00000000 __text_start__ = .
+ *(.isr_vector)
+ .isr_vector 0x00000000 0xb4 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ 0x00000000 exception_table
+ *(.text*)
+ .text 0x000000b4 0x60 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crtbegin.o
+ .text.setup 0x00000114 0x20 Sketch.o
+ 0x00000114 setup
+ .text.loop 0x00000134 0x28 Sketch.o
+ 0x00000134 loop
+ .text.Dummy_Handler
+ 0x0000015c 0x4 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ 0x0000015c DMAC_Handler
+ 0x0000015c HardFault_Handler
+ 0x0000015c AC_Handler
+ 0x0000015c PendSV_Handler
+ 0x0000015c NMI_Handler
+ 0x0000015c TC7_Handler
+ 0x0000015c SERCOM1_Handler
+ 0x0000015c ADC_Handler
+ 0x0000015c TCC1_Handler
+ 0x0000015c SERCOM2_Handler
+ 0x0000015c TCC0_Handler
+ 0x0000015c RTC_Handler
+ 0x0000015c EIC_Handler
+ 0x0000015c TC6_Handler
+ 0x0000015c WDT_Handler
+ 0x0000015c TC4_Handler
+ 0x0000015c TC3_Handler
+ 0x0000015c Dummy_Handler
+ 0x0000015c PM_Handler
+ 0x0000015c SVC_Handler
+ 0x0000015c TCC2_Handler
+ 0x0000015c EVSYS_Handler
+ 0x0000015c SERCOM3_Handler
+ 0x0000015c SERCOM4_Handler
+ 0x0000015c I2S_Handler
+ 0x0000015c NVMCTRL_Handler
+ 0x0000015c DAC_Handler
+ 0x0000015c PTC_Handler
+ 0x0000015c SYSCTRL_Handler
+ .text.USB_Handler
+ 0x00000160 0x14 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ 0x00000160 USB_Handler
+ .text.Reset_Handler
+ 0x00000174 0x54 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ 0x00000174 Reset_Handler
+ .text.SysTick_Handler
+ 0x000001c8 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ 0x000001c8 SysTick_Handler
+ .text.USB_SetHandler
+ 0x000001d8 0xc C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ 0x000001d8 USB_SetHandler
+ .text.millis 0x000001e4 0xc C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ 0x000001e4 millis
+ .text.micros 0x000001f0 0x60 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ 0x000001f0 micros
+ .text.delay 0x00000250 0x30 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ 0x00000250 delay
+ .text.resetExternalChip
+ 0x00000280 0x2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ 0x00000280 resetExternalChip
+ *fill* 0x00000282 0x2
+ .text.SysTick_DefaultHandler
+ 0x00000284 0x14 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ 0x00000284 SysTick_DefaultHandler
+ .text.__empty 0x00000298 0x2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(hooks.o)
+ 0x00000298 yield
+ .text.__false 0x0000029a 0x4 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(hooks.o)
+ 0x0000029a sysTickHook
+ .text._Z11initVariantv
+ 0x0000029e 0x2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ 0x0000029e initVariant()
+ .text.startup.main
+ 0x000002a0 0x40 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ 0x000002a0 main
+ .text.initiateReset
+ 0x000002e0 0x14 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ 0x000002e0 initiateReset
+ .text.cancelReset
+ 0x000002f4 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ 0x000002f4 cancelReset
+ .text.tickReset
+ 0x00000304 0x78 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ 0x00000304 tickReset
+ .text.SystemInit
+ 0x0000037c 0x15c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ 0x0000037c SystemInit
+ .text._ZN6Stream9timedPeekEv
+ 0x000004d8 0x2a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ 0x000004d8 Stream::timedPeek()
+ *fill* 0x00000502 0x2
+ .text._ZN6Stream13peekNextDigitE13LookaheadModeb
+ 0x00000504 0x54 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ 0x00000504 Stream::peekNextDigit(LookaheadMode, bool)
+ .text._ZN6Stream8parseIntE13LookaheadModec
+ 0x00000558 0x54 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ 0x00000558 Stream::parseInt(LookaheadMode, char)
+ .text._ZN7Serial_13getDescriptorER8USBSetup
+ 0x000005ac 0x4 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ 0x000005ac Serial_::getDescriptor(USBSetup&)
+ .text._ZThn16_N7Serial_13getDescriptorER8USBSetup
+ 0x000005b0 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ 0x000005b0 non-virtual thunk to Serial_::getDescriptor(USBSetup&)
+ .text._ZL5utox8mPc
+ 0x000005c0 0x24 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .text._ZN7Serial_12getShortNameEPc
+ 0x000005e4 0x44 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ 0x000005e4 Serial_::getShortName(char*)
+ .text._ZThn16_N7Serial_12getShortNameEPc
+ 0x00000628 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ 0x00000628 non-virtual thunk to Serial_::getShortName(char*)
+ .text._ZN7Serial_14handleEndpointEi
+ 0x00000638 0x2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ 0x00000638 Serial_::handleEndpoint(int)
+ *fill* 0x0000063a 0x2
+ .text._ZThn16_N7Serial_14handleEndpointEi
+ 0x0000063c 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ 0x0000063c non-virtual thunk to Serial_::handleEndpoint(int)
+ .text._ZN7Serial_17availableForWriteEv
+ 0x0000064c 0x4 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ 0x0000064c Serial_::availableForWrite()
+ .text._ZN7Serial_5writeEh
+ 0x00000650 0x14 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ 0x00000650 Serial_::write(unsigned char)
+ .text._ZN7Serial_12getInterfaceEPh
+ 0x00000664 0x128 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ 0x00000664 Serial_::getInterface(unsigned char*)
+ .text._ZThn16_N7Serial_12getInterfaceEPh
+ 0x0000078c 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ 0x0000078c non-virtual thunk to Serial_::getInterface(unsigned char*)
+ .text._ZN7Serial_5setupER8USBSetup
+ 0x0000079c 0xa8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ 0x0000079c Serial_::setup(USBSetup&)
+ .text._ZThn16_N7Serial_5setupER8USBSetup
+ 0x00000844 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ 0x00000844 non-virtual thunk to Serial_::setup(USBSetup&)
+ .text._ZN7Serial_9availableEv
+ 0x00000854 0x20 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ 0x00000854 Serial_::available()
+ .text._ZN7Serial_5flushEv
+ 0x00000874 0xe C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ 0x00000874 Serial_::flush()
+ .text._ZN7Serial_5clearEv
+ 0x00000882 0xe C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ 0x00000882 Serial_::clear()
+ .text._ZN7Serial_5writeEPKhj
+ 0x00000890 0x1e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ 0x00000890 Serial_::write(unsigned char const*, unsigned int)
+ *fill* 0x000008ae 0x2
+ .text._ZN7Serial_4peekEv
+ 0x000008b0 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ 0x000008b0 Serial_::peek()
+ .text._ZN7Serial_4readEv
+ 0x000008cc 0x24 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ 0x000008cc Serial_::read()
+ .text._ZN7Serial_C2ER14USBDeviceClass
+ 0x000008f0 0x50 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ 0x000008f0 Serial_::Serial_(USBDeviceClass&)
+ 0x000008f0 Serial_::Serial_(USBDeviceClass&)
+ .text._ZN7Serial_15enableInterruptEv
+ 0x00000940 0x30 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ 0x00000940 Serial_::enableInterrupt()
+ .text._ZN7Serial_5beginEm
+ 0x00000970 0x2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ 0x00000970 Serial_::begin(unsigned long)
+ *fill* 0x00000972 0x2
+ .text.startup._GLOBAL__sub_I__ZN7Serial_12getInterfaceEPh
+ 0x00000974 0x14 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .text._ZN13PluggableUSB_12getInterfaceEPh
+ 0x00000988 0x28 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ 0x00000988 PluggableUSB_::getInterface(unsigned char*)
+ .text._ZN13PluggableUSB_13getDescriptorER8USBSetup
+ 0x000009b0 0x20 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ 0x000009b0 PluggableUSB_::getDescriptor(USBSetup&)
+ .text._ZN13PluggableUSB_12getShortNameEPc
+ 0x000009d0 0x26 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ 0x000009d0 PluggableUSB_::getShortName(char*)
+ .text._ZN13PluggableUSB_5setupER8USBSetup
+ 0x000009f6 0x20 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ 0x000009f6 PluggableUSB_::setup(USBSetup&)
+ .text._ZN13PluggableUSB_14handleEndpointEi
+ 0x00000a16 0x1a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ 0x00000a16 PluggableUSB_::handleEndpoint(int)
+ .text._ZN13PluggableUSB_4plugEP18PluggableUSBModule
+ 0x00000a30 0x58 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ 0x00000a30 PluggableUSB_::plug(PluggableUSBModule*)
+ .text._Z12PluggableUSBv
+ 0x00000a88 0x20 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ 0x00000a88 PluggableUSB()
+ .text._ZN26DoubleBufferedEPOutHandlerD2Ev
+ 0x00000aa8 0x2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ 0x00000aa8 DoubleBufferedEPOutHandler::~DoubleBufferedEPOutHandler()
+ 0x00000aa8 DoubleBufferedEPOutHandler::~DoubleBufferedEPOutHandler()
+ .text._ZN26DoubleBufferedEPOutHandlerD0Ev
+ 0x00000aaa 0xc C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ 0x00000aaa DoubleBufferedEPOutHandler::~DoubleBufferedEPOutHandler()
+ *fill* 0x00000ab6 0x2
+ .text._ZN14USBDeviceClass6initEPEmm.part.7
+ 0x00000ab8 0xc4 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .text._ZN7__GuardC2Ev
+ 0x00000b7c 0xe C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ 0x00000b7c __Guard::__Guard()
+ 0x00000b7c __Guard::__Guard()
+ .text._ZN7__GuardD2Ev
+ 0x00000b8a 0xe C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ 0x00000b8a __Guard::~__Guard()
+ 0x00000b8a __Guard::~__Guard()
+ .text._ZNK26DoubleBufferedEPOutHandler10_availableEv
+ 0x00000b98 0x70 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ 0x00000b98 DoubleBufferedEPOutHandler::_available() const
+ .text._ZN26DoubleBufferedEPOutHandler7releaseEv
+ 0x00000c08 0x3c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ 0x00000c08 DoubleBufferedEPOutHandler::release()
+ .text._ZN26DoubleBufferedEPOutHandler14handleEndpointEv
+ 0x00000c44 0xe8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ 0x00000c44 DoubleBufferedEPOutHandler::handleEndpoint()
+ .text._ZN26DoubleBufferedEPOutHandler5_recvEv
+ 0x00000d2c 0x194 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ 0x00000d2c DoubleBufferedEPOutHandler::_recv()
+ .text._ZN26DoubleBufferedEPOutHandler4peekEv
+ 0x00000ec0 0x22 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ 0x00000ec0 DoubleBufferedEPOutHandler::peek()
+ .text._ZN26DoubleBufferedEPOutHandler9availableEv
+ 0x00000ee2 0x18 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ 0x00000ee2 DoubleBufferedEPOutHandler::available()
+ .text._ZN26DoubleBufferedEPOutHandler4recvEPvm
+ 0x00000efa 0x6c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ 0x00000efa DoubleBufferedEPOutHandler::recv(void*, unsigned long)
+ .text._ZN14USBDeviceClass14SendInterfacesEPm
+ 0x00000f66 0x20 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ 0x00000f66 USBDeviceClass::SendInterfaces(unsigned long*)
+ *fill* 0x00000f86 0x2
+ .text._ZN14USBDeviceClass4initEv
+ 0x00000f88 0x134 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ 0x00000f88 USBDeviceClass::init()
+ .text._ZN14USBDeviceClass6attachEv
+ 0x000010bc 0x34 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ 0x000010bc USBDeviceClass::attach()
+ .text._ZN14USBDeviceClass10setAddressEm
+ 0x000010f0 0x48 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ 0x000010f0 USBDeviceClass::setAddress(unsigned long)
+ .text._ZN14USBDeviceClass25handleClassInterfaceSetupER8USBSetup
+ 0x00001138 0x24 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ 0x00001138 USBDeviceClass::handleClassInterfaceSetup(USBSetup&)
+ .text._ZN14USBDeviceClass6initEPEmm
+ 0x0000115c 0x104 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ 0x0000115c USBDeviceClass::initEP(unsigned long, unsigned long)
+ .text._ZN14USBDeviceClass13initEndpointsEv
+ 0x00001260 0x24 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ 0x00001260 USBDeviceClass::initEndpoints()
+ .text._ZN14USBDeviceClass5clearEm
+ 0x00001284 0x38 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ 0x00001284 USBDeviceClass::clear(unsigned long)
+ .text._ZN14USBDeviceClass9availableEm
+ 0x000012bc 0x2c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ 0x000012bc USBDeviceClass::available(unsigned long)
+ .text._ZN14USBDeviceClass5flushEm
+ 0x000012e8 0x2c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ 0x000012e8 USBDeviceClass::flush(unsigned long)
+ .text._ZN14USBDeviceClass4recvEmPvm
+ 0x00001314 0xc4 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ 0x00001314 USBDeviceClass::recv(unsigned long, void*, unsigned long)
+ .text._ZN14USBDeviceClass4recvEm
+ 0x000013d8 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ 0x000013d8 USBDeviceClass::recv(unsigned long)
+ .text._ZN14USBDeviceClass14armRecvCtrlOUTEm
+ 0x000013f4 0x5c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ 0x000013f4 USBDeviceClass::armRecvCtrlOUT(unsigned long)
+ .text._ZN14USBDeviceClass11recvControlEPvm
+ 0x00001450 0x28 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ 0x00001450 USBDeviceClass::recvControl(void*, unsigned long)
+ .text._ZN14USBDeviceClass4sendEmPKvm
+ 0x00001478 0x10c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ 0x00001478 USBDeviceClass::send(unsigned long, void const*, unsigned long)
+ .text._ZN14USBDeviceClass7armSendEmPKvm
+ 0x00001584 0x48 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ 0x00001584 USBDeviceClass::armSend(unsigned long, void const*, unsigned long)
+ .text._ZN14USBDeviceClass11sendControlEPKvm
+ 0x000015cc 0x54 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ 0x000015cc USBDeviceClass::sendControl(void const*, unsigned long)
+ .text._ZN14USBDeviceClass20sendStringDescriptorEPKhm
+ 0x00001620 0x64 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ 0x00001620 USBDeviceClass::sendStringDescriptor(unsigned char const*, unsigned long)
+ .text._ZN14USBDeviceClass17sendConfigurationEm
+ 0x00001684 0x94 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ 0x00001684 USBDeviceClass::sendConfiguration(unsigned long)
+ .text._ZN14USBDeviceClass14sendDescriptorER8USBSetup
+ 0x00001718 0xe0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ 0x00001718 USBDeviceClass::sendDescriptor(USBSetup&)
+ .text._ZN14USBDeviceClass7sendZlpEm
+ 0x000017f8 0x18 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ 0x000017f8 USBDeviceClass::sendZlp(unsigned long)
+ .text._ZN14USBDeviceClass19handleStandardSetupER8USBSetup
+ 0x00001810 0xf4 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ 0x00001810 USBDeviceClass::handleStandardSetup(USBSetup&)
+ .text._ZN14USBDeviceClass10ISRHandlerEv
+ 0x00001904 0x108 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ 0x00001904 USBDeviceClass::ISRHandler()
+ .text.UDD_Handler
+ 0x00001a0c 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ 0x00001a0c UDD_Handler
+ .text.startup._GLOBAL__sub_I_usbd
+ 0x00001a1c 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .text.init 0x00001a2c 0xf0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ 0x00001a2c init
+ .text.mapResolution
+ 0x00001b1c 0x12 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ *fill* 0x00001b2e 0x2
+ .text.analogWriteResolution
+ 0x00001b30 0xc C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ 0x00001b30 analogWriteResolution
+ .text.analogReference
+ 0x00001b3c 0x64 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ 0x00001b3c analogReference
+ .text.analogWrite
+ 0x00001ba0 0x1e0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ 0x00001ba0 analogWrite
+ .text.pinMode 0x00001d80 0x98 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ 0x00001d80 pinMode
+ .text.digitalWrite
+ 0x00001e18 0x58 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ 0x00001e18 digitalWrite
+ .text.pinPeripheral
+ 0x00001e70 0xbc C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ 0x00001e70 pinPeripheral
+ .text.SERCOM0_Handler
+ 0x00001f2c 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ 0x00001f2c SERCOM0_Handler
+ .text.SERCOM5_Handler
+ 0x00001f3c 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ 0x00001f3c SERCOM5_Handler
+ .text.startup._GLOBAL__sub_I_g_APinDescription
+ 0x00001f4c 0x94 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .text._Znwj 0x00001fe0 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(new.o)
+ 0x00001fe0 operator new(unsigned int)
+ .text._ZdlPv 0x00001fe8 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(new.o)
+ 0x00001fe8 operator delete(void*)
+ .text._ZN6SERCOMC2EP6Sercom
+ 0x00001ff0 0x4 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ 0x00001ff0 SERCOM::SERCOM(Sercom*)
+ 0x00001ff0 SERCOM::SERCOM(Sercom*)
+ .text._ZN6SERCOM9initFrameE18SercomUartCharSize15SercomDataOrder16SercomParityMode19SercomNumberStopBit
+ 0x00001ff4 0x34 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ 0x00001ff4 SERCOM::initFrame(SercomUartCharSize, SercomDataOrder, SercomParityMode, SercomNumberStopBit)
+ .text._ZN6SERCOM8initPadsE15SercomUartTXPad11SercomRXPad
+ 0x00002028 0x24 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ 0x00002028 SERCOM::initPads(SercomUartTXPad, SercomRXPad)
+ .text._ZN6SERCOM9resetUARTEv
+ 0x0000204c 0x18 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ 0x0000204c SERCOM::resetUART()
+ .text._ZN6SERCOM10enableUARTEv
+ 0x00002064 0x12 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ 0x00002064 SERCOM::enableUART()
+ .text._ZN6SERCOM9flushUARTEv
+ 0x00002076 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ 0x00002076 SERCOM::flushUART()
+ .text._ZN6SERCOM15clearStatusUARTEv
+ 0x00002086 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ 0x00002086 SERCOM::clearStatusUART()
+ .text._ZN6SERCOM17availableDataUARTEv
+ 0x0000208e 0xa C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ 0x0000208e SERCOM::availableDataUART()
+ .text._ZN6SERCOM11isUARTErrorEv
+ 0x00002098 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ 0x00002098 SERCOM::isUARTError()
+ .text._ZN6SERCOM20acknowledgeUARTErrorEv
+ 0x000020a0 0xe C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ 0x000020a0 SERCOM::acknowledgeUARTError()
+ .text._ZN6SERCOM16isFrameErrorUARTEv
+ 0x000020ae 0xa C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ 0x000020ae SERCOM::isFrameErrorUART()
+ .text._ZN6SERCOM19clearFrameErrorUARTEv
+ 0x000020b8 0xc C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ 0x000020b8 SERCOM::clearFrameErrorUART()
+ .text._ZN6SERCOM23isDataRegisterEmptyUARTEv
+ 0x000020c4 0xa C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ 0x000020c4 SERCOM::isDataRegisterEmptyUART()
+ .text._ZN6SERCOM12readDataUARTEv
+ 0x000020ce 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ 0x000020ce SERCOM::readDataUART()
+ .text._ZN6SERCOM13writeDataUARTEh
+ 0x000020d6 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ 0x000020d6 SERCOM::writeDataUART(unsigned char)
+ .text._ZN6SERCOM36enableDataRegisterEmptyInterruptUARTEv
+ 0x000020e6 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ 0x000020e6 SERCOM::enableDataRegisterEmptyInterruptUART()
+ .text._ZN6SERCOM37disableDataRegisterEmptyInterruptUARTEv
+ 0x000020ee 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ 0x000020ee SERCOM::disableDataRegisterEmptyInterruptUART()
+ *fill* 0x000020f6 0x2
+ .text._ZN6SERCOM13initClockNVICEv
+ 0x000020f8 0xa8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ 0x000020f8 SERCOM::initClockNVIC()
+ .text._ZN6SERCOM8initUARTE14SercomUartMode20SercomUartSampleRatem
+ 0x000021a0 0x64 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ 0x000021a0 SERCOM::initUART(SercomUartMode, SercomUartSampleRate, unsigned long)
+ .text._ZN4UartcvbEv
+ 0x00002204 0x4 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ 0x00002204 Uart::operator bool()
+ .text._ZN4Uart5beginEm
+ 0x00002208 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ 0x00002208 Uart::begin(unsigned long)
+ .text._ZN4Uart4peekEv
+ 0x00002218 0x1a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ 0x00002218 Uart::peek()
+ .text._ZN4Uart3endEv
+ 0x00002232 0x20 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ 0x00002232 Uart::end()
+ .text._ZN4Uart16extractNbStopBitEt
+ 0x00002252 0xc C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ 0x00002252 Uart::extractNbStopBit(unsigned short)
+ .text._ZN4Uart15extractCharSizeEt
+ 0x0000225e 0x28 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ 0x0000225e Uart::extractCharSize(unsigned short)
+ .text._ZN4Uart13extractParityEt
+ 0x00002286 0x14 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ 0x00002286 Uart::extractParity(unsigned short)
+ *fill* 0x0000229a 0x2
+ .text._ZN4Uart5beginEmt
+ 0x0000229c 0xf8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ 0x0000229c Uart::begin(unsigned long, unsigned short)
+ .text._ZN11RingBufferNILi256EEC2Ev
+ 0x00002394 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ 0x00002394 RingBufferN<256>::RingBufferN()
+ 0x00002394 RingBufferN<256>::RingBufferN()
+ .text._ZN4UartC2EP6SERCOMhh11SercomRXPad15SercomUartTXPad
+ 0x000023b0 0x74 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ 0x000023b0 Uart::Uart(SERCOM*, unsigned char, unsigned char, SercomRXPad, SercomUartTXPad)
+ 0x000023b0 Uart::Uart(SERCOM*, unsigned char, unsigned char, SercomRXPad, SercomUartTXPad)
+ .text._ZN11RingBufferNILi256EE9availableEv
+ 0x00002424 0x12 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ 0x00002424 RingBufferN<256>::available()
+ .text._ZN4Uart5flushEv
+ 0x00002436 0x1a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ 0x00002436 Uart::flush()
+ .text._ZN4Uart9availableEv
+ 0x00002450 0xa C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ 0x00002450 Uart::available()
+ .text._ZN11RingBufferNILi256EE17availableForStoreEv
+ 0x0000245a 0x20 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ 0x0000245a RingBufferN<256>::availableForStore()
+ .text._ZN4Uart17availableForWriteEv
+ 0x0000247a 0xc C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ 0x0000247a Uart::availableForWrite()
+ .text._ZN4Uart10IrqHandlerEv
+ 0x00002486 0xcc C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ 0x00002486 Uart::IrqHandler()
+ *fill* 0x00002552 0x2
+ .text._ZN4Uart5writeEh
+ 0x00002554 0xb4 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ 0x00002554 Uart::write(unsigned char)
+ .text._ZN4Uart4readEv
+ 0x00002608 0x4c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ 0x00002608 Uart::read()
+ .text._ZN5Print5writeEPKhj
+ 0x00002654 0x28 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ 0x00002654 Print::write(unsigned char const*, unsigned int)
+ .text 0x0000267c 0x14 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_thumb1_case_uqi.o)
+ 0x0000267c __gnu_thumb1_case_uqi
+ .text 0x00002690 0x114 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_udivsi3.o)
+ 0x00002690 __aeabi_uidiv
+ 0x00002690 __udivsi3
+ 0x0000279c __aeabi_uidivmod
+ .text 0x000027a4 0x4 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_dvmd_tls.o)
+ 0x000027a4 __aeabi_idiv0
+ 0x000027a4 __aeabi_ldiv0
+ .text.__libc_init_array
+ 0x000027a8 0x48 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-init.o)
+ 0x000027a8 __libc_init_array
+ .text.malloc 0x000027f0 0x14 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-malloc.o)
+ 0x000027f0 malloc
+ .text.free 0x00002804 0x14 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-malloc.o)
+ 0x00002804 free
+ .text.memcpy 0x00002818 0x12 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-memcpy-stub.o)
+ 0x00002818 memcpy
+ .text.memset 0x0000282a 0x10 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-memset.o)
+ 0x0000282a memset
+ *fill* 0x0000283a 0x2
+ .text._free_r 0x0000283c 0x94 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-freer.o)
+ 0x0000283c _free_r
+ .text._malloc_r
+ 0x000028d0 0xbc c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-mallocr.o)
+ 0x000028d0 _malloc_r
+ .text._sbrk_r 0x0000298c 0x24 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-sbrkr.o)
+ 0x0000298c _sbrk_r
+ .text 0x000029b0 0xe c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strlen.o)
+ 0x000029b0 strlen
+ .text.__malloc_lock
+ 0x000029be 0x2 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-mlock.o)
+ 0x000029be __malloc_lock
+ .text.__malloc_unlock
+ 0x000029c0 0x2 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-mlock.o)
+ 0x000029c0 __malloc_unlock
+ *fill* 0x000029c2 0x2
+ .text._sbrk 0x000029c4 0x1c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libnosys.a(sbrk.o)
+ 0x000029c4 _sbrk
+ *(.init)
+ .init 0x000029e0 0x4 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crti.o
+ 0x000029e0 _init
+ .init 0x000029e4 0x8 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crtn.o
+ *(.fini)
+ .fini 0x000029ec 0x4 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crti.o
+ 0x000029ec _fini
+ .fini 0x000029f0 0x8 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crtn.o
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend.o *crtend?.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend.o *crtend?.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+ *(.rodata*)
+ .rodata._ZTV7Serial_
+ 0x000029f8 0x58 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ 0x000029f8 vtable for Serial_
+ .rodata._ZTV26DoubleBufferedEPOutHandler
+ 0x00002a50 0x24 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ 0x00002a50 vtable for DoubleBufferedEPOutHandler
+ .rodata._ZL14STRING_PRODUCT
+ 0x00002a74 0x9 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ *fill* 0x00002a7d 0x1
+ .rodata._ZL15STRING_LANGUAGE
+ 0x00002a7e 0x4 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .rodata._ZL19STRING_MANUFACTURER
+ 0x00002a82 0xd C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .rodata._ZL21USB_DeviceDescriptorB
+ 0x00002a8f 0x12 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ *fill* 0x00002aa1 0x1
+ .rodata 0x00002aa2 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ *fill* 0x00002ab2 0x2
+ .rodata.g_APinDescription
+ 0x00002ab4 0x450 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ 0x00002ab4 g_APinDescription
+ .rodata._ZTV4Uart
+ 0x00002f04 0x34 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ 0x00002f04 vtable for Uart
+ *(.eh_frame*)
+ .eh_frame 0x00002f38 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crtbegin.o
+ .eh_frame 0x00002f38 0x4 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crtend.o
+
+.glue_7 0x00002f3c 0x0
+ .glue_7 0x00002f3c 0x0 linker stubs
+
+.glue_7t 0x00002f3c 0x0
+ .glue_7t 0x00002f3c 0x0 linker stubs
+
+.vfp11_veneer 0x00002f3c 0x0
+ .vfp11_veneer 0x00002f3c 0x0 linker stubs
+
+.v4_bx 0x00002f3c 0x0
+ .v4_bx 0x00002f3c 0x0 linker stubs
+
+.iplt 0x00002f3c 0x0
+ .iplt 0x00002f3c 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crtbegin.o
+
+.rel.dyn 0x00002f3c 0x0
+ .rel.iplt 0x00002f3c 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crtbegin.o
+
+.ARM.extab
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ 0x00002f3c __exidx_start = .
+
+.ARM.exidx
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ 0x00002f3c __exidx_end = .
+ 0x00002f3c __etext = .
+
+.data 0x20000000 0xb0 load address 0x00002f3c
+ 0x20000000 __data_start__ = .
+ *(vtable)
+ *(.data*)
+ .data._ZL5ticks
+ 0x20000000 0x4 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .data._ZL10breakValue
+ 0x20000004 0x4 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .data._ZL12_usbLineInfo
+ 0x20000008 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .data._serialPeek
+ 0x20000010 0x4 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ 0x20000010 _serialPeek
+ .data.SystemCoreClock
+ 0x20000014 0x4 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ 0x20000014 SystemCoreClock
+ .data._writeResolution
+ 0x20000018 0x4 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .data.g_apTCInstances
+ 0x2000001c 0x18 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ 0x2000001c g_apTCInstances
+ .data._impure_ptr
+ 0x20000034 0x4 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-impure.o)
+ 0x20000034 _impure_ptr
+ .data.impure_data
+ 0x20000038 0x60 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-impure.o)
+ 0x20000098 . = ALIGN (0x4)
+ 0x20000098 PROVIDE (__preinit_array_start, .)
+ *(.preinit_array)
+ 0x20000098 PROVIDE (__preinit_array_end, .)
+ 0x20000098 . = ALIGN (0x4)
+ 0x20000098 PROVIDE (__init_array_start, .)
+ *(SORT(.init_array.*))
+ *(.init_array)
+ .init_array 0x20000098 0x4 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crtbegin.o
+ .init_array 0x2000009c 0x4 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .init_array 0x200000a0 0x4 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .init_array 0x200000a4 0x4 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ 0x200000a8 PROVIDE (__init_array_end, .)
+ 0x200000a8 . = ALIGN (0x4)
+ [!provide] PROVIDE (__fini_array_start, .)
+ *(SORT(.fini_array.*))
+ *(.fini_array)
+ .fini_array 0x200000a8 0x4 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crtbegin.o
+ [!provide] PROVIDE (__fini_array_end, .)
+ *(.jcr*)
+ .jcr 0x200000ac 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crtbegin.o
+ .jcr 0x200000ac 0x4 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crtend.o
+ 0x200000b0 . = ALIGN (0x10)
+ 0x200000b0 __data_end__ = .
+
+.igot.plt 0x200000b0 0x0 load address 0x00002fec
+ .igot.plt 0x200000b0 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crtbegin.o
+
+.bss 0x200000b0 0xaf0 load address 0x00002fec
+ 0x200000b0 . = ALIGN (0x4)
+ 0x200000b0 __bss_start__ = .
+ *(.bss*)
+ .bss 0x200000b0 0x1c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crtbegin.o
+ .bss.usb_isr 0x200000cc 0x4 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .bss._ulTickCount
+ 0x200000d0 0x4 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .bss.SerialUSB
+ 0x200000d4 0x34 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ 0x200000d4 SerialUSB
+ .bss._ZGVZ12PluggableUSBvE3obj
+ 0x20000108 0x4 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .bss._ZZ12PluggableUSBvE3obj
+ 0x2000010c 0x8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .bss.EndPoints
+ 0x20000114 0x28 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ 0x20000114 EndPoints
+ .bss.USBDevice
+ 0x2000013c 0x1 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ 0x2000013c USBDevice
+ *fill* 0x2000013d 0x3
+ .bss._ZL10epHandlers
+ 0x20000140 0x1c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .bss._ZL14isEndpointHalt
+ 0x2000015c 0x1 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .bss._ZL20LastTransmitTimedOut
+ 0x2000015d 0x7 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .bss._ZL21isRemoteWakeUpEnabled
+ 0x20000164 0x1 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ *fill* 0x20000165 0x3
+ .bss._ZL22udd_ep_in_cache_buffer
+ 0x20000168 0x1c0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .bss._ZL23udd_ep_out_cache_buffer
+ 0x20000328 0x1c0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .bss._dry_run 0x200004e8 0x1 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ 0x200004e8 _dry_run
+ .bss._pack_buffer
+ 0x200004e9 0x100 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ 0x200004e9 _pack_buffer
+ .bss._pack_message
+ 0x200005e9 0x1 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ 0x200005e9 _pack_message
+ .bss._pack_size
+ 0x200005ea 0x2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ 0x200005ea _pack_size
+ .bss._usbConfiguration
+ 0x200005ec 0x4 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ 0x200005ec _usbConfiguration
+ .bss._usbSetInterface
+ 0x200005f0 0x4 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ 0x200005f0 _usbSetInterface
+ .bss.usbd 0x200005f4 0x104 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ 0x200005f4 usbd
+ .bss.tcEnabled.12563
+ 0x200006f8 0x6 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ *fill* 0x200006fe 0x2
+ .bss.Serial 0x20000700 0x23c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ 0x20000700 Serial
+ .bss.Serial1 0x2000093c 0x23c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ 0x2000093c Serial1
+ .bss.sercom0 0x20000b78 0x4 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ 0x20000b78 sercom0
+ .bss.sercom1 0x20000b7c 0x4 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ 0x20000b7c sercom1
+ .bss.sercom2 0x20000b80 0x4 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ 0x20000b80 sercom2
+ .bss.sercom3 0x20000b84 0x4 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ 0x20000b84 sercom3
+ .bss.sercom4 0x20000b88 0x4 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ 0x20000b88 sercom4
+ .bss.sercom5 0x20000b8c 0x4 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ 0x20000b8c sercom5
+ .bss.__malloc_free_list
+ 0x20000b90 0x4 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-mallocr.o)
+ 0x20000b90 __malloc_free_list
+ .bss.__malloc_sbrk_start
+ 0x20000b94 0x4 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-mallocr.o)
+ 0x20000b94 __malloc_sbrk_start
+ .bss.heap_end.4116
+ 0x20000b98 0x4 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libnosys.a(sbrk.o)
+ *(COMMON)
+ COMMON 0x20000b9c 0x4 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-reent.o)
+ 0x20000b9c errno
+ 0x20000ba0 . = ALIGN (0x4)
+ 0x20000ba0 __bss_end__ = .
+
+.heap 0x20000ba0 0x0
+ 0x20000ba0 __end__ = .
+ 0x20000ba0 PROVIDE (end, .)
+ *(.heap*)
+ 0x20000ba0 __HeapLimit = .
+
+.stack_dummy 0x20000ba0 0x0
+ *(.stack*)
+ 0x20008000 __StackTop = (ORIGIN (RAM) + LENGTH (RAM))
+ 0x20008000 __StackLimit = (__StackTop - SIZEOF (.stack_dummy))
+ 0x20008000 PROVIDE (__stack, __StackTop)
+ 0x20007fff __ram_end__ = ((ORIGIN (RAM) + LENGTH (RAM)) - 0x1)
+ 0x00000001 ASSERT ((__StackLimit >= __HeapLimit), region RAM overflowed with stack)
+OUTPUT(UsbReceive.elf elf32-littlearm)
+
+.ARM.attributes
+ 0x00000000 0x28
+ .ARM.attributes
+ 0x00000000 0x1e c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crti.o
+ .ARM.attributes
+ 0x0000001e 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crtbegin.o
+ .ARM.attributes
+ 0x0000004a 0x32 Sketch.o
+ .ARM.attributes
+ 0x0000007c 0x32 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .ARM.attributes
+ 0x000000ae 0x32 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .ARM.attributes
+ 0x000000e0 0x32 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(hooks.o)
+ .ARM.attributes
+ 0x00000112 0x32 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .ARM.attributes
+ 0x00000144 0x32 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .ARM.attributes
+ 0x00000176 0x32 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .ARM.attributes
+ 0x000001a8 0x32 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .ARM.attributes
+ 0x000001da 0x32 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .ARM.attributes
+ 0x0000020c 0x32 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .ARM.attributes
+ 0x0000023e 0x32 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .ARM.attributes
+ 0x00000270 0x32 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .ARM.attributes
+ 0x000002a2 0x32 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .ARM.attributes
+ 0x000002d4 0x32 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .ARM.attributes
+ 0x00000306 0x32 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .ARM.attributes
+ 0x00000338 0x32 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .ARM.attributes
+ 0x0000036a 0x32 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(new.o)
+ .ARM.attributes
+ 0x0000039c 0x32 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .ARM.attributes
+ 0x000003ce 0x32 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .ARM.attributes
+ 0x00000400 0x32 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .ARM.attributes
+ 0x00000432 0x1e c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_thumb1_case_uqi.o)
+ .ARM.attributes
+ 0x00000450 0x1e c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_udivsi3.o)
+ .ARM.attributes
+ 0x0000046e 0x1e c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_dvmd_tls.o)
+ .ARM.attributes
+ 0x0000048c 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-impure.o)
+ .ARM.attributes
+ 0x000004b8 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-init.o)
+ .ARM.attributes
+ 0x000004e4 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-malloc.o)
+ .ARM.attributes
+ 0x00000510 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-memcpy-stub.o)
+ .ARM.attributes
+ 0x0000053c 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-memset.o)
+ .ARM.attributes
+ 0x00000568 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-freer.o)
+ .ARM.attributes
+ 0x00000594 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-mallocr.o)
+ .ARM.attributes
+ 0x000005c0 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-sbrkr.o)
+ .ARM.attributes
+ 0x000005ec 0x1c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strlen.o)
+ .ARM.attributes
+ 0x00000608 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-mlock.o)
+ .ARM.attributes
+ 0x00000634 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-reent.o)
+ .ARM.attributes
+ 0x00000660 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libnosys.a(sbrk.o)
+ .ARM.attributes
+ 0x0000068c 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crtend.o
+ .ARM.attributes
+ 0x000006b8 0x1e c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crtn.o
+
+.comment 0x00000000 0x59
+ .comment 0x00000000 0x59 Sketch.o
+ 0x5a (size before relaxing)
+ .comment 0x00000059 0x5a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .comment 0x00000059 0x5a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .comment 0x00000059 0x5a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(hooks.o)
+ .comment 0x00000059 0x5a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .comment 0x00000059 0x5a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .comment 0x00000059 0x5a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .comment 0x00000059 0x5a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .comment 0x00000059 0x5a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .comment 0x00000059 0x5a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .comment 0x00000059 0x5a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .comment 0x00000059 0x5a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .comment 0x00000059 0x5a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .comment 0x00000059 0x5a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .comment 0x00000059 0x5a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .comment 0x00000059 0x5a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .comment 0x00000059 0x5a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(new.o)
+ .comment 0x00000059 0x5a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .comment 0x00000059 0x5a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .comment 0x00000059 0x5a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+
+.debug_info 0x00000000 0x5bc66
+ .debug_info 0x00000000 0x5dd6 Sketch.o
+ .debug_info 0x00005dd6 0x127c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_info 0x00007052 0x14e9 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_info 0x0000853b 0x72 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(hooks.o)
+ .debug_info 0x000085ad 0x485b C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_info 0x0000ce08 0x4e62 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_info 0x00011c6a 0x3898 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_info 0x00015502 0x673a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_info 0x0001bc3c 0x9c1b C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_info 0x00025857 0x1c76 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .debug_info 0x000274cd 0xcbd5 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_info 0x000340a2 0x3054 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_info 0x000370f6 0x5499 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_info 0x0003c58f 0x1970 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_info 0x0003deff 0x1953 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_info 0x0003f852 0x6b4b C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_info 0x0004639d 0x107d C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(new.o)
+ .debug_info 0x0004741a 0x5e3d C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_info 0x0004d257 0x79d4 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_info 0x00054c2b 0x703b C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+
+.debug_abbrev 0x00000000 0x6748
+ .debug_abbrev 0x00000000 0x595 Sketch.o
+ .debug_abbrev 0x00000595 0x298 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_abbrev 0x0000082d 0x2d2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_abbrev 0x00000aff 0x4e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(hooks.o)
+ .debug_abbrev 0x00000b4d 0x4da C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_abbrev 0x00001027 0x589 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_abbrev 0x000015b0 0x28f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_abbrev 0x0000183f 0x740 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_abbrev 0x00001f7f 0xa50 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_abbrev 0x000029cf 0x51c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .debug_abbrev 0x00002eeb 0xbf5 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_abbrev 0x00003ae0 0x35c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_abbrev 0x00003e3c 0x450 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_abbrev 0x0000428c 0x2fd C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_abbrev 0x00004589 0x2ea C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_abbrev 0x00004873 0x4f2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_abbrev 0x00004d65 0x2e5 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(new.o)
+ .debug_abbrev 0x0000504a 0x75a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_abbrev 0x000057a4 0x815 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_abbrev 0x00005fb9 0x78f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+
+.debug_loc 0x00000000 0x8597
+ .debug_loc 0x00000000 0x5e Sketch.o
+ .debug_loc 0x0000005e 0x9c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_loc 0x000000fa 0x15b C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_loc 0x00000255 0x20 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_loc 0x00000275 0x6d C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_loc 0x000002e2 0x4e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_loc 0x00000330 0xdd4 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_loc 0x00001104 0xa78 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_loc 0x00001b7c 0x392 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .debug_loc 0x00001f0e 0x2b8b C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_loc 0x00004a99 0xcb C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_loc 0x00004b64 0x5d7 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_loc 0x0000513b 0x18c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_loc 0x000052c7 0x14e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_loc 0x00005415 0x8a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_loc 0x0000549f 0x82 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(new.o)
+ .debug_loc 0x00005521 0xd9d C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_loc 0x000062be 0xbde C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_loc 0x00006e9c 0x16fb C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+
+.debug_aranges 0x00000000 0x9a0
+ .debug_aranges
+ 0x00000000 0x28 Sketch.o
+ .debug_aranges
+ 0x00000028 0x40 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_aranges
+ 0x00000068 0x40 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_aranges
+ 0x000000a8 0x30 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(hooks.o)
+ .debug_aranges
+ 0x000000d8 0x28 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_aranges
+ 0x00000100 0x38 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_aranges
+ 0x00000138 0x20 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_aranges
+ 0x00000158 0x98 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_aranges
+ 0x000001f0 0x130 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_aranges
+ 0x00000320 0x58 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .debug_aranges
+ 0x00000378 0x178 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_aranges
+ 0x000004f0 0x20 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_aranges
+ 0x00000510 0x48 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_aranges
+ 0x00000558 0x30 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_aranges
+ 0x00000588 0x20 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_aranges
+ 0x000005a8 0x30 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_aranges
+ 0x000005d8 0x28 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(new.o)
+ .debug_aranges
+ 0x00000600 0x1f0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_aranges
+ 0x000007f0 0xb0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_aranges
+ 0x000008a0 0x100 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+
+.debug_ranges 0x00000000 0x14b0
+ .debug_ranges 0x00000000 0x18 Sketch.o
+ .debug_ranges 0x00000018 0x30 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_ranges 0x00000048 0x30 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_ranges 0x00000078 0x20 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(hooks.o)
+ .debug_ranges 0x00000098 0x18 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_ranges 0x000000b0 0x40 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_ranges 0x000000f0 0x10 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_ranges 0x00000100 0x128 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_ranges 0x00000228 0x1f0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_ranges 0x00000418 0x60 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .debug_ranges 0x00000478 0x8e8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_ranges 0x00000d60 0x28 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_ranges 0x00000d88 0x98 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_ranges 0x00000e20 0x20 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_ranges 0x00000e40 0x30 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_ranges 0x00000e70 0x20 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_ranges 0x00000e90 0x18 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(new.o)
+ .debug_ranges 0x00000ea8 0x2b0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_ranges 0x00001158 0x1d8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_ranges 0x00001330 0x180 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+
+.debug_macro 0x00000000 0x1d3d4
+ .debug_macro 0x00000000 0x6e7 Sketch.o
+ .debug_macro 0x000006e7 0x982 Sketch.o
+ .debug_macro 0x00001069 0x16 Sketch.o
+ .debug_macro 0x0000107f 0x1c Sketch.o
+ .debug_macro 0x0000109b 0x22 Sketch.o
+ .debug_macro 0x000010bd 0x87 Sketch.o
+ .debug_macro 0x00001144 0x51 Sketch.o
+ .debug_macro 0x00001195 0xef Sketch.o
+ .debug_macro 0x00001284 0x6a Sketch.o
+ .debug_macro 0x000012ee 0x1df Sketch.o
+ .debug_macro 0x000014cd 0x143 Sketch.o
+ .debug_macro 0x00001610 0x10 Sketch.o
+ .debug_macro 0x00001620 0x3c3 Sketch.o
+ .debug_macro 0x000019e3 0x10 Sketch.o
+ .debug_macro 0x000019f3 0x58 Sketch.o
+ .debug_macro 0x00001a4b 0x35 Sketch.o
+ .debug_macro 0x00001a80 0x9c Sketch.o
+ .debug_macro 0x00001b1c 0x16 Sketch.o
+ .debug_macro 0x00001b32 0x10e Sketch.o
+ .debug_macro 0x00001c40 0x94 Sketch.o
+ .debug_macro 0x00001cd4 0x58 Sketch.o
+ .debug_macro 0x00001d2c 0x1f Sketch.o
+ .debug_macro 0x00001d4b 0x43 Sketch.o
+ .debug_macro 0x00001d8e 0x20 Sketch.o
+ .debug_macro 0x00001dae 0x187 Sketch.o
+ .debug_macro 0x00001f35 0x353 Sketch.o
+ .debug_macro 0x00002288 0x16 Sketch.o
+ .debug_macro 0x0000229e 0x29 Sketch.o
+ .debug_macro 0x000022c7 0xea Sketch.o
+ .debug_macro 0x000023b1 0x16 Sketch.o
+ .debug_macro 0x000023c7 0x35 Sketch.o
+ .debug_macro 0x000023fc 0x18 Sketch.o
+ .debug_macro 0x00002414 0x1da Sketch.o
+ .debug_macro 0x000025ee 0x3d3 Sketch.o
+ .debug_macro 0x000029c1 0x10 Sketch.o
+ .debug_macro 0x000029d1 0x45d Sketch.o
+ .debug_macro 0x00002e2e 0x190 Sketch.o
+ .debug_macro 0x00002fbe 0x1c Sketch.o
+ .debug_macro 0x00002fda 0xd93 Sketch.o
+ .debug_macro 0x00003d6d 0x38e Sketch.o
+ .debug_macro 0x000040fb 0x40 Sketch.o
+ .debug_macro 0x0000413b 0x1c Sketch.o
+ .debug_macro 0x00004157 0x22 Sketch.o
+ .debug_macro 0x00004179 0xaf Sketch.o
+ .debug_macro 0x00004228 0x3ad Sketch.o
+ .debug_macro 0x000045d5 0x682 Sketch.o
+ .debug_macro 0x00004c57 0x8bf Sketch.o
+ .debug_macro 0x00005516 0x235 Sketch.o
+ .debug_macro 0x0000574b 0xd6a Sketch.o
+ .debug_macro 0x000064b5 0x4ce Sketch.o
+ .debug_macro 0x00006983 0x9f8 Sketch.o
+ .debug_macro 0x0000737b 0x82b Sketch.o
+ .debug_macro 0x00007ba6 0x45f Sketch.o
+ .debug_macro 0x00008005 0x5e Sketch.o
+ .debug_macro 0x00008063 0x906 Sketch.o
+ .debug_macro 0x00008969 0x225 Sketch.o
+ .debug_macro 0x00008b8e 0x797 Sketch.o
+ .debug_macro 0x00009325 0x5e Sketch.o
+ .debug_macro 0x00009383 0x634 Sketch.o
+ .debug_macro 0x000099b7 0x3b6 Sketch.o
+ .debug_macro 0x00009d6d 0xc55 Sketch.o
+ .debug_macro 0x0000a9c2 0x1092 Sketch.o
+ .debug_macro 0x0000ba54 0xc4a Sketch.o
+ .debug_macro 0x0000c69e 0x6bf Sketch.o
+ .debug_macro 0x0000cd5d 0x1b4b Sketch.o
+ .debug_macro 0x0000e8a8 0x144a Sketch.o
+ .debug_macro 0x0000fcf2 0x34e Sketch.o
+ .debug_macro 0x00010040 0x7c Sketch.o
+ .debug_macro 0x000100bc 0xa0 Sketch.o
+ .debug_macro 0x0001015c 0x4c Sketch.o
+ .debug_macro 0x000101a8 0xca Sketch.o
+ .debug_macro 0x00010272 0x94 Sketch.o
+ .debug_macro 0x00010306 0x58 Sketch.o
+ .debug_macro 0x0001035e 0x364 Sketch.o
+ .debug_macro 0x000106c2 0x82 Sketch.o
+ .debug_macro 0x00010744 0x197 Sketch.o
+ .debug_macro 0x000108db 0xb8 Sketch.o
+ .debug_macro 0x00010993 0xa0 Sketch.o
+ .debug_macro 0x00010a33 0xb2 Sketch.o
+ .debug_macro 0x00010ae5 0x1c Sketch.o
+ .debug_macro 0x00010b01 0x1c Sketch.o
+ .debug_macro 0x00010b1d 0x1c Sketch.o
+ .debug_macro 0x00010b39 0x7c Sketch.o
+ .debug_macro 0x00010bb5 0x161 Sketch.o
+ .debug_macro 0x00010d16 0xdc Sketch.o
+ .debug_macro 0x00010df2 0x12f Sketch.o
+ .debug_macro 0x00010f21 0x12f Sketch.o
+ .debug_macro 0x00011050 0x12f Sketch.o
+ .debug_macro 0x0001117f 0x12f Sketch.o
+ .debug_macro 0x000112ae 0x12f Sketch.o
+ .debug_macro 0x000113dd 0x12f Sketch.o
+ .debug_macro 0x0001150c 0x11e Sketch.o
+ .debug_macro 0x0001162a 0xe2 Sketch.o
+ .debug_macro 0x0001170c 0xe2 Sketch.o
+ .debug_macro 0x000117ee 0xe2 Sketch.o
+ .debug_macro 0x000118d0 0x12c Sketch.o
+ .debug_macro 0x000119fc 0x100 Sketch.o
+ .debug_macro 0x00011afc 0xf4 Sketch.o
+ .debug_macro 0x00011bf0 0x40f Sketch.o
+ .debug_macro 0x00011fff 0x40 Sketch.o
+ .debug_macro 0x0001203f 0x361 Sketch.o
+ .debug_macro 0x000123a0 0x16ea Sketch.o
+ .debug_macro 0x00013a8a 0x6d Sketch.o
+ .debug_macro 0x00013af7 0x5e Sketch.o
+ .debug_macro 0x00013b55 0x16 Sketch.o
+ .debug_macro 0x00013b6b 0x151 Sketch.o
+ .debug_macro 0x00013cbc 0x4c Sketch.o
+ .debug_macro 0x00013d08 0x10 Sketch.o
+ .debug_macro 0x00013d18 0x1c Sketch.o
+ .debug_macro 0x00013d34 0x10 Sketch.o
+ .debug_macro 0x00013d44 0x10 Sketch.o
+ .debug_macro 0x00013d54 0x1c Sketch.o
+ .debug_macro 0x00013d70 0x52 Sketch.o
+ .debug_macro 0x00013dc2 0x40 Sketch.o
+ .debug_macro 0x00013e02 0x10 Sketch.o
+ .debug_macro 0x00013e12 0x40 Sketch.o
+ .debug_macro 0x00013e52 0xd7 Sketch.o
+ .debug_macro 0x00013f29 0x16 Sketch.o
+ .debug_macro 0x00013f3f 0x18b Sketch.o
+ .debug_macro 0x000140ca 0x1c Sketch.o
+ .debug_macro 0x000140e6 0x11 Sketch.o
+ .debug_macro 0x000140f7 0xe2 Sketch.o
+ .debug_macro 0x000141d9 0x1c Sketch.o
+ .debug_macro 0x000141f5 0x16 Sketch.o
+ .debug_macro 0x0001420b 0x10 Sketch.o
+ .debug_macro 0x0001421b 0x28 Sketch.o
+ .debug_macro 0x00014243 0x1bc Sketch.o
+ .debug_macro 0x000143ff 0x28 Sketch.o
+ .debug_macro 0x00014427 0x70 Sketch.o
+ .debug_macro 0x00014497 0x2e Sketch.o
+ .debug_macro 0x000144c5 0x19d Sketch.o
+ .debug_macro 0x00014662 0x2e Sketch.o
+ .debug_macro 0x00014690 0x17e Sketch.o
+ .debug_macro 0x0001480e 0x22 Sketch.o
+ .debug_macro 0x00014830 0x40 Sketch.o
+ .debug_macro 0x00014870 0x46f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00014cdf 0x8e0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x000155bf 0x3a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x000155f9 0xb5 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x000156ae 0x3ad C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00015a5b 0x9c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00015af7 0x16 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00015b0d 0x97 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00015ba4 0x32a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00015ece 0xfd C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x00015fcb 0x43 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_macro 0x0001600e 0x4e4 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x000164f2 0x22 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00016514 0x10e C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x00016622 0x8d C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x000166af 0x35 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x000166e4 0x1e1 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_macro 0x000168c5 0x11 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(hooks.o)
+ .debug_macro 0x000168d6 0x6e7 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_macro 0x00016fbd 0x6f2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_macro 0x000176af 0x493 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_macro 0x00017b42 0x6e7 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_macro 0x00018229 0x758 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_macro 0x00018981 0x2e1 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .debug_macro 0x00018c62 0x52 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .debug_macro 0x00018cb4 0x8d C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .debug_macro 0x00018d41 0x57 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .debug_macro 0x00018d98 0x82 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .debug_macro 0x00018e1a 0xa2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .debug_macro 0x00018ebc 0x97 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .debug_macro 0x00018f53 0x196 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .debug_macro 0x000190e9 0x743 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x0001982c 0x2b C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00019857 0xee C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_macro 0x00019945 0x4d7 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x00019e1c 0x330 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x0001a14c 0x1d4 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_macro 0x0001a320 0x59b C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x0001a8bb 0x4c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_macro 0x0001a907 0x4d7 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_macro 0x0001adde 0x59b C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_macro 0x0001b379 0x596 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x0001b90f 0x34d C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_macro 0x0001bc5c 0x132 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(new.o)
+ .debug_macro 0x0001bd8e 0x6e7 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_macro 0x0001c475 0x701 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_macro 0x0001cb76 0x6e3 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_macro 0x0001d259 0x17b C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+
+.debug_line 0x00000000 0xde73
+ .debug_line 0x00000000 0xc99 Sketch.o
+ .debug_line 0x00000c99 0x7c9 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_line 0x00001462 0x8cf C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_line 0x00001d31 0x63 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(hooks.o)
+ .debug_line 0x00001d94 0xc22 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_line 0x000029b6 0xc94 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_line 0x0000364a 0x7f1 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_line 0x00003e3b 0xe0c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_line 0x00004c47 0xff1 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_line 0x00005c38 0x706 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .debug_line 0x0000633e 0x1851 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_line 0x00007b8f 0x8a3 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_line 0x00008432 0xab0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_line 0x00008ee2 0x894 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_line 0x00009776 0x930 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_line 0x0000a0a6 0x9c1 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_line 0x0000aa67 0x3fb C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(new.o)
+ .debug_line 0x0000ae62 0x1200 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_line 0x0000c062 0xedb C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_line 0x0000cf3d 0xf36 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+
+.debug_str 0x00000000 0x81c1e
+ .debug_str 0x00000000 0x7b694 Sketch.o
+ 0x7c44f (size before relaxing)
+ .debug_str 0x0007b694 0x6a9 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ 0x70a27 (size before relaxing)
+ .debug_str 0x0007bd3d 0xe9 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ 0x75570 (size before relaxing)
+ .debug_str 0x0007be26 0x2b C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(hooks.o)
+ 0x25e6 (size before relaxing)
+ .debug_str 0x0007be51 0x75 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ 0x7b525 (size before relaxing)
+ .debug_str 0x0007bec6 0x1fb C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ 0x7b7c7 (size before relaxing)
+ .debug_str 0x0007c0c1 0x8d1 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ 0x71240 (size before relaxing)
+ .debug_str 0x0007c992 0xbd C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ 0x7c497 (size before relaxing)
+ .debug_str 0x0007ca4f 0x2d4c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ 0x7f573 (size before relaxing)
+ .debug_str 0x0007f79b 0x57 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ 0xc380 (size before relaxing)
+ .debug_str 0x0007f7f2 0xf46 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ 0x7f28b (size before relaxing)
+ .debug_str 0x00080738 0x160 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ 0x75e3b (size before relaxing)
+ .debug_str 0x00080898 0x6a8 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ 0x77506 (size before relaxing)
+ .debug_str 0x00080f40 0x43 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ 0x75662 (size before relaxing)
+ .debug_str 0x00080f83 0x2f C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ 0x768d4 (size before relaxing)
+ .debug_str 0x00080fb2 0x37a C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ 0x76fed (size before relaxing)
+ .debug_str 0x0008132c 0x44 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(new.o)
+ 0x7451 (size before relaxing)
+ .debug_str 0x00081370 0x1a0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ 0x7b9a9 (size before relaxing)
+ .debug_str 0x00081510 0x361 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ 0x7cff4 (size before relaxing)
+ .debug_str 0x00081871 0x3ad C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ 0x7c45a (size before relaxing)
+
+.debug_frame 0x00000000 0x19cc
+ .debug_frame 0x00000000 0x40 Sketch.o
+ .debug_frame 0x00000040 0x7c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ .debug_frame 0x000000bc 0x88 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ .debug_frame 0x00000144 0x40 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(hooks.o)
+ .debug_frame 0x00000184 0x38 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ .debug_frame 0x000001bc 0x60 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ .debug_frame 0x0000021c 0x2c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ .debug_frame 0x00000248 0x1f0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ .debug_frame 0x00000438 0x2f0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ .debug_frame 0x00000728 0xdc C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ .debug_frame 0x00000804 0x470 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ .debug_frame 0x00000c74 0x28 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ .debug_frame 0x00000c9c 0x90 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ .debug_frame 0x00000d2c 0x64 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ .debug_frame 0x00000d90 0x30 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ .debug_frame 0x00000dc0 0x64 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ .debug_frame 0x00000e24 0x70 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(new.o)
+ .debug_frame 0x00000e94 0x46c C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ .debug_frame 0x00001300 0x1c4 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ .debug_frame 0x000014c4 0x318 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ .debug_frame 0x000017dc 0x20 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_udivsi3.o)
+ .debug_frame 0x000017fc 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-init.o)
+ .debug_frame 0x00001828 0x40 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-malloc.o)
+ .debug_frame 0x00001868 0x28 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-memcpy-stub.o)
+ .debug_frame 0x00001890 0x20 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-memset.o)
+ .debug_frame 0x000018b0 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-freer.o)
+ .debug_frame 0x000018dc 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-mallocr.o)
+ .debug_frame 0x00001908 0x2c c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-sbrkr.o)
+ .debug_frame 0x00001934 0x30 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-mlock.o)
+ .debug_frame 0x00001964 0x48 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-reent.o)
+ .debug_frame 0x000019ac 0x20 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libnosys.a(sbrk.o)
+
+Cross Reference Table
+
+Symbol File
+AC_Handler C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ADC_Handler C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+DAC_Handler C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+DMAC_Handler C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+DoubleBufferedEPOutHandler::_available() const C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+DoubleBufferedEPOutHandler::_recv() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+DoubleBufferedEPOutHandler::available() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+DoubleBufferedEPOutHandler::handleEndpoint() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+DoubleBufferedEPOutHandler::peek() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+DoubleBufferedEPOutHandler::recv(void*, unsigned long) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+DoubleBufferedEPOutHandler::release() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+DoubleBufferedEPOutHandler::~DoubleBufferedEPOutHandler() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+DoubleBufferedEPOutHandler::~DoubleBufferedEPOutHandler() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+DoubleBufferedEPOutHandler::~DoubleBufferedEPOutHandler() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+Dummy_Handler C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+EIC_Handler C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+EVSYS_Handler C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+EndPoints C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+HardFault_Handler C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+I2S_Handler C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+NMI_Handler C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+NVMCTRL_Handler C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+PM_Handler C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+PTC_Handler C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+PendSV_Handler C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+PluggableUSB() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+PluggableUSB_::PluggableUSB_() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+PluggableUSB_::PluggableUSB_() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+PluggableUSB_::getDescriptor(USBSetup&) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+PluggableUSB_::getInterface(unsigned char*) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+PluggableUSB_::getShortName(char*) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+PluggableUSB_::handleEndpoint(int) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+PluggableUSB_::plug(PluggableUSBModule*) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+PluggableUSB_::setup(USBSetup&) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(PluggableUSB.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+Print::availableForWrite() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+Print::flush() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+Print::print(Printable const&) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+Print::print(String const&) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+Print::print(__FlashStringHelper const*) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+Print::print(char const*) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+Print::print(char) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+Print::print(double, int) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+Print::print(int, int) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+Print::print(long, int) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+Print::print(unsigned char, int) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+Print::print(unsigned int, int) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+Print::print(unsigned long, int) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+Print::printFloat(double, unsigned char) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+Print::printNumber(unsigned long, unsigned char) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+Print::println() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+Print::println(Printable const&) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+Print::println(String const&) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+Print::println(__FlashStringHelper const*) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+Print::println(char const*) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+Print::println(char) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+Print::println(double, int) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+Print::println(int, int) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+Print::println(long, int) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+Print::println(unsigned char, int) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+Print::println(unsigned int, int) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+Print::println(unsigned long, int) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+Print::write(char const*) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+Print::write(unsigned char const*, unsigned int) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+RTC_Handler C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+Reset_Handler C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+RingBufferN<256>::RingBufferN() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+RingBufferN<256>::RingBufferN() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+RingBufferN<256>::available() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+RingBufferN<256>::availableForStore() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+SERCOM0_Handler C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+SERCOM1_Handler C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+SERCOM2_Handler C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+SERCOM3_Handler C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+SERCOM4_Handler C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+SERCOM5_Handler C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+SERCOM::SERCOM(Sercom*) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+SERCOM::SERCOM(Sercom*) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+SERCOM::acknowledgeUARTError() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+SERCOM::availableDataUART() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+SERCOM::availableWIRE() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+SERCOM::calculateBaudrateSynchronous(unsigned long) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+SERCOM::clearFrameErrorUART() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+SERCOM::clearStatusUART() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+SERCOM::disableDataRegisterEmptyInterruptUART() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+SERCOM::disableSPI() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+SERCOM::disableWIRE() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+SERCOM::enableDataRegisterEmptyInterruptUART() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+SERCOM::enableSPI() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+SERCOM::enableUART() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+SERCOM::enableWIRE() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+SERCOM::flushUART() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+SERCOM::getDataOrderSPI() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+SERCOM::initClockNVIC() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+SERCOM::initFrame(SercomUartCharSize, SercomDataOrder, SercomParityMode, SercomNumberStopBit) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+SERCOM::initMasterWIRE(unsigned long) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+SERCOM::initPads(SercomUartTXPad, SercomRXPad) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+SERCOM::initSPI(SercomSpiTXPad, SercomRXPad, SercomSpiCharSize, SercomDataOrder) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+SERCOM::initSPIClock(SercomSpiClockMode, unsigned long) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+SERCOM::initSlaveWIRE(unsigned char, bool) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+SERCOM::initUART(SercomUartMode, SercomUartSampleRate, unsigned long) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+SERCOM::isAddressMatch() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+SERCOM::isArbLostWIRE() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+SERCOM::isBufferOverflowErrorSPI() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+SERCOM::isBufferOverflowErrorUART() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+SERCOM::isBusBusyWIRE() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+SERCOM::isBusIdleWIRE() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+SERCOM::isBusOwnerWIRE() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+SERCOM::isDataReadyWIRE() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+SERCOM::isDataRegisterEmptySPI() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+SERCOM::isDataRegisterEmptyUART() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+SERCOM::isFrameErrorUART() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+SERCOM::isMasterReadOperationWIRE() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+SERCOM::isMasterWIRE() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+SERCOM::isParityErrorUART() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+SERCOM::isRXNackReceivedWIRE() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+SERCOM::isRestartDetectedWIRE() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+SERCOM::isSlaveWIRE() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+SERCOM::isStopDetectedWIRE() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+SERCOM::isUARTError() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+SERCOM::prepareAckBitWIRE() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+SERCOM::prepareCommandBitsWire(unsigned char) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+SERCOM::prepareNackBitWIRE() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+SERCOM::readDataUART() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+SERCOM::readDataWIRE() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+SERCOM::resetSPI() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+SERCOM::resetUART() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+SERCOM::resetWIRE() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+SERCOM::sendDataMasterWIRE(unsigned char) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+SERCOM::sendDataSlaveWIRE(unsigned char) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+SERCOM::setBaudrateSPI(unsigned char) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+SERCOM::setClockModeSPI(SercomSpiClockMode) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+SERCOM::setDataOrderSPI(SercomDataOrder) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+SERCOM::startTransmissionWIRE(unsigned char, SercomWireReadWriteFlag) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+SERCOM::transferDataSPI(unsigned char) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+SERCOM::writeDataUART(unsigned char) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+SVC_Handler C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+SYSCTRL_Handler C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+Serial C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+Serial1 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+SerialUSB C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ Sketch.o
+Serial_::Serial_(USBDeviceClass&) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+Serial_::Serial_(USBDeviceClass&) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+Serial_::available() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ Sketch.o
+Serial_::availableForWrite() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+Serial_::baud() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+Serial_::begin(unsigned long) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ Sketch.o
+Serial_::begin(unsigned long, unsigned char) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+Serial_::clear() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+Serial_::dtr() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+Serial_::enableInterrupt() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+Serial_::end() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+Serial_::flush() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+Serial_::getDescriptor(USBSetup&) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+Serial_::getInterface(unsigned char*) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+Serial_::getShortName(char*) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+Serial_::handleEndpoint(int) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+Serial_::numbits() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+Serial_::operator bool() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+Serial_::paritytype() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+Serial_::peek() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+Serial_::read() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+Serial_::readBreak() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+Serial_::readBytes(char*, unsigned int) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+Serial_::rts() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+Serial_::setup(USBSetup&) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+Serial_::stopbits() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+Serial_::write(unsigned char const*, unsigned int) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+Serial_::write(unsigned char) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+Stream::find(char*) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+Stream::find(char*, unsigned int) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+Stream::findMulti(Stream::MultiTarget*, int) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+Stream::findUntil(char*, char*) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+Stream::findUntil(char*, unsigned int, char*, unsigned int) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+Stream::parseFloat(LookaheadMode, char) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+Stream::parseInt(LookaheadMode, char) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ Sketch.o
+Stream::peekNextDigit(LookaheadMode, bool) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+Stream::readBytes(char*, unsigned int) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+Stream::readBytesUntil(char, char*, unsigned int) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+Stream::readString() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+Stream::readStringUntil(char) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+Stream::setTimeout(unsigned long) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+Stream::timedPeek() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+Stream::timedRead() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+String::String(String const&) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::String(String const&) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::String(String&&) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::String(String&&) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::String(StringSumHelper&&) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::String(StringSumHelper&&) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::String(__FlashStringHelper const*) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::String(__FlashStringHelper const*) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::String(char const*) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+String::String(char const*) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::String(char) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::String(char) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::String(double, unsigned char) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::String(double, unsigned char) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::String(float, unsigned char) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::String(float, unsigned char) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::String(int, unsigned char) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::String(int, unsigned char) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::String(long, unsigned char) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::String(long, unsigned char) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::String(unsigned char, unsigned char) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::String(unsigned char, unsigned char) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::String(unsigned int, unsigned char) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::String(unsigned int, unsigned char) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::String(unsigned long, unsigned char) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::String(unsigned long, unsigned char) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::StringIfHelper() const C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::changeBuffer(unsigned int) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::charAt(unsigned int) const C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::compareTo(String const&) const C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::concat(String const&) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::concat(__FlashStringHelper const*) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::concat(char const*) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::concat(char const*, unsigned int) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::concat(char) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+String::concat(double) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::concat(float) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::concat(int) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::concat(long) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::concat(unsigned char) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::concat(unsigned int) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::concat(unsigned long) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::copy(__FlashStringHelper const*, unsigned int) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::copy(char const*, unsigned int) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::endsWith(String const&) const C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::equals(String const&) const C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::equals(char const*) const C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::equalsIgnoreCase(String const&) const C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::getBytes(unsigned char*, unsigned int, unsigned int) const C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::indexOf(String const&) const C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::indexOf(String const&, unsigned int) const C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::indexOf(char) const C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::indexOf(char, unsigned int) const C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::invalidate() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::lastIndexOf(String const&) const C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::lastIndexOf(String const&, unsigned int) const C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::lastIndexOf(char) const C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::lastIndexOf(char, unsigned int) const C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::move(String&) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::operator<(String const&) const C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::operator<=(String const&) const C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::operator=(String const&) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::operator=(String&&) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::operator=(StringSumHelper&&) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::operator=(__FlashStringHelper const*) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::operator=(char const*) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::operator>(String const&) const C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::operator>=(String const&) const C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::operator[](unsigned int) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::operator[](unsigned int) const C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::remove(unsigned int) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::remove(unsigned int, unsigned int) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::replace(String const&, String const&) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::replace(char, char) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::reserve(unsigned int) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::setCharAt(unsigned int, char) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::startsWith(String const&) const C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::startsWith(String const&, unsigned int) const C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::substring(unsigned int, unsigned int) const C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::toDouble() const C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::toFloat() const C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::toInt() const C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::toLowerCase() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::toUpperCase() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::trim() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::~String() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+String::~String() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+SysTick_DefaultHandler C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+SysTick_Handler C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+SystemCoreClock C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+SystemInit C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(startup.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+TC3_Handler C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+TC4_Handler C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+TC5_Handler C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+TC6_Handler C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+TC7_Handler C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+TCC0_Handler C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+TCC1_Handler C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+TCC2_Handler C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+UDD_Handler C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+USBDevice C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+USBDeviceClass::ISRHandler() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+USBDeviceClass::SendInterfaces(unsigned long*) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+USBDeviceClass::armRecvCtrlOUT(unsigned long) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+USBDeviceClass::armSend(unsigned long, void const*, unsigned long) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+USBDeviceClass::attach() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+USBDeviceClass::available(unsigned long) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+USBDeviceClass::clear(unsigned long) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+USBDeviceClass::configured() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+USBDeviceClass::connected() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+USBDeviceClass::detach() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+USBDeviceClass::end() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+USBDeviceClass::flush(unsigned long) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+USBDeviceClass::handleClassInterfaceSetup(USBSetup&) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+USBDeviceClass::handleStandardSetup(USBSetup&) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+USBDeviceClass::init() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+USBDeviceClass::initEP(unsigned long, unsigned long) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+USBDeviceClass::initEndpoints() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+USBDeviceClass::packMessages(bool) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+USBDeviceClass::recv(unsigned long) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+USBDeviceClass::recv(unsigned long, void*, unsigned long) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+USBDeviceClass::recvControl(void*, unsigned long) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+USBDeviceClass::send(unsigned long, void const*, unsigned long) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+USBDeviceClass::sendConfiguration(unsigned long) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+USBDeviceClass::sendControl(void const*, unsigned long) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+USBDeviceClass::sendDescriptor(USBSetup&) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+USBDeviceClass::sendStringDescriptor(unsigned char const*, unsigned long) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+USBDeviceClass::sendZlp(unsigned long) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+USBDeviceClass::setAddress(unsigned long) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+USBDeviceClass::stall(unsigned long) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+USBDeviceClass::standby() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+USB_Handler C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+USB_SetHandler C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+Uart::IrqHandler() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+Uart::Uart(SERCOM*, unsigned char, unsigned char, SercomRXPad, SercomUartTXPad) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+Uart::Uart(SERCOM*, unsigned char, unsigned char, SercomRXPad, SercomUartTXPad) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+Uart::Uart(SERCOM*, unsigned char, unsigned char, SercomRXPad, SercomUartTXPad, unsigned char, unsigned char) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+Uart::Uart(SERCOM*, unsigned char, unsigned char, SercomRXPad, SercomUartTXPad, unsigned char, unsigned char) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+Uart::available() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+Uart::availableForWrite() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+Uart::begin(unsigned long) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+Uart::begin(unsigned long, unsigned short) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+Uart::end() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+Uart::extractCharSize(unsigned short) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+Uart::extractNbStopBit(unsigned short) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+Uart::extractParity(unsigned short) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+Uart::flush() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+Uart::operator bool() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+Uart::peek() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+Uart::read() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+Uart::write(unsigned char) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+WDT_Handler C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+_Balloc c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-mprec.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-gdtoa-gethex.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-dtoa.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtod.o)
+_Bfree c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-mprec.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-gdtoa-gethex.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-dtoa.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtod.o)
+_Jv_RegisterClasses c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crtbegin.o
+_PathLocale c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-locale.o)
+__Guard::__Guard() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+__Guard::__Guard() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+__Guard::~__Guard() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+__Guard::~__Guard() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+__StackTop C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+__aeabi_cdcmpeq c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_arm_cmpdf2.o)
+__aeabi_cdcmple c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_arm_cmpdf2.o)
+__aeabi_cdrcmple c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_arm_cmpdf2.o)
+__aeabi_cfcmpeq c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_arm_cmpsf2.o)
+__aeabi_cfcmple c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_arm_cmpsf2.o)
+__aeabi_cfrcmple c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_arm_cmpsf2.o)
+__aeabi_d2f c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(truncdfsf2.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtod.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+__aeabi_d2iz c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(fixdfsi.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-dtoa.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtod.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_fixunsdfsi.o)
+__aeabi_d2uiz c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_fixunsdfsi.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtod.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+__aeabi_dadd c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(adddf3.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-dtoa.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtod.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+__aeabi_dcmpeq c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_arm_cmpdf2.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-dtoa.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtod.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-vfprintf_float.o)
+__aeabi_dcmpge c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_arm_cmpdf2.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-dtoa.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_fixunsdfsi.o)
+__aeabi_dcmpgt c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_arm_cmpdf2.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-dtoa.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtod.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+__aeabi_dcmple c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_arm_cmpdf2.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtod.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-vfprintf_float.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+__aeabi_dcmplt c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_arm_cmpdf2.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-dtoa.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtod.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-vfprintf_float.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+__aeabi_dcmpun c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(unorddf2.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtod.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-vfprintf_float.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+__aeabi_ddiv c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(divdf3.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-mprec.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-dtoa.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtod.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+__aeabi_dmul c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(muldf3.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-mprec.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-dtoa.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtod.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+__aeabi_dsub c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(subdf3.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-dtoa.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtod.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_fixunsdfsi.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+__aeabi_f2d c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(extendsfdf2.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+__aeabi_fcmpeq c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_arm_cmpsf2.o)
+__aeabi_fcmpge c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_arm_cmpsf2.o)
+__aeabi_fcmpgt c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_arm_cmpsf2.o)
+__aeabi_fcmple c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_arm_cmpsf2.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtod.o)
+__aeabi_fcmplt c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_arm_cmpsf2.o)
+__aeabi_fcmpun c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(unordsf2.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtod.o)
+__aeabi_fmul c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(mulsf3.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+__aeabi_i2d c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(floatsidf.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-dtoa.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtod.o)
+__aeabi_i2f c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(floatsisf.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+__aeabi_idiv c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_divsi3.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-mprec.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-vfprintf_float.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+__aeabi_idiv0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_dvmd_tls.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_divsi3.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_udivsi3.o)
+__aeabi_idivmod c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_divsi3.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-vfprintf_float.o)
+__aeabi_ldiv0 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_dvmd_tls.o)
+__aeabi_ui2d c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(floatunsidf.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-dtoa.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtod.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+__aeabi_uidiv c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_udivsi3.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-dtoa.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtol.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-vfprintf_i.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(divdf3.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(SERCOM.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(itoa.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+__aeabi_uidivmod c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_udivsi3.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtol.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-vfprintf_i.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(divdf3.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(itoa.o)
+__any_on c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-mprec.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-gdtoa-gethex.o)
+__ascii_mbtowc c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-mbtowc_r.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-locale.o)
+__ascii_wctomb c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-wctomb_r.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-locale.o)
+__b2d c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-mprec.o)
+__bss_end__ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/crt0.o
+__bss_start__ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/crt0.o
+__call_exitprocs c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-exit.o)
+__clzsi2 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_clzsi2.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(floatsidf.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(extendsfdf2.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(floatunsidf.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(subdf3.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(muldf3.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(divdf3.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(adddf3.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(floatsisf.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(mulsf3.o)
+__copybits c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-mprec.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtod.o)
+__cvt c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-vfprintf_float.o)
+__cxa_deleted_virtual C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(abi.o)
+__cxa_pure_virtual C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(abi.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+__d2b c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-mprec.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-dtoa.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtod.o)
+__data_end__ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+__data_start__ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+__deregister_frame_info c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crtbegin.o
+__divsi3 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_divsi3.o)
+__dso_handle c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crtbegin.o
+__eqdf2 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(eqdf2.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_arm_cmpdf2.o)
+__eqsf2 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(eqsf2.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_arm_cmpsf2.o)
+__etext C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+__exponent c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-vfprintf_float.o)
+__fixunsdfsi c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_fixunsdfsi.o)
+__gedf2 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(gedf2.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_arm_cmpdf2.o)
+__gesf2 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(gesf2.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_arm_cmpsf2.o)
+__gethex c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-gdtoa-gethex.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtod.o)
+__global_locale c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-locale.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-localeconv.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-wctomb_r.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtol.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtod.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-mbtowc_r.o)
+__gnu_thumb1_case_uqi c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_thumb1_case_uqi.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-dtoa.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtod.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+__gtdf2 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(gedf2.o)
+__gtsf2 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(gesf2.o)
+__hexdig_fun c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-gdtoa-gethex.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-gdtoa-hexnan.o)
+__hexnan c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-gdtoa-hexnan.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtod.o)
+__hi0bits c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-mprec.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-gdtoa-gethex.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-dtoa.o)
+__i2b c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-mprec.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-dtoa.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtod.o)
+__init_array_end c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-init.o)
+__init_array_start c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-init.o)
+__ledf2 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(ledf2.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_arm_cmpdf2.o)
+__lesf2 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(lesf2.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_arm_cmpsf2.o)
+__libc_fini_array c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/crt0.o
+__libc_init_array c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-init.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/crt0.o
+__lo0bits c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-mprec.o)
+__locale_ctype_ptr c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-locale.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-toupper.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-tolower.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-isspace.o)
+__locale_ctype_ptr_l c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-locale.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtol.o)
+__locale_mb_cur_max c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-locale.o)
+__localeconv_l c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-localeconv.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-gdtoa-gethex.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtod.o)
+__lshift c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-mprec.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-gdtoa-gethex.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-dtoa.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtod.o)
+__ltdf2 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(ledf2.o)
+__ltsf2 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(lesf2.o)
+__malloc_free_list c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-mallocr.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-freer.o)
+__malloc_lock c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-mlock.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-mallocr.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-freer.o)
+__malloc_sbrk_start c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-mallocr.o)
+__malloc_unlock c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-mlock.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-mallocr.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-freer.o)
+__match c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-gdtoa-hexnan.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtod.o)
+__mcmp c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-mprec.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-dtoa.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtod.o)
+__mdiff c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-mprec.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-dtoa.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtod.o)
+__mprec_bigtens c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-mprec.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-dtoa.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtod.o)
+__mprec_tens c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-mprec.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-dtoa.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtod.o)
+__mprec_tinytens c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-mprec.o)
+__multadd c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-mprec.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-dtoa.o)
+__multiply c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-mprec.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-dtoa.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtod.o)
+__nedf2 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(eqdf2.o)
+__nesf2 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(eqsf2.o)
+__pow5mult c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-mprec.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-dtoa.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtod.o)
+__preinit_array_end c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-init.o)
+__preinit_array_start c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-init.o)
+__ratio c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-mprec.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtod.o)
+__register_frame_info c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crtbegin.o
+__s2b c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-mprec.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtod.o)
+__sf_fake_stderr c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-impure.o)
+__sf_fake_stdin c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-impure.o)
+__sf_fake_stdout c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-impure.o)
+__ssprint_r c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-svfprintf.o)
+__ssputs_r c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-svfprintf.o)
+__stack c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/crt0.o
+__text_start__ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+__udivsi3 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_udivsi3.o)
+__ulp c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-mprec.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtod.o)
+_atol_r c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-atol.o)
+_calloc_r c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-callocr.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-mprec.o)
+_ctype_ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-ctype_.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-locale.o)
+_dry_run C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+_dtoa_r c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-dtoa.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-vfprintf_float.o)
+_exit c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libnosys.a(_exit.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-exit.o)
+_fini c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crti.o
+_free_r c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-freer.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-reent.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-svfprintf.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-reallocr.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-malloc.o)
+_global_impure_ptr c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-impure.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-exit.o)
+_impure_ptr c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-impure.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-reent.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-localeconv.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-wctomb_r.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtol.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtod.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-sprintf.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-realloc.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-mbtowc_r.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-malloc.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-locale.o)
+_init c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crti.o
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-init.o)
+_localeconv_r c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-localeconv.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-vfprintf_float.o)
+_mainCRTStartup c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/crt0.o
+_malloc_r c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-mallocr.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-svfprintf.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-reallocr.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-callocr.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-malloc.o)
+_malloc_usable_size_r c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-msizer.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-reallocr.o)
+_mbtowc_r c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-mbtowc_r.o)
+_mprec_log10 c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-mprec.o)
+_pack_buffer C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+_pack_message C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+_pack_size C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+_printf_common c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-vfprintf_i.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-vfprintf_float.o)
+_printf_float c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-vfprintf_float.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-svfprintf.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(dtostrf.o)
+_printf_i c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-vfprintf_i.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-svfprintf.o)
+_realloc_r c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-reallocr.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-svfprintf.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-realloc.o)
+_reclaim_reent c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-reent.o)
+_sbrk c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libnosys.a(sbrk.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-sbrkr.o)
+_sbrk_r c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-sbrkr.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-mallocr.o)
+_serialPeek C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+_setlocale_r c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-locale.o)
+_siprintf_r c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-sprintf.o)
+_sprintf_r c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-sprintf.o)
+_start c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/crt0.o
+_strtod_l c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtod.o)
+_strtod_r c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtod.o)
+_strtol_r c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtol.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-atol.o)
+_svfiprintf_r c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-svfprintf.o)
+_svfprintf_r c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-svfprintf.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-sprintf.o)
+_usbConfiguration C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+_usbSetInterface C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+_wctomb_r c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-wctomb_r.o)
+analogRead C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+analogReadResolution C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+analogReference C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+analogWrite C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ Sketch.o
+analogWriteResolution C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ Sketch.o
+atexit c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/crt0.o
+atof c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-atof.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+atol c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-atol.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+cancelReset C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+cleanup_glue c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-reent.o)
+delay C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+digitalRead C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+digitalWrite C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+dtostrf C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(dtostrf.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+end c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libnosys.a(sbrk.o)
+errno c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-reent.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-sbrkr.o)
+exception_table C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+exit c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-exit.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/crt0.o
+free c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-malloc.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(new.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+g_APinDescription C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+g_apTCInstances C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+hardware_init_hook c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/crt0.o
+init C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+initVariant() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+initiateReset C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+isspace c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-isspace.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+itoa C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(itoa.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+localeconv c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-localeconv.o)
+loop Sketch.o
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ltoa C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(itoa.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+main C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/crt0.o
+malloc c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-malloc.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-mprec.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-dtoa.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(new.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+memchr c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-memchr-stub.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-svfprintf.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-vfprintf_i.o)
+memcpy c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-memcpy-stub.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-svfprintf.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-reallocr.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-mprec.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-gdtoa-gethex.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-dtoa.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtod.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+memmove c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-memmove.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-svfprintf.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+memset c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-memset.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-callocr.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/crt0.o
+micros C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+millis C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+nanf c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-sf_nan.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtod.o)
+non-virtual thunk to Serial_::getDescriptor(USBSetup&) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+non-virtual thunk to Serial_::getInterface(unsigned char*) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+non-virtual thunk to Serial_::getShortName(char*) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+non-virtual thunk to Serial_::handleEndpoint(int) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+non-virtual thunk to Serial_::setup(USBSetup&) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+operator delete(void*) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(new.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+operator delete[](void*) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(new.o)
+operator new(unsigned int) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(new.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+operator new[](unsigned int) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(new.o)
+operator+(StringSumHelper const&, String const&) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+operator+(StringSumHelper const&, __FlashStringHelper const*) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+operator+(StringSumHelper const&, char const*) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+operator+(StringSumHelper const&, char) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+operator+(StringSumHelper const&, double) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+operator+(StringSumHelper const&, float) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+operator+(StringSumHelper const&, int) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+operator+(StringSumHelper const&, long) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+operator+(StringSumHelper const&, unsigned char) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+operator+(StringSumHelper const&, unsigned int) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+operator+(StringSumHelper const&, unsigned long) C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+pendSVHook C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(hooks.o)
+pinMode C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_digital.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring.o)
+pinPeripheral C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_private.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(wiring_analog.o)
+realloc c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-realloc.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+resetExternalChip C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+sercom0 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+sercom1 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+sercom2 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+sercom3 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+sercom4 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+sercom5 C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(variant.o)
+serialEventRun() C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+setlocale c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-locale.o)
+setup Sketch.o
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(main.o)
+siprintf c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-sprintf.o)
+software_init_hook c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/crt0.o
+sprintf c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-sprintf.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(dtostrf.o)
+strchr c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strchr.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strrchr.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+strcmp c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strcmp.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-locale.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+strcpy c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strcpy.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+strlen c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strlen.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-gdtoa-gethex.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtod.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-nano-vfprintf_float.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Stream.o)
+strncmp c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strncmp.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-gdtoa-gethex.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtod.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+strncpy c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strncpy.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+strrchr c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strrchr.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+strstr c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strstr.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+strtod c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtod.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-atof.o)
+strtod_l c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtod.o)
+strtof c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtod.o)
+strtof_l c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtod.o)
+strtol c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtol.o)
+ c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-atol.o)
+strtol_l c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-strtol.o)
+svcHook C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(hooks.o)
+sysTickHook C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(hooks.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(cortex_handlers.o)
+tickReset C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Reset.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
+tolower c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-tolower.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+toupper c:/program files (x86)/atmel/studio/7.0/toolchain/arm/arm-gnu-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libc_nano.a(lib_a-toupper.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+ultoa C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(itoa.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+usbd C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+utoa C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(itoa.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(WString.o)
+vtable for DoubleBufferedEPOutHandler C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(USBCore.o)
+vtable for Print C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Print.o)
+vtable for Serial_ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(CDC.o)
+vtable for Uart C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(Uart.o)
+yield C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(hooks.o)
+ C:\GIT\serial-communication-arduino\UsbReceive\UsbReceive\ArduinoCore\Debug\libArduinoCore.a(delay.o)
diff --git a/UsbReceive/UsbReceive/UsbReceive/Debug/UsbReceive.srec b/UsbReceive/UsbReceive/UsbReceive/Debug/UsbReceive.srec
new file mode 100644
index 0000000000000000000000000000000000000000..37563df241732b07fced7c34f63baf8f5c4a7e02
--- /dev/null
+++ b/UsbReceive/UsbReceive/UsbReceive/Debug/UsbReceive.srec
@@ -0,0 +1,769 @@
+S0120000557362526563656976652E7372656325
+S113000000800020750100005D0100005D0100001A
+S113001000000000000000000000000000000000DC
+S11300200000000000000000000000005D0100006E
+S113003000000000000000005D010000C901000094
+S11300405D0100005D0100005D0100005D01000034
+S11300505D0100005D0100005D0100006101000020
+S11300605D0100002D1F00005D0100005D01000026
+S11300705D0100005D0100003D1F00005D01000006
+S11300805D0100005D0100005D0100005D010000F4
+S1130090000000005D0100005D0100005D01000042
+S11300A05D0100005D0100005D0100005D010000D4
+S11300B00000000010B5064C2378002B07D1054B37
+S11300C0002B02D0044800E000BF0123237010BDC0
+S11300D0B000002000000000382F0000084B10B5CD
+S11300E0002B03D00749084800E000BF0748036815
+S11300F0002B00D110BD064B002BFBD09847F9E72D
+S113010000000000B4000020382F0000AC000020E4
+S113011000000000E12110B54902054800F028FC68
+S11301200A2001F005FD00210E2001F039FD10BD6B
+S1130130D400002010B5084C200000F08BFB0028F0
+S113014008DB00210122200000F006FA01000E2045
+S113015001F026FD10BDC046D400002003BEFEE71A
+S1130160034B10B51B68002B00D0984710BDC04648
+S1130170CC00002070B50F490F4CA14204D100F00F
+S1130180FDF800F08DF8FEE70C4D00238D42F6D00B
+S1130190CA18E818A24205D39042F0D0084B094986
+S11301A0002204E0006804331060F1E704C38B42CA
+S11301B0FCD3E4E700000020B00000203C2F000046
+S11301C0B0000020A00B002010B500F066F8002855
+S11301D001D100F057F810BD014B18607047C046BC
+S11301E0CC000020014B18687047C046D0000020A6
+S11301F0F7B51348012284461249134C8E6863688C
+S113020005689B0E1340019288686268019F920EF4
+S11302103A4067463F6893420ED1BD420CD18642B4
+S11302200AD35B19FA254868AD00861B07486B435F
+S11302307043000DC018FEBD3D0013000600E3E747
+S1130240D000002010E000E000ED00E05555000073
+S113025070B5041E10D0FFF7CBFF050000F01CF8AA
+S1130260FFF7C6FF054B401B9842F7D9FA23013C20
+S11302709B00ED18002CF3D170BDC046E7030000CD
+S11302807047000010B5034A13680133136000F08F
+S113029039F810BDD0000020704700207047704727
+S11302A010B501F0C3FB02F07FFAFFF7F8FF01205D
+S11302B0FFF7CEFF084C200000F066FE200000F09F
+S11302C0FDFEFFF727FFFFF735FF044B002BFAD0A5
+S11302D000E000BFF7E7C0463C010020000000003A
+S11302E010B50400FFF7CCFF014B1C6010BDC046E5
+S11302F0000000200122024B52421A607047C0469F
+S113030000000020164A10B51368591C27D0013B81
+S11303101360002B23D172B6124B134A0433934259
+S113032008D8BFF34F8F114A114BDA60BFF34F8FD8
+S1130330C046FDE70F4A01211000147D0C42FCD099
+S11303402021148BFF319B085B0021431183D3616F
+S1130350094B13800123027D1A42FCD0E1E710BD52
+S11303600000002000000000030200000400FA0561
+S113037000ED00E00040004102A5FFFF1E2270B521
+S113038046484749436893431C3A13434360082350
+S11303908C692343C3248B61424BA4009C829C8AB6
+S11303A014439C82DC681442FCD001243E4A14703D
+S11303B01578254203D055786DB2002DF8DB012461
+S11303C09460547864B2002CFBDB384C546054784D
+S11303D064B2002CFBDB8224E4015480547864B2C0
+S11303E0002CFBDB02249C840E34DD682542FCD007
+S11303F02F4CDC621024DD682542FCD09D8C2D4CF2
+S11304002C439C841024DD682542FCD002249D8C5E
+S113041080262C439C844024DD683542FCD0DD6872
+S11304202542F9D01024DD682542FCD000249460D4
+S1130430547864B2002CFBDB1F4C5460547864B2D3
+S1130440002CFBDB1C6A1D4D2C4080251C621C6AA1
+S1130450AC431C6203239360194B536053785BB223
+S1130460002BFBDB0023FF240B72164A4B728B72AA
+S1130470CB72154B1A60154B154A1B6811689A0606
+S11304805B01C90E2340520F12020B431343114A5E
+S11304901385802342681343436070BD00400041CC
+S11304A00004004000080040000C00400105010069
+S11304B0B905FF7D040A000000070300FFFCFFFFED
+S11304C003060100006CDC0214000020246080009C
+S11304D0206080000040004210B50400FFF782FE57
+S11304E0E060236820009B699847002808DAFFF73A
+S11304F079FEE368C01AA3689842F2D3012040420F
+S113050010BD0000F8B504000D00160001272000FE
+S1130510FFF7E2FF00281CDB2D281AD00300303B34
+S1130520092B16D9002E01D02E2812D0012D0ED061
+S1130530022D07D10938172809D83A008240054B03
+S11305401A4204D0236820005B699847DFE7012042
+S11305504042F8BD13008000F8B5170000220500E2
+S11305600024FFF7CFFFA0421CDB2600B84209D0CD
+S11305702D2819D00300303B092B03D80A235C43F0
+S11305802418303C2B6828005B6998472800FFF743
+S1130590A3FF0300303B092BE8D98742E6D0002EA5
+S11305A000D064422000F8BD0126EBE7002070472C
+S11305B008B4024B9C46103808BC6047AD050000E7
+S11305C030B50F25CB1D013902002A401400000963
+S11305D03034092A01DD373214001C70013B8B4290
+S11305E0F2D130BD10B50C000B4B1868FFF7E8FFD3
+S11305F021000A4B08311868FFF7E2FF2100084B7D
+S113060010311868FFF7DCFF2100064B1831186819
+S1130610FFF7D6FF202010BD0CA0800040A0800072
+S113062044A0800048A0800008B4024B9C461038C7
+S113063008BC6047E50500007047000008B4024BA1
+S11306409C46103808BC6047390600003F207047BC
+S113065013B56B460268D971073354681900012237
+S1130660A04716BDF0B50B7895B003AC02330190EA
+S11306700B7042220021200002F0D7F80922042541
+S113068022720422A575627206250522242002AE78
+S1130690657625779519A074E075E076E8773000E3
+S11306A001210630C17730000730C17704A8C17733
+S11306B009202173617580190631C1770A208019D8
+S11306C0C27703208446654605A8C5772E201027E7
+S11306D0801907702F200925082380190570042527
+S11306E02370033363700EA8093BE37023716371B5
+S11306F06373A37362742376A276E27727752785E2
+S113070005703320350080190A2603700FA806707F
+S113071010A801703920401902703B203536761933
+S1130720317012A90A7080213D32401952190370A8
+S113073013704020002249420E0041335B191870A7
+S11307405A70019B20871B7D019AA370A372637763
+S11307500133DBB2A377527D353816434019C6778F
+S11307603120401903703A23501C5B19187041233F
+S113077002320A435B191A7021004222024800F037
+S113078025FF15B0F0BDC0463C01002008B4024B63
+S11307909C46103808BC60476506000070B50A79AD
+S11307A0037D0C0000259A420BD10B784E78A12BC7
+S11307B009D1212E05D107221F49204800F006FF48
+S11307C00135280070BD212BFBD1202E19D1072221
+S11307D019491A4800F03CFE174B1A785978090257
+S11307E011439A7812041143DA7812060A439621C7
+S11307F0C9008A4202D1DB79DB0708D5FFF77AFD0D
+S113080008E0222E0AD18A780B4BDA71E4E7FA2049
+S1130810FFF766FD0021094800F0EEFF0125232EB5
+S1130820CFD1E378A2781B021343054A0021034881
+S1130830136000F0E1FFC4E7080000203C01002041
+S11308400400002008B4024B9C46103808BC6047E2
+S11308509D07000010B5417D006A013100F02EFDB6
+S1130860034B1B6801335A1E9341181810BDC04630
+S11308701000002010B5417D006A023100F034FD03
+S113088010BD10B5417D006A023100F0FBFC10BDC3
+S113089070B50D00417D0400130002312A00006A86
+S11308A000F0EAFD002801D10123636070BD00005F
+S11308B010B5054C23685A1C04D103685B6998473A
+S11308C003002060180010BD10000020074A030038
+S11308D0106810B5411C03D001235B42136010BDA6
+S11308E0597D186A013100F077FDF8E71000002007
+S11308F0FA239B0070B504008360032383752300EF
+S1130900002228334260A3610C4B02201D004433B3
+S113091023610835631DE26125602162E075DA77A1
+S11309208323A362013B2363E06200F0ADF821005E
+S1130930103100F07DF8200070BDC046F829000099
+S113094010B5437D094A0220590101331268DBB214
+S11309505B015118D3180122FF318C7AFF332043F5
+S11309608872997A0A439A7210BDC046F405002031
+S11309707047000010B502490248FFF7B9FF10BDE7
+S11309803C010020D400002070B50E00002544680E
+S1130990002C0BD0236831005B68200098470028A6
+S11309A002DB2D18E468F3E701256D42280070BDD1
+S11309B070B50D004468002C08D0236829009B689A
+S11309C020009847002802D1E468F4E7200070BDB5
+S11309D070B50D0000264468002C09D02368290056
+S11309E020001B69984736182D18F6B2E468F3E71F
+S11309F030002C7070BD70B50D004468002C08D018
+S1130A00236829001B6820009847002802D1E46865
+S1130A10F4E7200070BD70B50D004468002C06D0CA
+S1130A2023682000DB6829009847E468F6E770BD76
+S1130A30F0B58C79457803002A190020072A1FDCB9
+S1130A405A68824216D159601A78C8790A71121804
+S1130A504D711A7000220B4D944210DD8F68587846
+S1130A609600F7590132860001307751D2B258709E
+S1130A70F2E70200D0680028FBD1D160E4E701204E
+S1130A80F0BDC046140100200122054905480B6849
+S1130A90134003D10370427043600A607047C0463C
+S1130AA0080100200C010020704710B5040001F07B
+S1130AB09BFA200010BD0000F0B5822919D1C3B201
+S1130AC0294D5A01AA189169284C80010C40C02173
+S1130AD08905214391612649083308187021506122
+S1130AE028685B011A5C8A43110030220A431A54B5
+S1130AF0F0BD0029FCD1C026C1B21B4C4B01E31848
+S1130B009A681A4DB6052A4032439A60194A800100
+S1130B1012185A600A000727246808325201115D2E
+S1130B20B9430F000121394311559F6910493D40D4
+S1130B3008182E439E6158617020115D814308009E
+S1130B4010210143115599680B48A21808408021CF
+S1130B504903014399609968890B8903996040238B
+S1130B6011790B431371C3E7F4050020FFFFFF8FD6
+S1130B706801002028030020FF3F00F0EFF31083FA
+S1130B8003600123436072B670470368002B02D1EF
+S1130B9062B6BFF36F8F7047F7B50600FC36B369D2
+S1130BA00400002B18D1B2277F00C55D6846FFF70B
+S1130BB0E5FF019BEDB2013B02D3E55DEDB2FAE73F
+S1130BC068460193FFF7E1FF002D01D10020FEBD2F
+S1130BD0706E336EC01AFAE76846FFF7CFFFD8226B
+S1130BE00025019B5200013B02D3A55CEDB2FAE75C
+S1130BF068460193FFF7C9FF002DE7D0D6235B00B9
+S1130C00E058043BE358E5E710B54468FC30436919
+S1130C100B48DBB25A01A2189168083308408021BE
+S1130C2049030143916091685B01890B89039160D9
+S1130C302268D318402219790A431A7110BDC0469C
+S1130C40FF3F00F0F7B50500FC352B7D4268190025
+S1130C5004000831106849014118C979C90711D540
+S1130C605B01D21893689B049B0C0CD12000FFF706
+S1130C70CBFF63681A686B69DBB208335B01D31876
+S1130C807F22DA71F7BDE969002923D16B6623005D
+S1130C9001266933FF33EE6168465360B227FFF7DC
+S1130CA06DFF7F00B221019BFF31013B5A1C38D0FC
+S1130CB0D822E6555200A25C581ED2B26254625C3D
+S1130CC08446002A04D120000193FFF79DFFE9E741
+S1130CD06346EBE7D621490063500023EB61230010
+S1130CE01D33FF3353606846D826FFF747FF0127BB
+S1130CF07600B221019BFF31013B5A1C11D0B22274
+S1130D00A7555200A25C581ED2B26254625C84465B
+S1130D10002A04D120000193FFF776FFE9E7634638
+S1130D20EBE768460193FFF730FFA2E7F7B505004C
+S1130D3068462C00FFF722FF0027FF22019BFC34AA
+S1130D40013B0DD3E0682169884204DBE768206930
+S1130D50D71B3F18F4E72769E1687F1A013FEFE7E3
+S1130D6068460193FFF711FFA3696846002B41D140
+S1130D70FFF704FFB221019B4900013B5A1C0CD030
+S1130D806E5C5A1EF6B2002E05D168460193FFF739
+S1130D90FCFE3000FEBD1300F0E768460193002618
+S1130DA0FFF7F3FEFF22BE4203D0236E616E8B4237
+S1130DB060D3636E226E9A42EBD100232366013323
+S1130DC0A3616846B224FFF7D9FE6400B222002171
+S1130DD0019BFF32013B581CD7D02955A85C5F1EEC
+S1130DE0002805D0A95428000193FFF70DFFEDE773
+S1130DF03B00F0E7FFF7C2FED821019B4900013B0D
+S1130E005A1C06D06E5C5A1EF6B2002EBDD01300DA
+S1130E10F6E768460193FFF7B8FED4220026520095
+S1130E20BE4205D0D6214900AB5869588B4232D313
+S1130E30D6235B00EB58A9589942AAD100236846EF
+S1130E40AB50A361D824FFF799FE6400B2220021BD
+S1130E50019BFF32013B581C97D02955A85C5F1EAB
+S1130E60002805D0A95428000193FFF7CDFEEDE733
+S1130E703B00F0E7591CEB18FF332166597FE36808
+S1130E80206901331340834203D0E06828180172BB
+S1130E90E360013687E7591CA950FF21EB18693339
+S1130EA0FF331B789C46E36801330B4021698B4276
+S1130EB004D06046E16869180872E3600136AFE760
+S1130EC010B50400FFF732FF2300FC331969DA6818
+S1130ED0914203D01B69E418207A10BD01204042DE
+S1130EE0FBE710B50400FC34FFF720FFE06823693A
+S1130EF0C01A01D50130FF3010BDF0B585B00192A4
+S1130F0000910500FFF712FF02A8FFF737FE01204A
+S1130F100024FF26039A4042013A1DD32B00FC33E0
+S1130F2001998C42F8D2D9681F69C91B01D50131D6
+S1130F30FF310029F0D01969DF688C460100BC45F7
+S1130F4006D019691F69691801373740097A1F618A
+S1130F50009F39550134E3E702A80392FFF715FE19
+S1130F60200005B0F0BD37B56B46DC1D00230D0035
+S1130F702370FFF789FD2100FFF706FD2B68181881
+S1130F80286020783EBD0000F8B520233E4A0500C5
+S1130F90D1690F200B43D36101223C490B781343E1
+S1130FA00B703B4B19788143197006211C7821433F
+S1130FB0197038490C7822430A701A7802401A7062
+S1130FC0602219780A431A70334B344A5A805F7886
+S1130FD0FF09FCD13248FFF7FFF8324E01233000FD
+S1130FE010C839002278134380222370520001F084
+S1130FF01CFCA378DB07FCD41F2004362A4B666252
+S11310001B685A0B990C9B01024001405B0F824202
+S113101000D105221F2900D10239072B00D1043B3E
+S1131020268D224F02403E40920132432285228D7A
+S1131030014082430E00110031432185228D1903A2
+S11310401B4B1C4813407F220B4323852378C1216B
+S11310501340237004232278890013430C22237045
+S113106023899343144A238153581B021B0A535068
+S11310708023136022787E3B1343237001230021D5
+S11310802B70FFF775FCF8BD000400405844004184
+S11310903C44004159440041000C0040064000001B
+S11310A00D1A0000F4050020246080003FF8FFFFC3
+S11310B0FF8FFFFFD400002000E100E0007800284B
+S11310C010D00121084B1B681A898A431A8108220F
+S11310D0198B0A431A830422198B0A431A830022A8
+S11310E0024B1A607047C046F4050020EC0500204E
+S11310F010B50F4A93699B0B9B03936113680222FB
+S1131100FF331A729879823A02439A711A7A9207D3
+S1131110FCD57F24074A2140937A0800A343190091
+S1131120802301439172917A5B420B43937210BD09
+S1131130F40500200050004110B50C00FFF7A4FC9A
+S11311402100FFF758FC002804D1034A93699B0B44
+S11311509B03936110BDC046F4050020F8B50D0053
+S1131160832A19D1CBB2394C5A01A2189169384853
+S1131170AD010840C02189050143916135492068CA
+S11311804D197021083355615B011A5C8A431100C3
+S113119040220A431A54F8BD022A52D12E4A8B0027
+S11311A09858002802D003685B699847DA20400009
+S11311B000F016FF80220400244E284B4660036092
+S11311C052000021083001F030FB22000023FC32E1
+S11311D0D3605561136113669361D3615366B22280
+S11311E05200A3544432A3500432A3500432A354F3
+S11311F0B222FF32A354EAB2500131188B68144F63
+S113120008321F40C0239B053B4307278B6033688C
+S11312105201D65CAD00BE43B446032667463E4346
+S1131220D65422001D32FF324A6001221B18FF33BC
+S1131230997A20000A439A72FFF7E6FC064B5C5148
+S1131240A9E711002800FFF737FCA4E7F405002004
+S1131250FFFFFF8F6801002040010020582A000092
+S113126070B505000124064BA200D258002A06D00E
+S1131270210028000134FFF771FF0A2CF3D170BD5F
+S1131280140100200B4BCAB20B48890159185301B1
+S1131290C318596199690832890B890399610368F4
+S11312A052019A180223D3715179823B0B43537133
+S11312B07047C04668010020F4050020084B8A00EE
+S11312C0D05810B5002803D003689B68984710BD18
+S11312D0C9B2044B4901591888688004800CF6E7A8
+S11312E040010020F405002010B50C00FFF7E6FFD4
+S11312F000280CD0064BE4B21B68083464011C19A6
+S1131300802362795B42134363710223E37110BD4E
+S1131310F4050020F0B51C002B4B85B01B680700BA
+S11313200D000292002B4BD0284B8A00D058002885
+S113133008D0036822005B680299984704002000E3
+S113134005B0F0BD3800FFF7B9FF844204D9290085
+S11313503800FFF7B3FF04000121EBB21C4E0393E6
+S11313605B010193F21893689B0B9B039360019AB2
+S1131370336802989B18FF335A7A0A4315495A7204
+S1131380AB01C918220001F047FA002CD7D029007C
+S11313903800FFF793FF0028D1D14021039B326826
+S11313A008335B01D3181879014319710121D971EC
+S11313B00121019BD318FF339A7A0A439A72BEE73C
+S11313C001246442BBE7C046EC0500204001002034
+S11313D0F40500202803002013B56B46DC1D220011
+S11313E00123FFF797FF012801D1207816BD0120C2
+S11313F04042FBE770B5134BCCB2134A600189013C
+S11314005918131859609968104D08340D408021FB
+S113141049032943402599609968890B8903996098
+S113142011686301CB181E7935431D719D796D06D2
+S1131430FCD564010919CB79DB07FCD51218906837
+S1131440C0B270BD28030020F4050020FF3F00F067
+S113145070B50D0000211400FFF7CCFFA04200D9A5
+S1131460200000230349A34203D05A5CEA54013309
+S1131470F9E770BD28030020F0B51E003A4B85B093
+S11314801B680F000192002B35D08023DB019E42A4
+S113149031D80025354A8B01D3180293002E2CD065
+S11314A0334B1B680393FF233B401C000093083419
+S11314B0039B64011C19A379DB0921D02D4B2E4910
+S11314C0186801F0E5F82D4B1721584301F0E0F8B6
+S11314D02B4BE279920713D4DA5D002A01D101384B
+S11314E0F7D20122DA55009B214A5B01D3189A698D
+S11314F0920B92039A6101256D42280005B0F0BD5C
+S113150000221F4B3400DA553F2E09D9009B40249A
+S11315105A01174B9B188022996912060A439A6153
+S113152022000199029801F077F9009BA1045A0165
+S11315300F4B890C9B18029A2D195A619A69361B14
+S1131540920B92030A439A61009B039A08335B014E
+S1131550D3180222DA715979823A0A435A71019BEB
+S11315601B1901939AE7C046EC050020680100208E
+S1131570F40500201400002040420F007011010007
+S11315805D01002070B50D001C000D4EAB01F61876
+S113159011003000220001F03FF9EDB209496D015C
+S11315A04D196E61AB69084A20001340AB61AB6909
+S11315B0A2049B0B920C9B031343AB6170BDC0460A
+S11315C068010020F4050020FF3F00F0F7B5104B40
+S11315D001901B780F001500002B0CD10D4B160049
+S11315E01C78002C09D00C4E0C483488001964195E
+S11315F001F012F934802800FEBD002EFBD03A1908
+S1131600330000210198FFF7BDFF2418361AF4E7D0
+S1131610E8040020E9050020EA050020E904002090
+S1131620F8B50E0015000027012A27D9100001F093
+S1131630DFF80400300001F0BBF90130400003235F
+S1131640207002223800637095420DD93178002948
+S11316500AD0531CDBB20136A1549D4203D002329E
+S1131660E054D2B2F0E72A0021000548FFF7AEFFAC
+S1131670471EB841C7B2200001F0C4F83800F8BDD5
+S11316803C010020F0B50027012687B01E4B0091D5
+S113169002A91E7005000297FFF765FC03AC0190D8
+S11316A009223900200001F0C0F809232370022325
+S11316B063709E33E3715A332372029B667109335C
+S11316C063806B461B7923710F4B1F70009B092BA2
+S11316D007D11A0021002800FFF778FF012007B086
+S11316E0F0BD0A4B09221E70094E21002800029702
+S11316F03780FFF76BFF02A92800FFF734FC034B88
+S113170032881F700349E6E7E8040020E905002059
+S1131710EA050020E904002070B5CE7892B00500F7
+S11317200C00022E0BD18B79C9792E48090219437A
+S1131730FFF7A8FF411E8841C0B212B070BDFFF789
+S1131740A3F92100FFF734F9002803D0C117081AC0
+S1131750C00FF2E7012E0ED1E279A37912021A43E7
+S11317602149112A3CDCD2B2002A39D02800FFF7E3
+S11317702DFF0120E1E7032EDFD1A378002B28D031
+S1131780022B08D1E279A379120218491A432800DE
+S1131790FFF746FFD1E7012B05D1E279A3791202C5
+S11317A01A431349F3E7032BC7D10100412201A8CF
+S11317B001F03BF8FFF768F901A9FFF709F90028E0
+S11317C005D0E279A37912021A4301A9DFE703786D
+S11317D0FFDEE279A37912021A430649032AC2DD25
+S11317E00A78C3E73C0100208F2A0000742A000015
+S11317F0822A00007E2A0000CBB204495B01C9188A
+S11318008B699B0B9B038B617047C046F4050020DA
+S113181037B5050048780C000B2811D800F02EFFCE
+S1131820061D102E104348644C4F5D60097801AAD0
+S1131830002907D10223117051702800FFF7A2FE7E
+S113184001203EBD002313705370284B1B78012BDD
+S113185000D1137002230021EFE78A780023012AC4
+S113186004D101AA13705370214BEFE71F4A137080
+S1131870204A93699B0B9B039361E1E78C78012CCD
+S113188006D100211A4B01AA1C7011702300D4E761
+S11318900120002CD5D1154B164A187093699B0B67
+S11318A09B039361CDE789782800FFF721FCC7E704
+S11318B02800FFF731FFC4E701230F4ACBE70B7879
+S11318C00020DB06BDD12800FFF7CAFCA2780A4B32
+S11318D00A481A60FFF734F8CAE70123084ABAE74E
+S11318E08A78074B1A60C3E70020AAE75C0100204E
+S11318F064010020F4050020EC050020D400002041
+S1131900F00500203B4BF7B51E780500002E61D191
+S1131910394C23689A8B12070DD5082231009A831B
+S11319203000FFF7C9F810222368FF33997A0A437D
+S11319309A72324B1E6023689A8B520701D5042297
+S11319409A83FF331A7A920603D52022597A0A43DE
+S11319505A721A7AD20625D56846294A6946C0CAF7
+S1131960C0C0A268920B9203A2604022587902433D
+S11319705A7160230A7828001A422CD1FFF748FFD5
+S113198000282BD0802223685242FF3399790A43DE
+S11319909A712368FF331A7A520603D54022597A82
+S11319A00A435A727F2601252368FF331E722F00D3
+S11319B0236808377F01DB19DB79002B07D0114B33
+S11319C0AA00D05800280CD003681B68984701353A
+S11319D0082DECD1F7BDFFF7AFFBD1E720220A4B6E
+S11319E0D6E7FFF751F82900FFF715F82368DF1948
+S11319F0FE71ECE7E9050020F4050020EC05002069
+S1131A002803002040010020FF50004110B5024887
+S1131A10FFF778FF10BDC0463C010020014A024B8D
+S1131A201A60704700500041F4050020FA21314B40
+S1131A3010B51868890000F02BFE2F4B013898422E
+S1131A4056D82E492E4A4860C020136A00061B024D
+S1131A501B0A03431362002407238C600B6080215C
+S1131A60136A09061B021B0A0B431362FC22254B53
+S1131A70196A0A431A62FC22196A92010A431A6219
+S1131A80A022196AD2020A431A62200000210134FA
+S1131A9000F076F9142CF8D11B4B1C005A7852B282
+S1131AA0002AFBDB194A5A80194B1A00597EC909CE
+S1131AB00129FBD0E421C90099803F21D970537ECC
+S1131AC0DB09012BFBD0C02300205B011361907064
+S1131AD000F034F863785BB2002BFBDB0D4B0E4A4D
+S1131AE06380D379DB09012BFBD04123537010BDF4
+S1131AF0FEE7C04614000020FFFFFF0010E000E0F6
+S1131B0000ED00E000040040000C00401E40000016
+S1131B10004000422140000000480042914202D0AF
+S1131B2002D98A1AD0407047521A9040FBE700004D
+S1131B30014B18607047C04618000020164A00B5D3
+S1131B401300517EC9090129FBD00138042816D895
+S1131B501969124A0A400F211A615A788A4300F01F
+S1131B608DFD0308060B0300110001220A435A707D
+S1131B7000BD11000322F9E711000222F6E7F02369
+S1131B8011691B050B430F21136153788B43190013
+S1131B9002230B435370EBE700400042FFFFFFF0CA
+S1131BA018234343F0B56D4A87B09B18DA680700E1
+S1131BB00C000092920722D51B7C5BB2002B01D053
+S1131BC0142B1AD1664B0A2219682000FFF7A6FFCE
+S1131BD0644A1300D179C9090129FBD08005800D1D
+S1131BE01081DA79D209012AFBD0022219780A433A
+S1131BF01A70DA79D209012AFBD007B0F0BD0826A1
+S1131C00009A574D3240019200D196E012229B5E19
+S1131C102968200010220193FFF780FF019B050033
+S1131C201E126B461C79009B0421DB0600D405219F
+S1131C30380000F01DF94C4B9A5D002A58D101324E
+S1131C409A554A490F3202A800F0E6FD02AA730031
+S1131C509B5A8022D2011A43454B5A805A78D209A2
+S1131C60012AFBD0434AB300D358022E1CD90221C7
+S1131C701A888A431A80DA7BD209FCD11988403247
+S1131C800A431A80DA7BD209FCD10C34ADB2640069
+S1131C90E552DA7BD209FCD1198802320A431A8050
+S1131CA0DA7BD209FCD1A8E702211A688A433249B7
+S1131CB01A600A0098680842FCD10221D86B0143DB
+S1131CC0D96399681142FCD11034A4001C196560D1
+S1131CD099681142FCD12949196499681142FCD1CF
+S1131CE0022118680143196099681142FCD184E704
+S1131CF0204AB300022E08D9D2580C34ADB2640085
+S1131D00A552D37BDB09FCD177E7D358022259795A
+S1131D100A435A71184A110098681042FCD11C34C5
+S1131D20A400E5509A680A42FCD1022218790243C1
+S1131D301A719A680A42FCD15FE7012100F020F889
+S1131D40296832002000FFF7E9FE01997F2800D9B5
+S1131D500121380000F060F84FE7C046B42A0000C3
+S1131D601800002000480042F8060020A22A0000C3
+S1131D70000C00401C000020FF0F7F00FFFF00004C
+S1131D80182330B51D00040045430820204A551986
+S1131D902856013014D0032912D808006343D156C1
+S1131DA0D31800F06BFC02280E1B5868CB010221EB
+S1131DB0184A9B181A1840321170012282405A6046
+S1131DC030BD5868CB010621124A9B181A184032BC
+S1131DD01170012282405A609A61F1E75868CB0180
+S1131DE006210C4A9B181A184032117001228240B5
+S1131DF05A605A61E4E75868CB010221054A9B18EE
+S1131E001A1840321170012282409A60D8E7C04605
+S1131E10B42A0000004400411823F0B508245843B4
+S1131E20114A13181C5701341BD0012635005F6872
+S1131E308356BD400D4ADB019A18906828420BD1A5
+S1131E400C00601E8441D2194032107834400336AD
+S1131E50A400B04320431070044A9B18002901D108
+S1131E605D61F0BD9D61FCE7B42A000000440041BF
+S1131E70F8B50300182058432A4A1018007A40B2D3
+S1131E800400013013D0481C00240C280FD800F0A3
+S1131E90F5FB451C1C1C1C1C1C1C1C07070707000D
+S1131EA0092906D100211800FFF76AFF0024200049
+S1131EB0F8BD0A2901D10839F5E700240B29F6D128
+S1131EC00A391800FFF75CFFF1E718204343D018E4
+S1131ED0466801253400D2561348D20112187308FB
+S1131EE0D31830332C401878002C0BD00F24090160
+S1131EF020400143C9B292191970403213781D432E
+S1131F001570D3E70F27B84301439219C9B219706A
+S1131F10130040331A7815431D70C8E70124644246
+S1131F20C5E7C046B42A00000044004110B5024889
+S1131F3000F0A9FA10BDC0460007002010B5024801
+S1131F4000F0A1FA10BDC0463C090020F7B50124F9
+S1131F500326154F1549380000F04AF8144915486E
+S1131F6000F046F81449154800F042F814491548A1
+S1131F7000F03EF81449154800F03AF8144D15499C
+S1131F80280000F035F8390000962300019400225F
+S1131F90114800F00DFA0096290001941E231F2217
+S1131FA00E4800F005FAF7BD780B00200008004247
+S1131FB0000C00427C0B002000100042800B00202B
+S1131FC000140042840B002000180042880B0020FB
+S1131FD08C0B0020001C0042000700203C0900205C
+S1131FE010B500F005FC10BD10B500F00BFC10BDE1
+S1131FF001607047F0B505AC25780468981E471E4B
+S1132000B841266892070006324302430720226043
+S11320100140AD01626829430020022B00D058031F
+S1132020114301436160F0BD10B5C0240368A403EB
+S11320301868120522400243C020090480020140AE
+S1132040114319605A681043586010BD0122036897
+S113205019680A431A601A68D207FCD4DA69D207ED
+S1132060F9D470470222036819680A431A60DA69CE
+S11320709207FCD4704703681A7ED20702D41A7EF2
+S11320809207FCD57047002203685A83704703689F
+S1132090187E4007C00F70470368187EC009704758
+S11320A0802302685B42117E0B43137670470368FA
+S11320B0588B8007C00F704702230268518B0B4373
+S11320C0538370470368187EC007C00F70470368C6
+S11320D0188DC0B2704703681A7ED207FCD589B246
+S11320E0012019857047012203689A7570470122FF
+S11320F003681A75704700000368214A30B593429B
+S113210011D0204A93422FD01F4A93422FD01F4A06
+S113211093422FD01E4A93422FD01E4A934222D17B
+S11321200E23192201E009231422012103259940D9
+S11321301948C024016099082B40AB40FC359D40F0
+S113214089000918A4000859A843C0259D402B0004
+S113215003430B518023DB011A43104B5A805A78F6
+S113216052B2002AFBDB30BD0A231522DDE70B2324
+S11321701622DAE70C231722D7E70D231822D4E717
+S113218000080042000C004200100042001400420B
+S113219000180042001C004200E100E0000C004076
+S11321A0F8B5040016000F001D00FFF7A5FF20007E
+S11321B0FFF74CFF1C22BB00134072072468120C6B
+S11321C0134323608423A375012F18D11021012EFA
+S11321D000D008390A4B69431868C00000F058FA67
+S11321E00722A3890240DB045203DB0C1343A381BF
+S11321F00304A089DB0C400B40031843A081F8BD05
+S1132200140000200120704710B50368014A1B6ABE
+S1132210984710BD130400000300FC33D9699A6980
+S1132220914203D0DB69C018007D70470120404211
+S1132230FBE710B504000069FFF708FF2200002344
+S1132240FC329361D36186229200A4186360A36078
+S113225010BDF02001403039484248417047F02316
+S11322601B011940802306209B0099420AD00133A8
+S1132270FF330130994205D0802302385B00994234
+S113228000D0002070470F2001400020012903D016
+S11322900239481E8141481C704700008923F0B56B
+S11322A0182685B002919B000400C05C330008210D
+S11322B04343324D1700EB185956FFF7D9FD304B05
+S11322C00821E05C33004343EB185956FFF7D0FD77
+S11322D02C4BE25C0393022A09D11133E05CFF2802
+S11322E005D008214643AE197156FFF7C1FD8A2671
+S11322F0B600A05DFF2819D00121FFF741FD182287
+S1132300A35D21495A43AB56AD18DB0158188B2104
+S1132310890060501D4901225B188C21890063509B
+S113232069688A408D21890062501A600122029BEB
+S113233011002069FFF734FF39002000FFF78FFFF9
+S1132340390005002000FFF79EFF39000600200039
+S1132350FFF77FFF33000090290020690122FFF777
+S113236049FE0B4B2069E25C039BE15CFFF75CFEDA
+S11323702069FFF777FE05B0F0BDC046B42A00001F
+S113238025020000270200001844004114440041C3
+S113239026020000802210B504005200002100F043
+S11323A044FA23000022FC335A6020009A6010BDD6
+S11323B0F7B51D0008AB1B780400009309AB1B782C
+S11323C01600019300234360FA239B008360114BA2
+S11323D00F00083303601430FFF7DCFF20001D30CA
+S11323E0FF30FFF7D7FF89236A469B002761E65435
+S11323F0094B1278E554094B2000E2546A46084B15
+S11324001279E2548A22293BFF3B9200A3541032F2
+S1132410A354FEBD042F0000250200002602000084
+S1132420270200000300FC3358689B68C01A01D5DA
+S11324300130FF30704710B5040020001D30FF301C
+S1132440FFF7F0FF0028F8D12069FFF714FE10BD54
+S113245010B51430FFF7E6FF10BD0300FC335968D4
+S11324609A68914204DB5A689868801AFF30704772
+S113247098685B68C01A0138F9E710B51D30FF3061
+S1132480FFF7EBFF10BD10B504000069FFF70FFE66
+S1132490002805D02069FFF71AFE2069FFF70CFE1B
+S11324A02069FFF7F4FD002820D02069FFF70FFE14
+S11324B02200FC329369D1690133DBB28B4203D031
+S11324C091696118087593618A239B00E35CFF2B73
+S11324D00CD020001430FFF7C0FF092806DC8B2342
+S11324E08D229B009200E358A2581A602069FFF7DE
+S11324F0E9FD00281AD020001D30FF30FFF792FFBD
+S1132500002822D086239B00E31899685A689142D8
+S113251018D08E219A684900A218515C9A68013239
+S1132520D2B29A60C9B22069FFF7D5FD2069FFF7DE
+S1132530B3FD002805D02069FFF7B2FD2069FFF73D
+S1132540A2FD10BD01214942ECE72069FFF7CFFD50
+S1132550ECE7000070B5040000690D00FFF7B2FD60
+S1132560002824D1FF2686239B00E3185A68996823
+S1132570013232408A422FD1EFF31083DB070DD4AE
+S11325801E4B5B68DB05DB0DEDD0103B5BB2002B13
+S113259019DB9B08C0331A4A9B009B582069FFF73C
+S11325A091FD0028DFD02000FFF76DFFDBE720005E
+S11325B01D30FF30FFF736FF0028D3D129002069F2
+S11325C0FFF789FD17E00F221340083B9B080D4AD3
+S11325D09B009B181B68E1E75A68013216409A6811
+S11325E0964205D08E215A684900A21855545E605F
+S11325F02069FFF778FD012070BDC04600ED00E0C2
+S113260000E100E01CED00E00300FC33D9699A69A5
+S113261070B5040091421AD0DA698218157DDA691E
+S11326200132D2B2DA618A239B00E35CFF2B0CD027
+S113263020001430FFF711FF0A2806DD8C238D22B9
+S11326409B009200E358A2581A60280070BD01252F
+S11326506D42E8E7F7B506000D000C008B180193F6
+S1132660019B671B9C4207D0336821781B683000AC
+S1132670984701340028F3D13800FEBD02B47146F6
+S113268049084900095C49008E4402BC7047C046B1
+S1132690002243088B4274D303098B425FD3030A9D
+S11326A08B4244D3030B8B4228D3030C8B420DD3B0
+S11326B0FF22090212BA030C8B4202D3121209023E
+S11326C065D0030B8B4219D300E0090AC30B8B427C
+S11326D001D3CB03C01A5241830B8B4201D38B032A
+S11326E0C01A5241430B8B4201D34B03C01A5241CF
+S11326F0030B8B4201D30B03C01A5241C30A8B4212
+S113270001D3CB02C01A5241830A8B4201D38B02FC
+S1132710C01A5241430A8B4201D34B02C01A5241A0
+S1132720030A8B4201D30B02C01A5241CDD2C30912
+S11327308B4201D3CB01C01A524183098B4201D38E
+S11327408B01C01A524143098B4201D34B01C01A79
+S1132750524103098B4201D30B01C01A5241C308F1
+S11327608B4201D3CB00C01A524183088B4201D360
+S11327708B00C01A524143088B4201D34B00C01A4C
+S11327805241411A00D20146524110467047FFE7B8
+S113279001B5002000F006F802BDC0460029F7D0BC
+S11327A076E770477047C04670B500260C4D0D4C57
+S11327B0641BA410A64209D1002600F011F90A4DA9
+S11327C00A4C641BA410A64205D170BDB300EB589B
+S11327D098470136EEE7B300EB5898470136F2E725
+S11327E0980000209800002098000020A8000020F5
+S11327F010B5034B0100186800F06AF810BDC0461C
+S11328003400002010B5034B0100186800F016F8DE
+S113281010BDC04634000020002310B59A4200D1F8
+S113282010BDCC5CC4540133F8E703008218934212
+S113283000D1704719700133F9E7000070B5050045
+S1132840002910D00C1F2368002B00DAE41828009C
+S113285000F0B5F81D4A1368002B05D163601460BD
+S1132860280000F0ADF870BDA34209D921686018B2
+S11328708342F3D118685B6841182160EEE71300C6
+S11328805A68002A01D0A242F9D919685818A042FE
+S11328900BD120680918581819608242E0D11068D9
+S11328A05268411819605A60DAE7A04202D90C2331
+S11328B02B60D5E721686018824203D11068526802
+S11328C04118216062605C60CAE7C046900B00203A
+S11328D0032370B5CD1C9D43083506000C2D1ED274
+S11328E00C25A9421DD8300000F069F8254A146867
+S11328F02100002919D1244C2368002B03D1300076
+S113290000F044F820602900300000F03FF8431C38
+S11329102CD10C233000336000F052F803E0002D7A
+S1132920DFDA0C233360002070BD0B685B1B1AD404
+S11329300B2B03D90B60CC18256003E08C420ED11D
+S113294063681360300000F03BF8200007220B306E
+S1132950231D9043C31AE7D05A42E250E4E74B6880
+S113296063600C00EEE70C004968C2E70323C41C53
+S11329709C43A042E0D0211A300000F007F8431C29
+S1132980DAD1C6E7900B0020940B0020002370B529
+S1132990064C05000800236000F014F8431C03D122
+S11329A02368002B00D02B6070BDC0469C0B002018
+S11329B00023C25C0133002AFBD1581E70477047C4
+S11329C070470000044A1368002B03D018181060E5
+S11329D018007047014BF9E7980B0020A00B00206A
+S11329E0F8B5C046F8BC08BC9E467047F8B5C0466A
+S11329F0F8BC08BC9E4670470000000000000000C0
+S1132A0051060000910800004D0600007508000002
+S1132A1055080000CD080000B1080000830800003C
+S1132A2065060000AD0500009D070000E5050000F7
+S1132A3039060000F0FFFFFF000000004508000019
+S1132A408D070000B10500003D06000029060000C6
+S1132A500000000000000000450C0000FB0E000018
+S1132A60E30E0000C10E0000A90A0000AB0A00003A
+S1132A70990B000054696E795A65726F0000040363
+S1132A80090454696E794369726375697473001239
+S1132A90010002EF020140EB03098000010102037F
+S1132AA001001A001A001B001B001C001C001D0062
+S1132AB01D000000000000000B00000002000000E8
+S1132AC004000000FF00FFFFFFFF0B0000000000F8
+S1132AD00A0000000200000004000000FF00FFFFE5
+S1132AE0FFFF0A00000000000E00000008000000C4
+S1132AF004000000FF00FFFFFFFF0E0000000000C5
+S1132B0009000000040000001C000000FF00010098
+S1132B10010009000000000008000000040000009B
+S1132B201C000000FF000000000010000000000076
+S1132B300F000000040000001C000000FF0001035F
+S1132B4001030F0000000000140000000500000055
+S1132B501C000000FF00020002000400000000004E
+S1132B60150000000800000004000000FF00FFFF43
+S1132B70FFFF050000000000060000000400000044
+S1132B801C000000FF00000100010600000000001E
+S1132B9007000000040000001C000000FF00010109
+S1132BA00101070000000000120000000400000002
+S1132BB01C000000FF0000030003020000000000EE
+S1132BC010000000020000001C000000FF000002D2
+S1132BD000020000000000001300000002000000DA
+S1132BE01C000000FF0003000300030000000000BD
+S1132BF011000000020000000C000000FF000102B0
+S1132C00FFFF0100000000000200000001000000BE
+S1132C10020000000000FFFFFFFF020001000000AF
+S1132C200800000001000000020000000200FFFF95
+S1132C30FFFF08000100000009000000010000007F
+S1132C40020000000300FFFFFFFF09000000000076
+S1132C500400000001000000020000000400FFFF67
+S1132C60FFFF040000000000050000000100000058
+S1132C70020000000500FFFFFFFF05000100000047
+S1132C800200000001000000020000000A00FFFF33
+S1132C90FFFF020000000000160000000200000018
+S1132CA004000000FF00FFFFFFFF0600000000001B
+S1132CB0170000000200000004000000FF00FFFFF6
+S1132CC0FFFF0700000000000C00000003000000EC
+S1132CD004000000FF00FFFFFFFF0C0001000000E4
+S1132CE00A0000000300000004000000FF00FFFFD2
+S1132CF0FFFF0A00010000000B00000003000000B9
+S1132D0004000000FF00FFFFFFFF0B0001000000B4
+S1132D100300000008000000040000000B00FFFF97
+S1132D20FFFF0300000000001B000000080000007B
+S1132D3004000000FF00FFFFFFFF0F000000000081
+S1132D401C0000000600000000000000FF00FFFF60
+S1132D50FFFFFF0000000000180000000600000054
+S1132D6000000000FF00FFFFFFFFFF000000000065
+S1132D70190000000600000000000000FF00FFFF33
+S1132D80FFFFFF0001000000160000000300000028
+S1132D9000000000FF00FFFFFFFF0600010000002D
+S1132DA0170000000300000000000000FF00FFFF08
+S1132DB0FFFF0700000000001600000002000000F2
+S1132DC000000000FF00FFFFFFFFFF000000000005
+S1132DD0170000000200000000000000FF00FFFFD9
+S1132DE0FFFFFF00000000001300000002000000CD
+S1132DF000000000FF00FFFFFFFFFF0000000000D5
+S1132E00100000000200000000000000FF00FFFFAF
+S1132E10FFFFFF000000000012000000020000009D
+S1132E2000000000FF00FFFFFFFFFF0000000000A4
+S1132E30110000000200000000000000FF00FFFF7E
+S1132E40FFFFFF00000000000D0000000200000072
+S1132E500C000000FF000100FFFF0D000000000057
+S1132E6015000000050000000C000000FF00030036
+S1132E70FFFFFF0000000000060000000400000047
+S1132E800C000000FF000001FFFFFF000000000035
+S1132E9007000000040000000C000000FF00010116
+S1132EA0FFFFFF000000000003000000010000001D
+S1132EB0020000000100FFFFFFFFFF000000000010
+S1132EC00200000001000000020000001400FFFFE7
+S1132ED0FFFF0200000000001E00000008000000C8
+S1132EE004000000FF00FFFFFFFFFF0000000000E0
+S1132EF01F0000000800000004000000FF00FFFFA6
+S1132F00FFFFFF0000000000000000005525000046
+S1132F10552600007B2400003724000051240000C3
+S1132F200926000019220000092200009D22000049
+S10F2F3033220000052200000000000015
+S1132F3CFFFFFFFFFFFFFFFF00C2010000000800BE
+S1132F4CFFFFFFFF40420F0008000000002000427A
+S1132F5C0024004200280042002C004200300042B1
+S1132F6C0034004238000020000000000000000083
+S1132F7C0000000000000000000000000000000041
+S1132F8C0000000000000000000000000000000031
+S1132F9C0000000000000000000000000000000021
+S1132FAC0000000000000000000000000000000011
+S1132FBC0000000000000000000000000000000001
+S1132FCC0000000000000000DD0000007509000096
+S1132FDC1D1A00004D1F0000B50000000000000089
+S903017586
diff --git a/UsbReceive/UsbReceive/UsbReceive/Debug/makedep.mk b/UsbReceive/UsbReceive/UsbReceive/Debug/makedep.mk
new file mode 100644
index 0000000000000000000000000000000000000000..8c05dc05920fe88b4785300e7cacfc33d04a9fc2
--- /dev/null
+++ b/UsbReceive/UsbReceive/UsbReceive/Debug/makedep.mk
@@ -0,0 +1,6 @@
+################################################################################
+# Automatically-generated file. Do not edit or delete the file
+################################################################################
+
+Sketch.cpp
+
diff --git a/UsbReceive/UsbReceive/UsbReceive/Sketch.cpp b/UsbReceive/UsbReceive/UsbReceive/Sketch.cpp
new file mode 100644
index 0000000000000000000000000000000000000000..21af0242ce10f2f0f0823da74365ec0c7ad18b6f
--- /dev/null
+++ b/UsbReceive/UsbReceive/UsbReceive/Sketch.cpp
@@ -0,0 +1,66 @@
+/*Begining of Auto generated code by Atmel studio */
+#include <Arduino.h>
+
+/*End of auto generated code by Atmel studio */
+
+/*************************************************************************
+* Code that reads values sent from python through serial
+ ************************************************************************/
+
+//#include <Wire.h> // For I2C communication with sensor
+//#include <Wireling.h> // For interfacing with TinyCircuits Wirelings
+//Beginning of Auto generated function prototypes by Atmel Studio
+//End of Auto generated function prototypes by Atmel Studio
+
+// Make Serial Monitor compatible for all TinyCircuits processors
+#if defined(ARDUINO_ARCH_AVR)
+ #define SerialMonitorInterface Serial
+#elif defined(ARDUINO_ARCH_SAMD)
+ #define SerialMonitorInterface SerialUSB
+#endif
+
+
+void setup() {
+
+ SerialMonitorInterface.begin(115200);
+// Wire.begin();
+
+ // Initialize Wireling
+// Wireling.begin();
+// Wireling.selectPort(0);
+
+ analogWriteResolution(10); // Change the DAC resolution to 10-bits
+ analogWrite(A0, 0); // Initialize Dac to Zero
+
+}
+
+void loop() {
+ int output;
+ //static float x = 270; // Current degrees for sine wave (initially 270 so that
+ // the sine wave is initially zero).
+
+ // output = (int) (512.0 * sin(0.017453 * x) + 512); // Sine Wave
+ if (SerialMonitorInterface.available()> -1) {
+ output = SerialMonitorInterface.parseInt();
+
+ analogWrite(A0, output);
+
+ }// end if serial available
+ //analogWrite(A0, output); // Write the analog output to A0
+ //SerialMonitorInterface.print(output);
+ //SerialMonitorInterface.println();
+
+ /*
+ * Increment Degrees for the Next Wave Point
+ *
+ * To utilize the entire resolution of the 10-bit DAC, at least 1024
+ * values must be used between 0 and 360 degrees. Therefore, a step
+ * value greater than 360/1024 will not utilize the entire resolution
+ * of the DAC.
+ */
+ //x += 0.35;
+ //if(x>=360.0) x -= 360.0;
+
+
+ //delay(1);
+}
diff --git a/UsbReceive/UsbReceive/UsbReceive/UsbReceive.componentinfo.xml b/UsbReceive/UsbReceive/UsbReceive/UsbReceive.componentinfo.xml
new file mode 100644
index 0000000000000000000000000000000000000000..b369e956f3f241ae1dca6f7a412d9552a74c3e5b
--- /dev/null
+++ b/UsbReceive/UsbReceive/UsbReceive/UsbReceive.componentinfo.xml
@@ -0,0 +1,53 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Store xmlns:i="http://www.w3.org/2001/XMLSchema-instance" xmlns="AtmelPackComponentManagement">
+ <ProjectComponents>
+ <ProjectComponent z:Id="i1" xmlns:z="http://schemas.microsoft.com/2003/10/Serialization/">
+ <CApiVersion></CApiVersion>
+ <CBundle></CBundle>
+ <CClass>CMSIS</CClass>
+ <CGroup>CORE</CGroup>
+ <CSub></CSub>
+ <CVariant></CVariant>
+ <CVendor>ARM</CVendor>
+ <CVersion>5.1.2</CVersion>
+ <DefaultRepoPath>C:/Program Files (x86)\Atmel\Studio\7.0\Packs</DefaultRepoPath>
+ <DependentComponents xmlns:d4p1="http://schemas.microsoft.com/2003/10/Serialization/Arrays" />
+ <Description></Description>
+ <Files xmlns:d4p1="http://schemas.microsoft.com/2003/10/Serialization/Arrays">
+ <d4p1:anyType i:type="FileInfo">
+ <AbsolutePath>C:/Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Documentation\Core\html\index.html</AbsolutePath>
+ <Attribute></Attribute>
+ <Category>doc</Category>
+ <Condition></Condition>
+ <FileContentHash i:nil="true" />
+ <FileVersion></FileVersion>
+ <Name>CMSIS/Documentation/Core/html/index.html</Name>
+ <SelectString></SelectString>
+ <SourcePath></SourcePath>
+ </d4p1:anyType>
+ <d4p1:anyType i:type="FileInfo">
+ <AbsolutePath>C:/Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include\</AbsolutePath>
+ <Attribute></Attribute>
+ <Category>include</Category>
+ <Condition></Condition>
+ <FileContentHash i:nil="true" />
+ <FileVersion></FileVersion>
+ <Name>CMSIS/Core/Include/</Name>
+ <SelectString></SelectString>
+ <SourcePath></SourcePath>
+ </d4p1:anyType>
+ </Files>
+ <PackName>CMSIS</PackName>
+ <PackPath>C:/Program Files (x86)/Atmel/Studio/7.0/Packs/arm/CMSIS/5.4.0/ARM.CMSIS.pdsc</PackPath>
+ <PackVersion>5.4.0</PackVersion>
+ <PresentInProject>true</PresentInProject>
+ <ReferenceConditionId>ARMv6_7_8-M Device</ReferenceConditionId>
+ <RteComponents xmlns:d4p1="http://schemas.microsoft.com/2003/10/Serialization/Arrays">
+ <d4p1:string></d4p1:string>
+ </RteComponents>
+ <Status>Resolved</Status>
+ <VersionMode>Fixed</VersionMode>
+ <IsComponentInAtProject>true</IsComponentInAtProject>
+ </ProjectComponent>
+ </ProjectComponents>
+</Store>
\ No newline at end of file
diff --git a/UsbReceive/UsbReceive/UsbReceive/UsbReceive.cppproj b/UsbReceive/UsbReceive/UsbReceive/UsbReceive.cppproj
new file mode 100644
index 0000000000000000000000000000000000000000..2ba094893f6f3521d288b1916d0b08383a8ece1d
--- /dev/null
+++ b/UsbReceive/UsbReceive/UsbReceive/UsbReceive.cppproj
@@ -0,0 +1,301 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Project DefaultTargets="Build" xmlns="http://schemas.microsoft.com/developer/msbuild/2003" ToolsVersion="14.0">
+ <PropertyGroup>
+ <SchemaVersion>2.0</SchemaVersion>
+ <ProjectVersion>7.0</ProjectVersion>
+ <ToolchainName>com.Atmel.ARMGCC.CPP</ToolchainName>
+ <ProjectGuid>dce6c7e3-ee26-4d79-826b-08594b9ad897</ProjectGuid>
+ <avrdevice>ATSAMD21G18A</avrdevice>
+ <avrdeviceseries>none</avrdeviceseries>
+ <OutputType>Executable</OutputType>
+ <Language>CPP</Language>
+ <OutputFileName>$(MSBuildProjectName)</OutputFileName>
+ <ArduinoProjectType>Sketch</ArduinoProjectType>
+ <OutputFileExtension>.elf</OutputFileExtension>
+ <OutputDirectory>$(MSBuildProjectDirectory)\$(Configuration)</OutputDirectory>
+ <Name>UsbReceive</Name>
+ <RootNamespace>UsbReceive</RootNamespace>
+ <ArduinoIdeDir>C:\Program Files (x86)\Arduino</ArduinoIdeDir>
+ <ToolchainFlavour>Native</ToolchainFlavour>
+ <KeepTimersRunning>true</KeepTimersRunning>
+ <OverrideVtor>false</OverrideVtor>
+ <CacheFlash>true</CacheFlash>
+ <ProgFlashFromRam>true</ProgFlashFromRam>
+ <RamSnippetAddress>0x20000000</RamSnippetAddress>
+ <UncachedRange />
+ <preserveEEPROM>true</preserveEEPROM>
+ <OverrideVtorValue>exception_table</OverrideVtorValue>
+ <BootSegment>2</BootSegment>
+ <eraseonlaunchrule>1</eraseonlaunchrule>
+ <AssemblyName>UsbReceive</AssemblyName>
+ <ResetRule>0</ResetRule>
+ <EraseKey />
+ <AsfFrameworkConfig>
+ <framework-data xmlns="">
+ <options />
+ <configurations />
+ <files />
+ <documentation help="" />
+ <offline-documentation help="" />
+ <dependencies>
+ <content-extension eid="atmel.asf" uuidref="Atmel.ASF" version="3.49.1" />
+ </dependencies>
+</framework-data>
+ </AsfFrameworkConfig>
+ <avrtool>com.atmel.avrdbg.tool.atmelice</avrtool>
+ <avrtoolserialnumber>J41800033620</avrtoolserialnumber>
+ <avrdeviceexpectedsignature>0x10010305</avrdeviceexpectedsignature>
+ <avrtoolinterface>SWD</avrtoolinterface>
+ <com_atmel_avrdbg_tool_atmelice>
+ <ToolOptions>
+ <InterfaceProperties>
+ <SwdClock>2000000</SwdClock>
+ </InterfaceProperties>
+ <InterfaceName>SWD</InterfaceName>
+ </ToolOptions>
+ <ToolType>com.atmel.avrdbg.tool.atmelice</ToolType>
+ <ToolNumber>J41800033620</ToolNumber>
+ <ToolName>Atmel-ICE</ToolName>
+ </com_atmel_avrdbg_tool_atmelice>
+ <avrtoolinterfaceclock>2000000</avrtoolinterfaceclock>
+ </PropertyGroup>
+ <PropertyGroup Condition=" '$(Configuration)' == 'Release' ">
+ <ToolchainSettings>
+ <ArmGccCpp>
+ <armgcc.common.outputfiles.hex>True</armgcc.common.outputfiles.hex>
+ <armgcc.common.outputfiles.lss>True</armgcc.common.outputfiles.lss>
+ <armgcc.common.outputfiles.eep>True</armgcc.common.outputfiles.eep>
+ <armgcc.common.outputfiles.bin>True</armgcc.common.outputfiles.bin>
+ <armgcc.common.outputfiles.srec>True</armgcc.common.outputfiles.srec>
+ <armgcc.compiler.symbols.DefSymbols>
+ <ListValues>
+ <Value>NDEBUG</Value>
+ <Value>F_CPU=48000000L</Value>
+ <Value>ARDUINO=108019</Value>
+ <Value>ARDUINO_SAMD_ZERO</Value>
+ <Value>ARDUINO_ARCH_SAMD</Value>
+ <Value>USB_VID=0x03EB</Value>
+ <Value>USB_PID=0x8009</Value>
+ <Value>USB_PRODUCT="\"TinyZero\""</Value>
+ <Value>USB_MANUFACTURER="\"TinyCircuits\""</Value>
+ <Value>USBCON</Value>
+ <Value>SAMD_SERIES</Value>
+ </ListValues>
+ </armgcc.compiler.symbols.DefSymbols>
+ <armgcc.compiler.directories.IncludePaths>
+ <ListValues>
+ <Value>%24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\</Value>
+ <Value>%24(ProjectDir)\..\ArduinoCore\include\core</Value>
+ <Value>%24(ProjectDir)\..\ArduinoCore\include\variants</Value>
+ <Value>%24(ProjectDir)\..\ArduinoCore\include\core\avr</Value>
+ <Value>%24(ProjectDir)\..\ArduinoCore\include\core\USB</Value>
+ <Value>%24(ProjectDir)\..\ArduinoCore\include\libraries\wire</Value>
+ </ListValues>
+ </armgcc.compiler.directories.IncludePaths>
+ <armgcc.compiler.optimization.level>Optimize for size (-Os)</armgcc.compiler.optimization.level>
+ <armgcc.compiler.optimization.OtherFlags>-fno-threadsafe-statics -fno-exceptions</armgcc.compiler.optimization.OtherFlags>
+ <armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>
+ <armgcc.compiler.optimization.PrepareDataForGarbageCollection>True</armgcc.compiler.optimization.PrepareDataForGarbageCollection>
+ <armgcc.compiler.optimization.EnableLongCalls>False</armgcc.compiler.optimization.EnableLongCalls>
+ <armgcc.compiler.optimization.DebugLevel>Maximum (-g3)</armgcc.compiler.optimization.DebugLevel>
+ <armgcc.compiler.warnings.InhibitAllWarnings>True</armgcc.compiler.warnings.InhibitAllWarnings>
+ <armgcc.compiler.miscellaneous.OtherFlags>-std=gnu11 --param max-inline-insns-single=500 -nostdlib</armgcc.compiler.miscellaneous.OtherFlags>
+ <armgcccpp.compiler.symbols.DefSymbols>
+ <ListValues>
+ <Value>NDEBUG</Value>
+ <Value>F_CPU=48000000L</Value>
+ <Value>ARDUINO=108019</Value>
+ <Value>ARDUINO_SAMD_ZERO</Value>
+ <Value>ARDUINO_ARCH_SAMD</Value>
+ <Value>USB_VID=0x03EB</Value>
+ <Value>USB_PID=0x8009</Value>
+ <Value>USB_PRODUCT="\"TinyZero\""</Value>
+ <Value>USB_MANUFACTURER="\"TinyCircuits\""</Value>
+ <Value>USBCON</Value>
+ <Value>SAMD_SERIES</Value>
+ </ListValues>
+ </armgcccpp.compiler.symbols.DefSymbols>
+ <armgcccpp.compiler.directories.IncludePaths>
+ <ListValues>
+ <Value>%24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\</Value>
+ <Value>%24(ProjectDir)\..\ArduinoCore\include\core</Value>
+ <Value>%24(ProjectDir)\..\ArduinoCore\include\variants</Value>
+ <Value>%24(ProjectDir)\..\ArduinoCore\include\core\avr</Value>
+ <Value>%24(ProjectDir)\..\ArduinoCore\include\core\USB</Value>
+ <Value>%24(ProjectDir)\..\ArduinoCore\include\libraries\wire</Value>
+ </ListValues>
+ </armgcccpp.compiler.directories.IncludePaths>
+ <armgcccpp.compiler.optimization.level>Optimize for size (-Os)</armgcccpp.compiler.optimization.level>
+ <armgcccpp.compiler.optimization.OtherFlags>-fno-threadsafe-statics -fno-exceptions</armgcccpp.compiler.optimization.OtherFlags>
+ <armgcccpp.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcccpp.compiler.optimization.PrepareFunctionsForGarbageCollection>
+ <armgcccpp.compiler.optimization.PrepareDataForGarbageCollection>True</armgcccpp.compiler.optimization.PrepareDataForGarbageCollection>
+ <armgcccpp.compiler.optimization.EnableLongCalls>False</armgcccpp.compiler.optimization.EnableLongCalls>
+ <armgcccpp.compiler.optimization.DebugLevel>Maximum (-g3)</armgcccpp.compiler.optimization.DebugLevel>
+ <armgcccpp.compiler.warnings.InhibitAllWarnings>True</armgcccpp.compiler.warnings.InhibitAllWarnings>
+ <armgcccpp.compiler.miscellaneous.OtherFlags>-std=gnu++11 --param max-inline-insns-single=500 -nostdlib</armgcccpp.compiler.miscellaneous.OtherFlags>
+ <armgcccpp.linker.general.UseNewlibNano>True</armgcccpp.linker.general.UseNewlibNano>
+ <armgcccpp.linker.general.AdditionalSpecs>Use syscall stubs (--specs=nosys.specs)</armgcccpp.linker.general.AdditionalSpecs>
+ <armgcccpp.linker.libraries.Libraries>
+ <ListValues>
+ <Value>libm</Value>
+ </ListValues>
+ </armgcccpp.linker.libraries.Libraries>
+ <armgcccpp.linker.libraries.LibrarySearchPaths>
+ <ListValues>
+ <Value>..\linker_scripts\linker_scripts\gcc</Value>
+ </ListValues>
+ </armgcccpp.linker.libraries.LibrarySearchPaths>
+ <armgcccpp.linker.optimization.GarbageCollectUnusedSections>True</armgcccpp.linker.optimization.GarbageCollectUnusedSections>
+ <armgcccpp.linker.miscellaneous.LinkerFlags>-Tflash_without_bootloader.ld -Wl,--cref -Os -Wl,--check-sections -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align</armgcccpp.linker.miscellaneous.LinkerFlags>
+ <armgcccpp.assembler.general.IncludePaths>
+ <ListValues>
+ <Value>%24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\</Value>
+ </ListValues>
+ </armgcccpp.assembler.general.IncludePaths>
+ <armgcccpp.assembler.debugging.DebugLevel>Default (-Wa,-g)</armgcccpp.assembler.debugging.DebugLevel>
+ <armgcccpp.preprocessingassembler.general.IncludePaths>
+ <ListValues>
+ <Value>%24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\</Value>
+ </ListValues>
+ </armgcccpp.preprocessingassembler.general.IncludePaths>
+ </ArmGccCpp>
+ </ToolchainSettings>
+ </PropertyGroup>
+ <PropertyGroup Condition=" '$(Configuration)' == 'Debug' ">
+ <ToolchainSettings>
+ <ArmGccCpp>
+ <armgcc.common.outputfiles.hex>True</armgcc.common.outputfiles.hex>
+ <armgcc.common.outputfiles.lss>True</armgcc.common.outputfiles.lss>
+ <armgcc.common.outputfiles.eep>True</armgcc.common.outputfiles.eep>
+ <armgcc.common.outputfiles.bin>True</armgcc.common.outputfiles.bin>
+ <armgcc.common.outputfiles.srec>True</armgcc.common.outputfiles.srec>
+ <armgcc.compiler.symbols.DefSymbols>
+ <ListValues>
+ <Value>DEBUG</Value>
+ <Value>F_CPU=48000000L</Value>
+ <Value>ARDUINO=108019</Value>
+ <Value>ARDUINO_SAMD_ZERO</Value>
+ <Value>ARDUINO_ARCH_SAMD</Value>
+ <Value>USB_VID=0x03EB</Value>
+ <Value>USB_PID=0x8009</Value>
+ <Value>USB_PRODUCT="\"TinyZero\""</Value>
+ <Value>USB_MANUFACTURER="\"TinyCircuits\""</Value>
+ <Value>USBCON</Value>
+ <Value>SAMD_SERIES</Value>
+ </ListValues>
+ </armgcc.compiler.symbols.DefSymbols>
+ <armgcc.compiler.directories.IncludePaths>
+ <ListValues>
+ <Value>%24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\</Value>
+ <Value>%24(ProjectDir)\..\ArduinoCore\include\core</Value>
+ <Value>%24(ProjectDir)\..\ArduinoCore\include\variants</Value>
+ <Value>%24(ProjectDir)\..\ArduinoCore\include\core\avr</Value>
+ <Value>%24(ProjectDir)\..\ArduinoCore\include\core\USB</Value>
+ <Value>%24(ProjectDir)\..\ArduinoCore\include\libraries\wire</Value>
+ </ListValues>
+ </armgcc.compiler.directories.IncludePaths>
+ <armgcc.compiler.optimization.level>Optimize for size (-Os)</armgcc.compiler.optimization.level>
+ <armgcc.compiler.optimization.OtherFlags>-fno-threadsafe-statics -fno-exceptions</armgcc.compiler.optimization.OtherFlags>
+ <armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection>
+ <armgcc.compiler.optimization.PrepareDataForGarbageCollection>True</armgcc.compiler.optimization.PrepareDataForGarbageCollection>
+ <armgcc.compiler.optimization.EnableLongCalls>False</armgcc.compiler.optimization.EnableLongCalls>
+ <armgcc.compiler.optimization.DebugLevel>Maximum (-g3)</armgcc.compiler.optimization.DebugLevel>
+ <armgcc.compiler.warnings.InhibitAllWarnings>True</armgcc.compiler.warnings.InhibitAllWarnings>
+ <armgcc.compiler.miscellaneous.OtherFlags>-std=gnu11 --param max-inline-insns-single=500 -nostdlib</armgcc.compiler.miscellaneous.OtherFlags>
+ <armgcccpp.compiler.symbols.DefSymbols>
+ <ListValues>
+ <Value>DEBUG</Value>
+ <Value>F_CPU=48000000L</Value>
+ <Value>ARDUINO=108019</Value>
+ <Value>ARDUINO_SAMD_ZERO</Value>
+ <Value>ARDUINO_ARCH_SAMD</Value>
+ <Value>USB_VID=0x03EB</Value>
+ <Value>USB_PID=0x8009</Value>
+ <Value>USB_PRODUCT="\"TinyZero\""</Value>
+ <Value>USB_MANUFACTURER="\"TinyCircuits\""</Value>
+ <Value>USBCON</Value>
+ <Value>SAMD_SERIES</Value>
+ </ListValues>
+ </armgcccpp.compiler.symbols.DefSymbols>
+ <armgcccpp.compiler.directories.IncludePaths>
+ <ListValues>
+ <Value>%24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\</Value>
+ <Value>%24(ProjectDir)\..\ArduinoCore\include\core</Value>
+ <Value>%24(ProjectDir)\..\ArduinoCore\include\variants</Value>
+ <Value>%24(ProjectDir)\..\ArduinoCore\include\core\avr</Value>
+ <Value>%24(ProjectDir)\..\ArduinoCore\include\core\USB</Value>
+ <Value>%24(ProjectDir)\..\ArduinoCore\include\libraries\wire</Value>
+ </ListValues>
+ </armgcccpp.compiler.directories.IncludePaths>
+ <armgcccpp.compiler.optimization.level>Optimize for size (-Os)</armgcccpp.compiler.optimization.level>
+ <armgcccpp.compiler.optimization.OtherFlags>-fno-threadsafe-statics -fno-exceptions</armgcccpp.compiler.optimization.OtherFlags>
+ <armgcccpp.compiler.optimization.PrepareFunctionsForGarbageCollection>True</armgcccpp.compiler.optimization.PrepareFunctionsForGarbageCollection>
+ <armgcccpp.compiler.optimization.PrepareDataForGarbageCollection>True</armgcccpp.compiler.optimization.PrepareDataForGarbageCollection>
+ <armgcccpp.compiler.optimization.EnableLongCalls>False</armgcccpp.compiler.optimization.EnableLongCalls>
+ <armgcccpp.compiler.optimization.DebugLevel>Maximum (-g3)</armgcccpp.compiler.optimization.DebugLevel>
+ <armgcccpp.compiler.warnings.InhibitAllWarnings>True</armgcccpp.compiler.warnings.InhibitAllWarnings>
+ <armgcccpp.compiler.miscellaneous.OtherFlags>-std=gnu++11 --param max-inline-insns-single=500 -nostdlib</armgcccpp.compiler.miscellaneous.OtherFlags>
+ <armgcccpp.linker.general.UseNewlibNano>True</armgcccpp.linker.general.UseNewlibNano>
+ <armgcccpp.linker.general.AdditionalSpecs>Use syscall stubs (--specs=nosys.specs)</armgcccpp.linker.general.AdditionalSpecs>
+ <armgcccpp.linker.libraries.Libraries>
+ <ListValues>
+ <Value>libm</Value>
+ </ListValues>
+ </armgcccpp.linker.libraries.Libraries>
+ <armgcccpp.linker.libraries.LibrarySearchPaths>
+ <ListValues>
+ <Value>..\linker_scripts\linker_scripts\gcc</Value>
+ </ListValues>
+ </armgcccpp.linker.libraries.LibrarySearchPaths>
+ <armgcccpp.linker.optimization.GarbageCollectUnusedSections>True</armgcccpp.linker.optimization.GarbageCollectUnusedSections>
+ <armgcccpp.linker.miscellaneous.LinkerFlags>-Tflash_without_bootloader.ld -Wl,--cref -Os -Wl,--check-sections -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align</armgcccpp.linker.miscellaneous.LinkerFlags>
+ <armgcccpp.assembler.general.IncludePaths>
+ <ListValues>
+ <Value>%24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\</Value>
+ </ListValues>
+ </armgcccpp.assembler.general.IncludePaths>
+ <armgcccpp.assembler.debugging.DebugLevel>Default (-Wa,-g)</armgcccpp.assembler.debugging.DebugLevel>
+ <armgcccpp.preprocessingassembler.general.IncludePaths>
+ <ListValues>
+ <Value>%24(PackRepoDir)\arm\CMSIS\5.4.0\CMSIS\Core\Include\</Value>
+ </ListValues>
+ </armgcccpp.preprocessingassembler.general.IncludePaths>
+ <armgcccpp.preprocessingassembler.debugging.DebugLevel>Default (-Wa,-g)</armgcccpp.preprocessingassembler.debugging.DebugLevel>
+ </ArmGccCpp>
+ </ToolchainSettings>
+ </PropertyGroup>
+ <ItemGroup>
+ <Compile Include="sam.h">
+ <SubType>compile</SubType>
+ </Compile>
+ <Compile Include="Sketch.cpp">
+ <SubType>compile</SubType>
+ </Compile>
+ <Content Include="readme.html">
+ </Content>
+ </ItemGroup>
+ <ItemGroup>
+ <ProjectReference Include="..\ArduinoCore\ArduinoCore.cppproj">
+ <Name>ArduinoCore</Name>
+ <Project>3cf7a0ab-b365-4936-958e-a8b73130ccde</Project>
+ <Private>True</Private>
+ </ProjectReference>
+ </ItemGroup>
+ <ItemGroup>
+ <Folder Include="linker_scripts\" />
+ <Folder Include="linker_scripts\linker_scripts\" />
+ <Folder Include="linker_scripts\linker_scripts\gcc\" />
+ </ItemGroup>
+ <ItemGroup>
+ <None Include="linker_scripts\linker_scripts\gcc\flash_without_bootloader.ld">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="linker_scripts\linker_scripts\gcc\flash_with_bootloader.ld">
+ <SubType>compile</SubType>
+ </None>
+ <None Include="linker_scripts\linker_scripts\gcc\link_for_menu.ld">
+ <SubType>compile</SubType>
+ </None>
+ </ItemGroup>
+ <Import Project="$(AVRSTUDIO_EXE_PATH)\\Vs\\Compiler.targets" />
+</Project>
\ No newline at end of file
diff --git a/UsbReceive/UsbReceive/UsbReceive/linker_scripts/linker_scripts/gcc/flash_with_bootloader.ld b/UsbReceive/UsbReceive/UsbReceive/linker_scripts/linker_scripts/gcc/flash_with_bootloader.ld
new file mode 100644
index 0000000000000000000000000000000000000000..3579464556c6779ff268a550386eb0a9bd5f3ea1
--- /dev/null
+++ b/UsbReceive/UsbReceive/UsbReceive/linker_scripts/linker_scripts/gcc/flash_with_bootloader.ld
@@ -0,0 +1,216 @@
+/*
+ Copyright (c) 2014-2015 Arduino LLC. All right reserved.
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ See the GNU Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+/* Linker script to configure memory regions.
+ * Need modifying for a specific board.
+ * FLASH.ORIGIN: starting address of flash
+ * FLASH.LENGTH: length of flash
+ * RAM.ORIGIN: starting address of RAM bank 0
+ * RAM.LENGTH: length of RAM bank 0
+ */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x00000000+0x2000, LENGTH = 0x00040000-0x2000 /* First 8KB used by bootloader */
+ RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __copy_table_start__
+ * __copy_table_end__
+ * __zero_table_start__
+ * __zero_table_end__
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ __text_start__ = .;
+
+ KEEP(*(.sketch_boot))
+
+ . = ALIGN(0x2000);
+ KEEP(*(.isr_vector))
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ /* To copy multiple ROM to RAM sections,
+ * uncomment .copy.table section and,
+ * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+ /*
+ .copy.table :
+ {
+ . = ALIGN(4);
+ __copy_table_start__ = .;
+ LONG (__etext)
+ LONG (__data_start__)
+ LONG (__data_end__ - __data_start__)
+ LONG (__etext2)
+ LONG (__data2_start__)
+ LONG (__data2_end__ - __data2_start__)
+ __copy_table_end__ = .;
+ } > FLASH
+ */
+
+ /* To clear multiple BSS sections,
+ * uncomment .zero.table section and,
+ * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+ /*
+ .zero.table :
+ {
+ . = ALIGN(4);
+ __zero_table_start__ = .;
+ LONG (__bss_start__)
+ LONG (__bss_end__ - __bss_start__)
+ LONG (__bss2_start__)
+ LONG (__bss2_end__ - __bss2_start__)
+ __zero_table_end__ = .;
+ } > FLASH
+ */
+
+ __etext = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(16);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > RAM
+
+ .heap (COPY):
+ {
+ __end__ = .;
+ PROVIDE(end = .);
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ *(.stack*)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ __ram_end__ = ORIGIN(RAM) + LENGTH(RAM) -1 ;
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/UsbReceive/UsbReceive/UsbReceive/linker_scripts/linker_scripts/gcc/flash_without_bootloader.ld b/UsbReceive/UsbReceive/UsbReceive/linker_scripts/linker_scripts/gcc/flash_without_bootloader.ld
new file mode 100644
index 0000000000000000000000000000000000000000..ebeeee37f4ee0439dcc8efe941642eb8fd24f5a7
--- /dev/null
+++ b/UsbReceive/UsbReceive/UsbReceive/linker_scripts/linker_scripts/gcc/flash_without_bootloader.ld
@@ -0,0 +1,214 @@
+/*
+ Copyright (c) 2014-2015 Arduino LLC. All right reserved.
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ See the GNU Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+/* Linker script to configure memory regions.
+ * Need modifying for a specific board.
+ * FLASH.ORIGIN: starting address of flash
+ * FLASH.LENGTH: length of flash
+ * RAM.ORIGIN: starting address of RAM bank 0
+ * RAM.LENGTH: length of RAM bank 0
+ */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000
+ RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __copy_table_start__
+ * __copy_table_end__
+ * __zero_table_start__
+ * __zero_table_end__
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * __ram_end__
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ __text_start__ = .;
+
+ KEEP(*(.isr_vector))
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ /* To copy multiple ROM to RAM sections,
+ * uncomment .copy.table section and,
+ * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+ /*
+ .copy.table :
+ {
+ . = ALIGN(4);
+ __copy_table_start__ = .;
+ LONG (__etext)
+ LONG (__data_start__)
+ LONG (__data_end__ - __data_start__)
+ LONG (__etext2)
+ LONG (__data2_start__)
+ LONG (__data2_end__ - __data2_start__)
+ __copy_table_end__ = .;
+ } > FLASH
+ */
+
+ /* To clear multiple BSS sections,
+ * uncomment .zero.table section and,
+ * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+ /*
+ .zero.table :
+ {
+ . = ALIGN(4);
+ __zero_table_start__ = .;
+ LONG (__bss_start__)
+ LONG (__bss_end__ - __bss_start__)
+ LONG (__bss2_start__)
+ LONG (__bss2_end__ - __bss2_start__)
+ __zero_table_end__ = .;
+ } > FLASH
+ */
+
+ __etext = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(16);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > RAM
+
+ .heap (COPY):
+ {
+ __end__ = .;
+ PROVIDE(end = .);
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ *(.stack*)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM) ;
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ __ram_end__ = ORIGIN(RAM) + LENGTH(RAM) -1 ;
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/UsbReceive/UsbReceive/UsbReceive/linker_scripts/linker_scripts/gcc/link_for_menu.ld b/UsbReceive/UsbReceive/UsbReceive/linker_scripts/linker_scripts/gcc/link_for_menu.ld
new file mode 100644
index 0000000000000000000000000000000000000000..c634b42a16ac0e5452823f75554d8e9a0a9a6ab5
--- /dev/null
+++ b/UsbReceive/UsbReceive/UsbReceive/linker_scripts/linker_scripts/gcc/link_for_menu.ld
@@ -0,0 +1,216 @@
+/*
+ Copyright (c) 2014-2015 Arduino LLC. All right reserved.
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ See the GNU Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+/* Linker script to configure memory regions.
+ * Need modifying for a specific board.
+ * FLASH.ORIGIN: starting address of flash
+ * FLASH.LENGTH: length of flash
+ * RAM.ORIGIN: starting address of RAM bank 0
+ * RAM.LENGTH: length of RAM bank 0
+ */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x00000000+0x10000, LENGTH = 0x00040000-0x10000 /* First 64KB for bootloader/menu */
+ RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __copy_table_start__
+ * __copy_table_end__
+ * __zero_table_start__
+ * __zero_table_end__
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ __text_start__ = .;
+
+ KEEP(*(.sketch_boot))
+
+ . = ALIGN(0x2000);
+ KEEP(*(.isr_vector))
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ /* To copy multiple ROM to RAM sections,
+ * uncomment .copy.table section and,
+ * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+ /*
+ .copy.table :
+ {
+ . = ALIGN(4);
+ __copy_table_start__ = .;
+ LONG (__etext)
+ LONG (__data_start__)
+ LONG (__data_end__ - __data_start__)
+ LONG (__etext2)
+ LONG (__data2_start__)
+ LONG (__data2_end__ - __data2_start__)
+ __copy_table_end__ = .;
+ } > FLASH
+ */
+
+ /* To clear multiple BSS sections,
+ * uncomment .zero.table section and,
+ * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+ /*
+ .zero.table :
+ {
+ . = ALIGN(4);
+ __zero_table_start__ = .;
+ LONG (__bss_start__)
+ LONG (__bss_end__ - __bss_start__)
+ LONG (__bss2_start__)
+ LONG (__bss2_end__ - __bss2_start__)
+ __zero_table_end__ = .;
+ } > FLASH
+ */
+
+ __etext = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(16);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > RAM
+
+ .heap (COPY):
+ {
+ __end__ = .;
+ PROVIDE(end = .);
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ *(.stack*)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ __ram_end__ = ORIGIN(RAM) + LENGTH(RAM) -1 ;
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/UsbReceive/UsbReceive/UsbReceive/sam.h b/UsbReceive/UsbReceive/UsbReceive/sam.h
new file mode 100644
index 0000000000000000000000000000000000000000..80a1c486cda80fa9ddd3dc896e11824ae8e9a006
--- /dev/null
+++ b/UsbReceive/UsbReceive/UsbReceive/sam.h
@@ -0,0 +1,567 @@
+/* ----------------------------------------------------------------------------
+ * SAM Software Package License
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2015, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following condition is met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+#ifndef _SAM_INCLUDED_
+#define _SAM_INCLUDED_
+
+#define part_is_defined(part) (defined(__ ## part ## __))
+
+/*
+ * ----------------------------------------------------------------------------
+ * SAMG family
+ * ----------------------------------------------------------------------------
+ */
+
+/* SAMG55 series */
+#define SAMG55J1 ( \
+ part_is_defined( SAMG55J19 ) )
+
+#define SAMG55G1 ( \
+ part_is_defined( SAMG55G19 ) )
+
+/* Entire SAMG55 series */
+#define SAMG55_SERIES (SAMG55J1 || SAMG55G1)
+
+/* SAMG54 series */
+#define SAMG54N1 ( \
+ part_is_defined( SAMG54N19 ) )
+
+#define SAMG54J1 ( \
+ part_is_defined( SAMG54J19 ) )
+
+#define SAMG54G1 ( \
+ part_is_defined( SAMG54G19 ) )
+
+/* Entire SAMG54 series */
+#define SAMG54_SERIES (SAMG54N1 || SAMG54J1 || SAMG54G1)
+
+
+
+/* Entire SAMG family */
+#define SAMG_SERIES ( SAMG55_SERIES || SAMG54_SERIES)
+
+/*
+ * ----------------------------------------------------------------------------
+ * SAMD family
+ * ----------------------------------------------------------------------------
+ */
+
+/* SAMD10 series */
+#define SAMD10C14 ( \
+ part_is_defined( SAMD10C14A ) )
+
+#define SAMD10C13 ( \
+ part_is_defined( SAMD10C13A ) )
+
+#define SAMD10D13A ( \
+ part_is_defined( SAMD10D13AS ) || \
+ part_is_defined( SAMD10D13AM ) )
+
+#define SAMD10D14A ( \
+ part_is_defined( SAMD10D14AS ) || \
+ part_is_defined( SAMD10D14AM ) )
+
+/* Entire SAMD10 series */
+#define SAMD10_SERIES (SAMD10C14 || SAMD10C13 || SAMD10D13A || SAMD10D14A)
+
+/* SAMD11 series */
+#define SAMD11C14 ( \
+ part_is_defined( SAMD11C14A ) )
+
+#define SAMD11D14A ( \
+ part_is_defined( SAMD11D14AS ) || \
+ part_is_defined( SAMD11D14AM ) )
+
+/* Entire SAMD11 series */
+#define SAMD11_SERIES (SAMD11C14 || SAMD11D14A)
+
+/* SAMD21 series */
+#define SAMD21J17 ( \
+ part_is_defined( SAMD21J17A ) )
+
+#define SAMD21G17A ( \
+ part_is_defined( SAMD21G17AU ) )
+
+#define SAMD21E15B ( \
+ part_is_defined( SAMD21E15BU ) )
+
+#define SAMD21E15 ( \
+ part_is_defined( SAMD21E15A ) || \
+ part_is_defined( SAMD21E15B ) || \
+ part_is_defined( SAMD21E15L ) )
+
+#define SAMD21E16 ( \
+ part_is_defined( SAMD21E16A ) || \
+ part_is_defined( SAMD21E16B ) || \
+ part_is_defined( SAMD21E16L ) )
+
+#define SAMD21E17 ( \
+ part_is_defined( SAMD21E17A ) )
+
+#define SAMD21E18 ( \
+ part_is_defined( SAMD21E18A ) )
+
+#define SAMD21E16B ( \
+ part_is_defined( SAMD21E16BU ) )
+
+#define SAMD21J15 ( \
+ part_is_defined( SAMD21J15A ) || \
+ part_is_defined( SAMD21J15B ) )
+
+#define SAMD21J16 ( \
+ part_is_defined( SAMD21J16A ) || \
+ part_is_defined( SAMD21J16B ) )
+
+#define SAMD21G16 ( \
+ part_is_defined( SAMD21G16A ) || \
+ part_is_defined( SAMD21G16B ) )
+
+#define SAMD21G17 ( \
+ part_is_defined( SAMD21G17A ) )
+
+#define SAMD21G18A ( \
+ part_is_defined( SAMD21G18AU ) )
+
+#define SAMD21G15 ( \
+ part_is_defined( SAMD21G15A ) || \
+ part_is_defined( SAMD21G15B ) )
+
+#define SAMD21G18 ( \
+ part_is_defined( SAMD21G18A ) )
+
+#define SAMD21J18 ( \
+ part_is_defined( SAMD21J18A ) )
+
+#define SAMD51G18A ( \
+ part_is_defined( SAMD51G18A ) )
+
+#define SAMD51G19A ( \
+ part_is_defined( SAMD51G19A ) )
+
+#define SAMD51J19A ( \
+ part_is_defined( SAMD51J19A ) )
+
+#define SAMD51J20A ( \
+ part_is_defined( SAMD51J20A ) )
+
+#define SAMD51N19A ( \
+ part_is_defined( SAMD51N19A ) )
+
+#define SAMD51N20A ( \
+ part_is_defined( SAMD51N20A ) )
+
+#define SAMD51P19A ( \
+ part_is_defined( SAMD51P19A ) )
+
+#define SAMD51P20A ( \
+ part_is_defined( SAMD51P20A ) )
+
+
+/* Entire SAMD21 series */
+#define SAMD21_SERIES (SAMD21J17 || SAMD21G17A || SAMD21E15B || SAMD21E15 || SAMD21E16 || SAMD21E17 || SAMD21E18 || SAMD21E16B || SAMD21J15 || SAMD21J16 || SAMD21G16 || SAMD21G17 || SAMD21G18A || SAMD21G15 || SAMD21G18 || SAMD21J18)
+
+/* Entire SAMD51 series */
+#define SAMD51_SERIES (SAMD51G18A || SAMD51G19A || SAMD51J19A || SAMD51J20A || SAMD51N19A || SAMD51N20A || SAMD51P19A || SAMD51P20A)
+
+/* Entire SAMD family */
+#define SAMD_SERIES (SAMD10_SERIES || SAMD11_SERIES || SAMD21_SERIES || SAMD51_SERIES)
+
+/*
+ * ----------------------------------------------------------------------------
+ * SAML family
+ * ----------------------------------------------------------------------------
+ */
+
+/* SAML21 series */
+#define SAML21E18A ( \
+ part_is_defined( SAML21E18A ) )
+#define SAML21G18A ( \
+ part_is_defined( SAML21G18A ) )
+#define SAML21J18A ( \
+ part_is_defined( SAML21J18A ) )
+
+#define SAML21E15B ( \
+ part_is_defined( SAML21E15B ) )
+#define SAML21E16B ( \
+ part_is_defined( SAML21E16B ) )
+#define SAML21E17B ( \
+ part_is_defined( SAML21E17B ) )
+#define SAML21E18B ( \
+ part_is_defined( SAML21E18B ) )
+#define SAML21G16B ( \
+ part_is_defined( SAML21G16B ) )
+#define SAML21G17B ( \
+ part_is_defined( SAML21G17B ) )
+#define SAML21G18B ( \
+ part_is_defined( SAML21G18B ) )
+#define SAML21J16B ( \
+ part_is_defined( SAML21J16B ) )
+#define SAML21J17B ( \
+ part_is_defined( SAML21J17B ) )
+#define SAML21J18B ( \
+ part_is_defined( SAML21J18B ) )
+#define SAML21J18BU ( \
+ part_is_defined( SAML21J18BU ) )
+
+/* Entire SAML21A series */
+#define SAML21_SERIES (SAML21E18A || SAML21G18A || SAML21J18A)
+
+/* Entire SAML21B series */
+#define SAML21B_SERIES (SAML21E15B || SAML21E16B || SAML21E17B || SAML21E18B || SAML21G16B || SAML21G17B || SAML21G18B || SAML21J16B || SAML21J17B || SAML21J18B || SAML21J18BU)
+
+/* Entire SAMD family */
+#define SAML_SERIES (SAML21A_SERIES || SAML21B_SERIES)
+
+/*
+ * ----------------------------------------------------------------------------
+ * SAMC family
+ * ----------------------------------------------------------------------------
+ */
+
+/* SAMC21 series */
+#define SAMC21E15A ( \
+ part_is_defined( SAMC21E15A ) )
+#define SAMC21E16A ( \
+ part_is_defined( SAMC21E16A ) )
+#define SAMC21E17A ( \
+ part_is_defined( SAMC21E17A ) )
+#define SAMC21E18A ( \
+ part_is_defined( SAMC21E18A ) )
+#define SAMC21G15A ( \
+ part_is_defined( SAMC21G15A ) )
+#define SAMC21G16A ( \
+ part_is_defined( SAMC21G16A ) )
+#define SAMC21G17A ( \
+ part_is_defined( SAMC21G17A ) )
+#define SAMC21G18A ( \
+ part_is_defined( SAMC21G18A ) )
+#define SAMC21J15A ( \
+ part_is_defined( SAMC21J15A ) )
+#define SAMC21J16A ( \
+ part_is_defined( SAMC21J16A ) )
+#define SAMC21J17A ( \
+ part_is_defined( SAMC21J17A ) )
+#define SAMC21J18A ( \
+ part_is_defined( SAMC21J18A ) )
+#define SAMC21J18AU ( \
+ part_is_defined( SAMC21J18AU ) )
+
+
+/* Entire SAMC21 series */
+#define SAMC21_SERIES (SAMC21E15A || SAMC21E16A || SAMC21E17A || SAMC21E18A || SAMC21G15A || SAMC21G16A || SAMC21G17A || SAMC21G18A || SAMC21J15A || SAMC21J16A || SAMC21J17A || SAMC21J18A || SAMC21J18AU)
+
+/* Entire SAMC family */
+#define SAMC_SERIES SAMC21_SERIES
+
+
+/*
+ * ----------------------------------------------------------------------------
+ * SAMS family
+ * ----------------------------------------------------------------------------
+ */
+
+/* SAMS70 series */
+#define SAMS70Q2 ( \
+ part_is_defined( SAMS70Q20 ) || \
+ part_is_defined( SAMS70Q21 ) )
+
+#define SAMS70Q1 ( \
+ part_is_defined( SAMS70Q19 ) )
+
+#define SAMS70N2 ( \
+ part_is_defined( SAMS70N20 ) || \
+ part_is_defined( SAMS70N21 ) )
+
+#define SAMS70N1 ( \
+ part_is_defined( SAMS70N19 ) )
+
+#define SAMS70J2 ( \
+ part_is_defined( SAMS70J20 ) || \
+ part_is_defined( SAMS70J21 ) )
+
+#define SAMS70J1 ( \
+ part_is_defined( SAMS70J19 ) )
+
+/* Entire SAMS70 series */
+#define SAMS70_SERIES (SAMS70Q2 || SAMS70Q1 || SAMS70N2 || SAMS70N1 || SAMS70J2 || SAMS70J1)
+
+/* Entire SAMS family */
+#define SAMS_SERIES (SAMS70_SERIES)
+
+/*
+ * ----------------------------------------------------------------------------
+ * SAME family
+ * ----------------------------------------------------------------------------
+ */
+
+/* SAME70 series */
+#define SAME70N1 ( \
+ part_is_defined( SAME70N19 ) )
+
+#define SAME70N2 ( \
+ part_is_defined( SAME70N20 ) || \
+ part_is_defined( SAME70N21 ) )
+
+#define SAME70J1 ( \
+ part_is_defined( SAME70J19 ) )
+
+#define SAME70J2 ( \
+ part_is_defined( SAME70J20 ) || \
+ part_is_defined( SAME70J21 ) )
+
+#define SAME70Q1 ( \
+ part_is_defined( SAME70Q19 ) )
+
+#define SAME70Q2 ( \
+ part_is_defined( SAME70Q20 ) || \
+ part_is_defined( SAME70Q21 ) )
+
+/* Entire SAME70 series */
+#define SAME70_SERIES (SAME70N1 || SAME70N2 || SAME70J1 || SAME70J2 || SAME70Q1 || SAME70Q2)
+
+/* Entire SAME family */
+#define SAME_SERIES (SAME70_SERIES)
+
+/*
+ * ----------------------------------------------------------------------------
+ * SAM3 family
+ * ----------------------------------------------------------------------------
+ */
+
+/* SAM3U series */
+#define SAM3U1 ( \
+ part_is_defined( SAM3U1E ) || \
+ part_is_defined( SAM3U1C ) )
+
+#define SAM3U2 ( \
+ part_is_defined( SAM3U2E ) || \
+ part_is_defined( SAM3U2C ) )
+
+#define SAM3U4 ( \
+ part_is_defined( SAM3U4E ) || \
+ part_is_defined( SAM3U4C ) )
+
+/* Entire SAM3U series */
+#define SAM3U_SERIES (SAM3U1 || SAM3U2 || SAM3U4)
+
+/* SAM3XA series */
+#define SAM3A4 ( \
+ part_is_defined( SAM3A4C ) )
+
+#define SAM3X4 ( \
+ part_is_defined( SAM3X4C ) || \
+ part_is_defined( SAM3X4E ) )
+
+#define SAM3A8 ( \
+ part_is_defined( SAM3A8C ) )
+
+#define SAM3X8 ( \
+ part_is_defined( SAM3X8C ) || \
+ part_is_defined( SAM3X8E ) || \
+ part_is_defined( SAM3X8H ) )
+
+/* Entire SAM3XA series */
+#define SAM3XA_SERIES (SAM3A4 || SAM3X4 || SAM3A8 || SAM3X8)
+
+/* Entire SAM3 family */
+#define SAM3_SERIES (SAM3U_SERIES || SAM3XA_SERIES)
+
+/*
+ * ----------------------------------------------------------------------------
+ * SAMR family
+ * ----------------------------------------------------------------------------
+ */
+
+/* SAMR21 series */
+#define SAMR21E16 ( \
+ part_is_defined( SAMR21E16A ) )
+
+#define SAMR21E18 ( \
+ part_is_defined( SAMR21E18A ) )
+
+#define SAMR21G16 ( \
+ part_is_defined( SAMR21G16A ) )
+
+#define SAMR21G17 ( \
+ part_is_defined( SAMR21G17A ) )
+
+#define SAMR21G18 ( \
+ part_is_defined( SAMR21G18A ) )
+
+#define SAMR21E17 ( \
+ part_is_defined( SAMR21E17A ) )
+
+/* Entire SAMR21 series */
+#define SAMR21_SERIES (SAMR21E16 || SAMR21E18 || SAMR21G16 || SAMR21G17 || SAMR21G18 || SAMR21E17)
+
+/* Entire SAMR family */
+#define SAMR_SERIES (SAMR21_SERIES)
+
+/*
+ * ----------------------------------------------------------------------------
+ * SAM4 family
+ * ----------------------------------------------------------------------------
+ */
+
+/* SAM4N series */
+#define SAM4N8 ( \
+ part_is_defined( SAM4N8A ) || \
+ part_is_defined( SAM4N8B ) || \
+ part_is_defined( SAM4N8C ) )
+
+#define SAM4N16 ( \
+ part_is_defined( SAM4N16B ) || \
+ part_is_defined( SAM4N16C ) )
+
+/* Entire SAM4N series */
+#define SAM4N_SERIES (SAM4N8 || SAM4N16)
+
+/* SAM4S series */
+#define SAM4S8 ( \
+ part_is_defined( SAM4S8C ) || \
+ part_is_defined( SAM4S8B ) )
+
+#define SAM4S2 ( \
+ part_is_defined( SAM4S2A ) || \
+ part_is_defined( SAM4S2B ) || \
+ part_is_defined( SAM4S2C ) )
+
+#define SAM4S4 ( \
+ part_is_defined( SAM4S4A ) || \
+ part_is_defined( SAM4S4B ) || \
+ part_is_defined( SAM4S4C ) )
+
+#define SAM4SD16 ( \
+ part_is_defined( SAM4SD16B ) || \
+ part_is_defined( SAM4SD16C ) )
+
+#define SAM4S16 ( \
+ part_is_defined( SAM4S16C ) || \
+ part_is_defined( SAM4S16B ) )
+
+#define SAM4SD32 ( \
+ part_is_defined( SAM4SD32B ) || \
+ part_is_defined( SAM4SD32C ) )
+
+#define SAM4SA16 ( \
+ part_is_defined( SAM4SA16B ) || \
+ part_is_defined( SAM4SA16C ) )
+
+/* Entire SAM4S series */
+#define SAM4S_SERIES (SAM4S8 || SAM4S2 || SAM4S4 || SAM4SD16 || SAM4S16 || SAM4SD32 || SAM4SA16)
+
+/* SAM4E series */
+#define SAM4E16 ( \
+ part_is_defined( SAM4E16E ) || \
+ part_is_defined( SAM4E16C ) )
+
+#define SAM4E8 ( \
+ part_is_defined( SAM4E8E ) || \
+ part_is_defined( SAM4E8C ) )
+
+/* Entire SAM4E series */
+#define SAM4E_SERIES (SAM4E16 || SAM4E8)
+
+/* SAM4C series */
+#define SAM4C4C_ ( \
+ part_is_defined( SAM4C4C_0 ) || \
+ part_is_defined( SAM4C4C_1 ) )
+
+#define SAM4C8C_ ( \
+ part_is_defined( SAM4C8C_0 ) || \
+ part_is_defined( SAM4C8C_1 ) )
+
+#define SAM4C16C_ ( \
+ part_is_defined( SAM4C16C_0 ) || \
+ part_is_defined( SAM4C16C_1 ) )
+
+#define SAM4C32C_ ( \
+ part_is_defined( SAM4C32C_0 ) || \
+ part_is_defined( SAM4C32C_1 ) )
+
+#define SAM4C32E_ ( \
+ part_is_defined( SAM4C32E_0 ) || \
+ part_is_defined( SAM4C32E_1 ) )
+
+/* Entire SAM4C series */
+#define SAM4C_SERIES (SAM4C4C_ || SAM4C8C_ || SAM4C16C_ || SAM4C32C_ || SAM4C32E_)
+
+/* Entire SAM4 family */
+#define SAM4_SERIES (SAM4N_SERIES || SAM4S_SERIES || SAM4E_SERIES || SAM4C_SERIES)
+
+/*
+ * ----------------------------------------------------------------------------
+ * Whole SAM product line
+ * ----------------------------------------------------------------------------
+ */
+
+#define SAM (SAM4_SERIES || SAMR_SERIES || SAM3_SERIES || SAMS_SERIES || SAME_SERIES || SAMD_SERIES || SAML_SERIES || SAMG_SERIES ||SAMC_SERIES)
+
+/*
+ * ----------------------------------------------------------------------------
+ * Header inclusion
+ * ----------------------------------------------------------------------------
+ */
+
+#if SAMG_SERIES
+#include "samg.h"
+#endif /* SAMG_SERIES */
+
+#if SAME_SERIES
+#include "same.h"
+#endif /* SAME_SERIES */
+
+#if SAMD_SERIES
+#include "samd.h"
+#endif /* SAMD_SERIES */
+
+#if SAML_SERIES
+#include "saml.h"
+#endif /* SAML_SERIES */
+
+#if SAMC_SERIES
+#include "samc.h"
+#endif /* SAMC_SERIES */
+
+#if SAMS_SERIES
+#include "sams.h"
+#endif /* SAMS_SERIES */
+
+#if SAM3_SERIES
+#include "sam3.h"
+#endif /* SAM3_SERIES */
+
+#if SAMR_SERIES
+#include "samr.h"
+#endif /* SAMR_SERIES */
+
+#if SAM4_SERIES
+#include "sam4.h"
+#endif /* SAM4_SERIES */
+
+#endif