diff --git a/.gitignore b/.gitignore
index 31a2ae473b61b58e212f445c2e5511401fc19ff1..dae54c3ada7b570b393b6ec95dc20570e1ef06c3 100644
--- a/.gitignore
+++ b/.gitignore
@@ -21,6 +21,10 @@ test_save_to_file
 test_save_to_file_layout
 cpu_save_file
 
+# mock files
+mock*
+dummy
+
 *~
 *.autosave
 *.a
diff --git a/test/test_core/test_breakpoint.py b/test/test_core/test_breakpoint.py
index 10002b60999b8b6b436d0ad281c3b7b25664a318..ec961f4ee887db8e5ad28f493c41b38b2e16ca74 100644
--- a/test/test_core/test_breakpoint.py
+++ b/test/test_core/test_breakpoint.py
@@ -223,6 +223,7 @@ def test_stop_on_memory_breakpoint():
     mem = Memory(in_s, out_s, ctrl_s, adr_s, 8)
     cpu.add_module(mem)
     assert mem._memory == [0 for _ in range(8)]
+    assert cpu.clock == 0
 
     in_s.update_value(1)
     ctrl_s.update_value(True)
@@ -234,6 +235,7 @@ def test_stop_on_memory_breakpoint():
     cpu.run_continuously()
     assert mem._memory == [0, 0, 1, 0, 0, 0, 0, 0]
     assert cpu.is_stopped == True
+    assert cpu.clock == 2
 
     mem._memory = [0 for _ in range(8)]
     in_s.update_value(1)
diff --git a/test/test_core/test_reset.py b/test/test_core/test_reset.py
index a14b494c8cfe05b2e17739935028829748b92bc7..6d84136c19bafa0f5bd8e314329dd2b7e293f880 100644
--- a/test/test_core/test_reset.py
+++ b/test/test_core/test_reset.py
@@ -35,6 +35,7 @@ class DummyModule(Module):
 
 def test_reset():
     cpu = Processor()
+    cpu.signal_history = ["this", "should", "be", "removed"]
     dummy = DummyModule()
     cpu.clock = 100
     cpu.removed_cycles = 1337
diff --git a/test/test_core/test_save_state.py b/test/test_core/test_save_state.py
index 30609ac51e39ceacc511b69ae21a6d116152af07..16199e77a9b1e2795d0563d55ff97a0c0e046ef7 100644
--- a/test/test_core/test_save_state.py
+++ b/test/test_core/test_save_state.py
@@ -1,10 +1,10 @@
-from simudator.core.modules.register import Register
-from simudator.core.module import Module
-from simudator.processor.simple.simple import SIMPLE_CPU
+from unittest.mock import mock_open, patch
 
+from simudator.core.module import Module
+from simudator.core.modules.register import Register
 from simudator.core.signal import Signal
+from simudator.processor.simple.simple import SIMPLE_CPU
 
-from unittest.mock import patch, mock_open
 
 def test_module_save_state():
     module = Module({})
@@ -25,11 +25,10 @@ def test_module_save_state():
         module._helper_save_state_to_file(dummy_file_path, content)
         mock_file().write.assert_called_with(content)
 
+
 def test_default_register_save_state():
-    cpu = SIMPLE_CPU
-    in_sigal = Signal(cpu)
-    out_sigal = Signal(cpu)
-    register = Register(in_sigal, out_sigal)
+    in_sigal = Signal(None)
+    register = Register(in_sigal, None)
     register.name = "a"
     register._value = "a"