diff --git a/src/simudator/processor/mia/modules/ar.py b/src/simudator/processor/mia/modules/ar.py
index f0613cf7c0e121ff156e62cdac3f559861677471..bca9795267a761968984bd26eef6069031551c36 100644
--- a/src/simudator/processor/mia/modules/ar.py
+++ b/src/simudator/processor/mia/modules/ar.py
@@ -8,6 +8,11 @@ class AR(IntegerRegister, MiaBusConnector):
Register for saving AlU calculations in MIA.
"""
+ # Python does not allow multiple inherintence if more than one of the
+ # parent classes uses __slots__. Thus we also includes the __slots__
+ # from MiaBusConnector.
+ __slots__ = ("bus_id", "bus_control_s")
+
def __init__(
self,
alu_input_signal: Signal,
diff --git a/src/simudator/processor/mia/modules/hr.py b/src/simudator/processor/mia/modules/hr.py
index 7acc3ad5e2b5eb331099dc5f03eb8816380a3e06..506c4d5b14a543f9e3c3095cfa03cf73461735b7 100644
--- a/src/simudator/processor/mia/modules/hr.py
+++ b/src/simudator/processor/mia/modules/hr.py
@@ -8,6 +8,11 @@ class HR(IntegerRegister, MiaBusConnector):
Register for saving large AlU calculations in MIA.
"""
+ # Python does not allow multiple inherintence if more than one of the
+ # parent classes uses __slots__. Thus we also includes the __slots__
+ # from MiaBusConnector.
+ __slots__ = ("bus_id", "bus_control_s")
+
def __init__(
self,
alu_input_signal: Signal,
diff --git a/src/simudator/processor/mia/modules/ir.py b/src/simudator/processor/mia/modules/ir.py
index a5202abd5b770f175606a2820dac291b291c9c5b..9095742af61c392b20d01c976e56fd7717cd8052 100644
--- a/src/simudator/processor/mia/modules/ir.py
+++ b/src/simudator/processor/mia/modules/ir.py
@@ -12,11 +12,10 @@ class IR(Module, MiaBusConnector):
several fields.
"""
- __slots__ = (
- ("op", "grx", "m", "a", "instruction")
- + Module.__slots__
- + MiaBusConnector.__slots__
- )
+ # Python does not allow multiple inherintence if more than one of the
+ # parent classes uses __slots__. Thus we also includes the __slots__
+ # from MiaBusConnector.
+ __slots__ = ("op", "grx", "m", "a", "bus_id", "instruction", "bus_control_s")
def __init__(
self,
@@ -30,6 +29,7 @@ class IR(Module, MiaBusConnector):
bus_id=0,
name: str = "IR",
) -> None:
+
signals = {
"in_input": from_bus,
"out_output": to_bus,
diff --git a/src/simudator/processor/mia/modules/lc.py b/src/simudator/processor/mia/modules/lc.py
index 15e1598df7c809b62dabda12014548c85df77172..045e9810a3174db204a16325483b429b75b40946 100644
--- a/src/simudator/processor/mia/modules/lc.py
+++ b/src/simudator/processor/mia/modules/lc.py
@@ -12,6 +12,9 @@ class LC(Module):
increase by one or read from mM_uADR.
"""
+ __slots__ = ("value", "read_from_bus", "read_from_uADR", "decrement_by_one", "bit_length", "mask")
+
+
def __init__(
self,
mM_control: Signal,
diff --git a/src/simudator/processor/mia/modules/mia_bus_connect.py b/src/simudator/processor/mia/modules/mia_bus_connect.py
index ced584d445b092004ce1d16f0bdadc7a8f63b834..e5607b1f82509d93fba475bce0ebcc7b68bd3729 100644
--- a/src/simudator/processor/mia/modules/mia_bus_connect.py
+++ b/src/simudator/processor/mia/modules/mia_bus_connect.py
@@ -9,7 +9,10 @@ class MiaBusConnector:
Has logic for controlling when to read and write to bus.
"""
- __slots__ = ("bus_id", "bus_control_s")
+ # Python does not allow multiple inherintence if more than one of the
+ # parent classes uses __slots__. Since the modules that inherit from MiaBusConnector
+ # also inherits from other classes we leave this class __slots__ empty.
+ __slots__ = ()
def __init__(self, bus_control: Signal, bus_id: int = 0) -> None:
# init the name
diff --git a/src/simudator/processor/mia/modules/mia_grx.py b/src/simudator/processor/mia/modules/mia_grx.py
index 414bcb9aa6f32f25d2c0ca12f2ad4b9919423c21..71e18a0dc38dea4ab75644ca05096ec2a1602c1b 100644
--- a/src/simudator/processor/mia/modules/mia_grx.py
+++ b/src/simudator/processor/mia/modules/mia_grx.py
@@ -14,6 +14,8 @@ class GRX(Module, MiaBusConnector):
registers should be indexed by the GRx bits or the M bits.
"""
+ __slots__ = ("grx_control", "m_control", "s_control", "bus_id", "registers")
+
def __init__(
self,
to_bus: Signal,
@@ -25,12 +27,10 @@ class GRX(Module, MiaBusConnector):
bus_id: int,
name="GRx",
registers=[0 for _ in range(4)],
- bit_length=16,
) -> None:
# Set connection to/from bus and bus_id
MiaBusConnector.__init__(self, bus_control, bus_id)
-
# Other signals
signals = {
"in_input": from_bus,
@@ -45,9 +45,6 @@ class GRX(Module, MiaBusConnector):
# set the registers
self.registers = registers
- # set the bit_length
- self.bit_length = bit_length
-
def update_register(self):
"""
If the module should read from the bus, update the correct
@@ -98,7 +95,6 @@ class GRX(Module, MiaBusConnector):
"""
state = {
"name": self.name,
- "bit_length": self.bit_length,
"registers": self.registers[:],
}
return state
@@ -115,8 +111,6 @@ class GRX(Module, MiaBusConnector):
Sets the grx state to one given in dict.
"""
self.name = state["name"]
- if "bit_length" in state:
- self.bit_length = state["bit_length"]
self.registers = state["registers"]
def reset(self) -> None:
@@ -162,8 +156,6 @@ class GRX(Module, MiaBusConnector):
"\n -----",
"\n bus_id: ",
self.bus_id,
- "\n bit_length: ",
- self.bit_length,
"\n GR0: ",
hex(self.registers[0]),
"\n GR1: ",
@@ -173,4 +165,3 @@ class GRX(Module, MiaBusConnector):
"\n GR3: ",
hex(self.registers[3]),
)
-
diff --git a/src/simudator/processor/mia/modules/micro_pc.py b/src/simudator/processor/mia/modules/micro_pc.py
index 55500e7d68773ca19001f75553d238c0c14c1bf8..f574fc345be55899556ef5587332c4d0e90bf376 100644
--- a/src/simudator/processor/mia/modules/micro_pc.py
+++ b/src/simudator/processor/mia/modules/micro_pc.py
@@ -11,6 +11,8 @@ class MicroPC(Module):
to read from or write to.
"""
+ __slots__ = ("value", "bit_length")
+
def __init__(
self,
control_signal: Signal,