diff --git a/docs/conf.py b/docs/conf.py
index d3b25afc04d08d30c0233277a0fb45c9638de8bc..14d81c23e6a1b6b6f5f2f2f4b097c01c9ffc0c4f 100644
--- a/docs/conf.py
+++ b/docs/conf.py
@@ -8,8 +8,10 @@
project = 'simuDAtor'
copyright = '2023, simuDAtor authors'
-author = ('Martin Högstedt, Elias Johansson, Johannes Kung, Oscar Gustafsson, '
- 'Anders Nilsson, Kent Palmkvist')
+author = (
+ 'Martin Högstedt, Elias Johansson, Johannes Kung, Oscar Gustafsson, '
+ 'Anders Nilsson, Kent Palmkvist'
+)
# -- General configuration ---------------------------------------------------
# https://www.sphinx-doc.org/en/master/usage/configuration.html#general-configuration
diff --git a/src/simudator/cli/cli.py b/src/simudator/cli/cli.py
index 63bbc344473a03c1c4818928cc9e3c2f81da5728..0578f640d35540598e04d9638f5caf96fca8da80 100644
--- a/src/simudator/cli/cli.py
+++ b/src/simudator/cli/cli.py
@@ -26,7 +26,6 @@ class CLI:
print("Welcome to simuDAtor!")
while self.running:
-
# Get user commands here
user_input = input("> ")
@@ -76,7 +75,7 @@ class CLI:
self.processor.run_continuously()
case ["r"] | ["resets"]:
- #self.processor.load_cycle(0)
+ # self.processor.load_cycle(0)
self.processor.reset()
case ["n", _] | ["next", _]:
@@ -98,7 +97,7 @@ class CLI:
except FileNotFoundError:
print("No file called ", user_input.split()[1], " was found")
- case ["pl", *_] | ["printlist", *_] :
+ case ["pl", *_] | ["printlist", *_]:
self.print_list_command(user_input.split())
case ["u", _] | ["undo", _]:
@@ -131,8 +130,9 @@ class CLI:
state_name = user_input.split()[3]
val = ast.literal_eval(user_input.split()[4])
try:
- self.processor.add_state_breakpoint(module_name,
- state_name, val)
+ self.processor.add_state_breakpoint(
+ module_name, state_name, val
+ )
except ValueError as e:
print(e)
@@ -141,8 +141,7 @@ class CLI:
try:
adress = ast.literal_eval(user_input.split()[3])
value = ast.literal_eval(user_input.split()[4])
- self.processor.add_memory_breakpoint(module_name,
- adress, value)
+ self.processor.add_memory_breakpoint(module_name, adress, value)
except ValueError as e:
print(e)
@@ -154,8 +153,7 @@ class CLI:
key, value = kwarg.split('=')
kwargs[key] = ast.literal_eval(value)
try:
- self.processor.add_lambda_breakpoint(lambda_name,
- **kwargs)
+ self.processor.add_lambda_breakpoint(lambda_name, **kwargs)
except ValueError as e:
print(e)
@@ -167,14 +165,14 @@ class CLI:
except ValueError:
print("Breakpoint ID must be an integer")
-
case ["h"] | ["help"]:
# prints help message
- print("Here is a list of possible commands:\n"
+ print(
+ "Here is a list of possible commands:\n"
"- c, clock : Prints the processors current clock cycle.\n"
"- p [name*], print [name*]: Prints the states with "
- "given name. "
- "Will print all modules if no names are given.\n"\
+ "given name. "
+ "Will print all modules if no names are given.\n"
"- p br, print breaks: Prints all breakpoints.\n"
"- p br lam, print break lambdas: Prints all available "
"lambdas of this processor to use for lambda "
@@ -209,8 +207,9 @@ class CLI:
"enclosed with quotation marks. \n"
"- rm br [id], remove break [id]: Remove the "
"breakpoint with the given ID.\n"
- "- h, help : Shows this message.\n"\
- "- q, quit : Closes the program. Nothing will be saved.")
+ "- h, help : Shows this message.\n"
+ "- q, quit : Closes the program. Nothing will be saved."
+ )
case ["q"] | ["quit"]:
# Ends the loop
@@ -273,10 +272,7 @@ class CLI:
else:
return
-
-
def print_list_command(self, user_input):
-
# no additional commands so only print
if len(user_input) == 1:
print("\n")
@@ -307,7 +303,6 @@ class CLI:
print("Unknown command")
-
if __name__ == '__main__':
cli = CLI(None)
cli.run()
diff --git a/src/simudator/processor/mia/alu.py b/src/simudator/processor/mia/alu.py
index 15e090010d61c70c77ca7a30de21d64966749939..107b675a193ffc325f17738c36de2445408aa7ba 100644
--- a/src/simudator/processor/mia/alu.py
+++ b/src/simudator/processor/mia/alu.py
@@ -15,19 +15,20 @@ class ALU(Module):
WORD_LENGTH = 16
- def __init__(self,
- name: str,
- input_signal_a: Signal,
- input_signal_b: Signal,
- input_signal_hr: Signal,
- control_signal: Signal,
- output_signal: Signal,
- output_signal_hr: Signal,
- z_signal: Signal,
- n_signal: Signal,
- o_signal: Signal,
- c_signal: Signal):
-
+ def __init__(
+ self,
+ name: str,
+ input_signal_a: Signal,
+ input_signal_b: Signal,
+ input_signal_hr: Signal,
+ control_signal: Signal,
+ output_signal: Signal,
+ output_signal_hr: Signal,
+ z_signal: Signal,
+ n_signal: Signal,
+ o_signal: Signal,
+ c_signal: Signal,
+ ):
super().__init__(name)
# Input Signals
@@ -98,7 +99,7 @@ class ALU(Module):
case 0b0011:
# returns 0
- output_value = 0
+ output_value = 0
case 0b0100:
# return sum of a and b
@@ -160,29 +161,35 @@ class ALU(Module):
self.output_signal_hr.update_value(self.hr_value)
def print_module(self) -> None:
- print("", self.name, "\n -----",
- "\n a_value: ", self.input_signal_a.get_value(),
- "\n b_value: ", self.input_signal_b.get_value(),
- "\n control_signal: ", self.control_signal.get_value()
- )
+ print(
+ "",
+ self.name,
+ "\n -----",
+ "\n a_value: ",
+ self.input_signal_a.get_value(),
+ "\n b_value: ",
+ self.input_signal_b.get_value(),
+ "\n control_signal: ",
+ self.control_signal.get_value(),
+ )
def get_input_signals(self) -> list[Signal]:
return [
- self.input_signal_a,
- self.input_signal_b,
- self.control_signal,
- self.input_signal_hr
- ]
+ self.input_signal_a,
+ self.input_signal_b,
+ self.control_signal,
+ self.input_signal_hr,
+ ]
def get_output_signals(self) -> list[Signal]:
return [
- self.output_signal,
- self.output_signal_hr,
- self.z_signal,
- self.n_signal,
- self.o_signal,
- self.c_signal
- ]
+ self.output_signal,
+ self.output_signal_hr,
+ self.z_signal,
+ self.n_signal,
+ self.o_signal,
+ self.c_signal,
+ ]
# ----- ALU operations -----
@@ -293,7 +300,6 @@ class ALU(Module):
carry = None
if hr_value is not None:
-
# get hr as a binary
hr_binary = self.int_to_bin(hr_value)
@@ -301,19 +307,18 @@ class ALU(Module):
long_word_binary = hr_binary[1:] + binary_number + [0]
# get hr number
- new_hr_number = self.bin_to_int(long_word_binary[:self.WORD_LENGTH])
+ new_hr_number = self.bin_to_int(long_word_binary[: self.WORD_LENGTH])
# update hr
self.hr_value = new_hr_number
# get new value from binary
- new_binary_number = long_word_binary[self.WORD_LENGTH:]
+ new_binary_number = long_word_binary[self.WORD_LENGTH :]
# Update carry with removed bit
carry = hr_binary[0]
else:
-
# Do shift
new_binary_number = binary_number[1:] + [0]
@@ -361,7 +366,6 @@ class ALU(Module):
carry = None
if hr_value is not None:
-
# get hr as a binary
hr_binary = self.int_to_bin(hr_value)
@@ -369,18 +373,17 @@ class ALU(Module):
long_word_binary = [binary_number[-1]] + hr_binary + binary_number[:-1]
# get hr number
- new_hr_number = self.bin_to_int(long_word_binary[:self.WORD_LENGTH])
+ new_hr_number = self.bin_to_int(long_word_binary[: self.WORD_LENGTH])
# update hr
self.hr_value = new_hr_number
# get new value from binary
- new_binary_number = long_word_binary[self.WORD_LENGTH:]
+ new_binary_number = long_word_binary[self.WORD_LENGTH :]
# Update carry with removed bit
carry = binary_number[-1]
-
else:
# Do shift
new_binary_number = [binary_number[0]] + binary_number[:-1]
@@ -410,33 +413,30 @@ class ALU(Module):
carry = None
if hr_value is not None:
-
# get hr as a binary
hr_binary = self.int_to_bin(self.input_signal_hr.get_value())
long_word_binary = hr_binary[1:] + binary_number + [hr_binary[0]]
# get hr number
- new_hr_number = self.bin_to_int(long_word_binary[:self.WORD_LENGTH])
+ new_hr_number = self.bin_to_int(long_word_binary[: self.WORD_LENGTH])
# update hr
self.hr_value = new_hr_number
# get new value from binary
- new_binary_number = long_word_binary[self.WORD_LENGTH:]
+ new_binary_number = long_word_binary[self.WORD_LENGTH :]
# Update carry with removed bit
carry = hr_binary[0]
else:
-
# Do rotation
new_binary_number = binary_number[1:] + [binary_number[0]]
# Update carry with removed bit
carry = binary_number[0]
-
# Convert shifted to int
value = self.bin_to_int(new_binary_number)
@@ -459,7 +459,7 @@ class ALU(Module):
# Get values for bits and add them
for bit_index in range(0, word_length):
- number += binary_number[bit_index] * 2**(word_length - bit_index -1)
+ number += binary_number[bit_index] * 2 ** (word_length - bit_index - 1)
return number
@@ -483,8 +483,8 @@ class ALU(Module):
for bit_index in range(0, word_length):
# If number is larger then bit we subtract the
# bits decimal value from the number and make the bit 1.
- if number >= 2**(word_length- bit_index -1):
- number -= 2**(word_length- bit_index -1)
+ if number >= 2 ** (word_length - bit_index - 1):
+ number -= 2 ** (word_length - bit_index - 1)
binary_number[bit_index] = 1
return binary_number
@@ -519,19 +519,18 @@ class ALU(Module):
# We add this so the rest of the caclulation is
# the same for nagativ numbers
- number += 2**(self.WORD_LENGTH-1)
+ number += 2 ** (self.WORD_LENGTH - 1)
# We can now look at the other bits
for bit_index in range(1, self.WORD_LENGTH):
# If number is larger then bit we subtract the
# bits decimal value from the number and make the bit 1.
- if number >= 2**(self.WORD_LENGTH - bit_index -1):
- number -= 2**(self.WORD_LENGTH - bit_index -1)
+ if number >= 2 ** (self.WORD_LENGTH - bit_index - 1):
+ number -= 2 ** (self.WORD_LENGTH - bit_index - 1)
binary_number[bit_index] = 1
return binary_number
-
def bin_to_int_twocomp(self, binary_number: [int]) -> int:
"""
Converts from two's complement binary list representation to int
@@ -541,23 +540,19 @@ class ALU(Module):
# two's complement representation so most significant
# bit will be negativ
if binary_number[0] == 1:
- number = -2**(self.WORD_LENGTH-1)
+ number = -(2 ** (self.WORD_LENGTH - 1))
# Get values for other bits
for bit_index in range(1, self.WORD_LENGTH):
- number += binary_number[bit_index] * 2**(self.WORD_LENGTH
- - bit_index -1)
+ number += binary_number[bit_index] * 2 ** (self.WORD_LENGTH - bit_index - 1)
return number
# ----- Internal operations -----
- def update_flags(self,
- binary_a: [int],
- binary_b: [int],
- binary_result: [int],
- carry: int) -> None:
-
+ def update_flags(
+ self, binary_a: [int], binary_b: [int], binary_result: [int], carry: int
+ ) -> None:
"""
Will update the flags depending on inputed values and the result.
This function can take none for any input and will update the
@@ -565,7 +560,6 @@ class ALU(Module):
"""
if binary_result is not None:
-
# Update z flag if we have result
# For this we check if result is zero
if self.bin_to_int(binary_result, len(binary_result)) == 0:
@@ -582,7 +576,6 @@ class ALU(Module):
# If we also have given values we can calculate o flag
if binary_a is not None and binary_b is not None:
-
# Check if last bit in result is diffrent from both iven values
if (binary_a[0] == binary_b[0]) and (binary_a[0] != binary_result[0]):
self.o_value = 1
@@ -593,7 +586,6 @@ class ALU(Module):
if carry is not None:
self.c_value = carry
-
def bitwise_not(self, binary_number: [int]) -> [int]:
"""
Returns bitwise not of given binary number
@@ -624,7 +616,7 @@ class ALU(Module):
carry = 0
# Do addition bit by bit and save carry between each loop
- for bit_index in range(self.WORD_LENGTH-1, -1, -1):
+ for bit_index in range(self.WORD_LENGTH - 1, -1, -1):
bit_sum = binary_a[bit_index] + binary_b[bit_index] + carry
match bit_sum:
case 0:
@@ -649,8 +641,7 @@ class ALU(Module):
binary_and = [0 for i in range(self.WORD_LENGTH)]
for binary_index in range(self.WORD_LENGTH):
- binary_and[binary_index] = binary_a[binary_index] \
- & binary_b[binary_index]
+ binary_and[binary_index] = binary_a[binary_index] & binary_b[binary_index]
return binary_and
@@ -661,7 +652,6 @@ class ALU(Module):
binary_or = [0 for i in range(self.WORD_LENGTH)]
for binary_index in range(self.WORD_LENGTH):
- binary_or[binary_index] = binary_a[binary_index] \
- | binary_b[binary_index]
+ binary_or[binary_index] = binary_a[binary_index] | binary_b[binary_index]
return binary_or
diff --git a/src/simudator/processor/mia/ar.py b/src/simudator/processor/mia/ar.py
index 46dbd67b96f96a4988edc1705eee6c3b85735f99..ee651082c41a9bcb37e2571568fb00d4bb70a697 100644
--- a/src/simudator/processor/mia/ar.py
+++ b/src/simudator/processor/mia/ar.py
@@ -8,23 +8,24 @@ class AR(IntegerRegister, MiaBusConnector):
Register for saving AlU calculations in MIA.
"""
- def __init__(self,
- alu_input_signal: Signal,
- alu_output_signal: Signal,
- bus_output_signal: Signal,
- bus_control_signal: Signal,
- bus_id: int,
- bit_length: int,
- name = "AR") -> None:
-
+ def __init__(
+ self,
+ alu_input_signal: Signal,
+ alu_output_signal: Signal,
+ bus_output_signal: Signal,
+ bus_control_signal: Signal,
+ bus_id: int,
+ bit_length: int,
+ name="AR",
+ ) -> None:
self.alu_output_signal = alu_output_signal
- IntegerRegister.__init__(self, alu_input_signal, bus_output_signal,
- bit_length, name=name)
+ IntegerRegister.__init__(
+ self, alu_input_signal, bus_output_signal, bit_length, name=name
+ )
MiaBusConnector.__init__(self, bus_control_signal, bus_id)
def output_register(self) -> None:
-
# always update alu
self.alu_output_signal.update_value(self.value)
@@ -44,13 +45,15 @@ class AR(IntegerRegister, MiaBusConnector):
return [self.input_s]
def get_output_signals(self) -> list[Signal]:
- return [
- self.alu_output_signal,
- self.output_s,
- self.bus_control_s
- ]
+ return [self.alu_output_signal, self.output_s, self.bus_control_s]
def print_module(self):
- print("", self.name, "\n -----",
- "\n value: ", hex(self.value),
- "\n bit length: ", self.bit_length)
+ print(
+ "",
+ self.name,
+ "\n -----",
+ "\n value: ",
+ hex(self.value),
+ "\n bit length: ",
+ self.bit_length,
+ )
diff --git a/src/simudator/processor/mia/asr.py b/src/simudator/processor/mia/asr.py
index d1b9990b4ee9e87d2a34226e60a42bee6acb6284..4bc5de379a75689c9c0ec14c684f8d4b6a42dfa3 100644
--- a/src/simudator/processor/mia/asr.py
+++ b/src/simudator/processor/mia/asr.py
@@ -8,16 +8,18 @@ class ASR(IntegerRegister, MiaBusConnector):
Register for controlling the memory andress in MIA.
"""
- def __init__(self,
- bus_input_signal: Signal,
- memory_output_signal: Signal,
- bus_control_signal: Signal,
- bus_id: int,
- bit_length: int,
- name = "ASR") -> None:
-
- IntegerRegister.__init__(self, bus_input_signal, memory_output_signal,
- bit_length, name=name)
+ def __init__(
+ self,
+ bus_input_signal: Signal,
+ memory_output_signal: Signal,
+ bus_control_signal: Signal,
+ bus_id: int,
+ bit_length: int,
+ name="ASR",
+ ) -> None:
+ IntegerRegister.__init__(
+ self, bus_input_signal, memory_output_signal, bit_length, name=name
+ )
MiaBusConnector.__init__(self, bus_control_signal, bus_id)
def update_register(self) -> None:
@@ -35,6 +37,12 @@ class ASR(IntegerRegister, MiaBusConnector):
return [self.output_s]
def print_module(self):
- print("", self.name, "\n -----",
- "\n value: ", hex(self.value),
- "\n bit length: ", self.bit_length)
+ print(
+ "",
+ self.name,
+ "\n -----",
+ "\n value: ",
+ hex(self.value),
+ "\n bit length: ",
+ self.bit_length,
+ )
diff --git a/src/simudator/processor/mia/bus.py b/src/simudator/processor/mia/bus.py
index a7ff764c74c0a5fd4da41c4e807cec1462c235da..423bc875d4991908a3556365381a162615828fb9 100644
--- a/src/simudator/processor/mia/bus.py
+++ b/src/simudator/processor/mia/bus.py
@@ -10,10 +10,9 @@ class Bus(Module):
input signal can send a value to the bus at a time.
"""
- def __init__(self,
- inputs: list[Signal] = [],
- outputs: list[Signal] = [],
- name: str = "Bus") -> None:
+ def __init__(
+ self, inputs: list[Signal] = [], outputs: list[Signal] = [], name: str = "Bus"
+ ) -> None:
super().__init__(name)
self.inputs = inputs
@@ -44,7 +43,6 @@ class Bus(Module):
for output_signal in self.outputs:
output_signal.update_value(value)
-
def get_state(self) -> dict:
return super().get_state()
diff --git a/src/simudator/processor/mia/hr.py b/src/simudator/processor/mia/hr.py
index 529c8ed19b433c76fab50e36ec394b5b2ccaa1a3..a817c87cce53c94454f3ed92799c3d6d14e6f3b1 100644
--- a/src/simudator/processor/mia/hr.py
+++ b/src/simudator/processor/mia/hr.py
@@ -8,23 +8,25 @@ class HR(IntegerRegister, MiaBusConnector):
Register for saving large AlU calculations in MIA.
"""
- def __init__(self,
- alu_input_signal: Signal,
- alu_output_signal: Signal,
- bus_input_signal: Signal,
- bus_output_signal: Signal,
- bus_control_signal: Signal,
- bus_id: int,
- bit_lenght: int,
- name = "HR") -> None:
-
+ def __init__(
+ self,
+ alu_input_signal: Signal,
+ alu_output_signal: Signal,
+ bus_input_signal: Signal,
+ bus_output_signal: Signal,
+ bus_control_signal: Signal,
+ bus_id: int,
+ bit_lenght: int,
+ name="HR",
+ ) -> None:
self.alu_output_signal = alu_output_signal
self.alu_input_signal = alu_input_signal
self.alu_input_signal.add_destination(self)
- IntegerRegister.__init__(self, bus_input_signal, bus_output_signal,
- bit_lenght, name=name)
+ IntegerRegister.__init__(
+ self, bus_input_signal, bus_output_signal, bit_lenght, name=name
+ )
MiaBusConnector.__init__(self, bus_control_signal, bus_id)
def update_register(self) -> None:
@@ -60,19 +62,22 @@ class HR(IntegerRegister, MiaBusConnector):
self.output_register()
def print_module(self):
- print("", self.name, "\n -----",
- "\n value: ", hex(self.value),
- "\n bit length: ", self.bit_length)
+ print(
+ "",
+ self.name,
+ "\n -----",
+ "\n value: ",
+ hex(self.value),
+ "\n bit length: ",
+ self.bit_length,
+ )
def get_input_signals(self) -> list[Signal]:
- return [
- self.alu_input_signal,
- self.input_s
- ]
+ return [self.alu_input_signal, self.input_s]
def get_output_signals(self) -> list[Signal]:
return [
- self.alu_output_signal,
- self.bus_control_s,
- self.output_s,
- ]
+ self.alu_output_signal,
+ self.bus_control_s,
+ self.output_s,
+ ]
diff --git a/src/simudator/processor/mia/ir.py b/src/simudator/processor/mia/ir.py
index 1b7f37a26c1efcbded17c294eb6ecf2b734b1386..0e4a5639db5e98959706888b166d017d224b9b20 100644
--- a/src/simudator/processor/mia/ir.py
+++ b/src/simudator/processor/mia/ir.py
@@ -11,16 +11,19 @@ class IR(Module, MiaBusConnector):
be performed by the cpu. The instructions are dividied into
several fields.
"""
- def __init__(self,
- to_bus: Signal,
- from_bus: Signal,
- op_s: Signal,
- grx_s: Signal,
- m_s: Signal,
- bus_control: Signal,
- default_value = 0,
- bus_id = 0,
- name: str = "IR") -> None:
+
+ def __init__(
+ self,
+ to_bus: Signal,
+ from_bus: Signal,
+ op_s: Signal,
+ grx_s: Signal,
+ m_s: Signal,
+ bus_control: Signal,
+ default_value=0,
+ bus_id=0,
+ name: str = "IR",
+ ) -> None:
MiaBusConnector.__init__(self, bus_control, bus_id)
Module.__init__(self, name)
@@ -54,7 +57,7 @@ class IR(Module, MiaBusConnector):
self.op = self.instruction >> 12
self.grx = (self.instruction >> 10) & 0b11
self.m = (self.instruction >> 8) & 0b11
- self.a = self.instruction & (2**8-1)
+ self.a = self.instruction & (2**8 - 1)
def output_register(self) -> None:
"""
@@ -76,13 +79,13 @@ class IR(Module, MiaBusConnector):
def get_state(self) -> dict[str, Any]:
state = {
- "name": self.name,
- "value": self.instruction,
- "op": self.op,
- "grx": self.grx,
- "m": self.m,
- "a": self.a
- }
+ "name": self.name,
+ "value": self.instruction,
+ "op": self.op,
+ "grx": self.grx,
+ "m": self.m,
+ "a": self.a,
+ }
return state
def get_gui_state(self) -> dict:
@@ -113,12 +116,21 @@ class IR(Module, MiaBusConnector):
self.a = 0
def print_module(self) -> None:
- print("", self.name, "\n -----",
- "\n value: ", hex(self.instruction),
- "\n op: ", bin(self.op),
- "\n grx: ", bin(self.grx),
- "\n m: ", bin(self.m),
- "\n a: ", bin(self.a))
+ print(
+ "",
+ self.name,
+ "\n -----",
+ "\n value: ",
+ hex(self.instruction),
+ "\n op: ",
+ bin(self.op),
+ "\n grx: ",
+ bin(self.grx),
+ "\n m: ",
+ bin(self.m),
+ "\n a: ",
+ bin(self.a),
+ )
def save_state_to_file(self, file_path: str) -> None:
"""
@@ -131,18 +143,16 @@ class IR(Module, MiaBusConnector):
def load_from_str(self, state_string):
string_pair = state_string.split(": ")
- #TODO: Maybe check if it starts with instruction: ?
+ # TODO: Maybe check if it starts with instruction: ?
self.instruction = int(string_pair[1], 16)
def get_input_signals(self) -> list[Signal]:
- return [
- self.from_bus_s
- ]
+ return [self.from_bus_s]
def get_output_signals(self) -> list[Signal]:
return [
- self.to_bus_s,
- self.op_s,
- self.grx_s,
- self.m_s,
- ]
+ self.to_bus_s,
+ self.op_s,
+ self.grx_s,
+ self.m_s,
+ ]
diff --git a/src/simudator/processor/mia/lc.py b/src/simudator/processor/mia/lc.py
index cff9e9e3477bc8fcbd9456d0d8f9e972806c4110..7a936386cd2a577ab0621b3b52e102ae9111c85a 100644
--- a/src/simudator/processor/mia/lc.py
+++ b/src/simudator/processor/mia/lc.py
@@ -13,15 +13,16 @@ class LC(Module):
increase by one or read from mM_uADR.
"""
- def __init__(self,
- mM_control: Signal,
- bus_input: Signal,
- l_flag: Signal,
- mM_uADR: Signal,
- name="LC",
- value=0,
- bit_length=8
- ) -> None:
+ def __init__(
+ self,
+ mM_control: Signal,
+ bus_input: Signal,
+ l_flag: Signal,
+ mM_uADR: Signal,
+ name="LC",
+ value=0,
+ bit_length=8,
+ ) -> None:
"""
:param mM_control: A signal connection from the micro memory
to the loop counter. This allows the micro memory to send bit
@@ -73,7 +74,7 @@ class LC(Module):
# bit length and mask
self.bit_length = bit_length
- self.mask = 2**self.bit_length-1
+ self.mask = 2**self.bit_length - 1
# set the loop counter as the destination of its input signals
self.mM_control_s.add_destination(self)
@@ -96,17 +97,17 @@ class LC(Module):
self.read_from_bus = False
self.read_from_uADR = False
- case 0b01: # Decrement by one
+ case 0b01: # Decrement by one
self.decrement_by_one = True
self.read_from_bus = False
self.read_from_uADR = False
- case 0b10: # Load 8 least significant bits from bus
+ case 0b10: # Load 8 least significant bits from bus
self.decrement_by_one = False
self.read_from_bus = True
self.read_from_uADR = False
- case 0b11: # LCs 7 least significant bits are loaded from uADR
+ case 0b11: # LCs 7 least significant bits are loaded from uADR
self.decrement_by_one = False
self.read_from_bus = False
self.read_from_uADR = True
@@ -126,7 +127,6 @@ class LC(Module):
if self.value < 0:
self.value = self.mask
-
def output_register(self) -> None:
"""
The loop counter will only output to the L flag, this is
@@ -144,7 +144,7 @@ class LC(Module):
else:
self.l_flag_s.update_value(0)
- def get_state(self) -> dict[str: Any]:
+ def get_state(self) -> dict[str:Any]:
"""
Returns a dict of the loop counter state.
These states are changable via set_states.
@@ -162,7 +162,7 @@ class LC(Module):
state["decrement_by_one"] = self.decrement_by_one
return state
- def set_state(self, state: dict[str: Any]) -> None:
+ def set_state(self, state: dict[str:Any]) -> None:
"""
Sets the loop counter state to one given in dict.
"""
@@ -200,23 +200,26 @@ class LC(Module):
def load_from_str(self, state_string):
string_pair = state_string.split(": ")
- #TODO: Maybe check if it starts with value: ?
+ # TODO: Maybe check if it starts with value: ?
self.value = int(string_pair[1], 16)
def print_module(self) -> None:
- print("", self.name, "\n -----",
- "\n value: ", hex(self.value),
- "\n decrement: ", self.decrement_by_one,
- "\n read from uADR: ", self.read_from_uADR,
- "\n read from bus: ", self.read_from_bus,
- )
+ print(
+ "",
+ self.name,
+ "\n -----",
+ "\n value: ",
+ hex(self.value),
+ "\n decrement: ",
+ self.decrement_by_one,
+ "\n read from uADR: ",
+ self.read_from_uADR,
+ "\n read from bus: ",
+ self.read_from_bus,
+ )
def get_input_signals(self) -> list[Signal]:
- return [
- self.mM_control_s,
- self.bus_input_s,
- self.mM_uADR_s
- ]
+ return [self.mM_control_s, self.bus_input_s, self.mM_uADR_s]
def get_output_signals(self) -> list[Signal]:
return [self.l_flag_s]
diff --git a/src/simudator/processor/mia/mia.py b/src/simudator/processor/mia/mia.py
index 7c56ba39eb4a8d65d4003d27ab008cb4254dd6df..b6576113e497e431d272a214c2ce47ff9a639f29 100644
--- a/src/simudator/processor/mia/mia.py
+++ b/src/simudator/processor/mia/mia.py
@@ -47,7 +47,7 @@ class MIA_CPU(Processor):
self.max_line_len = 100
# A signal used by all modules connected to the bus
- bus_control = Signal(self, "bus_control", (0,0))
+ bus_control = Signal(self, "bus_control", (0, 0))
# Dummy values used when the values in the constructor is not needed
# unused = Signal(self)
@@ -75,15 +75,15 @@ class MIA_CPU(Processor):
c_alu = Signal(self, "c_alu")
grx_bus = Signal(self, "grx_bus")
bus_grx = Signal(self, "bus_grx")
- grx_control = Signal(self, "grx_control") # used to index registers with GRx
- m_control = Signal(self, "m_control") # used to index registers with M
- s_control = Signal(self, "s_control") # decides if GRx or M is used
+ grx_control = Signal(self, "grx_control") # used to index registers with GRx
+ m_control = Signal(self, "m_control") # used to index registers with M
+ s_control = Signal(self, "s_control") # decides if GRx or M is used
pc_uM = Signal(self, "pc_uM")
bus_pc = Signal(self, "bus_pc")
pc_bus = Signal(self, "pc_bus")
pm_bus = Signal(self, "pm_bus")
bus_pm = Signal(self, "bus_pm")
- always_write_signal = Signal(self, value = (999, 0))
+ always_write_signal = Signal(self, value=(999, 0))
uPC_k1 = Signal(self, "uPC_k1")
k1_ir = Signal(self, "k1_ir")
uPC_k2 = Signal(self, "uPC_k2")
@@ -121,8 +121,19 @@ class MIA_CPU(Processor):
hr = HR(alu_hr, hr_alu, bus_hr, hr_bus, bus_control, hr_bus_id, hr_bit_length)
# ALU specific
- alu = ALU("ALU", alu_ar, alu_bus, alu_hr, alu_uM, ar_alu, hr_alu,
- z_alu, n_alu, o_alu, c_alu)
+ alu = ALU(
+ "ALU",
+ alu_ar,
+ alu_bus,
+ alu_hr,
+ alu_uM,
+ ar_alu,
+ hr_alu,
+ z_alu,
+ n_alu,
+ o_alu,
+ c_alu,
+ )
# PC specific
pc_bus_id = 0b011
@@ -133,78 +144,142 @@ class MIA_CPU(Processor):
pm_bus_id = 0b010
pm_adress_padding = 2
pm_value_padding = 4
- pm = MiaMemory(pm_bus, bus_pm, pm_asr, bus_control, pm_size,
- pm_bus_id, value_padding = pm_value_padding,
- adress_padding = pm_adress_padding, name = "PM")
-
+ pm = MiaMemory(
+ pm_bus,
+ bus_pm,
+ pm_asr,
+ bus_control,
+ pm_size,
+ pm_bus_id,
+ value_padding=pm_value_padding,
+ adress_padding=pm_adress_padding,
+ name="PM",
+ )
# GRX specific
grx_bus_id = 0b110
- grx = GRX(bus_grx, grx_bus, bus_control, grx_control, m_control,
- s_control, grx_bus_id)
+ grx = GRX(
+ bus_grx, grx_bus, bus_control, grx_control, m_control, s_control, grx_bus_id
+ )
# K1 specific
k1_size = 16
k1_adress_padding = 2
k1_value_padding = 2
- k1 = MiaMemory(always_write_signal, uPC_k1, k1_ir,
- always_write_signal, k1_size, always_write_id,
- name = "K1", adress_padding = k1_adress_padding,
- value_padding = k1_value_padding)
+ k1 = MiaMemory(
+ always_write_signal,
+ uPC_k1,
+ k1_ir,
+ always_write_signal,
+ k1_size,
+ always_write_id,
+ name="K1",
+ adress_padding=k1_adress_padding,
+ value_padding=k1_value_padding,
+ )
# K2 specific
k2_size = 4
k2_adress_padding = 2
k2_value_padding = 2
- k2 = MiaMemory(always_write_signal, uPC_k2, m_control,
- always_write_signal, k2_size, always_write_id,
- name = "K2", adress_padding = k2_adress_padding,
- value_padding = k2_value_padding)
+ k2 = MiaMemory(
+ always_write_signal,
+ uPC_k2,
+ m_control,
+ always_write_signal,
+ k2_size,
+ always_write_id,
+ name="K2",
+ adress_padding=k2_adress_padding,
+ value_padding=k2_value_padding,
+ )
# IR specific
ir_bus_id = 0b001
- ir = IR(bus_ir, ir_bus, k1_ir, grx_control, m_control, bus_control,
- default_value, ir_bus_id)
+ ir = IR(
+ bus_ir,
+ ir_bus,
+ k1_ir,
+ grx_control,
+ m_control,
+ bus_control,
+ default_value,
+ ir_bus_id,
+ )
# uPC specific
- uPC = MicroPC(uPC_uM_cont, uPC_k1, uPC_k2, SuPC_uPC, uPC_SuPC,
- uM_uPC, uPC_uM)
+ uPC = MicroPC(uPC_uM_cont, uPC_k1, uPC_k2, SuPC_uPC, uPC_SuPC, uM_uPC, uPC_uM)
# Su_PC specific
SuPC_bit_length = 7
SuPC_name = "SuPC"
- Su_PC = IntegerRegister(SuPC_uPC, uPC_SuPC, SuPC_bit_length,
- default_value, SuPC_name)
+ Su_PC = IntegerRegister(
+ SuPC_uPC, uPC_SuPC, SuPC_bit_length, default_value, SuPC_name
+ )
# uM specific
- uM = MicroMemory(alu_uM, bus_control, bus_uM, s_control, pc_uM,
- lc_uM, lc_uM_uADR, uM_uPC, uPC_uM_cont, uPC_uM,
- uM_z, uM_n, uM_c, uM_o, uM_l)
+ uM = MicroMemory(
+ alu_uM,
+ bus_control,
+ bus_uM,
+ s_control,
+ pc_uM,
+ lc_uM,
+ lc_uM_uADR,
+ uM_uPC,
+ uPC_uM_cont,
+ uPC_uM,
+ uM_z,
+ uM_n,
+ uM_c,
+ uM_o,
+ uM_l,
+ )
# LC specific
lc = LC(lc_uM, lc_bus, l_lc, lc_uM_uADR)
# Flags
- z_flag = Flag(z_alu, uM_z, name = "Z-Flag")
- n_flag = Flag(n_alu, uM_n, name = "N-Flag")
- c_flag = Flag(c_alu, uM_c, name = "C-Flag")
- o_flag = Flag(o_alu, uM_o, name = "O-Flag")
- l_flag = Flag(l_lc, uM_l, name = "L-Flag")
+ z_flag = Flag(z_alu, uM_z, name="Z-Flag")
+ n_flag = Flag(n_alu, uM_n, name="N-Flag")
+ c_flag = Flag(c_alu, uM_c, name="C-Flag")
+ o_flag = Flag(o_alu, uM_o, name="O-Flag")
+ l_flag = Flag(l_lc, uM_l, name="L-Flag")
# Bus
- bus = Bus([bus_ir, bus_pm, bus_pc, bus_hr, bus_grx, bus_ar, bus_uM],
- [asr_bus, ir_bus, pm_bus, pc_bus, hr_bus, grx_bus, alu_bus, lc_bus])
-
- ALLTHEMODULES = [uPC, lc, uM, Su_PC, ir, k2, k1, pc, ar, hr, grx,
- z_flag, n_flag, o_flag, l_flag, c_flag, pm, alu, asr,
- bus]
+ bus = Bus(
+ [bus_ir, bus_pm, bus_pc, bus_hr, bus_grx, bus_ar, bus_uM],
+ [asr_bus, ir_bus, pm_bus, pc_bus, hr_bus, grx_bus, alu_bus, lc_bus],
+ )
+
+ ALLTHEMODULES = [
+ uPC,
+ lc,
+ uM,
+ Su_PC,
+ ir,
+ k2,
+ k1,
+ pc,
+ ar,
+ hr,
+ grx,
+ z_flag,
+ n_flag,
+ o_flag,
+ l_flag,
+ c_flag,
+ pm,
+ alu,
+ asr,
+ bus,
+ ]
for module in ALLTHEMODULES:
self.add_module(module)
self.micro_memory = uM
-
self.lambdas = {}
def should_halt(self) -> bool:
@@ -223,6 +298,7 @@ class MIA_CPU(Processor):
def launch_gui(self):
from qtpy import QtCore
from qtpy.QtWidgets import QApplication
+
QApplication.setAttribute(QtCore.Qt.AA_EnableHighDpiScaling)
app = QApplication(sys.argv)
self.load_state_from_file("mia_uppg3.txt")
@@ -239,22 +315,24 @@ class MIA_CPU(Processor):
grx = self.get_module("GRx")
bus_signal_pairs = [
- (asr.input_s, None),
- (ir.from_bus_s, ir.to_bus_s),
- (pm.input_s, pm.output_s),
- (None, None),
- (pc.bus_input_s, pc.bus_output_s),
- (None, None),
- (alu.input_signal_b, None),
- (None, None),
- (None, ar.output_s),
- (None, None),
- (hr.input_s, hr.output_s),
- (None, None),
- (grx.from_bus , grx.to_bus)]
-
- gui.addModuleGraphicsItem(BusGraphicsItem(self.get_module("Bus"),
- bus_signal_pairs))
+ (asr.input_s, None),
+ (ir.from_bus_s, ir.to_bus_s),
+ (pm.input_s, pm.output_s),
+ (None, None),
+ (pc.bus_input_s, pc.bus_output_s),
+ (None, None),
+ (alu.input_signal_b, None),
+ (None, None),
+ (None, ar.output_s),
+ (None, None),
+ (hr.input_s, hr.output_s),
+ (None, None),
+ (grx.from_bus, grx.to_bus),
+ ]
+
+ gui.addModuleGraphicsItem(
+ BusGraphicsItem(self.get_module("Bus"), bus_signal_pairs)
+ )
gui.addModuleGraphicsItem(uPcGraphicsItem(self.get_module("uPC")))
gui.addModuleGraphicsItem(SupcGraphicsItem(self.get_module("SuPC")))
gui.addModuleGraphicsItem(PcGraphicsItem(self.get_module("PC")))
@@ -281,7 +359,7 @@ class MIA_CPU(Processor):
gui.addAllSignals()
gui.show()
- #gui.loadLayoutFromFile("mia_layout")
+ # gui.loadLayoutFromFile("mia_layout")
app.exec()
def launch_cli(self):
@@ -293,9 +371,7 @@ class MIA_CPU(Processor):
cli.run()
-
if __name__ == "__main__":
-
# this is bad terminal code, but who cares
cpu = MIA_CPU()
flag = None
diff --git a/src/simudator/processor/mia/mia_bus_connect.py b/src/simudator/processor/mia/mia_bus_connect.py
index 95b2a555004793644b49acf69b0122a43a4482d7..caf7fe303c30b5b8c9ed5a71b5281882d4303036 100644
--- a/src/simudator/processor/mia/mia_bus_connect.py
+++ b/src/simudator/processor/mia/mia_bus_connect.py
@@ -3,14 +3,13 @@ from __future__ import annotations
from simudator.core.signal import Signal
-class MiaBusConnector():
+class MiaBusConnector:
"""
Inherited by modules that are connected to a bus in the MIA archtecture.
Has logic for controlling when to read and write to bus.
"""
def __init__(self, bus_control: Signal, bus_id: int = 0) -> None:
-
# init the name
self.bus_id = bus_id
self.bus_control_s = bus_control
diff --git a/src/simudator/processor/mia/mia_grx.py b/src/simudator/processor/mia/mia_grx.py
index b897a6a946350c6989ce16d031e592b4aed602cd..75379bbcc82278e98c322f78cd6bfc292aef1efd 100644
--- a/src/simudator/processor/mia/mia_grx.py
+++ b/src/simudator/processor/mia/mia_grx.py
@@ -14,18 +14,19 @@ class GRX(Module, MiaBusConnector):
registers should be indexed by the GRx bits or the M bits.
"""
- def __init__(self,
- to_bus: Signal,
- from_bus: Signal,
- bus_control: Signal,
- grx_control: Signal,
- m_control: Signal,
- s_control: Signal,
- bus_id: int,
- name="GRx",
- registers=[0 for _ in range(4)],
- bit_length=16) -> None:
-
+ def __init__(
+ self,
+ to_bus: Signal,
+ from_bus: Signal,
+ bus_control: Signal,
+ grx_control: Signal,
+ m_control: Signal,
+ s_control: Signal,
+ bus_id: int,
+ name="GRx",
+ registers=[0 for _ in range(4)],
+ bit_length=16,
+ ) -> None:
# Set connection to/from bus and bus_id
MiaBusConnector.__init__(self, bus_control, bus_id)
@@ -65,8 +66,7 @@ class GRX(Module, MiaBusConnector):
elif s_control_value == 0b1:
grx_index = self.m_control_s.get_value()
else:
- raise ValueError("The value of the s signal"
- "must be 0b0 or 0b1 !!!")
+ raise ValueError("The value of the s signal" "must be 0b0 or 0b1 !!!")
self.registers[grx_index] = self.from_bus.get_value()
@@ -85,8 +85,7 @@ class GRX(Module, MiaBusConnector):
elif s_control_value == 0b1:
grx_index = self.m_control_s.get_value()
else:
- raise ValueError("The value of the s signal"
- "must be 0b0 or 0b1 !!!")
+ raise ValueError("The value of the s signal" "must be 0b0 or 0b1 !!!")
self.to_bus.update_value(self.registers[grx_index])
else:
@@ -101,17 +100,17 @@ class GRX(Module, MiaBusConnector):
These states are changable via set_states.
"""
state = {
- "name": self.name,
- "bit_length": self.bit_length,
- "registers": self.registers[:],
- }
+ "name": self.name,
+ "bit_length": self.bit_length,
+ "registers": self.registers[:],
+ }
return state
def get_gui_state(self) -> dict:
state = {
- "name": self.name,
- "registers": self.registers[:],
- }
+ "name": self.name,
+ "registers": self.registers[:],
+ }
return state
def set_state(self, state: dict[str, Any]):
@@ -153,30 +152,39 @@ class GRX(Module, MiaBusConnector):
self.reset()
lines = state_string.split("\n")
for line in lines:
- if line: # last line is empty from split with \n
+ if line: # last line is empty from split with \n
line_data = line.split(": ")
adress = int(line_data[0], 16)
value = int(line_data[1], 16)
self.registers[adress] = value
def print_module(self):
- print("", self.name, "\n -----",
- "\n bus_id: ", self.bus_id,
- "\n bit_length: ", self.bit_length,
- "\n GR0: ", hex(self.registers[0]),
- "\n GR1: ", hex(self.registers[1]),
- "\n GR2: ", hex(self.registers[2]),
- "\n GR3: ", hex(self.registers[3]),
- )
+ print(
+ "",
+ self.name,
+ "\n -----",
+ "\n bus_id: ",
+ self.bus_id,
+ "\n bit_length: ",
+ self.bit_length,
+ "\n GR0: ",
+ hex(self.registers[0]),
+ "\n GR1: ",
+ hex(self.registers[1]),
+ "\n GR2: ",
+ hex(self.registers[2]),
+ "\n GR3: ",
+ hex(self.registers[3]),
+ )
def get_input_signals(self) -> list[Signal]:
return [
- self.bus_control_s,
- self.from_bus,
- self.m_control_s,
- self.s_control_s,
- self.grx_control_s
- ]
+ self.bus_control_s,
+ self.from_bus,
+ self.m_control_s,
+ self.s_control_s,
+ self.grx_control_s,
+ ]
def get_output_signals(self) -> list[Signal]:
return [self.to_bus]
diff --git a/src/simudator/processor/mia/mia_memory.py b/src/simudator/processor/mia/mia_memory.py
index 709577537907823b9b0d518fb76de623ef77e554..cfac7f1414e04909c5cea78a508ecfa57d555176 100644
--- a/src/simudator/processor/mia/mia_memory.py
+++ b/src/simudator/processor/mia/mia_memory.py
@@ -10,21 +10,31 @@ class MiaMemory(MiaBusConnector, Memory):
arbitrary size and supports opperations that read and write
to/from the mia bus.
"""
- def __init__(self,
- input_signal: Signal,
- output_signal: Signal,
- adress_signal: Signal,
- bus_control_s: Signal,
- size: int = 1,
- bus_id: int = 0,
- value_padding: int = 2,
- adress_padding: int = 2,
- name: str = "PM") -> None:
+
+ def __init__(
+ self,
+ input_signal: Signal,
+ output_signal: Signal,
+ adress_signal: Signal,
+ bus_control_s: Signal,
+ size: int = 1,
+ bus_id: int = 0,
+ value_padding: int = 2,
+ adress_padding: int = 2,
+ name: str = "PM",
+ ) -> None:
MiaBusConnector.__init__(self, bus_control_s, bus_id)
- Memory.__init__(self, input_signal, output_signal, Signal(None),
- adress_signal, size, name = name,
- value_padding = value_padding,
- adress_padding = adress_padding)
+ Memory.__init__(
+ self,
+ input_signal,
+ output_signal,
+ Signal(None),
+ adress_signal,
+ size,
+ name=name,
+ value_padding=value_padding,
+ adress_padding=adress_padding,
+ )
self.bus_control_s.add_destination(self)
def update_register(self) -> None:
@@ -68,7 +78,7 @@ class MiaMemory(MiaBusConnector, Memory):
self.reset()
lines = state_string.split("\n")
for line in lines:
- if line: # last line is empty from split with \n
+ if line: # last line is empty from split with \n
line_data = line.split(": ")
adress = int(line_data[0], 16)
value = int(line_data[1], 16)
@@ -76,10 +86,10 @@ class MiaMemory(MiaBusConnector, Memory):
def get_input_signals(self) -> list[Signal]:
return [
- self.bus_control_s,
- self.input_s,
- self.adress_s,
- ]
+ self.bus_control_s,
+ self.input_s,
+ self.adress_s,
+ ]
def get_output_signals(self) -> list[Signal]:
return [self.output_s]
diff --git a/src/simudator/processor/mia/micro_memory.py b/src/simudator/processor/mia/micro_memory.py
index 578d8fc53492f19ec5b518cffbb7dc16d421847c..1cee0c08fd6d49b2e48daaa0b9e60c881332b9df 100644
--- a/src/simudator/processor/mia/micro_memory.py
+++ b/src/simudator/processor/mia/micro_memory.py
@@ -18,26 +18,27 @@ class MicroMemory(Module):
cycle.
"""
- def __init__(self,
- alu: Signal,
- bus_control: Signal,
- bus_constant: Signal,
- s: Signal,
- p: Signal,
- lc_control: Signal,
- lc_uadr: Signal,
- upc: Signal,
- upc_control: Signal,
- upc_uadr: Signal,
- z_flag: Signal,
- n_flag: Signal,
- c_flag: Signal,
- o_flag: Signal,
- l_flag: Signal,
- name: str = "uM",
- adress_padding: int = 2,
- value_padding: int = 7,
- ) -> None:
+ def __init__(
+ self,
+ alu: Signal,
+ bus_control: Signal,
+ bus_constant: Signal,
+ s: Signal,
+ p: Signal,
+ lc_control: Signal,
+ lc_uadr: Signal,
+ upc: Signal,
+ upc_control: Signal,
+ upc_uadr: Signal,
+ z_flag: Signal,
+ n_flag: Signal,
+ c_flag: Signal,
+ o_flag: Signal,
+ l_flag: Signal,
+ name: str = "uM",
+ adress_padding: int = 2,
+ value_padding: int = 7,
+ ) -> None:
"""
:param alu: Control signal specifying the ALU operand.
:type alu: Signal
@@ -115,7 +116,7 @@ class MicroMemory(Module):
self.o_flag_val = 0
self.l_flag_val = 0
self.memory = [0 for i in range(128)]
- self.halt = False # Used for signalling a HALT
+ self.halt = False # Used for signalling a HALT
# paddings to ensure saving to file has the correct format
self.adress_padding = adress_padding
@@ -186,7 +187,7 @@ class MicroMemory(Module):
self.lc_control_s.update_value(0b01)
case 0b10:
self.lc_control_s.update_value(0b10)
- #fb_field = 0b1001 # Ignores actual FB field
+ # fb_field = 0b1001 # Ignores actual FB field
case 0b11:
self.lc_control_s.update_value(0b11)
self.lc_uadr_s.update_value(uadr_field & 0b01111111)
@@ -276,30 +277,32 @@ class MicroMemory(Module):
self.halt = state["halt"]
def get_input_signals(self) -> [Signal]:
- return [self.upc_s,
- self.z_flag_s,
- self.n_flag_s,
- self.c_flag_s,
- self.o_flag_s,
- self.l_flag_s]
+ return [
+ self.upc_s,
+ self.z_flag_s,
+ self.n_flag_s,
+ self.c_flag_s,
+ self.o_flag_s,
+ self.l_flag_s,
+ ]
def get_uPC_signal(self):
return self.upc_s
def get_output_signals(self) -> [Signal]:
- return[
- self.alu_s,
- self.bus_control_s,
- self.s_s,
- self.p_s,
- self.lc_control_s,
- self.upc_control_s,
- self.bus_constant_s,
- self.upc_uadr_s,
- self.lc_uadr_s]
+ return [
+ self.alu_s,
+ self.bus_control_s,
+ self.s_s,
+ self.p_s,
+ self.lc_control_s,
+ self.upc_control_s,
+ self.bus_constant_s,
+ self.upc_uadr_s,
+ self.lc_uadr_s,
+ ]
def reset(self) -> None:
-
self.curr_instr = 0
self.z_flag_val = 0
self.n_flag_val = 0
@@ -307,7 +310,7 @@ class MicroMemory(Module):
self.o_flag_val = 0
self.l_flag_val = 0
self.memory = [0 for i in range(128)]
- self.halt = False # Used for signalling a HALT
+ self.halt = False # Used for signalling a HALT
def load_from_str(self, state_string) -> None:
"""
@@ -331,7 +334,7 @@ class MicroMemory(Module):
lines = state_string.split("\n")
for line in lines:
- if line: # last line is empty from split with \n
+ if line: # last line is empty from split with \n
line_data = line.split(": ")
adress = int(line_data[0], 16)
value = int(line_data[1], 16)
diff --git a/src/simudator/processor/mia/micro_pc.py b/src/simudator/processor/mia/micro_pc.py
index f95e1d426f7f25852c6ade71d5a88bdf9af2d1d0..1470c6edec5e254279d50037e1adca75c90d76c4 100644
--- a/src/simudator/processor/mia/micro_pc.py
+++ b/src/simudator/processor/mia/micro_pc.py
@@ -11,16 +11,18 @@ class MicroPC(Module):
to read from or write to.
"""
- def __init__(self,
- control_signal: Signal,
- from_k1: Signal,
- from_k2: Signal,
- to_supc: Signal,
- from_supc: Signal,
- to_um: Signal,
- from_um: Signal,
- bit_length: int = 8,
- name: str = "uPC") -> None:
+ def __init__(
+ self,
+ control_signal: Signal,
+ from_k1: Signal,
+ from_k2: Signal,
+ to_supc: Signal,
+ from_supc: Signal,
+ to_um: Signal,
+ from_um: Signal,
+ bit_length: int = 8,
+ name: str = "uPC",
+ ) -> None:
super().__init__(name)
self.value = 0
@@ -78,9 +80,9 @@ class MicroPC(Module):
def get_gui_state(self) -> dict:
state = {
- "name": self.name,
- "value": self.value,
- }
+ "name": self.name,
+ "value": self.value,
+ }
return state
def set_state(self, state: dict) -> None:
@@ -106,24 +108,23 @@ class MicroPC(Module):
def load_from_str(self, state_string):
string_pair = state_string.split(": ")
- #TODO: Maybe check if it starts with value: ?
+ # TODO: Maybe check if it starts with value: ?
self.value = int(string_pair[1], 16)
def print_module(self) -> None:
- print("", self.name, "\n -----",
- "\n value: ", hex(self.value))
+ print("", self.name, "\n -----", "\n value: ", hex(self.value))
def get_input_signals(self) -> list[Signal]:
return [
- self.control_signal,
- self.from_k1,
- self.from_k2,
- self.from_supc,
- self.from_um,
- ]
+ self.control_signal,
+ self.from_k1,
+ self.from_k2,
+ self.from_supc,
+ self.from_um,
+ ]
def get_output_signals(self) -> list[Signal]:
return [
- self.to_supc,
- self.to_um,
- ]
+ self.to_supc,
+ self.to_um,
+ ]
diff --git a/src/simudator/processor/mia/pc.py b/src/simudator/processor/mia/pc.py
index ceb8b1429390a54320a8265cda6a26f8b7089136..39100e2385bda8f7f021c441dacd4f2425633ec1 100644
--- a/src/simudator/processor/mia/pc.py
+++ b/src/simudator/processor/mia/pc.py
@@ -16,16 +16,16 @@ class PC(Module, MiaBusConnector):
value on the bus. If both are true it does nothing.
"""
- def __init__(self,
- p: Signal,
- bus_input: Signal,
- bus_output: Signal,
- bus_control: Signal,
- bus_id: int,
- name="PC",
- value=0
- ) -> None:
-
+ def __init__(
+ self,
+ p: Signal,
+ bus_input: Signal,
+ bus_output: Signal,
+ bus_control: Signal,
+ bus_id: int,
+ name="PC",
+ value=0,
+ ) -> None:
MiaBusConnector.__init__(self, bus_control, bus_id)
Module.__init__(self, name)
@@ -70,7 +70,7 @@ class PC(Module, MiaBusConnector):
if self.read_from_bus():
# Read the 8 lowest bits from the bus
- self.value = self.bus_input_s.get_value() & 0xff
+ self.value = self.bus_input_s.get_value() & 0xFF
if self.increase_by_one:
self.value += 1
@@ -78,8 +78,7 @@ class PC(Module, MiaBusConnector):
def update_logic(self) -> None:
self.output_register()
-
- def get_state(self) -> dict[str: Any]:
+ def get_state(self) -> dict[str:Any]:
"""
Returns a dict of the program counter state.
These states are changable via set_states.
@@ -96,12 +95,12 @@ class PC(Module, MiaBusConnector):
def get_gui_state(self) -> dict:
state = {
- "name": self.name,
- "value": self.value,
- }
+ "name": self.name,
+ "value": self.value,
+ }
return state
- def set_state(self, state: dict[str: Any]) -> None:
+ def set_state(self, state: dict[str:Any]) -> None:
"""
Sets the program counter state to one given in dict.
"""
@@ -128,18 +127,14 @@ class PC(Module, MiaBusConnector):
def load_from_str(self, state_string):
string_pair = state_string.split(": ")
- #TODO: Maybe check if it starts with value: ?
+ # TODO: Maybe check if it starts with value: ?
self.value = int(string_pair[1], 16)
def print_module(self) -> None:
- print("", self.name, "\n -----",
- "\n value: ", hex(self.value))
+ print("", self.name, "\n -----", "\n value: ", hex(self.value))
def get_input_signals(self) -> list[Signal]:
- return [
- self.bus_input_s,
- self.p
- ]
+ return [self.bus_input_s, self.p]
def get_output_signals(self) -> list[Signal]:
return [self.bus_output_s]
diff --git a/src/simudator/processor/simple/simple.py b/src/simudator/processor/simple/simple.py
index d75fd8d2b7586c549b24801f0f07b26d97351b37..7b66364741fab4904a2eb9d0cf6c41ba42c76587 100644
--- a/src/simudator/processor/simple/simple.py
+++ b/src/simudator/processor/simple/simple.py
@@ -33,18 +33,19 @@ class SIMPLE_CPU(Processor):
empty_input = Signal(self, "empty_input", value=None)
empty_output = Signal(self, "empty_output", value=None)
- self.memory = Memory(mem_input, mem_output,mem_control,mem_adress, 10)
+ self.memory = Memory(mem_input, mem_output, mem_control, mem_adress, 10)
self.input_register = Register(empty_input, mem_input, name="Input Reg")
- self.output_register = Register(mem_output,
- empty_output, name="Output Reg")
- self.control_register = Register(empty_input,
- mem_control, name="Control Reg")
- self.adress_register = Register(empty_input,
- mem_adress, name="Adress Reg")
-
-
- ALLTHEMODULES = [self.memory, self.input_register, self.output_register,
- self.control_register, self.adress_register]
+ self.output_register = Register(mem_output, empty_output, name="Output Reg")
+ self.control_register = Register(empty_input, mem_control, name="Control Reg")
+ self.adress_register = Register(empty_input, mem_adress, name="Adress Reg")
+
+ ALLTHEMODULES = [
+ self.memory,
+ self.input_register,
+ self.output_register,
+ self.control_register,
+ self.adress_register,
+ ]
for module in ALLTHEMODULES:
self.add_module(module)
@@ -72,9 +73,7 @@ class SIMPLE_CPU(Processor):
cli.run()
-
if __name__ == "__main__":
-
# this is bad terminal code, but who cares
cpu = SIMPLE_CPU()
flag = None
diff --git a/test/test.py b/test/test.py
index 7cad483ebdaca5ba23f2309a9410210da71fdfad..5303f448bd5cc5f0bbdd744e7c17f88725e20e59 100644
--- a/test/test.py
+++ b/test/test.py
@@ -1,6 +1,7 @@
+from simudator.cli.cli import CLI
from simudator.core.processor import Processor
from simudator.core.signal import Signal
-from simudator.cli.cli import CLI
+
def test_name():
return
@@ -11,15 +12,18 @@ def test_name():
assert s._name == "name"
print("All tests passed!")
+
def test_cli():
return
cpu = Processor()
cli = CLI(cpu)
cli.run()
+
def test_PC():
return
+
if __name__ == "__main__":
test_name()
- # test_cli()
+ # test_cli()
diff --git a/test/test_core/test_demux.py b/test/test_core/test_demux.py
index 991a5e301019f07283bd68a50f7b920d3bdc24cc..acf92510f17faaf59c475e6426384214ac68eec8 100644
--- a/test/test_core/test_demux.py
+++ b/test/test_core/test_demux.py
@@ -1,6 +1,7 @@
from simudator.core.modules.demux import Demux
-from simudator.core.signal import Signal
from simudator.core.processor import Processor
+from simudator.core.signal import Signal
+
def test_default_name():
cpu = Processor()
@@ -12,6 +13,7 @@ def test_default_name():
assert demux.name == "demux"
+
def test_name():
cpu = Processor()
from_demux = Signal(cpu)
@@ -22,6 +24,7 @@ def test_name():
assert demux.name == "Demux"
+
def test_get_state():
cpu = Processor()
from_demux = Signal(cpu)
@@ -37,6 +40,7 @@ def test_get_state():
assert state["bit_length"] == 5
assert state["mask"] == 31
+
def test_set_state():
state = dict()
state["name"] = "Demux"
@@ -60,7 +64,6 @@ def test_set_state():
def test_writing_to_output():
-
# Init required modules
cpu = Processor()
from_demux_s = Signal(cpu)
@@ -69,10 +72,10 @@ def test_writing_to_output():
output_2_s = Signal(cpu)
output_3_s = Signal(cpu)
outputs = [
- output_1_s,
- output_2_s,
- output_3_s,
- ]
+ output_1_s,
+ output_2_s,
+ output_3_s,
+ ]
bit_length = 5
demux = Demux(from_demux_s, bit_length, input_s, outputs)
@@ -80,7 +83,7 @@ def test_writing_to_output():
cpu.add_module(demux)
# update the control signal and the input signal, the 'correct'
- # output signal should receive the input signal, the others
+ # output signal should receive the input signal, the others
# should not be affected
from_demux_s.update_value(0)
outputs[0].update_value(0)
@@ -93,17 +96,16 @@ def test_writing_to_output():
assert outputs[1].get_value() == 0
assert outputs[2].get_value() == 0
-
-def test_throw_away_bits():
+def test_throw_away_bits():
# Init required modules
cpu = Processor()
from_demux_s = Signal(cpu)
input_s = Signal(cpu)
output_1_s = Signal(cpu)
outputs = [
- output_1_s,
- ]
+ output_1_s,
+ ]
bit_length = 2
demux = Demux(from_demux_s, bit_length, input_s, outputs)
@@ -111,11 +113,10 @@ def test_throw_away_bits():
cpu.add_module(demux)
# update the control signal and the input signal value,
- # the output signal should receive the value 3 since the
+ # the output signal should receive the value 3 since the
# mux only has two bits and it is receiving the value 1111
from_demux_s.update_value(0)
input_s.update_value(15)
cpu.do_tick()
assert outputs[0].get_value() == 3
-
diff --git a/test/test_core/test_memory.py b/test/test_core/test_memory.py
index 246d26565480fc9643d5f1b71c0f2e4369d635a3..30b0533041f7a2c5da72c543b198e3e0e71dbc7b 100644
--- a/test/test_core/test_memory.py
+++ b/test/test_core/test_memory.py
@@ -5,17 +5,17 @@ from simudator.core.signal import Signal
def test_memory():
cpu = Processor()
- input_s = Signal(cpu, value = 0)
- output_s = Signal(cpu, value = 0)
- control_s = Signal(cpu, value = 0)
- adress_s = Signal(cpu, value = 0)
+ input_s = Signal(cpu, value=0)
+ output_s = Signal(cpu, value=0)
+ control_s = Signal(cpu, value=0)
+ adress_s = Signal(cpu, value=0)
memory = Memory(input_s, output_s, control_s, adress_s, 2)
cpu.add_module(memory)
# Test that the memory is not written to before a new clock pulse
control_s.update_value(1)
input_s.update_value(1)
- memory.update_logic() # Simulate update at end of current clock pulse
+ memory.update_logic() # Simulate update at end of current clock pulse
assert output_s.get_value() == 0
# Test that the memory has been written to after the new clock pulse
@@ -25,11 +25,10 @@ def test_memory():
# Test that reading from the adress does not write to it
control_s.update_value(0)
input_s.update_value(0)
- memory.update_logic() # Simulate update at the end of current clock pulse
+ memory.update_logic() # Simulate update at the end of current clock pulse
cpu.do_tick()
assert output_s.get_value() == 1
-
# Test that reading from another adress works
adress_s.update_value(1)
memory.update_logic()
diff --git a/test/test_core/test_mux.py b/test/test_core/test_mux.py
index 948bd366d7c96383291b242af18f1803a1c9d1e0..7dab6d3630af58eef3411ca0f7763b6fb839bf09 100644
--- a/test/test_core/test_mux.py
+++ b/test/test_core/test_mux.py
@@ -1,6 +1,7 @@
from simudator.core.modules.mux import Mux
-from simudator.core.signal import Signal
from simudator.core.processor import Processor
+from simudator.core.signal import Signal
+
def test_default_name():
cpu = Processor()
@@ -12,6 +13,7 @@ def test_default_name():
assert mux.name == "mux"
+
def test_name():
cpu = Processor()
to_mux = Signal(cpu)
@@ -22,6 +24,7 @@ def test_name():
assert mux.name == "Mux"
+
def test_get_state():
cpu = Processor()
to_mux = Signal(cpu)
@@ -37,6 +40,7 @@ def test_get_state():
assert state["bit_length"] == 5
assert state["mask"] == 31
+
def test_set_state():
state = dict()
state["name"] = "Mux"
@@ -58,8 +62,8 @@ def test_set_state():
assert mux.bit_length == 2
assert mux.mask == 3
+
def test_writing_to_output():
-
# Init required modules
cpu = Processor()
to_mux_s = Signal(cpu)
@@ -80,8 +84,8 @@ def test_writing_to_output():
assert output_s.get_value() == 5
-def test_throw_away_bits():
+def test_throw_away_bits():
# Init required modules
cpu = Processor()
to_mux_s = Signal(cpu)
@@ -95,11 +99,10 @@ def test_throw_away_bits():
cpu.add_module(mux)
# update the control signal and the input signal value,
- # the output signal should receive the value 3 since the
+ # the output signal should receive the value 3 since the
# mux only has two bits and it is receiving the value 1111
to_mux_s.update_value(0)
inputs[0].update_value(15)
cpu.do_tick()
assert output_s.get_value() == 3
-
diff --git a/test/test_core/test_processor.py b/test/test_core/test_processor.py
index a9c4c136835d2fde4369447817d2270e2070b812..e619636f3f43b9c7b017e744087a6600f1120f47 100644
--- a/test/test_core/test_processor.py
+++ b/test/test_core/test_processor.py
@@ -2,8 +2,8 @@ from simudator.core.processor import Processor
TEST_PATH = "test/test_core/processor_state_test.txt"
-class Dummymodule():
+class Dummymodule:
def __init__(self, name):
self.name = name
self.string = None
diff --git a/test/test_core/test_register.py b/test/test_core/test_register.py
index 7ef8fc0da27cb7c12460a471eeb9dd07a1c3809e..ae6f51127da4fb86673387e86e9abb1b2b83d000 100644
--- a/test/test_core/test_register.py
+++ b/test/test_core/test_register.py
@@ -1,6 +1,7 @@
from simudator.core.modules.register import Register
-from simudator.core.signal import Signal
from simudator.core.processor import Processor
+from simudator.core.signal import Signal
+
def test_default_name():
cpu = Processor()
@@ -8,12 +9,14 @@ def test_default_name():
register = Register(s, s, 8)
assert register.name == "Register"
+
def test_name():
cpu = Processor()
s = Signal(cpu)
register = Register(s, s, 13, "reg")
assert register.name == "reg"
+
def test_set_state():
cpu = Processor()
s = Signal(cpu)
@@ -25,6 +28,7 @@ def test_set_state():
assert register.name == "Reg"
assert register.value == 14
+
def test_get_state():
cpu = Processor()
s = Signal(cpu)
@@ -34,8 +38,8 @@ def test_get_state():
assert state["name"] == "register"
assert state["value"] == 13
-def test_signal_propagation():
+def test_signal_propagation():
# Modules needed to run the test
cpu = Processor()
input_s = Signal(cpu)
@@ -48,5 +52,3 @@ def test_signal_propagation():
cpu.do_tick()
assert register.value == 10
-
-
diff --git a/test/test_mia/test_alu.py b/test/test_mia/test_alu.py
index f637dccb620be08c6c2795e93887223c22585f15..b053502077bc1664b913a0a551db938085c99303 100644
--- a/test/test_mia/test_alu.py
+++ b/test/test_mia/test_alu.py
@@ -6,61 +6,67 @@ cpu = Processor()
input_signal_a = Signal(cpu)
input_signal_b = Signal(cpu)
input_signal_hr = Signal(cpu)
-control_signal= Signal(cpu)
-output_signal= Signal(cpu)
-hr_signal= Signal(cpu)
-z_signal= Signal(cpu)
-n_signal= Signal(cpu)
-o_signal= Signal(cpu)
-c_signal= Signal(cpu)
-alu = ALU("alu",
- input_signal_a,
- input_signal_b,
- input_signal_hr,
- control_signal,
- output_signal,
- hr_signal,
- z_signal,
- n_signal,
- o_signal,
- c_signal)
+control_signal = Signal(cpu)
+output_signal = Signal(cpu)
+hr_signal = Signal(cpu)
+z_signal = Signal(cpu)
+n_signal = Signal(cpu)
+o_signal = Signal(cpu)
+c_signal = Signal(cpu)
+alu = ALU(
+ "alu",
+ input_signal_a,
+ input_signal_b,
+ input_signal_hr,
+ control_signal,
+ output_signal,
+ hr_signal,
+ z_signal,
+ n_signal,
+ o_signal,
+ c_signal,
+)
cpu.add_module(alu)
-def test_int_binary_converter():
- #test int to binary
+def test_int_binary_converter():
+ # test int to binary
assert alu.int_to_bin(0) == [0 for i in range(alu.WORD_LENGTH)]
- assert alu.int_to_bin(1) == [0]*(alu.WORD_LENGTH-1) + [1]
- assert alu.int_to_bin(32767) == [0] + [1]*(alu.WORD_LENGTH-1)
- assert alu.int_to_bin(9) == [0]*(alu.WORD_LENGTH-4) + [1, 0, 0, 1]
+ assert alu.int_to_bin(1) == [0] * (alu.WORD_LENGTH - 1) + [1]
+ assert alu.int_to_bin(32767) == [0] + [1] * (alu.WORD_LENGTH - 1)
+ assert alu.int_to_bin(9) == [0] * (alu.WORD_LENGTH - 4) + [1, 0, 0, 1]
# test binary to int
assert alu.bin_to_int(alu.int_to_bin(15)) == 15
assert alu.bin_to_int(alu.int_to_bin(0)) == 0
- assert alu.bin_to_int(alu.int_to_bin(2**16)) == 2**16-1
+ assert alu.bin_to_int(alu.int_to_bin(2**16)) == 2**16 - 1
assert alu.bin_to_int(alu.int_to_bin(3576)) == 3576
assert alu.bin_to_int([0 for i in range(alu.WORD_LENGTH)]) == 0
- assert alu.bin_to_int([0]*(alu.WORD_LENGTH-1) + [1]) == 1
- assert alu.bin_to_int([1 for i in range(alu.WORD_LENGTH)]) == 2**16-1
- assert alu.bin_to_int([0] + [1]*(alu.WORD_LENGTH-1)) == 32767
- assert alu.bin_to_int([0]*(alu.WORD_LENGTH-4) + [1, 0, 0, 1]) == 9
+ assert alu.bin_to_int([0] * (alu.WORD_LENGTH - 1) + [1]) == 1
+ assert alu.bin_to_int([1 for i in range(alu.WORD_LENGTH)]) == 2**16 - 1
+ assert alu.bin_to_int([0] + [1] * (alu.WORD_LENGTH - 1)) == 32767
+ assert alu.bin_to_int([0] * (alu.WORD_LENGTH - 4) + [1, 0, 0, 1]) == 9
-def test_ones_complement():
+def test_ones_complement():
# test bitwise not
- assert alu.ones_complement(0) == 2**16-1
- assert alu.ones_complement(1) == 2**16-1-1
- assert alu.ones_complement(2) == 2**16-1-2
- assert alu.ones_complement(300) == 2**16-1-300
+ assert alu.ones_complement(0) == 2**16 - 1
+ assert alu.ones_complement(1) == 2**16 - 1 - 1
+ assert alu.ones_complement(2) == 2**16 - 1 - 2
+ assert alu.ones_complement(300) == 2**16 - 1 - 300
+
def test_negative_bin():
assert alu.bin_to_int_twocomp(alu.int_to_negative_bin(0)) == 0
assert alu.bin_to_int_twocomp(alu.int_to_negative_bin(10)) == -10
assert alu.bin_to_int_twocomp(alu.int_to_negative_bin(1337)) == -1337
- assert alu.bin_to_int_twocomp(alu.int_to_negative_bin(2**15-1)) == -(2**15-1)
- assert alu.bin_to_int_twocomp(alu.int_to_negative_bin(2**16-1)) == 1
- assert alu.bin_to_int_twocomp(alu.int_to_negative_bin(2**16-10)) == 10
- assert alu.bin_to_int_twocomp(alu.int_to_negative_bin(2**16-4567)) == 4567
+ assert alu.bin_to_int_twocomp(alu.int_to_negative_bin(2**15 - 1)) == -(
+ 2**15 - 1
+ )
+ assert alu.bin_to_int_twocomp(alu.int_to_negative_bin(2**16 - 1)) == 1
+ assert alu.bin_to_int_twocomp(alu.int_to_negative_bin(2**16 - 10)) == 10
+ assert alu.bin_to_int_twocomp(alu.int_to_negative_bin(2**16 - 4567)) == 4567
+
def test_add_numbers():
# test binary sum
@@ -80,15 +86,14 @@ def test_add_numbers():
assert alu.o_value == 0
assert alu.c_value == 0
-
- assert alu.add_numbers(1, 2**16-1, True) == 0
+ assert alu.add_numbers(1, 2**16 - 1, True) == 0
assert alu.z_value == 1
assert alu.n_value == 0
assert alu.o_value == 0
assert alu.c_value == 1
-def test_binary_diff():
+def test_binary_diff():
assert alu.subtract_numbers(1, 1, True) == 0
assert alu.z_value == 1
assert alu.n_value == 0
@@ -99,12 +104,12 @@ def test_binary_diff():
assert alu.n_value == 1
assert alu.o_value == 0
assert alu.c_value == 0
- assert alu.subtract_numbers(0xa100, 0xa010, True) == (0xa100 - 0xa010)
+ assert alu.subtract_numbers(0xA100, 0xA010, True) == (0xA100 - 0xA010)
assert alu.z_value == 0
assert alu.n_value == 0
assert alu.o_value == 0
assert alu.c_value == 1
- assert alu.subtract_numbers(0xa010, 0xa100, True) == 0xffff+1 + (0xa010 - 0xa100)
+ assert alu.subtract_numbers(0xA010, 0xA100, True) == 0xFFFF + 1 + (0xA010 - 0xA100)
assert alu.z_value == 0
assert alu.n_value == 1
assert alu.o_value == 0
@@ -115,8 +120,8 @@ def test_binary_diff():
assert alu.subtract_numbers(500, 2, False) == 498
assert alu.subtract_numbers(10, 2, False) == 8
-def test_and_numbers():
+def test_and_numbers():
assert alu.and_numbers(1, 2) == 0
assert alu.and_numbers(1, 1) == 1
assert alu.and_numbers(3, 1) == 1
@@ -125,15 +130,15 @@ def test_and_numbers():
assert alu.and_numbers(20, 0) == 0
assert alu.and_numbers(5, 0) == 0
-def test_or_numbers():
+def test_or_numbers():
assert alu.or_numbers(1, 2) == 3
assert alu.or_numbers(1, 1) == 1
assert alu.or_numbers(0, 0) == 0
assert alu.or_numbers(20, 0) == 20
-def test_binary_logical_left_shift():
+def test_binary_logical_left_shift():
assert alu.logical_left_shift(0b01) == 0b10
assert alu.c_value == 0
assert alu.logical_left_shift(0b11) == 0b110
@@ -143,8 +148,8 @@ def test_binary_logical_left_shift():
assert alu.logical_left_shift(0b1000000000000000) == 0b0
assert alu.c_value == 1
-def test_arithmetic_right_shift():
+def test_arithmetic_right_shift():
assert alu.arithmetic_right_shift(0) == 0
assert alu.c_value == 0
assert alu.arithmetic_right_shift(1) == 0
@@ -156,6 +161,7 @@ def test_arithmetic_right_shift():
assert alu.arithmetic_right_shift(0b0111111111111111) == 0b0011111111111111
assert alu.c_value == 1
+
def test_logical_right_shift():
assert alu.logical_right_shift(0) == 0
assert alu.c_value == 0
@@ -164,13 +170,14 @@ def test_logical_right_shift():
assert alu.logical_right_shift(2) == 1
assert alu.c_value == 0
+
def test_rotate_left():
assert alu.left_rotate(0) == 0
assert alu.c_value == 0
assert alu.left_rotate(1) == 2
-def test_signals():
+def test_signals():
# Test just out
control_signal.update_value(1)
input_signal_b.update_value(15)
@@ -204,7 +211,7 @@ def test_signals():
input_signal_a.update_value(5)
control_signal.update_value(5)
cpu.do_tick()
- assert output_signal.get_value() == 2**16-2
+ assert output_signal.get_value() == 2**16 - 2
assert z_signal.get_value() == 0
assert n_signal.get_value() == 1
assert o_signal.get_value() == 0
@@ -221,8 +228,8 @@ def test_signals():
assert o_signal.get_value() == 0
assert c_signal.get_value() == 1
-def test_hr_signal():
+def test_hr_signal():
# test left shift
input_signal_a.update_value(0b1000000000000000)
input_signal_hr.update_value(0b0000000000000000)
diff --git a/test/test_mia/test_ir.py b/test/test_mia/test_ir.py
index d2993c5dd5d419856eaad6a7f94f9837c600fa67..cb06b0d090b86d9d762a0bef8398328b69caf6d1 100644
--- a/test/test_mia/test_ir.py
+++ b/test/test_mia/test_ir.py
@@ -13,13 +13,12 @@ def test_ir():
bus_control_s = Signal(cpu)
bus_id = 1
default_value = 2
- ir = IR(t_bus, f_bus, op_s, grx_s, m_s, bus_control_s,
- default_value, bus_id)
+ ir = IR(t_bus, f_bus, op_s, grx_s, m_s, bus_control_s, default_value, bus_id)
cpu.add_module(ir)
instruction = 0b0001101100000111
f_bus.update_value(instruction)
- bus_control_s.update_value((1,1))
+ bus_control_s.update_value((1, 1))
cpu.do_tick()
assert t_bus.get_value() == instruction
assert m_s.get_value() == (instruction >> 8) & 0b11
diff --git a/test/test_mia/test_lc.py b/test/test_mia/test_lc.py
index eafc49ed03ae481df6ddd0a6a301bc91ea4edcca..53da2e8d78b24f962892c3ff7f35e5dbbcd0d13a 100644
--- a/test/test_mia/test_lc.py
+++ b/test/test_mia/test_lc.py
@@ -10,14 +10,15 @@ def test_default_name():
lc = LC(s, s, s, s)
assert lc.name == "LC"
+
def test_name():
cpu = Processor()
s = Signal(cpu)
lc = LC(s, s, s, s, "lc")
assert lc.name == "lc"
-def test_read_from_bus():
+def test_read_from_bus():
cpu = Processor()
mM_control_s = Signal(cpu)
bus_input_s = Signal(cpu)
@@ -33,8 +34,8 @@ def test_read_from_bus():
cpu.do_tick()
assert lc.value == 10
-def test_read_from_uADR():
+def test_read_from_uADR():
cpu = Processor()
mM_control_s = Signal(cpu)
mM_uADR_s = Signal(cpu)
@@ -50,8 +51,8 @@ def test_read_from_uADR():
cpu.do_tick()
assert lc.value == 10
-def test_write_to_l_flag():
+def test_write_to_l_flag():
cpu = Processor()
# signals needed
@@ -85,8 +86,8 @@ def test_write_to_l_flag():
cpu.do_tick()
assert l_flag.value == 1
-def test_reset_l_flag():
+def test_reset_l_flag():
cpu = Processor()
mM_control_s = Signal(cpu)
@@ -111,8 +112,8 @@ def test_reset_l_flag():
cpu.do_tick()
assert l_flag.value == 0
-def test_lc_do_nothing():
+def test_lc_do_nothing():
cpu = Processor()
mM_control_s = Signal(cpu)
@@ -138,7 +139,6 @@ def test_lc_do_nothing():
def test_get_state():
-
# init all the modules
cpu = Processor()
bus_input_s = Signal(cpu)
diff --git a/test/test_mia/test_mia_grx.py b/test/test_mia/test_mia_grx.py
index f1bb6f9cd522ddc585feab2fd9f229e444feab74..89e8036e8d87f8b30fcedd8c59d9789891a7b7c2 100644
--- a/test/test_mia/test_mia_grx.py
+++ b/test/test_mia/test_mia_grx.py
@@ -11,6 +11,7 @@ def test_default_name():
assert grx.name == "GRx"
+
def test_name():
cpu = Processor()
s = Signal(cpu)
@@ -19,6 +20,7 @@ def test_name():
assert grx.name == "grx"
+
def test_read_from_bus():
cpu = Processor()
@@ -32,13 +34,12 @@ def test_read_from_bus():
bus_id = 1
- grx = GRX(to_bus, from_bus, bus_control, grx_control,
- m_control, s_control, bus_id)
+ grx = GRX(to_bus, from_bus, bus_control, grx_control, m_control, s_control, bus_id)
cpu.add_module(grx)
# set the cpu to read from bus
- bus_control.update_value((0,1))
+ bus_control.update_value((0, 1))
# set the value to be read to 7
from_bus.update_value(0b111)
# set the s bit to index using grx
@@ -57,6 +58,7 @@ def test_read_from_bus():
cpu.do_tick()
assert grx.registers[2] == 7
+
def test_write_to_bus():
cpu = Processor()
@@ -71,22 +73,31 @@ def test_write_to_bus():
bus_id = 1
# give registers none default values
- registers = [1,2,3,4]
-
- grx = GRX(to_bus, from_bus, bus_control, grx_control,
- m_control, s_control, bus_id, "grx", registers)
+ registers = [1, 2, 3, 4]
+
+ grx = GRX(
+ to_bus,
+ from_bus,
+ bus_control,
+ grx_control,
+ m_control,
+ s_control,
+ bus_id,
+ "grx",
+ registers,
+ )
cpu.add_module(grx)
# set the control so that grx should not read nor write to/from bus
# grx should output 'None'
- bus_control.update_value((3,2))
+ bus_control.update_value((3, 2))
cpu.do_tick()
assert to_bus.get_value() is None
# set the grx to write to the bus
- bus_control.update_value((1,3))
+ bus_control.update_value((1, 3))
# set the registers to be indexed by the grx bits
s_control.update_value(0)
# set the grx to select the first register
@@ -103,6 +114,7 @@ def test_write_to_bus():
cpu.do_tick()
assert to_bus.get_value() == 2
+
def test_set_value_from_bus():
cpu = Processor()
@@ -116,15 +128,14 @@ def test_set_value_from_bus():
bus_id = 1
- grx = GRX(to_bus, from_bus, bus_control, grx_control,
- m_control, s_control, bus_id)
+ grx = GRX(to_bus, from_bus, bus_control, grx_control, m_control, s_control, bus_id)
cpu.add_module(grx)
# 0 and 1 are valid values, all else should throw value error
s_control.update_value(2)
- bus_control.update_value((2,1))
+ bus_control.update_value((2, 1))
error = False
diff --git a/test/test_mia/test_mia_memory.py b/test/test_mia/test_mia_memory.py
index 5be23d870a342a0b5769127bc8499dfcee888f3a..e9db642396db3ddd0afd3657bbe0ed41d819fa74 100644
--- a/test/test_mia/test_mia_memory.py
+++ b/test/test_mia/test_mia_memory.py
@@ -76,6 +76,7 @@ def test_write():
assert output_s.get_value() is None
assert mem.get_state()["memory"] == [5, 2, 6, 4]
+
def test_load():
PATH = "test/test_mia/mia_memory_data_test.txt"
cpu = Processor()
@@ -87,8 +88,12 @@ def test_load():
output_s2 = Signal(cpu, value=0)
adress_s2 = Signal(cpu, value=0)
bus_control_s2 = Signal(cpu, value=0)
- pm1 = MiaMemory(input_s1, output_s1, adress_s1, bus_control_s1, 4, 0b010, name="PM1")
- pm2 = MiaMemory(input_s2, output_s2, adress_s2, bus_control_s2, 4, 0b010, name="PM2")
+ pm1 = MiaMemory(
+ input_s1, output_s1, adress_s1, bus_control_s1, 4, 0b010, name="PM1"
+ )
+ pm2 = MiaMemory(
+ input_s2, output_s2, adress_s2, bus_control_s2, 4, 0b010, name="PM2"
+ )
cpu.add_module(pm1)
cpu.add_module(pm2)
cpu.load_state_from_file(PATH)
@@ -99,7 +104,7 @@ def test_load():
bus_control_s2.update_value((0b010, 0))
cpu.do_tick()
- assert output_s1.get_value() == 0x0a
+ assert output_s1.get_value() == 0x0A
assert output_s2.get_value() == 0
adress_s1.update_value(1)
@@ -117,7 +122,7 @@ def test_load():
bus_control_s2.update_value((0b010, 0))
cpu.do_tick()
- assert output_s1.get_value() == 0x0f
+ assert output_s1.get_value() == 0x0F
assert output_s2.get_value() == 0
adress_s1.update_value(3)
diff --git a/test/test_mia/test_mia_register.py b/test/test_mia/test_mia_register.py
index 30c98ea5fba11574259c14241c5891c41a65ba74..d796dcce3195082611b25d50dd8674cf7e140aa6 100644
--- a/test/test_mia/test_mia_register.py
+++ b/test/test_mia/test_mia_register.py
@@ -31,6 +31,7 @@ def test_asr():
assert memory_output_signal.get_value() == 21
+
def test_ar():
cpu = Processor()
@@ -39,8 +40,15 @@ def test_ar():
bus_output_signal = Signal(cpu)
bus_control_signal = Signal(cpu)
- ar = AR(alu_input_signal, alu_output_signal, bus_output_signal,
- bus_control_signal, 1, 16, "AR")
+ ar = AR(
+ alu_input_signal,
+ alu_output_signal,
+ bus_output_signal,
+ bus_control_signal,
+ 1,
+ 16,
+ "AR",
+ )
cpu.add_module(ar)
@@ -61,6 +69,7 @@ def test_ar():
assert bus_output_signal.get_value() is None
+
def test_hr():
cpu = Processor()
@@ -70,8 +79,16 @@ def test_hr():
bus_output_signal = Signal(cpu)
bus_control_signal = Signal(cpu)
- hr = HR(alu_input_signal, alu_output_signal, bus_input_signal,
- bus_output_signal, bus_control_signal, 1, 16, "HR")
+ hr = HR(
+ alu_input_signal,
+ alu_output_signal,
+ bus_input_signal,
+ bus_output_signal,
+ bus_control_signal,
+ 1,
+ 16,
+ "HR",
+ )
cpu.add_module(hr)
diff --git a/test/test_mia/test_micro_memory.py b/test/test_mia/test_micro_memory.py
index f6898fa80c847fab58e440eee6503895d84ce09f..971b97d98ecaf94a0408a8953c0cd17b934397f6 100644
--- a/test/test_mia/test_micro_memory.py
+++ b/test/test_mia/test_micro_memory.py
@@ -20,10 +20,23 @@ def test_alu_field():
c_flag_s = Signal(cpu, value=0)
o_flag_s = Signal(cpu, value=0)
l_flag_s = Signal(cpu, value=0)
- uM = MicroMemory(alu_s, bus_control_s, bus_constant_s, s_s, p_s,
- lc_control_s, lc_uadr, upc_s, upc_control_s,
- upc_uadr_s, z_flag_s, n_flag_s, c_flag_s, o_flag_s,
- l_flag_s)
+ uM = MicroMemory(
+ alu_s,
+ bus_control_s,
+ bus_constant_s,
+ s_s,
+ p_s,
+ lc_control_s,
+ lc_uadr,
+ upc_s,
+ upc_control_s,
+ upc_uadr_s,
+ z_flag_s,
+ n_flag_s,
+ c_flag_s,
+ o_flag_s,
+ l_flag_s,
+ )
cpu.add_module(uM)
# Test that the value in the ALU field of the current instruction is
@@ -35,6 +48,7 @@ def test_alu_field():
uM.update_logic()
assert alu_s.get_value() == 0b1111
+
def test_bus_fields():
cpu = Processor()
alu_s = Signal(cpu, value=0)
@@ -52,16 +66,29 @@ def test_bus_fields():
c_flag_s = Signal(cpu, value=0)
o_flag_s = Signal(cpu, value=0)
l_flag_s = Signal(cpu, value=0)
- uM = MicroMemory(alu_s, bus_control_s, bus_constant_s, s_s, p_s,
- lc_control_s, lc_uadr, upc_s, upc_control_s,
- upc_uadr_s, z_flag_s, n_flag_s, c_flag_s, o_flag_s,
- l_flag_s)
+ uM = MicroMemory(
+ alu_s,
+ bus_control_s,
+ bus_constant_s,
+ s_s,
+ p_s,
+ lc_control_s,
+ lc_uadr,
+ upc_s,
+ upc_control_s,
+ upc_uadr_s,
+ z_flag_s,
+ n_flag_s,
+ c_flag_s,
+ o_flag_s,
+ l_flag_s,
+ )
cpu.add_module(uM)
# Test that the right control signal is sent for which modules should
# read from and write to the bus according to the TB & FB instruction
# fields
- tb_fb_instruction = 0b0000100001000000000000000 # TB: 0b100, FB: 0b001
+ tb_fb_instruction = 0b0000100001000000000000000 # TB: 0b100, FB: 0b001
state = uM.get_state()
state["memory"] = [tb_fb_instruction]
uM.set_state(state)
@@ -76,10 +103,10 @@ def test_bus_fields():
uM.set_state(state)
uM.update_logic()
assert alu_s.get_value() == 0b0100 # Should be the ALU field
- assert bus_constant_s.get_value() == 2**16-1 # Should be bit 9-24
- assert bus_control_s.get_value() == (0,0) # Bus shouldn't do anything
- assert p_s.get_value() == 0 # PC shouldn't do anything
- assert lc_control_s.get_value() == 0 # LC shouldn't do anything
+ assert bus_constant_s.get_value() == 2**16 - 1 # Should be bit 9-24
+ assert bus_control_s.get_value() == (0, 0) # Bus shouldn't do anything
+ assert p_s.get_value() == 0 # PC shouldn't do anything
+ assert lc_control_s.get_value() == 0 # LC shouldn't do anything
def test_s_field():
@@ -99,10 +126,23 @@ def test_s_field():
c_flag_s = Signal(cpu, value=0)
o_flag_s = Signal(cpu, value=0)
l_flag_s = Signal(cpu, value=0)
- uM = MicroMemory(alu_s, bus_control_s, bus_constant_s, s_s, p_s,
- lc_control_s, lc_uadr, upc_s, upc_control_s,
- upc_uadr_s, z_flag_s, n_flag_s, c_flag_s, o_flag_s,
- l_flag_s)
+ uM = MicroMemory(
+ alu_s,
+ bus_control_s,
+ bus_constant_s,
+ s_s,
+ p_s,
+ lc_control_s,
+ lc_uadr,
+ upc_s,
+ upc_control_s,
+ upc_uadr_s,
+ z_flag_s,
+ n_flag_s,
+ c_flag_s,
+ o_flag_s,
+ l_flag_s,
+ )
cpu.add_module(uM)
test_instruction = 0b0000000000100000000000000 # S: 1, all other bits: 0
@@ -131,10 +171,23 @@ def test_p_field():
c_flag_s = Signal(cpu, value=0)
o_flag_s = Signal(cpu, value=0)
l_flag_s = Signal(cpu, value=0)
- uM = MicroMemory(alu_s, bus_control_s, bus_constant_s, s_s, p_s,
- lc_control_s, lc_uadr, upc_s, upc_control_s,
- upc_uadr_s, z_flag_s, n_flag_s, c_flag_s, o_flag_s,
- l_flag_s)
+ uM = MicroMemory(
+ alu_s,
+ bus_control_s,
+ bus_constant_s,
+ s_s,
+ p_s,
+ lc_control_s,
+ lc_uadr,
+ upc_s,
+ upc_control_s,
+ upc_uadr_s,
+ z_flag_s,
+ n_flag_s,
+ c_flag_s,
+ o_flag_s,
+ l_flag_s,
+ )
cpu.add_module(uM)
test_instruction = 0b0000000000010000000000000 # P: 1, all other bits: 0
@@ -163,14 +216,27 @@ def test_lc_field():
c_flag_s = Signal(cpu, value=0)
o_flag_s = Signal(cpu, value=0)
l_flag_s = Signal(cpu, value=0)
- uM = MicroMemory(alu_s, bus_control_s, bus_constant_s, s_s, p_s,
- lc_control_s, lc_uadr, upc_s, upc_control_s,
- upc_uadr_s, z_flag_s, n_flag_s, c_flag_s, o_flag_s,
- l_flag_s)
+ uM = MicroMemory(
+ alu_s,
+ bus_control_s,
+ bus_constant_s,
+ s_s,
+ p_s,
+ lc_control_s,
+ lc_uadr,
+ upc_s,
+ upc_control_s,
+ upc_uadr_s,
+ z_flag_s,
+ n_flag_s,
+ c_flag_s,
+ o_flag_s,
+ l_flag_s,
+ )
cpu.add_module(uM)
# Test that the LC field is outputted onto the LC control signal
- test_instruction = 0b1111111111110011111111111 # LC: 00, all other bits are 1s
+ test_instruction = 0b1111111111110011111111111 # LC: 00, all other bits are 1s
state = uM.get_state()
state["memory"] = [test_instruction]
uM.set_state(state)
@@ -183,8 +249,8 @@ def test_lc_field():
state["memory"] = [test_instruction]
uM.set_state(state)
uM.update_logic()
- assert lc_control_s.get_value() == 0b11 # Should be equal to LC
- assert lc_uadr.get_value() == 0b1111111 # Should be equal to uADR
+ assert lc_control_s.get_value() == 0b11 # Should be equal to LC
+ assert lc_uadr.get_value() == 0b1111111 # Should be equal to uADR
def test_seq_field():
@@ -204,17 +270,32 @@ def test_seq_field():
c_flag_s = Signal(cpu, value=0)
o_flag_s = Signal(cpu, value=0)
l_flag_s = Signal(cpu, value=0)
- uM = MicroMemory(alu_s, bus_control_s, bus_constant_s, s_s, p_s,
- lc_control_s, lc_uadr, upc_s, upc_control_s,
- upc_uadr_s, z_flag_s, n_flag_s, c_flag_s, o_flag_s,
- l_flag_s)
+ uM = MicroMemory(
+ alu_s,
+ bus_control_s,
+ bus_constant_s,
+ s_s,
+ p_s,
+ lc_control_s,
+ lc_uadr,
+ upc_s,
+ upc_control_s,
+ upc_uadr_s,
+ z_flag_s,
+ n_flag_s,
+ c_flag_s,
+ o_flag_s,
+ l_flag_s,
+ )
cpu.add_module(uM)
# Test basic uPC control --------------------------------------------------
- test_instructions = [0b0000000000001100001111111, # SEQ: 0000 => uPC += 1
- 0b0000000000001100010000000, # SEQ: 0001 => uPC = K1
- 0b0000000000001100101111111, # SEQ: 0010 => uPC = K2
- 0b0000000000001100110000000] # SEQ: 0011 => uPC = 0
+ test_instructions = [
+ 0b0000000000001100001111111, # SEQ: 0000 => uPC += 1
+ 0b0000000000001100010000000, # SEQ: 0001 => uPC = K1
+ 0b0000000000001100101111111, # SEQ: 0010 => uPC = K2
+ 0b0000000000001100110000000,
+ ] # SEQ: 0011 => uPC = 0
state = uM.get_state()
state["memory"] = test_instructions
uM.set_state(state)
@@ -234,7 +315,7 @@ def test_seq_field():
upc_s.update_value(0)
uM.update_logic()
# The uPC control signal for loading uADR into uPC is 0b100
- assert upc_control_s.get_value() == 0b100 # Control signal => uPC=uADR
+ assert upc_control_s.get_value() == 0b100 # Control signal => uPC=uADR
assert upc_uadr_s.get_value() == 0b1111111 # Should be uADR
# Test conditional jumps --------------------------------------------------
@@ -244,20 +325,22 @@ def test_seq_field():
# SEQ = the bit pattern of the SEQ instruction field of the jump,
# flag_signal = the signal of the flag tested for the jump
# cond_val = the value that the flag should have for the jump to execute
- test_tups = [(0b0100, z_flag_s, 0),
- (0b1000, z_flag_s, 1),
- (0b1001, n_flag_s, 1),
- (0b1010, c_flag_s, 1),
- (0b1011, o_flag_s, 1),
- (0b1100, l_flag_s, 1),
- (0b1101, c_flag_s, 0),
- (0b1110, o_flag_s, 0)]
+ test_tups = [
+ (0b0100, z_flag_s, 0),
+ (0b1000, z_flag_s, 1),
+ (0b1001, n_flag_s, 1),
+ (0b1010, c_flag_s, 1),
+ (0b1011, o_flag_s, 1),
+ (0b1100, l_flag_s, 1),
+ (0b1101, c_flag_s, 0),
+ (0b1110, o_flag_s, 0),
+ ]
# Create the corresponding instructions for every conditional jump
# The uADR field is set to the index of the instruction + 1
test_instructions = []
for index, test_tup in enumerate(test_tups):
- instruction = (test_tup[0] << 7) + index+1
+ instruction = (test_tup[0] << 7) + index + 1
test_instructions.append(instruction)
state["memory"] = test_instructions
@@ -274,14 +357,14 @@ def test_seq_field():
# The uPC control signal should be 100 which corresponds to uPC = uADR
flag_signal.update_value(cond_val)
uM.update_logic()
- assert upc_control_s.get_value() == 0b100 # 100 => uPC = uADR
+ assert upc_control_s.get_value() == 0b100 # 100 => uPC = uADR
assert upc_uadr_s.get_value() == uADR
# Test the conditional jump withthe condition being false
# The uPC control signal should be 000 which corresponds to uPC += 1
flag_signal.update_value(not cond_val)
uM.update_logic()
- assert upc_control_s.get_value() == 0b000 # 000 => uPC += 1
+ assert upc_control_s.get_value() == 0b000 # 000 => uPC += 1
# Test subroutine jumps ---------------------------------------------------
# SEQ: 0110, uADR: 1111111
diff --git a/test/test_mia/test_micro_pc.py b/test/test_mia/test_micro_pc.py
index 67047b6936e6f114d8a45299fcc2410c3e400fe2..28032cd9ca7dd125dd71d53a0bcdc363dad2e9cb 100644
--- a/test/test_mia/test_micro_pc.py
+++ b/test/test_mia/test_micro_pc.py
@@ -15,7 +15,6 @@ def test_upc():
upc = MicroPC(control_signal, f_k1, f_k2, t_supc, f_supc, t_um, f_um)
cpu.add_module(upc)
-
control_signal.update_value(0b000)
f_k1.update_value(10)
f_k2.update_value(20)
diff --git a/test/test_mia/test_pc.py b/test/test_mia/test_pc.py
index e08a8b11b2abb07da6da4b96ae762882f2068df6..5e672ec1b7681323aa7282adae7a5326ddb8a14a 100644
--- a/test/test_mia/test_pc.py
+++ b/test/test_mia/test_pc.py
@@ -9,12 +9,14 @@ def test_default_name():
pc = PC(s, s, s, s, s)
assert pc.name == "PC"
+
def test_name():
cpu = Processor()
s = Signal(cpu)
pc = PC(s, s, s, s, 0, "pc")
assert pc.name == "pc"
+
def test_pc_increment():
"""
The value of the program counter should increase by one
@@ -28,7 +30,7 @@ def test_pc_increment():
bus_out = Signal(cpu)
# init bus_control with different value from the bus_id
- bus_control = Signal(cpu, "test", (1,1))
+ bus_control = Signal(cpu, "test", (1, 1))
bus_id = 4
@@ -47,6 +49,7 @@ def test_pc_increment():
cpu.do_tick()
assert pc.value == 7
+
def test_set_value_from_bus():
"""
The value of the program counter should be set by the bus when
@@ -59,7 +62,7 @@ def test_set_value_from_bus():
p = Signal(cpu, "p", False)
bus_in = Signal(cpu, "bus_in", 0)
bus_out = Signal(cpu)
- bus_control = Signal(cpu, "out", (7,1))
+ bus_control = Signal(cpu, "out", (7, 1))
bus_id = 1
pc = PC(p, bus_in, bus_out, bus_control, bus_id, "PC", 0)
@@ -76,6 +79,7 @@ def test_set_value_from_bus():
cpu.do_tick()
assert pc.value == 10
+
def test_write_to_bus():
# init all the modules
cpu = Processor()
@@ -83,7 +87,7 @@ def test_write_to_bus():
p = Signal(cpu, "p", False)
bus_in = Signal(cpu, "bus_in", 1)
bus_out = Signal(cpu, "bus_in", 2)
- bus_control = Signal(cpu, "out", (7,1))
+ bus_control = Signal(cpu, "out", (7, 1))
bus_id = 7
pc = PC(p, bus_in, bus_out, bus_control, bus_id, "PC", 20)
@@ -96,7 +100,7 @@ def test_write_to_bus():
assert bus_out.get_value() == 20
# the program counter should not read nor write to/from bus
- bus_control.update_value((1,2))
+ bus_control.update_value((1, 2))
cpu.do_tick()
assert bus_out.get_value() is None
@@ -118,7 +122,7 @@ def test_exception():
p = Signal(cpu, "p", False)
bus_in = Signal(cpu, "bus_in", 26)
bus_out = Signal(cpu)
- control = Signal(cpu, "out", (2,2))
+ control = Signal(cpu, "out", (2, 2))
bus_id = 1
pc = PC(p, bus_in, bus_out, control, bus_id, "PC", 13)
@@ -126,7 +130,7 @@ def test_exception():
# set values that should raise an error
p.update_value(True)
- control.update_value((2,1))
+ control.update_value((2, 1))
assert pc.value == 13
# reset one of the signals, the program counter should now read
@@ -141,22 +145,22 @@ def test_exception():
# reset the other signal, the program counter should now increment
# the value by one
- control.update_value((2,2))
+ control.update_value((2, 2))
cpu.do_tick()
assert pc.value == 27
# the program counter should do nothing
- control.update_value((2,1))
+ control.update_value((2, 1))
assert pc.value == 27
-def test_get_state():
+def test_get_state():
# init all the modules
cpu = Processor()
p = Signal(cpu, "p", False)
bus_in = Signal(cpu, "bus_in", 0)
bus_out = Signal(cpu)
- control = Signal(cpu, "bus", (2,2))
+ control = Signal(cpu, "bus", (2, 2))
bus_id = 1
pc = PC(p, bus_in, bus_out, control, bus_id, "PC", 13)
@@ -165,7 +169,7 @@ def test_get_state():
# update the signals
p.update_value(True)
- control.update_value((2,1))
+ control.update_value((2, 1))
# propagate the values to the program counter
cpu.do_tick()
@@ -175,24 +179,20 @@ def test_get_state():
assert state["value"] == 13
assert state["increment"] is True
-def test_set_state():
+def test_set_state():
# init all the modules
cpu = Processor()
p = Signal(cpu, "p", False)
bus_in = Signal(cpu, "bus_in", 0)
bus_out = Signal(cpu)
- control = Signal(cpu, "bus", (2,2))
+ control = Signal(cpu, "bus", (2, 2))
bus_id = 1
pc = PC(p, bus_in, bus_out, control, bus_id, "PC", 13)
- state = {
- "name": "pc",
- "value": 23,
- "increment": True
- }
+ state = {"name": "pc", "value": 23, "increment": True}
pc.set_state(state)
assert pc.name == "pc"