diff --git a/src/simudator/processor/mia/mia.py b/src/simudator/processor/mia/mia.py index 81519b1a9981a1729413ef9a477b5a1a70883965..05641f6560e2fe47cecb204e0966373f5084a147 100644 --- a/src/simudator/processor/mia/mia.py +++ b/src/simudator/processor/mia/mia.py @@ -318,15 +318,6 @@ class MIA_CPU(Processor): micro_memory_state = self.micro_memory.get_state() return micro_memory_state["halt"] - def run_continuously(self): - super().run_continuously() - # Need to do another tick after the halt for the cycle count to be - # correct. This is because the "halt signal" will be set at the end - # of the clock cycle before the last clock cycle where the halt - # technically should be executed - if self.should_halt(): - self.do_tick() - def launch_gui(self): from qtpy import QtCore from qtpy.QtWidgets import QApplication diff --git a/src/simudator/processor/mia/modules/micro_memory.py b/src/simudator/processor/mia/modules/micro_memory.py index 80ffbffdddd50f16668915ee767cec93ca2614a1..233fc4d3016f3f46c6056a7c2f10ea8ce5236266 100644 --- a/src/simudator/processor/mia/modules/micro_memory.py +++ b/src/simudator/processor/mia/modules/micro_memory.py @@ -134,10 +134,6 @@ class MicroMemory(Module): micro controller sets control signals to other modules in accordance with the micro instruction pointed to. """ - # Always set HALT to False so that an eventual previously signalled - # HALT is reset and execution can continue normally. - self.halt = False - instruction = self.upc_s.get_value() if instruction is None: return @@ -240,8 +236,27 @@ class MicroMemory(Module): case 0b1110: self._conditional_jump(self.o_flag_val, 0, uadr_field) case 0b1111: + # Halt is handled by update_register self.upc_control_s.update_value(0b011) - self.halt = True + + def update_register(self) -> None: + """ + Signal halt when the micro memory performs a halt instruction. + + Notes + ----- + Although the micro memory is not a register, this override is needed to + make sure a halt instruction is signalled on the actual clock cycle + where it is "executed". All control signals for the halt will have been + propagated at the end of the previous cycle. If the halt signalling + were to be done in update_logic, the halt would erroneously be signaled + one cycle to early. + """ + seq_field = (self.memory[self.curr_instr] >> 7) & 0b1111 + if seq_field == 0b1111: + self.halt = True + else: + self.halt = False def _conditional_jump(self, flag, cond_value, uadr): """Helper function for executing a conditional jump to the specified uadr