From a454d23517fc20db3e441d0759ed4929a477391f Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Martin=20H=C3=B6gstedt?= <marin.hogstedt@hotmail.com>
Date: Tue, 18 Jun 2024 10:50:36 +0200
Subject: [PATCH] added _ to bit_length in modules ar and asr
---
src/simudator/processor/mia/mia.py | 14 --------------
src/simudator/processor/mia/modules/ar.py | 4 ++--
src/simudator/processor/mia/modules/asr.py | 4 ++--
3 files changed, 4 insertions(+), 18 deletions(-)
diff --git a/src/simudator/processor/mia/mia.py b/src/simudator/processor/mia/mia.py
index 99f7b7a..1b6d95d 100644
--- a/src/simudator/processor/mia/mia.py
+++ b/src/simudator/processor/mia/mia.py
@@ -1,5 +1,4 @@
import sys
-
from typing import Any
from simudator.cli.cli import CLI
@@ -33,7 +32,6 @@ from simudator.processor.mia.modules.mia_grx import GRX
from simudator.processor.mia.modules.mia_memory import MiaMemory
from simudator.processor.mia.modules.micro_memory import MicroMemory
from simudator.processor.mia.modules.micro_pc import MicroPC
-
from simudator.processor.mia.modules.pc import PC
@@ -140,8 +138,6 @@ class MIA_CPU(Processor):
# PM specific
pm_size = 256
pm_bus_id = 0b010
- pm_address_padding = 2
- pm_value_padding = 4
pm = MiaMemory(
pm_bus,
bus_pm,
@@ -149,8 +145,6 @@ class MIA_CPU(Processor):
bus_control,
pm_size,
pm_bus_id,
- value_padding=pm_value_padding,
- address_padding=pm_address_padding,
name="PM",
)
@@ -162,8 +156,6 @@ class MIA_CPU(Processor):
# K1 specific
k1_size = 16
- k1_address_padding = 2
- k1_value_padding = 2
k1 = MiaMemory(
always_write_signal,
uPC_k1,
@@ -172,14 +164,10 @@ class MIA_CPU(Processor):
k1_size,
always_write_id,
name="K1",
- address_padding=k1_address_padding,
- value_padding=k1_value_padding,
)
# K2 specific
k2_size = 4
- k2_address_padding = 2
- k2_value_padding = 2
k2 = MiaMemory(
always_write_signal,
uPC_k2,
@@ -188,8 +176,6 @@ class MIA_CPU(Processor):
k2_size,
always_write_id,
name="K2",
- address_padding=k2_address_padding,
- value_padding=k2_value_padding,
)
# IR specific
diff --git a/src/simudator/processor/mia/modules/ar.py b/src/simudator/processor/mia/modules/ar.py
index a1e2c6f..5ca5556 100644
--- a/src/simudator/processor/mia/modules/ar.py
+++ b/src/simudator/processor/mia/modules/ar.py
@@ -8,7 +8,7 @@ class AR(IntegerRegister, MiaBusConnector):
Register for saving AlU calculations in MIA.
"""
- # Python does not allow multiple inherintence if more than one of the
+ # Python does not allow multiple inherintence if more than one of the
# parent classes uses __slots__. Thus we also includes the __slots__
# from MiaBusConnector.
__slots__ = ("bus_id", "bus_control_s")
@@ -55,5 +55,5 @@ class AR(IntegerRegister, MiaBusConnector):
"\n value: ",
hex(self._value),
"\n bit length: ",
- self.bit_length,
+ self._bit_length,
)
diff --git a/src/simudator/processor/mia/modules/asr.py b/src/simudator/processor/mia/modules/asr.py
index 08fa4c0..52db394 100644
--- a/src/simudator/processor/mia/modules/asr.py
+++ b/src/simudator/processor/mia/modules/asr.py
@@ -8,7 +8,7 @@ class ASR(IntegerRegister, MiaBusConnector):
Register for controlling the memory andress in MIA.
"""
- # Python does not allow multiple inherintence if more than one of the
+ # Python does not allow multiple inherintence if more than one of the
# parent classes uses __slots__. Thus we also includes the __slots__
# from MiaBusConnector.
__slots__ = ("bus_id", "bus_control_s")
@@ -43,5 +43,5 @@ class ASR(IntegerRegister, MiaBusConnector):
"\n value: ",
hex(self._value),
"\n bit length: ",
- self.bit_length,
+ self._bit_length,
)
--
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