diff --git a/src/simudator/processor/mia/mia.py b/src/simudator/processor/mia/mia.py
index 99f7b7aafa81ee8372ee9ccb27e5cb2456932dc1..1b6d95d866d8a1a63dff4809f2a4eb62a32faf21 100644
--- a/src/simudator/processor/mia/mia.py
+++ b/src/simudator/processor/mia/mia.py
@@ -1,5 +1,4 @@
 import sys
-
 from typing import Any
 
 from simudator.cli.cli import CLI
@@ -33,7 +32,6 @@ from simudator.processor.mia.modules.mia_grx import GRX
 from simudator.processor.mia.modules.mia_memory import MiaMemory
 from simudator.processor.mia.modules.micro_memory import MicroMemory
 from simudator.processor.mia.modules.micro_pc import MicroPC
-
 from simudator.processor.mia.modules.pc import PC
 
 
@@ -140,8 +138,6 @@ class MIA_CPU(Processor):
         # PM specific
         pm_size = 256
         pm_bus_id = 0b010
-        pm_address_padding = 2
-        pm_value_padding = 4
         pm = MiaMemory(
             pm_bus,
             bus_pm,
@@ -149,8 +145,6 @@ class MIA_CPU(Processor):
             bus_control,
             pm_size,
             pm_bus_id,
-            value_padding=pm_value_padding,
-            address_padding=pm_address_padding,
             name="PM",
         )
 
@@ -162,8 +156,6 @@ class MIA_CPU(Processor):
 
         # K1 specific
         k1_size = 16
-        k1_address_padding = 2
-        k1_value_padding = 2
         k1 = MiaMemory(
             always_write_signal,
             uPC_k1,
@@ -172,14 +164,10 @@ class MIA_CPU(Processor):
             k1_size,
             always_write_id,
             name="K1",
-            address_padding=k1_address_padding,
-            value_padding=k1_value_padding,
         )
 
         # K2 specific
         k2_size = 4
-        k2_address_padding = 2
-        k2_value_padding = 2
         k2 = MiaMemory(
             always_write_signal,
             uPC_k2,
@@ -188,8 +176,6 @@ class MIA_CPU(Processor):
             k2_size,
             always_write_id,
             name="K2",
-            address_padding=k2_address_padding,
-            value_padding=k2_value_padding,
         )
 
         # IR specific
diff --git a/src/simudator/processor/mia/modules/ar.py b/src/simudator/processor/mia/modules/ar.py
index a1e2c6ff115f840fb9bc4b260fa07eb6a7679a6f..5ca55569f7678c4a57cc67b5adb8a4f8090a0129 100644
--- a/src/simudator/processor/mia/modules/ar.py
+++ b/src/simudator/processor/mia/modules/ar.py
@@ -8,7 +8,7 @@ class AR(IntegerRegister, MiaBusConnector):
     Register for saving AlU calculations in MIA.
     """
 
-    # Python does not allow multiple inherintence if more than one of the 
+    # Python does not allow multiple inherintence if more than one of the
     # parent classes uses __slots__. Thus we also includes the __slots__
     # from MiaBusConnector.
     __slots__ = ("bus_id", "bus_control_s")
@@ -55,5 +55,5 @@ class AR(IntegerRegister, MiaBusConnector):
             "\n value: ",
             hex(self._value),
             "\n bit length: ",
-            self.bit_length,
+            self._bit_length,
         )
diff --git a/src/simudator/processor/mia/modules/asr.py b/src/simudator/processor/mia/modules/asr.py
index 08fa4c07a4c453198c0dab1d43b7b729d60f8f1e..52db394554dbaf045e44ca106ad3df0a7af6b361 100644
--- a/src/simudator/processor/mia/modules/asr.py
+++ b/src/simudator/processor/mia/modules/asr.py
@@ -8,7 +8,7 @@ class ASR(IntegerRegister, MiaBusConnector):
     Register for controlling the memory andress in MIA.
     """
 
-    # Python does not allow multiple inherintence if more than one of the 
+    # Python does not allow multiple inherintence if more than one of the
     # parent classes uses __slots__. Thus we also includes the __slots__
     # from MiaBusConnector.
     __slots__ = ("bus_id", "bus_control_s")
@@ -43,5 +43,5 @@ class ASR(IntegerRegister, MiaBusConnector):
             "\n value: ",
             hex(self._value),
             "\n bit length: ",
-            self.bit_length,
+            self._bit_length,
         )