diff --git a/src/simudator/core/breakpoint.py b/src/simudator/core/breakpoint.py
index be56ab7684f0c52c699b046520747bc4ff89cd50..115d3b460829840050d19ceead5c55dc2b8fd3bc 100644
--- a/src/simudator/core/breakpoint.py
+++ b/src/simudator/core/breakpoint.py
@@ -1,4 +1,6 @@
class Breakpoint:
+
+ __slots__ = "is_enabled"
"""
Base class for beakpoints, intended to be subclassed.
diff --git a/src/simudator/core/breakpoint_lambda.py b/src/simudator/core/breakpoint_lambda.py
index 6ae3746667ece75a87ce73281d65ec282e3b3a0c..52bff4bb3f88d631197bbc45cfd08f45f977c093 100644
--- a/src/simudator/core/breakpoint_lambda.py
+++ b/src/simudator/core/breakpoint_lambda.py
@@ -4,6 +4,8 @@ from simudator.core.breakpoint import Breakpoint
class LambdaBreakpoint(Breakpoint):
+
+ __slots__ = ("_lambda_func", "_kwargs")
"""
A breakpoint that uses a given function to decide whether the breakpoint
has been reached or not.
diff --git a/src/simudator/core/breakpoint_memory.py b/src/simudator/core/breakpoint_memory.py
index 07e18965f61fb90eea6d6c3fde42e3609137582f..8dbd66348eea3a2da753a1c1402bde9f638301e9 100644
--- a/src/simudator/core/breakpoint_memory.py
+++ b/src/simudator/core/breakpoint_memory.py
@@ -5,6 +5,9 @@ from simudator.core.modules import Memory
class MemoryBreakpoint(Breakpoint):
+
+ __slots__ = ("_memory", "_address", "_value")
+
"""
A breakpoint class for memory modules to break when a certain address
of the memory has a certain value.
diff --git a/src/simudator/core/breakpoint_state.py b/src/simudator/core/breakpoint_state.py
index 7ccfad0769008431c614a03ecc47ecb5e5304e22..58b042cbabf727bfb5ec1f523617592c0035595c 100644
--- a/src/simudator/core/breakpoint_state.py
+++ b/src/simudator/core/breakpoint_state.py
@@ -5,6 +5,8 @@ from simudator.core.module import Module
class StateBreakpoint(Breakpoint):
+
+ __slots__ = ("_module", "_state", "_value")
"""
A breakpoint class to break when the state variable for a module reaches
a specified value.
diff --git a/src/simudator/core/module.py b/src/simudator/core/module.py
index 473b82869df4136815bc1281df5c93ea0f9bffe5..6ae3b787de0d85be3457f5d7d9db3042e1b993df 100644
--- a/src/simudator/core/module.py
+++ b/src/simudator/core/module.py
@@ -28,6 +28,8 @@ class Module:
be prefixed with 'in\_' for input signals and 'out\_' for output signals.
"""
+ __slots__ = ("name", "signals")
+
def __init__(self, signals: dict[str, Signal], name: str = "") -> None:
self.name = name
self.signals = signals
diff --git a/src/simudator/core/modules/demux.py b/src/simudator/core/modules/demux.py
index 269138a4bb509972e5c4ef7d4af9f50c9ddc08c7..2aeb731c2e414cd161b71ec38ea2743d0be6ffbf 100644
--- a/src/simudator/core/modules/demux.py
+++ b/src/simudator/core/modules/demux.py
@@ -30,6 +30,8 @@ class Demux(Module):
Initial value to output to the currently selected output signal.
"""
+ __slots__ = ("_bit_length", "_value")
+
def __init__(
self,
control: Signal,
diff --git a/src/simudator/core/modules/memory.py b/src/simudator/core/modules/memory.py
index e1f68831055d7ec9b7ba0221f2a897e1a8bf357c..8f946bac71d900be0c087eeb00fdf1995cee9ab5 100644
--- a/src/simudator/core/modules/memory.py
+++ b/src/simudator/core/modules/memory.py
@@ -27,6 +27,11 @@ class Memory(Module):
Name of the module.
"""
+ __slots__ = (
+ "_memory",
+ "_current_address",
+ "_is_write",
+ )
"""
Constants used to textually pad the values of the memory when saving to
file.
diff --git a/src/simudator/core/modules/mux.py b/src/simudator/core/modules/mux.py
index 06a0fdda1631320d8c5679257add6483c7605850..018698e17e42ecc83ba737939135a370906cb14b 100644
--- a/src/simudator/core/modules/mux.py
+++ b/src/simudator/core/modules/mux.py
@@ -28,6 +28,8 @@ class Mux(Module):
Initial value to output to the output signal.
"""
+ __slots__ = ("_bit_length", "_value")
+
def __init__(
self,
control: Signal,
@@ -50,11 +52,10 @@ class Mux(Module):
super().__init__(signals, name)
# mask and bit_length
- self.bit_length = bit_length
- self.mask = 2**self.bit_length - 1
+ self._bit_length = bit_length
# Value to be read/written
- self.value = value
+ self._value = value
def update_register(self) -> None:
"""Read which signal to read from the control signal and forward that
@@ -63,13 +64,14 @@ class Mux(Module):
input_index = self.signals["in_control"].get_value()
input_signal_key = f"in_input_{input_index}"
input_value = self.signals[input_signal_key].get_value()
- self.value = input_value & self.mask
+ mask = 2**self._bit_length - 1
+ self._value = input_value & mask
def output_register(self):
"""Output the value of the currently selected input signal to the
output signal.
"""
- self.signals["out"].update_value(self.value)
+ self.signals["out"].update_value(self._value)
def update_logic(self):
"""Do nothing.
@@ -80,9 +82,8 @@ class Mux(Module):
def get_state(self) -> dict[str, Any]:
state = super().get_state()
- state["value"] = self.value
- state["bit_length"] = self.bit_length
- state["mask"] = self.mask
+ state["value"] = self._value
+ state["bit_length"] = self._bit_length
return state
@@ -97,18 +98,15 @@ class Mux(Module):
``int`` respectively.
"""
super().set_state(state)
- self.value = state["value"]
- self.bit_length = state["bit_length"]
- self.mask = state["mask"]
+ self._value = state["value"]
+ self._bit_length = state["bit_length"]
def print_module(self) -> None:
print(
self.name,
"\n-----",
"\nvalue: ",
- self.value,
+ self._value,
"\nbit length: ",
- self.bit_length,
- "\nmask: ",
- self.mask,
+ self._bit_length,
)
diff --git a/src/simudator/core/modules/register.py b/src/simudator/core/modules/register.py
index ce8eab9f2d8eb954a94d48bed2a675ebf27f94b6..e2b70cd4d6e0096ae841e8cbc370e0bb58cc7d3c 100644
--- a/src/simudator/core/modules/register.py
+++ b/src/simudator/core/modules/register.py
@@ -22,6 +22,8 @@ class Register(Module):
Name of the register.
"""
+ __slots__ = "_value"
+
def __init__(
self,
input_signal: Signal,
@@ -125,6 +127,8 @@ class IntegerRegister(Register):
Name of the register.
"""
+ __slots__ = "_bit_length"
+
def __init__(
self,
input: Signal,
diff --git a/src/simudator/core/processor.py b/src/simudator/core/processor.py
index 264ff98777b6e8fff486c5076246d4ba784309e1..0106327f75025ec87a47c75555a0041cfb301486 100644
--- a/src/simudator/core/processor.py
+++ b/src/simudator/core/processor.py
@@ -21,6 +21,30 @@ class Processor:
Uses modules and signals to simulate processor components behaviour.
"""
+ __slots__ = (
+ "modules",
+ "signals",
+ "clock",
+ "update_queue",
+ "module_history",
+ "signal_history",
+ "breakpoint_id_counter",
+ "breakpoints",
+ "breakpoint_reached",
+ "last_breakpoint",
+ "cycles_to_save",
+ "removed_cycles",
+ "max_line_len",
+ "line_separator",
+ "is_stopped",
+ "new_instruction",
+ "current_instructions",
+ "ignore_keys",
+ "lambdas",
+ "assembly_cycles",
+ "line_separator",
+ )
+
LINE_SEPARATOR = "-"
MAX_LINE_LEN = 170
CYCLES_TO_SAVE = 10000
@@ -712,7 +736,7 @@ class Processor:
if key != "name" and key not in ignore_keys
]
- def get_most_fields(self, modules: dict[Module, int], ignore_keys=[]) -> int:
+ def get_most_fields(self, modules: dict[Module, int], ignore_keys=None) -> int:
"""Get the maximum number of state variables among all modules.
Can optionally ignore keys.
@@ -731,6 +755,10 @@ class Processor:
The maximum of the number of module state variables among all
modules of the processor.
"""
+
+ if ignore_keys is None:
+ ignore_keys = []
+
fields = 0
for module in modules:
module_fields = len(self.fields_to_list(module, ignore_keys))
diff --git a/src/simudator/core/signal.py b/src/simudator/core/signal.py
index cbf9505e3c09ad980af14f35d550c0bd9411e666..8db1d14133278add895bc9b776f778addb5116df 100644
--- a/src/simudator/core/signal.py
+++ b/src/simudator/core/signal.py
@@ -18,6 +18,8 @@ class Signal:
Initial value of the signal.
"""
+ __slots__ = ("_processor", "_name", "_source", "_destinations", "_value")
+
def __init__(self, processor: Processor, name: str = "Signal", value=None):
self._processor = processor
self._name = name
diff --git a/src/simudator/gui/dialogs/lambda_breakpoint_dialog.py b/src/simudator/gui/dialogs/lambda_breakpoint_dialog.py
index 824131527bb809a225dc46337a9d0f4b96c2f0e6..9343ff10232952031b2d7e8aa40891d2b9996db4 100644
--- a/src/simudator/gui/dialogs/lambda_breakpoint_dialog.py
+++ b/src/simudator/gui/dialogs/lambda_breakpoint_dialog.py
@@ -13,6 +13,7 @@ from qtpy.QtWidgets import (
class LambdaBreakpointDialog(QDialog):
+
accepted = pyqtSignal(str, str, name="accepted")
def __init__(
diff --git a/src/simudator/processor/mia/gui/mia_grx_graphic.py b/src/simudator/processor/mia/gui/mia_grx_graphic.py
index 5474f915cc91a374f4fcccebadba008389e3a073..d7d94295ee0adc6f33fc7dc5f1c60d5beaa9bfc5 100644
--- a/src/simudator/processor/mia/gui/mia_grx_graphic.py
+++ b/src/simudator/processor/mia/gui/mia_grx_graphic.py
@@ -28,6 +28,7 @@ class GrxGraphicsItem(ModuleGraphicsItem):
REGISTER_MARGIN = 10
LINE_LENGTH = 30
MUX_WIDTH = 80
+ REGISTER_LENGTH = 4
def __init__(self, module: GRX):
self.register_text_labels = []
@@ -43,7 +44,9 @@ class GrxGraphicsItem(ModuleGraphicsItem):
for index, register_value in enumerate(self.module.registers):
# Make text to display for register
name = "Gr" + str(index)
- hex_length = math.ceil(self.state["bit_length"] / 4)
+
+ # Mia uses 4 hex numbers to represent the registers
+ hex_length = self.REGISTER_LENGTH
value_text = f"0x{register_value:0{hex_length}x}"
full_text = name + ": " + value_text[2:]
@@ -145,7 +148,9 @@ class GrxGraphicsItem(ModuleGraphicsItem):
for index, register_value in enumerate(self.module.registers):
text = self.register_text_labels[index]
name = "Gr" + str(index)
- hex_length = math.ceil(self.state["bit_length"] / 4)
+
+ # Mia uses 4 hex numbers for each register
+ hex_length = self.REGISTER_LENGTH
value_text = f"0x{register_value:0{hex_length}x}"
full_text = name + ": " + value_text[2:]
diff --git a/src/simudator/processor/mia/mia.py b/src/simudator/processor/mia/mia.py
index 99f7b7aafa81ee8372ee9ccb27e5cb2456932dc1..1b6d95d866d8a1a63dff4809f2a4eb62a32faf21 100644
--- a/src/simudator/processor/mia/mia.py
+++ b/src/simudator/processor/mia/mia.py
@@ -1,5 +1,4 @@
import sys
-
from typing import Any
from simudator.cli.cli import CLI
@@ -33,7 +32,6 @@ from simudator.processor.mia.modules.mia_grx import GRX
from simudator.processor.mia.modules.mia_memory import MiaMemory
from simudator.processor.mia.modules.micro_memory import MicroMemory
from simudator.processor.mia.modules.micro_pc import MicroPC
-
from simudator.processor.mia.modules.pc import PC
@@ -140,8 +138,6 @@ class MIA_CPU(Processor):
# PM specific
pm_size = 256
pm_bus_id = 0b010
- pm_address_padding = 2
- pm_value_padding = 4
pm = MiaMemory(
pm_bus,
bus_pm,
@@ -149,8 +145,6 @@ class MIA_CPU(Processor):
bus_control,
pm_size,
pm_bus_id,
- value_padding=pm_value_padding,
- address_padding=pm_address_padding,
name="PM",
)
@@ -162,8 +156,6 @@ class MIA_CPU(Processor):
# K1 specific
k1_size = 16
- k1_address_padding = 2
- k1_value_padding = 2
k1 = MiaMemory(
always_write_signal,
uPC_k1,
@@ -172,14 +164,10 @@ class MIA_CPU(Processor):
k1_size,
always_write_id,
name="K1",
- address_padding=k1_address_padding,
- value_padding=k1_value_padding,
)
# K2 specific
k2_size = 4
- k2_address_padding = 2
- k2_value_padding = 2
k2 = MiaMemory(
always_write_signal,
uPC_k2,
@@ -188,8 +176,6 @@ class MIA_CPU(Processor):
k2_size,
always_write_id,
name="K2",
- address_padding=k2_address_padding,
- value_padding=k2_value_padding,
)
# IR specific
diff --git a/src/simudator/processor/mia/modules/alu.py b/src/simudator/processor/mia/modules/alu.py
index 47ca0571e49bee3434230e20639cb674f91cab93..79c086dcb808dc6d2229866dcc78499c1d7f3cca 100644
--- a/src/simudator/processor/mia/modules/alu.py
+++ b/src/simudator/processor/mia/modules/alu.py
@@ -14,6 +14,8 @@ class ALU(Module):
Will do all calulations as two's complement binary numbers.
"""
+ __slots__ = ("z_value", "n_value", "o_value", "c_value", "hr_value")
+
WORD_LENGTH = 16
def __init__(
@@ -561,7 +563,11 @@ class ALU(Module):
# ----- Internal operations -----
def update_flags(
- self, binary_a: [int], binary_b: [int], binary_result: [int], carry: int
+ self,
+ binary_a: list[int],
+ binary_b: list[int],
+ binary_result: list[int],
+ carry: int,
) -> None:
"""
Will update the flags depending on inputed values and the result.
@@ -602,7 +608,7 @@ class ALU(Module):
"""
# Make empty binary number for result
- new_binary_number = [0 for i in range(self.WORD_LENGTH)]
+ new_binary_number = [0 for _ in range(self.WORD_LENGTH)]
# Change each bits value
for bit_index in range(self.WORD_LENGTH):
@@ -613,14 +619,16 @@ class ALU(Module):
return new_binary_number
- def add_binary_numbers(self, binary_a: [int], binary_b: [int]) -> ([int], int):
+ def add_binary_numbers(
+ self, binary_a: list[int], binary_b: list[int]
+ ) -> tuple[list[int], int]:
"""
Returns a tuple with the sum of two binary numbers
and the carry bit from the calculations
"""
# Make new binary number to store results
- binary_sum = [0 for i in range(self.WORD_LENGTH)]
+ binary_sum = [0 for _ in range(self.WORD_LENGTH)]
# Need carry for calculation
carry = 0
@@ -644,22 +652,22 @@ class ALU(Module):
return (binary_sum, carry)
- def binary_and(self, binary_a: int, binary_b: int) -> int:
+ def binary_and(self, binary_a: list[int], binary_b: list[int]) -> list[int]:
"""
Calculate and between binary two numbers
"""
- binary_and = [0 for i in range(self.WORD_LENGTH)]
+ binary_and = [0 for _ in range(self.WORD_LENGTH)]
for binary_index in range(self.WORD_LENGTH):
binary_and[binary_index] = binary_a[binary_index] & binary_b[binary_index]
return binary_and
- def binary_or(self, binary_a: [int], binary_b: [int]) -> [int]:
+ def binary_or(self, binary_a: list[int], binary_b: list[int]) -> list[int]:
"""
Calculate or between two binary numbers
"""
- binary_or = [0 for i in range(self.WORD_LENGTH)]
+ binary_or = [0 for _ in range(self.WORD_LENGTH)]
for binary_index in range(self.WORD_LENGTH):
binary_or[binary_index] = binary_a[binary_index] | binary_b[binary_index]
diff --git a/src/simudator/processor/mia/modules/ar.py b/src/simudator/processor/mia/modules/ar.py
index 1e958c5b7832be7fef3661f212aa775499b913ed..5ca55569f7678c4a57cc67b5adb8a4f8090a0129 100644
--- a/src/simudator/processor/mia/modules/ar.py
+++ b/src/simudator/processor/mia/modules/ar.py
@@ -8,6 +8,11 @@ class AR(IntegerRegister, MiaBusConnector):
Register for saving AlU calculations in MIA.
"""
+ # Python does not allow multiple inherintence if more than one of the
+ # parent classes uses __slots__. Thus we also includes the __slots__
+ # from MiaBusConnector.
+ __slots__ = ("bus_id", "bus_control_s")
+
def __init__(
self,
alu_input_signal: Signal,
@@ -50,5 +55,5 @@ class AR(IntegerRegister, MiaBusConnector):
"\n value: ",
hex(self._value),
"\n bit length: ",
- self.bit_length,
+ self._bit_length,
)
diff --git a/src/simudator/processor/mia/modules/asr.py b/src/simudator/processor/mia/modules/asr.py
index 46f00e3a9e3aae8d3ce4f22c16627e0b654badee..52db394554dbaf045e44ca106ad3df0a7af6b361 100644
--- a/src/simudator/processor/mia/modules/asr.py
+++ b/src/simudator/processor/mia/modules/asr.py
@@ -8,6 +8,11 @@ class ASR(IntegerRegister, MiaBusConnector):
Register for controlling the memory andress in MIA.
"""
+ # Python does not allow multiple inherintence if more than one of the
+ # parent classes uses __slots__. Thus we also includes the __slots__
+ # from MiaBusConnector.
+ __slots__ = ("bus_id", "bus_control_s")
+
def __init__(
self,
bus_input_signal: Signal,
@@ -38,5 +43,5 @@ class ASR(IntegerRegister, MiaBusConnector):
"\n value: ",
hex(self._value),
"\n bit length: ",
- self.bit_length,
+ self._bit_length,
)
diff --git a/src/simudator/processor/mia/modules/bus.py b/src/simudator/processor/mia/modules/bus.py
index 4325b6dbbe5048e14ae14dfad1a2b84647e9a99f..d94dbd9def73ae7064069ac9aa6b15c2c98cc715 100644
--- a/src/simudator/processor/mia/modules/bus.py
+++ b/src/simudator/processor/mia/modules/bus.py
@@ -10,6 +10,8 @@ class Bus(Module):
input signal can send a value to the bus at a time.
"""
+ __slots__ = ()
+
def __init__(
self, inputs: list[Signal] = [], outputs: list[Signal] = [], name: str = "Bus"
) -> None:
diff --git a/src/simudator/processor/mia/modules/hr.py b/src/simudator/processor/mia/modules/hr.py
index 58cba86c7ae51b9a3a899044d7a39a4c962b5e39..bd74491b83632dcbe52679eaba363326fece177c 100644
--- a/src/simudator/processor/mia/modules/hr.py
+++ b/src/simudator/processor/mia/modules/hr.py
@@ -8,6 +8,11 @@ class HR(IntegerRegister, MiaBusConnector):
Register for saving large AlU calculations in MIA.
"""
+ # Python does not allow multiple inherintence if more than one of the
+ # parent classes uses __slots__. Thus we also includes the __slots__
+ # from MiaBusConnector.
+ __slots__ = ("bus_id", "bus_control_s")
+
def __init__(
self,
alu_input_signal: Signal,
diff --git a/src/simudator/processor/mia/modules/ir.py b/src/simudator/processor/mia/modules/ir.py
index c3224a8adbd1ef68692e604e7f2e897becafba64..9095742af61c392b20d01c976e56fd7717cd8052 100644
--- a/src/simudator/processor/mia/modules/ir.py
+++ b/src/simudator/processor/mia/modules/ir.py
@@ -12,6 +12,11 @@ class IR(Module, MiaBusConnector):
several fields.
"""
+ # Python does not allow multiple inherintence if more than one of the
+ # parent classes uses __slots__. Thus we also includes the __slots__
+ # from MiaBusConnector.
+ __slots__ = ("op", "grx", "m", "a", "bus_id", "instruction", "bus_control_s")
+
def __init__(
self,
to_bus: Signal,
@@ -24,7 +29,6 @@ class IR(Module, MiaBusConnector):
bus_id=0,
name: str = "IR",
) -> None:
- MiaBusConnector.__init__(self, bus_control, bus_id)
signals = {
"in_input": from_bus,
@@ -34,6 +38,7 @@ class IR(Module, MiaBusConnector):
"out_m": m_s,
}
Module.__init__(self, signals, name)
+ MiaBusConnector.__init__(self, bus_control, bus_id)
# Internal values
self.op = 0
@@ -141,4 +146,3 @@ class IR(Module, MiaBusConnector):
string_pair = state_string.split(": ")
# TODO: Maybe check if it starts with instruction: ?
self.instruction = int(string_pair[1], 16)
-
diff --git a/src/simudator/processor/mia/modules/lc.py b/src/simudator/processor/mia/modules/lc.py
index 15e1598df7c809b62dabda12014548c85df77172..19eadbbf7bb0ac4edefd84c30d51d7140d51be31 100644
--- a/src/simudator/processor/mia/modules/lc.py
+++ b/src/simudator/processor/mia/modules/lc.py
@@ -12,6 +12,15 @@ class LC(Module):
increase by one or read from mM_uADR.
"""
+ __slots__ = (
+ "value",
+ "read_from_bus",
+ "read_from_uADR",
+ "decrement_by_one",
+ "bit_length",
+ "mask",
+ )
+
def __init__(
self,
mM_control: Signal,
@@ -50,7 +59,6 @@ class LC(Module):
Optional bit length of the loop counter.
"""
-
# signals
signals = {
"in_control": mM_control,
@@ -200,4 +208,3 @@ class LC(Module):
"\n read from bus: ",
self.read_from_bus,
)
-
diff --git a/src/simudator/processor/mia/modules/mia_bus_connect.py b/src/simudator/processor/mia/modules/mia_bus_connect.py
index caf7fe303c30b5b8c9ed5a71b5281882d4303036..e5607b1f82509d93fba475bce0ebcc7b68bd3729 100644
--- a/src/simudator/processor/mia/modules/mia_bus_connect.py
+++ b/src/simudator/processor/mia/modules/mia_bus_connect.py
@@ -9,6 +9,11 @@ class MiaBusConnector:
Has logic for controlling when to read and write to bus.
"""
+ # Python does not allow multiple inherintence if more than one of the
+ # parent classes uses __slots__. Since the modules that inherit from MiaBusConnector
+ # also inherits from other classes we leave this class __slots__ empty.
+ __slots__ = ()
+
def __init__(self, bus_control: Signal, bus_id: int = 0) -> None:
# init the name
self.bus_id = bus_id
diff --git a/src/simudator/processor/mia/modules/mia_grx.py b/src/simudator/processor/mia/modules/mia_grx.py
index 414bcb9aa6f32f25d2c0ca12f2ad4b9919423c21..d384aa6b3c4c49607df04c9e8b99698b736d441a 100644
--- a/src/simudator/processor/mia/modules/mia_grx.py
+++ b/src/simudator/processor/mia/modules/mia_grx.py
@@ -14,6 +14,18 @@ class GRX(Module, MiaBusConnector):
registers should be indexed by the GRx bits or the M bits.
"""
+ # Python does not allow multiple inherintence if more than one of the
+ # parent classes uses __slots__. Thus we also includes the __slots__
+ # from MiaBusConnector.
+ __slots__ = (
+ "grx_control",
+ "m_control",
+ "s_control",
+ "bus_id",
+ "registers",
+ "bus_control_s",
+ )
+
def __init__(
self,
to_bus: Signal,
@@ -25,12 +37,10 @@ class GRX(Module, MiaBusConnector):
bus_id: int,
name="GRx",
registers=[0 for _ in range(4)],
- bit_length=16,
) -> None:
# Set connection to/from bus and bus_id
MiaBusConnector.__init__(self, bus_control, bus_id)
-
# Other signals
signals = {
"in_input": from_bus,
@@ -45,9 +55,6 @@ class GRX(Module, MiaBusConnector):
# set the registers
self.registers = registers
- # set the bit_length
- self.bit_length = bit_length
-
def update_register(self):
"""
If the module should read from the bus, update the correct
@@ -98,7 +105,6 @@ class GRX(Module, MiaBusConnector):
"""
state = {
"name": self.name,
- "bit_length": self.bit_length,
"registers": self.registers[:],
}
return state
@@ -115,8 +121,6 @@ class GRX(Module, MiaBusConnector):
Sets the grx state to one given in dict.
"""
self.name = state["name"]
- if "bit_length" in state:
- self.bit_length = state["bit_length"]
self.registers = state["registers"]
def reset(self) -> None:
@@ -162,8 +166,6 @@ class GRX(Module, MiaBusConnector):
"\n -----",
"\n bus_id: ",
self.bus_id,
- "\n bit_length: ",
- self.bit_length,
"\n GR0: ",
hex(self.registers[0]),
"\n GR1: ",
@@ -173,4 +175,3 @@ class GRX(Module, MiaBusConnector):
"\n GR3: ",
hex(self.registers[3]),
)
-
diff --git a/src/simudator/processor/mia/modules/mia_memory.py b/src/simudator/processor/mia/modules/mia_memory.py
index 6201a7d7e7ebd1d28296cecd4bb45d46eb746e27..4b2ca42c137f718c4260e5ab9064f2a5a8b2d573 100644
--- a/src/simudator/processor/mia/modules/mia_memory.py
+++ b/src/simudator/processor/mia/modules/mia_memory.py
@@ -11,6 +11,11 @@ class MiaMemory(MiaBusConnector, Memory):
to/from the mia bus.
"""
+ # Python does not allow multiple inherintence if more than one of the
+ # parent classes uses __slots__. Thus we also includes the __slots__
+ # from MiaBusConnector.
+ __slots__ = ("label_adress_mapping", "bus_id", "bus_control_s")
+
def __init__(
self,
input_signal: Signal,
@@ -19,8 +24,6 @@ class MiaMemory(MiaBusConnector, Memory):
bus_control_s: Signal,
size: int = 1,
bus_id: int = 0,
- value_padding: int = 2,
- address_padding: int = 2,
name: str = "PM",
) -> None:
MiaBusConnector.__init__(self, bus_control_s, bus_id)
@@ -35,7 +38,6 @@ class MiaMemory(MiaBusConnector, Memory):
)
self.bus_control_s.add_destination(self)
- # TODO: only one of these are needed
self.label_adress_mapping = {}
def update_register(self) -> None:
diff --git a/src/simudator/processor/mia/modules/micro_memory.py b/src/simudator/processor/mia/modules/micro_memory.py
index 8915c5ed2f7ae4d51dd2cd7f5c22400f812fe1af..c118500e3bac6b0a9ad85d45f7bddbd44f85d892 100644
--- a/src/simudator/processor/mia/modules/micro_memory.py
+++ b/src/simudator/processor/mia/modules/micro_memory.py
@@ -17,6 +17,19 @@ class MicroMemory(Module):
cycle.
"""
+ __slots__ = (
+ "curr_instr",
+ "z_flag_val",
+ "n_flag_val",
+ "c_flag_val",
+ "o_flag_val",
+ "l_flag_val",
+ "memory",
+ "halt",
+ "adress_padding",
+ "value_padding",
+ )
+
def __init__(
self,
alu: Signal,
@@ -35,7 +48,7 @@ class MicroMemory(Module):
o_flag: Signal,
l_flag: Signal,
name: str = "uM",
- address_padding: int = 2,
+ adress_padding: int = 2,
value_padding: int = 7,
) -> None:
"""
@@ -81,7 +94,6 @@ class MicroMemory(Module):
None
"""
-
signals = {
"in_upc": upc,
"in_flag_z": z_flag,
@@ -113,7 +125,7 @@ class MicroMemory(Module):
self.halt = False # Used for signalling a HALT
# paddings to ensure saving to file has the correct format
- self.address_padding = address_padding
+ self.adress_padding = adress_padding
self.value_padding = value_padding
def update_logic(self) -> None:
@@ -168,7 +180,7 @@ class MicroMemory(Module):
if (0b0001 <= alu_field <= 0b0010) or (0b0100 <= alu_field <= 0b1000):
# Special case for writing to the ALU from the bus, in which case
# the FB field of the instruction is ignored (overwritten, even)
- # (The ALU does not have an actual bus address in the MIA processor)
+ # (The ALU does not have an actual bus adress in the MIA processor)
fb_field = 0b1000
# Handle LC according to the LC field
@@ -266,9 +278,9 @@ class MicroMemory(Module):
value 0 are not printed.
"""
print("", self.name, "\n -----\n")
- for address in range(len(self.memory)):
- if self.memory[address] != 0:
- print("", str(address), "", str(self.memory[address]), "\n")
+ for adress in range(len(self.memory)):
+ if self.memory[adress] != 0:
+ print("", str(adress), "", str(self.memory[adress]), "\n")
def get_state(self) -> dict:
state = super().get_state()
@@ -306,12 +318,12 @@ class MicroMemory(Module):
def load_from_str(self, state_string) -> None:
"""Load the contents of the micro memory from a string consisting of a
- row for every address. Each row should be formatted as 'ADR: VALUE'.
- Both the address and the value should be written in hex notation.
+ row for every adress. Each row should be formatted as 'ADR: VALUE'.
+ Both the adress and the value should be written in hex notation.
Adresses which are not specified in the string will receive the value
0.
- Example string where all addresses except for 0x00, 0x01 and 0xb0
+ Example string where all adresses except for 0x00, 0x01 and 0xb0
receive the value 0 by default::
'
@@ -327,17 +339,17 @@ class MicroMemory(Module):
for line in lines:
if line: # last line is empty from split with \n
line_data = line.split(": ")
- address = int(line_data[0], 16)
+ adress = int(line_data[0], 16)
value = int(line_data[1], 16)
- self.memory[address] = value
+ self.memory[adress] = value
def save_state_to_file(self, file_path: str) -> None:
"""Tries to save the modules state to a given file."""
file = open(file_path, "a")
file.write(self.name + ":\n")
for index, value in enumerate(self.memory):
- # Write the address in hex and add ': ' to the end
- file.write(hex(index)[2:].rjust(self.address_padding, "0") + ": ")
+ # Write the adress in hex and add ': ' to the end
+ file.write(hex(index)[2:].rjust(self.adress_padding, "0") + ": ")
# Write the value in hex
file.write(hex(value)[2:].rjust(self.value_padding, "0"))
file.write("\n")
@@ -347,7 +359,7 @@ class MicroMemory(Module):
def get_largest_mem_adr(self) -> int:
"""Helper function for pretty_print that returns the length of
- the largest address in the memory to print for a module.
+ the largest adress in the memory to print for a module.
"""
return len(str(len(self.memory)))
diff --git a/src/simudator/processor/mia/modules/micro_pc.py b/src/simudator/processor/mia/modules/micro_pc.py
index 74264229dbd021ce241815aa25cadfd7dbe1fced..adcd99ffefb2c09e95fb0f3d68544a09c9eea770 100644
--- a/src/simudator/processor/mia/modules/micro_pc.py
+++ b/src/simudator/processor/mia/modules/micro_pc.py
@@ -11,6 +11,8 @@ class MicroPC(Module):
to read from or write to.
"""
+ __slots__ = ("value", "bit_length")
+
def __init__(
self,
control_signal: Signal,
diff --git a/src/simudator/processor/mia/modules/pc.py b/src/simudator/processor/mia/modules/pc.py
index 575c4b65fde008511a6f184836c6e9cd43a4c973..f95524345c5901c9e740ebeb69f72cb9cf6b20b7 100644
--- a/src/simudator/processor/mia/modules/pc.py
+++ b/src/simudator/processor/mia/modules/pc.py
@@ -17,6 +17,11 @@ class PC(Module, MiaBusConnector):
value on the bus. If both are true it does nothing.
"""
+ # Python does not allow multiple inherintence if more than one of the
+ # parent classes uses __slots__. Thus we also includes the __slots__
+ # from MiaBusConnector.
+ __slots__ = ("bus_id", "bus_control_s", "value", "increase_by_one")
+
def __init__(
self,
p: Signal,
@@ -50,7 +55,7 @@ class PC(Module, MiaBusConnector):
self.signals["out_content"].update_value(None)
def update_register(self) -> None:
- """Updates the value of the PC according to the signals sent by the micro memory.
+ """Updates the value of the PC according to the signals sent by the micro memory.
If the program counter recives 'True' from both signals it
should do nothing and wait for the next cycle.
@@ -121,4 +126,3 @@ class PC(Module, MiaBusConnector):
def print_module(self) -> None:
print("", self.name, "\n -----", "\n value: ", hex(self.value))
-
diff --git a/src/simudator/processor/simple/simple.py b/src/simudator/processor/simple/simple.py
index 7b66364741fab4904a2eb9d0cf6c41ba42c76587..2d01160fd065a187a574c6873ab474e67db04fd6 100644
--- a/src/simudator/processor/simple/simple.py
+++ b/src/simudator/processor/simple/simple.py
@@ -15,6 +15,8 @@ class SIMPLE_CPU(Processor):
This cpu is made to test core modules and module graphics items for these modules.
"""
+ __slots__ = ()
+
def __init__(self) -> None:
super().__init__()
# Creating all signals
diff --git a/test/test_core/test_mux.py b/test/test_core/test_mux.py
index 7dab6d3630af58eef3411ca0f7763b6fb839bf09..fed767a99b0ebbcd6460ec126adbde0b224e6fa3 100644
--- a/test/test_core/test_mux.py
+++ b/test/test_core/test_mux.py
@@ -38,7 +38,6 @@ def test_get_state():
assert state["name"] == "Mux"
assert state["value"] == 7
assert state["bit_length"] == 5
- assert state["mask"] == 31
def test_set_state():
@@ -58,9 +57,8 @@ def test_set_state():
mux.set_state(state)
assert mux.name == "Mux"
- assert mux.value == 6
- assert mux.bit_length == 2
- assert mux.mask == 3
+ assert mux._value == 6
+ assert mux._bit_length == 2
def test_writing_to_output():