diff --git a/src/simudator/processor/mia/modules/asr.py b/src/simudator/processor/mia/modules/asr.py
index dbf5e8a9a16bbb6b16d802a0b6deea40c48eaa87..ba33b4761c5a3ea2bf3adc176e38641296352543 100644
--- a/src/simudator/processor/mia/modules/asr.py
+++ b/src/simudator/processor/mia/modules/asr.py
@@ -8,6 +8,8 @@ class ASR(IntegerRegister, MiaBusConnector):
Register for controlling the memory andress in MIA.
"""
+ __slots__ = ("bus_id", "bus_control_s")
+
def __init__(
self,
bus_input_signal: Signal,
diff --git a/src/simudator/processor/mia/modules/bus.py b/src/simudator/processor/mia/modules/bus.py
index 4325b6dbbe5048e14ae14dfad1a2b84647e9a99f..d94dbd9def73ae7064069ac9aa6b15c2c98cc715 100644
--- a/src/simudator/processor/mia/modules/bus.py
+++ b/src/simudator/processor/mia/modules/bus.py
@@ -10,6 +10,8 @@ class Bus(Module):
input signal can send a value to the bus at a time.
"""
+ __slots__ = ()
+
def __init__(
self, inputs: list[Signal] = [], outputs: list[Signal] = [], name: str = "Bus"
) -> None:
diff --git a/src/simudator/processor/mia/modules/lc.py b/src/simudator/processor/mia/modules/lc.py
index 045e9810a3174db204a16325483b429b75b40946..19eadbbf7bb0ac4edefd84c30d51d7140d51be31 100644
--- a/src/simudator/processor/mia/modules/lc.py
+++ b/src/simudator/processor/mia/modules/lc.py
@@ -12,8 +12,14 @@ class LC(Module):
increase by one or read from mM_uADR.
"""
- __slots__ = ("value", "read_from_bus", "read_from_uADR", "decrement_by_one", "bit_length", "mask")
-
+ __slots__ = (
+ "value",
+ "read_from_bus",
+ "read_from_uADR",
+ "decrement_by_one",
+ "bit_length",
+ "mask",
+ )
def __init__(
self,
@@ -53,7 +59,6 @@ class LC(Module):
Optional bit length of the loop counter.
"""
-
# signals
signals = {
"in_control": mM_control,
@@ -203,4 +208,3 @@ class LC(Module):
"\n read from bus: ",
self.read_from_bus,
)
-
diff --git a/src/simudator/processor/mia/modules/mia_grx.py b/src/simudator/processor/mia/modules/mia_grx.py
index 71e18a0dc38dea4ab75644ca05096ec2a1602c1b..135b930c3d7a3651e709d162515469874143272a 100644
--- a/src/simudator/processor/mia/modules/mia_grx.py
+++ b/src/simudator/processor/mia/modules/mia_grx.py
@@ -14,7 +14,14 @@ class GRX(Module, MiaBusConnector):
registers should be indexed by the GRx bits or the M bits.
"""
- __slots__ = ("grx_control", "m_control", "s_control", "bus_id", "registers")
+ __slots__ = (
+ "grx_control",
+ "m_control",
+ "s_control",
+ "bus_id",
+ "registers",
+ "bus_control_s",
+ )
def __init__(
self,
diff --git a/src/simudator/processor/mia/modules/mia_memory.py b/src/simudator/processor/mia/modules/mia_memory.py
index cc66d8b853a2c176b5c2cc4bc9d13dc2c54cabc2..b4b2e81a35ecb5979f0730f73831fb719ebf9718 100644
--- a/src/simudator/processor/mia/modules/mia_memory.py
+++ b/src/simudator/processor/mia/modules/mia_memory.py
@@ -11,6 +11,8 @@ class MiaMemory(MiaBusConnector, Memory):
to/from the mia bus.
"""
+ __slots__ = ("label_adress_mapping", "bus_id", "bus_control_s")
+
def __init__(
self,
input_signal: Signal,
@@ -37,7 +39,6 @@ class MiaMemory(MiaBusConnector, Memory):
)
self.bus_control_s.add_destination(self)
- # TODO: only one of these are needed
self.label_adress_mapping = {}
def update_register(self) -> None:
@@ -65,7 +66,9 @@ class MiaMemory(MiaBusConnector, Memory):
if address_value is not None:
self.current_address = address_value
if self.write_to_bus():
- self.signals["out_content"].update_value(self.memory[self.current_address])
+ self.signals["out_content"].update_value(
+ self.memory[self.current_address]
+ )
else:
self.signals["out_content"].update_value(None)
diff --git a/src/simudator/processor/mia/modules/micro_memory.py b/src/simudator/processor/mia/modules/micro_memory.py
index 7eb789584135f1e31dfbf09311bc8bea327da89d..d919ef88182af45375794cbcfaffdd3e1147ea12 100644
--- a/src/simudator/processor/mia/modules/micro_memory.py
+++ b/src/simudator/processor/mia/modules/micro_memory.py
@@ -17,6 +17,19 @@ class MicroMemory(Module):
cycle.
"""
+ __slots__ = (
+ "curr_instr",
+ "z_flag_val",
+ "n_flag_val",
+ "c_flag_val",
+ "o_flag_val",
+ "l_flag_val",
+ "memory",
+ "halt",
+ "adress_padding",
+ "value_padding",
+ )
+
def __init__(
self,
alu: Signal,
@@ -35,7 +48,7 @@ class MicroMemory(Module):
o_flag: Signal,
l_flag: Signal,
name: str = "uM",
- address_padding: int = 2,
+ adress_padding: int = 2,
value_padding: int = 7,
) -> None:
"""
@@ -81,7 +94,6 @@ class MicroMemory(Module):
None
"""
-
signals = {
"in_upc": upc,
"in_flag_z": z_flag,
@@ -113,7 +125,7 @@ class MicroMemory(Module):
self.halt = False # Used for signalling a HALT
# paddings to ensure saving to file has the correct format
- self.address_padding = address_padding
+ self.adress_padding = adress_padding
self.value_padding = value_padding
def update_logic(self) -> None:
@@ -168,7 +180,7 @@ class MicroMemory(Module):
if (0b0001 <= alu_field <= 0b0010) or (0b0100 <= alu_field <= 0b1000):
# Special case for writing to the ALU from the bus, in which case
# the FB field of the instruction is ignored (overwritten, even)
- # (The ALU does not have an actual bus address in the MIA processor)
+ # (The ALU does not have an actual bus adress in the MIA processor)
fb_field = 0b1000
# Handle LC according to the LC field
@@ -266,9 +278,9 @@ class MicroMemory(Module):
value 0 are not printed.
"""
print("", self.name, "\n -----\n")
- for address in range(len(self.memory)):
- if self.memory[address] != 0:
- print("", str(address), "", str(self.memory[address]), "\n")
+ for adress in range(len(self.memory)):
+ if self.memory[adress] != 0:
+ print("", str(adress), "", str(self.memory[adress]), "\n")
def get_state(self) -> dict:
state = super().get_state()
@@ -305,12 +317,12 @@ class MicroMemory(Module):
def load_from_str(self, state_string) -> None:
"""Load the contents of the micro memory from a string consisting of a
- row for every address. Each row should be formatted as 'ADR: VALUE'.
- Both the address and the value should be written in hex notation.
+ row for every adress. Each row should be formatted as 'ADR: VALUE'.
+ Both the adress and the value should be written in hex notation.
Adresses which are not specified in the string will receive the value
0.
- Example string where all addresses except for 0x00, 0x01 and 0xb0
+ Example string where all adresses except for 0x00, 0x01 and 0xb0
receive the value 0 by default::
'
@@ -326,17 +338,17 @@ class MicroMemory(Module):
for line in lines:
if line: # last line is empty from split with \n
line_data = line.split(": ")
- address = int(line_data[0], 16)
+ adress = int(line_data[0], 16)
value = int(line_data[1], 16)
- self.memory[address] = value
+ self.memory[adress] = value
def save_state_to_file(self, file_path: str) -> None:
"""Tries to save the modules state to a given file."""
file = open(file_path, "a")
file.write(self.name + ":\n")
for index, value in enumerate(self.memory):
- # Write the address in hex and add ': ' to the end
- file.write(hex(index)[2:].rjust(self.address_padding, "0") + ": ")
+ # Write the adress in hex and add ': ' to the end
+ file.write(hex(index)[2:].rjust(self.adress_padding, "0") + ": ")
# Write the value in hex
file.write(hex(value)[2:].rjust(self.value_padding, "0"))
file.write("\n")
@@ -346,7 +358,7 @@ class MicroMemory(Module):
def get_largest_mem_adr(self) -> int:
"""Helper function for pretty_print that returns the length of
- the largest address in the memory to print for a module.
+ the largest adress in the memory to print for a module.
"""
return len(str(len(self.memory)))
diff --git a/src/simudator/processor/mia/modules/pc.py b/src/simudator/processor/mia/modules/pc.py
index 575c4b65fde008511a6f184836c6e9cd43a4c973..4918b451a2dc903d0164fbe2cb0697043485798c 100644
--- a/src/simudator/processor/mia/modules/pc.py
+++ b/src/simudator/processor/mia/modules/pc.py
@@ -17,6 +17,8 @@ class PC(Module, MiaBusConnector):
value on the bus. If both are true it does nothing.
"""
+ __slots__ = ("bus_id", "bus_control_s", "value", "increase_by_one")
+
def __init__(
self,
p: Signal,
@@ -50,7 +52,7 @@ class PC(Module, MiaBusConnector):
self.signals["out_content"].update_value(None)
def update_register(self) -> None:
- """Updates the value of the PC according to the signals sent by the micro memory.
+ """Updates the value of the PC according to the signals sent by the micro memory.
If the program counter recives 'True' from both signals it
should do nothing and wait for the next cycle.
@@ -121,4 +123,3 @@ class PC(Module, MiaBusConnector):
def print_module(self) -> None:
print("", self.name, "\n -----", "\n value: ", hex(self.value))
-