From 6e517c6b70051b2d1a3c2076ac2f2308c05bd9c4 Mon Sep 17 00:00:00 2001
From: Martin <martin.hogstedt@hotmail.com>
Date: Mon, 8 Jul 2024 13:31:12 +0200
Subject: [PATCH] moved name from state to parameter and updated/added tests
---
src/simudator/core/module.py | 4 +-
src/simudator/core/modules/mux.py | 2 +-
src/simudator/core/modules/register.py | 2 +-
.../module_graphics_item.py | 4 +-
src/simudator/processor/mia/modules/ir.py | 14 ++---
src/simudator/processor/mia/modules/lc.py | 4 +-
.../processor/mia/modules/mia_grx.py | 13 ++---
src/simudator/processor/mia/modules/pc.py | 14 ++---
test/test_core/test_demux.py | 8 ++-
test/test_core/test_memory.py | 48 +++++++++++++---
test/test_core/test_mux.py | 9 +--
test/test_core/test_register.py | 10 ++--
test/test_mia/test_ir.py | 55 +++++++++++++++++++
test/test_mia/test_lc.py | 10 +++-
test/test_mia/test_pc.py | 12 ++--
15 files changed, 150 insertions(+), 59 deletions(-)
diff --git a/src/simudator/core/module.py b/src/simudator/core/module.py
index 37591ab..396869b 100644
--- a/src/simudator/core/module.py
+++ b/src/simudator/core/module.py
@@ -76,7 +76,6 @@ class Module:
each state variable.
"""
state_dict = dict()
- state_dict["name"] = self.name
return state_dict
def get_parameter(self) -> dict[str, Any]:
@@ -94,6 +93,7 @@ class Module:
each parameter variable.
"""
param_dict = dict()
+ param_dict["name"] = self.name
return param_dict
def get_gui_state(self) -> dict:
@@ -118,7 +118,7 @@ class Module:
state : dict[str, Any]
Module state represented as a dictionary.
"""
- self.name = state["name"]
+ pass
def get_output_signals(self) -> list[Signal]:
"""Return the output signals of the module.
diff --git a/src/simudator/core/modules/mux.py b/src/simudator/core/modules/mux.py
index bb193b6..4a1ff90 100644
--- a/src/simudator/core/modules/mux.py
+++ b/src/simudator/core/modules/mux.py
@@ -87,7 +87,7 @@ class Mux(Module):
return state
def get_parameter(self) -> dict[str, Any]:
- parameter = super().get_state()
+ parameter = super().get_parameter()
parameter["bit_length"] = self._bit_length
return parameter
diff --git a/src/simudator/core/modules/register.py b/src/simudator/core/modules/register.py
index 748c0c2..1d066ed 100644
--- a/src/simudator/core/modules/register.py
+++ b/src/simudator/core/modules/register.py
@@ -84,7 +84,7 @@ class Register(Module):
The state of the register to load. Should contain the keys "name"
and "value" with values of type ``str`` and ``int`` respectively.
"""
- self.name = state["name"]
+ super().set_state(state)
self._value = state["value"]
def reset(self) -> None:
diff --git a/src/simudator/gui/module_graphics_item/module_graphics_item.py b/src/simudator/gui/module_graphics_item/module_graphics_item.py
index b4768f7..89d8e9a 100644
--- a/src/simudator/gui/module_graphics_item/module_graphics_item.py
+++ b/src/simudator/gui/module_graphics_item/module_graphics_item.py
@@ -184,7 +184,7 @@ class ModuleGraphicsItem(QGraphicsObject, QGraphicsItem):
"""
This function will be run when the edit module actions
dialog is okey'd by the user.
- It will take the info from the dialog and edit the module accordinly.
+ It will take the info from the dialog and edit the module accordingly.
"""
try:
parsed_value = ast.literal_eval(value)
@@ -279,7 +279,7 @@ class ModuleGraphicsItem(QGraphicsObject, QGraphicsItem):
def generateActions(self) -> None:
"""
- Generates the default actions avalible in the context menu ofthe item.
+ Generates the default actions available in the context menu ofthe item.
All other modules will also have these but may also add more actions.
"""
diff --git a/src/simudator/processor/mia/modules/ir.py b/src/simudator/processor/mia/modules/ir.py
index aec64c9..e3fd890 100644
--- a/src/simudator/processor/mia/modules/ir.py
+++ b/src/simudator/processor/mia/modules/ir.py
@@ -78,14 +78,12 @@ class IR(Module, MiaBusConnector):
self.output_register()
def get_state(self) -> dict[str, Any]:
- state = {
- "name": self.name,
- "value": self._instruction,
- "op": self._op,
- "grx": self._grx,
- "m": self._m,
- "a": self._a,
- }
+ state = super().get_state()
+ state["value"] = self._instruction
+ state["op"] = self._op
+ state["grx"] = self._grx
+ state["m"] = self._m
+ state["a"] = self._a
return state
def get_gui_state(self) -> dict:
diff --git a/src/simudator/processor/mia/modules/lc.py b/src/simudator/processor/mia/modules/lc.py
index 9380ae6..6f815a3 100644
--- a/src/simudator/processor/mia/modules/lc.py
+++ b/src/simudator/processor/mia/modules/lc.py
@@ -144,7 +144,7 @@ class LC(Module):
def get_state(self) -> dict[str, Any]:
"""Returns a dict of the loop counter state.
- These states are changable via set_states.
+ These states are changeable via set_states.
Returns
-------
@@ -152,7 +152,6 @@ class LC(Module):
The state of the loop counter.
"""
state = dict()
- state["name"] = self.name
state["value"] = self._value
state["read_from_bus"] = self._read_from_bus
state["read_from_uADR"] = self._read_from_uADR
@@ -174,7 +173,6 @@ class LC(Module):
def set_state(self, state: dict[str, Any]) -> None:
"""Sets the loop counter state to one given in dict."""
- self.name = state["name"]
self._value = state["value"]
if "bit_length" in state:
self._bit_length = state["bit_length"]
diff --git a/src/simudator/processor/mia/modules/mia_grx.py b/src/simudator/processor/mia/modules/mia_grx.py
index 6530e22..14c2cc2 100644
--- a/src/simudator/processor/mia/modules/mia_grx.py
+++ b/src/simudator/processor/mia/modules/mia_grx.py
@@ -101,12 +101,10 @@ class GRX(Module, MiaBusConnector):
def get_state(self) -> dict[str, Any]:
"""
Returns a dict of the grx state.
- These states are changable via set_states.
+ These states are changeable via set_states.
"""
- state = {
- "name": self.name,
- "registers": self.registers[:],
- }
+ state = super().get_state()
+ state["registers"] = self.registers[:]
return state
def get_gui_state(self) -> dict:
@@ -120,7 +118,6 @@ class GRX(Module, MiaBusConnector):
"""
Sets the grx state to one given in dict.
"""
- self.name = state["name"]
self.registers = state["registers"]
def reset(self) -> None:
@@ -150,9 +147,9 @@ class GRX(Module, MiaBusConnector):
for line in lines:
if line: # last line is empty from split with \n
line_data = line.split(": ")
- adress = int(line_data[0], 16)
+ address = int(line_data[0], 16)
value = int(line_data[1], 16)
- self.registers[adress] = value
+ self.registers[address] = value
def print_module(self):
print(
diff --git a/src/simudator/processor/mia/modules/pc.py b/src/simudator/processor/mia/modules/pc.py
index 54f71b1..660ec89 100644
--- a/src/simudator/processor/mia/modules/pc.py
+++ b/src/simudator/processor/mia/modules/pc.py
@@ -82,15 +82,14 @@ class PC(Module, MiaBusConnector):
def get_state(self) -> dict[str, Any]:
"""Returns a dict of the program counter state.
- These states are changable via set_states.
+ These states are changeable via set_states.
Returns
-------
dict[str, Any]
The state of the program counter.
"""
- state = dict()
- state["name"] = self.name
+ state = super().get_state()
state["value"] = self._value
state["increment"] = self._increase_by_one
return state
@@ -102,11 +101,11 @@ class PC(Module, MiaBusConnector):
Returns
-------
dict[str, Any]
- The paramter of the program counter.
+ The parameter of the program counter.
"""
- paramter = Module.get_parameter(self)
- paramter["bit_length"] = self._bit_length
- return paramter
+ parameter = super().get_parameter()
+ parameter["bit_length"] = self._bit_length
+ return parameter
def get_gui_state(self) -> dict:
state = {
@@ -117,7 +116,6 @@ class PC(Module, MiaBusConnector):
def set_state(self, state: dict[str, Any]) -> None:
"""Sets the program counter state to one given in dict."""
- self.name = state["name"]
self._value = state["value"]
if "increment" in state:
self._increase_by_one = state["increment"]
diff --git a/test/test_core/test_demux.py b/test/test_core/test_demux.py
index 132b572..80b40ff 100644
--- a/test/test_core/test_demux.py
+++ b/test/test_core/test_demux.py
@@ -35,7 +35,8 @@ def test_get_state():
state = demux.get_state()
- assert state["name"] == "Demux"
+ assert len(state.keys()) == 1
+
assert state["value"] == 7
@@ -49,12 +50,14 @@ def test_get_parameter():
parameter = demux.get_parameter()
+ assert len(parameter.keys()) == 2
+
assert parameter["bit_length"] == 5
+ assert parameter["name"] == "Demux"
def test_set_state():
state = dict()
- state["name"] = "Demux"
state["value"] = 6
state["bit_length"] = 2
@@ -68,7 +71,6 @@ def test_set_state():
demux.set_state(state)
state = demux.get_state()
- assert state["name"] == "Demux"
assert state["value"] == 6
diff --git a/test/test_core/test_memory.py b/test/test_core/test_memory.py
index 4ded14f..b2c343f 100644
--- a/test/test_core/test_memory.py
+++ b/test/test_core/test_memory.py
@@ -8,8 +8,8 @@ def test_memory():
input_s = Signal(cpu, value=0)
output_s = Signal(cpu, value=0)
control_s = Signal(cpu, value=0)
- adress_s = Signal(cpu, value=0)
- memory = Memory(input_s, output_s, control_s, adress_s, 2)
+ address_s = Signal(cpu, value=0)
+ memory = Memory(input_s, output_s, control_s, address_s, 2)
cpu.add_module(memory)
# Test that the memory is not written to before a new clock pulse
@@ -22,15 +22,15 @@ def test_memory():
cpu.do_tick()
assert output_s.get_value() == 1
- # Test that reading from the adress does not write to it
+ # Test that reading from the address does not write to it
control_s.update_value(0)
input_s.update_value(0)
memory.update_logic() # Simulate update at the end of current clock pulse
cpu.do_tick()
assert output_s.get_value() == 1
- # Test that reading from another adress works
- adress_s.update_value(1)
+ # Test that reading from another address works
+ address_s.update_value(1)
memory.update_logic()
assert output_s.get_value() == 0
cpu.do_tick()
@@ -42,8 +42,40 @@ def test_get_parameter():
input_s = Signal(cpu, value=0)
output_s = Signal(cpu, value=0)
control_s = Signal(cpu, value=0)
- adress_s = Signal(cpu, value=0)
- memory = Memory(input_s, output_s, control_s, adress_s, 2)
+ address_s = Signal(cpu, value=0)
+ memory = Memory(input_s, output_s, control_s, address_s, 2)
parameter = memory.get_parameter()
- assert len(parameter.keys()) == 0
+ assert len(parameter.keys()) == 1
+
+ assert parameter["name"] == "Memory"
+
+
+def test_get_state():
+
+ cpu = Processor()
+ input_s = Signal(cpu, value=0)
+ output_s = Signal(cpu, value=0)
+ control_s = Signal(cpu, value=0)
+ address_s = Signal(cpu, value=0)
+ memory = Memory(input_s, output_s, control_s, address_s, 2)
+
+ state = memory.get_state()
+
+ assert len(state.keys()) == 3
+
+ assert state["is_write"] == False
+ assert state["current_address"] == 0
+ assert state["memory"] == [0, 0]
+
+ memory._is_write = True
+ memory._current_address = 1
+ memory._memory = [1, 2]
+
+ state = memory.get_state()
+
+ assert len(state.keys()) == 3
+
+ assert state["is_write"] == True
+ assert state["current_address"] == 1
+ assert state["memory"] == [1, 2]
diff --git a/test/test_core/test_mux.py b/test/test_core/test_mux.py
index 18dca41..838bcfb 100644
--- a/test/test_core/test_mux.py
+++ b/test/test_core/test_mux.py
@@ -35,7 +35,8 @@ def test_get_state():
state = mux.get_state()
- assert state["name"] == "Mux"
+ assert len(state.keys()) == 1
+
assert state["value"] == 7
@@ -49,14 +50,15 @@ def test_get_parameter():
parameter = mux.get_parameter()
+ assert len(parameter.keys()) == 2
+
assert parameter["bit_length"] == 5
+ assert parameter["name"] == "Mux"
def test_set_state():
state = dict()
- state["name"] = "Mux"
state["value"] = 6
- state["bit_length"] = 2
state["mask"] = 3
cpu = Processor()
@@ -68,7 +70,6 @@ def test_set_state():
mux.set_state(state)
- assert mux.name == "Mux"
assert mux._value == 6
diff --git a/test/test_core/test_register.py b/test/test_core/test_register.py
index 45f9c3e..ca11579 100644
--- a/test/test_core/test_register.py
+++ b/test/test_core/test_register.py
@@ -22,10 +22,9 @@ def test_set_state():
s = Signal(cpu)
register = Register(s, s, 4)
- state = {"name": "Reg", "value": 14}
+ state = {"value": 14}
register.set_state(state)
- assert register.name == "Reg"
assert register._value == 14
@@ -35,7 +34,8 @@ def test_get_state():
register = Register(s, s, 13, "register")
state = register.get_state()
- assert state["name"] == "register"
+ assert len(state.keys()) == 1
+
assert state["value"] == 13
@@ -45,7 +45,9 @@ def test_get_parameter():
register = Register(s, s, 13, "register")
parameter = register.get_parameter()
- assert len(parameter.keys()) == 0
+ assert len(parameter.keys()) == 1
+
+ assert parameter["name"] == "register"
def test_signal_propagation():
diff --git a/test/test_mia/test_ir.py b/test/test_mia/test_ir.py
index 09dff38..e2ac54b 100644
--- a/test/test_mia/test_ir.py
+++ b/test/test_mia/test_ir.py
@@ -50,3 +50,58 @@ def test_save_state():
ir.save_state_to_file(dummy_file_path)
mock_file.assert_called_once_with(dummy_file_path, "a")
mock_file().write.assert_called_once_with(content)
+
+
+def test_get_state():
+ cpu = Processor()
+ s = Signal(cpu)
+ ir = IR(
+ s,
+ s,
+ s,
+ s,
+ s,
+ s,
+ )
+ ir._instruction = 1
+ ir._op = 2
+ ir._grx = 3
+ ir._m = 4
+ ir._a = 5
+ state = ir.get_state()
+
+ assert len(state.keys()) == 5
+
+ assert state["value"] == 1
+ assert state["op"] == 2
+ assert state["grx"] == 3
+ assert state["m"] == 4
+ assert state["a"] == 5
+
+ ir.reset()
+ state = ir.get_state()
+
+ assert len(state.keys()) == 5
+
+ assert state["value"] == 0
+ assert state["op"] == 0
+ assert state["grx"] == 0
+ assert state["m"] == 0
+ assert state["a"] == 0
+
+
+def test_get_parameter():
+ cpu = Processor()
+ s = Signal(cpu)
+ ir = IR(
+ s,
+ s,
+ s,
+ s,
+ s,
+ s,
+ )
+ parameter = ir.get_parameter()
+ assert len(parameter.keys()) == 1
+
+ assert parameter["name"] == "IR"
diff --git a/test/test_mia/test_lc.py b/test/test_mia/test_lc.py
index 26e1bea..a45a076 100644
--- a/test/test_mia/test_lc.py
+++ b/test/test_mia/test_lc.py
@@ -157,7 +157,7 @@ def test_get_state():
cpu.do_tick()
state = lc.get_state()
- assert state["name"] == "LC"
+ assert len(state.keys()) == 4
assert state["value"] == 255
assert state["read_from_bus"] is False
assert state["read_from_uADR"] is False
@@ -167,7 +167,7 @@ def test_get_state():
cpu.do_tick()
state = lc.get_state()
- assert state["name"] == "LC"
+ assert len(state.keys()) == 4
assert state["value"] == 100
assert state["read_from_bus"] is True
assert state["read_from_uADR"] is False
@@ -177,7 +177,7 @@ def test_get_state():
cpu.do_tick()
state = lc.get_state()
- assert state["name"] == "LC"
+ assert len(state.keys()) == 4
assert state["value"] == 10
assert state["read_from_bus"] is False
assert state["read_from_uADR"] is True
@@ -194,7 +194,11 @@ def test_get_parameter():
lc = LC(mM_control_s, bus_input_s, l_flag_s, mM_uADR_s)
parameter = lc.get_parameter()
+
+ assert len(parameter.keys()) == 2
+
assert parameter["bit_length"] == 8
+ assert parameter["name"] == "LC"
def test_save_state():
diff --git a/test/test_mia/test_pc.py b/test/test_mia/test_pc.py
index 90084de..7d3d9cd 100644
--- a/test/test_mia/test_pc.py
+++ b/test/test_mia/test_pc.py
@@ -177,7 +177,9 @@ def test_get_state():
cpu.do_tick()
state = pc.get_state()
- assert state["name"] == "PC"
+
+ assert len(state.keys()) == 2
+
assert state["value"] == 13
assert state["increment"] is True
@@ -193,8 +195,11 @@ def test_get_parameter():
pc = PC(p, bus_in, bus_out, control, bus_id, "PC", 13)
parameter = pc.get_parameter()
- assert len(parameter.keys()) == 1
+
+ assert len(parameter.keys()) == 2
+
assert parameter["bit_length"] == 8
+ assert parameter["name"] == "PC"
def test_set_state():
@@ -209,10 +214,9 @@ def test_set_state():
pc = PC(p, bus_in, bus_out, control, bus_id, "PC", 13)
- state = {"name": "pc", "value": 23, "increment": True}
+ state = {"value": 23, "increment": True}
pc.set_state(state)
- assert pc.name == "pc"
assert pc._value == 23
assert pc._increase_by_one is True
--
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