diff --git a/src/simudator/core/module.py b/src/simudator/core/module.py
index 66d73fa4ab445dccb0a7d07cb51cb54034fdd278..d97eb36fb0d061dd33fec136d3a7520dade0a3d0 100644
--- a/src/simudator/core/module.py
+++ b/src/simudator/core/module.py
@@ -1,5 +1,7 @@
from __future__ import annotations
+from simudator.core.signal import Signal
+
class Module:
"""
@@ -8,30 +10,34 @@ class Module:
such as ALU, busses, registers and more.
"""
- def __init__(self, name: str = "") -> None:
-
+ def __init__(self, signals: dict[str, Signal], name: str = "") -> None:
self.name = name
+ self.signals = signals
+
+ for key, signal in self.signals.items():
+ if key[0:2] == "in":
+ signal.add_destination(self)
def update_register(self) -> None:
"""
Simulates module behaviour for saving input into the internal state
during a clock tick. Exact behaviour is specifid in each module type.
"""
- pass
+ raise NotImplemented
def output_register(self) -> None:
"""
Simulates module behaviour for giving data to output signals
during a clock tick. Exact behaviour is specifid in each module type.
"""
- pass
+ raise NotImplemented
def update_logic(self) -> None:
"""
Simulates behaviour for sending output using the internal state
during a clock tick. Exact behaviour is specifid in each module type.
"""
- pass
+ raise NotImplemented
def get_state(self) -> dict:
"""
@@ -56,30 +62,32 @@ class Module:
"""
self.name = state["name"]
- def get_output_signals(self) -> []:
+ def get_output_signals(self) -> list[Signal]:
"""
- Returns the modules output signals. Is implemented in specific classes.
+ Returns the modules output signals. Assumes all output signals are
+ stored with a key beginning in 'out' in the signals dictionary.
"""
- return []
+ return [signal for key, signal in self.signals.items() if key[0:3] == "out"]
- def get_input_signals(self) -> []:
+ def get_input_signals(self) -> list[Signal]:
"""
- Returns the modules input signals. Is implemented in specific classes.
+ Returns the modules input signals. Assumes all input signals are stored
+ with a key beginning in 'in' in the signals dictionary.
"""
- return []
+ return [signal for key, signal in self.signals.items() if key[0:2] == "in"]
def reset(self) -> None:
"""
Resets the module to its default state.
"""
- pass
+ raise NotImplemented
def load_from_str(self, state_string):
"""
Sets the moudles state according to a string
Each module type will decide how the string should be formated.
"""
- pass
+ raise NotImplemented
def get_longest_line_len(self, ignore_keys=None) -> int:
"""
@@ -112,7 +120,7 @@ class Module:
Tries to save the modules state to a given file.
Returns true on success and false if something went wrong.
"""
- pass
+ raise NotImplemented
def __str__(self) -> str:
return self.name
diff --git a/src/simudator/core/modules/demux.py b/src/simudator/core/modules/demux.py
index 157d6089f53f74ffea2b4a17bef0d6da4e821e3b..bdd0ff671c96946202aa772f4295fef9bc88c916 100644
--- a/src/simudator/core/modules/demux.py
+++ b/src/simudator/core/modules/demux.py
@@ -11,16 +11,19 @@ class Demux(Module):
signal 'from_demux_s'.
"""
- def __init__(self, from_demux: Signal, bit_length: int,
+ def __init__(self, control: Signal, bit_length: int,
input: Signal, outputs: list[Signal] = [],
name="demux", value=0) -> None:
- # Name
- super().__init__(name)
# Signals
- self.from_demux_s = from_demux
- self.outputs = outputs
- self.input_s = input
+ signals = {
+ "in_control": control,
+ "in_input": input,
+ }
+ for i, s in enumerate(outputs):
+ signals[f"out_output_{i}"] = s
+
+ super().__init__(signals, name)
# mask and bit_length
self.bit_length = bit_length
@@ -29,14 +32,11 @@ class Demux(Module):
# Value to be read/written
self.value = value
- # Set the demux as destination of its input signal
- self.input_s.add_destination(self)
-
def update_register(self) -> None:
"""
Read the input value and update the value of the demux.
"""
- input_value = self.input_s.get_value()
+ input_value = self.signals["in_input"].get_value()
self.value = input_value & self.mask
@@ -45,8 +45,9 @@ class Demux(Module):
Read which signal to write to from the control signal
'from_demux_s' and forward the input to that output signal.
"""
- output_index = self.from_demux_s.get_value()
- self.outputs[output_index].update_value(self.value)
+ output_index = self.signals["in_control"].get_value()
+ output_signal_key = f"out_output_{output_index}"
+ self.signals[output_signal_key].update_value(self.value)
def update_logic(self):
"""
@@ -54,7 +55,7 @@ class Demux(Module):
"""
pass
- def get_state(self) -> dict[str: Any]:
+ def get_state(self) -> dict[str, Any]:
"""
Returns a dict of the demux state.
"""
diff --git a/src/simudator/core/modules/memory.py b/src/simudator/core/modules/memory.py
index d71774550dd0565f864d93d7261f4b64a7f6a6b2..775f76f2b3773014e89cf69010ce0e4047117cea 100644
--- a/src/simudator/core/modules/memory.py
+++ b/src/simudator/core/modules/memory.py
@@ -14,39 +14,36 @@ class Memory(Module):
input_signal: Signal,
output_signal: Signal,
control_signal: Signal,
- adress_signal: Signal,
+ address_signal: Signal,
size: int,
value_padding: int = 2,
- adress_padding: int = 2,
+ address_padding: int = 2,
name="Memory",
) -> None:
- super().__init__(name)
- # Input signals
- self.input_s = input_signal
- self.control_s = control_signal
- self.adress_s = adress_signal
+ # signals
+ signals = {
+ "in_input": input_signal,
+ "in_control": control_signal,
+ "in_address": address_signal,
+ "out_content": output_signal,
+ }
- # Output signals
- self.output_s = output_signal
+ # Init super class
+ super().__init__(signals, name)
# Internal state
self.memory = [0 for _ in range(size)]
- self.current_adress = 0
+ self.current_address = 0
self.is_write = False
- # Register self as destination of input signals
- self.input_s.add_destination(self)
- self.control_s.add_destination(self)
- self.adress_s.add_destination(self)
-
# Values used to format the strings when saving state to file
- self.adress_padding = adress_padding
+ self.address_padding = address_padding
self.value_padding = value_padding
def update_register(self):
if self.is_write:
- self.memory[self.current_adress] = self.input_s.get_value()
+ self.memory[self.current_address] = self.signals["in_input"].get_value()
def output_register(self) -> None:
pass
@@ -54,42 +51,30 @@ class Memory(Module):
# in case the memory was written to in update_register()
def update_logic(self) -> None:
- if (
- self.adress_s.get_value() is not None
- and self.control_s.get_value() is not None
- ):
- self.is_write = self.control_s.get_value()
- self.current_adress = self.adress_s.get_value()
- self.output_s.update_value(self.memory[self.current_adress])
-
- def get_input_signal(self) -> Signal:
- return self.input_s
-
- def get_output_signal(self) -> Signal:
- return self.output_s
-
- def get_adress_signal(self) -> Signal:
- return self.adress_s
-
- def get_control_signal(self) -> Signal:
- return self.control_s
+ adr_sig = self.signals["in_address"]
+ ctrl_sig = self.signals["in_control"]
+ out_sig = self.signals["out_content"]
+ if adr_sig.get_value() is not None and ctrl_sig.get_value() is not None:
+ self.is_write = ctrl_sig.get_value()
+ self.current_address = adr_sig.get_value()
+ out_sig.update_value(self.memory[self.current_address])
def print_module(self) -> None:
print("", self.name, "\n -----")
- for adress, value in enumerate(self.memory):
+ for address, value in enumerate(self.memory):
if value:
- print("", str(hex(adress)), "", str(hex(value)), "\n")
+ print("", str(hex(address)), "", str(hex(value)), "\n")
def get_state(self) -> dict:
state = super().get_state()
state["is_write"] = self.is_write
- state["current_adress"] = self.current_adress
+ state["current_address"] = self.current_address
state["memory"] = self.memory[:]
return state
def get_gui_state(self) -> dict:
state = super().get_gui_state()
- state["current_adress"] = self.current_adress
+ state["current_address"] = self.current_address
state["memory"] = self.memory[:]
return state
@@ -97,24 +82,27 @@ class Memory(Module):
super().set_state(state)
if "is_write" in state:
self.is_write = state["is_write"]
- if "current_adress" in state:
- self.current_adress = state["current_adress"]
+ if "current_address" in state:
+ self.current_address = state["current_address"]
if "memory" in state:
self.memory = state["memory"]
def reset(self) -> None:
"""
- Reset the memory to 0 for each adress.
+ Reset the memory to 0 for each address.
"""
for i in range(len(self.memory)):
self.memory[i] = 0
- def get_longest_line_len(self, ignore_keys=[]) -> int:
+ def get_longest_line_len(self, ignore_keys=None) -> int:
"""
Helper function for pretty_print that returns the length of
the longest value in the memory to print for a module.
"""
+ if ignore_keys is None:
+ ignore_keys = []
+
longest_memory_line = 0
for value in self.memory:
@@ -127,7 +115,7 @@ class Memory(Module):
def get_largest_mem_adr(self) -> int:
"""
Helper function for pretty_print that returns the length of
- the largest adress in the memory to print for a module.
+ the largest address in the memory to print for a module.
"""
return len(str(len(self.memory)))
@@ -138,8 +126,8 @@ class Memory(Module):
file = open(file_path, "a")
file.write(self.name + ":\n")
for index, value in enumerate(self.memory):
- # Write the adress in hex and add ': ' to the end
- file.write(hex(index)[2:].rjust(self.adress_padding, "0") + ": ")
+ # Write the address in hex and add ': ' to the end
+ file.write(hex(index)[2:].rjust(self.address_padding, "0") + ": ")
# Write the value in hex
file.write(hex(value)[2:].rjust(self.value_padding, "0"))
file.write("\n")
diff --git a/src/simudator/core/modules/mux.py b/src/simudator/core/modules/mux.py
index e3a355a2774ce40ad4f2a9c6496d68b2070f65ac..0d50b4463323740d3f8d9e7b4d6fb529ea1e06e5 100644
--- a/src/simudator/core/modules/mux.py
+++ b/src/simudator/core/modules/mux.py
@@ -19,14 +19,17 @@ class Mux(Module):
name="mux",
value=0
) -> None:
- print("in: ", inputs)
- # Name
- super().__init__(name)
# Signals
- self.to_mux_s = to_mux
- self.output_s = output
- self.inputs = inputs
+ signals = {
+ "in_control": to_mux,
+ "out": output,
+ }
+ for i, s in enumerate(inputs):
+ signals[f"in_input_{i}"] = s
+
+ # Init super class
+ super().__init__(signals, name)
# mask and bit_length
self.bit_length = bit_length
@@ -35,25 +38,21 @@ class Mux(Module):
# Value to be read/written
self.value = value
- # Set mux as destination of all input signals
- if self.inputs: # make sure inputs is not empty
- for signal in self.inputs:
- signal.add_destination(self)
-
def update_register(self) -> None:
"""
Read which signal to read from the control signal
'to_mux_s' and forward that signal to the output.
"""
- input_index = self.to_mux_s.get_value()
- input_value = self.inputs[input_index].get_value()
+ input_index = self.signals["in_control"].get_value()
+ input_signal_key = f"in_input_{input_index}"
+ input_value = self.signals[input_signal_key].get_value()
self.value = input_value & self.mask
def output_register(self):
"""
Output the value of the mux to its output.
"""
- self.output_s.update_value(self.value)
+ self.signals["out"].update_value(self.value)
def update_logic(self):
"""
@@ -61,7 +60,7 @@ class Mux(Module):
"""
pass
- def get_state(self) -> dict[str: Any]:
+ def get_state(self) -> dict[str, Any]:
"""
Returns a dict of the mux state.
"""
diff --git a/src/simudator/core/modules/register.py b/src/simudator/core/modules/register.py
index 08ee3c1821f8b87e1fa1682124e834243137300d..f76219ce219ce12588744dbbb91708dbbdd6da7c 100644
--- a/src/simudator/core/modules/register.py
+++ b/src/simudator/core/modules/register.py
@@ -15,23 +15,22 @@ class Register(Module):
output_signal: Signal,
value: Any = 0, name: str = "Register") -> None:
- # set the registers name
- super().__init__(name)
-
# signals
- self.input_s = input_signal
- self.output_s = output_signal
- self.value = value
+ signals = {
+ "in_content": input_signal,
+ "out_content": output_signal,
+ }
- # set the register as destination of its input signal
- self.input_s.add_destination(self)
+ # init the instance
+ super().__init__(signals, name)
+ self.value = value
def update_register(self) -> None:
"""
Propagate the input signal to the registers internal state.
Throw away bits larger than the length of the register.
"""
- input_value = self.input_s.get_value()
+ input_value = self.signals["in_content"].get_value()
if input_value is None:
return
self.value = input_value
@@ -42,7 +41,7 @@ class Register(Module):
It is the response of the destination to know when it should
read the output.
"""
- self.output_s.update_value(self.value)
+ self.signals["out_content"].update_value(self.value)
def update_logic(self):
"""
@@ -50,7 +49,7 @@ class Register(Module):
"""
pass
- def get_state(self) -> dict[str: Any]:
+ def get_state(self) -> dict[str, Any]:
"""
Returns a dict of the register state.
These states are changable via set_states.
@@ -63,7 +62,7 @@ class Register(Module):
state = self.get_state()
return state
- def set_state(self, state: dict[str: Any]) -> None:
+ def set_state(self, state: dict[str, Any]) -> None:
"""
Sets the register state to one given in dict.
"""
@@ -76,12 +75,6 @@ class Register(Module):
"""
self.value = 0
- def get_output_signals(self) -> []:
- return [self.output_s]
-
- def get_input_signals(self) -> []:
- return [self.input_s]
-
def save_state_to_file(self, file_path: str) -> None:
"""
Tries to save the modules state to a given file.
@@ -127,7 +120,7 @@ class IntegerRegister(Register):
super().update_register()
self.value = self.value & self.mask
- def get_state(self) -> dict[str: Any]:
+ def get_state(self) -> dict[str, Any]:
"""
Returns a dict of the register state.
These states are changable via set_states.
@@ -136,7 +129,7 @@ class IntegerRegister(Register):
state["bit_length"] = self.bit_length
return state
- def set_state(self, state: dict[str: Any]) -> None:
+ def set_state(self, state: dict[str, Any]) -> None:
"""
Sets the register state to one given in dict.
"""
@@ -173,15 +166,6 @@ class Flag(IntegerRegister):
super().__init__(input_signal=input_signal, output_signal=output_signal,
bit_length=bit_length, value=value, name=name)
- def output_register(self) -> None:
- """
- Propagate the value of the flag to the output signal.
-
- It is the response of the destination to know when it should
- read the output.
- """
- self.output_s.update_value(self.value)
-
def update_logic(self):
"""
The flag has no logic but it still need to be updated during
@@ -189,7 +173,7 @@ class Flag(IntegerRegister):
should update the same tick as the change that causes the flag
to activate (ex: loop counter reaches zero -> set L flag to 1)
"""
- input_value = self.input_s.get_value()
+ input_value = self.signals["in_content"].get_value()
self.value = input_value & self.mask
def get_gui_state(self) -> dict:
diff --git a/src/simudator/core/processor.py b/src/simudator/core/processor.py
index feb67121d09825d986a4e46a16addfc62e3bf78b..91882c7925157c8cfaca04164b8fa2de6f03f894 100644
--- a/src/simudator/core/processor.py
+++ b/src/simudator/core/processor.py
@@ -31,7 +31,7 @@ class Processor:
self.breakpoints: dict[int, Breakpoint] = {}
self.breakpoint_reached = False
self.last_breakpoint = None
- self.cycles_to_save = 1000
+ self.cycles_to_save = 10000
self.removed_cycles = 0
self.max_line_len = 170
self.line_seperator = "-"
@@ -212,14 +212,16 @@ class Processor:
def reset(self):
"""
- Resets all values in the processor and
- then does one propogation to the signals.
- Is run before running the processor to propogate values in
- module out into signals of the system.
+ Reset the processor to its start state.
+
+ This resets all modules and removes any saved states for undoing clock
+ cycles. A round of value propagation is done to reset signals too.
"""
self.clock = 0
self.module_history.clear()
self.signal_history.clear()
+ self.removed_cycles = 0
+ self.assembly_cycles = [0]
for module in self.modules.values():
module.reset()
@@ -378,6 +380,7 @@ class Processor:
file.close()
for module in self.modules.values():
+ print(module)
module.save_state_to_file(file_path)
def pretty_print(self) -> None:
@@ -504,8 +507,10 @@ class Processor:
def pretty_print_names(self, module_to_line_length: dict[Module, int]) -> None:
"""
- Prints the name of the modules in one row with enough
- added spacing between the names so that the modules
+ Prints the name of the modules in one row, but pretty.
+
+
+ Adds spacing between the names so that the modules
longest field will have space to be printed below.
"""
name_string = ""
@@ -557,8 +562,9 @@ class Processor:
def get_most_fields(self, modules: dict[Module:int], ignore_keys=[]) -> int:
"""
- Return the most number of a fields a module has. Can optionally
- ignore keys.
+ Return the most number of a fields a module has.
+
+ Can optionally ignore keys.
"""
fields = 0
for module in modules:
diff --git a/src/simudator/gui/gui.py b/src/simudator/gui/gui.py
index 88f8a27d084ea39cd1d6e3c769693f0ef165f56f..825164f619a955d230c9b401701ba3ab7891ebc8 100644
--- a/src/simudator/gui/gui.py
+++ b/src/simudator/gui/gui.py
@@ -226,14 +226,18 @@ class GUI(QMainWindow):
self.breakpoint_action.triggered.connect(self.openBreakpointWindow)
# Create 'update value' window button
- self.update_value_action = QAction("Update values while running", self, checkable=True)
+ self.update_value_action = QAction(
+ "Update values while running", self, checkable=True
+ )
self.update_value_action.setChecked(False)
self.update_value_action.setStatusTip("Toggle value updates while running.")
self.update_value_action.triggered.connect(self.toggle_value_update_on_run)
# Create 'set delay' window button
self.set_delay_action = QAction("Set update delay", self)
- self.set_delay_action.setStatusTip("Sets the delay between each update when the cpu is running.")
+ self.set_delay_action.setStatusTip(
+ "Sets the delay between each update when the cpu is running."
+ )
self.set_delay_action.triggered.connect(self.set_update_delay)
# Create Tools menu for tool actions actions
@@ -256,7 +260,7 @@ class GUI(QMainWindow):
self.stop_action.triggered.connect(self.stopToolBarButtonClick)
toolbar.addAction(self.stop_action)
- # Add Asm label
+ # Add Asm label
self.clock_cycle_label = QLabel("Clock cycle: ", self)
toolbar.addWidget(self.clock_cycle_label)
@@ -303,7 +307,7 @@ class GUI(QMainWindow):
spacing.setFixedWidth(10)
toolbar.addWidget(spacing)
- # Add Asm label
+ # Add Asm label
self.asm_label = QLabel("Assembler Instructions: ", self)
toolbar.addWidget(self.asm_label)
@@ -370,7 +374,7 @@ class GUI(QMainWindow):
def updateCpuClockCycle(self) -> None:
"""
- Update the clock cycle counter.
+ Update the clock cycle counter.
Used while the program is running to show the user nothing has crashed.
"""
@@ -392,7 +396,6 @@ class GUI(QMainWindow):
if self.breakpoint_window is not None:
self.breakpoint_window.update()
-
"""
@Slot is used to explicitly mark a python method as a Qt slot
and specify a C++ signature for it, which is used most commonly
@@ -503,7 +506,9 @@ class GUI(QMainWindow):
steps = self.jump_value_box.value()
self.cpu_running = True
self.setDisabledWhenRunning(True)
- simulation_thread = RunThread(self.cpu, self.cpu_tick_signal, self.update_delay, False, False, steps)
+ simulation_thread = RunThread(
+ self.cpu, self.cpu_tick_signal, self.update_delay, False, False, steps
+ )
self.threadpool.start(simulation_thread)
def stepAsmToolBarButtonClick(self):
@@ -518,7 +523,9 @@ class GUI(QMainWindow):
steps = self.asm_jump_value_box.value()
self.cpu_running = True
self.setDisabledWhenRunning(True)
- simultaion_thread = RunThread(self.cpu, self.cpu_tick_signal, self.update_delay, False, True, steps)
+ simultaion_thread = RunThread(
+ self.cpu, self.cpu_tick_signal, self.update_delay, False, True, steps
+ )
self.threadpool.start(simultaion_thread)
self.updateCpuListeners()
@@ -550,8 +557,8 @@ class GUI(QMainWindow):
if self.update_all_values:
self.updateCpuListeners()
- # A signal of 0 steps signifies end of execution, i.e. the CPU has
- # halted or run the specified amount of ticks
+ # A signal of 0 steps signifies end of execution, i.e. the CPU has
+ # halted or run the specified amount of ticks
# => Enable the relevant parts of the GUI again
if steps == 0:
self.cpu_running = False
@@ -560,7 +567,9 @@ class GUI(QMainWindow):
# Inform user of reached break point
if self.cpu.breakpoint_reached:
- self.messageBox("Reached breakpoint: " + self.cpu.last_breakpoint.__str__())
+ self.messageBox(
+ "Reached breakpoint: " + self.cpu.last_breakpoint.__str__()
+ )
# Inform user of halt
if self.cpu.should_halt():
@@ -836,13 +845,15 @@ class GUI(QMainWindow):
"""
Toggles whether all values or only clock cycle is being updated each tick.
"""
- self.update_all_values = not self.update_all_values
+ self.update_all_values = not self.update_all_values
def set_update_delay(self):
"""
Sets the update delay for the visual updates while the cpu is running.
"""
- delay, ok = QInputDialog.getDouble(self, "Input Dialog", "Enter a float value:", decimals=5)
+ delay, ok = QInputDialog.getDouble(
+ self, "Input Dialog", "Enter a float value:", decimals=5
+ )
if ok:
self.update_delay = delay
diff --git a/src/simudator/gui/module_graphics_item/memory_graphic.py b/src/simudator/gui/module_graphics_item/memory_graphic.py
index 208d844c22503312509224ff48892e4fe571629f..2817042cc772ef63fbbce36395542b585fda8eec 100644
--- a/src/simudator/gui/module_graphics_item/memory_graphic.py
+++ b/src/simudator/gui/module_graphics_item/memory_graphic.py
@@ -1,3 +1,5 @@
+from math import ceil
+
from qtpy.QtCore import Qt
from qtpy.QtCore import Signal as pyqtSignal
from qtpy.QtCore import Slot
@@ -5,9 +7,8 @@ from qtpy.QtWidgets import (
QAction,
QGraphicsRectItem,
QGraphicsSimpleTextItem,
- QTextEdit,
- QVBoxLayout,
- QWidget,
+ QTableWidget,
+ QTableWidgetItem,
)
from simudator.core.modules import Memory
@@ -17,36 +18,84 @@ from simudator.gui.orientation import Orientation
from simudator.gui.port_graphics_item import PortGraphicsItem
-class MemoryWindow(QWidget):
- """
- Widget for showing content of memory
+class MemoryWindow(QTableWidget):
"""
+ A class showing the contents of a memory module in a QTableWidget.
+
+ This class assumes that the size of the memory module will remain constant.
- _ROW_LENGTH = 5
+ Parameters
+ ----------
+ memory_module: An instance of the Memory base class.
+ column_size: An integer specifying the number of columns, optional.
+
+ """
- def __init__(self, memory_module: Memory):
+ def __init__(self, memory_module: Memory, column_size=-1):
super().__init__()
- self.module = memory_module
+ self._memory = memory_module
+ self._column_size = column_size
+ self._memory_size = len(self._memory.get_state()["memory"])
+ self._set_column_size()
+ self.setColumnCount(self._column_size)
+ self.setRowCount(ceil(self._memory_size / self._column_size))
+ self.setHorizontalHeaderLabels(["+" + str(i) for i in range(4)])
- self.text = QTextEdit("")
- layout = QVBoxLayout()
- layout.addWidget(self.text)
- self.setLayout(layout)
+ vertical_headers = []
+ for i in range(0, self._memory_size, self._column_size):
+ vertical_headers.append(str(hex(i)))
+
+ self.setVerticalHeaderLabels(vertical_headers)
self.update()
def update(self):
- memory_str = ""
- for adress, value in enumerate(self.module.memory):
- # Add adress and content to string
- # Make sure its unifrom lenght so rows are consistent
- memory_str += f"{adress}" + ": " + f"{value}" + " " + "\t"
+ """
+ Update the content of this widget to reflect the content of the memory module.
+ """
+ memory_content = self._memory.get_state()["memory"]
+ for i in range(self._memory_size):
+ value = memory_content[i]
+ row = i // self._column_size
+ col = i % self._column_size
+ self.set_item(row, col, str(value))
- # Make new line when we reach end of row
- if adress % self._ROW_LENGTH == self._ROW_LENGTH - 1:
- memory_str += "\n"
+ def set_item(self, row: int, col: int, text: str) -> None:
+ """Set the text at specified table cell to the given text.
+
+ Parameters
+ ----------
+ row: int
+ The items row position in the pipeline diagram.
+ col: int
+ The items column position in the pipeline diagram.
+ text: str
+ The text to be displayed.
+ """
+ item = QTableWidgetItem(text)
- self.text.setText(memory_str)
+ self.setItem(row, col, item)
+
+ def _set_column_size(self) -> None:
+ """
+ Set the column size to a reasonable value if the size was not given to the constructor.
+
+ This function assumes that the attributes `column_size` and `memory_size` are set before it is called.
+ """
+
+ if not self._column_size == -1:
+ return
+
+ if self._memory_size > 200:
+ self._column_size = 4
+ return
+
+ if self._memory_size > 100:
+ self._column_size = 2
+ return
+
+ self._column_size = 1
+ return
class MemoryGraphicsItem(ModuleGraphicsItem):
@@ -77,34 +126,34 @@ class MemoryGraphicsItem(ModuleGraphicsItem):
)
self.output.setPos(self._width, self._height / 4)
- self.adress = PortGraphicsItem(
- self.module.get_adress_signal(), Orientation.DOWN, self
+ self.address = PortGraphicsItem(
+ self.module.get_address_signal(), Orientation.DOWN, self
)
- self.adress.setPos(self._width / 4, self._height)
+ self.address.setPos(self._width / 4, self._height)
self.control = PortGraphicsItem(
self.module.get_control_signal(), Orientation.DOWN, self
)
self.control.setPos(self._width * 3 / 4, self._height)
- self.ports = [self.input, self.output, self.adress, self.control]
+ self.ports = [self.input, self.output, self.address, self.control]
# Create name lable
name_text = QGraphicsSimpleTextItem(self.state["name"], self)
name_text.setPos(self._width / 2 - len(self.state["name"]) * self._CHAR_LEN, 0)
- # Create adress lable
- self.adress_text = QGraphicsSimpleTextItem(
- "adress: " + str(self.state["current_adress"]), self
+ # Create address lable
+ self.address_text = QGraphicsSimpleTextItem(
+ "address: " + str(self.state["current_address"]), self
)
- self.adress_text.setPos(self._width / 20, self._height / 8)
+ self.address_text.setPos(self._width / 20, self._height / 8)
def update(self):
"""
Also update memory window here.
"""
self.state = self.module.get_state()
- self.adress_text.setText("adress: " + str(self.state["current_adress"]))
+ self.address_text.setText("address: " + str(self.state["current_address"]))
if self.memory_window is not None:
self.memory_window.update()
@@ -167,30 +216,30 @@ class MemoryGraphicsItem(ModuleGraphicsItem):
@Slot(str, str, str)
def memoryBreakpointAccepted(
- self, module_name: str, adress: str, value: str
+ self, module_name: str, address: str, value: str
) -> None:
"""
Takes the info from a breakpoint dialog and sends it to the gui
"""
try:
- self.new_memory_breakpoint_signal.emit(module_name, adress, value)
+ self.new_memory_breakpoint_signal.emit(module_name, address, value)
except SyntaxError as e:
self.errorMessageWidget.showMessage(str(e))
@Slot(str, str, str)
- def editMemoryAccepted(self, module_name: str, adress: str, value: str) -> None:
+ def editMemoryAccepted(self, module_name: str, address: str, value: str) -> None:
"""
Takes the info from a edit memory dialog
and updates the memory content accordingly.
Also asks the gui to update.
"""
try:
- parsed_adress = int(adress)
+ parsed_address = int(address)
except SyntaxError as e:
self.errorMessageWidget.showMessage(str(e))
else:
module_state = self.module.get_state()
- module_state['memory'][parsed_adress] = value
+ module_state['memory'][parsed_address] = value
self.module.set_state(module_state)
self.update_graphics_signal.emit()
diff --git a/src/simudator/gui/pipeline.py b/src/simudator/gui/pipeline.py
index 2c400c06f93411d368b117796136d577687c94f0..9023ef17475fa40212b42481e56e0235b0a12bf7 100644
--- a/src/simudator/gui/pipeline.py
+++ b/src/simudator/gui/pipeline.py
@@ -1,6 +1,8 @@
-from qtpy.QtWidgets import QTableWidget, QTableWidgetItem
from typing import Any
+from qtpy.QtWidgets import QTableWidget, QTableWidgetItem
+
+
# TODO: Make the table unediatable
class PipeLine(QTableWidget):
"""
@@ -23,7 +25,6 @@ class PipeLine(QTableWidget):
self.set_item(3, 3, self.instructions[3])
"""
-
def set_instruction(self, instructions: list[str]) -> None:
"""Give the pipeline the current CPU instructions."""
self.instructions = instructions
@@ -43,7 +44,7 @@ class PipeLine(QTableWidget):
Depending on the CPU architecture the labels for each row
can change format. In a pipelined CPU we want to assign a clock cycle
to each instruction. In an ARM cpu we want the current
- CPU clock cycle for the first instruciton, and something else for the
+ CPU clock cycle for the first instruciton, and something else for the
micro instrucitons.
"""
raise NotImplemented
@@ -63,6 +64,3 @@ class PipeLine(QTableWidget):
item = QTableWidgetItem(text)
self.setItem(row, col, item)
-
-
-
diff --git a/src/simudator/processor/mia/gui/ar_graphic.py b/src/simudator/processor/mia/gui/ar_graphic.py
index 06dcdb07c61c9aa0efd98e98ce8eadd0ef6e6569..c6e5bf2647c055c90dfe17cedb9f52b22c5d44f4 100644
--- a/src/simudator/processor/mia/gui/ar_graphic.py
+++ b/src/simudator/processor/mia/gui/ar_graphic.py
@@ -18,20 +18,20 @@ class ArGraphicsItem(IntegerRegisterGraphicsItem):
)
# Draw bus port
- bus_port = PortGraphicsItem(self.module.output_s, parent=self)
+ bus_port = PortGraphicsItem(self.module.signals["out_content"], parent=self)
bus_port.setPos(width, self._RECT_HEIGHT / 2)
self.ports.append(bus_port)
# Draw to alu port
to_alu_port = PortGraphicsItem(
- self.module.alu_output_signal, Orientation.LEFT, parent=self
+ self.module.signals["out_alu"], Orientation.LEFT, parent=self
)
to_alu_port.setPos(0, self._RECT_HEIGHT / 2)
self.ports.append(to_alu_port)
# Draw from alu port
from_alu_port = PortGraphicsItem(
- self.module.input_s, Orientation.UP, parent=self
+ self.module.signals["in_content"], Orientation.UP, parent=self
)
from_alu_port.setPos(width / 2, 0)
self.ports.append(from_alu_port)
diff --git a/src/simudator/processor/mia/gui/asr_graphic.py b/src/simudator/processor/mia/gui/asr_graphic.py
index 752643f1e7d83340e8531d8260c210aaff5dce34..079a9250692b6153e227c8f958f5c15ee3ef32d3 100644
--- a/src/simudator/processor/mia/gui/asr_graphic.py
+++ b/src/simudator/processor/mia/gui/asr_graphic.py
@@ -19,13 +19,13 @@ class AsrGraphicsItem(IntegerRegisterGraphicsItem):
)
# Draw bus port
- bus_port = PortGraphicsItem(self.module.input_s, parent=self)
+ bus_port = PortGraphicsItem(self.module.signals["in_content"], parent=self)
bus_port.setPos(width, self._RECT_HEIGHT / 2)
self.ports.append(bus_port)
# Draw to memory port
to_memory_port = PortGraphicsItem(
- self.module.output_s, Orientation.LEFT, parent=self
+ self.module.signals["out_content"], Orientation.LEFT, parent=self
)
to_memory_port.setPos(0, self._RECT_HEIGHT / 2)
self.ports.append(to_memory_port)
diff --git a/src/simudator/processor/mia/gui/hr_graphic.py b/src/simudator/processor/mia/gui/hr_graphic.py
index 5b3331194bcd799b08339e9789dac56c1511263e..ce4ba72814d3022f05caba2a3487b9122c648cb3 100644
--- a/src/simudator/processor/mia/gui/hr_graphic.py
+++ b/src/simudator/processor/mia/gui/hr_graphic.py
@@ -17,11 +17,11 @@ class HrGraphicsItem(IntegerRegisterGraphicsItem):
)
# Draw to bus port
- to_bus_port = PortGraphicsItem(self.module.input_s, parent=self)
+ to_bus_port = PortGraphicsItem(self.module.signals["in_content"], parent=self)
to_bus_port.setPos(width, self._RECT_HEIGHT / 4)
self.ports.append(to_bus_port)
# Draw from bus port
- from_bus_port = PortGraphicsItem(self.module.output_s, parent=self)
+ from_bus_port = PortGraphicsItem(self.module.signals["out_content"], parent=self)
from_bus_port.setPos(width, self._RECT_HEIGHT * 3 / 4)
self.ports.append(from_bus_port)
diff --git a/src/simudator/processor/mia/gui/mia_alu_graphic.py b/src/simudator/processor/mia/gui/mia_alu_graphic.py
index 3bcd78a49acde6c541745bc96fc2e65b64373f22..737c7325cdaef600f745f4040fe317e782c80887 100644
--- a/src/simudator/processor/mia/gui/mia_alu_graphic.py
+++ b/src/simudator/processor/mia/gui/mia_alu_graphic.py
@@ -25,18 +25,18 @@ class AluGraphicsItem(ModuleGraphicsItem):
)
# make port for input a
- port_a = PortGraphicsItem(self.module.input_signal_a, Orientation.UP, self)
+ port_a = PortGraphicsItem(self.module.signals["in_input_a"], Orientation.UP, self)
port_a.setPos(self.RECT_WIDTH * 3 / 4, 0)
self.ports.append(port_a)
# make port for input b
- port_b = PortGraphicsItem(self.module.input_signal_b, Orientation.UP, self)
+ port_b = PortGraphicsItem(self.module.signals["in_input_b"], Orientation.UP, self)
port_b.setPos(self.RECT_WIDTH / 4, 0)
self.ports.append(port_b)
# make port for output
output_port = PortGraphicsItem(
- self.module.output_signal, Orientation.DOWN, self
+ self.module.signals["out_result"], Orientation.DOWN, self
)
output_port.setPos(self.RECT_WIDTH / 2, self.RECT_HEIGHT)
self.ports.append(output_port)
diff --git a/src/simudator/processor/mia/gui/mia_grx_graphic.py b/src/simudator/processor/mia/gui/mia_grx_graphic.py
index a3de6f2b8187675b442864930a1e81387cb7ff1d..5474f915cc91a374f4fcccebadba008389e3a073 100644
--- a/src/simudator/processor/mia/gui/mia_grx_graphic.py
+++ b/src/simudator/processor/mia/gui/mia_grx_graphic.py
@@ -29,9 +29,9 @@ class GrxGraphicsItem(ModuleGraphicsItem):
LINE_LENGTH = 30
MUX_WIDTH = 80
- def __init__(self, moudle: GRX):
+ def __init__(self, module: GRX):
self.register_text_labels = []
- super().__init__(moudle)
+ super().__init__(module)
def draw_graphics_item(self):
# The width of the register
@@ -123,14 +123,14 @@ class GrxGraphicsItem(ModuleGraphicsItem):
)
# Add ports to and from bus
- from_bus_port = PortGraphicsItem(self.module.from_bus, Orientation.RIGHT, self)
+ from_bus_port = PortGraphicsItem(self.module.signals["in_input"], Orientation.RIGHT, self)
from_bus_port.setPos(
rect_width + self.LINE_LENGTH + self.MUX_WIDTH,
# Use the buses port margins so the ports align nicely
mux_height / 2 - BusGraphicsItem.PORT_MARGIN / 2,
)
- to_bus_port = PortGraphicsItem(self.module.to_bus, Orientation.RIGHT, self)
+ to_bus_port = PortGraphicsItem(self.module.signals["out_content"], Orientation.RIGHT, self)
to_bus_port.setPos(
rect_width + self.LINE_LENGTH + self.MUX_WIDTH,
# Use the buses port margins so the ports align nicely
diff --git a/src/simudator/processor/mia/gui/mia_memory_graphic.py b/src/simudator/processor/mia/gui/mia_memory_graphic.py
index 33ae98cd0c016b90bf027b40a7e6f5d65a468828..ec29b7717ebc86efe8b0762dc07f3abef6ca34a1 100644
--- a/src/simudator/processor/mia/gui/mia_memory_graphic.py
+++ b/src/simudator/processor/mia/gui/mia_memory_graphic.py
@@ -12,44 +12,15 @@ from qtpy.QtWidgets import (
from simudator.core.modules import Memory
from simudator.gui.color_scheme import ColorScheme as CS
-from simudator.gui.module_graphics_item.memory_graphic import MemoryGraphicsItem
+from simudator.gui.module_graphics_item.memory_graphic import (
+ MemoryGraphicsItem,
+ MemoryWindow,
+)
from simudator.gui.orientation import Orientation
from simudator.gui.port_graphics_item import PortGraphicsItem
from simudator.processor.mia.gui.mia_memory_content_dialog import MiaMemoryContentDialog
-class MiaMemoryWindow(QWidget):
- """
- Widget for showing content of memory
- """
-
- ROW_LENGTH = 4
-
- def __init__(self, memory_module: Memory):
- super().__init__()
- self.module = memory_module
-
- self.text = QTextEdit("")
- layout = QVBoxLayout()
- layout.addWidget(self.text)
- self.setLayout(layout)
-
- self.update()
-
- def update(self):
- memory_str = ""
- for adress, value in enumerate(self.module.memory):
- # Add adress and content to string
- # Make sure its unifrom lenght so rows are consistent
- memory_str += f"0x{adress:02x}" + ": " + f"0x{value:04x}" + " " + "\t"
-
- # Make new line when we reach end of row
- if adress % self.ROW_LENGTH == self.ROW_LENGTH - 1:
- memory_str += "\n"
-
- self.text.setText(memory_str)
-
-
class MiaMemoryGraphicsItem(MemoryGraphicsItem):
"""
Graphics module for a Memory module.
@@ -70,38 +41,38 @@ class MiaMemoryGraphicsItem(MemoryGraphicsItem):
# Make ports
self.input = PortGraphicsItem(
- self.module.get_input_signal(), Orientation.RIGHT, self
+ self.module.signals["in_input"], Orientation.RIGHT, self
)
self.input.setPos(self._width, self._height / 8)
self.output = PortGraphicsItem(
- self.module.get_output_signal(), Orientation.RIGHT, self
+ self.module.signals["out_content"], Orientation.RIGHT, self
)
self.output.setPos(self._width, self._height / 4)
- self.adress = PortGraphicsItem(
- self.module.get_adress_signal(), Orientation.DOWN, self
+ self.address = PortGraphicsItem(
+ self.module.signals["in_address"], Orientation.DOWN, self
)
- self.adress.setPos(self._width / 4, self._height)
+ self.address.setPos(self._width / 4, self._height)
- self.ports = [self.input, self.output, self.adress]
+ self.ports = [self.input, self.output, self.address]
# Create name lable
name_text = QGraphicsSimpleTextItem(self.state["name"], self)
name_text.setPos(self._width / 2 - len(self.state["name"]) * self._CHAR_LEN, 0)
- # Create adress lable
- self.adress_text = QGraphicsSimpleTextItem(
- "adress: " + str(self.state["current_adress"]), self
+ # Create address lable
+ self.address_text = QGraphicsSimpleTextItem(
+ "address: " + str(self.state["current_address"]), self
)
- self.adress_text.setPos(self._width / 20, self._height / 8)
+ self.address_text.setPos(self._width / 20, self._height / 8)
def showMemoryContents(self) -> None:
"""
Create and show a MemoryWindow that displays the contents
of the memory module associated with this graphics item.
"""
- self.memory_window = MiaMemoryWindow(self.module)
+ self.memory_window = MemoryWindow(self.module)
self.memory_window.show()
def memoryBreakpointDialog(self) -> None:
@@ -113,16 +84,16 @@ class MiaMemoryGraphicsItem(MemoryGraphicsItem):
@Slot(str, str, str)
def memoryBreakpointAccepted(
- self, module_name: str, adress: str, value: str
+ self, module_name: str, address: str, value: str
) -> None:
"""
Same as prent function but also prases data so it is hexadecimal.
"""
try:
- parsed_adress = int(adress, 16)
+ parsed_address = int(address, 16)
parsed_value = ast.literal_eval(value)
self.new_memory_breakpoint_signal.emit(
- module_name, str(parsed_adress), str(parsed_value)
+ module_name, str(parsed_address), str(parsed_value)
)
except SyntaxError as e:
self._errorMessageWidget.showMessage(str(e))
@@ -132,12 +103,12 @@ class MiaMemoryGraphicsItem(MemoryGraphicsItem):
)
@Slot(str, str, str)
- def editMemoryAccepted(self, module_name: str, adress: str, value: str) -> None:
+ def editMemoryAccepted(self, module_name: str, address: str, value: str) -> None:
"""
Same as prent function but also prases data so it is hexadecimal.
"""
try:
- parsed_adress = int(adress, 16)
+ parsed_adress = int(address, 16)
parsed_value = ast.literal_eval(value)
except SyntaxError as e:
self._errorMessageWidget.showMessage(str(e))
@@ -158,3 +129,6 @@ class MiaMemoryGraphicsItem(MemoryGraphicsItem):
else:
self.module.set_state(module_state)
self.update_graphics_signal.emit()
+ module_state['memory'][parsed_adress] = parsed_value
+ self.module.set_state(module_state)
+ self.update_graphics_signal.emit()
diff --git a/src/simudator/processor/mia/gui/pc_graphic.py b/src/simudator/processor/mia/gui/pc_graphic.py
index 498de090b8af31e97563f590d28c193658d91440..34ed5fcbe1aa599609cd154e72968116ac713818 100644
--- a/src/simudator/processor/mia/gui/pc_graphic.py
+++ b/src/simudator/processor/mia/gui/pc_graphic.py
@@ -27,11 +27,13 @@ class PcGraphicsItem(IntegerRegisterGraphicsItem):
)
# Draw to bus port
- to_bus_port = PortGraphicsItem(self.module.bus_input_s, parent=self)
+ to_bus_port = PortGraphicsItem(self.module.signals["in_input"], parent=self)
to_bus_port.setPos(width, self._RECT_HEIGHT / 4)
self.ports.append(to_bus_port)
# Draw from bus port
- from_bus_port = PortGraphicsItem(self.module.bus_output_s, parent=self)
+ from_bus_port = PortGraphicsItem(
+ self.module.signals["out_content"], parent=self
+ )
from_bus_port.setPos(width, self._RECT_HEIGHT * 3 / 4)
self.ports.append(from_bus_port)
diff --git a/src/simudator/processor/mia/gui/supc_graphic.py b/src/simudator/processor/mia/gui/supc_graphic.py
index 730a1a292056febc7c76df298eba09ea3cd13edb..fab770b680df22d54ffad668165fc4091ac17d11 100644
--- a/src/simudator/processor/mia/gui/supc_graphic.py
+++ b/src/simudator/processor/mia/gui/supc_graphic.py
@@ -18,13 +18,15 @@ class SupcGraphicsItem(IntegerRegisterGraphicsItem):
)
# Draw to mPc port
- to_upc_port = PortGraphicsItem(self.module.input_s, Orientation.UP, parent=self)
+ to_upc_port = PortGraphicsItem(
+ self.module.signals["in_content"], Orientation.UP, parent=self
+ )
to_upc_port.setPos(width * 2 / 8, 0)
self.ports.append(to_upc_port)
# Draw from uPc port
from_upc_port = PortGraphicsItem(
- self.module.output_s, Orientation.UP, parent=self
+ self.module.signals["out_content"], Orientation.UP, parent=self
)
from_upc_port.setPos(width * 6 / 8, 0)
self.ports.append(from_upc_port)
diff --git a/src/simudator/processor/mia/gui/upc_graphic.py b/src/simudator/processor/mia/gui/upc_graphic.py
index 180c318e322fa512eb7b3bb5cc91b3cc508d8126..85d27b9a1715fbf22970baf711611fb7e5e9ac9c 100644
--- a/src/simudator/processor/mia/gui/upc_graphic.py
+++ b/src/simudator/processor/mia/gui/upc_graphic.py
@@ -27,25 +27,25 @@ class uPcGraphicsItem(IntegerRegisterGraphicsItem):
)
# Draw from K1 port
- from_k1 = PortGraphicsItem(self.module.from_k1, Orientation.UP, parent=self)
+ from_k1 = PortGraphicsItem(self.module.signals["in_k1"], Orientation.UP, parent=self)
from_k1.setPos(width * 2 / 8, 0)
self.ports.append(from_k1)
# Draw from K2 port
- from_k2 = PortGraphicsItem(self.module.from_k2, Orientation.UP, parent=self)
+ from_k2 = PortGraphicsItem(self.module.signals["in_k2"], Orientation.UP, parent=self)
from_k2.setPos(width * 6 / 8, 0)
self.ports.append(from_k2)
# Draw to SUPc port
to_supc_port = PortGraphicsItem(
- self.module.from_supc, Orientation.DOWN, parent=self
+ self.module.signals["out_supc"], Orientation.DOWN, parent=self
)
to_supc_port.setPos(width * 2 / 8, self._RECT_HEIGHT)
self.ports.append(to_supc_port)
# Draw from SuPc port
from_supc_port = PortGraphicsItem(
- self.module.to_supc, Orientation.DOWN, parent=self
+ self.module.signals["in_supc"], Orientation.DOWN, parent=self
)
from_supc_port.setPos(width * 6 / 8, self._RECT_HEIGHT)
self.ports.append(from_supc_port)
diff --git a/src/simudator/processor/mia/mia.py b/src/simudator/processor/mia/mia.py
index 077f74a3092f3f5f17cce2c86e4bcc59a8ec5c06..724ad94bedb46e5ab898ce607003f193b5a94f93 100644
--- a/src/simudator/processor/mia/mia.py
+++ b/src/simudator/processor/mia/mia.py
@@ -32,10 +32,6 @@ from simudator.processor.mia.modules.mia_memory import MiaMemory
from simudator.processor.mia.modules.micro_memory import MicroMemory
from simudator.processor.mia.modules.micro_pc import MicroPC
-# Using a bare expect is generally bad code practice,
-# howere here we want to load the default layout if
-# anything goes wrong with loading the selected one,
-# we dont care about what went wrong
from simudator.processor.mia.modules.pc import PC
@@ -142,7 +138,7 @@ class MIA_CPU(Processor):
# PM specific
pm_size = 256
pm_bus_id = 0b010
- pm_adress_padding = 2
+ pm_address_padding = 2
pm_value_padding = 4
pm = MiaMemory(
pm_bus,
@@ -152,7 +148,7 @@ class MIA_CPU(Processor):
pm_size,
pm_bus_id,
value_padding=pm_value_padding,
- adress_padding=pm_adress_padding,
+ address_padding=pm_address_padding,
name="PM",
)
@@ -164,7 +160,7 @@ class MIA_CPU(Processor):
# K1 specific
k1_size = 16
- k1_adress_padding = 2
+ k1_address_padding = 2
k1_value_padding = 2
k1 = MiaMemory(
always_write_signal,
@@ -174,13 +170,13 @@ class MIA_CPU(Processor):
k1_size,
always_write_id,
name="K1",
- adress_padding=k1_adress_padding,
+ address_padding=k1_address_padding,
value_padding=k1_value_padding,
)
# K2 specific
k2_size = 4
- k2_adress_padding = 2
+ k2_address_padding = 2
k2_value_padding = 2
k2 = MiaMemory(
always_write_signal,
@@ -190,7 +186,7 @@ class MIA_CPU(Processor):
k2_size,
always_write_id,
name="K2",
- adress_padding=k2_adress_padding,
+ address_padding=k2_address_padding,
value_padding=k2_value_padding,
)
@@ -335,19 +331,19 @@ class MIA_CPU(Processor):
grx = self.get_module("GRx")
bus_signal_pairs = [
- (asr.input_s, None),
- (ir.from_bus_s, ir.to_bus_s),
- (pm.input_s, pm.output_s),
+ (asr.signals["in_content"], None),
+ (ir.signals["in_input"], ir.signals["out_output"]),
+ (pm.signals["in_input"], pm.signals["out_content"]),
(None, None),
- (pc.bus_input_s, pc.bus_output_s),
+ (pc.signals["in_input"], pc.signals["out_content"]),
(None, None),
- (alu.input_signal_b, None),
+ (alu.signals["in_input_b"], None),
(None, None),
- (None, ar.output_s),
+ (None, ar.signals["out_content"]),
(None, None),
- (hr.input_s, hr.output_s),
+ (hr.signals["in_content"], hr.signals["out_content"]),
(None, None),
- (grx.from_bus, grx.to_bus),
+ (grx.signals["in_input"], grx.signals["out_content"]),
]
gui.addModuleGraphicsItem(
diff --git a/src/simudator/processor/mia/modules/alu.py b/src/simudator/processor/mia/modules/alu.py
index ac94ebee63e2f834614ea6abf1d48b212a06d3e0..47ca0571e49bee3434230e20639cb674f91cab93 100644
--- a/src/simudator/processor/mia/modules/alu.py
+++ b/src/simudator/processor/mia/modules/alu.py
@@ -30,27 +30,20 @@ class ALU(Module):
o_signal: Signal,
c_signal: Signal,
):
- super().__init__(name)
-
- # Input Signals
- self.input_signal_a = input_signal_a
- self.input_signal_b = input_signal_b
- self.control_signal = control_signal
- self.input_signal_hr = input_signal_hr
-
- # Add destinations
- self.input_signal_a.add_destination(self)
- self.input_signal_b.add_destination(self)
- self.control_signal.add_destination(self)
- self.input_signal_hr.add_destination(self)
-
- # Output Signals
- self.output_signal = output_signal
- self.output_signal_hr = output_signal_hr
- self.z_signal = z_signal
- self.n_signal = n_signal
- self.o_signal = o_signal
- self.c_signal = c_signal
+
+ signals = {
+ "in_input_a": input_signal_a,
+ "in_input_b": input_signal_b,
+ "in_control": control_signal,
+ "in_hr": input_signal_hr,
+ "out_result": output_signal,
+ "out_hr": output_signal_hr,
+ "out_flag_z": z_signal,
+ "out_flag_n": n_signal,
+ "out_flag_o": o_signal,
+ "out_flag_c": c_signal,
+ }
+ super().__init__(signals, name)
# flag values
self.z_value = 0
@@ -61,18 +54,36 @@ class ALU(Module):
# internal values
self.hr_value = None
+ def update_register(self) -> None:
+ """
+ The alu has no register.
+ """
+ pass
+
+ def output_register(self) -> None:
+ """
+ The alu has no register.
+ """
+ pass
+
+ def save_state_to_file(self, file_path: str) -> bool:
+ """
+ The ali is state-less.
+ """
+ return True
+
def update_logic(self) -> None:
"""
Will calculate and operation depending on given contorl signal
and update outputs with result.
"""
- value_a = self.input_signal_a.get_value()
- value_b = self.input_signal_b.get_value()
- value_hr = self.input_signal_hr.get_value()
+ value_a = self.signals["in_input_a"].get_value()
+ value_b = self.signals["in_input_b"].get_value()
+ value_hr = self.signals["in_hr"].get_value()
# bitmask control value to get first 4 bits
- control_value = self.control_signal.get_value()
+ control_value = self.signals["in_control"].get_value()
# If control value is none do nothing
if control_value is None:
@@ -154,12 +165,12 @@ class ALU(Module):
return
# Update output signal and flags
- self.output_signal.update_value(output_value)
- self.z_signal.update_value(self.z_value)
- self.n_signal.update_value(self.n_value)
- self.o_signal.update_value(self.o_value)
- self.c_signal.update_value(self.c_value)
- self.output_signal_hr.update_value(self.hr_value)
+ self.signals["out_result"].update_value(output_value)
+ self.signals["out_flag_z"].update_value(self.z_value)
+ self.signals["out_flag_n"].update_value(self.n_value)
+ self.signals["out_flag_o"].update_value(self.o_value)
+ self.signals["out_flag_c"].update_value(self.c_value)
+ self.signals["out_hr"].update_value(self.hr_value)
def print_module(self) -> None:
print(
@@ -167,30 +178,19 @@ class ALU(Module):
self.name,
"\n -----",
"\n a_value: ",
- self.input_signal_a.get_value(),
+ self.signals["in_input_a"].get_value(),
"\n b_value: ",
- self.input_signal_b.get_value(),
+ self.signals["in_input_b"].get_value(),
"\n control_signal: ",
- self.control_signal.get_value(),
+ self.signals["in_control"].get_value(),
)
- def get_input_signals(self) -> list[Signal]:
- return [
- self.input_signal_a,
- self.input_signal_b,
- self.control_signal,
- self.input_signal_hr,
- ]
-
- def get_output_signals(self) -> list[Signal]:
- return [
- self.output_signal,
- self.output_signal_hr,
- self.z_signal,
- self.n_signal,
- self.o_signal,
- self.c_signal,
- ]
+ def reset(self) -> None:
+ self.z_value = 0
+ self.n_value = 0
+ self.o_value = 0
+ self.c_value = 0
+ self.hr_value = None
# ----- ALU operations -----
@@ -421,7 +421,7 @@ class ALU(Module):
if hr_value is not None:
# get hr as a binary
- hr_binary = self.int_to_bin(self.input_signal_hr.get_value())
+ hr_binary = self.int_to_bin(self.signals["in_hr"].get_value())
long_word_binary = hr_binary[1:] + binary_number + [hr_binary[0]]
diff --git a/src/simudator/processor/mia/modules/ar.py b/src/simudator/processor/mia/modules/ar.py
index 19eca435ca649d49f28481f82a4d77495975a071..f0613cf7c0e121ff156e62cdac3f559861677471 100644
--- a/src/simudator/processor/mia/modules/ar.py
+++ b/src/simudator/processor/mia/modules/ar.py
@@ -18,34 +18,29 @@ class AR(IntegerRegister, MiaBusConnector):
bit_length: int,
name="AR",
) -> None:
- self.alu_output_signal = alu_output_signal
IntegerRegister.__init__(
self, alu_input_signal, bus_output_signal, bit_length, name=name
)
MiaBusConnector.__init__(self, bus_control_signal, bus_id)
+ self.signals["out_alu"] = alu_output_signal
+
def output_register(self) -> None:
# always update alu
- self.alu_output_signal.update_value(self.value)
+ self.signals["out_alu"].update_value(self.value)
# only update bus when asked too
if self.write_to_bus():
IntegerRegister.output_register(self)
else:
- self.output_s.update_value(None)
+ self.signals["out_content"].update_value(None)
def update_logic(self) -> None:
if self.write_to_bus():
IntegerRegister.output_register(self)
else:
- self.output_s.update_value(None)
-
- def get_input_signals(self) -> list[Signal]:
- return [self.input_s]
-
- def get_output_signals(self) -> list[Signal]:
- return [self.alu_output_signal, self.output_s, self.bus_control_s]
+ self.signals["out_content"].update_value(None)
def print_module(self):
print(
diff --git a/src/simudator/processor/mia/modules/asr.py b/src/simudator/processor/mia/modules/asr.py
index 3b5a53ed96341aa7c51ad678eaa542353ff35999..dbf5e8a9a16bbb6b16d802a0b6deea40c48eaa87 100644
--- a/src/simudator/processor/mia/modules/asr.py
+++ b/src/simudator/processor/mia/modules/asr.py
@@ -30,12 +30,6 @@ class ASR(IntegerRegister, MiaBusConnector):
if self.write_to_bus():
self.output_register()
- def get_input_signals(self) -> [Signal]:
- return [self.input_s, self.bus_control_s]
-
- def get_output_signals(self) -> [Signal]:
- return [self.output_s]
-
def print_module(self):
print(
"",
diff --git a/src/simudator/processor/mia/modules/bus.py b/src/simudator/processor/mia/modules/bus.py
index 423bc875d4991908a3556365381a162615828fb9..4325b6dbbe5048e14ae14dfad1a2b84647e9a99f 100644
--- a/src/simudator/processor/mia/modules/bus.py
+++ b/src/simudator/processor/mia/modules/bus.py
@@ -13,14 +13,13 @@ class Bus(Module):
def __init__(
self, inputs: list[Signal] = [], outputs: list[Signal] = [], name: str = "Bus"
) -> None:
- super().__init__(name)
- self.inputs = inputs
- self.outputs = outputs
-
- # add self as destination to all inputs
- for input_signal in self.inputs:
- input_signal.add_destination(self)
+ signals = {}
+ for i, s in enumerate(inputs):
+ signals[f"in_input_{i}"] = s
+ for i, s in enumerate(outputs):
+ signals[f"out_output_{i}"] = s
+ super().__init__(signals, name)
def update_logic(self) -> None:
"""
@@ -30,7 +29,7 @@ class Bus(Module):
nothing will be transferred onto the output signals.
"""
value = None
- for input_signal in self.inputs:
+ for input_signal in self.get_input_signals():
if input_signal.get_value() is not None:
if value is not None:
# Two input signals are writing to the bus at the
@@ -40,7 +39,7 @@ class Bus(Module):
value = input_signal.get_value()
if value is not None:
- for output_signal in self.outputs:
+ for output_signal in self.get_output_signals():
output_signal.update_value(value)
def get_state(self) -> dict:
@@ -52,11 +51,26 @@ class Bus(Module):
def print_module(self) -> None:
pass
- def get_input_signals(self) -> list[Signal]:
- return self.inputs
-
- def get_output_signals(self) -> list[Signal]:
- return self.outputs
+ def reset(self) -> None:
+ pass
def get_name(self) -> str:
return self.name
+
+ def update_register(self) -> None:
+ """
+ The bus has no register.
+ """
+ pass
+
+ def output_register(self) -> None:
+ """
+ The bus has no register.
+ """
+ pass
+
+ def save_state_to_file(self, file_path: str) -> bool:
+ """
+ The ali is state-less.
+ """
+ return True
diff --git a/src/simudator/processor/mia/modules/hr.py b/src/simudator/processor/mia/modules/hr.py
index 2a2d869792a87f4e21b16ad208798140fa4d0ad4..7acc3ad5e2b5eb331099dc5f03eb8816380a3e06 100644
--- a/src/simudator/processor/mia/modules/hr.py
+++ b/src/simudator/processor/mia/modules/hr.py
@@ -19,16 +19,15 @@ class HR(IntegerRegister, MiaBusConnector):
bit_lenght: int,
name="HR",
) -> None:
- self.alu_output_signal = alu_output_signal
- self.alu_input_signal = alu_input_signal
-
- self.alu_input_signal.add_destination(self)
-
IntegerRegister.__init__(
self, bus_input_signal, bus_output_signal, bit_lenght, name=name
)
MiaBusConnector.__init__(self, bus_control_signal, bus_id)
+ alu_input_signal.add_destination(self)
+ self.signals["in_alu"] = alu_input_signal
+ self.signals["out_alu"] = alu_output_signal
+
def update_register(self) -> None:
"""
Updates the internal values from the signals from the bus and
@@ -39,8 +38,8 @@ class HR(IntegerRegister, MiaBusConnector):
if self.read_from_bus():
IntegerRegister.update_register(self)
- elif self.alu_input_signal.get_value() is not None:
- input_value = self.alu_input_signal.get_value()
+ elif self.signals["in_alu"].get_value() is not None:
+ input_value = self.signals["in_alu"].get_value()
self.value = input_value & self.mask
def output_register(self) -> None:
@@ -50,13 +49,13 @@ class HR(IntegerRegister, MiaBusConnector):
output the alu signal.
"""
- self.alu_output_signal.update_value(self.value)
+ self.signals["out_alu"].update_value(self.value)
if self.write_to_bus():
IntegerRegister.output_register(self)
else:
- self.output_s.update_value(None)
+ self.signals["out_content"].update_value(None)
def update_logic(self):
self.output_register()
@@ -71,13 +70,3 @@ class HR(IntegerRegister, MiaBusConnector):
"\n bit length: ",
self.bit_length,
)
-
- def get_input_signals(self) -> list[Signal]:
- return [self.alu_input_signal, self.input_s]
-
- def get_output_signals(self) -> list[Signal]:
- return [
- self.alu_output_signal,
- self.bus_control_s,
- self.output_s,
- ]
diff --git a/src/simudator/processor/mia/modules/ir.py b/src/simudator/processor/mia/modules/ir.py
index 6d0e4ca0b0658e4492fd53e79ed1cfb002784387..c3224a8adbd1ef68692e604e7f2e897becafba64 100644
--- a/src/simudator/processor/mia/modules/ir.py
+++ b/src/simudator/processor/mia/modules/ir.py
@@ -25,19 +25,15 @@ class IR(Module, MiaBusConnector):
name: str = "IR",
) -> None:
MiaBusConnector.__init__(self, bus_control, bus_id)
- Module.__init__(self, name)
- # Input signals
- self.from_bus_s = from_bus
-
- # Output signals
- self.to_bus_s = to_bus
- self.op_s = op_s
- self.grx_s = grx_s
- self.m_s = m_s
-
- # Register as destination of input signals
- from_bus.add_destination(self)
+ signals = {
+ "in_input": from_bus,
+ "out_output": to_bus,
+ "out_op": op_s,
+ "out_grx": grx_s,
+ "out_m": m_s,
+ }
+ Module.__init__(self, signals, name)
# Internal values
self.op = 0
@@ -53,7 +49,7 @@ class IR(Module, MiaBusConnector):
from the bus and bitshift each part of the instruction.
"""
if self.read_from_bus():
- self.instruction = self.from_bus_s.get_value()
+ self.instruction = self.signals["in_input"].get_value()
self.op = self.instruction >> 12
self.grx = (self.instruction >> 10) & 0b11
self.m = (self.instruction >> 8) & 0b11
@@ -65,14 +61,14 @@ class IR(Module, MiaBusConnector):
and m_s, and output its whole instruction to the bus when
asked to.
"""
- self.op_s.update_value(self.op)
- self.grx_s.update_value(self.grx)
- self.m_s.update_value(self.m)
+ self.signals["out_op"].update_value(self.op)
+ self.signals["out_grx"].update_value(self.grx)
+ self.signals["out_m"].update_value(self.m)
if self.write_to_bus():
- self.to_bus_s.update_value(self.instruction)
+ self.signals["out_output"].update_value(self.instruction)
else:
- self.to_bus_s.update_value(None)
+ self.signals["out_output"].update_value(None)
def update_logic(self) -> None:
self.output_register()
@@ -146,13 +142,3 @@ class IR(Module, MiaBusConnector):
# TODO: Maybe check if it starts with instruction: ?
self.instruction = int(string_pair[1], 16)
- def get_input_signals(self) -> list[Signal]:
- return [self.from_bus_s]
-
- def get_output_signals(self) -> list[Signal]:
- return [
- self.to_bus_s,
- self.op_s,
- self.grx_s,
- self.m_s,
- ]
diff --git a/src/simudator/processor/mia/modules/lc.py b/src/simudator/processor/mia/modules/lc.py
index 8a2b6eeb34157feb3d0d89dda893ca5c12287bfb..15e1598df7c809b62dabda12014548c85df77172 100644
--- a/src/simudator/processor/mia/modules/lc.py
+++ b/src/simudator/processor/mia/modules/lc.py
@@ -50,14 +50,16 @@ class LC(Module):
Optional bit length of the loop counter.
"""
- # init the name
- super().__init__(name)
# signals
- self.mM_control_s = mM_control
- self.bus_input_s = bus_input
- self.l_flag_s = l_flag
- self.mM_uADR_s = mM_uADR
+ signals = {
+ "in_control": mM_control,
+ "in_input": bus_input,
+ "in_address": mM_uADR,
+ "out_flag_l": l_flag,
+ }
+
+ super().__init__(signals, name)
# the value of the loop counter
self.value = value
@@ -71,11 +73,6 @@ class LC(Module):
self.bit_length = bit_length
self.mask = 2**self.bit_length - 1
- # set the loop counter as the destination of its input signals
- self.mM_control_s.add_destination(self)
- self.bus_input_s.add_destination(self)
- self.mM_uADR_s.add_destination(self)
-
def update_register(self) -> None:
"""Reads bit 12 and 13 from the micro memory and updates the
loop counter.
@@ -85,7 +82,7 @@ class LC(Module):
3 - loads the 7 least significant bits from the uADR field.
"""
- match self.mM_control_s.get_value():
+ match self.signals["in_control"].get_value():
case 0b00: # LC is not effected
self.decrement_by_one = False
self.read_from_bus = False
@@ -107,11 +104,11 @@ class LC(Module):
self.read_from_uADR = True
if self.read_from_bus:
- input_value = self.bus_input_s.get_value()
+ input_value = self.signals["in_input"].get_value()
self.value = input_value & self.mask
if self.read_from_uADR:
- input_value = self.mM_uADR_s.get_value()
+ input_value = self.signals["in_address"].get_value()
self.value = input_value & self.mask
if self.decrement_by_one:
@@ -132,11 +129,11 @@ class LC(Module):
Otherwise set it to zero.
"""
if self.value == 0:
- self.l_flag_s.update_value(1)
+ self.signals["out_flag_l"].update_value(1)
else:
- self.l_flag_s.update_value(0)
+ self.signals["out_flag_l"].update_value(0)
- def get_state(self) -> dict[str:Any]:
+ def get_state(self) -> dict[str, Any]:
"""Returns a dict of the loop counter state.
These states are changable via set_states.
@@ -155,7 +152,7 @@ class LC(Module):
state["decrement_by_one"] = self.decrement_by_one
return state
- def set_state(self, state: dict[str:Any]) -> None:
+ def set_state(self, state: dict[str, Any]) -> None:
"""Sets the loop counter state to one given in dict."""
self.name = state["name"]
self.value = state["value"]
@@ -172,7 +169,6 @@ class LC(Module):
def reset(self) -> None:
"""Resets the loop counter to 0."""
- super().reset()
self.value = 0
self.read_from_bus = False
self.read_from_uADR = False
@@ -205,8 +201,3 @@ class LC(Module):
self.read_from_bus,
)
- def get_input_signals(self) -> list[Signal]:
- return [self.mM_control_s, self.bus_input_s, self.mM_uADR_s]
-
- def get_output_signals(self) -> list[Signal]:
- return [self.l_flag_s]
diff --git a/src/simudator/processor/mia/modules/mia_grx.py b/src/simudator/processor/mia/modules/mia_grx.py
index 1c5a33ef42b3d995c065aeeb31e107b4039cf8bb..414bcb9aa6f32f25d2c0ca12f2ad4b9919423c21 100644
--- a/src/simudator/processor/mia/modules/mia_grx.py
+++ b/src/simudator/processor/mia/modules/mia_grx.py
@@ -30,22 +30,19 @@ class GRX(Module, MiaBusConnector):
# Set connection to/from bus and bus_id
MiaBusConnector.__init__(self, bus_control, bus_id)
- # Set the name
- Module.__init__(self, name)
# Other signals
- self.to_bus = to_bus
- self.from_bus = from_bus
- self.m_control_s = m_control
- self.s_control_s = s_control
- self.grx_control_s = grx_control
-
- # Set self as destination of its signals
- self.m_control_s.add_destination(self)
- self.s_control_s.add_destination(self)
- self.grx_control_s.add_destination(self)
-
- # set the regusters
+ signals = {
+ "in_input": from_bus,
+ "in_control_grx": grx_control,
+ "in_control_s": s_control,
+ "in_control_m": m_control,
+ "out_content": to_bus,
+ }
+ # Init module superclass
+ Module.__init__(self, signals, name)
+
+ # set the registers
self.registers = registers
# set the bit_length
@@ -58,17 +55,17 @@ class GRX(Module, MiaBusConnector):
the GRx bits if s == 0 or M bits if s == 1.
"""
if self.read_from_bus():
- s_control_value = self.s_control_s.get_value()
+ s_control_value = self.signals["in_control_s"].get_value()
grx_index = 0
if s_control_value == 0b0:
- grx_index = self.grx_control_s.get_value()
+ grx_index = self.signals["in_control_grx"].get_value()
elif s_control_value == 0b1:
- grx_index = self.m_control_s.get_value()
+ grx_index = self.signals["in_control_m"].get_value()
else:
raise ValueError("The value of the s signal" "must be 0b0 or 0b1 !!!")
- self.registers[grx_index] = self.from_bus.get_value()
+ self.registers[grx_index] = self.signals["in_input"].get_value()
def output_register(self):
"""
@@ -77,19 +74,19 @@ class GRX(Module, MiaBusConnector):
the GRx bits if s == 0 or M bits if s == 1.
"""
if self.write_to_bus():
- s_control_value = self.s_control_s.get_value()
+ s_control_value = self.signals["in_control_s"].get_value()
grx_index = 0
if s_control_value == 0b0:
- grx_index = self.grx_control_s.get_value()
+ grx_index = self.signals["in_control_grx"].get_value()
elif s_control_value == 0b1:
- grx_index = self.m_control_s.get_value()
+ grx_index = self.signals["in_control_m"].get_value()
else:
raise ValueError("The value of the s signal" "must be 0b0 or 0b1 !!!")
- self.to_bus.update_value(self.registers[grx_index])
+ self.signals["out_content"].update_value(self.registers[grx_index])
else:
- self.to_bus.update_value(None)
+ self.signals["out_content"].update_value(None)
def update_logic(self) -> None:
self.output_register()
@@ -177,14 +174,3 @@ class GRX(Module, MiaBusConnector):
hex(self.registers[3]),
)
- def get_input_signals(self) -> list[Signal]:
- return [
- self.bus_control_s,
- self.from_bus,
- self.m_control_s,
- self.s_control_s,
- self.grx_control_s,
- ]
-
- def get_output_signals(self) -> list[Signal]:
- return [self.to_bus]
diff --git a/src/simudator/processor/mia/modules/mia_memory.py b/src/simudator/processor/mia/modules/mia_memory.py
index 9aab5263db44b74c37df12640876bf42481b22f3..cc66d8b853a2c176b5c2cc4bc9d13dc2c54cabc2 100644
--- a/src/simudator/processor/mia/modules/mia_memory.py
+++ b/src/simudator/processor/mia/modules/mia_memory.py
@@ -15,12 +15,12 @@ class MiaMemory(MiaBusConnector, Memory):
self,
input_signal: Signal,
output_signal: Signal,
- adress_signal: Signal,
+ address_signal: Signal,
bus_control_s: Signal,
size: int = 1,
bus_id: int = 0,
value_padding: int = 2,
- adress_padding: int = 2,
+ address_padding: int = 2,
name: str = "PM",
) -> None:
MiaBusConnector.__init__(self, bus_control_s, bus_id)
@@ -29,11 +29,11 @@ class MiaMemory(MiaBusConnector, Memory):
input_signal,
output_signal,
Signal(None),
- adress_signal,
+ address_signal,
size,
name=name,
value_padding=value_padding,
- adress_padding=adress_padding,
+ address_padding=address_padding,
)
self.bus_control_s.add_destination(self)
@@ -42,32 +42,32 @@ class MiaMemory(MiaBusConnector, Memory):
def update_register(self) -> None:
"""
- Updates the value of the current adress.
+ Updates the value of the current address.
"""
if self.read_from_bus():
- self.memory[self.current_adress] = self.input_s.get_value()
+ self.memory[self.current_address] = self.signals["in_input"].get_value()
def output_register(self) -> None:
"""
- Outputs the value of the current adress.
+ Outputs the value of the current address.
"""
if self.write_to_bus():
- self.output_s.update_value(self.memory[self.current_adress])
+ self.signals["out_content"].update_value(self.memory[self.current_address])
else:
- self.output_s.update_value(None)
+ self.signals["out_content"].update_value(None)
def update_logic(self) -> None:
"""
- Outputs the value of the current adress unless current adress
+ Outputs the value of the current address unless current address
is None
"""
- adress_value = self.adress_s.get_value()
- if adress_value is not None:
- self.current_adress = adress_value
+ address_value = self.signals["in_address"].get_value()
+ if address_value is not None:
+ self.current_address = address_value
if self.write_to_bus():
- self.output_s.update_value(self.memory[self.current_adress])
+ self.signals["out_content"].update_value(self.memory[self.current_address])
else:
- self.output_s.update_value(None)
+ self.signals["out_content"].update_value(None)
def reset(self) -> None:
size = len(self.memory)
@@ -103,13 +103,3 @@ class MiaMemory(MiaBusConnector, Memory):
return self.label_adress_mapping[adress]
return ""
-
- def get_input_signals(self) -> list[Signal]:
- return [
- self.bus_control_s,
- self.input_s,
- self.adress_s,
- ]
-
- def get_output_signals(self) -> list[Signal]:
- return [self.output_s]
diff --git a/src/simudator/processor/mia/modules/micro_memory.py b/src/simudator/processor/mia/modules/micro_memory.py
index 233fc4d3016f3f46c6056a7c2f10ea8ce5236266..7eb789584135f1e31dfbf09311bc8bea327da89d 100644
--- a/src/simudator/processor/mia/modules/micro_memory.py
+++ b/src/simudator/processor/mia/modules/micro_memory.py
@@ -22,8 +22,8 @@ class MicroMemory(Module):
alu: Signal,
bus_control: Signal,
bus_constant: Signal,
- s: Signal,
- p: Signal,
+ grx_control: Signal,
+ pc_control: Signal,
lc_control: Signal,
lc_uadr: Signal,
upc: Signal,
@@ -35,7 +35,7 @@ class MicroMemory(Module):
o_flag: Signal,
l_flag: Signal,
name: str = "uM",
- adress_padding: int = 2,
+ address_padding: int = 2,
value_padding: int = 7,
) -> None:
"""
@@ -48,9 +48,9 @@ class MicroMemory(Module):
from the bus.
bus_constant : Signal
Signal for sending uADR instruction field to bus.
- s : Signal
- Control signal for [XXXXXXXXXX]
- p : Signal
+ grx_control : Signal
+ Control signal for GRx.
+ pc_control : Signal
Control signal for program counter PC.
lc_control : Signal
Control signal for loop counter LC.
@@ -81,36 +81,26 @@ class MicroMemory(Module):
None
"""
- super().__init__(name)
-
- # Input signals
- self.upc_s = upc
- self.z_flag_s = z_flag
- self.n_flag_s = n_flag
- self.c_flag_s = c_flag
- self.o_flag_s = o_flag
- self.l_flag_s = l_flag
-
- # Register self as destination for input signals
- self.upc_s.add_destination(self)
- self.z_flag_s.add_destination(self)
- self.n_flag_s.add_destination(self)
- self.c_flag_s.add_destination(self)
- self.o_flag_s.add_destination(self)
- self.l_flag_s.add_destination(self)
-
- # Output control signals
- self.alu_s = alu
- self.bus_control_s = bus_control
- self.s_s = s
- self.p_s = p
- self.lc_control_s = lc_control
- self.upc_control_s = upc_control
-
- # Output data signals
- self.bus_constant_s = bus_constant
- self.upc_uadr_s = upc_uadr
- self.lc_uadr_s = lc_uadr
+
+ signals = {
+ "in_upc": upc,
+ "in_flag_z": z_flag,
+ "in_flag_n": n_flag,
+ "in_flag_c": c_flag,
+ "in_flag_o": o_flag,
+ "in_flag_l": l_flag,
+ "out_alu": alu,
+ "out_grx": grx_control,
+ "out_pc": pc_control,
+ "out_bus": bus_constant,
+ "out_upc": upc_uadr,
+ "out_lc": lc_uadr,
+ "out_control_bus": bus_control,
+ "out_control_lc": lc_control,
+ "out_control_upc": upc_control,
+ }
+
+ super().__init__(signals, name)
# Internal variables
self.curr_instr = 0
@@ -123,7 +113,7 @@ class MicroMemory(Module):
self.halt = False # Used for signalling a HALT
# paddings to ensure saving to file has the correct format
- self.adress_padding = adress_padding
+ self.address_padding = address_padding
self.value_padding = value_padding
def update_logic(self) -> None:
@@ -134,16 +124,16 @@ class MicroMemory(Module):
micro controller sets control signals to other modules in accordance
with the micro instruction pointed to.
"""
- instruction = self.upc_s.get_value()
+ instruction = self.signals["in_upc"].get_value()
if instruction is None:
return
self.curr_instr = instruction
- self.z_flag_val = self.z_flag_s.get_value()
- self.n_flag_val = self.n_flag_s.get_value()
- self.c_flag_val = self.c_flag_s.get_value()
- self.o_flag_val = self.o_flag_s.get_value()
- self.l_flag_val = self.l_flag_s.get_value()
+ self.z_flag_val = self.signals["in_flag_z"].get_value()
+ self.n_flag_val = self.signals["in_flag_n"].get_value()
+ self.c_flag_val = self.signals["in_flag_c"].get_value()
+ self.o_flag_val = self.signals["in_flag_o"].get_value()
+ self.l_flag_val = self.signals["in_flag_l"].get_value()
# Extract the different fields of the micro instruction
instr = self.memory[self.curr_instr]
@@ -163,64 +153,64 @@ class MicroMemory(Module):
# by the ALU
# Increase uPC by 1
instr_constant = instr & 0b1111111111111111
- self.alu_s.update_value(alu_field)
- self.bus_control_s.update_value((0b000, 0b000))
- self.bus_constant_s.update_value(instr_constant)
- self.upc_control_s.update_value(0)
+ self.signals["out_alu"].update_value(alu_field)
+ self.signals["out_control_bus"].update_value((0b000, 0b000))
+ self.signals["out_bus"].update_value(instr_constant)
+ self.signals["out_control_upc"].update_value(0)
# Make sure other control signals are set to 0 so that there
# is no unexpected behaviour from leftover signal values
- self.lc_control_s.update_value(0)
- self.p_s.update_value(0)
- self.s_s.update_value(0)
+ self.signals["out_control_lc"].update_value(0)
+ self.signals["out_pc"].update_value(0)
+ self.signals["out_grx"].update_value(0)
return
if (0b0001 <= alu_field <= 0b0010) or (0b0100 <= alu_field <= 0b1000):
# Special case for writing to the ALU from the bus, in which case
# the FB field of the instruction is ignored (overwritten, even)
- # (The ALU does not have an actual bus adress in the MIA processor)
+ # (The ALU does not have an actual bus address in the MIA processor)
fb_field = 0b1000
# Handle LC according to the LC field
match lc_field:
case 0b00:
- self.lc_control_s.update_value(0b00)
+ self.signals["out_control_lc"].update_value(0b00)
case 0b01:
- self.lc_control_s.update_value(0b01)
+ self.signals["out_control_lc"].update_value(0b01)
case 0b10:
- self.lc_control_s.update_value(0b10)
+ self.signals["out_control_lc"].update_value(0b10)
# fb_field = 0b1001 # Ignores actual FB field
case 0b11:
- self.lc_control_s.update_value(0b11)
- self.lc_uadr_s.update_value(uadr_field & 0b01111111)
+ self.signals["out_control_lc"].update_value(0b11)
+ self.signals["out_lc"].update_value(uadr_field & 0b01111111)
# Update control signals that require no special handling
- self.alu_s.update_value(alu_field)
- self.bus_constant_s.update_value(None)
- self.bus_control_s.update_value((tb_field, fb_field))
- self.s_s.update_value(s_field)
- self.p_s.update_value(p_field)
+ self.signals["out_alu"].update_value(alu_field)
+ self.signals["out_bus"].update_value(None)
+ self.signals["out_control_bus"].update_value((tb_field, fb_field))
+ self.signals["out_grx"].update_value(s_field)
+ self.signals["out_pc"].update_value(p_field)
# Handle uPC according to the SEQ field
match seq_field:
case 0b0000:
- self.upc_control_s.update_value(0b000)
+ self.signals["out_control_upc"].update_value(0b000)
case 0b0001:
- self.upc_control_s.update_value(0b001)
+ self.signals["out_control_upc"].update_value(0b001)
case 0b0010:
- self.upc_control_s.update_value(0b010)
+ self.signals["out_control_upc"].update_value(0b010)
case 0b0011:
- self.upc_control_s.update_value(0b011)
+ self.signals["out_control_upc"].update_value(0b011)
case 0b0100:
self._conditional_jump(self.z_flag_val, 0, uadr_field)
case 0b0101:
- self.upc_control_s.update_value(0b100)
- self.upc_uadr_s.update_value(uadr_field)
+ self.signals["out_control_upc"].update_value(0b100)
+ self.signals["out_upc"].update_value(uadr_field)
case 0b0110:
- self.upc_control_s.update_value(0b110)
- self.upc_uadr_s.update_value(uadr_field)
+ self.signals["out_control_upc"].update_value(0b110)
+ self.signals["out_upc"].update_value(uadr_field)
case 0b0111:
- self.upc_control_s.update_value(0b101)
+ self.signals["out_control_upc"].update_value(0b101)
case 0b1000:
self._conditional_jump(self.z_flag_val, 1, uadr_field)
case 0b1001:
@@ -237,7 +227,7 @@ class MicroMemory(Module):
self._conditional_jump(self.o_flag_val, 0, uadr_field)
case 0b1111:
# Halt is handled by update_register
- self.upc_control_s.update_value(0b011)
+ self.signals["out_control_upc"].update_value(0b011)
def update_register(self) -> None:
"""
@@ -246,10 +236,10 @@ class MicroMemory(Module):
Notes
-----
Although the micro memory is not a register, this override is needed to
- make sure a halt instruction is signalled on the actual clock cycle
+ make sure a halt instruction is signalled on the actual clock cycle
where it is "executed". All control signals for the halt will have been
- propagated at the end of the previous cycle. If the halt signalling
- were to be done in update_logic, the halt would erroneously be signaled
+ propagated at the end of the previous cycle. If the halt signalling
+ were to be done in update_logic, the halt would erroneously be signaled
one cycle to early.
"""
seq_field = (self.memory[self.curr_instr] >> 7) & 0b1111
@@ -264,10 +254,10 @@ class MicroMemory(Module):
true then uPC is increased by 1.
"""
if flag == cond_value:
- self.upc_control_s.update_value(0b100)
- self.upc_uadr_s.update_value(uadr)
+ self.signals["out_control_upc"].update_value(0b100)
+ self.signals["out_upc"].update_value(uadr)
return
- self.upc_control_s.update_value(0b000)
+ self.signals["out_control_upc"].update_value(0b000)
def print_module(self) -> None:
"""Print the contents of the micro memory.
@@ -276,9 +266,9 @@ class MicroMemory(Module):
value 0 are not printed.
"""
print("", self.name, "\n -----\n")
- for adress in range(len(self.memory)):
- if self.memory[adress] != 0:
- print("", str(adress), "", str(self.memory[adress]), "\n")
+ for address in range(len(self.memory)):
+ if self.memory[address] != 0:
+ print("", str(address), "", str(self.memory[address]), "\n")
def get_state(self) -> dict:
state = super().get_state()
@@ -297,31 +287,11 @@ class MicroMemory(Module):
if "halt" in state:
self.halt = state["halt"]
- def get_input_signals(self) -> [Signal]:
- return [
- self.upc_s,
- self.z_flag_s,
- self.n_flag_s,
- self.c_flag_s,
- self.o_flag_s,
- self.l_flag_s,
- ]
+ def output_register(self):
+ pass
def get_uPC_signal(self):
- return self.upc_s
-
- def get_output_signals(self) -> [Signal]:
- return [
- self.alu_s,
- self.bus_control_s,
- self.s_s,
- self.p_s,
- self.lc_control_s,
- self.upc_control_s,
- self.bus_constant_s,
- self.upc_uadr_s,
- self.lc_uadr_s,
- ]
+ return self.signals["in_upc"]
def reset(self) -> None:
self.curr_instr = 0
@@ -335,12 +305,12 @@ class MicroMemory(Module):
def load_from_str(self, state_string) -> None:
"""Load the contents of the micro memory from a string consisting of a
- row for every adress. Each row should be formatted as 'ADR: VALUE'.
- Both the adress and the value should be written in hex notation.
+ row for every address. Each row should be formatted as 'ADR: VALUE'.
+ Both the address and the value should be written in hex notation.
Adresses which are not specified in the string will receive the value
0.
- Example string where all adresses except for 0x00, 0x01 and 0xb0
+ Example string where all addresses except for 0x00, 0x01 and 0xb0
receive the value 0 by default::
'
@@ -356,17 +326,17 @@ class MicroMemory(Module):
for line in lines:
if line: # last line is empty from split with \n
line_data = line.split(": ")
- adress = int(line_data[0], 16)
+ address = int(line_data[0], 16)
value = int(line_data[1], 16)
- self.memory[adress] = value
+ self.memory[address] = value
def save_state_to_file(self, file_path: str) -> None:
"""Tries to save the modules state to a given file."""
file = open(file_path, "a")
file.write(self.name + ":\n")
for index, value in enumerate(self.memory):
- # Write the adress in hex and add ': ' to the end
- file.write(hex(index)[2:].rjust(self.adress_padding, "0") + ": ")
+ # Write the address in hex and add ': ' to the end
+ file.write(hex(index)[2:].rjust(self.address_padding, "0") + ": ")
# Write the value in hex
file.write(hex(value)[2:].rjust(self.value_padding, "0"))
file.write("\n")
@@ -376,7 +346,7 @@ class MicroMemory(Module):
def get_largest_mem_adr(self) -> int:
"""Helper function for pretty_print that returns the length of
- the largest adress in the memory to print for a module.
+ the largest address in the memory to print for a module.
"""
return len(str(len(self.memory)))
diff --git a/src/simudator/processor/mia/modules/micro_pc.py b/src/simudator/processor/mia/modules/micro_pc.py
index 1470c6edec5e254279d50037e1adca75c90d76c4..55500e7d68773ca19001f75553d238c0c14c1bf8 100644
--- a/src/simudator/processor/mia/modules/micro_pc.py
+++ b/src/simudator/processor/mia/modules/micro_pc.py
@@ -23,31 +23,25 @@ class MicroPC(Module):
bit_length: int = 8,
name: str = "uPC",
) -> None:
- super().__init__(name)
self.value = 0
self.bit_length = bit_length
- # Input signals
- self.control_signal = control_signal
- self.from_k1 = from_k1
- self.from_k2 = from_k2
- self.from_supc = from_supc
- self.from_um = from_um
-
- # Output signals
- self.to_supc = to_supc
- self.to_um = to_um
+ # Signals
+ signals = {
+ "in_control": control_signal,
+ "in_k1": from_k1,
+ "in_k2": from_k2,
+ "in_supc": from_supc,
+ "in_um": from_um,
+ "out_supc": to_supc,
+ "out_um": to_um,
+ }
- # Register as destination of the input signals
- control_signal.add_destination(self)
- from_k1.add_destination(self)
- from_k2.add_destination(self)
- from_supc.add_destination(self)
- from_um.add_destination(self)
+ super().__init__(signals, name)
def update_register(self) -> None:
- match self.control_signal.get_value():
+ match self.signals["in_control"].get_value():
case 0b000:
self.value += 1
@@ -56,21 +50,21 @@ class MicroPC(Module):
self.value = 0
case 0b001:
- self.value = self.from_k1.get_value()
+ self.value = self.signals["in_k1"].get_value()
case 0b010:
- self.value = self.from_k2.get_value()
+ self.value = self.signals["in_k2"].get_value()
case 0b011:
self.value = 0
case 0b100:
- self.value = self.from_um.get_value()
+ self.value = self.signals["in_um"].get_value()
case 0b101:
- self.value = self.from_supc.get_value()
+ self.value = self.signals["in_supc"].get_value()
case 0b110:
- self.to_supc.update_value(self.value + 1)
- self.value = self.from_um.get_value()
+ self.signals["out_supc"].update_value(self.value + 1)
+ self.value = self.signals["in_um"].get_value()
def output_register(self) -> None:
- self.to_um.update_value(self.value)
+ self.signals["out_um"].update_value(self.value)
def get_state(self) -> dict:
state = super().get_state()
@@ -97,6 +91,12 @@ class MicroPC(Module):
"""
self.value = 0
+ def update_logic(self) -> None:
+ """
+ The uPC has no logic.
+ """
+ pass
+
def save_state_to_file(self, file_path: str) -> None:
"""
Tries to save the modules state to a given file.
@@ -113,18 +113,3 @@ class MicroPC(Module):
def print_module(self) -> None:
print("", self.name, "\n -----", "\n value: ", hex(self.value))
-
- def get_input_signals(self) -> list[Signal]:
- return [
- self.control_signal,
- self.from_k1,
- self.from_k2,
- self.from_supc,
- self.from_um,
- ]
-
- def get_output_signals(self) -> list[Signal]:
- return [
- self.to_supc,
- self.to_um,
- ]
diff --git a/src/simudator/processor/mia/modules/pc.py b/src/simudator/processor/mia/modules/pc.py
index 4fe148bf6555c4969938fc40c73f6d2bac2e0d0a..575c4b65fde008511a6f184836c6e9cd43a4c973 100644
--- a/src/simudator/processor/mia/modules/pc.py
+++ b/src/simudator/processor/mia/modules/pc.py
@@ -28,18 +28,13 @@ class PC(Module, MiaBusConnector):
value=0,
) -> None:
MiaBusConnector.__init__(self, bus_control, bus_id)
- Module.__init__(self, name)
- # control signals
- self.p = p
-
- # input/output signals
- self.bus_input_s = bus_input
- self.bus_output_s = bus_output
-
- # set program counter as destination of all signlas
- self.p.add_destination(self)
- self.bus_input_s.add_destination(self)
+ signals = {
+ "in_control": p,
+ "in_input": bus_input,
+ "out_content": bus_output,
+ }
+ Module.__init__(self, signals, name)
# internal state
self.value = value
@@ -50,9 +45,9 @@ class PC(Module, MiaBusConnector):
def output_register(self) -> None:
"""Output the value of the program counter to the bus."""
if self.write_to_bus():
- self.bus_output_s.update_value(self.value)
+ self.signals["out_content"].update_value(self.value)
else:
- self.bus_output_s.update_value(None)
+ self.signals["out_content"].update_value(None)
def update_register(self) -> None:
"""Updates the value of the PC according to the signals sent by the micro memory.
@@ -61,14 +56,14 @@ class PC(Module, MiaBusConnector):
should do nothing and wait for the next cycle.
"""
- self.increase_by_one = self.p.get_value()
+ self.increase_by_one = self.signals["in_control"].get_value()
if self.increase_by_one and self.read_from_bus():
return
if self.read_from_bus():
# Read the 8 lowest bits from the bus
- self.value = self.bus_input_s.get_value() & 0xFF
+ self.value = self.signals["in_input"].get_value() & 0xFF
if self.increase_by_one:
self.value += 1
@@ -76,7 +71,7 @@ class PC(Module, MiaBusConnector):
def update_logic(self) -> None:
self.output_register()
- def get_state(self) -> dict[str:Any]:
+ def get_state(self) -> dict[str, Any]:
"""Returns a dict of the program counter state.
These states are changable via set_states.
@@ -100,7 +95,7 @@ class PC(Module, MiaBusConnector):
}
return state
- def set_state(self, state: dict[str:Any]) -> None:
+ def set_state(self, state: dict[str, Any]) -> None:
"""Sets the program counter state to one given in dict."""
self.name = state["name"]
self.value = state["value"]
@@ -127,8 +122,3 @@ class PC(Module, MiaBusConnector):
def print_module(self) -> None:
print("", self.name, "\n -----", "\n value: ", hex(self.value))
- def get_input_signals(self) -> list[Signal]:
- return [self.bus_input_s, self.p]
-
- def get_output_signals(self) -> list[Signal]:
- return [self.bus_output_s]
diff --git a/test/test_core/test_breakpoint.py b/test/test_core/test_breakpoint.py
index 27986d7ff411f8cd8351b7c0a16238e9c90fe5bb..01f115d012ba1a4cf042244d71761be28dd28673 100644
--- a/test/test_core/test_breakpoint.py
+++ b/test/test_core/test_breakpoint.py
@@ -1,6 +1,6 @@
-from simudator.core.breakpoint_state import StateBreakpoint
-from simudator.core.breakpoint_memory import MemoryBreakpoint
from simudator.core.breakpoint_lambda import LambdaBreakpoint
+from simudator.core.breakpoint_memory import MemoryBreakpoint
+from simudator.core.breakpoint_state import StateBreakpoint
from simudator.core.module import Module
from simudator.core.modules.memory import Memory
from simudator.core.processor import Processor
@@ -9,7 +9,7 @@ from simudator.core.signal import Signal
class DummyModule(Module):
def __init__(self, name: str = "") -> None:
- super().__init__(name)
+ super().__init__({}, name)
self.value = 0
def get_state(self) -> dict:
@@ -33,7 +33,7 @@ def test_state_breakpoint():
assert bp.is_break()
# Module state is no longer set to break value => should no longer break
- # Also checks that a value of a different type than that of the break value
+ # Also checks that a value of a different type than that of the break value
# does not cause issues
m.value = "-"
assert not bp.is_break()
@@ -86,13 +86,13 @@ def test_memory_breakpoint():
def test_lambda_breakpoint_no_args():
"""
- Test the functionality of LambdaBreakpoint when supplied with a function
+ Test the functionality of LambdaBreakpoint when supplied with a function
that takes no arguments.
"""
# Test functions with no arguments
# Function returns False => should not break
bp = LambdaBreakpoint(lambda: False)
- assert not bp.is_break()
+ assert not bp.is_break()
# Function returns True => should break
bp = LambdaBreakpoint(lambda: True)
@@ -101,9 +101,10 @@ def test_lambda_breakpoint_no_args():
def test_lambda_breakpoint_args():
"""
- Test the functionality of LambdaBreakpoint when supplied with a function
+ Test the functionality of LambdaBreakpoint when supplied with a function
that takes arguments.
"""
+
# Test functions with arguments
# Arguments of same type
def func_1(num, thres):
@@ -120,18 +121,21 @@ def test_lambda_breakpoint_args():
# Arguments of different types
def str_float_comp(string, num):
return float(string) == num
+
kwargs = {"string": "2.5", "num": 2.5}
bp = LambdaBreakpoint(str_float_comp, **kwargs)
assert bp.is_break() == str_float_comp(**kwargs)
-def test_lambda_breakpoint_ref_args():
+
+def test_lambda_breakpoint_ref_args():
"""
- Test the functionality of LambdaBreakpoint when supplied with a function
+ Test the functionality of LambdaBreakpoint when supplied with a function
that takes references as arguments.
"""
# Explicit comparison of references
l1 = []
l2 = []
+
def func_list_ref_comp(l):
return l is l2
@@ -145,13 +149,14 @@ def test_lambda_breakpoint_ref_args():
# Test that changes to a reference are reflected in the breakpoint
l = [1, 2, "a"]
+
def func_list_comp(l):
return l == [1, 2, "a", "b"]
kwargs = {"l": l}
bp = LambdaBreakpoint(func_list_comp, **kwargs)
- # The supplied list is not equal to the internal list of the
+ # The supplied list is not equal to the internal list of the
# supplied function => shoud not break
assert bp.is_break() == func_list_comp(l)
@@ -160,7 +165,6 @@ def test_lambda_breakpoint_ref_args():
l.append("b")
assert bp.is_break() == func_list_comp(l)
-
# Test with reference to a more advanced data structure, e.g. a class
class Dummy:
def __init__(self):
@@ -176,8 +180,7 @@ def test_lambda_breakpoint_ref_args():
assert bp.is_break() == func_dummy_val(dummy, value)
# The supplied argument should be a reference, so changes to `dummy`
- # should affect the break point
- dummy.value = value
+ # should affect the break point
+ dummy.value = value
assert bp.is_break() == func_dummy_val(dummy, value)
assert bp.is_break() == (not func_dummy_val(dummy, not value))
-
diff --git a/test/test_core/test_processor.py b/test/test_core/test_processor.py
index 7e978f5a419589e81d2a11a7c452c450261aefa8..cd6c65c7d635abf93c200e6d83918155d6de1bdd 100644
--- a/test/test_core/test_processor.py
+++ b/test/test_core/test_processor.py
@@ -10,7 +10,7 @@ class Dummymodule(Module):
self.string = None
def load_from_str(self, state_string):
- self.string = state_string
+ self.string = state_string
def get_string(self):
return self.string
@@ -18,6 +18,9 @@ class Dummymodule(Module):
def reset(self):
self.string = ""
+ def output_register(self):
+ pass
+
def test_load_from_file():
cpu = Processor()
diff --git a/test/test_mia/test_step.py b/test/test_mia/test_step.py
new file mode 100644
index 0000000000000000000000000000000000000000..028945db7c22021a701b68765ee734d70608f9e0
--- /dev/null
+++ b/test/test_mia/test_step.py
@@ -0,0 +1,34 @@
+from simudator.processor.mia.mia import MIA_CPU
+
+
+def test_increment_10():
+ cpu = MIA_CPU()
+ cpu.load_state_from_file("mia_uppg3.txt")
+
+ for itr in range(10000, 10):
+ for _ in range(itr):
+ cpu.do_tick()
+
+ for i in range(itr, -1):
+ cpu.load_cycle(i)
+
+
+def test_max_undo():
+ cpu = MIA_CPU()
+ cpu.load_state_from_file("mia_uppg3.txt")
+ max_undo = cpu.cycles_to_save
+
+ for _ in range(2 * max_undo):
+ cpu.do_tick()
+
+ cpu.load_cycle(max_undo)
+
+
+def test_do_50000_undo_one():
+ cpu = MIA_CPU()
+ cpu.load_state_from_file("mia_uppg3.txt")
+
+ for _ in range(50000):
+ cpu.do_tick()
+
+ cpu.load_cycle(50000 - 1)