diff --git a/src/simudator/core/processor.py b/src/simudator/core/processor.py
index b5269963bf81cb413f066bbb946b9344be6ba106..5a7be7b15b3d00af1c2e2e55223627826ef9efad 100644
--- a/src/simudator/core/processor.py
+++ b/src/simudator/core/processor.py
@@ -8,8 +8,8 @@ from simudator.core.breakpoint_memory import MemoryBreakpoint
from simudator.core.breakpoint_state import StateBreakpoint
from simudator.core.module import Module
from simudator.core.modules.memory import Memory
-from simudator.processor.mia.bus import Bus
-from simudator.processor.mia.micro_memory import MicroMemory
+from simudator.processor.mia.modules.bus import Bus
+from simudator.processor.mia.modules.micro_memory import MicroMemory
from .signal import Signal
diff --git a/src/simudator/gui/module_graphics_item/mia/__init__.py b/src/simudator/gui/module_graphics_item/mia/__init__.py
deleted file mode 100644
index 23fa55a545e67ba7cb5923817debab54d9ae5929..0000000000000000000000000000000000000000
--- a/src/simudator/gui/module_graphics_item/mia/__init__.py
+++ /dev/null
@@ -1,33 +0,0 @@
-from simudator.gui.module_graphics_item.mia.ar_graphic import ArGraphicsItem
-from simudator.gui.module_graphics_item.mia.asr_graphic import AsrGraphicsItem
-from simudator.gui.module_graphics_item.mia.bus_graphic import BusGraphicsItem
-from simudator.gui.module_graphics_item.mia.hr_graphic import HrGraphicsItem
-from simudator.gui.module_graphics_item.mia.mia_alu_graphic import AluGraphicsItem
-from simudator.gui.module_graphics_item.mia.mia_flag_graphic import FlagGraphicsItem
-from simudator.gui.module_graphics_item.mia.mia_grx_graphic import GrxGraphicsItem
-from simudator.gui.module_graphics_item.mia.mia_ir_graphic import IrGraphicsItem
-from simudator.gui.module_graphics_item.mia.mia_memory_graphic import (
- MiaMemoryGraphicsItem,
-)
-from simudator.gui.module_graphics_item.mia.mia_micro_memory_graphic import (
- MicroMemoryGraphicsItem,
-)
-from simudator.gui.module_graphics_item.mia.pc_graphic import PcGraphicsItem
-from simudator.gui.module_graphics_item.mia.supc_graphic import SupcGraphicsItem
-from simudator.gui.module_graphics_item.mia.upc_graphic import uPcGraphicsItem
-
-__all__ = [
- "MiaMemoryGraphicsItem",
- "MicroMemoryGraphicsItem",
- "ArGraphicsItem",
- "PcGraphicsItem",
- "AsrGraphicsItem",
- "HrGraphicsItem",
- "SupcGraphicsItem",
- "uPcGraphicsItem",
- "FlagGraphicsItem",
- "BusGraphicsItem",
- "AluGraphicsItem",
- "GrxGraphicsItem",
- "IrGraphicsItem",
-]
diff --git a/src/simudator/processor/__init__.py b/src/simudator/processor/__init__.py
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/src/simudator/processor/mia/__init__.py b/src/simudator/processor/mia/__init__.py
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/src/simudator/processor/mia/gui/__init__.py b/src/simudator/processor/mia/gui/__init__.py
new file mode 100644
index 0000000000000000000000000000000000000000..4934a674d7f2ba5f0dd37dec6bb52fdb9e60afff
--- /dev/null
+++ b/src/simudator/processor/mia/gui/__init__.py
@@ -0,0 +1,29 @@
+from .ar_graphic import ArGraphicsItem
+from .asr_graphic import AsrGraphicsItem
+from .bus_graphic import BusGraphicsItem
+from .hr_graphic import HrGraphicsItem
+from .mia_alu_graphic import AluGraphicsItem
+from .mia_flag_graphic import FlagGraphicsItem
+from .mia_grx_graphic import GrxGraphicsItem
+from .mia_ir_graphic import IrGraphicsItem
+from .mia_memory_graphic import MiaMemoryGraphicsItem
+from .mia_micro_memory_graphic import MicroMemoryGraphicsItem
+from .pc_graphic import PcGraphicsItem
+from .supc_graphic import SupcGraphicsItem
+from .upc_graphic import uPcGraphicsItem
+
+__all__ = [
+ "MiaMemoryGraphicsItem",
+ "MicroMemoryGraphicsItem",
+ "ArGraphicsItem",
+ "PcGraphicsItem",
+ "AsrGraphicsItem",
+ "HrGraphicsItem",
+ "SupcGraphicsItem",
+ "uPcGraphicsItem",
+ "FlagGraphicsItem",
+ "BusGraphicsItem",
+ "AluGraphicsItem",
+ "GrxGraphicsItem",
+ "IrGraphicsItem",
+]
diff --git a/src/simudator/gui/module_graphics_item/mia/ar_graphic.py b/src/simudator/processor/mia/gui/ar_graphic.py
similarity index 100%
rename from src/simudator/gui/module_graphics_item/mia/ar_graphic.py
rename to src/simudator/processor/mia/gui/ar_graphic.py
diff --git a/src/simudator/gui/module_graphics_item/mia/asr_graphic.py b/src/simudator/processor/mia/gui/asr_graphic.py
similarity index 100%
rename from src/simudator/gui/module_graphics_item/mia/asr_graphic.py
rename to src/simudator/processor/mia/gui/asr_graphic.py
diff --git a/src/simudator/gui/module_graphics_item/mia/bus_graphic.py b/src/simudator/processor/mia/gui/bus_graphic.py
similarity index 100%
rename from src/simudator/gui/module_graphics_item/mia/bus_graphic.py
rename to src/simudator/processor/mia/gui/bus_graphic.py
diff --git a/src/simudator/gui/module_graphics_item/mia/hr_graphic.py b/src/simudator/processor/mia/gui/hr_graphic.py
similarity index 100%
rename from src/simudator/gui/module_graphics_item/mia/hr_graphic.py
rename to src/simudator/processor/mia/gui/hr_graphic.py
diff --git a/src/simudator/gui/module_graphics_item/mia/mia_alu_graphic.py b/src/simudator/processor/mia/gui/mia_alu_graphic.py
similarity index 100%
rename from src/simudator/gui/module_graphics_item/mia/mia_alu_graphic.py
rename to src/simudator/processor/mia/gui/mia_alu_graphic.py
diff --git a/src/simudator/gui/module_graphics_item/mia/mia_flag_graphic.py b/src/simudator/processor/mia/gui/mia_flag_graphic.py
similarity index 100%
rename from src/simudator/gui/module_graphics_item/mia/mia_flag_graphic.py
rename to src/simudator/processor/mia/gui/mia_flag_graphic.py
diff --git a/src/simudator/gui/module_graphics_item/mia/mia_grx_graphic.py b/src/simudator/processor/mia/gui/mia_grx_graphic.py
similarity index 97%
rename from src/simudator/gui/module_graphics_item/mia/mia_grx_graphic.py
rename to src/simudator/processor/mia/gui/mia_grx_graphic.py
index 3b4bbf9027ac0f904f2446d2e25f44bbd4c70e7b..a3de6f2b8187675b442864930a1e81387cb7ff1d 100644
--- a/src/simudator/gui/module_graphics_item/mia/mia_grx_graphic.py
+++ b/src/simudator/processor/mia/gui/mia_grx_graphic.py
@@ -9,11 +9,11 @@ from qtpy.QtWidgets import (
QGraphicsSimpleTextItem,
)
-from simudator.gui.module_graphics_item.mia.bus_graphic import BusGraphicsItem
from simudator.gui.module_graphics_item.module_graphics_item import ModuleGraphicsItem
from simudator.gui.orientation import Orientation
from simudator.gui.port_graphics_item import PortGraphicsItem
-from simudator.processor.mia.mia_grx import GRX
+from simudator.processor.mia.gui.bus_graphic import BusGraphicsItem
+from simudator.processor.mia.modules.mia_grx import GRX
class GrxGraphicsItem(ModuleGraphicsItem):
diff --git a/src/simudator/gui/module_graphics_item/mia/mia_ir_graphic.py b/src/simudator/processor/mia/gui/mia_ir_graphic.py
similarity index 100%
rename from src/simudator/gui/module_graphics_item/mia/mia_ir_graphic.py
rename to src/simudator/processor/mia/gui/mia_ir_graphic.py
diff --git a/src/simudator/gui/module_graphics_item/mia/mia_memory_content_dialog.py b/src/simudator/processor/mia/gui/mia_memory_content_dialog.py
similarity index 100%
rename from src/simudator/gui/module_graphics_item/mia/mia_memory_content_dialog.py
rename to src/simudator/processor/mia/gui/mia_memory_content_dialog.py
diff --git a/src/simudator/gui/module_graphics_item/mia/mia_memory_graphic.py b/src/simudator/processor/mia/gui/mia_memory_graphic.py
similarity index 97%
rename from src/simudator/gui/module_graphics_item/mia/mia_memory_graphic.py
rename to src/simudator/processor/mia/gui/mia_memory_graphic.py
index 759df324b6453fa63202c789990cf1aa65b31a19..e3c314a88f855d411ec5a7f3b86716a656644519 100644
--- a/src/simudator/gui/module_graphics_item/mia/mia_memory_graphic.py
+++ b/src/simudator/processor/mia/gui/mia_memory_graphic.py
@@ -12,11 +12,9 @@ from qtpy.QtWidgets import (
from simudator.core.modules import Memory
from simudator.gui.color_scheme import ColorScheme as CS
from simudator.gui.module_graphics_item.memory_graphic import MemoryGraphicsItem
-from simudator.gui.module_graphics_item.mia.mia_memory_content_dialog import (
- MiaMemoryContentDialog,
-)
from simudator.gui.orientation import Orientation
from simudator.gui.port_graphics_item import PortGraphicsItem
+from simudator.processor.mia.gui.mia_memory_content_dialog import MiaMemoryContentDialog
class MiaMemoryWindow(QWidget):
diff --git a/src/simudator/gui/module_graphics_item/mia/mia_micro_memory_graphic.py b/src/simudator/processor/mia/gui/mia_micro_memory_graphic.py
similarity index 94%
rename from src/simudator/gui/module_graphics_item/mia/mia_micro_memory_graphic.py
rename to src/simudator/processor/mia/gui/mia_micro_memory_graphic.py
index d0b4402f5bc30443770444677a3d47cb2e6c48dd..f23c01bebd3e431836356f72a4371dcfa2ef4e3e 100644
--- a/src/simudator/gui/module_graphics_item/mia/mia_micro_memory_graphic.py
+++ b/src/simudator/processor/mia/gui/mia_micro_memory_graphic.py
@@ -1,11 +1,9 @@
from qtpy.QtWidgets import QGraphicsRectItem, QGraphicsSimpleTextItem
-from simudator.gui.module_graphics_item.mia.mia_memory_graphic import (
- MiaMemoryGraphicsItem,
-)
from simudator.gui.orientation import Orientation
from simudator.gui.port_graphics_item import PortGraphicsItem
-from simudator.processor.mia.micro_memory import MicroMemory
+from simudator.processor.mia.gui.mia_memory_graphic import MiaMemoryGraphicsItem
+from simudator.processor.mia.modules.micro_memory import MicroMemory
class MicroMemoryGraphicsItem(MiaMemoryGraphicsItem):
diff --git a/src/simudator/gui/module_graphics_item/mia/pc_graphic.py b/src/simudator/processor/mia/gui/pc_graphic.py
similarity index 100%
rename from src/simudator/gui/module_graphics_item/mia/pc_graphic.py
rename to src/simudator/processor/mia/gui/pc_graphic.py
diff --git a/src/simudator/gui/module_graphics_item/mia/supc_graphic.py b/src/simudator/processor/mia/gui/supc_graphic.py
similarity index 100%
rename from src/simudator/gui/module_graphics_item/mia/supc_graphic.py
rename to src/simudator/processor/mia/gui/supc_graphic.py
diff --git a/src/simudator/gui/module_graphics_item/mia/upc_graphic.py b/src/simudator/processor/mia/gui/upc_graphic.py
similarity index 100%
rename from src/simudator/gui/module_graphics_item/mia/upc_graphic.py
rename to src/simudator/processor/mia/gui/upc_graphic.py
diff --git a/src/simudator/processor/mia/mia.py b/src/simudator/processor/mia/mia.py
index b6576113e497e431d272a214c2ce47ff9a639f29..913b2dd770255e4b10246823dead9125d5345a85 100644
--- a/src/simudator/processor/mia/mia.py
+++ b/src/simudator/processor/mia/mia.py
@@ -5,7 +5,7 @@ from simudator.core.modules import Flag
from simudator.core.modules.register import IntegerRegister
from simudator.core.processor import Processor, Signal
from simudator.gui.gui import GUI
-from simudator.gui.module_graphics_item.mia import (
+from simudator.processor.mia.gui import (
AluGraphicsItem,
ArGraphicsItem,
AsrGraphicsItem,
@@ -20,23 +20,23 @@ from simudator.gui.module_graphics_item.mia import (
SupcGraphicsItem,
uPcGraphicsItem,
)
-from simudator.processor.mia.alu import ALU
-from simudator.processor.mia.ar import AR
-from simudator.processor.mia.asr import ASR
-from simudator.processor.mia.bus import Bus
-from simudator.processor.mia.hr import HR
-from simudator.processor.mia.ir import IR
-from simudator.processor.mia.lc import LC
-from simudator.processor.mia.mia_grx import GRX
-from simudator.processor.mia.mia_memory import MiaMemory
-from simudator.processor.mia.micro_memory import MicroMemory
-from simudator.processor.mia.micro_pc import MicroPC
+from simudator.processor.mia.modules.alu import ALU
+from simudator.processor.mia.modules.ar import AR
+from simudator.processor.mia.modules.asr import ASR
+from simudator.processor.mia.modules.bus import Bus
+from simudator.processor.mia.modules.hr import HR
+from simudator.processor.mia.modules.ir import IR
+from simudator.processor.mia.modules.lc import LC
+from simudator.processor.mia.modules.mia_grx import GRX
+from simudator.processor.mia.modules.mia_memory import MiaMemory
+from simudator.processor.mia.modules.micro_memory import MicroMemory
+from simudator.processor.mia.modules.micro_pc import MicroPC
# Using a bare expect is generally bad code practice,
# howere here we want to load the default layout if
# anything goes wrong with loading the selected one,
# we dont care about what went wrong
-from simudator.processor.mia.pc import PC
+from simudator.processor.mia.modules.pc import PC
class MIA_CPU(Processor):
diff --git a/src/simudator/processor/mia/modules/__init__.py b/src/simudator/processor/mia/modules/__init__.py
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/src/simudator/processor/mia/alu.py b/src/simudator/processor/mia/modules/alu.py
similarity index 100%
rename from src/simudator/processor/mia/alu.py
rename to src/simudator/processor/mia/modules/alu.py
diff --git a/src/simudator/processor/mia/ar.py b/src/simudator/processor/mia/modules/ar.py
similarity index 95%
rename from src/simudator/processor/mia/ar.py
rename to src/simudator/processor/mia/modules/ar.py
index ee651082c41a9bcb37e2571568fb00d4bb70a697..19eca435ca649d49f28481f82a4d77495975a071 100644
--- a/src/simudator/processor/mia/ar.py
+++ b/src/simudator/processor/mia/modules/ar.py
@@ -1,6 +1,6 @@
from simudator.core.modules.register import IntegerRegister
from simudator.core.signal import Signal
-from simudator.processor.mia.mia_bus_connect import MiaBusConnector
+from simudator.processor.mia.modules.mia_bus_connect import MiaBusConnector
class AR(IntegerRegister, MiaBusConnector):
diff --git a/src/simudator/processor/mia/asr.py b/src/simudator/processor/mia/modules/asr.py
similarity index 94%
rename from src/simudator/processor/mia/asr.py
rename to src/simudator/processor/mia/modules/asr.py
index 4bc5de379a75689c9c0ec14c684f8d4b6a42dfa3..3b5a53ed96341aa7c51ad678eaa542353ff35999 100644
--- a/src/simudator/processor/mia/asr.py
+++ b/src/simudator/processor/mia/modules/asr.py
@@ -1,6 +1,6 @@
from simudator.core.modules.register import IntegerRegister
from simudator.core.signal import Signal
-from simudator.processor.mia.mia_bus_connect import MiaBusConnector
+from simudator.processor.mia.modules.mia_bus_connect import MiaBusConnector
class ASR(IntegerRegister, MiaBusConnector):
diff --git a/src/simudator/processor/mia/bus.py b/src/simudator/processor/mia/modules/bus.py
similarity index 100%
rename from src/simudator/processor/mia/bus.py
rename to src/simudator/processor/mia/modules/bus.py
diff --git a/src/simudator/processor/mia/hr.py b/src/simudator/processor/mia/modules/hr.py
similarity index 96%
rename from src/simudator/processor/mia/hr.py
rename to src/simudator/processor/mia/modules/hr.py
index a817c87cce53c94454f3ed92799c3d6d14e6f3b1..2a2d869792a87f4e21b16ad208798140fa4d0ad4 100644
--- a/src/simudator/processor/mia/hr.py
+++ b/src/simudator/processor/mia/modules/hr.py
@@ -1,6 +1,6 @@
from simudator.core.modules.register import IntegerRegister
from simudator.core.signal import Signal
-from simudator.processor.mia.mia_bus_connect import MiaBusConnector
+from simudator.processor.mia.modules.mia_bus_connect import MiaBusConnector
class HR(IntegerRegister, MiaBusConnector):
diff --git a/src/simudator/processor/mia/ir.py b/src/simudator/processor/mia/modules/ir.py
similarity index 98%
rename from src/simudator/processor/mia/ir.py
rename to src/simudator/processor/mia/modules/ir.py
index 0e4a5639db5e98959706888b166d017d224b9b20..6d0e4ca0b0658e4492fd53e79ed1cfb002784387 100644
--- a/src/simudator/processor/mia/ir.py
+++ b/src/simudator/processor/mia/modules/ir.py
@@ -2,7 +2,7 @@ from typing import Any
from simudator.core.module import Module
from simudator.core.signal import Signal
-from simudator.processor.mia.mia_bus_connect import MiaBusConnector
+from simudator.processor.mia.modules.mia_bus_connect import MiaBusConnector
class IR(Module, MiaBusConnector):
diff --git a/src/simudator/processor/mia/lc.py b/src/simudator/processor/mia/modules/lc.py
similarity index 100%
rename from src/simudator/processor/mia/lc.py
rename to src/simudator/processor/mia/modules/lc.py
diff --git a/src/simudator/processor/mia/mia_bus_connect.py b/src/simudator/processor/mia/modules/mia_bus_connect.py
similarity index 100%
rename from src/simudator/processor/mia/mia_bus_connect.py
rename to src/simudator/processor/mia/modules/mia_bus_connect.py
diff --git a/src/simudator/processor/mia/mia_grx.py b/src/simudator/processor/mia/modules/mia_grx.py
similarity index 98%
rename from src/simudator/processor/mia/mia_grx.py
rename to src/simudator/processor/mia/modules/mia_grx.py
index 75379bbcc82278e98c322f78cd6bfc292aef1efd..1c5a33ef42b3d995c065aeeb31e107b4039cf8bb 100644
--- a/src/simudator/processor/mia/mia_grx.py
+++ b/src/simudator/processor/mia/modules/mia_grx.py
@@ -4,7 +4,7 @@ from typing import Any
from simudator.core.module import Module
from simudator.core.signal import Signal
-from simudator.processor.mia.mia_bus_connect import MiaBusConnector
+from simudator.processor.mia.modules.mia_bus_connect import MiaBusConnector
class GRX(Module, MiaBusConnector):
diff --git a/src/simudator/processor/mia/mia_memory.py b/src/simudator/processor/mia/modules/mia_memory.py
similarity index 97%
rename from src/simudator/processor/mia/mia_memory.py
rename to src/simudator/processor/mia/modules/mia_memory.py
index cfac7f1414e04909c5cea78a508ecfa57d555176..f3d0f600dae3168e937bfb034ce0665069f4af58 100644
--- a/src/simudator/processor/mia/mia_memory.py
+++ b/src/simudator/processor/mia/modules/mia_memory.py
@@ -1,6 +1,6 @@
from simudator.core.modules.memory import Memory
from simudator.core.signal import Signal
-from simudator.processor.mia.mia_bus_connect import MiaBusConnector
+from simudator.processor.mia.modules.mia_bus_connect import MiaBusConnector
class MiaMemory(MiaBusConnector, Memory):
diff --git a/src/simudator/processor/mia/micro_memory.py b/src/simudator/processor/mia/modules/micro_memory.py
similarity index 100%
rename from src/simudator/processor/mia/micro_memory.py
rename to src/simudator/processor/mia/modules/micro_memory.py
diff --git a/src/simudator/processor/mia/micro_pc.py b/src/simudator/processor/mia/modules/micro_pc.py
similarity index 100%
rename from src/simudator/processor/mia/micro_pc.py
rename to src/simudator/processor/mia/modules/micro_pc.py
diff --git a/src/simudator/processor/mia/pc.py b/src/simudator/processor/mia/modules/pc.py
similarity index 98%
rename from src/simudator/processor/mia/pc.py
rename to src/simudator/processor/mia/modules/pc.py
index 39100e2385bda8f7f021c441dacd4f2425633ec1..f5fd9651c2a5419896a22b2dd3993df4a4712f74 100644
--- a/src/simudator/processor/mia/pc.py
+++ b/src/simudator/processor/mia/modules/pc.py
@@ -4,7 +4,7 @@ from typing import Any
from simudator.core.module import Module
from simudator.core.signal import Signal
-from simudator.processor.mia.mia_bus_connect import MiaBusConnector
+from simudator.processor.mia.modules.mia_bus_connect import MiaBusConnector
class PC(Module, MiaBusConnector):
diff --git a/test/test_mia/test_alu.py b/test/test_mia/test_alu.py
index b053502077bc1664b913a0a551db938085c99303..09ebf6405f7bf7f32dcd05a932a828b9b3f8289f 100644
--- a/test/test_mia/test_alu.py
+++ b/test/test_mia/test_alu.py
@@ -1,6 +1,6 @@
from simudator.core.processor import Processor
from simudator.core.signal import Signal
-from simudator.processor.mia.alu import ALU
+from simudator.processor.mia.modules.alu import ALU
cpu = Processor()
input_signal_a = Signal(cpu)
diff --git a/test/test_mia/test_bus.py b/test/test_mia/test_bus.py
index 0f8257c18203c82d3285f8b57d68999edafdde48..026b23d991ce309d1def81bf9bb73466875b12c5 100644
--- a/test/test_mia/test_bus.py
+++ b/test/test_mia/test_bus.py
@@ -1,6 +1,6 @@
from simudator.core.processor import Processor
from simudator.core.signal import Signal
-from simudator.processor.mia.bus import Bus
+from simudator.processor.mia.modules.bus import Bus
def test_bus():
@@ -20,8 +20,8 @@ def test_bus():
# Test that nothing changes when there is no input to the bus
cpu.do_tick()
- assert out_s_1.get_value() == None
- assert out_s_2.get_value() == None
+ assert out_s_1.get_value() is None
+ assert out_s_2.get_value() is None
# Test that all output signals are given the input value
# when there is input to the bus
diff --git a/test/test_mia/test_ir.py b/test/test_mia/test_ir.py
index cb06b0d090b86d9d762a0bef8398328b69caf6d1..113a19c1cd885e960b6ea3641626136e764a0e7d 100644
--- a/test/test_mia/test_ir.py
+++ b/test/test_mia/test_ir.py
@@ -1,6 +1,6 @@
from simudator.core.processor import Processor
from simudator.core.signal import Signal
-from simudator.processor.mia.ir import IR
+from simudator.processor.mia.modules.ir import IR
def test_ir():
diff --git a/test/test_mia/test_lc.py b/test/test_mia/test_lc.py
index 53da2e8d78b24f962892c3ff7f35e5dbbcd0d13a..aaa591c611a661a94302578b79dd0c2ba4400d0d 100644
--- a/test/test_mia/test_lc.py
+++ b/test/test_mia/test_lc.py
@@ -1,7 +1,7 @@
from simudator.core.modules import Flag
from simudator.core.processor import Processor
from simudator.core.signal import Signal
-from simudator.processor.mia.lc import LC
+from simudator.processor.mia.modules.lc import LC
def test_default_name():
diff --git a/test/test_mia/test_mia_grx.py b/test/test_mia/test_mia_grx.py
index 89e8036e8d87f8b30fcedd8c59d9789891a7b7c2..7740e2a673c800c3264a2fd7303d0ee75de70cae 100644
--- a/test/test_mia/test_mia_grx.py
+++ b/test/test_mia/test_mia_grx.py
@@ -1,6 +1,6 @@
from simudator.core.processor import Processor
from simudator.core.signal import Signal
-from simudator.processor.mia.mia_grx import GRX
+from simudator.processor.mia.modules.mia_grx import GRX
def test_default_name():
diff --git a/test/test_mia/test_mia_memory.py b/test/test_mia/test_mia_memory.py
index e9db642396db3ddd0afd3657bbe0ed41d819fa74..99e0227c01bf6edc1869fbf16487931704af93b5 100644
--- a/test/test_mia/test_mia_memory.py
+++ b/test/test_mia/test_mia_memory.py
@@ -1,6 +1,6 @@
from simudator.core.processor import Processor
from simudator.core.signal import Signal
-from simudator.processor.mia.mia_memory import MiaMemory
+from simudator.processor.mia.modules.mia_memory import MiaMemory
def test_read():
diff --git a/test/test_mia/test_mia_register.py b/test/test_mia/test_mia_register.py
index d796dcce3195082611b25d50dd8674cf7e140aa6..206af5a4af55710559b102a2e0411a5edf166939 100644
--- a/test/test_mia/test_mia_register.py
+++ b/test/test_mia/test_mia_register.py
@@ -1,8 +1,8 @@
from simudator.core.processor import Processor
from simudator.core.signal import Signal
-from simudator.processor.mia.ar import AR
-from simudator.processor.mia.asr import ASR
-from simudator.processor.mia.hr import HR
+from simudator.processor.mia.modules.ar import AR
+from simudator.processor.mia.modules.asr import ASR
+from simudator.processor.mia.modules.hr import HR
def test_asr():
diff --git a/test/test_mia/test_micro_memory.py b/test/test_mia/test_micro_memory.py
index 971b97d98ecaf94a0408a8953c0cd17b934397f6..efa544c6c1028b8c19aa757a43c783eed365f896 100644
--- a/test/test_mia/test_micro_memory.py
+++ b/test/test_mia/test_micro_memory.py
@@ -1,6 +1,6 @@
from simudator.core.processor import Processor
from simudator.core.signal import Signal
-from simudator.processor.mia.micro_memory import MicroMemory
+from simudator.processor.mia.modules.micro_memory import MicroMemory
def test_alu_field():
diff --git a/test/test_mia/test_micro_pc.py b/test/test_mia/test_micro_pc.py
index 28032cd9ca7dd125dd71d53a0bcdc363dad2e9cb..1772b552331e538153f4170570d8c7b4a23320b7 100644
--- a/test/test_mia/test_micro_pc.py
+++ b/test/test_mia/test_micro_pc.py
@@ -1,6 +1,6 @@
from simudator.core.processor import Processor
from simudator.core.signal import Signal
-from simudator.processor.mia.micro_pc import MicroPC
+from simudator.processor.mia.modules.micro_pc import MicroPC
def test_upc():
diff --git a/test/test_mia/test_pc.py b/test/test_mia/test_pc.py
index 5e672ec1b7681323aa7282adae7a5326ddb8a14a..48d216cfd83ef37ae7cfea4a73efd9e54d3f06a3 100644
--- a/test/test_mia/test_pc.py
+++ b/test/test_mia/test_pc.py
@@ -1,6 +1,6 @@
from simudator.core.processor import Processor
from simudator.core.signal import Signal
-from simudator.processor.mia.pc import PC
+from simudator.processor.mia.modules.pc import PC
def test_default_name():