diff --git a/src/simudator/core/modules/register.py b/src/simudator/core/modules/register.py
index 00f0dfef3f62e7ffda01b5a75a7601782e10928c..f33b89e4d65bacc337013f806ee8ec0b96330e72 100644
--- a/src/simudator/core/modules/register.py
+++ b/src/simudator/core/modules/register.py
@@ -54,12 +54,7 @@ class Register(Module):
         self._value = input_value
 
     def output_register(self) -> None:
-        """
-        Propagate the value of the register to the output signal.
-
-        It is the response of the destination to know when it should
-        read the output.
-        """
+        """Output the value of the register onto the output signal."""
         self.signals["out_content"].update_value(self._value)
 
     def update_logic(self):
@@ -71,11 +66,6 @@ class Register(Module):
         pass
 
     def get_state(self) -> dict[str, Any]:
-        """
-        Returns a dict of the register state.
-
-        These states are changeable via set_states.
-        """
         state = super().get_state()
         state["value"] = self._value
         return state
@@ -99,16 +89,11 @@ class Register(Module):
 
     def reset(self) -> None:
         """
-        Resets the register to 0.
+        Reset the register to 0.
         """
         self._value = 0
 
     def save_state_to_file(self, file_path: str) -> bool:
-        """
-        Tries to save the modules state to a given file.
-
-        Returns true on success and false if something went wrong.
-        """
         content = self.name + ":\n" + "value: " + str(self._value) + "\n\n"
         return super()._helper_save_state_to_file(file_path, content)
 
@@ -182,9 +167,6 @@ class IntegerRegister(Register):
         super().set_state(state)
 
     def save_state_to_file(self, file_path: str) -> None:
-        """
-        Tries to save the modules state to a given file.
-        """
         file = open(file_path, "a")
         file.write(self.name + ":\n")
         file.write("value: " + hex(self._value)[2:] + "\n\n")