diff --git a/src/simudator/core/modules/memory.py b/src/simudator/core/modules/memory.py
index 492601d6a4f3916924536123d90463391f4ac381..43c21188996ebd0d6205df308e3cc3a2a36bd6cf 100644
--- a/src/simudator/core/modules/memory.py
+++ b/src/simudator/core/modules/memory.py
@@ -1,49 +1,66 @@
from __future__ import annotations
+from typing import Any
+
from simudator.core.module import Module
from simudator.core.signal import Signal
+# Used to pad the values of the memory when saving to file
+VALUE_PADDING = 2
+ADDRESS_PADDING = 2
+
class Memory(Module):
"""
A general size memory module.
+
+ Parameters
+ ----------
+ input : Signal
+ Signal of which the value may be written to the current address.
+ output : Signal
+ Signal to which the content of the current address is written.
+ control : Signal
+ Signal used to enable or disable write to the current address. Assumed
+ to output ``bool``.
+ address : Signal
+ Signal used to address the memory. Assumed to output ``int``.
+ size : int
+ Size of the address space of the memory.
+ name : str
+ Name of the module.
"""
def __init__(
self,
- input_signal: Signal,
- output_signal: Signal,
- control_signal: Signal,
- address_signal: Signal,
+ input: Signal,
+ output: Signal,
+ control: Signal,
+ address: Signal,
size: int,
- value_padding: int = 2,
- address_padding: int = 2,
name="Memory",
) -> None:
# signals
signals = {
- "in_input": input_signal,
- "in_control": control_signal,
- "in_address": address_signal,
- "out_content": output_signal
+ "in_input": input,
+ "in_control": control,
+ "in_address": address,
+ "out_content": output,
}
# Init super class
super().__init__(signals, name)
# Internal state
- self.memory = [0 for i in range(size)]
- self.current_address = 0
- self.is_write = False
-
- # Values used to format the strings when saving state to file
- self.address_padding = address_padding
- self.value_padding = value_padding
+ self._memory = [0 for _ in range(size)]
+ self._current_address = 0
+ self._is_write = False
def update_register(self):
- if self.is_write:
- self.memory[self.current_address] = self.signals["in_input"].get_value()
+ if self._is_write:
+ value = self.signals["in_input"].get_value()
+ self._memory[self._current_address] = value
def output_register(self) -> None:
pass
@@ -54,59 +71,50 @@ class Memory(Module):
adr_sig = self.signals["in_address"]
ctrl_sig = self.signals["in_control"]
out_sig = self.signals["out_content"]
- if (
-
- adr_sig.get_value() is not None
- and ctrl_sig.get_value() is not None
- ):
- self.is_write = ctrl_sig.get_value()
- self.current_address = adr_sig.get_value()
- out_sig.update_value(self.memory[self.current_address])
+ if adr_sig.get_value() is not None and ctrl_sig.get_value() is not None:
+ self._is_write = ctrl_sig.get_value()
+ self._current_address = adr_sig.get_value()
+ out_sig.update_value(self._memory[self._current_address])
def print_module(self) -> None:
print("", self.name, "\n -----")
- for address, value in enumerate(self.memory):
+ for address, value in enumerate(self._memory):
if value:
print("", str(hex(address)), "", str(hex(value)), "\n")
- def get_state(self) -> dict:
+ def get_state(self) -> dict[str, Any]:
state = super().get_state()
- state["is_write"] = self.is_write
- state["current_address"] = self.current_address
- state["memory"] = self.memory[:]
+ state["is_write"] = self._is_write
+ state["current_address"] = self._current_address
+ state["memory"] = self._memory[:]
return state
- def get_gui_state(self) -> dict:
+ def get_gui_state(self) -> dict[str, Any]:
state = super().get_gui_state()
- state["current_address"] = self.current_address
- state["memory"] = self.memory[:]
+ state["current_address"] = self._current_address
+ state["memory"] = self._memory[:]
return state
- def set_state(self, state: dict) -> None:
+ def set_state(self, state: dict[str, Any]) -> None:
super().set_state(state)
if "is_write" in state:
- self.is_write = state["is_write"]
+ self._is_write = state["is_write"]
if "current_address" in state:
- self.current_address = state["current_address"]
+ self._current_address = state["current_address"]
if "memory" in state:
- self.memory = state["memory"]
+ self._memory = state["memory"]
def reset(self) -> None:
"""
Reset the memory to 0 for each address.
"""
- for i in range(len(self.memory)):
- self.memory[i] = 0
+ for i in range(len(self._memory)):
+ self._memory[i] = 0
def get_longest_line_len(self, ignore_keys=[]) -> int:
- """
- Helper function for pretty_print that returns the length of
- the longest value in the memory to print for a module.
- """
-
longest_memory_line = 0
- for value in self.memory:
+ for value in self._memory:
value_len = len(str(value))
if value_len > longest_memory_line:
longest_memory_line = value_len
@@ -118,19 +126,16 @@ class Memory(Module):
Helper function for pretty_print that returns the length of
the largest address in the memory to print for a module.
"""
- return len(str(len(self.memory)))
+ return len(str(len(self._memory)))
- def save_state_to_file(self, file_path: str) -> None:
- """
- Tries to save the modules state to a given file.
- """
+ def save_state_to_file(self, file_path: str) -> bool:
file = open(file_path, "a")
file.write(self.name + ":\n")
- for index, value in enumerate(self.memory):
+ for index, value in enumerate(self._memory):
# Write the address in hex and add ': ' to the end
- file.write(hex(index)[2:].rjust(self.address_padding, "0") + ": ")
+ file.write(hex(index)[2:].rjust(ADDRESS_PADDING, "0") + ": ")
# Write the value in hex
- file.write(hex(value)[2:].rjust(self.value_padding, "0"))
+ file.write(hex(value)[2:].rjust(VALUE_PADDING, "0"))
file.write("\n")
file.write("\n")
diff --git a/src/simudator/processor/mia/modules/mia_memory.py b/src/simudator/processor/mia/modules/mia_memory.py
index cc66d8b853a2c176b5c2cc4bc9d13dc2c54cabc2..733f3ecb2b5a7829c9c08048316adfc9ca5c9858 100644
--- a/src/simudator/processor/mia/modules/mia_memory.py
+++ b/src/simudator/processor/mia/modules/mia_memory.py
@@ -32,8 +32,6 @@ class MiaMemory(MiaBusConnector, Memory):
address_signal,
size,
name=name,
- value_padding=value_padding,
- address_padding=address_padding,
)
self.bus_control_s.add_destination(self)
@@ -45,14 +43,16 @@ class MiaMemory(MiaBusConnector, Memory):
Updates the value of the current address.
"""
if self.read_from_bus():
- self.memory[self.current_address] = self.signals["in_input"].get_value()
+ self._memory[self._current_address] = self.signals["in_input"].get_value()
def output_register(self) -> None:
"""
Outputs the value of the current address.
"""
if self.write_to_bus():
- self.signals["out_content"].update_value(self.memory[self.current_address])
+ self.signals["out_content"].update_value(
+ self._memory[self._current_address]
+ )
else:
self.signals["out_content"].update_value(None)
@@ -63,15 +63,17 @@ class MiaMemory(MiaBusConnector, Memory):
"""
address_value = self.signals["in_address"].get_value()
if address_value is not None:
- self.current_address = address_value
+ self._current_address = address_value
if self.write_to_bus():
- self.signals["out_content"].update_value(self.memory[self.current_address])
+ self.signals["out_content"].update_value(
+ self._memory[self._current_address]
+ )
else:
self.signals["out_content"].update_value(None)
def reset(self) -> None:
- size = len(self.memory)
- self.memory = [0 for i in range(size)]
+ size = len(self._memory)
+ self._memory = [0 for i in range(size)]
def load_from_str(self, state_string) -> None:
"""
@@ -89,7 +91,7 @@ class MiaMemory(MiaBusConnector, Memory):
# Last character of the adress is a semicolon
adress = int(line_data[0][:-1], 16)
- self.memory[adress] = value
+ self._memory[adress] = value
# There is an asm instruction label
if len(line_data) == 3: