diff --git a/src/simudator/processor/mia/modules/lc.py b/src/simudator/processor/mia/modules/lc.py
index 7a936386cd2a577ab0621b3b52e102ae9111c85a..eb93d36f6be802420c6b118af4f778dc44f26949 100644
--- a/src/simudator/processor/mia/modules/lc.py
+++ b/src/simudator/processor/mia/modules/lc.py
@@ -7,8 +7,7 @@ from simudator.core.signal import Signal
class LC(Module):
- """
- A class representing the loop counter. It is controlled by the
+ """A class representing the loop counter. It is controlled by the
signal uM_control which determines if it should read from bus,
increase by one or read from mM_uADR.
"""
@@ -24,35 +23,37 @@ class LC(Module):
bit_length=8,
) -> None:
"""
- :param mM_control: A signal connection from the micro memory
+ Parameters
+ ----------
+ mM_control : Signal
+ A signal connection from the micro memory
+ bus_input : Signal
+ A signal connection from the bus to the loop
+ l_flag : Signal
+ A signal connection from the loop counter to the
+ mM_uADR : Signal
+ A signal connection from the micro memory to
+ name : str
+ Optional name of the loop counter.
+ value : int
+ Optional start value of the loop counter.
+ bit_length : int
+ Optional bit length of the loop counter.
+
+
to the loop counter. This allows the micro memory to send bit
12 and 13 to the loop counter. Bit 12 and 13 decides the
loop counters behaviour.
- :type mM_control: Signal
- :param bus_input: A signal connection from the bus to the loop
counter. The loop counter reads from this signal when it reads
from the bus.
- :type bus_input: Signal
- :param l_flag: A signal connection from the loop counter to the
L flag. The loop counter writes to this signal when it needs to
update the L flag.
- :type l_flag: Signal
- :param mM_uADR: A signal connection from the micro memory to
the loop counter. This allows the loop counter to read the 7
least significant bits from the uADR field.
- :type mM_uADR: Signal
-
- :param name: Optional name of the loop counter.
- :type name: str
- :param value: Optional start value of the loop counter.
- :type value: int
-
- :param bit_length: Optional bit length of the loop counter.
- :type bit_length: int
"""
# init the name
@@ -82,8 +83,7 @@ class LC(Module):
self.mM_uADR_s.add_destination(self)
def update_register(self) -> None:
- """
- Reads bit 12 and 13 from the micro memory and updates the
+ """Reads bit 12 and 13 from the micro memory and updates the
loop counter.
0 - does nothing.
1 - decrements the loop counter by one.
@@ -128,15 +128,13 @@ class LC(Module):
self.value = self.mask
def output_register(self) -> None:
- """
- The loop counter will only output to the L flag, this is
+ """The loop counter will only output to the L flag, this is
handled in 'update_logic'.
"""
pass
def update_logic(self) -> None:
- """
- When the loop counter reaches zero, set the l flag to 1.
+ """When the loop counter reaches zero, set the l flag to 1.
Otherwise set it to zero.
"""
if self.value == 0:
@@ -145,12 +143,13 @@ class LC(Module):
self.l_flag_s.update_value(0)
def get_state(self) -> dict[str:Any]:
- """
- Returns a dict of the loop counter state.
+ """Returns a dict of the loop counter state.
These states are changable via set_states.
- :return: The state of the loop counter.
- :rtype: dict[Any]
+ Returns
+ -------
+ dict[Any]
+ The state of the loop counter.
"""
state = dict()
state["name"] = self.name
@@ -163,9 +162,7 @@ class LC(Module):
return state
def set_state(self, state: dict[str:Any]) -> None:
- """
- Sets the loop counter state to one given in dict.
- """
+ """Sets the loop counter state to one given in dict."""
self.name = state["name"]
self.value = state["value"]
if "bit_length" in state:
@@ -180,9 +177,7 @@ class LC(Module):
self.decrement_by_one = state["decrement_by_one"]
def reset(self) -> None:
- """
- Resets the loop counter to 0.
- """
+ """Resets the loop counter to 0."""
super().reset()
self.value = 0
self.read_from_bus = False
@@ -190,9 +185,7 @@ class LC(Module):
self.decrement_by_one = False
def save_state_to_file(self, file_path: str) -> None:
- """
- Tries to save the modules state to a given file.
- """
+ """Tries to save the modules state to a given file."""
file = open(file_path, "a")
file.write(self.name + ":\n")
file.write("value: " + hex(self.value)[2:] + "\n\n")
diff --git a/src/simudator/processor/mia/modules/micro_memory.py b/src/simudator/processor/mia/modules/micro_memory.py
index 1cee0c08fd6d49b2e48daaa0b9e60c881332b9df..4ed5a26613fe3f4a611aa0fb80ad4c9ad4ff88d9 100644
--- a/src/simudator/processor/mia/modules/micro_memory.py
+++ b/src/simudator/processor/mia/modules/micro_memory.py
@@ -5,8 +5,7 @@ from simudator.core.signal import Signal
class MicroMemory(Module):
- """
- An implementation of the micro memory from the MIA lab. The micro memory
+ """An implementation of the micro memory from the MIA lab. The micro memory
has control signals for the ALU, bus transfer, the general registers GRx,
the program counter PC, the loop counter LC and the micro program counter
uPC. It also has signals for sending data to the bus, the LC and the uPC as
@@ -40,41 +39,46 @@ class MicroMemory(Module):
value_padding: int = 7,
) -> None:
"""
- :param alu: Control signal specifying the ALU operand.
- :type alu: Signal
- :param bus_control: Control signal for which modules should write to
- and read from the bus.
- :type bus_control: Signal
- :param bus_constant: Signal for sending uADR instruction field to bus.
- :type bus_constant: Signal
- :param s: Control signal for [XXXXXXXXXX]
- :type s: Signal
- :param p: Control signal for program counter PC.
- :type p: Signal
- :param lc_control: Control signal for loop counter LC.
- :type lc_control: Signal
- :param lc_uadr: Signal for sending uADR instruction field to LC.
- :type lc_uadr: Signal
- :param upc: Signal carrying the value of the micro program counter uPC.
- :type upc: Signal
- :param upc_control: Control signal for uPC.
- :type upc_control: Signal
- :param upc_uadr: Signal for sending uADR instruction field to uPC.
- :type upc_uadr: Signal
- :param z_flag: Signal carrying the value of the z-flag.
- :type z_flag: Signal
- :param n_flag: Signal carrying the value of the n-flag.
- :type n_flag: Signal
- :param c_flag: Signal carrying the value of the c-flag.
- :type c_flag: Signal
- :param o_flag: Signal carrying the value of the o-flag.
- :type o_flag: Signal
- :param l_flag: Signal carrying the value of the l-flag.
- :type l_flag: Signal
- :param name: Optional name for the module. Defaults to 'uM'.
- :type name: str
-
- :return: None
+ Parameters
+ ----------
+ alu : Signal
+ Control signal specifying the ALU operand.
+ bus_control : Signal
+ Control signal for which modules should write to and read
+ from the bus.
+ bus_constant : Signal
+ Signal for sending uADR instruction field to bus.
+ s : Signal
+ Control signal for [XXXXXXXXXX]
+ p : Signal
+ Control signal for program counter PC.
+ lc_control : Signal
+ Control signal for loop counter LC.
+ lc_uadr : Signal
+ Signal for sending uADR instruction field to LC.
+ upc : Signal
+ Signal carrying the value of the micro program counter uPC.
+ upc_control : Signal
+ Control signal for uPC.
+ upc_uadr : Signal
+ Signal for sending uADR instruction field to uPC.
+ z_flag : Signal
+ Signal carrying the value of the z-flag.
+ n_flag : Signal
+ Signal carrying the value of the n-flag.
+ c_flag : Signal
+ Signal carrying the value of the c-flag.
+ o_flag : Signal
+ Signal carrying the value of the o-flag.
+ l_flag : Signal
+ Signal carrying the value of the l-flag.
+ name : str
+ Optional name for the module. Defaults to 'uM'.
+
+ Returns
+ -------
+ unknown
+ None
"""
super().__init__(name)
@@ -123,8 +127,7 @@ class MicroMemory(Module):
self.value_padding = value_padding
def update_logic(self) -> None:
- """
- Update the micro controller with a new instruction index. The
+ """Update the micro controller with a new instruction index. The
micro controller sets control signals to other modules in accordance
with the micro instruction pointed to.
"""
@@ -238,8 +241,7 @@ class MicroMemory(Module):
self.halt = True
def _conditional_jump(self, flag, cond_value, uadr):
- """
- Helper function for executing a conditional jump to the specified uadr
+ """Helper function for executing a conditional jump to the specified uadr
if the specified flag has the specified value. If the condition is not
true then uPC is increased by 1.
"""
@@ -250,8 +252,7 @@ class MicroMemory(Module):
self.upc_control_s.update_value(0b000)
def print_module(self) -> None:
- """
- Print the contents of the micro memory. Adresses which contain the
+ """Print the contents of the micro memory. Adresses which contain the
value 0 are not printed.
"""
print("", self.name, "\n -----\n")
@@ -313,8 +314,7 @@ class MicroMemory(Module):
self.halt = False # Used for signalling a HALT
def load_from_str(self, state_string) -> None:
- """
- Load the contents of the micro memory from a string consisting of a
+ """Load the contents of the micro memory from a string consisting of a
row for every adress. Each row should be formatted as 'ADR: VALUE'.
Both the adress and the value should be written in hex notation.
Adresses which are not specified in the string will receive the value
@@ -341,9 +341,7 @@ class MicroMemory(Module):
self.memory[adress] = value
def save_state_to_file(self, file_path: str) -> None:
- """
- Tries to save the modules state to a given file.
- """
+ """Tries to save the modules state to a given file."""
file = open(file_path, "a")
file.write(self.name + ":\n")
for index, value in enumerate(self.memory):
@@ -357,15 +355,13 @@ class MicroMemory(Module):
file.close()
def get_largest_mem_adr(self) -> int:
- """
- Helper function for pretty_print that returns the length of
+ """Helper function for pretty_print that returns the length of
the largest adress in the memory to print for a module.
"""
return len(str(len(self.memory)))
def get_longest_line_len(self, ignore_keys=[]) -> int:
- """
- Helper function for pretty_print that returns the length of
+ """Helper function for pretty_print that returns the length of
the longest value in the memory to print for a module.
"""
diff --git a/src/simudator/processor/mia/modules/pc.py b/src/simudator/processor/mia/modules/pc.py
index f5fd9651c2a5419896a22b2dd3993df4a4712f74..d145c223bfa935837d1dc0f07103925d92d6f7f0 100644
--- a/src/simudator/processor/mia/modules/pc.py
+++ b/src/simudator/processor/mia/modules/pc.py
@@ -8,8 +8,7 @@ from simudator.processor.mia.modules.mia_bus_connect import MiaBusConnector
class PC(Module, MiaBusConnector):
- """
- A program counter moduled after the mia lab. The module have two
+ """A program counter moduled after the mia lab. The module have two
control signals, p and bus_control. If the p signal is true the
program counter increases its value by one, if the bus_control
is true (the id to read from bus is the pc's id) the pc takes the
@@ -47,17 +46,14 @@ class PC(Module, MiaBusConnector):
self.increase_by_one = False
def output_register(self) -> None:
- """
- Output the value of the program counter to the bus.
- """
+ """Output the value of the program counter to the bus."""
if self.write_to_bus():
self.bus_output_s.update_value(self.value)
else:
self.bus_output_s.update_value(None)
def update_register(self) -> None:
- """
- Updates the value of the PC according to the signals sent
+ """Updates the value of the PC according to the signals sent
by the micro memory. If the program counter recives
'True' from both signals it should do nothing and wait for the
next cycle.
@@ -79,12 +75,13 @@ class PC(Module, MiaBusConnector):
self.output_register()
def get_state(self) -> dict[str:Any]:
- """
- Returns a dict of the program counter state.
+ """Returns a dict of the program counter state.
These states are changable via set_states.
- :return: The state of the program counter.
- :rtype: dict[Any]
+ Returns
+ -------
+ dict[Any]
+ The state of the program counter.
"""
state = dict()
state["name"] = self.name
@@ -101,25 +98,19 @@ class PC(Module, MiaBusConnector):
return state
def set_state(self, state: dict[str:Any]) -> None:
- """
- Sets the program counter state to one given in dict.
- """
+ """Sets the program counter state to one given in dict."""
self.name = state["name"]
self.value = state["value"]
if "increment" in state:
self.increase_by_one = state["increment"]
def reset(self) -> None:
- """
- Reset the program counter to 0.
- """
+ """Reset the program counter to 0."""
self.value = 0
self.increase_by_one = False
def save_state_to_file(self, file_path: str) -> None:
- """
- Tries to save the modules state to a given file.
- """
+ """Tries to save the modules state to a given file."""
file = open(file_path, "a")
file.write(self.name + ":\n")
file.write("value: " + hex(self.value)[2:] + "\n\n")