diff --git a/src/simudator/gui/module_graphics_item/integer_memory_graphic.py b/src/simudator/gui/module_graphics_item/integer_memory_graphic.py
index c746c082c3fcc3e33d16b20949415b833cdfcf07..4902f59be8670a117cfd8665d1385ce16462e656 100644
--- a/src/simudator/gui/module_graphics_item/integer_memory_graphic.py
+++ b/src/simudator/gui/module_graphics_item/integer_memory_graphic.py
@@ -1,3 +1,5 @@
+import sys
+import traceback
from enum import Enum
from qtpy.QtWidgets import QButtonGroup, QHBoxLayout, QHeaderView, QRadioButton
@@ -40,7 +42,10 @@ class IntegerMemoryWindow(MemoryWindow):
An integer specifying the number of bits of each address.
"""
- def __init__(self, memory_module: Memory, bit_length: int):
+ def __init__(
+ self,
+ memory_module: Memory,
+ ):
# Do not let parent create edit/view buttons
super().__init__(memory_module, False)
@@ -49,11 +54,11 @@ class IntegerMemoryWindow(MemoryWindow):
self.layout.removeWidget(self._memory_table)
# Add our own
- self._memory_table = IntegerMemoryTable(memory_module, bit_length)
+ self._memory_table = IntegerMemoryTable(memory_module)
self.layout.addWidget(self._memory_table)
# Create base buttons, they are exclusive by default
- # so need a seperate QButtonGroup since these four
+ # so need a separate QButtonGroup since these four
# have nothing to do with the edit/view buttons
self.dec_signed_button = QRadioButton("Decimal Signed")
self.dec_unsigned_button = QRadioButton("Decimal Unsigned")
@@ -136,9 +141,9 @@ class IntegerMemoryTable(MemoryTable):
"""
- def __init__(self, memory_module: Memory, bit_length: int, column_size=-1):
+ def __init__(self, memory_module: Memory, column_size=-1):
self._base = Base.DECIMAL_UNSIGNED
- self._bit_length = bit_length
+ self._bit_length = memory_module.get_parameter()["bit_length"]
super().__init__(memory_module, column_size)
self.update()
diff --git a/src/simudator/processor/mia/gui/mia_memory_graphic.py b/src/simudator/processor/mia/gui/mia_memory_graphic.py
index 21d61b027d8bc3386cf0ff66eb3809969b47ce0d..a65eb30bbf6fdb55b69b5be989c8dd738c62f65f 100644
--- a/src/simudator/processor/mia/gui/mia_memory_graphic.py
+++ b/src/simudator/processor/mia/gui/mia_memory_graphic.py
@@ -68,8 +68,7 @@ class MiaMemoryGraphicsItem(MemoryGraphicsItem):
Create and show a MemoryWindow that displays the contents
of the memory module associated with this graphics item.
"""
- bit_length = 16
- self.memory_window = IntegerMemoryWindow(self.module, bit_length)
+ self.memory_window = IntegerMemoryWindow(self.module)
self.memory_window.show()
def memoryBreakpointDialog(self) -> None:
diff --git a/src/simudator/processor/mia/mia.py b/src/simudator/processor/mia/mia.py
index 6d2544196c98a25ff3b09281f7e120d95f3e473d..5fbd52a3ec7c0ba8339f2d338868427a9f420956 100644
--- a/src/simudator/processor/mia/mia.py
+++ b/src/simudator/processor/mia/mia.py
@@ -155,6 +155,7 @@ class MIA_CPU(Processor):
pm_size,
pm_bus_id,
name="PM",
+ bit_length=16,
)
# GRX specific
@@ -173,6 +174,7 @@ class MIA_CPU(Processor):
k1_size,
always_write_id,
name="K1",
+ bit_length=7,
)
# K2 specific
@@ -185,6 +187,7 @@ class MIA_CPU(Processor):
k2_size,
always_write_id,
name="K2",
+ bit_length=7,
)
# IR specific
diff --git a/src/simudator/processor/mia/modules/mia_memory.py b/src/simudator/processor/mia/modules/mia_memory.py
index 4b2ca42c137f718c4260e5ab9064f2a5a8b2d573..2def97845d5bcd15502825501504e182b316f4aa 100644
--- a/src/simudator/processor/mia/modules/mia_memory.py
+++ b/src/simudator/processor/mia/modules/mia_memory.py
@@ -1,3 +1,5 @@
+from typing import Any
+
from simudator.core.modules.memory import Memory
from simudator.core.signal import Signal
from simudator.processor.mia.modules.mia_bus_connect import MiaBusConnector
@@ -7,14 +9,14 @@ class MiaMemory(MiaBusConnector, Memory):
"""
A MIA specific memory, functionality from the general memory
and the MiaBusConnector is inherited. The module can be of
- arbitrary size and supports opperations that read and write
+ arbitrary size and supports operations that read and write
to/from the mia bus.
"""
# Python does not allow multiple inherintence if more than one of the
# parent classes uses __slots__. Thus we also includes the __slots__
# from MiaBusConnector.
- __slots__ = ("label_adress_mapping", "bus_id", "bus_control_s")
+ __slots__ = ("label_address_mapping", "bus_id", "bus_control_s", "_bit_length")
def __init__(
self,
@@ -25,6 +27,7 @@ class MiaMemory(MiaBusConnector, Memory):
size: int = 1,
bus_id: int = 0,
name: str = "PM",
+ bit_length: int = 16,
) -> None:
MiaBusConnector.__init__(self, bus_control_s, bus_id)
Memory.__init__(
@@ -38,7 +41,8 @@ class MiaMemory(MiaBusConnector, Memory):
)
self.bus_control_s.add_destination(self)
- self.label_adress_mapping = {}
+ self.label_address_mapping = {}
+ self._bit_length = bit_length
def update_register(self) -> None:
"""
@@ -77,6 +81,11 @@ class MiaMemory(MiaBusConnector, Memory):
size = len(self._memory)
self._memory = [0 for _ in range(size)]
+ def get_parameter(self) -> dict[str, Any]:
+ parameter = super().get_parameter()
+ parameter["bit_length"] = self._bit_length
+ return parameter
+
def load_from_str(self, state_string) -> None:
"""
Loads the module from a string, used when loading state from
@@ -90,20 +99,20 @@ class MiaMemory(MiaBusConnector, Memory):
line_data = line.split()
value = int(line_data[1], 16)
- # Last character of the adress is a semicolon
- adress = int(line_data[0][:-1], 16)
+ # Last character of the address is a semicolon
+ address = int(line_data[0][:-1], 16)
- self._memory[adress] = value
+ self._memory[address] = value
# There is an asm instruction label
if len(line_data) == 3:
instr = line_data[2]
- self.label_adress_mapping[adress] = instr
+ self.label_address_mapping[address] = instr
- def get_label(self, adress: int) -> str:
+ def get_label(self, address: int) -> str:
"""Return the label at the given memory address if it exists, else an empty string"""
- if adress in self.label_adress_mapping.keys():
- return self.label_adress_mapping[adress]
+ if address in self.label_address_mapping.keys():
+ return self.label_address_mapping[address]
return ""
diff --git a/src/simudator/processor/mia/modules/micro_memory.py b/src/simudator/processor/mia/modules/micro_memory.py
index 4109d9b7f2d021f745e0c49524e639a1c2fb92c5..5ff0fb694e752f8f8f68bcf990b439a4f7462b54 100644
--- a/src/simudator/processor/mia/modules/micro_memory.py
+++ b/src/simudator/processor/mia/modules/micro_memory.py
@@ -288,6 +288,16 @@ class MicroMemory(Module):
state["memory"] = self._memory[:]
return state
+ def get_parameter(self) -> dict:
+ parameter = super().get_parameter()
+
+ # Bit length is not used internally within this module.
+ # The only way the micro memory memory can receive input
+ # is from the user, and the user is not able to insert values that
+ # are larger than 25 bits
+ parameter["bit_length"] = 25
+ return parameter
+
def set_state(self, state: dict) -> None:
super().set_state(state)
self._memory = state["memory"]
@@ -307,7 +317,7 @@ class MicroMemory(Module):
self._c_flag_val = 0
self._o_flag_val = 0
self._l_flag_val = 0
- self._memory = [0 for i in range(128)]
+ self._memory = [0 for _ in range(128)]
self._halt = False # Used for signalling a HALT
def load_from_str(self, state_string) -> None: