From 3250326e3f448a24fa56bad1342a6314213088ce Mon Sep 17 00:00:00 2001
From: Johannes Kung <johku144@student.liu.se>
Date: Mon, 17 Jun 2024 10:03:19 +0200
Subject: [PATCH] Minor documentation refactoring to core modules
---
src/simudator/core/module.py | 10 +++++-----
src/simudator/core/modules/demux.py | 2 +-
src/simudator/core/modules/memory.py | 15 +++++++++------
3 files changed, 15 insertions(+), 12 deletions(-)
diff --git a/src/simudator/core/module.py b/src/simudator/core/module.py
index 1c495ee..9b305e5 100644
--- a/src/simudator/core/module.py
+++ b/src/simudator/core/module.py
@@ -13,8 +13,8 @@ class Module:
----------
signals : dict[str, Signal]
Dictionary containing all signals connected to the module. Input
- signals should have keys beginning with `"in_"` and output signals keys
- beginning with "out_".
+ signals should have keys beginning with 'in\_' and output signals keys
+ beginning with 'out\_'.
name : str
Name of the module.
@@ -25,7 +25,7 @@ class Module:
signals : dict[str, Signal]
The signals connected to this module. The key for a signal can be
regarded as the name of a signal 'port' of the module. The keys should
- be prefixed with 'in_' for input signals and 'out_' for output signals.
+ be prefixed with 'in\_' for input signals and 'out\_' for output signals.
"""
def __init__(self, signals: dict[str, Signal], name: str = "") -> None:
@@ -101,7 +101,7 @@ class Module:
def get_output_signals(self) -> list[Signal]:
"""Return the output signals of the module.
- Assumes all output signals are stored with a key beginning in 'out' in
+ Assumes all output signals are stored with a key beginning in 'out\_' in
the signals dictionary.
Returns
@@ -114,7 +114,7 @@ class Module:
def get_input_signals(self) -> list[Signal]:
"""Return the input signals of the module.
- Assumes all input signals are stored with a key beginning in 'in' in
+ Assumes all input signals are stored with a key beginning in 'in\_' in
the signals dictionary.
Returns
diff --git a/src/simudator/core/modules/demux.py b/src/simudator/core/modules/demux.py
index 3ab7d0e..269138a 100644
--- a/src/simudator/core/modules/demux.py
+++ b/src/simudator/core/modules/demux.py
@@ -19,7 +19,7 @@ class Demux(Module):
bit_length : int
Maximum number of bits for the value outputted by the demux. All extra
bits of the input value are discarded.
- input : Signals
+ input : Signal
Input signal of which the value is forwarded to the currently
selected output signal.
outputs : list[Signal]
diff --git a/src/simudator/core/modules/memory.py b/src/simudator/core/modules/memory.py
index c8c0a77..d5f42d0 100644
--- a/src/simudator/core/modules/memory.py
+++ b/src/simudator/core/modules/memory.py
@@ -5,10 +5,6 @@ from typing import Any
from simudator.core.module import Module
from simudator.core.signal import Signal
-# Used to pad the values of the memory when saving to file
-MEMORY_VALUE_PADDING = 2
-MEMORY_ADDRESS_PADDING = 2
-
class Memory(Module):
"""
@@ -31,6 +27,13 @@ class Memory(Module):
Name of the module.
"""
+ """
+ Constants used to textually pad the values of the memory when saving to
+ file.
+ """
+ MEMORY_VALUE_PADDING = 2
+ MEMORY_ADDRESS_PADDING = 2
+
def __init__(
self,
input: Signal,
@@ -133,9 +136,9 @@ class Memory(Module):
file.write(self.name + ":\n")
for index, value in enumerate(self._memory):
# Write the address in hex and add ': ' to the end
- file.write(hex(index)[2:].rjust(MEMORY_ADDRESS_PADDING, "0") + ": ")
+ file.write(hex(index)[2:].rjust(Memory.MEMORY_ADDRESS_PADDING, "0") + ": ")
# Write the value in hex
- file.write(hex(value)[2:].rjust(MEMORY_VALUE_PADDING, "0"))
+ file.write(hex(value)[2:].rjust(Memory.MEMORY_VALUE_PADDING, "0"))
file.write("\n")
file.write("\n")
--
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